1 /*-
2 * Copyright (c) 2015 Alexander Kabaev <kan@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 #include <sys/param.h>
29 #include <sys/systm.h>
30 #include <sys/bus.h>
31 #include <sys/kernel.h>
32 #include <sys/lock.h>
33 #include <sys/malloc.h>
34 #include <sys/module.h>
35 #include <sys/mutex.h>
36 #include <sys/resource.h>
37 #include <sys/rman.h>
38 #include <sys/sysctl.h>
39
40 #include <machine/bus.h>
41
42 #include <dev/extres/clk/clk.h>
43
44 #include <dev/ofw/ofw_bus.h>
45 #include <dev/ofw/ofw_bus_subr.h>
46
47 #include <dev/mmc/bridge.h>
48 #include <dev/mmc/mmcreg.h>
49 #include <dev/mmc/mmcbrvar.h>
50
51 #include <mips/ingenic/jz4780_regs.h>
52
53 #undef JZ_MMC_DEBUG
54
55 #define JZ_MSC_MEMRES 0
56 #define JZ_MSC_IRQRES 1
57 #define JZ_MSC_RESSZ 2
58 #define JZ_MSC_DMA_SEGS 128
59 #define JZ_MSC_DMA_MAX_SIZE maxphys
60
61 #define JZ_MSC_INT_ERR_BITS (JZ_INT_CRC_RES_ERR | JZ_INT_CRC_READ_ERR | \
62 JZ_INT_CRC_WRITE_ERR | JZ_INT_TIMEOUT_RES | \
63 JZ_INT_TIMEOUT_READ)
64 static int jz4780_mmc_pio_mode = 0;
65
66 TUNABLE_INT("hw.jz.mmc.pio_mode", &jz4780_mmc_pio_mode);
67
68 struct jz4780_mmc_dma_desc {
69 uint32_t dma_next;
70 uint32_t dma_phys;
71 uint32_t dma_len;
72 uint32_t dma_cmd;
73 };
74
75 struct jz4780_mmc_softc {
76 bus_space_handle_t sc_bsh;
77 bus_space_tag_t sc_bst;
78 device_t sc_dev;
79 clk_t sc_clk;
80 int sc_bus_busy;
81 int sc_resid;
82 int sc_timeout;
83 struct callout sc_timeoutc;
84 struct mmc_host sc_host;
85 struct mmc_request * sc_req;
86 struct mtx sc_mtx;
87 struct resource * sc_res[JZ_MSC_RESSZ];
88 uint32_t sc_intr_seen;
89 uint32_t sc_intr_mask;
90 uint32_t sc_intr_wait;
91 void * sc_intrhand;
92 uint32_t sc_cmdat;
93
94 /* Fields required for DMA access. */
95 bus_addr_t sc_dma_desc_phys;
96 bus_dmamap_t sc_dma_map;
97 bus_dma_tag_t sc_dma_tag;
98 void * sc_dma_desc;
99 bus_dmamap_t sc_dma_buf_map;
100 bus_dma_tag_t sc_dma_buf_tag;
101 int sc_dma_inuse;
102 int sc_dma_map_err;
103 uint32_t sc_dma_ctl;
104 };
105
106 static struct resource_spec jz4780_mmc_res_spec[] = {
107 { SYS_RES_MEMORY, 0, RF_ACTIVE },
108 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
109 { -1, 0, 0 }
110 };
111
112 static int jz4780_mmc_probe(device_t);
113 static int jz4780_mmc_attach(device_t);
114 static int jz4780_mmc_detach(device_t);
115 static int jz4780_mmc_setup_dma(struct jz4780_mmc_softc *);
116 static int jz4780_mmc_reset(struct jz4780_mmc_softc *);
117 static void jz4780_mmc_intr(void *);
118 static int jz4780_mmc_enable_clock(struct jz4780_mmc_softc *);
119 static int jz4780_mmc_config_clock(struct jz4780_mmc_softc *, uint32_t);
120
121 static int jz4780_mmc_update_ios(device_t, device_t);
122 static int jz4780_mmc_request(device_t, device_t, struct mmc_request *);
123 static int jz4780_mmc_get_ro(device_t, device_t);
124 static int jz4780_mmc_acquire_host(device_t, device_t);
125 static int jz4780_mmc_release_host(device_t, device_t);
126
127 #define JZ_MMC_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
128 #define JZ_MMC_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
129 #define JZ_MMC_READ_2(_sc, _reg) \
130 bus_space_read_2((_sc)->sc_bst, (_sc)->sc_bsh, _reg)
131 #define JZ_MMC_WRITE_2(_sc, _reg, _value) \
132 bus_space_write_2((_sc)->sc_bst, (_sc)->sc_bsh, _reg, _value)
133 #define JZ_MMC_READ_4(_sc, _reg) \
134 bus_space_read_4((_sc)->sc_bst, (_sc)->sc_bsh, _reg)
135 #define JZ_MMC_WRITE_4(_sc, _reg, _value) \
136 bus_space_write_4((_sc)->sc_bst, (_sc)->sc_bsh, _reg, _value)
137
138 static int
jz4780_mmc_probe(device_t dev)139 jz4780_mmc_probe(device_t dev)
140 {
141
142 if (!ofw_bus_status_okay(dev))
143 return (ENXIO);
144 if (!ofw_bus_is_compatible(dev, "ingenic,jz4780-mmc"))
145 return (ENXIO);
146 if (device_get_unit(dev) > 0) /* XXXKAN */
147 return (ENXIO);
148 device_set_desc(dev, "Ingenic JZ4780 Integrated MMC/SD controller");
149
150 return (BUS_PROBE_DEFAULT);
151 }
152
153 static int
jz4780_mmc_attach(device_t dev)154 jz4780_mmc_attach(device_t dev)
155 {
156 struct jz4780_mmc_softc *sc;
157 struct sysctl_ctx_list *ctx;
158 struct sysctl_oid_list *tree;
159 device_t child;
160 ssize_t len;
161 pcell_t prop;
162 phandle_t node;
163
164 sc = device_get_softc(dev);
165 sc->sc_dev = dev;
166 sc->sc_req = NULL;
167 if (bus_alloc_resources(dev, jz4780_mmc_res_spec, sc->sc_res) != 0) {
168 device_printf(dev, "cannot allocate device resources\n");
169 return (ENXIO);
170 }
171 sc->sc_bst = rman_get_bustag(sc->sc_res[JZ_MSC_MEMRES]);
172 sc->sc_bsh = rman_get_bushandle(sc->sc_res[JZ_MSC_MEMRES]);
173 if (bus_setup_intr(dev, sc->sc_res[JZ_MSC_IRQRES],
174 INTR_TYPE_MISC | INTR_MPSAFE, NULL, jz4780_mmc_intr, sc,
175 &sc->sc_intrhand)) {
176 bus_release_resources(dev, jz4780_mmc_res_spec, sc->sc_res);
177 device_printf(dev, "cannot setup interrupt handler\n");
178 return (ENXIO);
179 }
180 sc->sc_timeout = 10;
181 ctx = device_get_sysctl_ctx(dev);
182 tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
183 SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "req_timeout", CTLFLAG_RW,
184 &sc->sc_timeout, 0, "Request timeout in seconds");
185 mtx_init(&sc->sc_mtx, device_get_nameunit(sc->sc_dev), "jz4780_mmc",
186 MTX_DEF);
187 callout_init_mtx(&sc->sc_timeoutc, &sc->sc_mtx, 0);
188
189 /* Reset controller. */
190 if (jz4780_mmc_reset(sc) != 0) {
191 device_printf(dev, "cannot reset the controller\n");
192 goto fail;
193 }
194 if (jz4780_mmc_pio_mode == 0 && jz4780_mmc_setup_dma(sc) != 0) {
195 device_printf(sc->sc_dev, "Couldn't setup DMA!\n");
196 jz4780_mmc_pio_mode = 1;
197 }
198 if (bootverbose)
199 device_printf(sc->sc_dev, "DMA status: %s\n",
200 jz4780_mmc_pio_mode ? "disabled" : "enabled");
201
202 node = ofw_bus_get_node(dev);
203 /* Determine max operating frequency */
204 sc->sc_host.f_max = 24000000;
205 len = OF_getencprop(node, "max-frequency", &prop, sizeof(prop));
206 if (len / sizeof(prop) == 1)
207 sc->sc_host.f_max = prop;
208 sc->sc_host.f_min = sc->sc_host.f_max / 128;
209
210 sc->sc_host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340;
211 sc->sc_host.caps = MMC_CAP_HSPEED;
212 sc->sc_host.mode = mode_sd;
213 /*
214 * Check for bus-width property, default to both 4 and 8 bit
215 * if no bus width is specified.
216 */
217 len = OF_getencprop(node, "bus-width", &prop, sizeof(prop));
218 if (len / sizeof(prop) != 1)
219 sc->sc_host.caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA;
220 else if (prop == 8)
221 sc->sc_host.caps |= MMC_CAP_8_BIT_DATA;
222 else if (prop == 4)
223 sc->sc_host.caps |= MMC_CAP_4_BIT_DATA;
224 /* Activate the module clock. */
225 if (jz4780_mmc_enable_clock(sc) != 0) {
226 device_printf(dev, "cannot activate mmc clock\n");
227 goto fail;
228 }
229
230 child = device_add_child(dev, "mmc", -1);
231 if (child == NULL) {
232 device_printf(dev, "attaching MMC bus failed!\n");
233 goto fail;
234 }
235 if (device_probe_and_attach(child) != 0) {
236 device_printf(dev, "attaching MMC child failed!\n");
237 device_delete_child(dev, child);
238 goto fail;
239 }
240
241 return (0);
242
243 fail:
244 callout_drain(&sc->sc_timeoutc);
245 mtx_destroy(&sc->sc_mtx);
246 bus_teardown_intr(dev, sc->sc_res[JZ_MSC_IRQRES], sc->sc_intrhand);
247 bus_release_resources(dev, jz4780_mmc_res_spec, sc->sc_res);
248 if (sc->sc_clk != NULL)
249 clk_release(sc->sc_clk);
250 return (ENXIO);
251 }
252
253 static int
jz4780_mmc_detach(device_t dev)254 jz4780_mmc_detach(device_t dev)
255 {
256
257 return (EBUSY);
258 }
259
260 static int
jz4780_mmc_enable_clock(struct jz4780_mmc_softc * sc)261 jz4780_mmc_enable_clock(struct jz4780_mmc_softc *sc)
262 {
263 int err;
264
265 err = clk_get_by_ofw_name(sc->sc_dev, 0, "mmc", &sc->sc_clk);
266 if (err == 0)
267 err = clk_enable(sc->sc_clk);
268 if (err == 0)
269 err = clk_set_freq(sc->sc_clk, sc->sc_host.f_max, 0);
270 if (err != 0)
271 clk_release(sc->sc_clk);
272 return (err);
273 }
274
275 static void
jz4780_mmc_dma_desc_cb(void * arg,bus_dma_segment_t * segs,int nsegs,int err)276 jz4780_mmc_dma_desc_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err)
277 {
278 struct jz4780_mmc_softc *sc;
279
280 sc = (struct jz4780_mmc_softc *)arg;
281 if (err) {
282 sc->sc_dma_map_err = err;
283 return;
284 }
285 sc->sc_dma_desc_phys = segs[0].ds_addr;
286 }
287
288 static int
jz4780_mmc_setup_dma(struct jz4780_mmc_softc * sc)289 jz4780_mmc_setup_dma(struct jz4780_mmc_softc *sc)
290 {
291 int dma_desc_size, error;
292
293 /* Allocate the DMA descriptor memory. */
294 dma_desc_size = sizeof(struct jz4780_mmc_dma_desc) * JZ_MSC_DMA_SEGS;
295 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
296 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
297 dma_desc_size, 1, dma_desc_size, 0, NULL, NULL, &sc->sc_dma_tag);
298 if (error)
299 return (error);
300 error = bus_dmamem_alloc(sc->sc_dma_tag, &sc->sc_dma_desc,
301 BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->sc_dma_map);
302 if (error)
303 return (error);
304
305 error = bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map,
306 sc->sc_dma_desc, dma_desc_size, jz4780_mmc_dma_desc_cb, sc, 0);
307 if (error)
308 return (error);
309 if (sc->sc_dma_map_err)
310 return (sc->sc_dma_map_err);
311
312 /* Create the DMA map for data transfers. */
313 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
314 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
315 JZ_MSC_DMA_MAX_SIZE * JZ_MSC_DMA_SEGS, JZ_MSC_DMA_SEGS,
316 JZ_MSC_DMA_MAX_SIZE, BUS_DMA_ALLOCNOW, NULL, NULL,
317 &sc->sc_dma_buf_tag);
318 if (error)
319 return (error);
320 error = bus_dmamap_create(sc->sc_dma_buf_tag, 0,
321 &sc->sc_dma_buf_map);
322 if (error)
323 return (error);
324
325 return (0);
326 }
327
328 static void
jz4780_mmc_dma_cb(void * arg,bus_dma_segment_t * segs,int nsegs,int err)329 jz4780_mmc_dma_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err)
330 {
331 struct jz4780_mmc_dma_desc *dma_desc;
332 struct jz4780_mmc_softc *sc;
333 uint32_t dma_desc_phys;
334 int i;
335
336 sc = (struct jz4780_mmc_softc *)arg;
337 sc->sc_dma_map_err = err;
338 dma_desc = sc->sc_dma_desc;
339 dma_desc_phys = sc->sc_dma_desc_phys;
340
341 /* Note nsegs is guaranteed to be zero if err is non-zero. */
342 for (i = 0; i < nsegs; i++) {
343 dma_desc[i].dma_phys = segs[i].ds_addr;
344 dma_desc[i].dma_len = segs[i].ds_len;
345 if (i < (nsegs - 1)) {
346 dma_desc_phys += sizeof(struct jz4780_mmc_dma_desc);
347 dma_desc[i].dma_next = dma_desc_phys;
348 dma_desc[i].dma_cmd = (i << 16) | JZ_DMA_LINK;
349 } else {
350 dma_desc[i].dma_next = 0;
351 dma_desc[i].dma_cmd = (i << 16) | JZ_DMA_ENDI;
352 }
353 #ifdef JZ_MMC_DEBUG
354 device_printf(sc->sc_dev, "%d: desc %#x phys %#x len %d next %#x cmd %#x\n",
355 i, dma_desc_phys - sizeof(struct jz4780_mmc_dma_desc),
356 dma_desc[i].dma_phys, dma_desc[i].dma_len,
357 dma_desc[i].dma_next, dma_desc[i].dma_cmd);
358 #endif
359 }
360 }
361
362 static int
jz4780_mmc_prepare_dma(struct jz4780_mmc_softc * sc)363 jz4780_mmc_prepare_dma(struct jz4780_mmc_softc *sc)
364 {
365 bus_dmasync_op_t sync_op;
366 int error;
367 struct mmc_command *cmd;
368 uint32_t off;
369
370 cmd = sc->sc_req->cmd;
371 if (cmd->data->len > JZ_MSC_DMA_MAX_SIZE * JZ_MSC_DMA_SEGS)
372 return (EFBIG);
373 error = bus_dmamap_load(sc->sc_dma_buf_tag, sc->sc_dma_buf_map,
374 cmd->data->data, cmd->data->len, jz4780_mmc_dma_cb, sc,
375 BUS_DMA_NOWAIT);
376 if (error)
377 return (error);
378 if (sc->sc_dma_map_err)
379 return (sc->sc_dma_map_err);
380
381 sc->sc_dma_inuse = 1;
382 if (cmd->data->flags & MMC_DATA_WRITE)
383 sync_op = BUS_DMASYNC_PREWRITE;
384 else
385 sync_op = BUS_DMASYNC_PREREAD;
386 bus_dmamap_sync(sc->sc_dma_buf_tag, sc->sc_dma_buf_map, sync_op);
387 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, BUS_DMASYNC_PREWRITE);
388
389 /* Configure default DMA parameters */
390 sc->sc_dma_ctl = JZ_MODE_SEL | JZ_INCR_64 | JZ_DMAEN;
391
392 /* Enable unaligned buffer handling */
393 off = (uintptr_t)cmd->data->data & 3;
394 if (off != 0)
395 sc->sc_dma_ctl |= (off << JZ_AOFST_S) | JZ_ALIGNEN;
396 return (0);
397 }
398
399 static void
jz4780_mmc_start_dma(struct jz4780_mmc_softc * sc)400 jz4780_mmc_start_dma(struct jz4780_mmc_softc *sc)
401 {
402
403 /* Set the address of the first descriptor */
404 JZ_MMC_WRITE_4(sc, JZ_MSC_DMANDA, sc->sc_dma_desc_phys);
405 /* Enable and start the dma engine */
406 JZ_MMC_WRITE_4(sc, JZ_MSC_DMAC, sc->sc_dma_ctl);
407 }
408
409 static int
jz4780_mmc_reset(struct jz4780_mmc_softc * sc)410 jz4780_mmc_reset(struct jz4780_mmc_softc *sc)
411 {
412 int timeout;
413
414 /* Stop the clock */
415 JZ_MMC_WRITE_4(sc, JZ_MSC_CTRL, JZ_CLOCK_STOP);
416
417 timeout = 1000;
418 while (--timeout > 0) {
419 if ((JZ_MMC_READ_4(sc, JZ_MSC_STAT) & JZ_CLK_EN) == 0)
420 break;
421 DELAY(100);
422 }
423 if (timeout == 0) {
424 device_printf(sc->sc_dev, "Failed to stop clk.\n");
425 return (ETIMEDOUT);
426 }
427
428 /* Reset */
429 JZ_MMC_WRITE_4(sc, JZ_MSC_CTRL, JZ_RESET);
430
431 timeout = 10;
432 while (--timeout > 0) {
433 if ((JZ_MMC_READ_4(sc, JZ_MSC_STAT) & JZ_IS_RESETTING) == 0)
434 break;
435 DELAY(1000);
436 }
437
438 if (timeout == 0) {
439 /*
440 * X1000 never clears reseting bit.
441 * Ignore for now.
442 */
443 }
444
445 /* Set the timeouts. */
446 JZ_MMC_WRITE_4(sc, JZ_MSC_RESTO, 0xffff);
447 JZ_MMC_WRITE_4(sc, JZ_MSC_RDTO, 0xffffffff);
448
449 /* Mask all interrupt initially */
450 JZ_MMC_WRITE_4(sc, JZ_MSC_IMASK, 0xffffffff);
451 /* Clear pending interrupts. */
452 JZ_MMC_WRITE_4(sc, JZ_MSC_IFLG, 0xffffffff);
453
454 /* Remember interrupts we always want */
455 sc->sc_intr_mask = JZ_MSC_INT_ERR_BITS;
456
457 return (0);
458 }
459
460 static void
jz4780_mmc_req_done(struct jz4780_mmc_softc * sc)461 jz4780_mmc_req_done(struct jz4780_mmc_softc *sc)
462 {
463 struct mmc_command *cmd;
464 struct mmc_request *req;
465 bus_dmasync_op_t sync_op;
466
467 cmd = sc->sc_req->cmd;
468 /* Reset the controller in case of errors */
469 if (cmd->error != MMC_ERR_NONE)
470 jz4780_mmc_reset(sc);
471 /* Unmap DMA if necessary */
472 if (sc->sc_dma_inuse == 1) {
473 if (cmd->data->flags & MMC_DATA_WRITE)
474 sync_op = BUS_DMASYNC_POSTWRITE;
475 else
476 sync_op = BUS_DMASYNC_POSTREAD;
477 bus_dmamap_sync(sc->sc_dma_buf_tag, sc->sc_dma_buf_map,
478 sync_op);
479 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map,
480 BUS_DMASYNC_POSTWRITE);
481 bus_dmamap_unload(sc->sc_dma_buf_tag, sc->sc_dma_buf_map);
482 }
483 req = sc->sc_req;
484 callout_stop(&sc->sc_timeoutc);
485 sc->sc_req = NULL;
486 sc->sc_resid = 0;
487 sc->sc_dma_inuse = 0;
488 sc->sc_dma_map_err = 0;
489 sc->sc_intr_wait = 0;
490 sc->sc_intr_seen = 0;
491 req->done(req);
492 }
493
494 static void
jz4780_mmc_read_response(struct jz4780_mmc_softc * sc)495 jz4780_mmc_read_response(struct jz4780_mmc_softc *sc)
496 {
497 struct mmc_command *cmd;
498 int i;
499
500 cmd = sc->sc_req->cmd;
501 if (cmd->flags & MMC_RSP_PRESENT) {
502 if (cmd->flags & MMC_RSP_136) {
503 uint16_t val;
504
505 val = JZ_MMC_READ_2(sc, JZ_MSC_RES);
506 for (i = 0; i < 4; i++) {
507 cmd->resp[i] = val << 24;
508 val = JZ_MMC_READ_2(sc, JZ_MSC_RES);
509 cmd->resp[i] |= val << 8;
510 val = JZ_MMC_READ_2(sc, JZ_MSC_RES);
511 cmd->resp[i] |= val >> 8;
512 }
513 } else {
514 cmd->resp[0] = JZ_MMC_READ_2(sc, JZ_MSC_RES) << 24;
515 cmd->resp[0] |= JZ_MMC_READ_2(sc, JZ_MSC_RES) << 8;
516 cmd->resp[0] |= JZ_MMC_READ_2(sc, JZ_MSC_RES) & 0xff;
517 }
518 }
519 }
520
521 static void
jz4780_mmc_req_ok(struct jz4780_mmc_softc * sc)522 jz4780_mmc_req_ok(struct jz4780_mmc_softc *sc)
523 {
524 struct mmc_command *cmd;
525
526 cmd = sc->sc_req->cmd;
527 /* All data has been transferred ? */
528 if (cmd->data != NULL && (sc->sc_resid << 2) < cmd->data->len)
529 cmd->error = MMC_ERR_FAILED;
530 jz4780_mmc_req_done(sc);
531 }
532
533 static void
jz4780_mmc_timeout(void * arg)534 jz4780_mmc_timeout(void *arg)
535 {
536 struct jz4780_mmc_softc *sc;
537
538 sc = (struct jz4780_mmc_softc *)arg;
539 if (sc->sc_req != NULL) {
540 device_printf(sc->sc_dev, "controller timeout, rint %#x stat %#x\n",
541 JZ_MMC_READ_4(sc, JZ_MSC_IFLG), JZ_MMC_READ_4(sc, JZ_MSC_STAT));
542 sc->sc_req->cmd->error = MMC_ERR_TIMEOUT;
543 jz4780_mmc_req_done(sc);
544 } else
545 device_printf(sc->sc_dev,
546 "Spurious timeout - no active request\n");
547 }
548
549 static int
jz4780_mmc_pio_transfer(struct jz4780_mmc_softc * sc,struct mmc_data * data)550 jz4780_mmc_pio_transfer(struct jz4780_mmc_softc *sc, struct mmc_data *data)
551 {
552 uint32_t mask, *buf;
553 int i, write;
554
555 buf = (uint32_t *)data->data;
556 write = (data->flags & MMC_DATA_WRITE) ? 1 : 0;
557 mask = write ? JZ_DATA_FIFO_FULL : JZ_DATA_FIFO_EMPTY;
558 for (i = sc->sc_resid; i < (data->len >> 2); i++) {
559 if ((JZ_MMC_READ_4(sc, JZ_MSC_STAT) & mask))
560 return (1);
561 if (write)
562 JZ_MMC_WRITE_4(sc, JZ_MSC_TXFIFO, buf[i]);
563 else
564 buf[i] = JZ_MMC_READ_4(sc, JZ_MSC_RXFIFO);
565 sc->sc_resid = i + 1;
566 }
567
568 /* Done with pio transfer, shut FIFO interrupts down */
569 mask = JZ_MMC_READ_4(sc, JZ_MSC_IMASK);
570 mask |= (JZ_INT_TXFIFO_WR_REQ | JZ_INT_RXFIFO_RD_REQ);
571 JZ_MMC_WRITE_4(sc, JZ_MSC_IMASK, mask);
572 return (0);
573 }
574
575 static void
jz4780_mmc_intr(void * arg)576 jz4780_mmc_intr(void *arg)
577 {
578 struct jz4780_mmc_softc *sc;
579 struct mmc_data *data;
580 uint32_t rint;
581
582 sc = (struct jz4780_mmc_softc *)arg;
583 JZ_MMC_LOCK(sc);
584 rint = JZ_MMC_READ_4(sc, JZ_MSC_IFLG);
585 #if defined(JZ_MMC_DEBUG)
586 device_printf(sc->sc_dev, "rint: %#x, stat: %#x\n",
587 rint, JZ_MMC_READ_4(sc, JZ_MSC_STAT));
588 if (sc->sc_dma_inuse == 1 && (sc->sc_intr_seen & JZ_INT_DMAEND) == 0)
589 device_printf(sc->sc_dev, "\tdmada %#x dmanext %#x dmac %#x"
590 " dmalen %d dmacmd %#x\n",
591 JZ_MMC_READ_4(sc, JZ_MSC_DMADA),
592 JZ_MMC_READ_4(sc, JZ_MSC_DMANDA),
593 JZ_MMC_READ_4(sc, JZ_MSC_DMAC),
594 JZ_MMC_READ_4(sc, JZ_MSC_DMALEN),
595 JZ_MMC_READ_4(sc, JZ_MSC_DMACMD));
596 #endif
597 if (sc->sc_req == NULL) {
598 device_printf(sc->sc_dev,
599 "Spurious interrupt - no active request, rint: 0x%08X\n",
600 rint);
601 goto end;
602 }
603 if (rint & JZ_MSC_INT_ERR_BITS) {
604 #if defined(JZ_MMC_DEBUG)
605 device_printf(sc->sc_dev, "controller error, rint %#x stat %#x\n",
606 rint, JZ_MMC_READ_4(sc, JZ_MSC_STAT));
607 #endif
608 if (rint & (JZ_INT_TIMEOUT_RES | JZ_INT_TIMEOUT_READ))
609 sc->sc_req->cmd->error = MMC_ERR_TIMEOUT;
610 else
611 sc->sc_req->cmd->error = MMC_ERR_FAILED;
612 jz4780_mmc_req_done(sc);
613 goto end;
614 }
615 data = sc->sc_req->cmd->data;
616 /* Check for command response */
617 if (rint & JZ_INT_END_CMD_RES) {
618 jz4780_mmc_read_response(sc);
619 if (sc->sc_dma_inuse == 1)
620 jz4780_mmc_start_dma(sc);
621 }
622 if (data != NULL) {
623 if (sc->sc_dma_inuse == 1 && (rint & JZ_INT_DMAEND))
624 sc->sc_resid = data->len >> 2;
625 else if (sc->sc_dma_inuse == 0 &&
626 (rint & (JZ_INT_TXFIFO_WR_REQ | JZ_INT_RXFIFO_RD_REQ)))
627 jz4780_mmc_pio_transfer(sc, data);
628 }
629 sc->sc_intr_seen |= rint;
630 if ((sc->sc_intr_seen & sc->sc_intr_wait) == sc->sc_intr_wait)
631 jz4780_mmc_req_ok(sc);
632 end:
633 JZ_MMC_WRITE_4(sc, JZ_MSC_IFLG, rint);
634 JZ_MMC_UNLOCK(sc);
635 }
636
637 static int
jz4780_mmc_request(device_t bus,device_t child,struct mmc_request * req)638 jz4780_mmc_request(device_t bus, device_t child, struct mmc_request *req)
639 {
640 struct jz4780_mmc_softc *sc;
641 struct mmc_command *cmd;
642 uint32_t cmdat, iwait;
643 int blksz;
644
645 sc = device_get_softc(bus);
646 JZ_MMC_LOCK(sc);
647 if (sc->sc_req != NULL) {
648 JZ_MMC_UNLOCK(sc);
649 return (EBUSY);
650 }
651 /* Start with template value */
652 cmdat = sc->sc_cmdat;
653 iwait = JZ_INT_END_CMD_RES;
654
655 /* Configure response format */
656 cmd = req->cmd;
657 switch (MMC_RSP(cmd->flags)) {
658 case MMC_RSP_R1:
659 case MMC_RSP_R1B:
660 cmdat |= JZ_RES_R1;
661 break;
662 case MMC_RSP_R2:
663 cmdat |= JZ_RES_R2;
664 break;
665 case MMC_RSP_R3:
666 cmdat |= JZ_RES_R3;
667 break;
668 };
669 if (cmd->opcode == MMC_GO_IDLE_STATE)
670 cmdat |= JZ_INIT;
671 if (cmd->flags & MMC_RSP_BUSY) {
672 cmdat |= JZ_BUSY;
673 iwait |= JZ_INT_PRG_DONE;
674 }
675
676 sc->sc_req = req;
677 sc->sc_resid = 0;
678 cmd->error = MMC_ERR_NONE;
679
680 if (cmd->data != NULL) {
681 cmdat |= JZ_DATA_EN;
682 if (cmd->data->flags & MMC_DATA_MULTI) {
683 cmdat |= JZ_AUTO_CMD12;
684 iwait |= JZ_INT_AUTO_CMD12_DONE;
685 }
686 if (cmd->data->flags & MMC_DATA_WRITE) {
687 cmdat |= JZ_WRITE;
688 iwait |= JZ_INT_PRG_DONE;
689 }
690 if (cmd->data->flags & MMC_DATA_STREAM)
691 cmdat |= JZ_STREAM;
692 else
693 iwait |= JZ_INT_DATA_TRAN_DONE;
694
695 blksz = min(cmd->data->len, MMC_SECTOR_SIZE);
696 JZ_MMC_WRITE_4(sc, JZ_MSC_BLKLEN, blksz);
697 JZ_MMC_WRITE_4(sc, JZ_MSC_NOB, cmd->data->len / blksz);
698
699 /* Attempt to setup DMA for this transaction */
700 if (jz4780_mmc_pio_mode == 0)
701 jz4780_mmc_prepare_dma(sc);
702 if (sc->sc_dma_inuse != 0) {
703 /* Wait for DMA completion interrupt */
704 iwait |= JZ_INT_DMAEND;
705 } else {
706 iwait |= (cmd->data->flags & MMC_DATA_WRITE) ?
707 JZ_INT_TXFIFO_WR_REQ : JZ_INT_RXFIFO_RD_REQ;
708 JZ_MMC_WRITE_4(sc, JZ_MSC_DMAC, 0);
709 }
710 }
711
712 sc->sc_intr_seen = 0;
713 sc->sc_intr_wait = iwait;
714 JZ_MMC_WRITE_4(sc, JZ_MSC_IMASK, ~(sc->sc_intr_mask | iwait));
715
716 #if defined(JZ_MMC_DEBUG)
717 device_printf(sc->sc_dev,
718 "REQUEST: CMD%u arg %#x flags %#x cmdat %#x sc_intr_wait = %#x\n",
719 cmd->opcode, cmd->arg, cmd->flags, cmdat, sc->sc_intr_wait);
720 #endif
721
722 JZ_MMC_WRITE_4(sc, JZ_MSC_ARG, cmd->arg);
723 JZ_MMC_WRITE_4(sc, JZ_MSC_CMD, cmd->opcode);
724 JZ_MMC_WRITE_4(sc, JZ_MSC_CMDAT, cmdat);
725
726 JZ_MMC_WRITE_4(sc, JZ_MSC_CTRL, JZ_START_OP | JZ_CLOCK_START);
727
728 callout_reset(&sc->sc_timeoutc, sc->sc_timeout * hz,
729 jz4780_mmc_timeout, sc);
730 JZ_MMC_UNLOCK(sc);
731
732 return (0);
733 }
734
735 static int
jz4780_mmc_read_ivar(device_t bus,device_t child,int which,uintptr_t * result)736 jz4780_mmc_read_ivar(device_t bus, device_t child, int which,
737 uintptr_t *result)
738 {
739 struct jz4780_mmc_softc *sc;
740
741 sc = device_get_softc(bus);
742 switch (which) {
743 default:
744 return (EINVAL);
745 case MMCBR_IVAR_BUS_MODE:
746 *(int *)result = sc->sc_host.ios.bus_mode;
747 break;
748 case MMCBR_IVAR_BUS_WIDTH:
749 *(int *)result = sc->sc_host.ios.bus_width;
750 break;
751 case MMCBR_IVAR_CHIP_SELECT:
752 *(int *)result = sc->sc_host.ios.chip_select;
753 break;
754 case MMCBR_IVAR_CLOCK:
755 *(int *)result = sc->sc_host.ios.clock;
756 break;
757 case MMCBR_IVAR_F_MIN:
758 *(int *)result = sc->sc_host.f_min;
759 break;
760 case MMCBR_IVAR_F_MAX:
761 *(int *)result = sc->sc_host.f_max;
762 break;
763 case MMCBR_IVAR_HOST_OCR:
764 *(int *)result = sc->sc_host.host_ocr;
765 break;
766 case MMCBR_IVAR_MODE:
767 *(int *)result = sc->sc_host.mode;
768 break;
769 case MMCBR_IVAR_OCR:
770 *(int *)result = sc->sc_host.ocr;
771 break;
772 case MMCBR_IVAR_POWER_MODE:
773 *(int *)result = sc->sc_host.ios.power_mode;
774 break;
775 case MMCBR_IVAR_RETUNE_REQ:
776 *(int *)result = retune_req_none;
777 break;
778 case MMCBR_IVAR_VDD:
779 *(int *)result = sc->sc_host.ios.vdd;
780 break;
781 case MMCBR_IVAR_VCCQ:
782 *result = sc->sc_host.ios.vccq;
783 break;
784 case MMCBR_IVAR_CAPS:
785 *(int *)result = sc->sc_host.caps;
786 break;
787 case MMCBR_IVAR_TIMING:
788 *(int *)result = sc->sc_host.ios.timing;
789 break;
790 case MMCBR_IVAR_MAX_DATA:
791 *(int *)result = 65535;
792 break;
793 case MMCBR_IVAR_MAX_BUSY_TIMEOUT:
794 *(int *)result = 1000000; /* 1s max */
795 break;
796 }
797
798 return (0);
799 }
800
801 static int
jz4780_mmc_write_ivar(device_t bus,device_t child,int which,uintptr_t value)802 jz4780_mmc_write_ivar(device_t bus, device_t child, int which,
803 uintptr_t value)
804 {
805 struct jz4780_mmc_softc *sc;
806
807 sc = device_get_softc(bus);
808 switch (which) {
809 default:
810 return (EINVAL);
811 case MMCBR_IVAR_BUS_MODE:
812 sc->sc_host.ios.bus_mode = value;
813 break;
814 case MMCBR_IVAR_BUS_WIDTH:
815 sc->sc_host.ios.bus_width = value;
816 break;
817 case MMCBR_IVAR_CHIP_SELECT:
818 sc->sc_host.ios.chip_select = value;
819 break;
820 case MMCBR_IVAR_CLOCK:
821 sc->sc_host.ios.clock = value;
822 break;
823 case MMCBR_IVAR_MODE:
824 sc->sc_host.mode = value;
825 break;
826 case MMCBR_IVAR_OCR:
827 sc->sc_host.ocr = value;
828 break;
829 case MMCBR_IVAR_POWER_MODE:
830 sc->sc_host.ios.power_mode = value;
831 break;
832 case MMCBR_IVAR_VDD:
833 sc->sc_host.ios.vdd = value;
834 break;
835 case MMCBR_IVAR_VCCQ:
836 sc->sc_host.ios.vccq = value;
837 break;
838 case MMCBR_IVAR_TIMING:
839 sc->sc_host.ios.timing = value;
840 break;
841 /* These are read-only */
842 case MMCBR_IVAR_CAPS:
843 case MMCBR_IVAR_HOST_OCR:
844 case MMCBR_IVAR_F_MIN:
845 case MMCBR_IVAR_F_MAX:
846 case MMCBR_IVAR_MAX_DATA:
847 return (EINVAL);
848 }
849
850 return (0);
851 }
852
853 static int
jz4780_mmc_disable_clock(struct jz4780_mmc_softc * sc)854 jz4780_mmc_disable_clock(struct jz4780_mmc_softc *sc)
855 {
856 int timeout;
857
858 JZ_MMC_WRITE_4(sc, JZ_MSC_CTRL, JZ_CLOCK_STOP);
859
860 for (timeout = 1000; timeout > 0; timeout--)
861 if ((JZ_MMC_READ_4(sc, JZ_MSC_STAT) & JZ_CLK_EN) == 0)
862 return (0);
863 return (ETIMEDOUT);
864 }
865
866 static int
jz4780_mmc_config_clock(struct jz4780_mmc_softc * sc,uint32_t freq)867 jz4780_mmc_config_clock(struct jz4780_mmc_softc *sc, uint32_t freq)
868 {
869 uint64_t rate;
870 uint32_t clk_freq;
871 int err, div;
872
873 err = jz4780_mmc_disable_clock(sc);
874 if (err != 0)
875 return (err);
876
877 clk_get_freq(sc->sc_clk, &rate);
878 clk_freq = (uint32_t)rate;
879
880 div = 0;
881 while (clk_freq > freq) {
882 div++;
883 clk_freq >>= 1;
884 }
885 if (div >= 7)
886 div = 7;
887 #if defined(JZ_MMC_DEBUG)
888 if (div != JZ_MMC_READ_4(sc, JZ_MSC_CLKRT))
889 device_printf(sc->sc_dev,
890 "UPDATE_IOS: clk -> %u\n", clk_freq);
891 #endif
892 JZ_MMC_WRITE_4(sc, JZ_MSC_CLKRT, div);
893 return (0);
894 }
895
896 static int
jz4780_mmc_update_ios(device_t bus,device_t child)897 jz4780_mmc_update_ios(device_t bus, device_t child)
898 {
899 struct jz4780_mmc_softc *sc;
900 struct mmc_ios *ios;
901 int error;
902
903 sc = device_get_softc(bus);
904 ios = &sc->sc_host.ios;
905 if (ios->clock) {
906 /* Set the MMC clock. */
907 error = jz4780_mmc_config_clock(sc, ios->clock);
908 if (error != 0)
909 return (error);
910 }
911
912 /* Set the bus width. */
913 switch (ios->bus_width) {
914 case bus_width_1:
915 sc->sc_cmdat &= ~(JZ_BUS_WIDTH_M);
916 sc->sc_cmdat |= JZ_BUS_1BIT;
917 break;
918 case bus_width_4:
919 sc->sc_cmdat &= ~(JZ_BUS_WIDTH_M);
920 sc->sc_cmdat |= JZ_BUS_4BIT;
921 break;
922 case bus_width_8:
923 sc->sc_cmdat &= ~(JZ_BUS_WIDTH_M);
924 sc->sc_cmdat |= JZ_BUS_8BIT;
925 break;
926 }
927 return (0);
928 }
929
930 static int
jz4780_mmc_get_ro(device_t bus,device_t child)931 jz4780_mmc_get_ro(device_t bus, device_t child)
932 {
933
934 return (0);
935 }
936
937 static int
jz4780_mmc_acquire_host(device_t bus,device_t child)938 jz4780_mmc_acquire_host(device_t bus, device_t child)
939 {
940 struct jz4780_mmc_softc *sc;
941 int error;
942
943 sc = device_get_softc(bus);
944 JZ_MMC_LOCK(sc);
945 while (sc->sc_bus_busy) {
946 error = msleep(sc, &sc->sc_mtx, PCATCH, "mmchw", 0);
947 if (error != 0) {
948 JZ_MMC_UNLOCK(sc);
949 return (error);
950 }
951 }
952 sc->sc_bus_busy++;
953 JZ_MMC_UNLOCK(sc);
954
955 return (0);
956 }
957
958 static int
jz4780_mmc_release_host(device_t bus,device_t child)959 jz4780_mmc_release_host(device_t bus, device_t child)
960 {
961 struct jz4780_mmc_softc *sc;
962
963 sc = device_get_softc(bus);
964 JZ_MMC_LOCK(sc);
965 sc->sc_bus_busy--;
966 wakeup(sc);
967 JZ_MMC_UNLOCK(sc);
968
969 return (0);
970 }
971
972 static device_method_t jz4780_mmc_methods[] = {
973 /* Device interface */
974 DEVMETHOD(device_probe, jz4780_mmc_probe),
975 DEVMETHOD(device_attach, jz4780_mmc_attach),
976 DEVMETHOD(device_detach, jz4780_mmc_detach),
977
978 /* Bus interface */
979 DEVMETHOD(bus_read_ivar, jz4780_mmc_read_ivar),
980 DEVMETHOD(bus_write_ivar, jz4780_mmc_write_ivar),
981
982 /* MMC bridge interface */
983 DEVMETHOD(mmcbr_update_ios, jz4780_mmc_update_ios),
984 DEVMETHOD(mmcbr_request, jz4780_mmc_request),
985 DEVMETHOD(mmcbr_get_ro, jz4780_mmc_get_ro),
986 DEVMETHOD(mmcbr_acquire_host, jz4780_mmc_acquire_host),
987 DEVMETHOD(mmcbr_release_host, jz4780_mmc_release_host),
988
989 DEVMETHOD_END
990 };
991
992 static devclass_t jz4780_mmc_devclass;
993
994 static driver_t jz4780_mmc_driver = {
995 "jzmmc",
996 jz4780_mmc_methods,
997 sizeof(struct jz4780_mmc_softc),
998 };
999
1000 DRIVER_MODULE(jzmmc, simplebus, jz4780_mmc_driver, jz4780_mmc_devclass, NULL,
1001 NULL);
1002 MMC_DECLARE_BRIDGE(jzmmc);
1003