1 /*-
2 * SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB
3 *
4 * Copyright (c) 2015 - 2023 Intel Corporation
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenFabrics.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #include "osdep.h"
36 #include "irdma_hmc.h"
37 #include "irdma_defs.h"
38 #include "irdma_type.h"
39 #include "irdma_ws.h"
40 #include "irdma_protos.h"
41
42 /**
43 * irdma_qp_from_entry - Given entry, get to the qp structure
44 * @entry: Points to list of qp structure
45 */
46 static struct irdma_sc_qp *
irdma_qp_from_entry(struct list_head * entry)47 irdma_qp_from_entry(struct list_head *entry)
48 {
49 if (!entry)
50 return NULL;
51
52 return (struct irdma_sc_qp *)((char *)entry -
53 offsetof(struct irdma_sc_qp, list));
54 }
55
56 /**
57 * irdma_get_qp_from_list - get next qp from a list
58 * @head: Listhead of qp's
59 * @qp: current qp
60 */
61 struct irdma_sc_qp *
irdma_get_qp_from_list(struct list_head * head,struct irdma_sc_qp * qp)62 irdma_get_qp_from_list(struct list_head *head,
63 struct irdma_sc_qp *qp)
64 {
65 struct list_head *lastentry;
66 struct list_head *entry = NULL;
67
68 if (list_empty(head))
69 return NULL;
70
71 if (!qp) {
72 entry = (head)->next;
73 } else {
74 lastentry = &qp->list;
75 entry = (lastentry)->next;
76 if (entry == head)
77 return NULL;
78 }
79
80 return irdma_qp_from_entry(entry);
81 }
82
83 /**
84 * irdma_sc_suspend_resume_qps - suspend/resume all qp's on VSI
85 * @vsi: the VSI struct pointer
86 * @op: Set to IRDMA_OP_RESUME or IRDMA_OP_SUSPEND
87 */
88 void
irdma_sc_suspend_resume_qps(struct irdma_sc_vsi * vsi,u8 op)89 irdma_sc_suspend_resume_qps(struct irdma_sc_vsi *vsi, u8 op)
90 {
91 struct irdma_sc_qp *qp = NULL;
92 u8 i;
93
94 for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++) {
95 mutex_lock(&vsi->qos[i].qos_mutex);
96 qp = irdma_get_qp_from_list(&vsi->qos[i].qplist, qp);
97 while (qp) {
98 if (op == IRDMA_OP_RESUME) {
99 if (!qp->dev->ws_add(vsi, i)) {
100 qp->qs_handle =
101 vsi->qos[qp->user_pri].qs_handle;
102 irdma_cqp_qp_suspend_resume(qp, op);
103 } else {
104 irdma_cqp_qp_suspend_resume(qp, op);
105 irdma_modify_qp_to_err(qp);
106 }
107 } else if (op == IRDMA_OP_SUSPEND) {
108 /* issue cqp suspend command */
109 if (!irdma_cqp_qp_suspend_resume(qp, op))
110 atomic_inc(&vsi->qp_suspend_reqs);
111 }
112 qp = irdma_get_qp_from_list(&vsi->qos[i].qplist, qp);
113 }
114 mutex_unlock(&vsi->qos[i].qos_mutex);
115 }
116 }
117
118 static void
irdma_set_qos_info(struct irdma_sc_vsi * vsi,struct irdma_l2params * l2p)119 irdma_set_qos_info(struct irdma_sc_vsi *vsi, struct irdma_l2params *l2p)
120 {
121 u8 i;
122
123 vsi->qos_rel_bw = l2p->vsi_rel_bw;
124 vsi->qos_prio_type = l2p->vsi_prio_type;
125 vsi->dscp_mode = l2p->dscp_mode;
126 if (l2p->dscp_mode) {
127 irdma_memcpy(vsi->dscp_map, l2p->dscp_map, sizeof(vsi->dscp_map));
128 for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++)
129 l2p->up2tc[i] = i;
130 }
131 for (i = 0; i < IRDMA_MAX_TRAFFIC_CLASS; i++)
132 vsi->tc_print_warning[i] = true;
133 for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++) {
134 if (vsi->dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1)
135 vsi->qos[i].qs_handle = l2p->qs_handle_list[i];
136 if (vsi->dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_2)
137 irdma_init_config_check(&vsi->cfg_check[i],
138 l2p->up2tc[i],
139 l2p->qs_handle_list[i]);
140 vsi->qos[i].traffic_class = l2p->up2tc[i];
141 vsi->qos[i].rel_bw =
142 l2p->tc_info[vsi->qos[i].traffic_class].rel_bw;
143 vsi->qos[i].prio_type =
144 l2p->tc_info[vsi->qos[i].traffic_class].prio_type;
145 vsi->qos[i].valid = false;
146 }
147 }
148
149 /**
150 * irdma_change_l2params - given the new l2 parameters, change all qp
151 * @vsi: RDMA VSI pointer
152 * @l2params: New parameters from l2
153 */
154 void
irdma_change_l2params(struct irdma_sc_vsi * vsi,struct irdma_l2params * l2params)155 irdma_change_l2params(struct irdma_sc_vsi *vsi,
156 struct irdma_l2params *l2params)
157 {
158 if (l2params->tc_changed) {
159 vsi->tc_change_pending = false;
160 irdma_set_qos_info(vsi, l2params);
161 irdma_sc_suspend_resume_qps(vsi, IRDMA_OP_RESUME);
162 }
163 if (l2params->mtu_changed) {
164 vsi->mtu = l2params->mtu;
165 if (vsi->ieq)
166 irdma_reinitialize_ieq(vsi);
167 }
168 }
169
170 /**
171 * irdma_qp_rem_qos - remove qp from qos lists during destroy qp
172 * @qp: qp to be removed from qos
173 */
174 void
irdma_qp_rem_qos(struct irdma_sc_qp * qp)175 irdma_qp_rem_qos(struct irdma_sc_qp *qp)
176 {
177 struct irdma_sc_vsi *vsi = qp->vsi;
178
179 irdma_debug(qp->dev, IRDMA_DEBUG_DCB,
180 "DCB: Remove qp[%d] UP[%d] qset[%d] on_qoslist[%d]\n",
181 qp->qp_uk.qp_id, qp->user_pri, qp->qs_handle,
182 qp->on_qoslist);
183 mutex_lock(&vsi->qos[qp->user_pri].qos_mutex);
184 if (qp->on_qoslist) {
185 qp->on_qoslist = false;
186 list_del(&qp->list);
187 }
188 mutex_unlock(&vsi->qos[qp->user_pri].qos_mutex);
189 }
190
191 /**
192 * irdma_qp_add_qos - called during setctx for qp to be added to qos
193 * @qp: qp to be added to qos
194 */
195 void
irdma_qp_add_qos(struct irdma_sc_qp * qp)196 irdma_qp_add_qos(struct irdma_sc_qp *qp)
197 {
198 struct irdma_sc_vsi *vsi = qp->vsi;
199
200 irdma_debug(qp->dev, IRDMA_DEBUG_DCB,
201 "DCB: Add qp[%d] UP[%d] qset[%d] on_qoslist[%d]\n",
202 qp->qp_uk.qp_id, qp->user_pri, qp->qs_handle,
203 qp->on_qoslist);
204 mutex_lock(&vsi->qos[qp->user_pri].qos_mutex);
205 if (!qp->on_qoslist) {
206 list_add(&qp->list, &vsi->qos[qp->user_pri].qplist);
207 qp->on_qoslist = true;
208 qp->qs_handle = vsi->qos[qp->user_pri].qs_handle;
209 }
210 mutex_unlock(&vsi->qos[qp->user_pri].qos_mutex);
211 }
212
213 /**
214 * irdma_sc_pd_init - initialize sc pd struct
215 * @dev: sc device struct
216 * @pd: sc pd ptr
217 * @pd_id: pd_id for allocated pd
218 * @abi_ver: User/Kernel ABI version
219 */
220 void
irdma_sc_pd_init(struct irdma_sc_dev * dev,struct irdma_sc_pd * pd,u32 pd_id,int abi_ver)221 irdma_sc_pd_init(struct irdma_sc_dev *dev, struct irdma_sc_pd *pd, u32 pd_id,
222 int abi_ver)
223 {
224 pd->pd_id = pd_id;
225 pd->abi_ver = abi_ver;
226 pd->dev = dev;
227 }
228
229 /**
230 * irdma_sc_add_arp_cache_entry - cqp wqe add arp cache entry
231 * @cqp: struct for cqp hw
232 * @info: arp entry information
233 * @scratch: u64 saved to be used during cqp completion
234 * @post_sq: flag for cqp db to ring
235 */
236 static int
irdma_sc_add_arp_cache_entry(struct irdma_sc_cqp * cqp,struct irdma_add_arp_cache_entry_info * info,u64 scratch,bool post_sq)237 irdma_sc_add_arp_cache_entry(struct irdma_sc_cqp *cqp,
238 struct irdma_add_arp_cache_entry_info *info,
239 u64 scratch, bool post_sq)
240 {
241 __le64 *wqe;
242 u64 hdr;
243
244 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
245 if (!wqe)
246 return -ENOSPC;
247 set_64bit_val(wqe, IRDMA_BYTE_8, info->reach_max);
248
249 set_64bit_val(wqe, IRDMA_BYTE_16, irdma_mac_to_u64(info->mac_addr));
250
251 hdr = info->arp_index |
252 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MANAGE_ARP) |
253 FIELD_PREP(IRDMA_CQPSQ_MAT_PERMANENT, info->permanent) |
254 FIELD_PREP(IRDMA_CQPSQ_MAT_ENTRYVALID, true) |
255 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
256 irdma_wmb(); /* make sure WQE is written before valid bit is set */
257
258 set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
259
260 irdma_debug_buf(cqp->dev, IRDMA_DEBUG_WQE, "ARP_CACHE_ENTRY WQE", wqe,
261 IRDMA_CQP_WQE_SIZE * 8);
262 if (post_sq)
263 irdma_sc_cqp_post_sq(cqp);
264
265 return 0;
266 }
267
268 /**
269 * irdma_sc_del_arp_cache_entry - dele arp cache entry
270 * @cqp: struct for cqp hw
271 * @scratch: u64 saved to be used during cqp completion
272 * @arp_index: arp index to delete arp entry
273 * @post_sq: flag for cqp db to ring
274 */
275 static int
irdma_sc_del_arp_cache_entry(struct irdma_sc_cqp * cqp,u64 scratch,u16 arp_index,bool post_sq)276 irdma_sc_del_arp_cache_entry(struct irdma_sc_cqp *cqp, u64 scratch,
277 u16 arp_index, bool post_sq)
278 {
279 __le64 *wqe;
280 u64 hdr;
281
282 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
283 if (!wqe)
284 return -ENOSPC;
285
286 hdr = arp_index |
287 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MANAGE_ARP) |
288 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
289 irdma_wmb(); /* make sure WQE is written before valid bit is set */
290
291 set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
292
293 irdma_debug_buf(cqp->dev, IRDMA_DEBUG_WQE, "ARP_CACHE_DEL_ENTRY WQE",
294 wqe, IRDMA_CQP_WQE_SIZE * 8);
295 if (post_sq)
296 irdma_sc_cqp_post_sq(cqp);
297
298 return 0;
299 }
300
301 /**
302 * irdma_sc_manage_apbvt_entry - for adding and deleting apbvt entries
303 * @cqp: struct for cqp hw
304 * @info: info for apbvt entry to add or delete
305 * @scratch: u64 saved to be used during cqp completion
306 * @post_sq: flag for cqp db to ring
307 */
308 static int
irdma_sc_manage_apbvt_entry(struct irdma_sc_cqp * cqp,struct irdma_apbvt_info * info,u64 scratch,bool post_sq)309 irdma_sc_manage_apbvt_entry(struct irdma_sc_cqp *cqp,
310 struct irdma_apbvt_info *info,
311 u64 scratch, bool post_sq)
312 {
313 __le64 *wqe;
314 u64 hdr;
315
316 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
317 if (!wqe)
318 return -ENOSPC;
319
320 set_64bit_val(wqe, IRDMA_BYTE_16, info->port);
321
322 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MANAGE_APBVT) |
323 FIELD_PREP(IRDMA_CQPSQ_MAPT_ADDPORT, info->add) |
324 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
325 irdma_wmb(); /* make sure WQE is written before valid bit is set */
326
327 set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
328
329 irdma_debug_buf(cqp->dev, IRDMA_DEBUG_WQE, "MANAGE_APBVT WQE", wqe,
330 IRDMA_CQP_WQE_SIZE * 8);
331 if (post_sq)
332 irdma_sc_cqp_post_sq(cqp);
333
334 return 0;
335 }
336
337 /**
338 * irdma_sc_manage_qhash_table_entry - manage quad hash entries
339 * @cqp: struct for cqp hw
340 * @info: info for quad hash to manage
341 * @scratch: u64 saved to be used during cqp completion
342 * @post_sq: flag for cqp db to ring
343 *
344 * This is called before connection establishment is started.
345 * For passive connections, when listener is created, it will
346 * call with entry type of IRDMA_QHASH_TYPE_TCP_SYN with local
347 * ip address and tcp port. When SYN is received (passive
348 * connections) or sent (active connections), this routine is
349 * called with entry type of IRDMA_QHASH_TYPE_TCP_ESTABLISHED
350 * and quad is passed in info.
351 *
352 * When iwarp connection is done and its state moves to RTS, the
353 * quad hash entry in the hardware will point to iwarp's qp
354 * number and requires no calls from the driver.
355 */
356 static int
irdma_sc_manage_qhash_table_entry(struct irdma_sc_cqp * cqp,struct irdma_qhash_table_info * info,u64 scratch,bool post_sq)357 irdma_sc_manage_qhash_table_entry(struct irdma_sc_cqp *cqp,
358 struct irdma_qhash_table_info *info,
359 u64 scratch, bool post_sq)
360 {
361 __le64 *wqe;
362 u64 qw1 = 0;
363 u64 qw2 = 0;
364 u64 temp;
365 struct irdma_sc_vsi *vsi = info->vsi;
366
367 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
368 if (!wqe)
369 return -ENOSPC;
370 set_64bit_val(wqe, IRDMA_BYTE_0, irdma_mac_to_u64(info->mac_addr));
371
372 qw1 = FIELD_PREP(IRDMA_CQPSQ_QHASH_QPN, info->qp_num) |
373 FIELD_PREP(IRDMA_CQPSQ_QHASH_DEST_PORT, info->dest_port);
374 if (info->ipv4_valid) {
375 set_64bit_val(wqe, IRDMA_BYTE_48,
376 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR3, info->dest_ip[0]));
377 } else {
378 set_64bit_val(wqe, IRDMA_BYTE_56,
379 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR0, info->dest_ip[0]) |
380 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR1, info->dest_ip[1]));
381
382 set_64bit_val(wqe, IRDMA_BYTE_48,
383 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR2, info->dest_ip[2]) |
384 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR3, info->dest_ip[3]));
385 }
386 qw2 = FIELD_PREP(IRDMA_CQPSQ_QHASH_QS_HANDLE,
387 vsi->qos[info->user_pri].qs_handle);
388 if (info->vlan_valid)
389 qw2 |= FIELD_PREP(IRDMA_CQPSQ_QHASH_VLANID, info->vlan_id);
390 set_64bit_val(wqe, IRDMA_BYTE_16, qw2);
391 if (info->entry_type == IRDMA_QHASH_TYPE_TCP_ESTABLISHED) {
392 qw1 |= FIELD_PREP(IRDMA_CQPSQ_QHASH_SRC_PORT, info->src_port);
393 if (!info->ipv4_valid) {
394 set_64bit_val(wqe, IRDMA_BYTE_40,
395 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR0, info->src_ip[0]) |
396 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR1, info->src_ip[1]));
397 set_64bit_val(wqe, IRDMA_BYTE_32,
398 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR2, info->src_ip[2]) |
399 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR3, info->src_ip[3]));
400 } else {
401 set_64bit_val(wqe, IRDMA_BYTE_32,
402 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR3, info->src_ip[0]));
403 }
404 }
405
406 set_64bit_val(wqe, IRDMA_BYTE_8, qw1);
407 temp = FIELD_PREP(IRDMA_CQPSQ_QHASH_WQEVALID, cqp->polarity) |
408 FIELD_PREP(IRDMA_CQPSQ_QHASH_OPCODE,
409 IRDMA_CQP_OP_MANAGE_QUAD_HASH_TABLE_ENTRY) |
410 FIELD_PREP(IRDMA_CQPSQ_QHASH_MANAGE, info->manage) |
411 FIELD_PREP(IRDMA_CQPSQ_QHASH_IPV4VALID, info->ipv4_valid) |
412 FIELD_PREP(IRDMA_CQPSQ_QHASH_VLANVALID, info->vlan_valid) |
413 FIELD_PREP(IRDMA_CQPSQ_QHASH_ENTRYTYPE, info->entry_type);
414 irdma_wmb(); /* make sure WQE is written before valid bit is set */
415
416 set_64bit_val(wqe, IRDMA_BYTE_24, temp);
417
418 irdma_debug_buf(cqp->dev, IRDMA_DEBUG_WQE, "MANAGE_QHASH WQE", wqe,
419 IRDMA_CQP_WQE_SIZE * 8);
420 if (post_sq)
421 irdma_sc_cqp_post_sq(cqp);
422
423 return 0;
424 }
425
426 /**
427 * irdma_sc_qp_init - initialize qp
428 * @qp: sc qp
429 * @info: initialization qp info
430 */
431 int
irdma_sc_qp_init(struct irdma_sc_qp * qp,struct irdma_qp_init_info * info)432 irdma_sc_qp_init(struct irdma_sc_qp *qp, struct irdma_qp_init_info *info)
433 {
434 int ret_code;
435 u32 pble_obj_cnt;
436 u16 wqe_size;
437
438 if (info->qp_uk_init_info.max_sq_frag_cnt >
439 info->pd->dev->hw_attrs.uk_attrs.max_hw_wq_frags ||
440 info->qp_uk_init_info.max_rq_frag_cnt >
441 info->pd->dev->hw_attrs.uk_attrs.max_hw_wq_frags)
442 return -EINVAL;
443
444 qp->dev = info->pd->dev;
445 qp->vsi = info->vsi;
446 qp->ieq_qp = info->vsi->exception_lan_q;
447 qp->sq_pa = info->sq_pa;
448 qp->rq_pa = info->rq_pa;
449 qp->hw_host_ctx_pa = info->host_ctx_pa;
450 qp->q2_pa = info->q2_pa;
451 qp->shadow_area_pa = info->shadow_area_pa;
452 qp->q2_buf = info->q2;
453 qp->pd = info->pd;
454 qp->hw_host_ctx = info->host_ctx;
455 info->qp_uk_init_info.wqe_alloc_db = qp->pd->dev->wqe_alloc_db;
456 ret_code = irdma_uk_qp_init(&qp->qp_uk, &info->qp_uk_init_info);
457 if (ret_code)
458 return ret_code;
459
460 qp->virtual_map = info->virtual_map;
461 pble_obj_cnt = info->pd->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt;
462
463 if ((info->virtual_map && info->sq_pa >= pble_obj_cnt) ||
464 (info->virtual_map && info->rq_pa >= pble_obj_cnt))
465 return -EINVAL;
466
467 qp->llp_stream_handle = (void *)(-1);
468 qp->hw_sq_size = irdma_get_encoded_wqe_size(qp->qp_uk.sq_ring.size,
469 IRDMA_QUEUE_TYPE_SQ_RQ);
470 irdma_debug(qp->dev, IRDMA_DEBUG_WQE,
471 "hw_sq_size[%04d] sq_ring.size[%04d]\n", qp->hw_sq_size,
472 qp->qp_uk.sq_ring.size);
473 if (qp->qp_uk.uk_attrs->hw_rev == IRDMA_GEN_1)
474 wqe_size = IRDMA_WQE_SIZE_128;
475 else
476 ret_code = irdma_fragcnt_to_wqesize_rq(qp->qp_uk.max_rq_frag_cnt,
477 &wqe_size);
478 if (ret_code)
479 return ret_code;
480
481 qp->hw_rq_size =
482 irdma_get_encoded_wqe_size(qp->qp_uk.rq_size *
483 (wqe_size / IRDMA_QP_WQE_MIN_SIZE),
484 IRDMA_QUEUE_TYPE_SQ_RQ);
485 irdma_debug(qp->dev, IRDMA_DEBUG_WQE,
486 "hw_rq_size[%04d] qp_uk.rq_size[%04d] wqe_size[%04d]\n",
487 qp->hw_rq_size, qp->qp_uk.rq_size, wqe_size);
488
489 qp->sq_tph_val = info->sq_tph_val;
490 qp->rq_tph_val = info->rq_tph_val;
491 qp->sq_tph_en = info->sq_tph_en;
492 qp->rq_tph_en = info->rq_tph_en;
493 qp->rcv_tph_en = info->rcv_tph_en;
494 qp->xmit_tph_en = info->xmit_tph_en;
495 qp->qp_uk.first_sq_wq = info->qp_uk_init_info.first_sq_wq;
496 qp->qs_handle = qp->vsi->qos[qp->user_pri].qs_handle;
497
498 return 0;
499 }
500
501 /**
502 * irdma_sc_qp_create - create qp
503 * @qp: sc qp
504 * @info: qp create info
505 * @scratch: u64 saved to be used during cqp completion
506 * @post_sq: flag for cqp db to ring
507 */
508 int
irdma_sc_qp_create(struct irdma_sc_qp * qp,struct irdma_create_qp_info * info,u64 scratch,bool post_sq)509 irdma_sc_qp_create(struct irdma_sc_qp *qp, struct irdma_create_qp_info *info,
510 u64 scratch, bool post_sq)
511 {
512 struct irdma_sc_cqp *cqp;
513 __le64 *wqe;
514 u64 hdr;
515
516 cqp = qp->dev->cqp;
517 if (qp->qp_uk.qp_id < cqp->dev->hw_attrs.min_hw_qp_id ||
518 qp->qp_uk.qp_id > (cqp->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_QP].max_cnt - 1))
519 return -EINVAL;
520
521 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
522 if (!wqe)
523 return -ENOSPC;
524
525 set_64bit_val(wqe, IRDMA_BYTE_16, qp->hw_host_ctx_pa);
526 set_64bit_val(wqe, IRDMA_BYTE_40, qp->shadow_area_pa);
527
528 hdr = qp->qp_uk.qp_id |
529 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_CREATE_QP) |
530 FIELD_PREP(IRDMA_CQPSQ_QP_ORDVALID, info->ord_valid) |
531 FIELD_PREP(IRDMA_CQPSQ_QP_TOECTXVALID, info->tcp_ctx_valid) |
532 FIELD_PREP(IRDMA_CQPSQ_QP_MACVALID, info->mac_valid) |
533 FIELD_PREP(IRDMA_CQPSQ_QP_QPTYPE, qp->qp_uk.qp_type) |
534 FIELD_PREP(IRDMA_CQPSQ_QP_VQ, qp->virtual_map) |
535 FIELD_PREP(IRDMA_CQPSQ_QP_FORCELOOPBACK, info->force_lpb) |
536 FIELD_PREP(IRDMA_CQPSQ_QP_CQNUMVALID, info->cq_num_valid) |
537 FIELD_PREP(IRDMA_CQPSQ_QP_ARPTABIDXVALID,
538 info->arp_cache_idx_valid) |
539 FIELD_PREP(IRDMA_CQPSQ_QP_NEXTIWSTATE, info->next_iwarp_state) |
540 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
541
542 irdma_wmb(); /* make sure WQE is written before valid bit is set */
543
544 set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
545
546 irdma_debug_buf(cqp->dev, IRDMA_DEBUG_WQE, "QP_CREATE WQE", wqe,
547 IRDMA_CQP_WQE_SIZE * 8);
548 if (post_sq)
549 irdma_sc_cqp_post_sq(cqp);
550
551 return 0;
552 }
553
554 /**
555 * irdma_sc_qp_modify - modify qp cqp wqe
556 * @qp: sc qp
557 * @info: modify qp info
558 * @scratch: u64 saved to be used during cqp completion
559 * @post_sq: flag for cqp db to ring
560 */
561 int
irdma_sc_qp_modify(struct irdma_sc_qp * qp,struct irdma_modify_qp_info * info,u64 scratch,bool post_sq)562 irdma_sc_qp_modify(struct irdma_sc_qp *qp, struct irdma_modify_qp_info *info,
563 u64 scratch, bool post_sq)
564 {
565 __le64 *wqe;
566 struct irdma_sc_cqp *cqp;
567 u64 hdr;
568 u8 term_actions = 0;
569 u8 term_len = 0;
570
571 cqp = qp->dev->cqp;
572 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
573 if (!wqe)
574 return -ENOSPC;
575
576 if (info->next_iwarp_state == IRDMA_QP_STATE_TERMINATE) {
577 if (info->dont_send_fin)
578 term_actions += IRDMAQP_TERM_SEND_TERM_ONLY;
579 if (info->dont_send_term)
580 term_actions += IRDMAQP_TERM_SEND_FIN_ONLY;
581 if (term_actions == IRDMAQP_TERM_SEND_TERM_AND_FIN ||
582 term_actions == IRDMAQP_TERM_SEND_TERM_ONLY)
583 term_len = info->termlen;
584 }
585
586 set_64bit_val(wqe, IRDMA_BYTE_8,
587 FIELD_PREP(IRDMA_CQPSQ_QP_NEWMSS, info->new_mss) |
588 FIELD_PREP(IRDMA_CQPSQ_QP_TERMLEN, term_len));
589 set_64bit_val(wqe, IRDMA_BYTE_16, qp->hw_host_ctx_pa);
590 set_64bit_val(wqe, IRDMA_BYTE_40, qp->shadow_area_pa);
591
592 hdr = qp->qp_uk.qp_id |
593 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MODIFY_QP) |
594 FIELD_PREP(IRDMA_CQPSQ_QP_ORDVALID, info->ord_valid) |
595 FIELD_PREP(IRDMA_CQPSQ_QP_TOECTXVALID, info->tcp_ctx_valid) |
596 FIELD_PREP(IRDMA_CQPSQ_QP_CACHEDVARVALID,
597 info->cached_var_valid) |
598 FIELD_PREP(IRDMA_CQPSQ_QP_VQ, qp->virtual_map) |
599 FIELD_PREP(IRDMA_CQPSQ_QP_FORCELOOPBACK, info->force_lpb) |
600 FIELD_PREP(IRDMA_CQPSQ_QP_CQNUMVALID, info->cq_num_valid) |
601 FIELD_PREP(IRDMA_CQPSQ_QP_MACVALID, info->mac_valid) |
602 FIELD_PREP(IRDMA_CQPSQ_QP_QPTYPE, qp->qp_uk.qp_type) |
603 FIELD_PREP(IRDMA_CQPSQ_QP_MSSCHANGE, info->mss_change) |
604 FIELD_PREP(IRDMA_CQPSQ_QP_REMOVEHASHENTRY,
605 info->remove_hash_idx) |
606 FIELD_PREP(IRDMA_CQPSQ_QP_TERMACT, term_actions) |
607 FIELD_PREP(IRDMA_CQPSQ_QP_RESETCON, info->reset_tcp_conn) |
608 FIELD_PREP(IRDMA_CQPSQ_QP_ARPTABIDXVALID,
609 info->arp_cache_idx_valid) |
610 FIELD_PREP(IRDMA_CQPSQ_QP_NEXTIWSTATE, info->next_iwarp_state) |
611 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
612
613 irdma_wmb(); /* make sure WQE is written before valid bit is set */
614
615 set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
616
617 irdma_debug_buf(cqp->dev, IRDMA_DEBUG_WQE, "QP_MODIFY WQE", wqe,
618 IRDMA_CQP_WQE_SIZE * 8);
619 if (post_sq)
620 irdma_sc_cqp_post_sq(cqp);
621
622 return 0;
623 }
624
625 /**
626 * irdma_sc_qp_destroy - cqp destroy qp
627 * @qp: sc qp
628 * @scratch: u64 saved to be used during cqp completion
629 * @remove_hash_idx: flag if to remove hash idx
630 * @ignore_mw_bnd: memory window bind flag
631 * @post_sq: flag for cqp db to ring
632 */
633 int
irdma_sc_qp_destroy(struct irdma_sc_qp * qp,u64 scratch,bool remove_hash_idx,bool ignore_mw_bnd,bool post_sq)634 irdma_sc_qp_destroy(struct irdma_sc_qp *qp, u64 scratch,
635 bool remove_hash_idx, bool ignore_mw_bnd, bool post_sq)
636 {
637 __le64 *wqe;
638 struct irdma_sc_cqp *cqp;
639 u64 hdr;
640
641 cqp = qp->dev->cqp;
642 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
643 if (!wqe)
644 return -ENOSPC;
645
646 set_64bit_val(wqe, IRDMA_BYTE_16, qp->hw_host_ctx_pa);
647 set_64bit_val(wqe, IRDMA_BYTE_40, qp->shadow_area_pa);
648
649 hdr = qp->qp_uk.qp_id |
650 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DESTROY_QP) |
651 FIELD_PREP(IRDMA_CQPSQ_QP_QPTYPE, qp->qp_uk.qp_type) |
652 FIELD_PREP(IRDMA_CQPSQ_QP_IGNOREMWBOUND, ignore_mw_bnd) |
653 FIELD_PREP(IRDMA_CQPSQ_QP_REMOVEHASHENTRY, remove_hash_idx) |
654 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
655 irdma_wmb(); /* make sure WQE is written before valid bit is set */
656
657 set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
658
659 irdma_debug_buf(cqp->dev, IRDMA_DEBUG_WQE, "QP_DESTROY WQE", wqe,
660 IRDMA_CQP_WQE_SIZE * 8);
661 if (post_sq)
662 irdma_sc_cqp_post_sq(cqp);
663
664 return 0;
665 }
666
667 /**
668 * irdma_sc_get_encoded_ird_size -
669 * @ird_size: IRD size
670 * The ird from the connection is rounded to a supported HW setting and then encoded
671 * for ird_size field of qp_ctx. Consumers are expected to provide valid ird size based
672 * on hardware attributes. IRD size defaults to a value of 4 in case of invalid input
673 */
irdma_sc_get_encoded_ird_size(u16 ird_size)674 static u8 irdma_sc_get_encoded_ird_size(u16 ird_size) {
675 switch (ird_size ?
676 roundup_pow_of_two(2 * ird_size) : 4) {
677 case 256:
678 return IRDMA_IRD_HW_SIZE_256;
679 case 128:
680 return IRDMA_IRD_HW_SIZE_128;
681 case 64:
682 case 32:
683 return IRDMA_IRD_HW_SIZE_64;
684 case 16:
685 case 8:
686 return IRDMA_IRD_HW_SIZE_16;
687 case 4:
688 default:
689 break;
690 }
691
692 return IRDMA_IRD_HW_SIZE_4;
693 }
694
695 /**
696 * irdma_sc_qp_setctx_roce - set qp's context
697 * @qp: sc qp
698 * @qp_ctx: context ptr
699 * @info: ctx info
700 */
701 void
irdma_sc_qp_setctx_roce(struct irdma_sc_qp * qp,__le64 * qp_ctx,struct irdma_qp_host_ctx_info * info)702 irdma_sc_qp_setctx_roce(struct irdma_sc_qp *qp, __le64 * qp_ctx,
703 struct irdma_qp_host_ctx_info *info)
704 {
705 struct irdma_roce_offload_info *roce_info;
706 struct irdma_udp_offload_info *udp;
707 u8 push_mode_en;
708 u32 push_idx;
709
710 roce_info = info->roce_info;
711 udp = info->udp_info;
712
713 qp->user_pri = info->user_pri;
714 if (qp->push_idx == IRDMA_INVALID_PUSH_PAGE_INDEX) {
715 push_mode_en = 0;
716 push_idx = 0;
717 } else {
718 push_mode_en = 1;
719 push_idx = qp->push_idx;
720 }
721 set_64bit_val(qp_ctx, IRDMA_BYTE_0,
722 FIELD_PREP(IRDMAQPC_RQWQESIZE, qp->qp_uk.rq_wqe_size) |
723 FIELD_PREP(IRDMAQPC_RCVTPHEN, qp->rcv_tph_en) |
724 FIELD_PREP(IRDMAQPC_XMITTPHEN, qp->xmit_tph_en) |
725 FIELD_PREP(IRDMAQPC_RQTPHEN, qp->rq_tph_en) |
726 FIELD_PREP(IRDMAQPC_SQTPHEN, qp->sq_tph_en) |
727 FIELD_PREP(IRDMAQPC_PPIDX, push_idx) |
728 FIELD_PREP(IRDMAQPC_PMENA, push_mode_en) |
729 FIELD_PREP(IRDMAQPC_PDIDXHI, roce_info->pd_id >> 16) |
730 FIELD_PREP(IRDMAQPC_DC_TCP_EN, roce_info->dctcp_en) |
731 FIELD_PREP(IRDMAQPC_ERR_RQ_IDX_VALID, roce_info->err_rq_idx_valid) |
732 FIELD_PREP(IRDMAQPC_ISQP1, roce_info->is_qp1) |
733 FIELD_PREP(IRDMAQPC_ROCE_TVER, roce_info->roce_tver) |
734 FIELD_PREP(IRDMAQPC_IPV4, udp->ipv4) |
735 FIELD_PREP(IRDMAQPC_INSERTVLANTAG, udp->insert_vlan_tag));
736 set_64bit_val(qp_ctx, IRDMA_BYTE_8, qp->sq_pa);
737 set_64bit_val(qp_ctx, IRDMA_BYTE_16, qp->rq_pa);
738 if (roce_info->dcqcn_en || roce_info->dctcp_en) {
739 udp->tos &= ~ECN_CODE_PT_MASK;
740 udp->tos |= ECN_CODE_PT_VAL;
741 }
742
743 set_64bit_val(qp_ctx, IRDMA_BYTE_24,
744 FIELD_PREP(IRDMAQPC_RQSIZE, qp->hw_rq_size) |
745 FIELD_PREP(IRDMAQPC_SQSIZE, qp->hw_sq_size) |
746 FIELD_PREP(IRDMAQPC_TTL, udp->ttl) | FIELD_PREP(IRDMAQPC_TOS, udp->tos) |
747 FIELD_PREP(IRDMAQPC_SRCPORTNUM, udp->src_port) |
748 FIELD_PREP(IRDMAQPC_DESTPORTNUM, udp->dst_port));
749 set_64bit_val(qp_ctx, IRDMA_BYTE_32,
750 FIELD_PREP(IRDMAQPC_DESTIPADDR2, udp->dest_ip_addr[2]) |
751 FIELD_PREP(IRDMAQPC_DESTIPADDR3, udp->dest_ip_addr[3]));
752 set_64bit_val(qp_ctx, IRDMA_BYTE_40,
753 FIELD_PREP(IRDMAQPC_DESTIPADDR0, udp->dest_ip_addr[0]) |
754 FIELD_PREP(IRDMAQPC_DESTIPADDR1, udp->dest_ip_addr[1]));
755 set_64bit_val(qp_ctx, IRDMA_BYTE_48,
756 FIELD_PREP(IRDMAQPC_SNDMSS, udp->snd_mss) |
757 FIELD_PREP(IRDMAQPC_VLANTAG, udp->vlan_tag) |
758 FIELD_PREP(IRDMAQPC_ARPIDX, udp->arp_idx));
759 set_64bit_val(qp_ctx, IRDMA_BYTE_56,
760 FIELD_PREP(IRDMAQPC_PKEY, roce_info->p_key) |
761 FIELD_PREP(IRDMAQPC_PDIDX, roce_info->pd_id) |
762 FIELD_PREP(IRDMAQPC_ACKCREDITS, roce_info->ack_credits) |
763 FIELD_PREP(IRDMAQPC_FLOWLABEL, udp->flow_label));
764 set_64bit_val(qp_ctx, IRDMA_BYTE_64,
765 FIELD_PREP(IRDMAQPC_QKEY, roce_info->qkey) |
766 FIELD_PREP(IRDMAQPC_DESTQP, roce_info->dest_qp));
767 set_64bit_val(qp_ctx, IRDMA_BYTE_80,
768 FIELD_PREP(IRDMAQPC_PSNNXT, udp->psn_nxt) |
769 FIELD_PREP(IRDMAQPC_LSN, udp->lsn));
770 set_64bit_val(qp_ctx, IRDMA_BYTE_88,
771 FIELD_PREP(IRDMAQPC_EPSN, udp->epsn));
772 set_64bit_val(qp_ctx, IRDMA_BYTE_96,
773 FIELD_PREP(IRDMAQPC_PSNMAX, udp->psn_max) |
774 FIELD_PREP(IRDMAQPC_PSNUNA, udp->psn_una));
775 set_64bit_val(qp_ctx, IRDMA_BYTE_112,
776 FIELD_PREP(IRDMAQPC_CWNDROCE, udp->cwnd));
777 set_64bit_val(qp_ctx, IRDMA_BYTE_128,
778 FIELD_PREP(IRDMAQPC_ERR_RQ_IDX, roce_info->err_rq_idx) |
779 FIELD_PREP(IRDMAQPC_RNRNAK_THRESH, udp->rnr_nak_thresh) |
780 FIELD_PREP(IRDMAQPC_REXMIT_THRESH, udp->rexmit_thresh) |
781 FIELD_PREP(IRDMAQPC_RTOMIN, roce_info->rtomin));
782 set_64bit_val(qp_ctx, IRDMA_BYTE_136,
783 FIELD_PREP(IRDMAQPC_TXCQNUM, info->send_cq_num) |
784 FIELD_PREP(IRDMAQPC_RXCQNUM, info->rcv_cq_num));
785 set_64bit_val(qp_ctx, IRDMA_BYTE_144,
786 FIELD_PREP(IRDMAQPC_STAT_INDEX, info->stats_idx));
787 set_64bit_val(qp_ctx, IRDMA_BYTE_152,
788 FIELD_PREP(IRDMAQPC_MACADDRESS,
789 irdma_mac_to_u64(roce_info->mac_addr)));
790 set_64bit_val(qp_ctx, IRDMA_BYTE_160,
791 FIELD_PREP(IRDMAQPC_ORDSIZE, roce_info->ord_size) |
792 FIELD_PREP(IRDMAQPC_IRDSIZE, irdma_sc_get_encoded_ird_size(roce_info->ird_size)) |
793 FIELD_PREP(IRDMAQPC_WRRDRSPOK, roce_info->wr_rdresp_en) |
794 FIELD_PREP(IRDMAQPC_RDOK, roce_info->rd_en) |
795 FIELD_PREP(IRDMAQPC_USESTATSINSTANCE, info->stats_idx_valid) |
796 FIELD_PREP(IRDMAQPC_FASTREGEN, roce_info->fast_reg_en) |
797 FIELD_PREP(IRDMAQPC_DCQCNENABLE, roce_info->dcqcn_en) |
798 FIELD_PREP(IRDMAQPC_RCVNOICRC, roce_info->rcv_no_icrc) |
799 FIELD_PREP(IRDMAQPC_FW_CC_ENABLE, roce_info->fw_cc_enable) |
800 FIELD_PREP(IRDMAQPC_UDPRIVCQENABLE, roce_info->udprivcq_en) |
801 FIELD_PREP(IRDMAQPC_PRIVEN, roce_info->priv_mode_en) |
802 FIELD_PREP(IRDMAQPC_TIMELYENABLE, roce_info->timely_en));
803 set_64bit_val(qp_ctx, IRDMA_BYTE_168,
804 FIELD_PREP(IRDMAQPC_QPCOMPCTX, info->qp_compl_ctx));
805 set_64bit_val(qp_ctx, IRDMA_BYTE_176,
806 FIELD_PREP(IRDMAQPC_SQTPHVAL, qp->sq_tph_val) |
807 FIELD_PREP(IRDMAQPC_RQTPHVAL, qp->rq_tph_val) |
808 FIELD_PREP(IRDMAQPC_QSHANDLE, qp->qs_handle));
809 set_64bit_val(qp_ctx, IRDMA_BYTE_184,
810 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR3, udp->local_ipaddr[3]) |
811 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR2, udp->local_ipaddr[2]));
812 set_64bit_val(qp_ctx, IRDMA_BYTE_192,
813 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR1, udp->local_ipaddr[1]) |
814 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR0, udp->local_ipaddr[0]));
815 set_64bit_val(qp_ctx, IRDMA_BYTE_200,
816 FIELD_PREP(IRDMAQPC_THIGH, roce_info->t_high) |
817 FIELD_PREP(IRDMAQPC_TLOW, roce_info->t_low));
818 set_64bit_val(qp_ctx, IRDMA_BYTE_208,
819 FIELD_PREP(IRDMAQPC_REMENDPOINTIDX, info->rem_endpoint_idx));
820
821 irdma_debug_buf(qp->dev, IRDMA_DEBUG_WQE, "QP_HOST CTX WQE", qp_ctx,
822 IRDMA_QP_CTX_SIZE);
823 }
824
825 /*
826 * irdma_sc_alloc_local_mac_entry - allocate a mac entry @cqp: struct for cqp hw @scratch: u64 saved to be used during
827 * cqp completion @post_sq: flag for cqp db to ring
828 */
829 static int
irdma_sc_alloc_local_mac_entry(struct irdma_sc_cqp * cqp,u64 scratch,bool post_sq)830 irdma_sc_alloc_local_mac_entry(struct irdma_sc_cqp *cqp, u64 scratch,
831 bool post_sq)
832 {
833 __le64 *wqe;
834 u64 hdr;
835
836 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
837 if (!wqe)
838 return -ENOSPC;
839
840 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE,
841 IRDMA_CQP_OP_ALLOCATE_LOC_MAC_TABLE_ENTRY) |
842 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
843
844 irdma_wmb(); /* make sure WQE is written before valid bit is set */
845
846 set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
847
848 irdma_debug_buf(cqp->dev, IRDMA_DEBUG_WQE, "ALLOCATE_LOCAL_MAC WQE",
849 wqe, IRDMA_CQP_WQE_SIZE * 8);
850
851 if (post_sq)
852 irdma_sc_cqp_post_sq(cqp);
853 return 0;
854 }
855
856 /**
857 * irdma_sc_add_local_mac_entry - add mac enry
858 * @cqp: struct for cqp hw
859 * @info:mac addr info
860 * @scratch: u64 saved to be used during cqp completion
861 * @post_sq: flag for cqp db to ring
862 */
863 static int
irdma_sc_add_local_mac_entry(struct irdma_sc_cqp * cqp,struct irdma_local_mac_entry_info * info,u64 scratch,bool post_sq)864 irdma_sc_add_local_mac_entry(struct irdma_sc_cqp *cqp,
865 struct irdma_local_mac_entry_info *info,
866 u64 scratch, bool post_sq)
867 {
868 __le64 *wqe;
869 u64 header;
870
871 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
872 if (!wqe)
873 return -ENOSPC;
874
875 set_64bit_val(wqe, IRDMA_BYTE_32, irdma_mac_to_u64(info->mac_addr));
876
877 header = FIELD_PREP(IRDMA_CQPSQ_MLM_TABLEIDX, info->entry_idx) |
878 FIELD_PREP(IRDMA_CQPSQ_OPCODE,
879 IRDMA_CQP_OP_MANAGE_LOC_MAC_TABLE) |
880 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
881
882 irdma_wmb(); /* make sure WQE is written before valid bit is set */
883
884 set_64bit_val(wqe, IRDMA_BYTE_24, header);
885
886 irdma_debug_buf(cqp->dev, IRDMA_DEBUG_WQE, "ADD_LOCAL_MAC WQE", wqe,
887 IRDMA_CQP_WQE_SIZE * 8);
888
889 if (post_sq)
890 irdma_sc_cqp_post_sq(cqp);
891 return 0;
892 }
893
894 /**
895 * irdma_sc_del_local_mac_entry - cqp wqe to dele local mac
896 * @cqp: struct for cqp hw
897 * @scratch: u64 saved to be used during cqp completion
898 * @entry_idx: index of mac entry
899 * @ignore_ref_count: to force mac adde delete
900 * @post_sq: flag for cqp db to ring
901 */
902 static int
irdma_sc_del_local_mac_entry(struct irdma_sc_cqp * cqp,u64 scratch,u16 entry_idx,u8 ignore_ref_count,bool post_sq)903 irdma_sc_del_local_mac_entry(struct irdma_sc_cqp *cqp, u64 scratch,
904 u16 entry_idx, u8 ignore_ref_count,
905 bool post_sq)
906 {
907 __le64 *wqe;
908 u64 header;
909
910 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
911 if (!wqe)
912 return -ENOSPC;
913 header = FIELD_PREP(IRDMA_CQPSQ_MLM_TABLEIDX, entry_idx) |
914 FIELD_PREP(IRDMA_CQPSQ_OPCODE,
915 IRDMA_CQP_OP_MANAGE_LOC_MAC_TABLE) |
916 FIELD_PREP(IRDMA_CQPSQ_MLM_FREEENTRY, 1) |
917 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity) |
918 FIELD_PREP(IRDMA_CQPSQ_MLM_IGNORE_REF_CNT, ignore_ref_count);
919
920 irdma_wmb(); /* make sure WQE is written before valid bit is set */
921
922 set_64bit_val(wqe, IRDMA_BYTE_24, header);
923
924 irdma_debug_buf(cqp->dev, IRDMA_DEBUG_WQE, "DEL_LOCAL_MAC_IPADDR WQE",
925 wqe, IRDMA_CQP_WQE_SIZE * 8);
926
927 if (post_sq)
928 irdma_sc_cqp_post_sq(cqp);
929 return 0;
930 }
931
932 /**
933 * irdma_sc_qp_setctx - set qp's context
934 * @qp: sc qp
935 * @qp_ctx: context ptr
936 * @info: ctx info
937 */
938 void
irdma_sc_qp_setctx(struct irdma_sc_qp * qp,__le64 * qp_ctx,struct irdma_qp_host_ctx_info * info)939 irdma_sc_qp_setctx(struct irdma_sc_qp *qp, __le64 * qp_ctx,
940 struct irdma_qp_host_ctx_info *info)
941 {
942 struct irdma_iwarp_offload_info *iw;
943 struct irdma_tcp_offload_info *tcp;
944 struct irdma_sc_dev *dev;
945 u8 push_mode_en;
946 u32 push_idx;
947 u64 qw0, qw3, qw7 = 0, qw16 = 0;
948 u64 mac = 0;
949
950 iw = info->iwarp_info;
951 tcp = info->tcp_info;
952 dev = qp->dev;
953 if (iw->rcv_mark_en) {
954 qp->pfpdu.marker_len = 4;
955 qp->pfpdu.rcv_start_seq = tcp->rcv_nxt;
956 }
957 qp->user_pri = info->user_pri;
958 if (qp->push_idx == IRDMA_INVALID_PUSH_PAGE_INDEX) {
959 push_mode_en = 0;
960 push_idx = 0;
961 } else {
962 push_mode_en = 1;
963 push_idx = qp->push_idx;
964 }
965 qw0 = FIELD_PREP(IRDMAQPC_RQWQESIZE, qp->qp_uk.rq_wqe_size) |
966 FIELD_PREP(IRDMAQPC_RCVTPHEN, qp->rcv_tph_en) |
967 FIELD_PREP(IRDMAQPC_XMITTPHEN, qp->xmit_tph_en) |
968 FIELD_PREP(IRDMAQPC_RQTPHEN, qp->rq_tph_en) |
969 FIELD_PREP(IRDMAQPC_SQTPHEN, qp->sq_tph_en) |
970 FIELD_PREP(IRDMAQPC_PPIDX, push_idx) |
971 FIELD_PREP(IRDMAQPC_PMENA, push_mode_en);
972
973 set_64bit_val(qp_ctx, IRDMA_BYTE_8, qp->sq_pa);
974 set_64bit_val(qp_ctx, IRDMA_BYTE_16, qp->rq_pa);
975
976 qw3 = FIELD_PREP(IRDMAQPC_RQSIZE, qp->hw_rq_size) |
977 FIELD_PREP(IRDMAQPC_SQSIZE, qp->hw_sq_size);
978 if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1)
979 qw3 |= FIELD_PREP(IRDMAQPC_GEN1_SRCMACADDRIDX,
980 qp->src_mac_addr_idx);
981 set_64bit_val(qp_ctx, IRDMA_BYTE_136,
982 FIELD_PREP(IRDMAQPC_TXCQNUM, info->send_cq_num) |
983 FIELD_PREP(IRDMAQPC_RXCQNUM, info->rcv_cq_num));
984 set_64bit_val(qp_ctx, IRDMA_BYTE_168,
985 FIELD_PREP(IRDMAQPC_QPCOMPCTX, info->qp_compl_ctx));
986 set_64bit_val(qp_ctx, IRDMA_BYTE_176,
987 FIELD_PREP(IRDMAQPC_SQTPHVAL, qp->sq_tph_val) |
988 FIELD_PREP(IRDMAQPC_RQTPHVAL, qp->rq_tph_val) |
989 FIELD_PREP(IRDMAQPC_QSHANDLE, qp->qs_handle) |
990 FIELD_PREP(IRDMAQPC_EXCEPTION_LAN_QUEUE, qp->ieq_qp));
991 if (info->iwarp_info_valid) {
992 qw0 |= FIELD_PREP(IRDMAQPC_DDP_VER, iw->ddp_ver) |
993 FIELD_PREP(IRDMAQPC_RDMAP_VER, iw->rdmap_ver) |
994 FIELD_PREP(IRDMAQPC_DC_TCP_EN, iw->dctcp_en) |
995 FIELD_PREP(IRDMAQPC_ECN_EN, iw->ecn_en) |
996 FIELD_PREP(IRDMAQPC_IBRDENABLE, iw->ib_rd_en) |
997 FIELD_PREP(IRDMAQPC_PDIDXHI, iw->pd_id >> 16) |
998 FIELD_PREP(IRDMAQPC_ERR_RQ_IDX_VALID,
999 iw->err_rq_idx_valid);
1000 qw7 |= FIELD_PREP(IRDMAQPC_PDIDX, iw->pd_id);
1001 qw16 |= FIELD_PREP(IRDMAQPC_ERR_RQ_IDX, iw->err_rq_idx) |
1002 FIELD_PREP(IRDMAQPC_RTOMIN, iw->rtomin);
1003 set_64bit_val(qp_ctx, IRDMA_BYTE_144,
1004 FIELD_PREP(IRDMAQPC_Q2ADDR, qp->q2_pa >> 8) |
1005 FIELD_PREP(IRDMAQPC_STAT_INDEX, info->stats_idx));
1006
1007 if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2)
1008 mac = FIELD_PREP(IRDMAQPC_MACADDRESS,
1009 irdma_mac_to_u64(iw->mac_addr));
1010
1011 set_64bit_val(qp_ctx, IRDMA_BYTE_152,
1012 mac | FIELD_PREP(IRDMAQPC_LASTBYTESENT, iw->last_byte_sent));
1013 set_64bit_val(qp_ctx, IRDMA_BYTE_160,
1014 FIELD_PREP(IRDMAQPC_ORDSIZE, iw->ord_size) |
1015 FIELD_PREP(IRDMAQPC_IRDSIZE, irdma_sc_get_encoded_ird_size(iw->ird_size)) |
1016 FIELD_PREP(IRDMAQPC_WRRDRSPOK, iw->wr_rdresp_en) |
1017 FIELD_PREP(IRDMAQPC_RDOK, iw->rd_en) |
1018 FIELD_PREP(IRDMAQPC_SNDMARKERS, iw->snd_mark_en) |
1019 FIELD_PREP(IRDMAQPC_FASTREGEN, iw->fast_reg_en) |
1020 FIELD_PREP(IRDMAQPC_PRIVEN, iw->priv_mode_en) |
1021 FIELD_PREP(IRDMAQPC_USESTATSINSTANCE, info->stats_idx_valid) |
1022 FIELD_PREP(IRDMAQPC_IWARPMODE, 1) |
1023 FIELD_PREP(IRDMAQPC_RCVMARKERS, iw->rcv_mark_en) |
1024 FIELD_PREP(IRDMAQPC_ALIGNHDRS, iw->align_hdrs) |
1025 FIELD_PREP(IRDMAQPC_RCVNOMPACRC, iw->rcv_no_mpa_crc) |
1026 FIELD_PREP(IRDMAQPC_RCVMARKOFFSET, iw->rcv_mark_offset) |
1027 FIELD_PREP(IRDMAQPC_SNDMARKOFFSET, iw->snd_mark_offset) |
1028 FIELD_PREP(IRDMAQPC_TIMELYENABLE, iw->timely_en));
1029 }
1030 if (info->tcp_info_valid) {
1031 qw0 |= FIELD_PREP(IRDMAQPC_IPV4, tcp->ipv4) |
1032 FIELD_PREP(IRDMAQPC_NONAGLE, tcp->no_nagle) |
1033 FIELD_PREP(IRDMAQPC_INSERTVLANTAG,
1034 tcp->insert_vlan_tag) |
1035 FIELD_PREP(IRDMAQPC_TIMESTAMP, tcp->time_stamp) |
1036 FIELD_PREP(IRDMAQPC_LIMIT, tcp->cwnd_inc_limit) |
1037 FIELD_PREP(IRDMAQPC_DROPOOOSEG, tcp->drop_ooo_seg) |
1038 FIELD_PREP(IRDMAQPC_DUPACK_THRESH, tcp->dup_ack_thresh);
1039
1040 if (iw->ecn_en || iw->dctcp_en) {
1041 tcp->tos &= ~ECN_CODE_PT_MASK;
1042 tcp->tos |= ECN_CODE_PT_VAL;
1043 }
1044
1045 qw3 |= FIELD_PREP(IRDMAQPC_TTL, tcp->ttl) |
1046 FIELD_PREP(IRDMAQPC_AVOIDSTRETCHACK, tcp->avoid_stretch_ack) |
1047 FIELD_PREP(IRDMAQPC_TOS, tcp->tos) |
1048 FIELD_PREP(IRDMAQPC_SRCPORTNUM, tcp->src_port) |
1049 FIELD_PREP(IRDMAQPC_DESTPORTNUM, tcp->dst_port);
1050 if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) {
1051 qw3 |= FIELD_PREP(IRDMAQPC_GEN1_SRCMACADDRIDX, tcp->src_mac_addr_idx);
1052
1053 qp->src_mac_addr_idx = tcp->src_mac_addr_idx;
1054 }
1055 set_64bit_val(qp_ctx, IRDMA_BYTE_32,
1056 FIELD_PREP(IRDMAQPC_DESTIPADDR2, tcp->dest_ip_addr[2]) |
1057 FIELD_PREP(IRDMAQPC_DESTIPADDR3, tcp->dest_ip_addr[3]));
1058 set_64bit_val(qp_ctx, IRDMA_BYTE_40,
1059 FIELD_PREP(IRDMAQPC_DESTIPADDR0, tcp->dest_ip_addr[0]) |
1060 FIELD_PREP(IRDMAQPC_DESTIPADDR1, tcp->dest_ip_addr[1]));
1061 set_64bit_val(qp_ctx, IRDMA_BYTE_48,
1062 FIELD_PREP(IRDMAQPC_SNDMSS, tcp->snd_mss) |
1063 FIELD_PREP(IRDMAQPC_SYN_RST_HANDLING, tcp->syn_rst_handling) |
1064 FIELD_PREP(IRDMAQPC_VLANTAG, tcp->vlan_tag) |
1065 FIELD_PREP(IRDMAQPC_ARPIDX, tcp->arp_idx));
1066 qw7 |= FIELD_PREP(IRDMAQPC_FLOWLABEL, tcp->flow_label) |
1067 FIELD_PREP(IRDMAQPC_WSCALE, tcp->wscale) |
1068 FIELD_PREP(IRDMAQPC_IGNORE_TCP_OPT,
1069 tcp->ignore_tcp_opt) |
1070 FIELD_PREP(IRDMAQPC_IGNORE_TCP_UNS_OPT,
1071 tcp->ignore_tcp_uns_opt) |
1072 FIELD_PREP(IRDMAQPC_TCPSTATE, tcp->tcp_state) |
1073 FIELD_PREP(IRDMAQPC_RCVSCALE, tcp->rcv_wscale) |
1074 FIELD_PREP(IRDMAQPC_SNDSCALE, tcp->snd_wscale);
1075 set_64bit_val(qp_ctx, IRDMA_BYTE_72,
1076 FIELD_PREP(IRDMAQPC_TIMESTAMP_RECENT, tcp->time_stamp_recent) |
1077 FIELD_PREP(IRDMAQPC_TIMESTAMP_AGE, tcp->time_stamp_age));
1078 set_64bit_val(qp_ctx, IRDMA_BYTE_80,
1079 FIELD_PREP(IRDMAQPC_SNDNXT, tcp->snd_nxt) |
1080 FIELD_PREP(IRDMAQPC_SNDWND, tcp->snd_wnd));
1081 set_64bit_val(qp_ctx, IRDMA_BYTE_88,
1082 FIELD_PREP(IRDMAQPC_RCVNXT, tcp->rcv_nxt) |
1083 FIELD_PREP(IRDMAQPC_RCVWND, tcp->rcv_wnd));
1084 set_64bit_val(qp_ctx, IRDMA_BYTE_96,
1085 FIELD_PREP(IRDMAQPC_SNDMAX, tcp->snd_max) |
1086 FIELD_PREP(IRDMAQPC_SNDUNA, tcp->snd_una));
1087 set_64bit_val(qp_ctx, IRDMA_BYTE_104,
1088 FIELD_PREP(IRDMAQPC_SRTT, tcp->srtt) |
1089 FIELD_PREP(IRDMAQPC_RTTVAR, tcp->rtt_var));
1090 set_64bit_val(qp_ctx, IRDMA_BYTE_112,
1091 FIELD_PREP(IRDMAQPC_SSTHRESH, tcp->ss_thresh) |
1092 FIELD_PREP(IRDMAQPC_CWND, tcp->cwnd));
1093 set_64bit_val(qp_ctx, IRDMA_BYTE_120,
1094 FIELD_PREP(IRDMAQPC_SNDWL1, tcp->snd_wl1) |
1095 FIELD_PREP(IRDMAQPC_SNDWL2, tcp->snd_wl2));
1096 qw16 |= FIELD_PREP(IRDMAQPC_MAXSNDWND, tcp->max_snd_window) |
1097 FIELD_PREP(IRDMAQPC_REXMIT_THRESH, tcp->rexmit_thresh);
1098 set_64bit_val(qp_ctx, IRDMA_BYTE_184,
1099 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR3, tcp->local_ipaddr[3]) |
1100 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR2, tcp->local_ipaddr[2]));
1101 set_64bit_val(qp_ctx, IRDMA_BYTE_192,
1102 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR1, tcp->local_ipaddr[1]) |
1103 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR0, tcp->local_ipaddr[0]));
1104 set_64bit_val(qp_ctx, IRDMA_BYTE_200,
1105 FIELD_PREP(IRDMAQPC_THIGH, iw->t_high) |
1106 FIELD_PREP(IRDMAQPC_TLOW, iw->t_low));
1107 set_64bit_val(qp_ctx, IRDMA_BYTE_208,
1108 FIELD_PREP(IRDMAQPC_REMENDPOINTIDX, info->rem_endpoint_idx));
1109 }
1110
1111 set_64bit_val(qp_ctx, IRDMA_BYTE_0, qw0);
1112 set_64bit_val(qp_ctx, IRDMA_BYTE_24, qw3);
1113 set_64bit_val(qp_ctx, IRDMA_BYTE_56, qw7);
1114 set_64bit_val(qp_ctx, IRDMA_BYTE_128, qw16);
1115
1116 irdma_debug_buf(qp->dev, IRDMA_DEBUG_WQE, "QP_HOST CTX", qp_ctx,
1117 IRDMA_QP_CTX_SIZE);
1118 }
1119
1120 /**
1121 * irdma_sc_alloc_stag - mr stag alloc
1122 * @dev: sc device struct
1123 * @info: stag info
1124 * @scratch: u64 saved to be used during cqp completion
1125 * @post_sq: flag for cqp db to ring
1126 */
1127 static int
irdma_sc_alloc_stag(struct irdma_sc_dev * dev,struct irdma_allocate_stag_info * info,u64 scratch,bool post_sq)1128 irdma_sc_alloc_stag(struct irdma_sc_dev *dev,
1129 struct irdma_allocate_stag_info *info,
1130 u64 scratch, bool post_sq)
1131 {
1132 __le64 *wqe;
1133 struct irdma_sc_cqp *cqp;
1134 u64 hdr;
1135 enum irdma_page_size page_size;
1136
1137 if (!info->total_len && !info->all_memory)
1138 return -EINVAL;
1139
1140 if (info->page_size == 0x40000000)
1141 page_size = IRDMA_PAGE_SIZE_1G;
1142 else if (info->page_size == 0x200000)
1143 page_size = IRDMA_PAGE_SIZE_2M;
1144 else
1145 page_size = IRDMA_PAGE_SIZE_4K;
1146
1147 cqp = dev->cqp;
1148 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
1149 if (!wqe)
1150 return -ENOSPC;
1151
1152 set_64bit_val(wqe, IRDMA_BYTE_8,
1153 FLD_LS_64(dev, info->pd_id, IRDMA_CQPSQ_STAG_PDID) |
1154 FIELD_PREP(IRDMA_CQPSQ_STAG_STAGLEN, info->total_len));
1155 set_64bit_val(wqe, IRDMA_BYTE_16,
1156 FIELD_PREP(IRDMA_CQPSQ_STAG_IDX, info->stag_idx));
1157 set_64bit_val(wqe, IRDMA_BYTE_40,
1158 FIELD_PREP(IRDMA_CQPSQ_STAG_HMCFNIDX, info->hmc_fcn_index));
1159
1160 if (info->chunk_size)
1161 set_64bit_val(wqe, IRDMA_BYTE_48,
1162 FIELD_PREP(IRDMA_CQPSQ_STAG_FIRSTPMPBLIDX, info->first_pm_pbl_idx));
1163
1164 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_ALLOC_STAG) |
1165 FIELD_PREP(IRDMA_CQPSQ_STAG_MR, 1) |
1166 FIELD_PREP(IRDMA_CQPSQ_STAG_ARIGHTS, info->access_rights) |
1167 FIELD_PREP(IRDMA_CQPSQ_STAG_LPBLSIZE, info->chunk_size) |
1168 FIELD_PREP(IRDMA_CQPSQ_STAG_HPAGESIZE, page_size) |
1169 FIELD_PREP(IRDMA_CQPSQ_STAG_REMACCENABLED, info->remote_access) |
1170 FIELD_PREP(IRDMA_CQPSQ_STAG_USEHMCFNIDX, info->use_hmc_fcn_index) |
1171 FIELD_PREP(IRDMA_CQPSQ_STAG_USEPFRID, info->use_pf_rid) |
1172 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
1173 irdma_wmb(); /* make sure WQE is written before valid bit is set */
1174
1175 set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
1176
1177 irdma_debug_buf(dev, IRDMA_DEBUG_WQE, "ALLOC_STAG WQE", wqe,
1178 IRDMA_CQP_WQE_SIZE * 8);
1179 if (post_sq)
1180 irdma_sc_cqp_post_sq(cqp);
1181
1182 return 0;
1183 }
1184
1185 /**
1186 * irdma_sc_mr_reg_non_shared - non-shared mr registration
1187 * @dev: sc device struct
1188 * @info: mr info
1189 * @scratch: u64 saved to be used during cqp completion
1190 * @post_sq: flag for cqp db to ring
1191 */
1192 static int
irdma_sc_mr_reg_non_shared(struct irdma_sc_dev * dev,struct irdma_reg_ns_stag_info * info,u64 scratch,bool post_sq)1193 irdma_sc_mr_reg_non_shared(struct irdma_sc_dev *dev,
1194 struct irdma_reg_ns_stag_info *info,
1195 u64 scratch, bool post_sq)
1196 {
1197 __le64 *wqe;
1198 u64 fbo;
1199 struct irdma_sc_cqp *cqp;
1200 u64 hdr;
1201 u32 pble_obj_cnt;
1202 bool remote_access;
1203 u8 addr_type;
1204 enum irdma_page_size page_size;
1205
1206 if (!info->total_len && !info->all_memory)
1207 return -EINVAL;
1208
1209 if (info->page_size == 0x40000000)
1210 page_size = IRDMA_PAGE_SIZE_1G;
1211 else if (info->page_size == 0x200000)
1212 page_size = IRDMA_PAGE_SIZE_2M;
1213 else if (info->page_size == 0x1000)
1214 page_size = IRDMA_PAGE_SIZE_4K;
1215 else
1216 return -EINVAL;
1217
1218 if (info->access_rights & (IRDMA_ACCESS_FLAGS_REMOTEREAD_ONLY |
1219 IRDMA_ACCESS_FLAGS_REMOTEWRITE_ONLY))
1220 remote_access = true;
1221 else
1222 remote_access = false;
1223
1224 pble_obj_cnt = dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt;
1225 if (info->chunk_size && info->first_pm_pbl_index >= pble_obj_cnt)
1226 return -EINVAL;
1227
1228 cqp = dev->cqp;
1229 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
1230 if (!wqe)
1231 return -ENOSPC;
1232 fbo = info->va & (info->page_size - 1);
1233
1234 set_64bit_val(wqe, IRDMA_BYTE_0,
1235 (info->addr_type == IRDMA_ADDR_TYPE_VA_BASED ?
1236 info->va : fbo));
1237 set_64bit_val(wqe, IRDMA_BYTE_8,
1238 FIELD_PREP(IRDMA_CQPSQ_STAG_STAGLEN, info->total_len) |
1239 FLD_LS_64(dev, info->pd_id, IRDMA_CQPSQ_STAG_PDID));
1240 set_64bit_val(wqe, IRDMA_BYTE_16,
1241 FIELD_PREP(IRDMA_CQPSQ_STAG_KEY, info->stag_key) |
1242 FIELD_PREP(IRDMA_CQPSQ_STAG_IDX, info->stag_idx));
1243 if (!info->chunk_size)
1244 set_64bit_val(wqe, IRDMA_BYTE_32, info->reg_addr_pa);
1245 else
1246 set_64bit_val(wqe, IRDMA_BYTE_48,
1247 FIELD_PREP(IRDMA_CQPSQ_STAG_FIRSTPMPBLIDX, info->first_pm_pbl_index));
1248
1249 set_64bit_val(wqe, IRDMA_BYTE_40, info->hmc_fcn_index);
1250
1251 addr_type = (info->addr_type == IRDMA_ADDR_TYPE_VA_BASED) ? 1 : 0;
1252 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_REG_MR) |
1253 FIELD_PREP(IRDMA_CQPSQ_STAG_MR, 1) |
1254 FIELD_PREP(IRDMA_CQPSQ_STAG_LPBLSIZE, info->chunk_size) |
1255 FIELD_PREP(IRDMA_CQPSQ_STAG_HPAGESIZE, page_size) |
1256 FIELD_PREP(IRDMA_CQPSQ_STAG_ARIGHTS, info->access_rights) |
1257 FIELD_PREP(IRDMA_CQPSQ_STAG_REMACCENABLED, remote_access) |
1258 FIELD_PREP(IRDMA_CQPSQ_STAG_VABASEDTO, addr_type) |
1259 FIELD_PREP(IRDMA_CQPSQ_STAG_USEHMCFNIDX, info->use_hmc_fcn_index) |
1260 FIELD_PREP(IRDMA_CQPSQ_STAG_USEPFRID, info->use_pf_rid) |
1261 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
1262 irdma_wmb(); /* make sure WQE is written before valid bit is set */
1263
1264 set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
1265
1266 irdma_debug_buf(dev, IRDMA_DEBUG_WQE, "MR_REG_NS WQE", wqe,
1267 IRDMA_CQP_WQE_SIZE * 8);
1268 if (post_sq)
1269 irdma_sc_cqp_post_sq(cqp);
1270
1271 return 0;
1272 }
1273
1274 /**
1275 * irdma_sc_dealloc_stag - deallocate stag
1276 * @dev: sc device struct
1277 * @info: dealloc stag info
1278 * @scratch: u64 saved to be used during cqp completion
1279 * @post_sq: flag for cqp db to ring
1280 */
1281 static int
irdma_sc_dealloc_stag(struct irdma_sc_dev * dev,struct irdma_dealloc_stag_info * info,u64 scratch,bool post_sq)1282 irdma_sc_dealloc_stag(struct irdma_sc_dev *dev,
1283 struct irdma_dealloc_stag_info *info,
1284 u64 scratch, bool post_sq)
1285 {
1286 u64 hdr;
1287 __le64 *wqe;
1288 struct irdma_sc_cqp *cqp;
1289
1290 cqp = dev->cqp;
1291 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
1292 if (!wqe)
1293 return -ENOSPC;
1294
1295 set_64bit_val(wqe, IRDMA_BYTE_8,
1296 FLD_LS_64(dev, info->pd_id, IRDMA_CQPSQ_STAG_PDID));
1297 set_64bit_val(wqe, IRDMA_BYTE_16,
1298 FIELD_PREP(IRDMA_CQPSQ_STAG_IDX, info->stag_idx));
1299
1300 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DEALLOC_STAG) |
1301 FIELD_PREP(IRDMA_CQPSQ_STAG_MR, info->mr) |
1302 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
1303 irdma_wmb(); /* make sure WQE is written before valid bit is set */
1304
1305 set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
1306
1307 irdma_debug_buf(dev, IRDMA_DEBUG_WQE, "DEALLOC_STAG WQE", wqe,
1308 IRDMA_CQP_WQE_SIZE * 8);
1309 if (post_sq)
1310 irdma_sc_cqp_post_sq(cqp);
1311
1312 return 0;
1313 }
1314
1315 /**
1316 * irdma_sc_mw_alloc - mw allocate
1317 * @dev: sc device struct
1318 * @info: memory window allocation information
1319 * @scratch: u64 saved to be used during cqp completion
1320 * @post_sq: flag for cqp db to ring
1321 */
1322 static int
irdma_sc_mw_alloc(struct irdma_sc_dev * dev,struct irdma_mw_alloc_info * info,u64 scratch,bool post_sq)1323 irdma_sc_mw_alloc(struct irdma_sc_dev *dev,
1324 struct irdma_mw_alloc_info *info, u64 scratch,
1325 bool post_sq)
1326 {
1327 u64 hdr;
1328 struct irdma_sc_cqp *cqp;
1329 __le64 *wqe;
1330
1331 cqp = dev->cqp;
1332 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
1333 if (!wqe)
1334 return -ENOSPC;
1335
1336 set_64bit_val(wqe, IRDMA_BYTE_8,
1337 FLD_LS_64(dev, info->pd_id, IRDMA_CQPSQ_STAG_PDID));
1338 set_64bit_val(wqe, IRDMA_BYTE_16,
1339 FIELD_PREP(IRDMA_CQPSQ_STAG_IDX, info->mw_stag_index));
1340
1341 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_ALLOC_STAG) |
1342 FIELD_PREP(IRDMA_CQPSQ_STAG_MWTYPE, info->mw_wide) |
1343 FIELD_PREP(IRDMA_CQPSQ_STAG_MW1_BIND_DONT_VLDT_KEY,
1344 info->mw1_bind_dont_vldt_key) |
1345 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
1346 irdma_wmb(); /* make sure WQE is written before valid bit is set */
1347
1348 set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
1349
1350 irdma_debug_buf(dev, IRDMA_DEBUG_WQE, "MW_ALLOC WQE", wqe,
1351 IRDMA_CQP_WQE_SIZE * 8);
1352 if (post_sq)
1353 irdma_sc_cqp_post_sq(cqp);
1354
1355 return 0;
1356 }
1357
1358 /**
1359 * irdma_sc_mr_fast_register - Posts RDMA fast register mr WR to iwarp qp
1360 * @qp: sc qp struct
1361 * @info: fast mr info
1362 * @post_sq: flag for cqp db to ring
1363 */
1364 int
irdma_sc_mr_fast_register(struct irdma_sc_qp * qp,struct irdma_fast_reg_stag_info * info,bool post_sq)1365 irdma_sc_mr_fast_register(struct irdma_sc_qp *qp,
1366 struct irdma_fast_reg_stag_info *info,
1367 bool post_sq)
1368 {
1369 u64 temp, hdr;
1370 __le64 *wqe;
1371 u32 wqe_idx;
1372 u16 quanta = IRDMA_QP_WQE_MIN_QUANTA;
1373 enum irdma_page_size page_size;
1374 struct irdma_post_sq_info sq_info = {0};
1375
1376 if (info->page_size == 0x40000000)
1377 page_size = IRDMA_PAGE_SIZE_1G;
1378 else if (info->page_size == 0x200000)
1379 page_size = IRDMA_PAGE_SIZE_2M;
1380 else
1381 page_size = IRDMA_PAGE_SIZE_4K;
1382
1383 sq_info.wr_id = info->wr_id;
1384 sq_info.signaled = info->signaled;
1385 sq_info.push_wqe = info->push_wqe;
1386
1387 wqe = irdma_qp_get_next_send_wqe(&qp->qp_uk, &wqe_idx, &quanta, 0, &sq_info);
1388 if (!wqe)
1389 return -ENOSPC;
1390
1391 qp->qp_uk.sq_wrtrk_array[wqe_idx].signaled = info->signaled;
1392 irdma_debug(qp->dev, IRDMA_DEBUG_MR,
1393 "wr_id[%llxh] wqe_idx[%04d] location[%p]\n",
1394 (unsigned long long)info->wr_id, wqe_idx,
1395 &qp->qp_uk.sq_wrtrk_array[wqe_idx].wrid);
1396
1397 temp = (info->addr_type == IRDMA_ADDR_TYPE_VA_BASED) ?
1398 (uintptr_t)info->va : info->fbo;
1399 set_64bit_val(wqe, IRDMA_BYTE_0, temp);
1400
1401 temp = FIELD_GET(IRDMAQPSQ_FIRSTPMPBLIDXHI,
1402 info->first_pm_pbl_index >> 16);
1403 set_64bit_val(wqe, IRDMA_BYTE_8,
1404 FIELD_PREP(IRDMAQPSQ_FIRSTPMPBLIDXHI, temp) |
1405 FIELD_PREP(IRDMAQPSQ_PBLADDR, info->reg_addr_pa >> IRDMA_HW_PAGE_SHIFT));
1406 set_64bit_val(wqe, IRDMA_BYTE_16,
1407 info->total_len |
1408 FIELD_PREP(IRDMAQPSQ_FIRSTPMPBLIDXLO, info->first_pm_pbl_index));
1409
1410 hdr = FIELD_PREP(IRDMAQPSQ_STAGKEY, info->stag_key) |
1411 FIELD_PREP(IRDMAQPSQ_STAGINDEX, info->stag_idx) |
1412 FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_FAST_REGISTER) |
1413 FIELD_PREP(IRDMAQPSQ_LPBLSIZE, info->chunk_size) |
1414 FIELD_PREP(IRDMAQPSQ_HPAGESIZE, page_size) |
1415 FIELD_PREP(IRDMAQPSQ_STAGRIGHTS, info->access_rights) |
1416 FIELD_PREP(IRDMAQPSQ_VABASEDTO, info->addr_type) |
1417 FIELD_PREP(IRDMAQPSQ_PUSHWQE, (sq_info.push_wqe ? 1 : 0)) |
1418 FIELD_PREP(IRDMAQPSQ_READFENCE, info->read_fence) |
1419 FIELD_PREP(IRDMAQPSQ_LOCALFENCE, info->local_fence) |
1420 FIELD_PREP(IRDMAQPSQ_SIGCOMPL, info->signaled) |
1421 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity);
1422 irdma_wmb(); /* make sure WQE is written before valid bit is set */
1423
1424 set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
1425
1426 irdma_debug_buf(qp->dev, IRDMA_DEBUG_WQE, "FAST_REG WQE", wqe,
1427 IRDMA_QP_WQE_MIN_SIZE);
1428 if (sq_info.push_wqe)
1429 irdma_qp_push_wqe(&qp->qp_uk, wqe, quanta, wqe_idx, post_sq);
1430 else if (post_sq)
1431 irdma_uk_qp_post_wr(&qp->qp_uk);
1432
1433 return 0;
1434 }
1435
1436 /**
1437 * irdma_sc_gen_rts_ae - request AE generated after RTS
1438 * @qp: sc qp struct
1439 */
1440 static void
irdma_sc_gen_rts_ae(struct irdma_sc_qp * qp)1441 irdma_sc_gen_rts_ae(struct irdma_sc_qp *qp)
1442 {
1443 __le64 *wqe;
1444 u64 hdr;
1445 struct irdma_qp_uk *qp_uk;
1446
1447 qp_uk = &qp->qp_uk;
1448
1449 wqe = qp_uk->sq_base[1].elem;
1450
1451 hdr = FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_NOP) |
1452 FIELD_PREP(IRDMAQPSQ_LOCALFENCE, 1) |
1453 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity);
1454 irdma_wmb(); /* make sure WQE is written before valid bit is set */
1455
1456 set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
1457 irdma_debug_buf(qp->dev, IRDMA_DEBUG_QP, "NOP W/LOCAL FENCE WQE", wqe,
1458 IRDMA_QP_WQE_MIN_SIZE);
1459
1460 wqe = qp_uk->sq_base[2].elem;
1461 hdr = FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_GEN_RTS_AE) |
1462 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity);
1463 irdma_wmb(); /* make sure WQE is written before valid bit is set */
1464
1465 set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
1466 irdma_debug_buf(qp->dev, IRDMA_DEBUG_QP, "CONN EST WQE", wqe,
1467 IRDMA_QP_WQE_MIN_SIZE);
1468 if (qp->qp_uk.start_wqe_idx) {
1469 wqe = qp_uk->sq_base[3].elem;
1470 hdr = FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_NOP) |
1471 FIELD_PREP(IRDMAQPSQ_LOCALFENCE, 1) |
1472 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity);
1473 irdma_wmb(); /* make sure WQE is written before valid bit is set */
1474
1475 set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
1476 }
1477 }
1478
1479 /**
1480 * irdma_sc_send_lsmm - send last streaming mode message
1481 * @qp: sc qp struct
1482 * @lsmm_buf: buffer with lsmm message
1483 * @size: size of lsmm buffer
1484 * @stag: stag of lsmm buffer
1485 */
1486 void
irdma_sc_send_lsmm(struct irdma_sc_qp * qp,void * lsmm_buf,u32 size,irdma_stag stag)1487 irdma_sc_send_lsmm(struct irdma_sc_qp *qp, void *lsmm_buf, u32 size,
1488 irdma_stag stag)
1489 {
1490 __le64 *wqe;
1491 u64 hdr;
1492 struct irdma_qp_uk *qp_uk;
1493
1494 qp_uk = &qp->qp_uk;
1495 wqe = qp_uk->sq_base->elem;
1496
1497 set_64bit_val(wqe, IRDMA_BYTE_0, (uintptr_t)lsmm_buf);
1498 if (qp->qp_uk.uk_attrs->hw_rev == IRDMA_GEN_1) {
1499 set_64bit_val(wqe, IRDMA_BYTE_8,
1500 FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_LEN, size) |
1501 FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_STAG, stag));
1502 } else {
1503 set_64bit_val(wqe, IRDMA_BYTE_8,
1504 FIELD_PREP(IRDMAQPSQ_FRAG_LEN, size) |
1505 FIELD_PREP(IRDMAQPSQ_FRAG_STAG, stag) |
1506 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity));
1507 }
1508 set_64bit_val(wqe, IRDMA_BYTE_16, 0);
1509
1510 hdr = FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_RDMA_SEND) |
1511 FIELD_PREP(IRDMAQPSQ_STREAMMODE, 1) |
1512 FIELD_PREP(IRDMAQPSQ_WAITFORRCVPDU, 1) |
1513 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity);
1514 irdma_wmb(); /* make sure WQE is written before valid bit is set */
1515
1516 set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
1517
1518 irdma_debug_buf(qp->dev, IRDMA_DEBUG_WQE, "SEND_LSMM WQE", wqe,
1519 IRDMA_QP_WQE_MIN_SIZE);
1520
1521 if (qp->dev->hw_attrs.uk_attrs.feature_flags & IRDMA_FEATURE_RTS_AE)
1522 irdma_sc_gen_rts_ae(qp);
1523 }
1524
1525 /**
1526 * irdma_sc_send_rtt - send last read0 or write0
1527 * @qp: sc qp struct
1528 * @read: Do read0 or write0
1529 */
1530 void
irdma_sc_send_rtt(struct irdma_sc_qp * qp,bool read)1531 irdma_sc_send_rtt(struct irdma_sc_qp *qp, bool read)
1532 {
1533 __le64 *wqe;
1534 u64 hdr;
1535 struct irdma_qp_uk *qp_uk;
1536
1537 qp_uk = &qp->qp_uk;
1538 wqe = qp_uk->sq_base->elem;
1539
1540 set_64bit_val(wqe, IRDMA_BYTE_0, 0);
1541 set_64bit_val(wqe, IRDMA_BYTE_16, 0);
1542 if (read) {
1543 if (qp->qp_uk.uk_attrs->hw_rev == IRDMA_GEN_1) {
1544 set_64bit_val(wqe, IRDMA_BYTE_8,
1545 FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_STAG, 0xabcd));
1546 } else {
1547 set_64bit_val(wqe, IRDMA_BYTE_8,
1548 (u64)0xabcd | FIELD_PREP(IRDMAQPSQ_VALID,
1549 qp->qp_uk.swqe_polarity));
1550 }
1551 hdr = FIELD_PREP(IRDMAQPSQ_REMSTAG, 0x1234) |
1552 FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_RDMA_READ) |
1553 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity);
1554
1555 } else {
1556 if (qp->qp_uk.uk_attrs->hw_rev == IRDMA_GEN_1) {
1557 set_64bit_val(wqe, IRDMA_BYTE_8, 0);
1558 } else {
1559 set_64bit_val(wqe, IRDMA_BYTE_8,
1560 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity));
1561 }
1562 hdr = FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_RDMA_WRITE) |
1563 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity);
1564 }
1565
1566 irdma_wmb(); /* make sure WQE is written before valid bit is set */
1567
1568 set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
1569
1570 irdma_debug_buf(qp->dev, IRDMA_DEBUG_WQE, "RTR WQE", wqe,
1571 IRDMA_QP_WQE_MIN_SIZE);
1572
1573 if (qp->dev->hw_attrs.uk_attrs.feature_flags & IRDMA_FEATURE_RTS_AE)
1574 irdma_sc_gen_rts_ae(qp);
1575 }
1576
1577 /**
1578 * irdma_iwarp_opcode - determine if incoming is rdma layer
1579 * @info: aeq info for the packet
1580 * @pkt: packet for error
1581 */
irdma_iwarp_opcode(struct irdma_aeqe_info * info,u8 * pkt)1582 static u32 irdma_iwarp_opcode(struct irdma_aeqe_info *info, u8 *pkt){
1583 BE16 *mpa;
1584 u32 opcode = 0xffffffff;
1585
1586 if (info->q2_data_written) {
1587 mpa = (BE16 *) pkt;
1588 opcode = IRDMA_NTOHS(mpa[1]) & 0xf;
1589 }
1590
1591 return opcode;
1592 }
1593
1594 /**
1595 * irdma_locate_mpa - return pointer to mpa in the pkt
1596 * @pkt: packet with data
1597 */
irdma_locate_mpa(u8 * pkt)1598 static u8 *irdma_locate_mpa(u8 *pkt) {
1599 /* skip over ethernet header */
1600 pkt += IRDMA_MAC_HLEN;
1601
1602 /* Skip over IP and TCP headers */
1603 pkt += 4 * (pkt[0] & 0x0f);
1604 pkt += 4 * ((pkt[12] >> 4) & 0x0f);
1605
1606 return pkt;
1607 }
1608
1609 /**
1610 * irdma_bld_termhdr_ctrl - setup terminate hdr control fields
1611 * @qp: sc qp ptr for pkt
1612 * @hdr: term hdr
1613 * @opcode: flush opcode for termhdr
1614 * @layer_etype: error layer + error type
1615 * @err: error cod ein the header
1616 */
1617 static void
irdma_bld_termhdr_ctrl(struct irdma_sc_qp * qp,struct irdma_terminate_hdr * hdr,enum irdma_flush_opcode opcode,u8 layer_etype,u8 err)1618 irdma_bld_termhdr_ctrl(struct irdma_sc_qp *qp,
1619 struct irdma_terminate_hdr *hdr,
1620 enum irdma_flush_opcode opcode,
1621 u8 layer_etype, u8 err)
1622 {
1623 qp->flush_code = opcode;
1624 hdr->layer_etype = layer_etype;
1625 hdr->error_code = err;
1626 }
1627
1628 /**
1629 * irdma_bld_termhdr_ddp_rdma - setup ddp and rdma hdrs in terminate hdr
1630 * @pkt: ptr to mpa in offending pkt
1631 * @hdr: term hdr
1632 * @copy_len: offending pkt length to be copied to term hdr
1633 * @is_tagged: DDP tagged or untagged
1634 */
1635 static void
irdma_bld_termhdr_ddp_rdma(u8 * pkt,struct irdma_terminate_hdr * hdr,int * copy_len,u8 * is_tagged)1636 irdma_bld_termhdr_ddp_rdma(u8 *pkt, struct irdma_terminate_hdr *hdr,
1637 int *copy_len, u8 *is_tagged)
1638 {
1639 u16 ddp_seg_len;
1640
1641 ddp_seg_len = IRDMA_NTOHS(*(BE16 *) pkt);
1642 if (ddp_seg_len) {
1643 *copy_len = 2;
1644 hdr->hdrct = DDP_LEN_FLAG;
1645 if (pkt[2] & 0x80) {
1646 *is_tagged = 1;
1647 if (ddp_seg_len >= TERM_DDP_LEN_TAGGED) {
1648 *copy_len += TERM_DDP_LEN_TAGGED;
1649 hdr->hdrct |= DDP_HDR_FLAG;
1650 }
1651 } else {
1652 if (ddp_seg_len >= TERM_DDP_LEN_UNTAGGED) {
1653 *copy_len += TERM_DDP_LEN_UNTAGGED;
1654 hdr->hdrct |= DDP_HDR_FLAG;
1655 }
1656 if (ddp_seg_len >= (TERM_DDP_LEN_UNTAGGED + TERM_RDMA_LEN) &&
1657 ((pkt[3] & RDMA_OPCODE_M) == RDMA_READ_REQ_OPCODE)) {
1658 *copy_len += TERM_RDMA_LEN;
1659 hdr->hdrct |= RDMA_HDR_FLAG;
1660 }
1661 }
1662 }
1663 }
1664
1665 /**
1666 * irdma_bld_terminate_hdr - build terminate message header
1667 * @qp: qp associated with received terminate AE
1668 * @info: the struct contiaing AE information
1669 */
1670 static int
irdma_bld_terminate_hdr(struct irdma_sc_qp * qp,struct irdma_aeqe_info * info)1671 irdma_bld_terminate_hdr(struct irdma_sc_qp *qp,
1672 struct irdma_aeqe_info *info)
1673 {
1674 u8 *pkt = qp->q2_buf + Q2_BAD_FRAME_OFFSET;
1675 int copy_len = 0;
1676 u8 is_tagged = 0;
1677 u32 opcode;
1678 struct irdma_terminate_hdr *termhdr;
1679
1680 termhdr = (struct irdma_terminate_hdr *)qp->q2_buf;
1681 memset(termhdr, 0, Q2_BAD_FRAME_OFFSET);
1682
1683 if (info->q2_data_written) {
1684 pkt = irdma_locate_mpa(pkt);
1685 irdma_bld_termhdr_ddp_rdma(pkt, termhdr, ©_len, &is_tagged);
1686 }
1687
1688 opcode = irdma_iwarp_opcode(info, pkt);
1689 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC;
1690 qp->sq_flush_code = info->sq;
1691 qp->rq_flush_code = info->rq;
1692
1693 switch (info->ae_id) {
1694 case IRDMA_AE_AMP_UNALLOCATED_STAG:
1695 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR;
1696 if (opcode == IRDMA_OP_TYPE_RDMA_WRITE)
1697 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_PROT_ERR,
1698 (LAYER_DDP << 4) | DDP_TAGGED_BUF,
1699 DDP_TAGGED_INV_STAG);
1700 else
1701 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR,
1702 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT,
1703 RDMAP_INV_STAG);
1704 break;
1705 case IRDMA_AE_AMP_BOUNDS_VIOLATION:
1706 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR;
1707 if (info->q2_data_written)
1708 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_PROT_ERR,
1709 (LAYER_DDP << 4) | DDP_TAGGED_BUF,
1710 DDP_TAGGED_BOUNDS);
1711 else
1712 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR,
1713 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT,
1714 RDMAP_INV_BOUNDS);
1715 break;
1716 case IRDMA_AE_AMP_BAD_PD:
1717 switch (opcode) {
1718 case IRDMA_OP_TYPE_RDMA_WRITE:
1719 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_PROT_ERR,
1720 (LAYER_DDP << 4) | DDP_TAGGED_BUF,
1721 DDP_TAGGED_UNASSOC_STAG);
1722 break;
1723 case IRDMA_OP_TYPE_SEND_INV:
1724 case IRDMA_OP_TYPE_SEND_SOL_INV:
1725 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR,
1726 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT,
1727 RDMAP_CANT_INV_STAG);
1728 break;
1729 default:
1730 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR,
1731 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT,
1732 RDMAP_UNASSOC_STAG);
1733 }
1734 break;
1735 case IRDMA_AE_AMP_INVALID_STAG:
1736 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR;
1737 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR,
1738 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT,
1739 RDMAP_INV_STAG);
1740 break;
1741 case IRDMA_AE_AMP_BAD_QP:
1742 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_LOC_QP_OP_ERR,
1743 (LAYER_DDP << 4) | DDP_UNTAGGED_BUF,
1744 DDP_UNTAGGED_INV_QN);
1745 break;
1746 case IRDMA_AE_AMP_BAD_STAG_KEY:
1747 case IRDMA_AE_AMP_BAD_STAG_INDEX:
1748 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR;
1749 switch (opcode) {
1750 case IRDMA_OP_TYPE_SEND_INV:
1751 case IRDMA_OP_TYPE_SEND_SOL_INV:
1752 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_OP_ERR,
1753 (LAYER_RDMA << 4) | RDMAP_REMOTE_OP,
1754 RDMAP_CANT_INV_STAG);
1755 break;
1756 default:
1757 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR,
1758 (LAYER_RDMA << 4) | RDMAP_REMOTE_OP,
1759 RDMAP_INV_STAG);
1760 }
1761 break;
1762 case IRDMA_AE_AMP_RIGHTS_VIOLATION:
1763 case IRDMA_AE_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS:
1764 case IRDMA_AE_PRIV_OPERATION_DENIED:
1765 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR;
1766 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR,
1767 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT,
1768 RDMAP_ACCESS);
1769 break;
1770 case IRDMA_AE_AMP_TO_WRAP:
1771 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR;
1772 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR,
1773 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT,
1774 RDMAP_TO_WRAP);
1775 break;
1776 case IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR:
1777 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_GENERAL_ERR,
1778 (LAYER_MPA << 4) | DDP_LLP, MPA_CRC);
1779 break;
1780 case IRDMA_AE_LLP_SEGMENT_TOO_SMALL:
1781 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_LOC_LEN_ERR,
1782 (LAYER_DDP << 4) | DDP_CATASTROPHIC,
1783 DDP_CATASTROPHIC_LOCAL);
1784 break;
1785 case IRDMA_AE_LCE_QP_CATASTROPHIC:
1786 case IRDMA_AE_DDP_NO_L_BIT:
1787 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_FATAL_ERR,
1788 (LAYER_DDP << 4) | DDP_CATASTROPHIC,
1789 DDP_CATASTROPHIC_LOCAL);
1790 break;
1791 case IRDMA_AE_DDP_INVALID_MSN_GAP_IN_MSN:
1792 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_GENERAL_ERR,
1793 (LAYER_DDP << 4) | DDP_UNTAGGED_BUF,
1794 DDP_UNTAGGED_INV_MSN_RANGE);
1795 break;
1796 case IRDMA_AE_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER:
1797 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR;
1798 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_LOC_LEN_ERR,
1799 (LAYER_DDP << 4) | DDP_UNTAGGED_BUF,
1800 DDP_UNTAGGED_INV_TOO_LONG);
1801 break;
1802 case IRDMA_AE_DDP_UBE_INVALID_DDP_VERSION:
1803 if (is_tagged)
1804 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_GENERAL_ERR,
1805 (LAYER_DDP << 4) | DDP_TAGGED_BUF,
1806 DDP_TAGGED_INV_DDP_VER);
1807 else
1808 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_GENERAL_ERR,
1809 (LAYER_DDP << 4) | DDP_UNTAGGED_BUF,
1810 DDP_UNTAGGED_INV_DDP_VER);
1811 break;
1812 case IRDMA_AE_DDP_UBE_INVALID_MO:
1813 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_GENERAL_ERR,
1814 (LAYER_DDP << 4) | DDP_UNTAGGED_BUF,
1815 DDP_UNTAGGED_INV_MO);
1816 break;
1817 case IRDMA_AE_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE:
1818 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_OP_ERR,
1819 (LAYER_DDP << 4) | DDP_UNTAGGED_BUF,
1820 DDP_UNTAGGED_INV_MSN_NO_BUF);
1821 break;
1822 case IRDMA_AE_DDP_UBE_INVALID_QN:
1823 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_GENERAL_ERR,
1824 (LAYER_DDP << 4) | DDP_UNTAGGED_BUF,
1825 DDP_UNTAGGED_INV_QN);
1826 break;
1827 case IRDMA_AE_RDMAP_ROE_INVALID_RDMAP_VERSION:
1828 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_GENERAL_ERR,
1829 (LAYER_RDMA << 4) | RDMAP_REMOTE_OP,
1830 RDMAP_INV_RDMAP_VER);
1831 break;
1832 default:
1833 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_FATAL_ERR,
1834 (LAYER_RDMA << 4) | RDMAP_REMOTE_OP,
1835 RDMAP_UNSPECIFIED);
1836 break;
1837 }
1838
1839 if (copy_len)
1840 irdma_memcpy(termhdr + 1, pkt, copy_len);
1841
1842 return sizeof(*termhdr) + copy_len;
1843 }
1844
1845 /**
1846 * irdma_terminate_send_fin() - Send fin for terminate message
1847 * @qp: qp associated with received terminate AE
1848 */
1849 void
irdma_terminate_send_fin(struct irdma_sc_qp * qp)1850 irdma_terminate_send_fin(struct irdma_sc_qp *qp)
1851 {
1852 irdma_term_modify_qp(qp, IRDMA_QP_STATE_TERMINATE,
1853 IRDMAQP_TERM_SEND_FIN_ONLY, 0);
1854 }
1855
1856 /**
1857 * irdma_terminate_connection() - Bad AE and send terminate to remote QP
1858 * @qp: qp associated with received terminate AE
1859 * @info: the struct contiaing AE information
1860 */
1861 void
irdma_terminate_connection(struct irdma_sc_qp * qp,struct irdma_aeqe_info * info)1862 irdma_terminate_connection(struct irdma_sc_qp *qp,
1863 struct irdma_aeqe_info *info)
1864 {
1865 u8 termlen = 0;
1866
1867 if (qp->term_flags & IRDMA_TERM_SENT)
1868 return;
1869
1870 termlen = irdma_bld_terminate_hdr(qp, info);
1871 irdma_terminate_start_timer(qp);
1872 qp->term_flags |= IRDMA_TERM_SENT;
1873 irdma_term_modify_qp(qp, IRDMA_QP_STATE_TERMINATE,
1874 IRDMAQP_TERM_SEND_TERM_ONLY, termlen);
1875 }
1876
1877 /**
1878 * irdma_terminate_received - handle terminate received AE
1879 * @qp: qp associated with received terminate AE
1880 * @info: the struct contiaing AE information
1881 */
1882 void
irdma_terminate_received(struct irdma_sc_qp * qp,struct irdma_aeqe_info * info)1883 irdma_terminate_received(struct irdma_sc_qp *qp,
1884 struct irdma_aeqe_info *info)
1885 {
1886 u8 *pkt = qp->q2_buf + Q2_BAD_FRAME_OFFSET;
1887 BE32 *mpa;
1888 u8 ddp_ctl;
1889 u8 rdma_ctl;
1890 u16 aeq_id = 0;
1891 struct irdma_terminate_hdr *termhdr;
1892
1893 mpa = (BE32 *) irdma_locate_mpa(pkt);
1894 if (info->q2_data_written) {
1895 /* did not validate the frame - do it now */
1896 ddp_ctl = (ntohl(mpa[0]) >> 8) & 0xff;
1897 rdma_ctl = ntohl(mpa[0]) & 0xff;
1898 if ((ddp_ctl & 0xc0) != 0x40)
1899 aeq_id = IRDMA_AE_LCE_QP_CATASTROPHIC;
1900 else if ((ddp_ctl & 0x03) != 1)
1901 aeq_id = IRDMA_AE_DDP_UBE_INVALID_DDP_VERSION;
1902 else if (ntohl(mpa[2]) != 2)
1903 aeq_id = IRDMA_AE_DDP_UBE_INVALID_QN;
1904 else if (ntohl(mpa[3]) != 1)
1905 aeq_id = IRDMA_AE_DDP_INVALID_MSN_GAP_IN_MSN;
1906 else if (ntohl(mpa[4]) != 0)
1907 aeq_id = IRDMA_AE_DDP_UBE_INVALID_MO;
1908 else if ((rdma_ctl & 0xc0) != 0x40)
1909 aeq_id = IRDMA_AE_RDMAP_ROE_INVALID_RDMAP_VERSION;
1910
1911 info->ae_id = aeq_id;
1912 if (info->ae_id) {
1913 /* Bad terminate recvd - send back a terminate */
1914 irdma_terminate_connection(qp, info);
1915 return;
1916 }
1917 }
1918
1919 qp->term_flags |= IRDMA_TERM_RCVD;
1920 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC;
1921 termhdr = (struct irdma_terminate_hdr *)&mpa[5];
1922 if (termhdr->layer_etype == RDMAP_REMOTE_PROT ||
1923 termhdr->layer_etype == RDMAP_REMOTE_OP) {
1924 irdma_terminate_done(qp, 0);
1925 } else {
1926 irdma_terminate_start_timer(qp);
1927 irdma_terminate_send_fin(qp);
1928 }
1929 }
1930
1931 static int
irdma_null_ws_add(struct irdma_sc_vsi * vsi,u8 user_pri)1932 irdma_null_ws_add(struct irdma_sc_vsi *vsi, u8 user_pri)
1933 {
1934 return 0;
1935 }
1936
1937 static void
irdma_null_ws_remove(struct irdma_sc_vsi * vsi,u8 user_pri)1938 irdma_null_ws_remove(struct irdma_sc_vsi *vsi, u8 user_pri)
1939 {
1940 /* do nothing */
1941 }
1942
1943 static void
irdma_null_ws_reset(struct irdma_sc_vsi * vsi)1944 irdma_null_ws_reset(struct irdma_sc_vsi *vsi)
1945 {
1946 /* do nothing */
1947 }
1948
1949 /**
1950 * irdma_sc_vsi_init - Init the vsi structure
1951 * @vsi: pointer to vsi structure to initialize
1952 * @info: the info used to initialize the vsi struct
1953 */
1954 void
irdma_sc_vsi_init(struct irdma_sc_vsi * vsi,struct irdma_vsi_init_info * info)1955 irdma_sc_vsi_init(struct irdma_sc_vsi *vsi,
1956 struct irdma_vsi_init_info *info)
1957 {
1958 u8 i;
1959
1960 vsi->dev = info->dev;
1961 vsi->back_vsi = info->back_vsi;
1962 vsi->register_qset = info->register_qset;
1963 vsi->unregister_qset = info->unregister_qset;
1964 vsi->mtu = info->params->mtu;
1965 vsi->exception_lan_q = info->exception_lan_q;
1966 vsi->vsi_idx = info->pf_data_vsi_num;
1967
1968 irdma_set_qos_info(vsi, info->params);
1969 for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++) {
1970 mutex_init(&vsi->qos[i].qos_mutex);
1971 INIT_LIST_HEAD(&vsi->qos[i].qplist);
1972 }
1973 if (vsi->register_qset) {
1974 vsi->dev->ws_add = irdma_ws_add;
1975 vsi->dev->ws_remove = irdma_ws_remove;
1976 vsi->dev->ws_reset = irdma_ws_reset;
1977 } else {
1978 vsi->dev->ws_add = irdma_null_ws_add;
1979 vsi->dev->ws_remove = irdma_null_ws_remove;
1980 vsi->dev->ws_reset = irdma_null_ws_reset;
1981 }
1982 }
1983
1984 /**
1985 * irdma_get_stats_idx - Return stats index
1986 * @vsi: pointer to the vsi
1987 */
irdma_get_stats_idx(struct irdma_sc_vsi * vsi)1988 static u16 irdma_get_stats_idx(struct irdma_sc_vsi *vsi){
1989 struct irdma_stats_inst_info stats_info = {0};
1990 struct irdma_sc_dev *dev = vsi->dev;
1991
1992 if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) {
1993 if (!irdma_cqp_stats_inst_cmd(vsi, IRDMA_OP_STATS_ALLOCATE,
1994 &stats_info))
1995 return stats_info.stats_idx;
1996 }
1997
1998 return IRDMA_INVALID_STATS_IDX;
1999 }
2000
2001 /**
2002 * irdma_vsi_stats_init - Initialize the vsi statistics
2003 * @vsi: pointer to the vsi structure
2004 * @info: The info structure used for initialization
2005 */
2006 int
irdma_vsi_stats_init(struct irdma_sc_vsi * vsi,struct irdma_vsi_stats_info * info)2007 irdma_vsi_stats_init(struct irdma_sc_vsi *vsi,
2008 struct irdma_vsi_stats_info *info)
2009 {
2010 struct irdma_dma_mem *stats_buff_mem;
2011
2012 vsi->pestat = info->pestat;
2013 vsi->pestat->hw = vsi->dev->hw;
2014 vsi->pestat->vsi = vsi;
2015
2016 stats_buff_mem = &vsi->pestat->gather_info.stats_buff_mem;
2017 stats_buff_mem->size = IRDMA_GATHER_STATS_BUF_SIZE * 2;
2018 stats_buff_mem->va = irdma_allocate_dma_mem(vsi->pestat->hw,
2019 stats_buff_mem,
2020 stats_buff_mem->size, 1);
2021 if (!stats_buff_mem->va)
2022 return -ENOMEM;
2023
2024 vsi->pestat->gather_info.gather_stats_va = stats_buff_mem->va;
2025 vsi->pestat->gather_info.last_gather_stats_va =
2026 (void *)((uintptr_t)stats_buff_mem->va +
2027 IRDMA_GATHER_STATS_BUF_SIZE);
2028
2029 irdma_hw_stats_start_timer(vsi);
2030
2031 /* when stat allocation is not required default to fcn_id. */
2032 vsi->stats_idx = info->fcn_id;
2033 if (info->alloc_stats_inst) {
2034 u16 stats_idx = irdma_get_stats_idx(vsi);
2035
2036 if (stats_idx != IRDMA_INVALID_STATS_IDX) {
2037 vsi->stats_inst_alloc = true;
2038 vsi->stats_idx = stats_idx;
2039 vsi->pestat->gather_info.use_stats_inst = true;
2040 vsi->pestat->gather_info.stats_inst_index = stats_idx;
2041 }
2042 }
2043
2044 return 0;
2045 }
2046
2047 /**
2048 * irdma_vsi_stats_free - Free the vsi stats
2049 * @vsi: pointer to the vsi structure
2050 */
2051 void
irdma_vsi_stats_free(struct irdma_sc_vsi * vsi)2052 irdma_vsi_stats_free(struct irdma_sc_vsi *vsi)
2053 {
2054 struct irdma_stats_inst_info stats_info = {0};
2055 struct irdma_sc_dev *dev = vsi->dev;
2056
2057 if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) {
2058 if (vsi->stats_inst_alloc) {
2059 stats_info.stats_idx = vsi->stats_idx;
2060 irdma_cqp_stats_inst_cmd(vsi, IRDMA_OP_STATS_FREE,
2061 &stats_info);
2062 }
2063 }
2064
2065 if (!vsi->pestat)
2066 return;
2067
2068 irdma_hw_stats_stop_timer(vsi);
2069 irdma_free_dma_mem(vsi->pestat->hw,
2070 &vsi->pestat->gather_info.stats_buff_mem);
2071 }
2072
2073 /**
2074 * irdma_get_encoded_wqe_size - given wq size, returns hardware encoded size
2075 * @wqsize: size of the wq (sq, rq) to encoded_size
2076 * @queue_type: queue type selected for the calculation algorithm
2077 */
2078 u8
irdma_get_encoded_wqe_size(u32 wqsize,enum irdma_queue_type queue_type)2079 irdma_get_encoded_wqe_size(u32 wqsize, enum irdma_queue_type queue_type)
2080 {
2081 u8 encoded_size = 0;
2082
2083 /*
2084 * cqp sq's hw coded value starts from 1 for size of 4 while it starts from 0 for qp' wq's.
2085 */
2086 if (queue_type == IRDMA_QUEUE_TYPE_CQP)
2087 encoded_size = 1;
2088 wqsize >>= 2;
2089 while (wqsize >>= 1)
2090 encoded_size++;
2091
2092 return encoded_size;
2093 }
2094
2095 /**
2096 * irdma_sc_gather_stats - collect the statistics
2097 * @cqp: struct for cqp hw
2098 * @info: gather stats info structure
2099 * @scratch: u64 saved to be used during cqp completion
2100 */
2101 static int
irdma_sc_gather_stats(struct irdma_sc_cqp * cqp,struct irdma_stats_gather_info * info,u64 scratch)2102 irdma_sc_gather_stats(struct irdma_sc_cqp *cqp,
2103 struct irdma_stats_gather_info *info,
2104 u64 scratch)
2105 {
2106 __le64 *wqe;
2107 u64 temp;
2108
2109 if (info->stats_buff_mem.size < IRDMA_GATHER_STATS_BUF_SIZE)
2110 return -ENOSPC;
2111
2112 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
2113 if (!wqe)
2114 return -ENOSPC;
2115
2116 set_64bit_val(wqe, IRDMA_BYTE_40,
2117 FIELD_PREP(IRDMA_CQPSQ_STATS_HMC_FCN_INDEX, info->hmc_fcn_index));
2118 set_64bit_val(wqe, IRDMA_BYTE_32, info->stats_buff_mem.pa);
2119
2120 temp = FIELD_PREP(IRDMA_CQPSQ_STATS_WQEVALID, cqp->polarity) |
2121 FIELD_PREP(IRDMA_CQPSQ_STATS_USE_INST, info->use_stats_inst) |
2122 FIELD_PREP(IRDMA_CQPSQ_STATS_INST_INDEX,
2123 info->stats_inst_index) |
2124 FIELD_PREP(IRDMA_CQPSQ_STATS_USE_HMC_FCN_INDEX,
2125 info->use_hmc_fcn_index) |
2126 FIELD_PREP(IRDMA_CQPSQ_STATS_OP, IRDMA_CQP_OP_GATHER_STATS);
2127 irdma_wmb(); /* make sure WQE is written before valid bit is set */
2128
2129 set_64bit_val(wqe, IRDMA_BYTE_24, temp);
2130
2131 irdma_debug_buf(cqp->dev, IRDMA_DEBUG_STATS, "GATHER_STATS WQE", wqe,
2132 IRDMA_CQP_WQE_SIZE * 8);
2133
2134 irdma_sc_cqp_post_sq(cqp);
2135
2136 return 0;
2137 }
2138
2139 /**
2140 * irdma_sc_manage_stats_inst - allocate or free stats instance
2141 * @cqp: struct for cqp hw
2142 * @info: stats info structure
2143 * @alloc: alloc vs. delete flag
2144 * @scratch: u64 saved to be used during cqp completion
2145 */
2146 static int
irdma_sc_manage_stats_inst(struct irdma_sc_cqp * cqp,struct irdma_stats_inst_info * info,bool alloc,u64 scratch)2147 irdma_sc_manage_stats_inst(struct irdma_sc_cqp *cqp,
2148 struct irdma_stats_inst_info *info,
2149 bool alloc, u64 scratch)
2150 {
2151 __le64 *wqe;
2152 u64 temp;
2153
2154 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
2155 if (!wqe)
2156 return -ENOSPC;
2157
2158 set_64bit_val(wqe, IRDMA_BYTE_40,
2159 FIELD_PREP(IRDMA_CQPSQ_STATS_HMC_FCN_INDEX, info->hmc_fn_id));
2160 temp = FIELD_PREP(IRDMA_CQPSQ_STATS_WQEVALID, cqp->polarity) |
2161 FIELD_PREP(IRDMA_CQPSQ_STATS_ALLOC_INST, alloc) |
2162 FIELD_PREP(IRDMA_CQPSQ_STATS_USE_HMC_FCN_INDEX,
2163 info->use_hmc_fcn_index) |
2164 FIELD_PREP(IRDMA_CQPSQ_STATS_INST_INDEX, info->stats_idx) |
2165 FIELD_PREP(IRDMA_CQPSQ_STATS_OP, IRDMA_CQP_OP_MANAGE_STATS);
2166
2167 irdma_wmb(); /* make sure WQE is written before valid bit is set */
2168
2169 set_64bit_val(wqe, IRDMA_BYTE_24, temp);
2170
2171 irdma_debug_buf(cqp->dev, IRDMA_DEBUG_WQE, "MANAGE_STATS WQE", wqe,
2172 IRDMA_CQP_WQE_SIZE * 8);
2173
2174 irdma_sc_cqp_post_sq(cqp);
2175 return 0;
2176 }
2177
2178 /**
2179 * irdma_sc_set_up_map - set the up map table
2180 * @cqp: struct for cqp hw
2181 * @info: User priority map info
2182 * @scratch: u64 saved to be used during cqp completion
2183 */
2184 static int
irdma_sc_set_up_map(struct irdma_sc_cqp * cqp,struct irdma_up_info * info,u64 scratch)2185 irdma_sc_set_up_map(struct irdma_sc_cqp *cqp,
2186 struct irdma_up_info *info, u64 scratch)
2187 {
2188 __le64 *wqe;
2189 u64 temp = 0;
2190 int i;
2191
2192 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
2193 if (!wqe)
2194 return -ENOSPC;
2195
2196 for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++)
2197 temp |= (u64)info->map[i] << (i * 8);
2198
2199 set_64bit_val(wqe, IRDMA_BYTE_0, temp);
2200 set_64bit_val(wqe, IRDMA_BYTE_40,
2201 FIELD_PREP(IRDMA_CQPSQ_UP_CNPOVERRIDE, info->cnp_up_override) |
2202 FIELD_PREP(IRDMA_CQPSQ_UP_HMCFCNIDX, info->hmc_fcn_idx));
2203
2204 temp = FIELD_PREP(IRDMA_CQPSQ_UP_WQEVALID, cqp->polarity) |
2205 FIELD_PREP(IRDMA_CQPSQ_UP_USEVLAN, info->use_vlan) |
2206 FIELD_PREP(IRDMA_CQPSQ_UP_USEOVERRIDE,
2207 info->use_cnp_up_override) |
2208 FIELD_PREP(IRDMA_CQPSQ_UP_OP, IRDMA_CQP_OP_UP_MAP);
2209 irdma_wmb(); /* make sure WQE is written before valid bit is set */
2210
2211 set_64bit_val(wqe, IRDMA_BYTE_24, temp);
2212
2213 irdma_debug_buf(cqp->dev, IRDMA_DEBUG_WQE, "UPMAP WQE", wqe,
2214 IRDMA_CQP_WQE_SIZE * 8);
2215 irdma_sc_cqp_post_sq(cqp);
2216
2217 return 0;
2218 }
2219
2220 /**
2221 * irdma_sc_manage_ws_node - create/modify/destroy WS node
2222 * @cqp: struct for cqp hw
2223 * @info: node info structure
2224 * @node_op: 0 for add 1 for modify, 2 for delete
2225 * @scratch: u64 saved to be used during cqp completion
2226 */
2227 static int
irdma_sc_manage_ws_node(struct irdma_sc_cqp * cqp,struct irdma_ws_node_info * info,enum irdma_ws_node_op node_op,u64 scratch)2228 irdma_sc_manage_ws_node(struct irdma_sc_cqp *cqp,
2229 struct irdma_ws_node_info *info,
2230 enum irdma_ws_node_op node_op, u64 scratch)
2231 {
2232 __le64 *wqe;
2233 u64 temp = 0;
2234
2235 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
2236 if (!wqe)
2237 return -ENOSPC;
2238
2239 set_64bit_val(wqe, IRDMA_BYTE_32,
2240 FIELD_PREP(IRDMA_CQPSQ_WS_VSI, info->vsi) |
2241 FIELD_PREP(IRDMA_CQPSQ_WS_WEIGHT, info->weight));
2242
2243 temp = FIELD_PREP(IRDMA_CQPSQ_WS_WQEVALID, cqp->polarity) |
2244 FIELD_PREP(IRDMA_CQPSQ_WS_NODEOP, node_op) |
2245 FIELD_PREP(IRDMA_CQPSQ_WS_ENABLENODE, info->enable) |
2246 FIELD_PREP(IRDMA_CQPSQ_WS_NODETYPE, info->type_leaf) |
2247 FIELD_PREP(IRDMA_CQPSQ_WS_PRIOTYPE, info->prio_type) |
2248 FIELD_PREP(IRDMA_CQPSQ_WS_TC, info->tc) |
2249 FIELD_PREP(IRDMA_CQPSQ_WS_OP, IRDMA_CQP_OP_WORK_SCHED_NODE) |
2250 FIELD_PREP(IRDMA_CQPSQ_WS_PARENTID, info->parent_id) |
2251 FIELD_PREP(IRDMA_CQPSQ_WS_NODEID, info->id);
2252 irdma_wmb(); /* make sure WQE is written before valid bit is set */
2253
2254 set_64bit_val(wqe, IRDMA_BYTE_24, temp);
2255
2256 irdma_debug_buf(cqp->dev, IRDMA_DEBUG_WQE, "MANAGE_WS WQE", wqe,
2257 IRDMA_CQP_WQE_SIZE * 8);
2258 irdma_sc_cqp_post_sq(cqp);
2259
2260 return 0;
2261 }
2262
2263 /**
2264 * irdma_sc_qp_flush_wqes - flush qp's wqe
2265 * @qp: sc qp
2266 * @info: dlush information
2267 * @scratch: u64 saved to be used during cqp completion
2268 * @post_sq: flag for cqp db to ring
2269 */
2270 int
irdma_sc_qp_flush_wqes(struct irdma_sc_qp * qp,struct irdma_qp_flush_info * info,u64 scratch,bool post_sq)2271 irdma_sc_qp_flush_wqes(struct irdma_sc_qp *qp,
2272 struct irdma_qp_flush_info *info, u64 scratch,
2273 bool post_sq)
2274 {
2275 u64 temp = 0;
2276 __le64 *wqe;
2277 struct irdma_sc_cqp *cqp;
2278 u64 hdr;
2279 bool flush_sq = false, flush_rq = false;
2280
2281 if (info->rq && !qp->flush_rq)
2282 flush_rq = true;
2283 if (info->sq && !qp->flush_sq)
2284 flush_sq = true;
2285 qp->flush_sq |= flush_sq;
2286 qp->flush_rq |= flush_rq;
2287
2288 if (!flush_sq && !flush_rq) {
2289 irdma_debug(qp->dev, IRDMA_DEBUG_CQP,
2290 "Additional flush request ignored for qp %x\n",
2291 qp->qp_uk.qp_id);
2292 return -EALREADY;
2293 }
2294
2295 cqp = qp->pd->dev->cqp;
2296 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
2297 if (!wqe)
2298 return -ENOSPC;
2299
2300 if (info->userflushcode) {
2301 if (flush_rq)
2302 temp |= FIELD_PREP(IRDMA_CQPSQ_FWQE_RQMNERR,
2303 info->rq_minor_code) |
2304 FIELD_PREP(IRDMA_CQPSQ_FWQE_RQMJERR,
2305 info->rq_major_code);
2306 if (flush_sq)
2307 temp |= FIELD_PREP(IRDMA_CQPSQ_FWQE_SQMNERR,
2308 info->sq_minor_code) |
2309 FIELD_PREP(IRDMA_CQPSQ_FWQE_SQMJERR,
2310 info->sq_major_code);
2311 }
2312 set_64bit_val(wqe, IRDMA_BYTE_16, temp);
2313
2314 temp = (info->generate_ae) ?
2315 info->ae_code | FIELD_PREP(IRDMA_CQPSQ_FWQE_AESOURCE,
2316 info->ae_src) : 0;
2317 set_64bit_val(wqe, IRDMA_BYTE_8, temp);
2318 hdr = qp->qp_uk.qp_id |
2319 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_FLUSH_WQES) |
2320 FIELD_PREP(IRDMA_CQPSQ_FWQE_GENERATE_AE, info->generate_ae) |
2321 FIELD_PREP(IRDMA_CQPSQ_FWQE_USERFLCODE, info->userflushcode) |
2322 FIELD_PREP(IRDMA_CQPSQ_FWQE_FLUSHSQ, flush_sq) |
2323 FIELD_PREP(IRDMA_CQPSQ_FWQE_FLUSHRQ, flush_rq) |
2324 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
2325 irdma_wmb(); /* make sure WQE is written before valid bit is set */
2326
2327 set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
2328
2329 irdma_debug_buf(cqp->dev, IRDMA_DEBUG_WQE, "QP_FLUSH WQE", wqe,
2330 IRDMA_CQP_WQE_SIZE * 8);
2331 if (post_sq)
2332 irdma_sc_cqp_post_sq(cqp);
2333
2334 return 0;
2335 }
2336
2337 /**
2338 * irdma_sc_gen_ae - generate AE, uses flush WQE CQP OP
2339 * @qp: sc qp
2340 * @info: gen ae information
2341 * @scratch: u64 saved to be used during cqp completion
2342 * @post_sq: flag for cqp db to ring
2343 */
2344 static int
irdma_sc_gen_ae(struct irdma_sc_qp * qp,struct irdma_gen_ae_info * info,u64 scratch,bool post_sq)2345 irdma_sc_gen_ae(struct irdma_sc_qp *qp,
2346 struct irdma_gen_ae_info *info, u64 scratch,
2347 bool post_sq)
2348 {
2349 u64 temp;
2350 __le64 *wqe;
2351 struct irdma_sc_cqp *cqp;
2352 u64 hdr;
2353
2354 cqp = qp->pd->dev->cqp;
2355 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
2356 if (!wqe)
2357 return -ENOSPC;
2358
2359 temp = info->ae_code | FIELD_PREP(IRDMA_CQPSQ_FWQE_AESOURCE,
2360 info->ae_src);
2361 set_64bit_val(wqe, IRDMA_BYTE_8, temp);
2362
2363 hdr = qp->qp_uk.qp_id | FIELD_PREP(IRDMA_CQPSQ_OPCODE,
2364 IRDMA_CQP_OP_GEN_AE) |
2365 FIELD_PREP(IRDMA_CQPSQ_FWQE_GENERATE_AE, 1) |
2366 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
2367 irdma_wmb(); /* make sure WQE is written before valid bit is set */
2368
2369 set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
2370
2371 irdma_debug_buf(cqp->dev, IRDMA_DEBUG_WQE, "GEN_AE WQE", wqe,
2372 IRDMA_CQP_WQE_SIZE * 8);
2373 if (post_sq)
2374 irdma_sc_cqp_post_sq(cqp);
2375
2376 return 0;
2377 }
2378
2379 /*** irdma_sc_qp_upload_context - upload qp's context
2380 * @dev: sc device struct
2381 * @info: upload context info ptr for return
2382 * @scratch: u64 saved to be used during cqp completion
2383 * @post_sq: flag for cqp db to ring
2384 */
2385 static int
irdma_sc_qp_upload_context(struct irdma_sc_dev * dev,struct irdma_upload_context_info * info,u64 scratch,bool post_sq)2386 irdma_sc_qp_upload_context(struct irdma_sc_dev *dev,
2387 struct irdma_upload_context_info *info,
2388 u64 scratch, bool post_sq)
2389 {
2390 __le64 *wqe;
2391 struct irdma_sc_cqp *cqp;
2392 u64 hdr;
2393
2394 cqp = dev->cqp;
2395 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
2396 if (!wqe)
2397 return -ENOSPC;
2398
2399 set_64bit_val(wqe, IRDMA_BYTE_16, info->buf_pa);
2400
2401 hdr = FIELD_PREP(IRDMA_CQPSQ_UCTX_QPID, info->qp_id) |
2402 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_UPLOAD_CONTEXT) |
2403 FIELD_PREP(IRDMA_CQPSQ_UCTX_QPTYPE, info->qp_type) |
2404 FIELD_PREP(IRDMA_CQPSQ_UCTX_RAWFORMAT, info->raw_format) |
2405 FIELD_PREP(IRDMA_CQPSQ_UCTX_FREEZEQP, info->freeze_qp) |
2406 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
2407 irdma_wmb(); /* make sure WQE is written before valid bit is set */
2408
2409 set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
2410
2411 irdma_debug_buf(dev, IRDMA_DEBUG_WQE, "QP_UPLOAD_CTX WQE", wqe,
2412 IRDMA_CQP_WQE_SIZE * 8);
2413 if (post_sq)
2414 irdma_sc_cqp_post_sq(cqp);
2415
2416 return 0;
2417 }
2418
2419 /**
2420 * irdma_sc_manage_push_page - Handle push page
2421 * @cqp: struct for cqp hw
2422 * @info: push page info
2423 * @scratch: u64 saved to be used during cqp completion
2424 * @post_sq: flag for cqp db to ring
2425 */
2426 static int
irdma_sc_manage_push_page(struct irdma_sc_cqp * cqp,struct irdma_cqp_manage_push_page_info * info,u64 scratch,bool post_sq)2427 irdma_sc_manage_push_page(struct irdma_sc_cqp *cqp,
2428 struct irdma_cqp_manage_push_page_info *info,
2429 u64 scratch, bool post_sq)
2430 {
2431 __le64 *wqe;
2432 u64 hdr;
2433
2434 if (info->free_page &&
2435 info->push_idx >= cqp->dev->hw_attrs.max_hw_device_pages)
2436 return -EINVAL;
2437
2438 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
2439 if (!wqe)
2440 return -ENOSPC;
2441
2442 set_64bit_val(wqe, IRDMA_BYTE_16, info->qs_handle);
2443 hdr = FIELD_PREP(IRDMA_CQPSQ_MPP_PPIDX, info->push_idx) |
2444 FIELD_PREP(IRDMA_CQPSQ_MPP_PPTYPE, info->push_page_type) |
2445 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MANAGE_PUSH_PAGES) |
2446 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity) |
2447 FIELD_PREP(IRDMA_CQPSQ_MPP_FREE_PAGE, info->free_page);
2448 irdma_wmb(); /* make sure WQE is written before valid bit is set */
2449
2450 set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
2451
2452 irdma_debug_buf(cqp->dev, IRDMA_DEBUG_WQE, "MANAGE_PUSH_PAGES WQE", wqe,
2453 IRDMA_CQP_WQE_SIZE * 8);
2454 if (post_sq)
2455 irdma_sc_cqp_post_sq(cqp);
2456
2457 return 0;
2458 }
2459
2460 /**
2461 * irdma_sc_suspend_qp - suspend qp for param change
2462 * @cqp: struct for cqp hw
2463 * @qp: sc qp struct
2464 * @scratch: u64 saved to be used during cqp completion
2465 */
2466 static int
irdma_sc_suspend_qp(struct irdma_sc_cqp * cqp,struct irdma_sc_qp * qp,u64 scratch)2467 irdma_sc_suspend_qp(struct irdma_sc_cqp *cqp, struct irdma_sc_qp *qp,
2468 u64 scratch)
2469 {
2470 u64 hdr;
2471 __le64 *wqe;
2472
2473 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
2474 if (!wqe)
2475 return -ENOSPC;
2476
2477 hdr = FIELD_PREP(IRDMA_CQPSQ_SUSPENDQP_QPID, qp->qp_uk.qp_id) |
2478 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_SUSPEND_QP) |
2479 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
2480 irdma_wmb(); /* make sure WQE is written before valid bit is set */
2481
2482 set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
2483
2484 irdma_debug_buf(cqp->dev, IRDMA_DEBUG_WQE, "SUSPEND_QP WQE", wqe,
2485 IRDMA_CQP_WQE_SIZE * 8);
2486 irdma_sc_cqp_post_sq(cqp);
2487
2488 return 0;
2489 }
2490
2491 /**
2492 * irdma_sc_resume_qp - resume qp after suspend
2493 * @cqp: struct for cqp hw
2494 * @qp: sc qp struct
2495 * @scratch: u64 saved to be used during cqp completion
2496 */
2497 static int
irdma_sc_resume_qp(struct irdma_sc_cqp * cqp,struct irdma_sc_qp * qp,u64 scratch)2498 irdma_sc_resume_qp(struct irdma_sc_cqp *cqp, struct irdma_sc_qp *qp,
2499 u64 scratch)
2500 {
2501 u64 hdr;
2502 __le64 *wqe;
2503
2504 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
2505 if (!wqe)
2506 return -ENOSPC;
2507
2508 set_64bit_val(wqe, IRDMA_BYTE_16,
2509 FIELD_PREP(IRDMA_CQPSQ_RESUMEQP_QSHANDLE, qp->qs_handle));
2510
2511 hdr = FIELD_PREP(IRDMA_CQPSQ_RESUMEQP_QPID, qp->qp_uk.qp_id) |
2512 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_RESUME_QP) |
2513 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
2514 irdma_wmb(); /* make sure WQE is written before valid bit is set */
2515
2516 set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
2517
2518 irdma_debug_buf(cqp->dev, IRDMA_DEBUG_WQE, "RESUME_QP WQE", wqe,
2519 IRDMA_CQP_WQE_SIZE * 8);
2520 irdma_sc_cqp_post_sq(cqp);
2521
2522 return 0;
2523 }
2524
2525 /**
2526 * irdma_sc_cq_ack - acknowledge completion q
2527 * @cq: cq struct
2528 */
2529 static inline void
irdma_sc_cq_ack(struct irdma_sc_cq * cq)2530 irdma_sc_cq_ack(struct irdma_sc_cq *cq)
2531 {
2532 db_wr32(cq->cq_uk.cq_id, cq->cq_uk.cq_ack_db);
2533 }
2534
2535 /**
2536 * irdma_sc_cq_init - initialize completion q
2537 * @cq: cq struct
2538 * @info: cq initialization info
2539 */
2540 int
irdma_sc_cq_init(struct irdma_sc_cq * cq,struct irdma_cq_init_info * info)2541 irdma_sc_cq_init(struct irdma_sc_cq *cq, struct irdma_cq_init_info *info)
2542 {
2543 int ret_code;
2544 u32 pble_obj_cnt;
2545
2546 pble_obj_cnt = info->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt;
2547 if (info->virtual_map && info->first_pm_pbl_idx >= pble_obj_cnt)
2548 return -EINVAL;
2549
2550 cq->cq_pa = info->cq_base_pa;
2551 cq->dev = info->dev;
2552 cq->ceq_id = info->ceq_id;
2553 info->cq_uk_init_info.cqe_alloc_db = cq->dev->cq_arm_db;
2554 info->cq_uk_init_info.cq_ack_db = cq->dev->cq_ack_db;
2555 ret_code = irdma_uk_cq_init(&cq->cq_uk, &info->cq_uk_init_info);
2556 if (ret_code)
2557 return ret_code;
2558
2559 cq->virtual_map = info->virtual_map;
2560 cq->pbl_chunk_size = info->pbl_chunk_size;
2561 cq->ceqe_mask = info->ceqe_mask;
2562 cq->cq_type = (info->type) ? info->type : IRDMA_CQ_TYPE_IWARP;
2563 cq->shadow_area_pa = info->shadow_area_pa;
2564 cq->shadow_read_threshold = info->shadow_read_threshold;
2565 cq->ceq_id_valid = info->ceq_id_valid;
2566 cq->tph_en = info->tph_en;
2567 cq->tph_val = info->tph_val;
2568 cq->first_pm_pbl_idx = info->first_pm_pbl_idx;
2569 cq->vsi = info->vsi;
2570
2571 return 0;
2572 }
2573
2574 /**
2575 * irdma_sc_cq_create - create completion q
2576 * @cq: cq struct
2577 * @scratch: u64 saved to be used during cqp completion
2578 * @check_overflow: flag for overflow check
2579 * @post_sq: flag for cqp db to ring
2580 */
2581 static int
irdma_sc_cq_create(struct irdma_sc_cq * cq,u64 scratch,bool check_overflow,bool post_sq)2582 irdma_sc_cq_create(struct irdma_sc_cq *cq, u64 scratch,
2583 bool check_overflow, bool post_sq)
2584 {
2585 __le64 *wqe;
2586 struct irdma_sc_cqp *cqp;
2587 u64 hdr;
2588 struct irdma_sc_ceq *ceq;
2589 int ret_code = 0;
2590
2591 cqp = cq->dev->cqp;
2592 if (cq->cq_uk.cq_id > (cqp->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].max_cnt - 1))
2593 return -EINVAL;
2594
2595 if (cq->ceq_id > (cq->dev->hmc_fpm_misc.max_ceqs - 1))
2596 return -EINVAL;
2597
2598 ceq = cq->dev->ceq[cq->ceq_id];
2599 if (ceq && ceq->reg_cq) {
2600 ret_code = irdma_sc_add_cq_ctx(ceq, cq);
2601 if (ret_code)
2602 return ret_code;
2603 }
2604
2605 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
2606 if (!wqe) {
2607 if (ceq && ceq->reg_cq)
2608 irdma_sc_remove_cq_ctx(ceq, cq);
2609 return -ENOSPC;
2610 }
2611
2612 set_64bit_val(wqe, IRDMA_BYTE_0, cq->cq_uk.cq_size);
2613 set_64bit_val(wqe, IRDMA_BYTE_8, RS_64_1(cq, 1));
2614 set_64bit_val(wqe, IRDMA_BYTE_16,
2615 FIELD_PREP(IRDMA_CQPSQ_CQ_SHADOW_READ_THRESHOLD,
2616 cq->shadow_read_threshold));
2617 set_64bit_val(wqe, IRDMA_BYTE_32, cq->virtual_map ? 0 : cq->cq_pa);
2618 set_64bit_val(wqe, IRDMA_BYTE_40, cq->shadow_area_pa);
2619 set_64bit_val(wqe, IRDMA_BYTE_48,
2620 FIELD_PREP(IRDMA_CQPSQ_CQ_FIRSTPMPBLIDX,
2621 cq->virtual_map ? cq->first_pm_pbl_idx : 0));
2622 set_64bit_val(wqe, IRDMA_BYTE_56,
2623 FIELD_PREP(IRDMA_CQPSQ_TPHVAL, cq->tph_val) |
2624 FIELD_PREP(IRDMA_CQPSQ_VSIIDX, cq->vsi->vsi_idx));
2625 hdr = FLD_LS_64(cq->dev, cq->cq_uk.cq_id, IRDMA_CQPSQ_CQ_CQID) |
2626 FLD_LS_64(cq->dev, cq->ceq_id_valid ? cq->ceq_id : 0,
2627 IRDMA_CQPSQ_CQ_CEQID) |
2628 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_CREATE_CQ) |
2629 FIELD_PREP(IRDMA_CQPSQ_CQ_LPBLSIZE, cq->pbl_chunk_size) |
2630 FIELD_PREP(IRDMA_CQPSQ_CQ_CHKOVERFLOW, check_overflow) |
2631 FIELD_PREP(IRDMA_CQPSQ_CQ_VIRTMAP, cq->virtual_map) |
2632 FIELD_PREP(IRDMA_CQPSQ_CQ_ENCEQEMASK, cq->ceqe_mask) |
2633 FIELD_PREP(IRDMA_CQPSQ_CQ_CEQIDVALID, cq->ceq_id_valid) |
2634 FIELD_PREP(IRDMA_CQPSQ_TPHEN, cq->tph_en) |
2635 FIELD_PREP(IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT,
2636 cq->cq_uk.avoid_mem_cflct) |
2637 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
2638
2639 irdma_wmb(); /* make sure WQE is written before valid bit is set */
2640
2641 set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
2642
2643 irdma_debug_buf(cqp->dev, IRDMA_DEBUG_WQE, "CQ_CREATE WQE", wqe,
2644 IRDMA_CQP_WQE_SIZE * 8);
2645 if (post_sq)
2646 irdma_sc_cqp_post_sq(cqp);
2647
2648 return 0;
2649 }
2650
2651 /**
2652 * irdma_sc_cq_destroy - destroy completion q
2653 * @cq: cq struct
2654 * @scratch: u64 saved to be used during cqp completion
2655 * @post_sq: flag for cqp db to ring
2656 */
2657 int
irdma_sc_cq_destroy(struct irdma_sc_cq * cq,u64 scratch,bool post_sq)2658 irdma_sc_cq_destroy(struct irdma_sc_cq *cq, u64 scratch, bool post_sq)
2659 {
2660 struct irdma_sc_cqp *cqp;
2661 __le64 *wqe;
2662 u64 hdr;
2663 struct irdma_sc_ceq *ceq;
2664
2665 cqp = cq->dev->cqp;
2666 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
2667 if (!wqe)
2668 return -ENOSPC;
2669
2670 ceq = cq->dev->ceq[cq->ceq_id];
2671 if (ceq && ceq->reg_cq)
2672 irdma_sc_remove_cq_ctx(ceq, cq);
2673
2674 set_64bit_val(wqe, IRDMA_BYTE_0, cq->cq_uk.cq_size);
2675 set_64bit_val(wqe, IRDMA_BYTE_8, RS_64_1(cq, 1));
2676 set_64bit_val(wqe, IRDMA_BYTE_40, cq->shadow_area_pa);
2677 set_64bit_val(wqe, IRDMA_BYTE_48,
2678 (cq->virtual_map ? cq->first_pm_pbl_idx : 0));
2679
2680 hdr = cq->cq_uk.cq_id |
2681 FLD_LS_64(cq->dev, (cq->ceq_id_valid ? cq->ceq_id : 0),
2682 IRDMA_CQPSQ_CQ_CEQID) |
2683 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DESTROY_CQ) |
2684 FIELD_PREP(IRDMA_CQPSQ_CQ_LPBLSIZE, cq->pbl_chunk_size) |
2685 FIELD_PREP(IRDMA_CQPSQ_CQ_VIRTMAP, cq->virtual_map) |
2686 FIELD_PREP(IRDMA_CQPSQ_CQ_ENCEQEMASK, cq->ceqe_mask) |
2687 FIELD_PREP(IRDMA_CQPSQ_CQ_CEQIDVALID, cq->ceq_id_valid) |
2688 FIELD_PREP(IRDMA_CQPSQ_TPHEN, cq->tph_en) |
2689 FIELD_PREP(IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT, cq->cq_uk.avoid_mem_cflct) |
2690 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
2691 irdma_wmb(); /* make sure WQE is written before valid bit is set */
2692
2693 set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
2694
2695 irdma_debug_buf(cqp->dev, IRDMA_DEBUG_WQE, "CQ_DESTROY WQE", wqe,
2696 IRDMA_CQP_WQE_SIZE * 8);
2697 if (post_sq)
2698 irdma_sc_cqp_post_sq(cqp);
2699
2700 return 0;
2701 }
2702
2703 /**
2704 * irdma_sc_cq_resize - set resized cq buffer info
2705 * @cq: resized cq
2706 * @info: resized cq buffer info
2707 */
2708 void
irdma_sc_cq_resize(struct irdma_sc_cq * cq,struct irdma_modify_cq_info * info)2709 irdma_sc_cq_resize(struct irdma_sc_cq *cq, struct irdma_modify_cq_info *info)
2710 {
2711 cq->virtual_map = info->virtual_map;
2712 cq->cq_pa = info->cq_pa;
2713 cq->first_pm_pbl_idx = info->first_pm_pbl_idx;
2714 cq->pbl_chunk_size = info->pbl_chunk_size;
2715 irdma_uk_cq_resize(&cq->cq_uk, info->cq_base, info->cq_size);
2716 }
2717
2718 /**
2719 * irdma_sc_cq_modify - modify a Completion Queue
2720 * @cq: cq struct
2721 * @info: modification info struct
2722 * @scratch: u64 saved to be used during cqp completion
2723 * @post_sq: flag to post to sq
2724 */
2725 static int
irdma_sc_cq_modify(struct irdma_sc_cq * cq,struct irdma_modify_cq_info * info,u64 scratch,bool post_sq)2726 irdma_sc_cq_modify(struct irdma_sc_cq *cq,
2727 struct irdma_modify_cq_info *info, u64 scratch,
2728 bool post_sq)
2729 {
2730 struct irdma_sc_cqp *cqp;
2731 __le64 *wqe;
2732 u64 hdr;
2733 u32 pble_obj_cnt;
2734
2735 pble_obj_cnt = cq->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt;
2736 if (info->cq_resize && info->virtual_map &&
2737 info->first_pm_pbl_idx >= pble_obj_cnt)
2738 return -EINVAL;
2739
2740 cqp = cq->dev->cqp;
2741 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
2742 if (!wqe)
2743 return -ENOSPC;
2744
2745 set_64bit_val(wqe, IRDMA_BYTE_0, info->cq_size);
2746 set_64bit_val(wqe, IRDMA_BYTE_8, RS_64_1(cq, 1));
2747 set_64bit_val(wqe, IRDMA_BYTE_16,
2748 FIELD_PREP(IRDMA_CQPSQ_CQ_SHADOW_READ_THRESHOLD, info->shadow_read_threshold));
2749 set_64bit_val(wqe, IRDMA_BYTE_32, info->cq_pa);
2750 set_64bit_val(wqe, IRDMA_BYTE_40, cq->shadow_area_pa);
2751 set_64bit_val(wqe, IRDMA_BYTE_48, info->first_pm_pbl_idx);
2752 set_64bit_val(wqe, IRDMA_BYTE_56,
2753 FIELD_PREP(IRDMA_CQPSQ_TPHVAL, cq->tph_val) |
2754 FIELD_PREP(IRDMA_CQPSQ_VSIIDX, cq->vsi->vsi_idx));
2755
2756 hdr = cq->cq_uk.cq_id |
2757 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MODIFY_CQ) |
2758 FIELD_PREP(IRDMA_CQPSQ_CQ_CQRESIZE, info->cq_resize) |
2759 FIELD_PREP(IRDMA_CQPSQ_CQ_LPBLSIZE, info->pbl_chunk_size) |
2760 FIELD_PREP(IRDMA_CQPSQ_CQ_CHKOVERFLOW, info->check_overflow) |
2761 FIELD_PREP(IRDMA_CQPSQ_CQ_VIRTMAP, info->virtual_map) |
2762 FIELD_PREP(IRDMA_CQPSQ_CQ_ENCEQEMASK, cq->ceqe_mask) |
2763 FIELD_PREP(IRDMA_CQPSQ_TPHEN, cq->tph_en) |
2764 FIELD_PREP(IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT,
2765 cq->cq_uk.avoid_mem_cflct) |
2766 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
2767 irdma_wmb(); /* make sure WQE is written before valid bit is set */
2768
2769 set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
2770
2771 irdma_debug_buf(cqp->dev, IRDMA_DEBUG_WQE, "CQ_MODIFY WQE", wqe,
2772 IRDMA_CQP_WQE_SIZE * 8);
2773 if (post_sq)
2774 irdma_sc_cqp_post_sq(cqp);
2775
2776 return 0;
2777 }
2778
2779 /**
2780 * irdma_check_cqp_progress - check cqp processing progress
2781 * @timeout: timeout info struct
2782 * @dev: sc device struct
2783 */
2784 void
irdma_check_cqp_progress(struct irdma_cqp_timeout * timeout,struct irdma_sc_dev * dev)2785 irdma_check_cqp_progress(struct irdma_cqp_timeout *timeout,
2786 struct irdma_sc_dev *dev)
2787 {
2788 u64 completed_ops = atomic64_read(&dev->cqp->completed_ops);
2789
2790 if (timeout->compl_cqp_cmds != completed_ops) {
2791 timeout->compl_cqp_cmds = completed_ops;
2792 timeout->count = 0;
2793 } else if (timeout->compl_cqp_cmds != dev->cqp->requested_ops) {
2794 timeout->count++;
2795 }
2796 }
2797
2798 /**
2799 * irdma_get_cqp_reg_info - get head and tail for cqp using registers
2800 * @cqp: struct for cqp hw
2801 * @val: cqp tail register value
2802 * @tail: wqtail register value
2803 * @error: cqp processing err
2804 */
2805 static inline void
irdma_get_cqp_reg_info(struct irdma_sc_cqp * cqp,u32 * val,u32 * tail,u32 * error)2806 irdma_get_cqp_reg_info(struct irdma_sc_cqp *cqp, u32 *val,
2807 u32 *tail, u32 *error)
2808 {
2809 *val = readl(cqp->dev->hw_regs[IRDMA_CQPTAIL]);
2810 *tail = FIELD_GET(IRDMA_CQPTAIL_WQTAIL, *val);
2811 *error = FIELD_GET(IRDMA_CQPTAIL_CQP_OP_ERR, *val);
2812 }
2813
2814 /**
2815 * irdma_cqp_poll_registers - poll cqp registers
2816 * @cqp: struct for cqp hw
2817 * @tail: wqtail register value
2818 * @count: how many times to try for completion
2819 */
2820 static int
irdma_cqp_poll_registers(struct irdma_sc_cqp * cqp,u32 tail,u32 count)2821 irdma_cqp_poll_registers(struct irdma_sc_cqp *cqp, u32 tail,
2822 u32 count)
2823 {
2824 u32 i = 0;
2825 u32 newtail, error, val;
2826
2827 while (i++ < count) {
2828 irdma_get_cqp_reg_info(cqp, &val, &newtail, &error);
2829 if (error) {
2830 error = readl(cqp->dev->hw_regs[IRDMA_CQPERRCODES]);
2831 irdma_debug(cqp->dev, IRDMA_DEBUG_CQP,
2832 "CQPERRCODES error_code[x%08X]\n", error);
2833 return -EIO;
2834 }
2835 if (newtail != tail) {
2836 /* SUCCESS */
2837 IRDMA_RING_MOVE_TAIL(cqp->sq_ring);
2838 atomic64_inc(&cqp->completed_ops);
2839 return 0;
2840 }
2841 irdma_usec_delay(cqp->dev->hw_attrs.max_sleep_count);
2842 }
2843
2844 return -ETIMEDOUT;
2845 }
2846
2847 /**
2848 * irdma_sc_decode_fpm_commit - decode a 64 bit value into count and base
2849 * @dev: sc device struct
2850 * @buf: pointer to commit buffer
2851 * @buf_idx: buffer index
2852 * @obj_info: object info pointer
2853 * @rsrc_idx: indexs of memory resource
2854 */
irdma_sc_decode_fpm_commit(struct irdma_sc_dev * dev,__le64 * buf,u32 buf_idx,struct irdma_hmc_obj_info * obj_info,u32 rsrc_idx)2855 static u64 irdma_sc_decode_fpm_commit(struct irdma_sc_dev *dev, __le64 * buf,
2856 u32 buf_idx, struct irdma_hmc_obj_info *obj_info,
2857 u32 rsrc_idx){
2858 u64 temp;
2859
2860 get_64bit_val(buf, buf_idx, &temp);
2861
2862 switch (rsrc_idx) {
2863 case IRDMA_HMC_IW_QP:
2864 obj_info[rsrc_idx].cnt = (u32)FIELD_GET(IRDMA_COMMIT_FPM_QPCNT, temp);
2865 break;
2866 case IRDMA_HMC_IW_CQ:
2867 obj_info[rsrc_idx].cnt = (u32)FLD_RS_64(dev, temp, IRDMA_COMMIT_FPM_CQCNT);
2868 break;
2869 case IRDMA_HMC_IW_APBVT_ENTRY:
2870 if (dev->hw_attrs.uk_attrs.hw_rev <= IRDMA_GEN_2)
2871 obj_info[rsrc_idx].cnt = 1;
2872 else
2873 obj_info[rsrc_idx].cnt = 0;
2874 break;
2875 default:
2876 obj_info[rsrc_idx].cnt = (u32)temp;
2877 break;
2878 }
2879
2880 obj_info[rsrc_idx].base = (u64)RS_64_1(temp, IRDMA_COMMIT_FPM_BASE_S) * 512;
2881
2882 return temp;
2883 }
2884
2885 /**
2886 * irdma_sc_parse_fpm_commit_buf - parse fpm commit buffer
2887 * @dev: pointer to dev struct
2888 * @buf: ptr to fpm commit buffer
2889 * @info: ptr to irdma_hmc_obj_info struct
2890 * @sd: number of SDs for HMC objects
2891 *
2892 * parses fpm commit info and copy base value
2893 * of hmc objects in hmc_info
2894 */
2895 static void
irdma_sc_parse_fpm_commit_buf(struct irdma_sc_dev * dev,__le64 * buf,struct irdma_hmc_obj_info * info,u32 * sd)2896 irdma_sc_parse_fpm_commit_buf(struct irdma_sc_dev *dev, __le64 * buf,
2897 struct irdma_hmc_obj_info *info,
2898 u32 *sd)
2899 {
2900 u64 size;
2901 u32 i;
2902 u64 max_base = 0;
2903 u32 last_hmc_obj = 0;
2904
2905 irdma_sc_decode_fpm_commit(dev, buf, IRDMA_BYTE_0, info,
2906 IRDMA_HMC_IW_QP);
2907 irdma_sc_decode_fpm_commit(dev, buf, IRDMA_BYTE_8, info,
2908 IRDMA_HMC_IW_CQ);
2909 /* skiping RSRVD */
2910 irdma_sc_decode_fpm_commit(dev, buf, IRDMA_BYTE_24, info,
2911 IRDMA_HMC_IW_HTE);
2912 irdma_sc_decode_fpm_commit(dev, buf, IRDMA_BYTE_32, info,
2913 IRDMA_HMC_IW_ARP);
2914 irdma_sc_decode_fpm_commit(dev, buf, IRDMA_BYTE_40, info,
2915 IRDMA_HMC_IW_APBVT_ENTRY);
2916 irdma_sc_decode_fpm_commit(dev, buf, IRDMA_BYTE_48, info,
2917 IRDMA_HMC_IW_MR);
2918 irdma_sc_decode_fpm_commit(dev, buf, IRDMA_BYTE_56, info,
2919 IRDMA_HMC_IW_XF);
2920 irdma_sc_decode_fpm_commit(dev, buf, IRDMA_BYTE_64, info,
2921 IRDMA_HMC_IW_XFFL);
2922 irdma_sc_decode_fpm_commit(dev, buf, IRDMA_BYTE_72, info,
2923 IRDMA_HMC_IW_Q1);
2924 irdma_sc_decode_fpm_commit(dev, buf, IRDMA_BYTE_80, info,
2925 IRDMA_HMC_IW_Q1FL);
2926 irdma_sc_decode_fpm_commit(dev, buf, IRDMA_BYTE_88, info,
2927 IRDMA_HMC_IW_TIMER);
2928 irdma_sc_decode_fpm_commit(dev, buf, IRDMA_BYTE_112, info,
2929 IRDMA_HMC_IW_PBLE);
2930 /* skipping RSVD. */
2931 if (dev->hw_attrs.uk_attrs.hw_rev != IRDMA_GEN_1) {
2932 irdma_sc_decode_fpm_commit(dev, buf, IRDMA_BYTE_96, info,
2933 IRDMA_HMC_IW_FSIMC);
2934 irdma_sc_decode_fpm_commit(dev, buf, IRDMA_BYTE_104, info,
2935 IRDMA_HMC_IW_FSIAV);
2936 irdma_sc_decode_fpm_commit(dev, buf, IRDMA_BYTE_128, info,
2937 IRDMA_HMC_IW_RRF);
2938 irdma_sc_decode_fpm_commit(dev, buf, IRDMA_BYTE_136, info,
2939 IRDMA_HMC_IW_RRFFL);
2940 irdma_sc_decode_fpm_commit(dev, buf, IRDMA_BYTE_144, info,
2941 IRDMA_HMC_IW_HDR);
2942 irdma_sc_decode_fpm_commit(dev, buf, IRDMA_BYTE_152, info,
2943 IRDMA_HMC_IW_MD);
2944 if (dev->cqp->protocol_used == IRDMA_IWARP_PROTOCOL_ONLY) {
2945 irdma_sc_decode_fpm_commit(dev, buf, IRDMA_BYTE_160, info,
2946 IRDMA_HMC_IW_OOISC);
2947 irdma_sc_decode_fpm_commit(dev, buf, IRDMA_BYTE_168, info,
2948 IRDMA_HMC_IW_OOISCFFL);
2949 }
2950 }
2951
2952 /* searching for the last object in HMC to find the size of the HMC area. */
2953 for (i = IRDMA_HMC_IW_QP; i < IRDMA_HMC_IW_MAX; i++) {
2954 if (info[i].base > max_base) {
2955 max_base = info[i].base;
2956 last_hmc_obj = i;
2957 }
2958 }
2959
2960 size = info[last_hmc_obj].cnt * info[last_hmc_obj].size +
2961 info[last_hmc_obj].base;
2962
2963 if (size & 0x1FFFFF)
2964 *sd = (u32)((size >> 21) + 1); /* add 1 for remainder */
2965 else
2966 *sd = (u32)(size >> 21);
2967
2968 }
2969
2970 /**
2971 * irdma_sc_decode_fpm_query() - Decode a 64 bit value into max count and size
2972 * @buf: ptr to fpm query buffer
2973 * @buf_idx: index into buf
2974 * @obj_info: ptr to irdma_hmc_obj_info struct
2975 * @rsrc_idx: resource index into info
2976 *
2977 * Decode a 64 bit value from fpm query buffer into max count and size
2978 */
irdma_sc_decode_fpm_query(__le64 * buf,u32 buf_idx,struct irdma_hmc_obj_info * obj_info,u32 rsrc_idx)2979 static u64 irdma_sc_decode_fpm_query(__le64 * buf, u32 buf_idx,
2980 struct irdma_hmc_obj_info *obj_info,
2981 u32 rsrc_idx){
2982 u64 temp;
2983 u32 size;
2984
2985 get_64bit_val(buf, buf_idx, &temp);
2986 obj_info[rsrc_idx].max_cnt = (u32)temp;
2987 size = (u32)RS_64_1(temp, 32);
2988 obj_info[rsrc_idx].size = LS_64_1(1, size);
2989
2990 return temp;
2991 }
2992
2993 /**
2994 * irdma_sc_parse_fpm_query_buf() - parses fpm query buffer
2995 * @dev: ptr to shared code device
2996 * @buf: ptr to fpm query buffer
2997 * @hmc_info: ptr to irdma_hmc_obj_info struct
2998 * @hmc_fpm_misc: ptr to fpm data
2999 *
3000 * parses fpm query buffer and copy max_cnt and
3001 * size value of hmc objects in hmc_info
3002 */
3003 static int
irdma_sc_parse_fpm_query_buf(struct irdma_sc_dev * dev,__le64 * buf,struct irdma_hmc_info * hmc_info,struct irdma_hmc_fpm_misc * hmc_fpm_misc)3004 irdma_sc_parse_fpm_query_buf(struct irdma_sc_dev *dev, __le64 * buf,
3005 struct irdma_hmc_info *hmc_info,
3006 struct irdma_hmc_fpm_misc *hmc_fpm_misc)
3007 {
3008 struct irdma_hmc_obj_info *obj_info;
3009 u64 temp;
3010 u32 size;
3011 u16 max_pe_sds;
3012
3013 obj_info = hmc_info->hmc_obj;
3014
3015 get_64bit_val(buf, IRDMA_BYTE_0, &temp);
3016 hmc_info->first_sd_index = (u16)FIELD_GET(IRDMA_QUERY_FPM_FIRST_PE_SD_INDEX, temp);
3017 max_pe_sds = (u16)FIELD_GET(IRDMA_QUERY_FPM_MAX_PE_SDS, temp);
3018
3019 hmc_fpm_misc->max_sds = max_pe_sds;
3020 hmc_info->sd_table.sd_cnt = max_pe_sds + hmc_info->first_sd_index;
3021 get_64bit_val(buf, 8, &temp);
3022 obj_info[IRDMA_HMC_IW_QP].max_cnt = (u32)FIELD_GET(IRDMA_QUERY_FPM_MAX_QPS, temp);
3023 size = (u32)RS_64_1(temp, 32);
3024 obj_info[IRDMA_HMC_IW_QP].size = LS_64_1(1, size);
3025
3026 get_64bit_val(buf, 16, &temp);
3027 obj_info[IRDMA_HMC_IW_CQ].max_cnt = (u32)FIELD_GET(IRDMA_QUERY_FPM_MAX_CQS, temp);
3028 size = (u32)RS_64_1(temp, 32);
3029 obj_info[IRDMA_HMC_IW_CQ].size = LS_64_1(1, size);
3030
3031 irdma_sc_decode_fpm_query(buf, 32, obj_info, IRDMA_HMC_IW_HTE);
3032 irdma_sc_decode_fpm_query(buf, 40, obj_info, IRDMA_HMC_IW_ARP);
3033
3034 obj_info[IRDMA_HMC_IW_APBVT_ENTRY].size = 8192;
3035 obj_info[IRDMA_HMC_IW_APBVT_ENTRY].max_cnt = 1;
3036
3037 irdma_sc_decode_fpm_query(buf, 48, obj_info, IRDMA_HMC_IW_MR);
3038 irdma_sc_decode_fpm_query(buf, 56, obj_info, IRDMA_HMC_IW_XF);
3039
3040 get_64bit_val(buf, 64, &temp);
3041 obj_info[IRDMA_HMC_IW_XFFL].max_cnt = (u32)temp;
3042 obj_info[IRDMA_HMC_IW_XFFL].size = 4;
3043 hmc_fpm_misc->xf_block_size = FIELD_GET(IRDMA_QUERY_FPM_XFBLOCKSIZE, temp);
3044 if (!hmc_fpm_misc->xf_block_size)
3045 return -EINVAL;
3046
3047 irdma_sc_decode_fpm_query(buf, 72, obj_info, IRDMA_HMC_IW_Q1);
3048 get_64bit_val(buf, 80, &temp);
3049 obj_info[IRDMA_HMC_IW_Q1FL].max_cnt = (u32)temp;
3050 obj_info[IRDMA_HMC_IW_Q1FL].size = 4;
3051
3052 hmc_fpm_misc->q1_block_size = FIELD_GET(IRDMA_QUERY_FPM_Q1BLOCKSIZE, temp);
3053 if (!hmc_fpm_misc->q1_block_size)
3054 return -EINVAL;
3055
3056 irdma_sc_decode_fpm_query(buf, 88, obj_info, IRDMA_HMC_IW_TIMER);
3057
3058 get_64bit_val(buf, 112, &temp);
3059 obj_info[IRDMA_HMC_IW_PBLE].max_cnt = (u32)temp;
3060 obj_info[IRDMA_HMC_IW_PBLE].size = 8;
3061
3062 get_64bit_val(buf, 120, &temp);
3063 hmc_fpm_misc->max_ceqs = FIELD_GET(IRDMA_QUERY_FPM_MAX_CEQS, temp);
3064 hmc_fpm_misc->ht_multiplier = FIELD_GET(IRDMA_QUERY_FPM_HTMULTIPLIER, temp);
3065 hmc_fpm_misc->timer_bucket = FIELD_GET(IRDMA_QUERY_FPM_TIMERBUCKET, temp);
3066 if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1)
3067 return 0;
3068 irdma_sc_decode_fpm_query(buf, 96, obj_info, IRDMA_HMC_IW_FSIMC);
3069 irdma_sc_decode_fpm_query(buf, 104, obj_info, IRDMA_HMC_IW_FSIAV);
3070 irdma_sc_decode_fpm_query(buf, 128, obj_info, IRDMA_HMC_IW_RRF);
3071
3072 get_64bit_val(buf, IRDMA_BYTE_136, &temp);
3073 obj_info[IRDMA_HMC_IW_RRFFL].max_cnt = (u32)temp;
3074 obj_info[IRDMA_HMC_IW_RRFFL].size = 4;
3075 hmc_fpm_misc->rrf_block_size = FIELD_GET(IRDMA_QUERY_FPM_RRFBLOCKSIZE, temp);
3076 if (!hmc_fpm_misc->rrf_block_size &&
3077 obj_info[IRDMA_HMC_IW_RRFFL].max_cnt)
3078 return -EINVAL;
3079
3080 irdma_sc_decode_fpm_query(buf, 144, obj_info, IRDMA_HMC_IW_HDR);
3081 irdma_sc_decode_fpm_query(buf, 152, obj_info, IRDMA_HMC_IW_MD);
3082
3083 if (dev->cqp->protocol_used == IRDMA_IWARP_PROTOCOL_ONLY) {
3084 irdma_sc_decode_fpm_query(buf, 160, obj_info, IRDMA_HMC_IW_OOISC);
3085
3086 get_64bit_val(buf, IRDMA_BYTE_168, &temp);
3087 obj_info[IRDMA_HMC_IW_OOISCFFL].max_cnt = (u32)temp;
3088 obj_info[IRDMA_HMC_IW_OOISCFFL].size = 4;
3089 hmc_fpm_misc->ooiscf_block_size = FIELD_GET(IRDMA_QUERY_FPM_OOISCFBLOCKSIZE, temp);
3090 if (!hmc_fpm_misc->ooiscf_block_size &&
3091 obj_info[IRDMA_HMC_IW_OOISCFFL].max_cnt)
3092 return -EINVAL;
3093 }
3094
3095 return 0;
3096 }
3097
3098 /**
3099 * irdma_sc_find_reg_cq - find cq ctx index
3100 * @ceq: ceq sc structure
3101 * @cq: cq sc structure
3102 */
irdma_sc_find_reg_cq(struct irdma_sc_ceq * ceq,struct irdma_sc_cq * cq)3103 static u32 irdma_sc_find_reg_cq(struct irdma_sc_ceq *ceq,
3104 struct irdma_sc_cq *cq){
3105 u32 i;
3106
3107 for (i = 0; i < ceq->reg_cq_size; i++) {
3108 if (cq == ceq->reg_cq[i])
3109 return i;
3110 }
3111
3112 return IRDMA_INVALID_CQ_IDX;
3113 }
3114
3115 /**
3116 * irdma_sc_add_cq_ctx - add cq ctx tracking for ceq
3117 * @ceq: ceq sc structure
3118 * @cq: cq sc structure
3119 */
3120 int
irdma_sc_add_cq_ctx(struct irdma_sc_ceq * ceq,struct irdma_sc_cq * cq)3121 irdma_sc_add_cq_ctx(struct irdma_sc_ceq *ceq, struct irdma_sc_cq *cq)
3122 {
3123 unsigned long flags;
3124
3125 spin_lock_irqsave(&ceq->req_cq_lock, flags);
3126
3127 if (ceq->reg_cq_size == ceq->elem_cnt) {
3128 spin_unlock_irqrestore(&ceq->req_cq_lock, flags);
3129 return -ENOSPC;
3130 }
3131
3132 ceq->reg_cq[ceq->reg_cq_size++] = cq;
3133
3134 spin_unlock_irqrestore(&ceq->req_cq_lock, flags);
3135
3136 return 0;
3137 }
3138
3139 /**
3140 * irdma_sc_remove_cq_ctx - remove cq ctx tracking for ceq
3141 * @ceq: ceq sc structure
3142 * @cq: cq sc structure
3143 */
3144 void
irdma_sc_remove_cq_ctx(struct irdma_sc_ceq * ceq,struct irdma_sc_cq * cq)3145 irdma_sc_remove_cq_ctx(struct irdma_sc_ceq *ceq, struct irdma_sc_cq *cq)
3146 {
3147 unsigned long flags;
3148 u32 cq_ctx_idx;
3149
3150 spin_lock_irqsave(&ceq->req_cq_lock, flags);
3151 cq_ctx_idx = irdma_sc_find_reg_cq(ceq, cq);
3152 if (cq_ctx_idx == IRDMA_INVALID_CQ_IDX)
3153 goto exit;
3154
3155 ceq->reg_cq_size--;
3156 if (cq_ctx_idx != ceq->reg_cq_size)
3157 ceq->reg_cq[cq_ctx_idx] = ceq->reg_cq[ceq->reg_cq_size];
3158 ceq->reg_cq[ceq->reg_cq_size] = NULL;
3159
3160 exit:
3161 spin_unlock_irqrestore(&ceq->req_cq_lock, flags);
3162 }
3163
3164 /**
3165 * irdma_sc_cqp_init - Initialize buffers for a control Queue Pair
3166 * @cqp: IWARP control queue pair pointer
3167 * @info: IWARP control queue pair init info pointer
3168 *
3169 * Initializes the object and context buffers for a control Queue Pair.
3170 */
3171 int
irdma_sc_cqp_init(struct irdma_sc_cqp * cqp,struct irdma_cqp_init_info * info)3172 irdma_sc_cqp_init(struct irdma_sc_cqp *cqp,
3173 struct irdma_cqp_init_info *info)
3174 {
3175 u8 hw_sq_size;
3176
3177 if (info->sq_size > IRDMA_CQP_SW_SQSIZE_2048 ||
3178 info->sq_size < IRDMA_CQP_SW_SQSIZE_4 ||
3179 ((info->sq_size & (info->sq_size - 1))))
3180 return -EINVAL;
3181
3182 hw_sq_size = irdma_get_encoded_wqe_size(info->sq_size,
3183 IRDMA_QUEUE_TYPE_CQP);
3184 cqp->size = sizeof(*cqp);
3185 cqp->sq_size = info->sq_size;
3186 cqp->hw_sq_size = hw_sq_size;
3187 cqp->sq_base = info->sq;
3188 cqp->host_ctx = info->host_ctx;
3189 cqp->sq_pa = info->sq_pa;
3190 cqp->host_ctx_pa = info->host_ctx_pa;
3191 cqp->dev = info->dev;
3192 cqp->struct_ver = info->struct_ver;
3193 cqp->hw_maj_ver = info->hw_maj_ver;
3194 cqp->hw_min_ver = info->hw_min_ver;
3195 cqp->scratch_array = info->scratch_array;
3196 cqp->polarity = 0;
3197 cqp->en_datacenter_tcp = info->en_datacenter_tcp;
3198 cqp->ena_vf_count = info->ena_vf_count;
3199 cqp->hmc_profile = info->hmc_profile;
3200 cqp->ceqs_per_vf = info->ceqs_per_vf;
3201 cqp->disable_packed = info->disable_packed;
3202 cqp->rocev2_rto_policy = info->rocev2_rto_policy;
3203 cqp->protocol_used = info->protocol_used;
3204 irdma_memcpy(&cqp->dcqcn_params, &info->dcqcn_params, sizeof(cqp->dcqcn_params));
3205 cqp->en_rem_endpoint_trk = info->en_rem_endpoint_trk;
3206 info->dev->cqp = cqp;
3207
3208 IRDMA_RING_INIT(cqp->sq_ring, cqp->sq_size);
3209 cqp->requested_ops = 0;
3210 atomic64_set(&cqp->completed_ops, 0);
3211 /* for the cqp commands backlog. */
3212 INIT_LIST_HEAD(&cqp->dev->cqp_cmd_head);
3213
3214 writel(0, cqp->dev->hw_regs[IRDMA_CQPTAIL]);
3215 writel(0, cqp->dev->hw_regs[IRDMA_CQPDB]);
3216 writel(0, cqp->dev->hw_regs[IRDMA_CCQPSTATUS]);
3217
3218 irdma_debug(cqp->dev, IRDMA_DEBUG_WQE,
3219 "sq_size[%04d] hw_sq_size[%04d] sq_base[%p] sq_pa[%llxh] cqp[%p] polarity[x%04x]\n",
3220 cqp->sq_size, cqp->hw_sq_size, cqp->sq_base,
3221 (unsigned long long)cqp->sq_pa, cqp, cqp->polarity);
3222 return 0;
3223 }
3224
3225 /**
3226 * irdma_sc_cqp_create - create cqp during bringup
3227 * @cqp: struct for cqp hw
3228 * @maj_err: If error, major err number
3229 * @min_err: If error, minor err number
3230 */
3231 int
irdma_sc_cqp_create(struct irdma_sc_cqp * cqp,u16 * maj_err,u16 * min_err)3232 irdma_sc_cqp_create(struct irdma_sc_cqp *cqp, u16 *maj_err, u16 *min_err)
3233 {
3234 u64 temp;
3235 u8 hw_rev;
3236 u32 cnt = 0, p1, p2, val = 0, err_code;
3237 int ret_code;
3238
3239 hw_rev = cqp->dev->hw_attrs.uk_attrs.hw_rev;
3240 cqp->sdbuf.size = IRDMA_UPDATE_SD_BUFF_SIZE * cqp->sq_size;
3241 cqp->sdbuf.va = irdma_allocate_dma_mem(cqp->dev->hw, &cqp->sdbuf,
3242 cqp->sdbuf.size,
3243 IRDMA_SD_BUF_ALIGNMENT);
3244 if (!cqp->sdbuf.va)
3245 return -ENOMEM;
3246
3247 spin_lock_init(&cqp->dev->cqp_lock);
3248
3249 temp = FIELD_PREP(IRDMA_CQPHC_SQSIZE, cqp->hw_sq_size) |
3250 FIELD_PREP(IRDMA_CQPHC_SVER, cqp->struct_ver) |
3251 FIELD_PREP(IRDMA_CQPHC_DISABLE_PFPDUS, cqp->disable_packed) |
3252 FIELD_PREP(IRDMA_CQPHC_CEQPERVF, cqp->ceqs_per_vf);
3253 if (hw_rev >= IRDMA_GEN_2) {
3254 temp |= FIELD_PREP(IRDMA_CQPHC_ROCEV2_RTO_POLICY,
3255 cqp->rocev2_rto_policy) |
3256 FIELD_PREP(IRDMA_CQPHC_PROTOCOL_USED,
3257 cqp->protocol_used);
3258 }
3259
3260 set_64bit_val(cqp->host_ctx, IRDMA_BYTE_0, temp);
3261 set_64bit_val(cqp->host_ctx, IRDMA_BYTE_8, cqp->sq_pa);
3262
3263 temp = FIELD_PREP(IRDMA_CQPHC_ENABLED_VFS, cqp->ena_vf_count) |
3264 FIELD_PREP(IRDMA_CQPHC_HMC_PROFILE, cqp->hmc_profile);
3265
3266 if (hw_rev >= IRDMA_GEN_2)
3267 temp |= FIELD_PREP(IRDMA_CQPHC_EN_REM_ENDPOINT_TRK,
3268 cqp->en_rem_endpoint_trk);
3269 set_64bit_val(cqp->host_ctx, IRDMA_BYTE_16, temp);
3270 set_64bit_val(cqp->host_ctx, IRDMA_BYTE_24, (uintptr_t)cqp);
3271 temp = FIELD_PREP(IRDMA_CQPHC_HW_MAJVER, cqp->hw_maj_ver) |
3272 FIELD_PREP(IRDMA_CQPHC_HW_MINVER, cqp->hw_min_ver);
3273 if (hw_rev >= IRDMA_GEN_2) {
3274 temp |= FIELD_PREP(IRDMA_CQPHC_MIN_RATE, cqp->dcqcn_params.min_rate) |
3275 FIELD_PREP(IRDMA_CQPHC_MIN_DEC_FACTOR, cqp->dcqcn_params.min_dec_factor);
3276 }
3277 set_64bit_val(cqp->host_ctx, IRDMA_BYTE_32, temp);
3278 set_64bit_val(cqp->host_ctx, IRDMA_BYTE_40, 0);
3279 temp = 0;
3280 if (hw_rev >= IRDMA_GEN_2) {
3281 temp |= FIELD_PREP(IRDMA_CQPHC_DCQCN_T, cqp->dcqcn_params.dcqcn_t) |
3282 FIELD_PREP(IRDMA_CQPHC_RAI_FACTOR, cqp->dcqcn_params.rai_factor) |
3283 FIELD_PREP(IRDMA_CQPHC_HAI_FACTOR, cqp->dcqcn_params.hai_factor);
3284 }
3285 set_64bit_val(cqp->host_ctx, IRDMA_BYTE_48, temp);
3286 temp = 0;
3287 if (hw_rev >= IRDMA_GEN_2) {
3288 temp |= FIELD_PREP(IRDMA_CQPHC_DCQCN_B, cqp->dcqcn_params.dcqcn_b) |
3289 FIELD_PREP(IRDMA_CQPHC_DCQCN_F, cqp->dcqcn_params.dcqcn_f) |
3290 FIELD_PREP(IRDMA_CQPHC_CC_CFG_VALID, cqp->dcqcn_params.cc_cfg_valid) |
3291 FIELD_PREP(IRDMA_CQPHC_RREDUCE_MPERIOD, cqp->dcqcn_params.rreduce_mperiod);
3292 }
3293 set_64bit_val(cqp->host_ctx, IRDMA_BYTE_56, temp);
3294 irdma_debug_buf(cqp->dev, IRDMA_DEBUG_WQE, "CQP_HOST_CTX WQE",
3295 cqp->host_ctx, IRDMA_CQP_CTX_SIZE * 8);
3296 p1 = RS_32_1(cqp->host_ctx_pa, 32);
3297 p2 = (u32)cqp->host_ctx_pa;
3298
3299 writel(p1, cqp->dev->hw_regs[IRDMA_CCQPHIGH]);
3300 writel(p2, cqp->dev->hw_regs[IRDMA_CCQPLOW]);
3301
3302 do {
3303 if (cnt++ > cqp->dev->hw_attrs.max_done_count) {
3304 ret_code = -ETIMEDOUT;
3305 goto err;
3306 }
3307 irdma_usec_delay(cqp->dev->hw_attrs.max_sleep_count);
3308 val = readl(cqp->dev->hw_regs[IRDMA_CCQPSTATUS]);
3309 } while (!val);
3310
3311 if (FLD_RS_32(cqp->dev, val, IRDMA_CCQPSTATUS_CCQP_ERR)) {
3312 ret_code = -EOPNOTSUPP;
3313 goto err;
3314 }
3315
3316 cqp->process_cqp_sds = irdma_update_sds_noccq;
3317 return 0;
3318
3319 err:
3320 spin_lock_destroy(&cqp->dev->cqp_lock);
3321 irdma_free_dma_mem(cqp->dev->hw, &cqp->sdbuf);
3322 err_code = readl(cqp->dev->hw_regs[IRDMA_CQPERRCODES]);
3323 *min_err = FIELD_GET(IRDMA_CQPERRCODES_CQP_MINOR_CODE, err_code);
3324 *maj_err = FIELD_GET(IRDMA_CQPERRCODES_CQP_MAJOR_CODE, err_code);
3325 return ret_code;
3326 }
3327
3328 /**
3329 * irdma_sc_cqp_post_sq - post of cqp's sq
3330 * @cqp: struct for cqp hw
3331 */
3332 void
irdma_sc_cqp_post_sq(struct irdma_sc_cqp * cqp)3333 irdma_sc_cqp_post_sq(struct irdma_sc_cqp *cqp)
3334 {
3335 db_wr32(IRDMA_RING_CURRENT_HEAD(cqp->sq_ring), cqp->dev->cqp_db);
3336
3337 irdma_debug(cqp->dev, IRDMA_DEBUG_WQE,
3338 "CQP SQ head 0x%x tail 0x%x size 0x%x\n", cqp->sq_ring.head,
3339 cqp->sq_ring.tail, cqp->sq_ring.size);
3340 }
3341
3342 /**
3343 * irdma_sc_cqp_get_next_send_wqe_idx - get next wqe on cqp sq
3344 * and pass back index
3345 * @cqp: CQP HW structure
3346 * @scratch: private data for CQP WQE
3347 * @wqe_idx: WQE index of CQP SQ
3348 */
3349 __le64 *
irdma_sc_cqp_get_next_send_wqe_idx(struct irdma_sc_cqp * cqp,u64 scratch,u32 * wqe_idx)3350 irdma_sc_cqp_get_next_send_wqe_idx(struct irdma_sc_cqp *cqp, u64 scratch,
3351 u32 *wqe_idx)
3352 {
3353 __le64 *wqe = NULL;
3354 int ret_code;
3355
3356 if (IRDMA_RING_FULL_ERR(cqp->sq_ring)) {
3357 irdma_debug(cqp->dev, IRDMA_DEBUG_WQE,
3358 "CQP SQ is full, head 0x%x tail 0x%x size 0x%x\n",
3359 cqp->sq_ring.head, cqp->sq_ring.tail,
3360 cqp->sq_ring.size);
3361 return NULL;
3362 }
3363 IRDMA_ATOMIC_RING_MOVE_HEAD(cqp->sq_ring, *wqe_idx, ret_code);
3364 if (ret_code)
3365 return NULL;
3366
3367 cqp->requested_ops++;
3368 if (!*wqe_idx)
3369 cqp->polarity = !cqp->polarity;
3370 wqe = cqp->sq_base[*wqe_idx].elem;
3371 cqp->scratch_array[*wqe_idx] = scratch;
3372
3373 memset(&wqe[0], 0, 24);
3374 memset(&wqe[4], 0, 32);
3375
3376 return wqe;
3377 }
3378
3379 /**
3380 * irdma_sc_cqp_destroy - destroy cqp during close
3381 * @cqp: struct for cqp hw
3382 * @free_hwcqp: true for regular cqp destroy; false for reset path
3383 */
3384 int
irdma_sc_cqp_destroy(struct irdma_sc_cqp * cqp,bool free_hwcqp)3385 irdma_sc_cqp_destroy(struct irdma_sc_cqp *cqp, bool free_hwcqp)
3386 {
3387 u32 cnt = 0, val;
3388 int ret_code = 0;
3389
3390 if (free_hwcqp) {
3391 writel(0, cqp->dev->hw_regs[IRDMA_CCQPHIGH]);
3392 writel(0, cqp->dev->hw_regs[IRDMA_CCQPLOW]);
3393 do {
3394 if (cnt++ > cqp->dev->hw_attrs.max_done_count) {
3395 ret_code = -ETIMEDOUT;
3396 break;
3397 }
3398 irdma_usec_delay(cqp->dev->hw_attrs.max_sleep_count);
3399 val = readl(cqp->dev->hw_regs[IRDMA_CCQPSTATUS]);
3400 } while (FLD_RS_32(cqp->dev, val, IRDMA_CCQPSTATUS_CCQP_DONE));
3401 }
3402 irdma_free_dma_mem(cqp->dev->hw, &cqp->sdbuf);
3403 spin_lock_destroy(&cqp->dev->cqp_lock);
3404 return ret_code;
3405 }
3406
3407 /**
3408 * irdma_sc_ccq_arm - enable intr for control cq
3409 * @ccq: ccq sc struct
3410 */
3411 void
irdma_sc_ccq_arm(struct irdma_sc_cq * ccq)3412 irdma_sc_ccq_arm(struct irdma_sc_cq *ccq)
3413 {
3414 unsigned long flags;
3415 u64 temp_val;
3416 u16 sw_cq_sel;
3417 u8 arm_next_se;
3418 u8 arm_seq_num;
3419
3420 spin_lock_irqsave(&ccq->dev->cqp_lock, flags);
3421 get_64bit_val(ccq->cq_uk.shadow_area, IRDMA_BYTE_32, &temp_val);
3422 sw_cq_sel = (u16)FIELD_GET(IRDMA_CQ_DBSA_SW_CQ_SELECT, temp_val);
3423 arm_next_se = (u8)FIELD_GET(IRDMA_CQ_DBSA_ARM_NEXT_SE, temp_val);
3424 arm_seq_num = (u8)FIELD_GET(IRDMA_CQ_DBSA_ARM_SEQ_NUM, temp_val);
3425 arm_seq_num++;
3426 temp_val = FIELD_PREP(IRDMA_CQ_DBSA_ARM_SEQ_NUM, arm_seq_num) |
3427 FIELD_PREP(IRDMA_CQ_DBSA_SW_CQ_SELECT, sw_cq_sel) |
3428 FIELD_PREP(IRDMA_CQ_DBSA_ARM_NEXT_SE, arm_next_se) |
3429 FIELD_PREP(IRDMA_CQ_DBSA_ARM_NEXT, 1);
3430 set_64bit_val(ccq->cq_uk.shadow_area, IRDMA_BYTE_32, temp_val);
3431 spin_unlock_irqrestore(&ccq->dev->cqp_lock, flags);
3432
3433 irdma_wmb(); /* make sure shadow area is updated before arming */
3434
3435 db_wr32(ccq->cq_uk.cq_id, ccq->dev->cq_arm_db);
3436 }
3437
3438 /**
3439 * irdma_sc_ccq_get_cqe_info - get ccq's cq entry
3440 * @ccq: ccq sc struct
3441 * @info: completion q entry to return
3442 */
3443 int
irdma_sc_ccq_get_cqe_info(struct irdma_sc_cq * ccq,struct irdma_ccq_cqe_info * info)3444 irdma_sc_ccq_get_cqe_info(struct irdma_sc_cq *ccq,
3445 struct irdma_ccq_cqe_info *info)
3446 {
3447 u64 qp_ctx, temp, temp1;
3448 __le64 *cqe;
3449 struct irdma_sc_cqp *cqp;
3450 u32 wqe_idx;
3451 u32 error;
3452 u8 polarity;
3453 int ret_code = 0;
3454 unsigned long flags;
3455
3456 if (ccq->cq_uk.avoid_mem_cflct)
3457 cqe = IRDMA_GET_CURRENT_EXTENDED_CQ_ELEM(&ccq->cq_uk);
3458 else
3459 cqe = IRDMA_GET_CURRENT_CQ_ELEM(&ccq->cq_uk);
3460
3461 get_64bit_val(cqe, IRDMA_BYTE_24, &temp);
3462 polarity = (u8)FIELD_GET(IRDMA_CQ_VALID, temp);
3463 if (polarity != ccq->cq_uk.polarity)
3464 return -ENOENT;
3465
3466 /* Ensure CEQE contents are read after valid bit is checked */
3467 rmb();
3468
3469 get_64bit_val(cqe, IRDMA_BYTE_8, &qp_ctx);
3470 cqp = (struct irdma_sc_cqp *)(irdma_uintptr) qp_ctx;
3471 info->error = (bool)FIELD_GET(IRDMA_CQ_ERROR, temp);
3472 info->maj_err_code = IRDMA_CQPSQ_MAJ_NO_ERROR;
3473 info->min_err_code = (u16)FIELD_GET(IRDMA_CQ_MINERR, temp);
3474 if (info->error) {
3475 info->maj_err_code = (u16)FIELD_GET(IRDMA_CQ_MAJERR, temp);
3476 error = readl(cqp->dev->hw_regs[IRDMA_CQPERRCODES]);
3477 irdma_debug(cqp->dev, IRDMA_DEBUG_CQP,
3478 "CQPERRCODES error_code[x%08X]\n", error);
3479 }
3480
3481 wqe_idx = (u32)FIELD_GET(IRDMA_CQ_WQEIDX, temp);
3482 info->scratch = cqp->scratch_array[wqe_idx];
3483
3484 get_64bit_val(cqe, IRDMA_BYTE_16, &temp1);
3485 info->op_ret_val = (u32)FIELD_GET(IRDMA_CCQ_OPRETVAL, temp1);
3486
3487 get_64bit_val(cqp->sq_base[wqe_idx].elem, IRDMA_BYTE_24, &temp1);
3488 info->op_code = (u8)FIELD_GET(IRDMA_CQPSQ_OPCODE, temp1);
3489 info->cqp = cqp;
3490
3491 /* move the head for cq */
3492 IRDMA_RING_MOVE_HEAD(ccq->cq_uk.cq_ring, ret_code);
3493 if (!IRDMA_RING_CURRENT_HEAD(ccq->cq_uk.cq_ring))
3494 ccq->cq_uk.polarity ^= 1;
3495
3496 /* update cq tail in cq shadow memory also */
3497 IRDMA_RING_MOVE_TAIL(ccq->cq_uk.cq_ring);
3498 set_64bit_val(ccq->cq_uk.shadow_area, IRDMA_BYTE_0,
3499 IRDMA_RING_CURRENT_HEAD(ccq->cq_uk.cq_ring));
3500
3501 irdma_wmb(); /* make sure shadow area is updated before moving tail */
3502
3503 spin_lock_irqsave(&cqp->dev->cqp_lock, flags);
3504 IRDMA_RING_MOVE_TAIL(cqp->sq_ring);
3505 spin_unlock_irqrestore(&cqp->dev->cqp_lock, flags);
3506 atomic64_inc(&cqp->completed_ops);
3507
3508 return ret_code;
3509 }
3510
3511 /**
3512 * irdma_sc_poll_for_cqp_op_done - Waits for last write to complete in CQP SQ
3513 * @cqp: struct for cqp hw
3514 * @op_code: cqp opcode for completion
3515 * @compl_info: completion q entry to return
3516 */
3517 int
irdma_sc_poll_for_cqp_op_done(struct irdma_sc_cqp * cqp,u8 op_code,struct irdma_ccq_cqe_info * compl_info)3518 irdma_sc_poll_for_cqp_op_done(struct irdma_sc_cqp *cqp, u8 op_code,
3519 struct irdma_ccq_cqe_info *compl_info)
3520 {
3521 struct irdma_ccq_cqe_info info = {0};
3522 struct irdma_sc_cq *ccq;
3523 int ret_code = 0;
3524 u32 cnt = 0;
3525
3526 ccq = cqp->dev->ccq;
3527 while (1) {
3528 if (cnt++ > 100 * cqp->dev->hw_attrs.max_done_count)
3529 return -ETIMEDOUT;
3530
3531 if (irdma_sc_ccq_get_cqe_info(ccq, &info)) {
3532 irdma_usec_delay(cqp->dev->hw_attrs.max_sleep_count);
3533 continue;
3534 }
3535 if (info.error && info.op_code != IRDMA_CQP_OP_QUERY_STAG) {
3536 ret_code = -EIO;
3537 break;
3538 }
3539 /* make sure op code matches */
3540 if (op_code == info.op_code)
3541 break;
3542 irdma_debug(cqp->dev, IRDMA_DEBUG_WQE,
3543 "opcode mismatch for my op code 0x%x, returned opcode %x\n",
3544 op_code, info.op_code);
3545 }
3546
3547 if (compl_info)
3548 irdma_memcpy(compl_info, &info, sizeof(*compl_info));
3549
3550 return ret_code;
3551 }
3552
3553 /**
3554 * irdma_sc_manage_hmc_pm_func_table - manage of function table
3555 * @cqp: struct for cqp hw
3556 * @scratch: u64 saved to be used during cqp completion
3557 * @info: info for the manage function table operation
3558 * @post_sq: flag for cqp db to ring
3559 */
3560 static int
irdma_sc_manage_hmc_pm_func_table(struct irdma_sc_cqp * cqp,struct irdma_hmc_fcn_info * info,u64 scratch,bool post_sq)3561 irdma_sc_manage_hmc_pm_func_table(struct irdma_sc_cqp *cqp,
3562 struct irdma_hmc_fcn_info *info,
3563 u64 scratch, bool post_sq)
3564 {
3565 __le64 *wqe;
3566 u64 hdr;
3567
3568 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
3569 if (!wqe)
3570 return -ENOSPC;
3571
3572 hdr = FIELD_PREP(IRDMA_CQPSQ_MHMC_VFIDX, info->vf_id) |
3573 FIELD_PREP(IRDMA_CQPSQ_OPCODE,
3574 IRDMA_CQP_OP_MANAGE_HMC_PM_FUNC_TABLE) |
3575 FIELD_PREP(IRDMA_CQPSQ_MHMC_FREEPMFN, info->free_fcn) |
3576 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
3577 irdma_wmb(); /* make sure WQE is written before valid bit is set */
3578
3579 set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
3580
3581 irdma_debug_buf(cqp->dev, IRDMA_DEBUG_WQE,
3582 "MANAGE_HMC_PM_FUNC_TABLE WQE", wqe,
3583 IRDMA_CQP_WQE_SIZE * 8);
3584 if (post_sq)
3585 irdma_sc_cqp_post_sq(cqp);
3586
3587 return 0;
3588 }
3589
3590 /**
3591 * irdma_sc_commit_fpm_val_done - wait for cqp eqe completion
3592 * for fpm commit
3593 * @cqp: struct for cqp hw
3594 */
3595 static int
irdma_sc_commit_fpm_val_done(struct irdma_sc_cqp * cqp)3596 irdma_sc_commit_fpm_val_done(struct irdma_sc_cqp *cqp)
3597 {
3598 return irdma_sc_poll_for_cqp_op_done(cqp, IRDMA_CQP_OP_COMMIT_FPM_VAL,
3599 NULL);
3600 }
3601
3602 /**
3603 * irdma_sc_commit_fpm_val - cqp wqe for commit fpm values
3604 * @cqp: struct for cqp hw
3605 * @scratch: u64 saved to be used during cqp completion
3606 * @hmc_fn_id: hmc function id
3607 * @commit_fpm_mem: Memory for fpm values
3608 * @post_sq: flag for cqp db to ring
3609 * @wait_type: poll ccq or cqp registers for cqp completion
3610 */
3611 static int
irdma_sc_commit_fpm_val(struct irdma_sc_cqp * cqp,u64 scratch,u16 hmc_fn_id,struct irdma_dma_mem * commit_fpm_mem,bool post_sq,u8 wait_type)3612 irdma_sc_commit_fpm_val(struct irdma_sc_cqp *cqp, u64 scratch,
3613 u16 hmc_fn_id,
3614 struct irdma_dma_mem *commit_fpm_mem,
3615 bool post_sq, u8 wait_type)
3616 {
3617 __le64 *wqe;
3618 u64 hdr;
3619 u32 tail, val, error;
3620 int ret_code = 0;
3621
3622 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
3623 if (!wqe)
3624 return -ENOSPC;
3625
3626 set_64bit_val(wqe, IRDMA_BYTE_16, hmc_fn_id);
3627 set_64bit_val(wqe, IRDMA_BYTE_32, commit_fpm_mem->pa);
3628
3629 hdr = FIELD_PREP(IRDMA_CQPSQ_BUFSIZE, IRDMA_COMMIT_FPM_BUF_SIZE) |
3630 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_COMMIT_FPM_VAL) |
3631 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
3632
3633 irdma_wmb(); /* make sure WQE is written before valid bit is set */
3634
3635 set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
3636
3637 irdma_debug_buf(cqp->dev, IRDMA_DEBUG_WQE, "COMMIT_FPM_VAL WQE", wqe,
3638 IRDMA_CQP_WQE_SIZE * 8);
3639 irdma_get_cqp_reg_info(cqp, &val, &tail, &error);
3640
3641 if (post_sq) {
3642 irdma_sc_cqp_post_sq(cqp);
3643 if (wait_type == IRDMA_CQP_WAIT_POLL_REGS)
3644 ret_code = irdma_cqp_poll_registers(cqp, tail,
3645 cqp->dev->hw_attrs.max_done_count);
3646 else if (wait_type == IRDMA_CQP_WAIT_POLL_CQ)
3647 ret_code = irdma_sc_commit_fpm_val_done(cqp);
3648 }
3649
3650 return ret_code;
3651 }
3652
3653 /**
3654 * irdma_sc_query_fpm_val_done - poll for cqp wqe completion for
3655 * query fpm
3656 * @cqp: struct for cqp hw
3657 */
3658 static int
irdma_sc_query_fpm_val_done(struct irdma_sc_cqp * cqp)3659 irdma_sc_query_fpm_val_done(struct irdma_sc_cqp *cqp)
3660 {
3661 return irdma_sc_poll_for_cqp_op_done(cqp, IRDMA_CQP_OP_QUERY_FPM_VAL,
3662 NULL);
3663 }
3664
3665 /**
3666 * irdma_sc_query_fpm_val - cqp wqe query fpm values
3667 * @cqp: struct for cqp hw
3668 * @scratch: u64 saved to be used during cqp completion
3669 * @hmc_fn_id: hmc function id
3670 * @query_fpm_mem: memory for return fpm values
3671 * @post_sq: flag for cqp db to ring
3672 * @wait_type: poll ccq or cqp registers for cqp completion
3673 */
3674 static int
irdma_sc_query_fpm_val(struct irdma_sc_cqp * cqp,u64 scratch,u16 hmc_fn_id,struct irdma_dma_mem * query_fpm_mem,bool post_sq,u8 wait_type)3675 irdma_sc_query_fpm_val(struct irdma_sc_cqp *cqp, u64 scratch,
3676 u16 hmc_fn_id,
3677 struct irdma_dma_mem *query_fpm_mem,
3678 bool post_sq, u8 wait_type)
3679 {
3680 __le64 *wqe;
3681 u64 hdr;
3682 u32 tail, val, error;
3683 int ret_code = 0;
3684
3685 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
3686 if (!wqe)
3687 return -ENOSPC;
3688
3689 set_64bit_val(wqe, IRDMA_BYTE_16, hmc_fn_id);
3690 set_64bit_val(wqe, IRDMA_BYTE_32, query_fpm_mem->pa);
3691
3692 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_QUERY_FPM_VAL) |
3693 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
3694 irdma_wmb(); /* make sure WQE is written before valid bit is set */
3695
3696 set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
3697
3698 irdma_debug_buf(cqp->dev, IRDMA_DEBUG_WQE, "QUERY_FPM WQE", wqe,
3699 IRDMA_CQP_WQE_SIZE * 8);
3700 irdma_get_cqp_reg_info(cqp, &val, &tail, &error);
3701
3702 if (post_sq) {
3703 irdma_sc_cqp_post_sq(cqp);
3704 if (wait_type == IRDMA_CQP_WAIT_POLL_REGS)
3705 ret_code = irdma_cqp_poll_registers(cqp, tail,
3706 cqp->dev->hw_attrs.max_done_count);
3707 else if (wait_type == IRDMA_CQP_WAIT_POLL_CQ)
3708 ret_code = irdma_sc_query_fpm_val_done(cqp);
3709 }
3710
3711 return ret_code;
3712 }
3713
3714 /**
3715 * irdma_sc_ceq_init - initialize ceq
3716 * @ceq: ceq sc structure
3717 * @info: ceq initialization info
3718 */
3719 int
irdma_sc_ceq_init(struct irdma_sc_ceq * ceq,struct irdma_ceq_init_info * info)3720 irdma_sc_ceq_init(struct irdma_sc_ceq *ceq,
3721 struct irdma_ceq_init_info *info)
3722 {
3723 u32 pble_obj_cnt;
3724
3725 if (info->elem_cnt < info->dev->hw_attrs.min_hw_ceq_size ||
3726 info->elem_cnt > info->dev->hw_attrs.max_hw_ceq_size)
3727 return -EINVAL;
3728
3729 if (info->ceq_id > (info->dev->hmc_fpm_misc.max_ceqs - 1))
3730 return -EINVAL;
3731 pble_obj_cnt = info->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt;
3732
3733 if (info->virtual_map && info->first_pm_pbl_idx >= pble_obj_cnt)
3734 return -EINVAL;
3735
3736 ceq->size = sizeof(*ceq);
3737 ceq->ceqe_base = (struct irdma_ceqe *)info->ceqe_base;
3738 ceq->ceq_id = info->ceq_id;
3739 ceq->dev = info->dev;
3740 ceq->elem_cnt = info->elem_cnt;
3741 ceq->ceq_elem_pa = info->ceqe_pa;
3742 ceq->virtual_map = info->virtual_map;
3743 ceq->itr_no_expire = info->itr_no_expire;
3744 ceq->reg_cq = info->reg_cq;
3745 ceq->reg_cq_size = 0;
3746 spin_lock_init(&ceq->req_cq_lock);
3747 ceq->pbl_chunk_size = (ceq->virtual_map ? info->pbl_chunk_size : 0);
3748 ceq->first_pm_pbl_idx = (ceq->virtual_map ? info->first_pm_pbl_idx : 0);
3749 ceq->pbl_list = (ceq->virtual_map ? info->pbl_list : NULL);
3750 ceq->tph_en = info->tph_en;
3751 ceq->tph_val = info->tph_val;
3752 ceq->vsi = info->vsi;
3753 ceq->polarity = 1;
3754 IRDMA_RING_INIT(ceq->ceq_ring, ceq->elem_cnt);
3755 ceq->dev->ceq[info->ceq_id] = ceq;
3756
3757 return 0;
3758 }
3759
3760 /**
3761 * irdma_sc_ceq_create - create ceq wqe
3762 * @ceq: ceq sc structure
3763 * @scratch: u64 saved to be used during cqp completion
3764 * @post_sq: flag for cqp db to ring
3765 */
3766 static int
irdma_sc_ceq_create(struct irdma_sc_ceq * ceq,u64 scratch,bool post_sq)3767 irdma_sc_ceq_create(struct irdma_sc_ceq *ceq, u64 scratch,
3768 bool post_sq)
3769 {
3770 struct irdma_sc_cqp *cqp;
3771 __le64 *wqe;
3772 u64 hdr;
3773
3774 cqp = ceq->dev->cqp;
3775 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
3776 if (!wqe)
3777 return -ENOSPC;
3778 set_64bit_val(wqe, IRDMA_BYTE_16, ceq->elem_cnt);
3779 set_64bit_val(wqe, IRDMA_BYTE_32,
3780 (ceq->virtual_map ? 0 : ceq->ceq_elem_pa));
3781 set_64bit_val(wqe, IRDMA_BYTE_48,
3782 (ceq->virtual_map ? ceq->first_pm_pbl_idx : 0));
3783 set_64bit_val(wqe, IRDMA_BYTE_56,
3784 FIELD_PREP(IRDMA_CQPSQ_TPHVAL, ceq->tph_val) |
3785 FIELD_PREP(IRDMA_CQPSQ_VSIIDX, ceq->vsi->vsi_idx));
3786 hdr = FIELD_PREP(IRDMA_CQPSQ_CEQ_CEQID, ceq->ceq_id) |
3787 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_CREATE_CEQ) |
3788 FIELD_PREP(IRDMA_CQPSQ_CEQ_LPBLSIZE, ceq->pbl_chunk_size) |
3789 FIELD_PREP(IRDMA_CQPSQ_CEQ_VMAP, ceq->virtual_map) |
3790 FIELD_PREP(IRDMA_CQPSQ_CEQ_ITRNOEXPIRE, ceq->itr_no_expire) |
3791 FIELD_PREP(IRDMA_CQPSQ_TPHEN, ceq->tph_en) |
3792 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
3793 irdma_wmb(); /* make sure WQE is written before valid bit is set */
3794
3795 set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
3796
3797 irdma_debug_buf(cqp->dev, IRDMA_DEBUG_WQE, "CEQ_CREATE WQE", wqe,
3798 IRDMA_CQP_WQE_SIZE * 8);
3799 if (post_sq)
3800 irdma_sc_cqp_post_sq(cqp);
3801
3802 return 0;
3803 }
3804
3805 /**
3806 * irdma_sc_cceq_create_done - poll for control ceq wqe to complete
3807 * @ceq: ceq sc structure
3808 */
3809 static int
irdma_sc_cceq_create_done(struct irdma_sc_ceq * ceq)3810 irdma_sc_cceq_create_done(struct irdma_sc_ceq *ceq)
3811 {
3812 struct irdma_sc_cqp *cqp;
3813
3814 cqp = ceq->dev->cqp;
3815 return irdma_sc_poll_for_cqp_op_done(cqp, IRDMA_CQP_OP_CREATE_CEQ,
3816 NULL);
3817 }
3818
3819 /**
3820 * irdma_sc_cceq_destroy_done - poll for destroy cceq to complete
3821 * @ceq: ceq sc structure
3822 */
3823 int
irdma_sc_cceq_destroy_done(struct irdma_sc_ceq * ceq)3824 irdma_sc_cceq_destroy_done(struct irdma_sc_ceq *ceq)
3825 {
3826 struct irdma_sc_cqp *cqp;
3827
3828 if (ceq->reg_cq)
3829 irdma_sc_remove_cq_ctx(ceq, ceq->dev->ccq);
3830 cqp = ceq->dev->cqp;
3831 cqp->process_cqp_sds = irdma_update_sds_noccq;
3832
3833 return irdma_sc_poll_for_cqp_op_done(cqp, IRDMA_CQP_OP_DESTROY_CEQ,
3834 NULL);
3835 }
3836
3837 /**
3838 * irdma_sc_cceq_create - create cceq
3839 * @ceq: ceq sc structure
3840 * @scratch: u64 saved to be used during cqp completion
3841 */
3842 int
irdma_sc_cceq_create(struct irdma_sc_ceq * ceq,u64 scratch)3843 irdma_sc_cceq_create(struct irdma_sc_ceq *ceq, u64 scratch)
3844 {
3845 int ret_code;
3846 struct irdma_sc_dev *dev = ceq->dev;
3847
3848 dev->ccq->vsi = ceq->vsi;
3849 if (ceq->reg_cq) {
3850 ret_code = irdma_sc_add_cq_ctx(ceq, ceq->dev->ccq);
3851 if (ret_code)
3852 return ret_code;
3853 }
3854 ret_code = irdma_sc_ceq_create(ceq, scratch, true);
3855 if (!ret_code)
3856 return irdma_sc_cceq_create_done(ceq);
3857
3858 return ret_code;
3859 }
3860
3861 /**
3862 * irdma_sc_ceq_destroy - destroy ceq
3863 * @ceq: ceq sc structure
3864 * @scratch: u64 saved to be used during cqp completion
3865 * @post_sq: flag for cqp db to ring
3866 */
3867 int
irdma_sc_ceq_destroy(struct irdma_sc_ceq * ceq,u64 scratch,bool post_sq)3868 irdma_sc_ceq_destroy(struct irdma_sc_ceq *ceq, u64 scratch, bool post_sq)
3869 {
3870 struct irdma_sc_cqp *cqp;
3871 __le64 *wqe;
3872 u64 hdr;
3873
3874 cqp = ceq->dev->cqp;
3875 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
3876 if (!wqe)
3877 return -ENOSPC;
3878
3879 set_64bit_val(wqe, IRDMA_BYTE_16, ceq->elem_cnt);
3880 set_64bit_val(wqe, IRDMA_BYTE_48, ceq->first_pm_pbl_idx);
3881 hdr = ceq->ceq_id |
3882 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DESTROY_CEQ) |
3883 FIELD_PREP(IRDMA_CQPSQ_CEQ_LPBLSIZE, ceq->pbl_chunk_size) |
3884 FIELD_PREP(IRDMA_CQPSQ_CEQ_VMAP, ceq->virtual_map) |
3885 FIELD_PREP(IRDMA_CQPSQ_TPHEN, ceq->tph_en) |
3886 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
3887 irdma_wmb(); /* make sure WQE is written before valid bit is set */
3888
3889 set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
3890
3891 irdma_debug_buf(cqp->dev, IRDMA_DEBUG_WQE, "CEQ_DESTROY WQE", wqe,
3892 IRDMA_CQP_WQE_SIZE * 8);
3893 ceq->dev->ceq[ceq->ceq_id] = NULL;
3894 if (post_sq)
3895 irdma_sc_cqp_post_sq(cqp);
3896
3897 return 0;
3898 }
3899
3900 /**
3901 * irdma_sc_process_ceq - process ceq
3902 * @dev: sc device struct
3903 * @ceq: ceq sc structure
3904 *
3905 * It is expected caller serializes this function with cleanup_ceqes()
3906 * because these functions manipulate the same ceq
3907 */
3908 void *
irdma_sc_process_ceq(struct irdma_sc_dev * dev,struct irdma_sc_ceq * ceq)3909 irdma_sc_process_ceq(struct irdma_sc_dev *dev, struct irdma_sc_ceq *ceq)
3910 {
3911 u64 temp;
3912 __le64 *ceqe;
3913 struct irdma_sc_cq *cq = NULL;
3914 struct irdma_sc_cq *temp_cq;
3915 u8 polarity;
3916 u32 cq_idx;
3917 unsigned long flags;
3918
3919 do {
3920 cq_idx = 0;
3921 ceqe = IRDMA_GET_CURRENT_CEQ_ELEM(ceq);
3922 get_64bit_val(ceqe, IRDMA_BYTE_0, &temp);
3923 polarity = (u8)FIELD_GET(IRDMA_CEQE_VALID, temp);
3924 if (polarity != ceq->polarity)
3925 return NULL;
3926
3927 temp_cq = (struct irdma_sc_cq *)(irdma_uintptr) LS_64_1(temp, 1);
3928 if (!temp_cq) {
3929 cq_idx = IRDMA_INVALID_CQ_IDX;
3930 IRDMA_RING_MOVE_TAIL(ceq->ceq_ring);
3931
3932 if (!IRDMA_RING_CURRENT_TAIL(ceq->ceq_ring))
3933 ceq->polarity ^= 1;
3934 continue;
3935 }
3936
3937 cq = temp_cq;
3938 if (ceq->reg_cq) {
3939 spin_lock_irqsave(&ceq->req_cq_lock, flags);
3940 cq_idx = irdma_sc_find_reg_cq(ceq, cq);
3941 spin_unlock_irqrestore(&ceq->req_cq_lock, flags);
3942 }
3943 IRDMA_RING_MOVE_TAIL(ceq->ceq_ring);
3944 if (!IRDMA_RING_CURRENT_TAIL(ceq->ceq_ring))
3945 ceq->polarity ^= 1;
3946 } while (cq_idx == IRDMA_INVALID_CQ_IDX);
3947
3948 if (cq)
3949 irdma_sc_cq_ack(cq);
3950 return cq;
3951 }
3952
3953 /**
3954 * irdma_sc_cleanup_ceqes - clear the valid ceqes ctx matching the cq
3955 * @cq: cq for which the ceqes need to be cleaned up
3956 * @ceq: ceq ptr
3957 *
3958 * The function is called after the cq is destroyed to cleanup
3959 * its pending ceqe entries. It is expected caller serializes this
3960 * function with process_ceq() in interrupt context.
3961 */
3962 void
irdma_sc_cleanup_ceqes(struct irdma_sc_cq * cq,struct irdma_sc_ceq * ceq)3963 irdma_sc_cleanup_ceqes(struct irdma_sc_cq *cq, struct irdma_sc_ceq *ceq)
3964 {
3965 struct irdma_sc_cq *next_cq;
3966 u8 ceq_polarity = ceq->polarity;
3967 __le64 *ceqe;
3968 u8 polarity;
3969 u64 temp;
3970 int next;
3971 u32 i;
3972
3973 next = IRDMA_RING_GET_NEXT_TAIL(ceq->ceq_ring, 0);
3974
3975 for (i = 1; i <= IRDMA_RING_SIZE(*ceq); i++) {
3976 ceqe = IRDMA_GET_CEQ_ELEM_AT_POS(ceq, next);
3977
3978 get_64bit_val(ceqe, IRDMA_BYTE_0, &temp);
3979 polarity = (u8)FIELD_GET(IRDMA_CEQE_VALID, temp);
3980 if (polarity != ceq_polarity)
3981 return;
3982
3983 next_cq = (struct irdma_sc_cq *)(irdma_uintptr) LS_64_1(temp, 1);
3984 if (cq == next_cq)
3985 set_64bit_val(ceqe, IRDMA_BYTE_0, temp & IRDMA_CEQE_VALID);
3986
3987 next = IRDMA_RING_GET_NEXT_TAIL(ceq->ceq_ring, i);
3988 if (!next)
3989 ceq_polarity ^= 1;
3990 }
3991 }
3992
3993 /**
3994 * irdma_sc_aeq_init - initialize aeq
3995 * @aeq: aeq structure ptr
3996 * @info: aeq initialization info
3997 */
3998 int
irdma_sc_aeq_init(struct irdma_sc_aeq * aeq,struct irdma_aeq_init_info * info)3999 irdma_sc_aeq_init(struct irdma_sc_aeq *aeq,
4000 struct irdma_aeq_init_info *info)
4001 {
4002 u32 pble_obj_cnt;
4003
4004 if (info->elem_cnt < info->dev->hw_attrs.min_hw_aeq_size ||
4005 info->elem_cnt > info->dev->hw_attrs.max_hw_aeq_size)
4006 return -EINVAL;
4007
4008 pble_obj_cnt = info->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt;
4009
4010 if (info->virtual_map && info->first_pm_pbl_idx >= pble_obj_cnt)
4011 return -EINVAL;
4012
4013 aeq->size = sizeof(*aeq);
4014 aeq->polarity = 1;
4015 aeq->aeqe_base = (struct irdma_sc_aeqe *)info->aeqe_base;
4016 aeq->dev = info->dev;
4017 aeq->elem_cnt = info->elem_cnt;
4018 aeq->aeq_elem_pa = info->aeq_elem_pa;
4019 IRDMA_RING_INIT(aeq->aeq_ring, aeq->elem_cnt);
4020 aeq->virtual_map = info->virtual_map;
4021 aeq->pbl_list = (aeq->virtual_map ? info->pbl_list : NULL);
4022 aeq->pbl_chunk_size = (aeq->virtual_map ? info->pbl_chunk_size : 0);
4023 aeq->first_pm_pbl_idx = (aeq->virtual_map ? info->first_pm_pbl_idx : 0);
4024 aeq->msix_idx = info->msix_idx;
4025 info->dev->aeq = aeq;
4026
4027 return 0;
4028 }
4029
4030 /**
4031 * irdma_sc_aeq_create - create aeq
4032 * @aeq: aeq structure ptr
4033 * @scratch: u64 saved to be used during cqp completion
4034 * @post_sq: flag for cqp db to ring
4035 */
4036 static int
irdma_sc_aeq_create(struct irdma_sc_aeq * aeq,u64 scratch,bool post_sq)4037 irdma_sc_aeq_create(struct irdma_sc_aeq *aeq, u64 scratch,
4038 bool post_sq)
4039 {
4040 __le64 *wqe;
4041 struct irdma_sc_cqp *cqp;
4042 u64 hdr;
4043
4044 cqp = aeq->dev->cqp;
4045 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
4046 if (!wqe)
4047 return -ENOSPC;
4048 set_64bit_val(wqe, IRDMA_BYTE_16, aeq->elem_cnt);
4049 set_64bit_val(wqe, IRDMA_BYTE_32,
4050 (aeq->virtual_map ? 0 : aeq->aeq_elem_pa));
4051 set_64bit_val(wqe, IRDMA_BYTE_48,
4052 (aeq->virtual_map ? aeq->first_pm_pbl_idx : 0));
4053
4054 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_CREATE_AEQ) |
4055 FIELD_PREP(IRDMA_CQPSQ_AEQ_LPBLSIZE, aeq->pbl_chunk_size) |
4056 FIELD_PREP(IRDMA_CQPSQ_AEQ_VMAP, aeq->virtual_map) |
4057 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
4058 irdma_wmb(); /* make sure WQE is written before valid bit is set */
4059
4060 set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
4061
4062 irdma_debug_buf(cqp->dev, IRDMA_DEBUG_WQE, "AEQ_CREATE WQE", wqe,
4063 IRDMA_CQP_WQE_SIZE * 8);
4064 if (post_sq)
4065 irdma_sc_cqp_post_sq(cqp);
4066
4067 return 0;
4068 }
4069
4070 /**
4071 * irdma_sc_aeq_destroy - destroy aeq during close
4072 * @aeq: aeq structure ptr
4073 * @scratch: u64 saved to be used during cqp completion
4074 * @post_sq: flag for cqp db to ring
4075 */
4076 int
irdma_sc_aeq_destroy(struct irdma_sc_aeq * aeq,u64 scratch,bool post_sq)4077 irdma_sc_aeq_destroy(struct irdma_sc_aeq *aeq, u64 scratch, bool post_sq)
4078 {
4079 __le64 *wqe;
4080 struct irdma_sc_cqp *cqp;
4081 struct irdma_sc_dev *dev;
4082 u64 hdr;
4083
4084 dev = aeq->dev;
4085 writel(0, dev->hw_regs[IRDMA_PFINT_AEQCTL]);
4086
4087 cqp = dev->cqp;
4088 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
4089 if (!wqe)
4090 return -ENOSPC;
4091 set_64bit_val(wqe, IRDMA_BYTE_16, aeq->elem_cnt);
4092 set_64bit_val(wqe, IRDMA_BYTE_48, aeq->first_pm_pbl_idx);
4093 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DESTROY_AEQ) |
4094 FIELD_PREP(IRDMA_CQPSQ_AEQ_LPBLSIZE, aeq->pbl_chunk_size) |
4095 FIELD_PREP(IRDMA_CQPSQ_AEQ_VMAP, aeq->virtual_map) |
4096 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
4097 irdma_wmb(); /* make sure WQE is written before valid bit is set */
4098
4099 set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
4100
4101 irdma_debug_buf(dev, IRDMA_DEBUG_WQE, "AEQ_DESTROY WQE", wqe,
4102 IRDMA_CQP_WQE_SIZE * 8);
4103 if (post_sq)
4104 irdma_sc_cqp_post_sq(cqp);
4105 return 0;
4106 }
4107
4108 /**
4109 * irdma_sc_get_next_aeqe - get next aeq entry
4110 * @aeq: aeq structure ptr
4111 * @info: aeqe info to be returned
4112 */
4113 int
irdma_sc_get_next_aeqe(struct irdma_sc_aeq * aeq,struct irdma_aeqe_info * info)4114 irdma_sc_get_next_aeqe(struct irdma_sc_aeq *aeq,
4115 struct irdma_aeqe_info *info)
4116 {
4117 u64 temp, compl_ctx;
4118 __le64 *aeqe;
4119 u8 ae_src;
4120 u8 polarity;
4121
4122 aeqe = IRDMA_GET_CURRENT_AEQ_ELEM(aeq);
4123 get_64bit_val(aeqe, IRDMA_BYTE_8, &temp);
4124 polarity = (u8)FIELD_GET(IRDMA_AEQE_VALID, temp);
4125
4126 if (aeq->polarity != polarity)
4127 return -ENOENT;
4128
4129 /* Ensure AEQE contents are read after valid bit is checked */
4130 rmb();
4131
4132 get_64bit_val(aeqe, IRDMA_BYTE_0, &compl_ctx);
4133
4134 irdma_debug_buf(aeq->dev, IRDMA_DEBUG_WQE, "AEQ_ENTRY WQE", aeqe, 16);
4135
4136 ae_src = (u8)FIELD_GET(IRDMA_AEQE_AESRC, temp);
4137 info->wqe_idx = (u16)FIELD_GET(IRDMA_AEQE_WQDESCIDX, temp);
4138 info->qp_cq_id = (u32)FIELD_GET(IRDMA_AEQE_QPCQID_LOW, temp) |
4139 ((u32)FIELD_GET(IRDMA_AEQE_QPCQID_HI, temp) << 18);
4140 info->ae_id = (u16)FIELD_GET(IRDMA_AEQE_AECODE, temp);
4141 info->tcp_state = (u8)FIELD_GET(IRDMA_AEQE_TCPSTATE, temp);
4142 info->iwarp_state = (u8)FIELD_GET(IRDMA_AEQE_IWSTATE, temp);
4143 info->q2_data_written = (u8)FIELD_GET(IRDMA_AEQE_Q2DATA, temp);
4144 info->aeqe_overflow = (bool)FIELD_GET(IRDMA_AEQE_OVERFLOW, temp);
4145
4146 info->ae_src = ae_src;
4147 switch (info->ae_id) {
4148 case IRDMA_AE_PRIV_OPERATION_DENIED:
4149 case IRDMA_AE_AMP_INVALIDATE_TYPE1_MW:
4150 case IRDMA_AE_AMP_MWBIND_ZERO_BASED_TYPE1_MW:
4151 case IRDMA_AE_AMP_FASTREG_INVALID_PBL_HPS_CFG:
4152 case IRDMA_AE_AMP_FASTREG_PBLE_MISMATCH:
4153 case IRDMA_AE_UDA_XMIT_DGRAM_TOO_LONG:
4154 case IRDMA_AE_UDA_XMIT_BAD_PD:
4155 case IRDMA_AE_UDA_XMIT_DGRAM_TOO_SHORT:
4156 case IRDMA_AE_BAD_CLOSE:
4157 case IRDMA_AE_RDMA_READ_WHILE_ORD_ZERO:
4158 case IRDMA_AE_STAG_ZERO_INVALID:
4159 case IRDMA_AE_IB_RREQ_AND_Q1_FULL:
4160 case IRDMA_AE_IB_INVALID_REQUEST:
4161 case IRDMA_AE_WQE_UNEXPECTED_OPCODE:
4162 case IRDMA_AE_IB_REMOTE_ACCESS_ERROR:
4163 case IRDMA_AE_IB_REMOTE_OP_ERROR:
4164 case IRDMA_AE_DDP_UBE_INVALID_DDP_VERSION:
4165 case IRDMA_AE_DDP_UBE_INVALID_MO:
4166 case IRDMA_AE_DDP_UBE_INVALID_QN:
4167 case IRDMA_AE_DDP_NO_L_BIT:
4168 case IRDMA_AE_RDMAP_ROE_INVALID_RDMAP_VERSION:
4169 case IRDMA_AE_RDMAP_ROE_UNEXPECTED_OPCODE:
4170 case IRDMA_AE_ROE_INVALID_RDMA_READ_REQUEST:
4171 case IRDMA_AE_ROE_INVALID_RDMA_WRITE_OR_READ_RESP:
4172 case IRDMA_AE_ROCE_RSP_LENGTH_ERROR:
4173 case IRDMA_AE_ROCE_REQ_LENGTH_ERROR:
4174 case IRDMA_AE_INVALID_ARP_ENTRY:
4175 case IRDMA_AE_INVALID_TCP_OPTION_RCVD:
4176 case IRDMA_AE_STALE_ARP_ENTRY:
4177 case IRDMA_AE_INVALID_AH_ENTRY:
4178 case IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR:
4179 case IRDMA_AE_LLP_SEGMENT_TOO_SMALL:
4180 case IRDMA_AE_LLP_TOO_MANY_RETRIES:
4181 case IRDMA_AE_LCE_QP_CATASTROPHIC:
4182 case IRDMA_AE_LLP_DOUBT_REACHABILITY:
4183 case IRDMA_AE_LLP_CONNECTION_ESTABLISHED:
4184 case IRDMA_AE_RESET_SENT:
4185 case IRDMA_AE_TERMINATE_SENT:
4186 case IRDMA_AE_RESET_NOT_SENT:
4187 case IRDMA_AE_QP_SUSPEND_COMPLETE:
4188 case IRDMA_AE_UDA_L4LEN_INVALID:
4189 info->qp = true;
4190 info->compl_ctx = compl_ctx;
4191 break;
4192 case IRDMA_AE_LCE_CQ_CATASTROPHIC:
4193 info->cq = true;
4194 info->compl_ctx = LS_64_1(compl_ctx, 1);
4195 ae_src = IRDMA_AE_SOURCE_RSVD;
4196 break;
4197 case IRDMA_AE_ROCE_EMPTY_MCG:
4198 case IRDMA_AE_ROCE_BAD_MC_IP_ADDR:
4199 case IRDMA_AE_ROCE_BAD_MC_QPID:
4200 case IRDMA_AE_MCG_QP_PROTOCOL_MISMATCH:
4201 /* fallthrough */
4202 case IRDMA_AE_LLP_CONNECTION_RESET:
4203 case IRDMA_AE_LLP_SYN_RECEIVED:
4204 case IRDMA_AE_LLP_FIN_RECEIVED:
4205 case IRDMA_AE_LLP_CLOSE_COMPLETE:
4206 case IRDMA_AE_LLP_TERMINATE_RECEIVED:
4207 case IRDMA_AE_RDMAP_ROE_BAD_LLP_CLOSE:
4208 ae_src = IRDMA_AE_SOURCE_RSVD;
4209 info->qp = true;
4210 info->compl_ctx = compl_ctx;
4211 break;
4212 case IRDMA_AE_RESOURCE_EXHAUSTION:
4213 /*
4214 * ae_src contains the exhausted resource with a unique decoding. Set RSVD here to prevent matching
4215 * with a CQ or QP.
4216 */
4217 ae_src = IRDMA_AE_SOURCE_RSVD;
4218 break;
4219 default:
4220 break;
4221 }
4222
4223 switch (ae_src) {
4224 case IRDMA_AE_SOURCE_RQ:
4225 case IRDMA_AE_SOURCE_RQ_0011:
4226 info->qp = true;
4227 info->rq = true;
4228 info->compl_ctx = compl_ctx;
4229 info->err_rq_idx_valid = true;
4230 break;
4231 case IRDMA_AE_SOURCE_CQ:
4232 case IRDMA_AE_SOURCE_CQ_0110:
4233 case IRDMA_AE_SOURCE_CQ_1010:
4234 case IRDMA_AE_SOURCE_CQ_1110:
4235 info->cq = true;
4236 info->compl_ctx = LS_64_1(compl_ctx, 1);
4237 break;
4238 case IRDMA_AE_SOURCE_SQ:
4239 case IRDMA_AE_SOURCE_SQ_0111:
4240 info->qp = true;
4241 info->sq = true;
4242 info->compl_ctx = compl_ctx;
4243 break;
4244 case IRDMA_AE_SOURCE_IN_WR:
4245 info->qp = true;
4246 info->compl_ctx = compl_ctx;
4247 info->in_rdrsp_wr = true;
4248 break;
4249 case IRDMA_AE_SOURCE_IN_RR:
4250 info->qp = true;
4251 info->compl_ctx = compl_ctx;
4252 info->in_rdrsp_wr = true;
4253 break;
4254 case IRDMA_AE_SOURCE_OUT_RR:
4255 case IRDMA_AE_SOURCE_OUT_RR_1111:
4256 info->qp = true;
4257 info->compl_ctx = compl_ctx;
4258 info->out_rdrsp = true;
4259 break;
4260 case IRDMA_AE_SOURCE_RSVD:
4261 default:
4262 break;
4263 }
4264
4265 IRDMA_RING_MOVE_TAIL(aeq->aeq_ring);
4266 if (!IRDMA_RING_CURRENT_TAIL(aeq->aeq_ring))
4267 aeq->polarity ^= 1;
4268
4269 return 0;
4270 }
4271
4272 /**
4273 * irdma_sc_repost_aeq_entries - repost completed aeq entries
4274 * @dev: sc device struct
4275 * @count: allocate count
4276 */
4277 void
irdma_sc_repost_aeq_entries(struct irdma_sc_dev * dev,u32 count)4278 irdma_sc_repost_aeq_entries(struct irdma_sc_dev *dev, u32 count)
4279 {
4280 db_wr32(count, dev->aeq_alloc_db);
4281
4282 }
4283
4284 /**
4285 * irdma_sc_ccq_init - initialize control cq
4286 * @cq: sc's cq ctruct
4287 * @info: info for control cq initialization
4288 */
4289 int
irdma_sc_ccq_init(struct irdma_sc_cq * cq,struct irdma_ccq_init_info * info)4290 irdma_sc_ccq_init(struct irdma_sc_cq *cq, struct irdma_ccq_init_info *info)
4291 {
4292 u32 pble_obj_cnt;
4293
4294 if (info->num_elem < info->dev->hw_attrs.uk_attrs.min_hw_cq_size ||
4295 info->num_elem > info->dev->hw_attrs.uk_attrs.max_hw_cq_size)
4296 return -EINVAL;
4297
4298 if (info->ceq_id > (info->dev->hmc_fpm_misc.max_ceqs - 1))
4299 return -EINVAL;
4300
4301 pble_obj_cnt = info->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt;
4302
4303 if (info->virtual_map && info->first_pm_pbl_idx >= pble_obj_cnt)
4304 return -EINVAL;
4305
4306 cq->cq_pa = info->cq_pa;
4307 cq->cq_uk.cq_base = info->cq_base;
4308 cq->shadow_area_pa = info->shadow_area_pa;
4309 cq->cq_uk.shadow_area = info->shadow_area;
4310 cq->shadow_read_threshold = info->shadow_read_threshold;
4311 cq->dev = info->dev;
4312 cq->ceq_id = info->ceq_id;
4313 cq->cq_uk.cq_size = info->num_elem;
4314 cq->cq_type = IRDMA_CQ_TYPE_CQP;
4315 cq->ceqe_mask = info->ceqe_mask;
4316 IRDMA_RING_INIT(cq->cq_uk.cq_ring, info->num_elem);
4317 cq->cq_uk.cq_id = 0; /* control cq is id 0 always */
4318 cq->ceq_id_valid = info->ceq_id_valid;
4319 cq->tph_en = info->tph_en;
4320 cq->tph_val = info->tph_val;
4321 cq->cq_uk.avoid_mem_cflct = info->avoid_mem_cflct;
4322 cq->pbl_list = info->pbl_list;
4323 cq->virtual_map = info->virtual_map;
4324 cq->pbl_chunk_size = info->pbl_chunk_size;
4325 cq->first_pm_pbl_idx = info->first_pm_pbl_idx;
4326 cq->cq_uk.polarity = true;
4327 cq->vsi = info->vsi;
4328 cq->cq_uk.cq_ack_db = cq->dev->cq_ack_db;
4329
4330 /* Only applicable to CQs other than CCQ so initialize to zero */
4331 cq->cq_uk.cqe_alloc_db = NULL;
4332
4333 info->dev->ccq = cq;
4334 return 0;
4335 }
4336
4337 /**
4338 * irdma_sc_ccq_create_done - poll cqp for ccq create
4339 * @ccq: ccq sc struct
4340 */
4341 static inline int
irdma_sc_ccq_create_done(struct irdma_sc_cq * ccq)4342 irdma_sc_ccq_create_done(struct irdma_sc_cq *ccq)
4343 {
4344 struct irdma_sc_cqp *cqp;
4345
4346 cqp = ccq->dev->cqp;
4347
4348 return irdma_sc_poll_for_cqp_op_done(cqp, IRDMA_CQP_OP_CREATE_CQ, NULL);
4349 }
4350
4351 /**
4352 * irdma_sc_ccq_create - create control cq
4353 * @ccq: ccq sc struct
4354 * @scratch: u64 saved to be used during cqp completion
4355 * @check_overflow: overlow flag for ccq
4356 * @post_sq: flag for cqp db to ring
4357 */
4358 int
irdma_sc_ccq_create(struct irdma_sc_cq * ccq,u64 scratch,bool check_overflow,bool post_sq)4359 irdma_sc_ccq_create(struct irdma_sc_cq *ccq, u64 scratch,
4360 bool check_overflow, bool post_sq)
4361 {
4362 int ret_code;
4363
4364 ret_code = irdma_sc_cq_create(ccq, scratch, check_overflow, post_sq);
4365 if (ret_code)
4366 return ret_code;
4367
4368 if (post_sq) {
4369 ret_code = irdma_sc_ccq_create_done(ccq);
4370 if (ret_code)
4371 return ret_code;
4372 }
4373 ccq->dev->cqp->process_cqp_sds = irdma_cqp_sds_cmd;
4374
4375 return 0;
4376 }
4377
4378 /**
4379 * irdma_sc_ccq_destroy - destroy ccq during close
4380 * @ccq: ccq sc struct
4381 * @scratch: u64 saved to be used during cqp completion
4382 * @post_sq: flag for cqp db to ring
4383 */
4384 int
irdma_sc_ccq_destroy(struct irdma_sc_cq * ccq,u64 scratch,bool post_sq)4385 irdma_sc_ccq_destroy(struct irdma_sc_cq *ccq, u64 scratch, bool post_sq)
4386 {
4387 struct irdma_sc_cqp *cqp;
4388 __le64 *wqe;
4389 u64 hdr;
4390 int ret_code = 0;
4391 u32 tail, val, error;
4392
4393 cqp = ccq->dev->cqp;
4394 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
4395 if (!wqe)
4396 return -ENOSPC;
4397
4398 set_64bit_val(wqe, IRDMA_BYTE_0, ccq->cq_uk.cq_size);
4399 set_64bit_val(wqe, IRDMA_BYTE_8, RS_64_1(ccq, 1));
4400 set_64bit_val(wqe, IRDMA_BYTE_40, ccq->shadow_area_pa);
4401
4402 hdr = ccq->cq_uk.cq_id |
4403 FLD_LS_64(ccq->dev, (ccq->ceq_id_valid ? ccq->ceq_id : 0),
4404 IRDMA_CQPSQ_CQ_CEQID) |
4405 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DESTROY_CQ) |
4406 FIELD_PREP(IRDMA_CQPSQ_CQ_ENCEQEMASK, ccq->ceqe_mask) |
4407 FIELD_PREP(IRDMA_CQPSQ_CQ_CEQIDVALID, ccq->ceq_id_valid) |
4408 FIELD_PREP(IRDMA_CQPSQ_TPHEN, ccq->tph_en) |
4409 FIELD_PREP(IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT, ccq->cq_uk.avoid_mem_cflct) |
4410 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
4411 irdma_wmb(); /* make sure WQE is written before valid bit is set */
4412
4413 set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
4414
4415 irdma_debug_buf(cqp->dev, IRDMA_DEBUG_WQE, "CCQ_DESTROY WQE", wqe,
4416 IRDMA_CQP_WQE_SIZE * 8);
4417 irdma_get_cqp_reg_info(cqp, &val, &tail, &error);
4418
4419 if (post_sq) {
4420 irdma_sc_cqp_post_sq(cqp);
4421 ret_code = irdma_cqp_poll_registers(cqp, tail,
4422 cqp->dev->hw_attrs.max_done_count);
4423 }
4424
4425 cqp->process_cqp_sds = irdma_update_sds_noccq;
4426
4427 return ret_code;
4428 }
4429
4430 /**
4431 * irdma_sc_init_iw_hmc() - queries fpm values using cqp and populates hmc_info
4432 * @dev : ptr to irdma_dev struct
4433 * @hmc_fn_id: hmc function id
4434 */
4435 int
irdma_sc_init_iw_hmc(struct irdma_sc_dev * dev,u16 hmc_fn_id)4436 irdma_sc_init_iw_hmc(struct irdma_sc_dev *dev, u16 hmc_fn_id)
4437 {
4438 struct irdma_hmc_info *hmc_info;
4439 struct irdma_hmc_fpm_misc *hmc_fpm_misc;
4440 struct irdma_dma_mem query_fpm_mem;
4441 int ret_code = 0;
4442 u8 wait_type;
4443
4444 hmc_info = dev->hmc_info;
4445 hmc_fpm_misc = &dev->hmc_fpm_misc;
4446 query_fpm_mem.pa = dev->fpm_query_buf_pa;
4447 query_fpm_mem.va = dev->fpm_query_buf;
4448 hmc_info->hmc_fn_id = hmc_fn_id;
4449 wait_type = (u8)IRDMA_CQP_WAIT_POLL_REGS;
4450
4451 ret_code = irdma_sc_query_fpm_val(dev->cqp, 0, hmc_info->hmc_fn_id,
4452 &query_fpm_mem, true, wait_type);
4453 if (ret_code)
4454 return ret_code;
4455
4456 /* parse the fpm_query_buf and fill hmc obj info */
4457 ret_code = irdma_sc_parse_fpm_query_buf(dev, query_fpm_mem.va, hmc_info,
4458 hmc_fpm_misc);
4459
4460 irdma_debug_buf(dev, IRDMA_DEBUG_HMC, "QUERY FPM BUFFER",
4461 query_fpm_mem.va, IRDMA_QUERY_FPM_BUF_SIZE);
4462 return ret_code;
4463 }
4464
4465 /**
4466 * irdma_sc_cfg_iw_fpm() - commits hmc obj cnt values using cqp
4467 * command and populates fpm base address in hmc_info
4468 * @dev : ptr to irdma_dev struct
4469 * @hmc_fn_id: hmc function id
4470 */
4471 static int
irdma_sc_cfg_iw_fpm(struct irdma_sc_dev * dev,u16 hmc_fn_id)4472 irdma_sc_cfg_iw_fpm(struct irdma_sc_dev *dev, u16 hmc_fn_id)
4473 {
4474 struct irdma_hmc_obj_info *obj_info;
4475 __le64 *buf;
4476 struct irdma_hmc_info *hmc_info;
4477 struct irdma_dma_mem commit_fpm_mem;
4478 int ret_code = 0;
4479 u8 wait_type;
4480
4481 hmc_info = dev->hmc_info;
4482 obj_info = hmc_info->hmc_obj;
4483 buf = dev->fpm_commit_buf;
4484
4485 set_64bit_val(buf, IRDMA_BYTE_0, (u64)obj_info[IRDMA_HMC_IW_QP].cnt);
4486 set_64bit_val(buf, IRDMA_BYTE_8, (u64)obj_info[IRDMA_HMC_IW_CQ].cnt);
4487 set_64bit_val(buf, IRDMA_BYTE_16, (u64)0); /* RSRVD */
4488 set_64bit_val(buf, IRDMA_BYTE_24, (u64)obj_info[IRDMA_HMC_IW_HTE].cnt);
4489 set_64bit_val(buf, IRDMA_BYTE_32, (u64)obj_info[IRDMA_HMC_IW_ARP].cnt);
4490 set_64bit_val(buf, IRDMA_BYTE_40, (u64)0); /* RSVD */
4491 set_64bit_val(buf, IRDMA_BYTE_48, (u64)obj_info[IRDMA_HMC_IW_MR].cnt);
4492 set_64bit_val(buf, IRDMA_BYTE_56, (u64)obj_info[IRDMA_HMC_IW_XF].cnt);
4493 set_64bit_val(buf, IRDMA_BYTE_64, (u64)obj_info[IRDMA_HMC_IW_XFFL].cnt);
4494 set_64bit_val(buf, IRDMA_BYTE_72, (u64)obj_info[IRDMA_HMC_IW_Q1].cnt);
4495 set_64bit_val(buf, IRDMA_BYTE_80, (u64)obj_info[IRDMA_HMC_IW_Q1FL].cnt);
4496 set_64bit_val(buf, IRDMA_BYTE_88,
4497 (u64)obj_info[IRDMA_HMC_IW_TIMER].cnt);
4498 set_64bit_val(buf, IRDMA_BYTE_96,
4499 (u64)obj_info[IRDMA_HMC_IW_FSIMC].cnt);
4500 set_64bit_val(buf, IRDMA_BYTE_104,
4501 (u64)obj_info[IRDMA_HMC_IW_FSIAV].cnt);
4502 set_64bit_val(buf, IRDMA_BYTE_112,
4503 (u64)obj_info[IRDMA_HMC_IW_PBLE].cnt);
4504 set_64bit_val(buf, IRDMA_BYTE_120, (u64)0); /* RSVD */
4505 set_64bit_val(buf, IRDMA_BYTE_128, (u64)obj_info[IRDMA_HMC_IW_RRF].cnt);
4506 set_64bit_val(buf, IRDMA_BYTE_136,
4507 (u64)obj_info[IRDMA_HMC_IW_RRFFL].cnt);
4508 set_64bit_val(buf, IRDMA_BYTE_144, (u64)obj_info[IRDMA_HMC_IW_HDR].cnt);
4509 set_64bit_val(buf, IRDMA_BYTE_152, (u64)obj_info[IRDMA_HMC_IW_MD].cnt);
4510 set_64bit_val(buf, IRDMA_BYTE_160,
4511 (u64)obj_info[IRDMA_HMC_IW_OOISC].cnt);
4512 set_64bit_val(buf, IRDMA_BYTE_168,
4513 (u64)obj_info[IRDMA_HMC_IW_OOISCFFL].cnt);
4514 commit_fpm_mem.pa = dev->fpm_commit_buf_pa;
4515 commit_fpm_mem.va = dev->fpm_commit_buf;
4516
4517 wait_type = (u8)IRDMA_CQP_WAIT_POLL_REGS;
4518 irdma_debug_buf(dev, IRDMA_DEBUG_HMC, "COMMIT FPM BUFFER",
4519 commit_fpm_mem.va, IRDMA_COMMIT_FPM_BUF_SIZE);
4520 ret_code = irdma_sc_commit_fpm_val(dev->cqp, 0, hmc_info->hmc_fn_id,
4521 &commit_fpm_mem, true, wait_type);
4522 if (!ret_code)
4523 irdma_sc_parse_fpm_commit_buf(dev, dev->fpm_commit_buf,
4524 hmc_info->hmc_obj,
4525 &hmc_info->sd_table.sd_cnt);
4526 irdma_debug_buf(dev, IRDMA_DEBUG_HMC, "COMMIT FPM BUFFER",
4527 commit_fpm_mem.va, IRDMA_COMMIT_FPM_BUF_SIZE);
4528
4529 return ret_code;
4530 }
4531
4532 /**
4533 * cqp_sds_wqe_fill - fill cqp wqe doe sd
4534 * @cqp: struct for cqp hw
4535 * @info: sd info for wqe
4536 * @scratch: u64 saved to be used during cqp completion
4537 */
4538 static int
cqp_sds_wqe_fill(struct irdma_sc_cqp * cqp,struct irdma_update_sds_info * info,u64 scratch)4539 cqp_sds_wqe_fill(struct irdma_sc_cqp *cqp,
4540 struct irdma_update_sds_info *info, u64 scratch)
4541 {
4542 u64 data;
4543 u64 hdr;
4544 __le64 *wqe;
4545 int mem_entries, wqe_entries;
4546 struct irdma_dma_mem *sdbuf = &cqp->sdbuf;
4547 u64 offset = 0;
4548 u32 wqe_idx;
4549
4550 wqe = irdma_sc_cqp_get_next_send_wqe_idx(cqp, scratch, &wqe_idx);
4551 if (!wqe)
4552 return -ENOSPC;
4553
4554 wqe_entries = (info->cnt > 3) ? 3 : info->cnt;
4555 mem_entries = info->cnt - wqe_entries;
4556
4557 if (mem_entries) {
4558 offset = wqe_idx * IRDMA_UPDATE_SD_BUFF_SIZE;
4559 irdma_memcpy(((char *)sdbuf->va + offset), &info->entry[3], mem_entries << 4);
4560
4561 data = (u64)sdbuf->pa + offset;
4562 } else {
4563 data = 0;
4564 }
4565 data |= FLD_LS_64(cqp->dev, info->hmc_fn_id, IRDMA_CQPSQ_UPESD_HMCFNID);
4566 set_64bit_val(wqe, IRDMA_BYTE_16, data);
4567
4568 switch (wqe_entries) {
4569 case 3:
4570 set_64bit_val(wqe, IRDMA_BYTE_48,
4571 (FIELD_PREP(IRDMA_CQPSQ_UPESD_SDCMD, info->entry[2].cmd) |
4572 FIELD_PREP(IRDMA_CQPSQ_UPESD_ENTRY_VALID, 1)));
4573
4574 set_64bit_val(wqe, IRDMA_BYTE_56, info->entry[2].data);
4575 /* fallthrough */
4576 case 2:
4577 set_64bit_val(wqe, IRDMA_BYTE_32,
4578 (FIELD_PREP(IRDMA_CQPSQ_UPESD_SDCMD, info->entry[1].cmd) |
4579 FIELD_PREP(IRDMA_CQPSQ_UPESD_ENTRY_VALID, 1)));
4580
4581 set_64bit_val(wqe, IRDMA_BYTE_40, info->entry[1].data);
4582 /* fallthrough */
4583 case 1:
4584 set_64bit_val(wqe, IRDMA_BYTE_0,
4585 FIELD_PREP(IRDMA_CQPSQ_UPESD_SDCMD, info->entry[0].cmd));
4586
4587 set_64bit_val(wqe, IRDMA_BYTE_8, info->entry[0].data);
4588 break;
4589 default:
4590 break;
4591 }
4592
4593 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_UPDATE_PE_SDS) |
4594 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity) |
4595 FIELD_PREP(IRDMA_CQPSQ_UPESD_ENTRY_COUNT, mem_entries);
4596 irdma_wmb(); /* make sure WQE is written before valid bit is set */
4597
4598 set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
4599
4600 if (mem_entries)
4601 irdma_debug_buf(cqp->dev, IRDMA_DEBUG_WQE, "UPDATE_PE_SDS WQE Buffer",
4602 (char *)sdbuf->va + offset, mem_entries << 4);
4603
4604 irdma_debug_buf(cqp->dev, IRDMA_DEBUG_WQE, "UPDATE_PE_SDS WQE", wqe,
4605 IRDMA_CQP_WQE_SIZE * 8);
4606
4607 return 0;
4608 }
4609
4610 /**
4611 * irdma_update_pe_sds - cqp wqe for sd
4612 * @dev: ptr to irdma_dev struct
4613 * @info: sd info for sd's
4614 * @scratch: u64 saved to be used during cqp completion
4615 */
4616 static int
irdma_update_pe_sds(struct irdma_sc_dev * dev,struct irdma_update_sds_info * info,u64 scratch)4617 irdma_update_pe_sds(struct irdma_sc_dev *dev,
4618 struct irdma_update_sds_info *info, u64 scratch)
4619 {
4620 struct irdma_sc_cqp *cqp = dev->cqp;
4621 int ret_code;
4622
4623 ret_code = cqp_sds_wqe_fill(cqp, info, scratch);
4624 if (!ret_code)
4625 irdma_sc_cqp_post_sq(cqp);
4626
4627 return ret_code;
4628 }
4629
4630 /**
4631 * irdma_update_sds_noccq - update sd before ccq created
4632 * @dev: sc device struct
4633 * @info: sd info for sd's
4634 */
4635 int
irdma_update_sds_noccq(struct irdma_sc_dev * dev,struct irdma_update_sds_info * info)4636 irdma_update_sds_noccq(struct irdma_sc_dev *dev,
4637 struct irdma_update_sds_info *info)
4638 {
4639 u32 error, val, tail;
4640 struct irdma_sc_cqp *cqp = dev->cqp;
4641 int ret_code;
4642
4643 ret_code = cqp_sds_wqe_fill(cqp, info, 0);
4644 if (ret_code)
4645 return ret_code;
4646
4647 irdma_get_cqp_reg_info(cqp, &val, &tail, &error);
4648
4649 irdma_sc_cqp_post_sq(cqp);
4650 return irdma_cqp_poll_registers(cqp, tail,
4651 cqp->dev->hw_attrs.max_done_count);
4652 }
4653
4654 /**
4655 * irdma_sc_static_hmc_pages_allocated - cqp wqe to allocate hmc pages
4656 * @cqp: struct for cqp hw
4657 * @scratch: u64 saved to be used during cqp completion
4658 * @hmc_fn_id: hmc function id
4659 * @post_sq: flag for cqp db to ring
4660 * @poll_registers: flag to poll register for cqp completion
4661 */
4662 int
irdma_sc_static_hmc_pages_allocated(struct irdma_sc_cqp * cqp,u64 scratch,u16 hmc_fn_id,bool post_sq,bool poll_registers)4663 irdma_sc_static_hmc_pages_allocated(struct irdma_sc_cqp *cqp, u64 scratch,
4664 u16 hmc_fn_id, bool post_sq,
4665 bool poll_registers)
4666 {
4667 u64 hdr;
4668 __le64 *wqe;
4669 u32 tail, val, error;
4670
4671 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
4672 if (!wqe)
4673 return -ENOSPC;
4674
4675 set_64bit_val(wqe, IRDMA_BYTE_16,
4676 FIELD_PREP(IRDMA_SHMC_PAGE_ALLOCATED_HMC_FN_ID, hmc_fn_id));
4677
4678 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE,
4679 IRDMA_CQP_OP_SHMC_PAGES_ALLOCATED) |
4680 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
4681 irdma_wmb(); /* make sure WQE is written before valid bit is set */
4682
4683 set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
4684
4685 irdma_debug_buf(cqp->dev, IRDMA_DEBUG_WQE, "SHMC_PAGES_ALLOCATED WQE",
4686 wqe, IRDMA_CQP_WQE_SIZE * 8);
4687 irdma_get_cqp_reg_info(cqp, &val, &tail, &error);
4688
4689 if (post_sq) {
4690 irdma_sc_cqp_post_sq(cqp);
4691 if (poll_registers)
4692 /* check for cqp sq tail update */
4693 return irdma_cqp_poll_registers(cqp, tail,
4694 cqp->dev->hw_attrs.max_done_count);
4695 else
4696 return irdma_sc_poll_for_cqp_op_done(cqp,
4697 IRDMA_CQP_OP_SHMC_PAGES_ALLOCATED,
4698 NULL);
4699 }
4700
4701 return 0;
4702 }
4703
4704 /**
4705 * irdma_cqp_ring_full - check if cqp ring is full
4706 * @cqp: struct for cqp hw
4707 */
4708 static bool
irdma_cqp_ring_full(struct irdma_sc_cqp * cqp)4709 irdma_cqp_ring_full(struct irdma_sc_cqp *cqp)
4710 {
4711 return IRDMA_RING_FULL_ERR(cqp->sq_ring);
4712 }
4713
4714 /**
4715 * irdma_est_sd - returns approximate number of SDs for HMC
4716 * @dev: sc device struct
4717 * @hmc_info: hmc structure, size and count for HMC objects
4718 */
irdma_est_sd(struct irdma_sc_dev * dev,struct irdma_hmc_info * hmc_info)4719 static u32 irdma_est_sd(struct irdma_sc_dev *dev,
4720 struct irdma_hmc_info *hmc_info){
4721 struct irdma_hmc_obj_info *pble_info;
4722 u64 size = 0;
4723 u64 sd;
4724 int i;
4725
4726 for (i = IRDMA_HMC_IW_QP; i < IRDMA_HMC_IW_MAX; i++) {
4727 if (i != IRDMA_HMC_IW_PBLE)
4728 size += round_up(hmc_info->hmc_obj[i].cnt *
4729 hmc_info->hmc_obj[i].size, 512);
4730 }
4731
4732 pble_info = &hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE];
4733 size += round_up(pble_info->cnt * pble_info->size, 512);
4734 if (size & 0x1FFFFF)
4735 sd = (size >> 21) + 1; /* add 1 for remainder */
4736 else
4737 sd = size >> 21;
4738 if (sd > 0xFFFFFFFF) {
4739 irdma_debug(dev, IRDMA_DEBUG_HMC, "sd overflow[%ld]\n", sd);
4740 sd = 0xFFFFFFFE;
4741 }
4742
4743 return (u32)sd;
4744 }
4745
4746 /**
4747 * irdma_sc_query_rdma_features - query RDMA features and FW ver
4748 * @cqp: struct for cqp hw
4749 * @buf: buffer to hold query info
4750 * @scratch: u64 saved to be used during cqp completion
4751 */
4752 static int
irdma_sc_query_rdma_features(struct irdma_sc_cqp * cqp,struct irdma_dma_mem * buf,u64 scratch)4753 irdma_sc_query_rdma_features(struct irdma_sc_cqp *cqp,
4754 struct irdma_dma_mem *buf, u64 scratch)
4755 {
4756 __le64 *wqe;
4757 u64 temp;
4758 u32 tail, val, error;
4759 int status;
4760
4761 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
4762 if (!wqe)
4763 return -ENOSPC;
4764
4765 temp = buf->pa;
4766 set_64bit_val(wqe, IRDMA_BYTE_32, temp);
4767
4768 temp = FIELD_PREP(IRDMA_CQPSQ_QUERY_RDMA_FEATURES_WQEVALID,
4769 cqp->polarity) |
4770 FIELD_PREP(IRDMA_CQPSQ_QUERY_RDMA_FEATURES_BUF_LEN, buf->size) |
4771 FIELD_PREP(IRDMA_CQPSQ_UP_OP, IRDMA_CQP_OP_QUERY_RDMA_FEATURES);
4772 irdma_wmb(); /* make sure WQE is written before valid bit is set */
4773
4774 set_64bit_val(wqe, IRDMA_BYTE_24, temp);
4775
4776 irdma_debug_buf(cqp->dev, IRDMA_DEBUG_WQE, "QUERY RDMA FEATURES", wqe,
4777 IRDMA_CQP_WQE_SIZE * 8);
4778 irdma_get_cqp_reg_info(cqp, &val, &tail, &error);
4779
4780 irdma_sc_cqp_post_sq(cqp);
4781 status = irdma_cqp_poll_registers(cqp, tail,
4782 cqp->dev->hw_attrs.max_done_count);
4783 if (error || status)
4784 status = -EIO;
4785
4786 return status;
4787 }
4788
4789 /**
4790 * irdma_get_rdma_features - get RDMA features
4791 * @dev: sc device struct
4792 */
4793 int
irdma_get_rdma_features(struct irdma_sc_dev * dev)4794 irdma_get_rdma_features(struct irdma_sc_dev *dev)
4795 {
4796 int ret_code, byte_idx, feat_type, feat_cnt, feat_idx;
4797 struct irdma_dma_mem feat_buf;
4798 u64 temp;
4799
4800 feat_buf.size = IRDMA_FEATURE_BUF_SIZE;
4801 feat_buf.va = irdma_allocate_dma_mem(dev->hw, &feat_buf, feat_buf.size,
4802 IRDMA_FEATURE_BUF_ALIGNMENT);
4803 if (!feat_buf.va)
4804 return -ENOMEM;
4805
4806 ret_code = irdma_sc_query_rdma_features(dev->cqp, &feat_buf, 0);
4807 if (ret_code)
4808 goto exit;
4809
4810 get_64bit_val(feat_buf.va, IRDMA_BYTE_0, &temp);
4811 feat_cnt = (u16)FIELD_GET(IRDMA_FEATURE_CNT, temp);
4812 if (feat_cnt < IRDMA_MIN_FEATURES) {
4813 ret_code = -EINVAL;
4814 goto exit;
4815 } else if (feat_cnt > IRDMA_MAX_FEATURES) {
4816 irdma_debug(dev, IRDMA_DEBUG_DEV,
4817 "feature buf size insufficient, retrying with larger buffer\n");
4818 irdma_free_dma_mem(dev->hw, &feat_buf);
4819 feat_buf.size = 8 * feat_cnt;
4820 feat_buf.va = irdma_allocate_dma_mem(dev->hw, &feat_buf,
4821 feat_buf.size,
4822 IRDMA_FEATURE_BUF_ALIGNMENT);
4823 if (!feat_buf.va)
4824 return -ENOMEM;
4825
4826 ret_code = irdma_sc_query_rdma_features(dev->cqp, &feat_buf, 0);
4827 if (ret_code)
4828 goto exit;
4829
4830 get_64bit_val(feat_buf.va, IRDMA_BYTE_0, &temp);
4831 feat_cnt = (u16)FIELD_GET(IRDMA_FEATURE_CNT, temp);
4832 if (feat_cnt < IRDMA_MIN_FEATURES) {
4833 ret_code = -EINVAL;
4834 goto exit;
4835 }
4836 }
4837
4838 irdma_debug_buf(dev, IRDMA_DEBUG_WQE, "QUERY RDMA FEATURES", feat_buf.va,
4839 feat_cnt * 8);
4840
4841 for (byte_idx = 0, feat_idx = 0; feat_idx < min(feat_cnt, IRDMA_MAX_FEATURES);
4842 feat_idx++, byte_idx += 8) {
4843 get_64bit_val(feat_buf.va, byte_idx, &temp);
4844 feat_type = FIELD_GET(IRDMA_FEATURE_TYPE, temp);
4845 dev->feature_info[feat_type] = temp;
4846 }
4847 exit:
4848 irdma_free_dma_mem(dev->hw, &feat_buf);
4849 return ret_code;
4850 }
4851
irdma_q1_cnt(struct irdma_sc_dev * dev,struct irdma_hmc_info * hmc_info,u32 qpwanted)4852 static u32 irdma_q1_cnt(struct irdma_sc_dev *dev,
4853 struct irdma_hmc_info *hmc_info, u32 qpwanted){
4854 u32 q1_cnt;
4855
4856 if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) {
4857 q1_cnt = roundup_pow_of_two(dev->hw_attrs.max_hw_ird * 2 * qpwanted);
4858 } else {
4859 if (dev->cqp->protocol_used != IRDMA_IWARP_PROTOCOL_ONLY)
4860 q1_cnt = roundup_pow_of_two(dev->hw_attrs.max_hw_ird * 2 * qpwanted + 512);
4861 else
4862 q1_cnt = dev->hw_attrs.max_hw_ird * 2 * qpwanted;
4863 }
4864
4865 return q1_cnt;
4866 }
4867
4868 static void
cfg_fpm_value_gen_1(struct irdma_sc_dev * dev,struct irdma_hmc_info * hmc_info,u32 qpwanted)4869 cfg_fpm_value_gen_1(struct irdma_sc_dev *dev,
4870 struct irdma_hmc_info *hmc_info, u32 qpwanted)
4871 {
4872 hmc_info->hmc_obj[IRDMA_HMC_IW_XF].cnt = roundup_pow_of_two(qpwanted * dev->hw_attrs.max_hw_wqes);
4873 }
4874
4875 static void
cfg_fpm_value_gen_2(struct irdma_sc_dev * dev,struct irdma_hmc_info * hmc_info,u32 qpwanted)4876 cfg_fpm_value_gen_2(struct irdma_sc_dev *dev,
4877 struct irdma_hmc_info *hmc_info, u32 qpwanted)
4878 {
4879 struct irdma_hmc_fpm_misc *hmc_fpm_misc = &dev->hmc_fpm_misc;
4880
4881 hmc_info->hmc_obj[IRDMA_HMC_IW_XF].cnt =
4882 4 * hmc_fpm_misc->xf_block_size * qpwanted;
4883
4884 hmc_info->hmc_obj[IRDMA_HMC_IW_HDR].cnt = qpwanted;
4885
4886 if (hmc_info->hmc_obj[IRDMA_HMC_IW_RRF].max_cnt)
4887 hmc_info->hmc_obj[IRDMA_HMC_IW_RRF].cnt = 32 * qpwanted;
4888 if (hmc_info->hmc_obj[IRDMA_HMC_IW_RRFFL].max_cnt)
4889 hmc_info->hmc_obj[IRDMA_HMC_IW_RRFFL].cnt =
4890 hmc_info->hmc_obj[IRDMA_HMC_IW_RRF].cnt /
4891 hmc_fpm_misc->rrf_block_size;
4892 if (dev->cqp->protocol_used == IRDMA_IWARP_PROTOCOL_ONLY) {
4893 if (hmc_info->hmc_obj[IRDMA_HMC_IW_OOISC].max_cnt)
4894 hmc_info->hmc_obj[IRDMA_HMC_IW_OOISC].cnt = 32 * qpwanted;
4895 if (hmc_info->hmc_obj[IRDMA_HMC_IW_OOISCFFL].max_cnt)
4896 hmc_info->hmc_obj[IRDMA_HMC_IW_OOISCFFL].cnt =
4897 hmc_info->hmc_obj[IRDMA_HMC_IW_OOISC].cnt /
4898 hmc_fpm_misc->ooiscf_block_size;
4899 }
4900 }
4901
4902 /**
4903 * irdma_cfg_fpm_val - configure HMC objects
4904 * @dev: sc device struct
4905 * @qp_count: desired qp count
4906 */
4907 int
irdma_cfg_fpm_val(struct irdma_sc_dev * dev,u32 qp_count)4908 irdma_cfg_fpm_val(struct irdma_sc_dev *dev, u32 qp_count)
4909 {
4910 struct irdma_virt_mem virt_mem;
4911 u32 i, mem_size;
4912 u32 qpwanted, mrwanted, pblewanted;
4913 u32 powerof2, hte;
4914 u32 sd_needed;
4915 u32 sd_diff;
4916 u32 loop_count = 0;
4917 struct irdma_hmc_info *hmc_info;
4918 struct irdma_hmc_fpm_misc *hmc_fpm_misc;
4919 int ret_code = 0;
4920 u32 max_sds;
4921
4922 hmc_info = dev->hmc_info;
4923 hmc_fpm_misc = &dev->hmc_fpm_misc;
4924 ret_code = irdma_sc_init_iw_hmc(dev, dev->hmc_fn_id);
4925 if (ret_code) {
4926 irdma_debug(dev, IRDMA_DEBUG_HMC,
4927 "irdma_sc_init_iw_hmc returned error_code = %d\n",
4928 ret_code);
4929 return ret_code;
4930 }
4931
4932 max_sds = hmc_fpm_misc->max_sds;
4933
4934 for (i = IRDMA_HMC_IW_QP; i < IRDMA_HMC_IW_MAX; i++)
4935 hmc_info->hmc_obj[i].cnt = hmc_info->hmc_obj[i].max_cnt;
4936
4937 sd_needed = irdma_est_sd(dev, hmc_info);
4938 irdma_debug(dev, IRDMA_DEBUG_HMC, "sd count %d where max sd is %d\n",
4939 hmc_info->sd_table.sd_cnt, max_sds);
4940
4941 qpwanted = min(qp_count, hmc_info->hmc_obj[IRDMA_HMC_IW_QP].max_cnt);
4942
4943 powerof2 = 1;
4944 while (powerof2 <= qpwanted)
4945 powerof2 *= 2;
4946 powerof2 /= 2;
4947 qpwanted = powerof2;
4948
4949 mrwanted = hmc_info->hmc_obj[IRDMA_HMC_IW_MR].max_cnt;
4950 pblewanted = hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].max_cnt;
4951
4952 irdma_debug(dev, IRDMA_DEBUG_HMC,
4953 "req_qp=%d max_sd=%d, max_qp = %d, max_cq=%d, max_mr=%d, max_pble=%d, mc=%d, av=%d\n",
4954 qp_count, max_sds,
4955 hmc_info->hmc_obj[IRDMA_HMC_IW_QP].max_cnt,
4956 hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].max_cnt,
4957 hmc_info->hmc_obj[IRDMA_HMC_IW_MR].max_cnt,
4958 hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].max_cnt,
4959 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].max_cnt,
4960 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].max_cnt);
4961 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].cnt =
4962 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].max_cnt;
4963 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt =
4964 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].max_cnt;
4965 hmc_info->hmc_obj[IRDMA_HMC_IW_ARP].cnt =
4966 hmc_info->hmc_obj[IRDMA_HMC_IW_ARP].max_cnt;
4967 if (dev->hw_attrs.uk_attrs.hw_rev <= IRDMA_GEN_2)
4968 hmc_info->hmc_obj[IRDMA_HMC_IW_APBVT_ENTRY].cnt = 1;
4969
4970 while (irdma_q1_cnt(dev, hmc_info, qpwanted) > hmc_info->hmc_obj[IRDMA_HMC_IW_Q1].max_cnt)
4971 qpwanted /= 2;
4972
4973 if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) {
4974 cfg_fpm_value_gen_1(dev, hmc_info, qpwanted);
4975 while (hmc_info->hmc_obj[IRDMA_HMC_IW_XF].cnt > hmc_info->hmc_obj[IRDMA_HMC_IW_XF].max_cnt) {
4976 qpwanted /= 2;
4977 cfg_fpm_value_gen_1(dev, hmc_info, qpwanted);
4978 }
4979 }
4980
4981 do {
4982 ++loop_count;
4983 hmc_info->hmc_obj[IRDMA_HMC_IW_QP].cnt = qpwanted;
4984 hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt =
4985 min(2 * qpwanted, hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt);
4986 hmc_info->hmc_obj[IRDMA_HMC_IW_RESERVED].cnt = 0; /* Reserved */
4987 hmc_info->hmc_obj[IRDMA_HMC_IW_MR].cnt = mrwanted;
4988
4989 hte = round_up(qpwanted + hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].cnt, 512);
4990 powerof2 = 1;
4991 while (powerof2 < hte)
4992 powerof2 *= 2;
4993 hmc_info->hmc_obj[IRDMA_HMC_IW_HTE].cnt =
4994 powerof2 * hmc_fpm_misc->ht_multiplier;
4995 if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1)
4996 cfg_fpm_value_gen_1(dev, hmc_info, qpwanted);
4997 else
4998 cfg_fpm_value_gen_2(dev, hmc_info, qpwanted);
4999
5000 hmc_info->hmc_obj[IRDMA_HMC_IW_Q1].cnt = irdma_q1_cnt(dev, hmc_info, qpwanted);
5001 hmc_info->hmc_obj[IRDMA_HMC_IW_XFFL].cnt =
5002 hmc_info->hmc_obj[IRDMA_HMC_IW_XF].cnt / hmc_fpm_misc->xf_block_size;
5003 hmc_info->hmc_obj[IRDMA_HMC_IW_Q1FL].cnt =
5004 hmc_info->hmc_obj[IRDMA_HMC_IW_Q1].cnt / hmc_fpm_misc->q1_block_size;
5005 hmc_info->hmc_obj[IRDMA_HMC_IW_TIMER].cnt =
5006 (round_up(qpwanted, 512) / 512 + 1) * hmc_fpm_misc->timer_bucket;
5007
5008 hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt = pblewanted;
5009 sd_needed = irdma_est_sd(dev, hmc_info);
5010 irdma_debug(dev, IRDMA_DEBUG_HMC,
5011 "sd_needed = %d, max_sds=%d, mrwanted=%d, pblewanted=%d qpwanted=%d\n",
5012 sd_needed, max_sds, mrwanted, pblewanted, qpwanted);
5013
5014 /* Do not reduce resources further. All objects fit with max SDs */
5015 if (sd_needed <= max_sds)
5016 break;
5017
5018 sd_diff = sd_needed - max_sds;
5019 if (sd_diff > 128) {
5020 if (!(loop_count % 2) && qpwanted > 128) {
5021 qpwanted /= 2;
5022 } else {
5023 mrwanted /= 2;
5024 pblewanted /= 2;
5025 }
5026 continue;
5027 }
5028 if (dev->cqp->hmc_profile != IRDMA_HMC_PROFILE_FAVOR_VF &&
5029 pblewanted > (512 * FPM_MULTIPLIER * sd_diff)) {
5030 pblewanted -= 256 * FPM_MULTIPLIER * sd_diff;
5031 continue;
5032 } else if (pblewanted > 100 * FPM_MULTIPLIER) {
5033 pblewanted -= 10 * FPM_MULTIPLIER;
5034 } else if (pblewanted > 16 * FPM_MULTIPLIER) {
5035 pblewanted -= FPM_MULTIPLIER;
5036 } else if (qpwanted <= 128) {
5037 if (hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].cnt > 256)
5038 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].cnt /= 2;
5039 if (hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt > 256)
5040 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt /= 2;
5041 }
5042 if (mrwanted > FPM_MULTIPLIER)
5043 mrwanted -= FPM_MULTIPLIER;
5044 if (!(loop_count % 10) && qpwanted > 128) {
5045 qpwanted /= 2;
5046 if (hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt > 256)
5047 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt /= 2;
5048 }
5049 } while (loop_count < 2000);
5050
5051 if (sd_needed > max_sds) {
5052 irdma_debug(dev, IRDMA_DEBUG_HMC,
5053 "cfg_fpm failed loop_cnt=%d, sd_needed=%d, max sd count %d\n",
5054 loop_count, sd_needed, hmc_info->sd_table.sd_cnt);
5055 return -EINVAL;
5056 }
5057
5058 if (loop_count > 1 && sd_needed < max_sds) {
5059 pblewanted += (max_sds - sd_needed) * 256 * FPM_MULTIPLIER;
5060 hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt = pblewanted;
5061 sd_needed = irdma_est_sd(dev, hmc_info);
5062 }
5063
5064 irdma_debug(dev, IRDMA_DEBUG_HMC,
5065 "loop_cnt=%d, sd_needed=%d, qpcnt = %d, cqcnt=%d, mrcnt=%d, pblecnt=%d, mc=%d, ah=%d, max sd count %d, first sd index %d\n",
5066 loop_count, sd_needed,
5067 hmc_info->hmc_obj[IRDMA_HMC_IW_QP].cnt,
5068 hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt,
5069 hmc_info->hmc_obj[IRDMA_HMC_IW_MR].cnt,
5070 hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt,
5071 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].cnt,
5072 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt,
5073 hmc_info->sd_table.sd_cnt, hmc_info->first_sd_index);
5074
5075 ret_code = irdma_sc_cfg_iw_fpm(dev, dev->hmc_fn_id);
5076 if (ret_code) {
5077 irdma_debug(dev, IRDMA_DEBUG_HMC,
5078 "cfg_iw_fpm returned error_code[x%08X]\n",
5079 readl(dev->hw_regs[IRDMA_CQPERRCODES]));
5080 return ret_code;
5081 }
5082
5083 mem_size = sizeof(struct irdma_hmc_sd_entry) *
5084 (hmc_info->sd_table.sd_cnt + hmc_info->first_sd_index + 1);
5085 virt_mem.size = mem_size;
5086 virt_mem.va = kzalloc(virt_mem.size, GFP_KERNEL);
5087 if (!virt_mem.va) {
5088 irdma_debug(dev, IRDMA_DEBUG_HMC,
5089 "failed to allocate memory for sd_entry buffer\n");
5090 return -ENOMEM;
5091 }
5092 hmc_info->sd_table.sd_entry = virt_mem.va;
5093
5094 return ret_code;
5095 }
5096
5097 /**
5098 * irdma_exec_cqp_cmd - execute cqp cmd when wqe are available
5099 * @dev: rdma device
5100 * @pcmdinfo: cqp command info
5101 */
5102 static int
irdma_exec_cqp_cmd(struct irdma_sc_dev * dev,struct cqp_cmds_info * pcmdinfo)5103 irdma_exec_cqp_cmd(struct irdma_sc_dev *dev,
5104 struct cqp_cmds_info *pcmdinfo)
5105 {
5106 int status;
5107 struct irdma_dma_mem val_mem;
5108 bool alloc = false;
5109
5110 dev->cqp_cmd_stats[pcmdinfo->cqp_cmd]++;
5111 switch (pcmdinfo->cqp_cmd) {
5112 case IRDMA_OP_CEQ_DESTROY:
5113 status = irdma_sc_ceq_destroy(pcmdinfo->in.u.ceq_destroy.ceq,
5114 pcmdinfo->in.u.ceq_destroy.scratch,
5115 pcmdinfo->post_sq);
5116 break;
5117 case IRDMA_OP_AEQ_DESTROY:
5118 status = irdma_sc_aeq_destroy(pcmdinfo->in.u.aeq_destroy.aeq,
5119 pcmdinfo->in.u.aeq_destroy.scratch,
5120 pcmdinfo->post_sq);
5121 break;
5122 case IRDMA_OP_CEQ_CREATE:
5123 status = irdma_sc_ceq_create(pcmdinfo->in.u.ceq_create.ceq,
5124 pcmdinfo->in.u.ceq_create.scratch,
5125 pcmdinfo->post_sq);
5126 break;
5127 case IRDMA_OP_AEQ_CREATE:
5128 status = irdma_sc_aeq_create(pcmdinfo->in.u.aeq_create.aeq,
5129 pcmdinfo->in.u.aeq_create.scratch,
5130 pcmdinfo->post_sq);
5131 break;
5132 case IRDMA_OP_QP_UPLOAD_CONTEXT:
5133 status = irdma_sc_qp_upload_context(pcmdinfo->in.u.qp_upload_context.dev,
5134 &pcmdinfo->in.u.qp_upload_context.info,
5135 pcmdinfo->in.u.qp_upload_context.scratch,
5136 pcmdinfo->post_sq);
5137 break;
5138 case IRDMA_OP_CQ_CREATE:
5139 status = irdma_sc_cq_create(pcmdinfo->in.u.cq_create.cq,
5140 pcmdinfo->in.u.cq_create.scratch,
5141 pcmdinfo->in.u.cq_create.check_overflow,
5142 pcmdinfo->post_sq);
5143 break;
5144 case IRDMA_OP_CQ_MODIFY:
5145 status = irdma_sc_cq_modify(pcmdinfo->in.u.cq_modify.cq,
5146 &pcmdinfo->in.u.cq_modify.info,
5147 pcmdinfo->in.u.cq_modify.scratch,
5148 pcmdinfo->post_sq);
5149 break;
5150 case IRDMA_OP_CQ_DESTROY:
5151 status = irdma_sc_cq_destroy(pcmdinfo->in.u.cq_destroy.cq,
5152 pcmdinfo->in.u.cq_destroy.scratch,
5153 pcmdinfo->post_sq);
5154 break;
5155 case IRDMA_OP_QP_FLUSH_WQES:
5156 status = irdma_sc_qp_flush_wqes(pcmdinfo->in.u.qp_flush_wqes.qp,
5157 &pcmdinfo->in.u.qp_flush_wqes.info,
5158 pcmdinfo->in.u.qp_flush_wqes.scratch,
5159 pcmdinfo->post_sq);
5160 break;
5161 case IRDMA_OP_GEN_AE:
5162 status = irdma_sc_gen_ae(pcmdinfo->in.u.gen_ae.qp,
5163 &pcmdinfo->in.u.gen_ae.info,
5164 pcmdinfo->in.u.gen_ae.scratch,
5165 pcmdinfo->post_sq);
5166 break;
5167 case IRDMA_OP_MANAGE_PUSH_PAGE:
5168 status = irdma_sc_manage_push_page(pcmdinfo->in.u.manage_push_page.cqp,
5169 &pcmdinfo->in.u.manage_push_page.info,
5170 pcmdinfo->in.u.manage_push_page.scratch,
5171 pcmdinfo->post_sq);
5172 break;
5173 case IRDMA_OP_UPDATE_PE_SDS:
5174 status = irdma_update_pe_sds(pcmdinfo->in.u.update_pe_sds.dev,
5175 &pcmdinfo->in.u.update_pe_sds.info,
5176 pcmdinfo->in.u.update_pe_sds.scratch);
5177 break;
5178 case IRDMA_OP_MANAGE_HMC_PM_FUNC_TABLE:
5179 /* switch to calling through the call table */
5180 status =
5181 irdma_sc_manage_hmc_pm_func_table(pcmdinfo->in.u.manage_hmc_pm.dev->cqp,
5182 &pcmdinfo->in.u.manage_hmc_pm.info,
5183 pcmdinfo->in.u.manage_hmc_pm.scratch,
5184 true);
5185 break;
5186 case IRDMA_OP_SUSPEND:
5187 status = irdma_sc_suspend_qp(pcmdinfo->in.u.suspend_resume.cqp,
5188 pcmdinfo->in.u.suspend_resume.qp,
5189 pcmdinfo->in.u.suspend_resume.scratch);
5190 break;
5191 case IRDMA_OP_RESUME:
5192 status = irdma_sc_resume_qp(pcmdinfo->in.u.suspend_resume.cqp,
5193 pcmdinfo->in.u.suspend_resume.qp,
5194 pcmdinfo->in.u.suspend_resume.scratch);
5195 break;
5196 case IRDMA_OP_QUERY_FPM_VAL:
5197 val_mem.pa = pcmdinfo->in.u.query_fpm_val.fpm_val_pa;
5198 val_mem.va = pcmdinfo->in.u.query_fpm_val.fpm_val_va;
5199 status = irdma_sc_query_fpm_val(pcmdinfo->in.u.query_fpm_val.cqp,
5200 pcmdinfo->in.u.query_fpm_val.scratch,
5201 pcmdinfo->in.u.query_fpm_val.hmc_fn_id,
5202 &val_mem, true, IRDMA_CQP_WAIT_EVENT);
5203 break;
5204 case IRDMA_OP_COMMIT_FPM_VAL:
5205 val_mem.pa = pcmdinfo->in.u.commit_fpm_val.fpm_val_pa;
5206 val_mem.va = pcmdinfo->in.u.commit_fpm_val.fpm_val_va;
5207 status = irdma_sc_commit_fpm_val(pcmdinfo->in.u.commit_fpm_val.cqp,
5208 pcmdinfo->in.u.commit_fpm_val.scratch,
5209 pcmdinfo->in.u.commit_fpm_val.hmc_fn_id,
5210 &val_mem,
5211 true,
5212 IRDMA_CQP_WAIT_EVENT);
5213 break;
5214 case IRDMA_OP_STATS_ALLOCATE:
5215 alloc = true;
5216 /* fallthrough */
5217 case IRDMA_OP_STATS_FREE:
5218 status = irdma_sc_manage_stats_inst(pcmdinfo->in.u.stats_manage.cqp,
5219 &pcmdinfo->in.u.stats_manage.info,
5220 alloc,
5221 pcmdinfo->in.u.stats_manage.scratch);
5222 break;
5223 case IRDMA_OP_STATS_GATHER:
5224 status = irdma_sc_gather_stats(pcmdinfo->in.u.stats_gather.cqp,
5225 &pcmdinfo->in.u.stats_gather.info,
5226 pcmdinfo->in.u.stats_gather.scratch);
5227 break;
5228 case IRDMA_OP_WS_MODIFY_NODE:
5229 status = irdma_sc_manage_ws_node(pcmdinfo->in.u.ws_node.cqp,
5230 &pcmdinfo->in.u.ws_node.info,
5231 IRDMA_MODIFY_NODE,
5232 pcmdinfo->in.u.ws_node.scratch);
5233 break;
5234 case IRDMA_OP_WS_DELETE_NODE:
5235 status = irdma_sc_manage_ws_node(pcmdinfo->in.u.ws_node.cqp,
5236 &pcmdinfo->in.u.ws_node.info,
5237 IRDMA_DEL_NODE,
5238 pcmdinfo->in.u.ws_node.scratch);
5239 break;
5240 case IRDMA_OP_WS_ADD_NODE:
5241 status = irdma_sc_manage_ws_node(pcmdinfo->in.u.ws_node.cqp,
5242 &pcmdinfo->in.u.ws_node.info,
5243 IRDMA_ADD_NODE,
5244 pcmdinfo->in.u.ws_node.scratch);
5245 break;
5246 case IRDMA_OP_SET_UP_MAP:
5247 status = irdma_sc_set_up_map(pcmdinfo->in.u.up_map.cqp,
5248 &pcmdinfo->in.u.up_map.info,
5249 pcmdinfo->in.u.up_map.scratch);
5250 break;
5251 case IRDMA_OP_QUERY_RDMA_FEATURES:
5252 status = irdma_sc_query_rdma_features(pcmdinfo->in.u.query_rdma.cqp,
5253 &pcmdinfo->in.u.query_rdma.query_buff_mem,
5254 pcmdinfo->in.u.query_rdma.scratch);
5255 break;
5256 case IRDMA_OP_DELETE_ARP_CACHE_ENTRY:
5257 status = irdma_sc_del_arp_cache_entry(pcmdinfo->in.u.del_arp_cache_entry.cqp,
5258 pcmdinfo->in.u.del_arp_cache_entry.scratch,
5259 pcmdinfo->in.u.del_arp_cache_entry.arp_index,
5260 pcmdinfo->post_sq);
5261 break;
5262 case IRDMA_OP_MANAGE_APBVT_ENTRY:
5263 status = irdma_sc_manage_apbvt_entry(pcmdinfo->in.u.manage_apbvt_entry.cqp,
5264 &pcmdinfo->in.u.manage_apbvt_entry.info,
5265 pcmdinfo->in.u.manage_apbvt_entry.scratch,
5266 pcmdinfo->post_sq);
5267 break;
5268 case IRDMA_OP_MANAGE_QHASH_TABLE_ENTRY:
5269 status = irdma_sc_manage_qhash_table_entry(pcmdinfo->in.u.manage_qhash_table_entry.cqp,
5270 &pcmdinfo->in.u.manage_qhash_table_entry.info,
5271 pcmdinfo->in.u.manage_qhash_table_entry.scratch,
5272 pcmdinfo->post_sq);
5273 break;
5274 case IRDMA_OP_QP_MODIFY:
5275 status = irdma_sc_qp_modify(pcmdinfo->in.u.qp_modify.qp,
5276 &pcmdinfo->in.u.qp_modify.info,
5277 pcmdinfo->in.u.qp_modify.scratch,
5278 pcmdinfo->post_sq);
5279 break;
5280 case IRDMA_OP_QP_CREATE:
5281 status = irdma_sc_qp_create(pcmdinfo->in.u.qp_create.qp,
5282 &pcmdinfo->in.u.qp_create.info,
5283 pcmdinfo->in.u.qp_create.scratch,
5284 pcmdinfo->post_sq);
5285 break;
5286 case IRDMA_OP_QP_DESTROY:
5287 status = irdma_sc_qp_destroy(pcmdinfo->in.u.qp_destroy.qp,
5288 pcmdinfo->in.u.qp_destroy.scratch,
5289 pcmdinfo->in.u.qp_destroy.remove_hash_idx,
5290 pcmdinfo->in.u.qp_destroy.ignore_mw_bnd,
5291 pcmdinfo->post_sq);
5292 break;
5293 case IRDMA_OP_ALLOC_STAG:
5294 status = irdma_sc_alloc_stag(pcmdinfo->in.u.alloc_stag.dev,
5295 &pcmdinfo->in.u.alloc_stag.info,
5296 pcmdinfo->in.u.alloc_stag.scratch,
5297 pcmdinfo->post_sq);
5298 break;
5299 case IRDMA_OP_MR_REG_NON_SHARED:
5300 status = irdma_sc_mr_reg_non_shared(pcmdinfo->in.u.mr_reg_non_shared.dev,
5301 &pcmdinfo->in.u.mr_reg_non_shared.info,
5302 pcmdinfo->in.u.mr_reg_non_shared.scratch,
5303 pcmdinfo->post_sq);
5304 break;
5305 case IRDMA_OP_DEALLOC_STAG:
5306 status = irdma_sc_dealloc_stag(pcmdinfo->in.u.dealloc_stag.dev,
5307 &pcmdinfo->in.u.dealloc_stag.info,
5308 pcmdinfo->in.u.dealloc_stag.scratch,
5309 pcmdinfo->post_sq);
5310 break;
5311 case IRDMA_OP_MW_ALLOC:
5312 status = irdma_sc_mw_alloc(pcmdinfo->in.u.mw_alloc.dev,
5313 &pcmdinfo->in.u.mw_alloc.info,
5314 pcmdinfo->in.u.mw_alloc.scratch,
5315 pcmdinfo->post_sq);
5316 break;
5317 case IRDMA_OP_ADD_ARP_CACHE_ENTRY:
5318 status = irdma_sc_add_arp_cache_entry(pcmdinfo->in.u.add_arp_cache_entry.cqp,
5319 &pcmdinfo->in.u.add_arp_cache_entry.info,
5320 pcmdinfo->in.u.add_arp_cache_entry.scratch,
5321 pcmdinfo->post_sq);
5322 break;
5323 case IRDMA_OP_ALLOC_LOCAL_MAC_ENTRY:
5324 status = irdma_sc_alloc_local_mac_entry(pcmdinfo->in.u.alloc_local_mac_entry.cqp,
5325 pcmdinfo->in.u.alloc_local_mac_entry.scratch,
5326 pcmdinfo->post_sq);
5327 break;
5328 case IRDMA_OP_ADD_LOCAL_MAC_ENTRY:
5329 status = irdma_sc_add_local_mac_entry(pcmdinfo->in.u.add_local_mac_entry.cqp,
5330 &pcmdinfo->in.u.add_local_mac_entry.info,
5331 pcmdinfo->in.u.add_local_mac_entry.scratch,
5332 pcmdinfo->post_sq);
5333 break;
5334 case IRDMA_OP_DELETE_LOCAL_MAC_ENTRY:
5335 status = irdma_sc_del_local_mac_entry(pcmdinfo->in.u.del_local_mac_entry.cqp,
5336 pcmdinfo->in.u.del_local_mac_entry.scratch,
5337 pcmdinfo->in.u.del_local_mac_entry.entry_idx,
5338 pcmdinfo->in.u.del_local_mac_entry.ignore_ref_count,
5339 pcmdinfo->post_sq);
5340 break;
5341 case IRDMA_OP_AH_CREATE:
5342 status = irdma_sc_create_ah(pcmdinfo->in.u.ah_create.cqp,
5343 &pcmdinfo->in.u.ah_create.info,
5344 pcmdinfo->in.u.ah_create.scratch);
5345 break;
5346 case IRDMA_OP_AH_DESTROY:
5347 status = irdma_sc_destroy_ah(pcmdinfo->in.u.ah_destroy.cqp,
5348 &pcmdinfo->in.u.ah_destroy.info,
5349 pcmdinfo->in.u.ah_destroy.scratch);
5350 break;
5351 case IRDMA_OP_MC_CREATE:
5352 status = irdma_sc_create_mcast_grp(pcmdinfo->in.u.mc_create.cqp,
5353 &pcmdinfo->in.u.mc_create.info,
5354 pcmdinfo->in.u.mc_create.scratch);
5355 break;
5356 case IRDMA_OP_MC_DESTROY:
5357 status = irdma_sc_destroy_mcast_grp(pcmdinfo->in.u.mc_destroy.cqp,
5358 &pcmdinfo->in.u.mc_destroy.info,
5359 pcmdinfo->in.u.mc_destroy.scratch);
5360 break;
5361 case IRDMA_OP_MC_MODIFY:
5362 status = irdma_sc_modify_mcast_grp(pcmdinfo->in.u.mc_modify.cqp,
5363 &pcmdinfo->in.u.mc_modify.info,
5364 pcmdinfo->in.u.mc_modify.scratch);
5365 break;
5366 default:
5367 status = -EOPNOTSUPP;
5368 break;
5369 }
5370
5371 return status;
5372 }
5373
5374 /**
5375 * irdma_process_cqp_cmd - process all cqp commands
5376 * @dev: sc device struct
5377 * @pcmdinfo: cqp command info
5378 */
5379 int
irdma_process_cqp_cmd(struct irdma_sc_dev * dev,struct cqp_cmds_info * pcmdinfo)5380 irdma_process_cqp_cmd(struct irdma_sc_dev *dev,
5381 struct cqp_cmds_info *pcmdinfo)
5382 {
5383 int status = 0;
5384 unsigned long flags;
5385
5386 spin_lock_irqsave(&dev->cqp_lock, flags);
5387 if (list_empty(&dev->cqp_cmd_head) && !irdma_cqp_ring_full(dev->cqp))
5388 status = irdma_exec_cqp_cmd(dev, pcmdinfo);
5389 else
5390 list_add_tail(&pcmdinfo->cqp_cmd_entry, &dev->cqp_cmd_head);
5391 spin_unlock_irqrestore(&dev->cqp_lock, flags);
5392 return status;
5393 }
5394
5395 /**
5396 * irdma_process_bh - called from tasklet for cqp list
5397 * @dev: sc device struct
5398 */
5399 int
irdma_process_bh(struct irdma_sc_dev * dev)5400 irdma_process_bh(struct irdma_sc_dev *dev)
5401 {
5402 int status = 0;
5403 struct cqp_cmds_info *pcmdinfo;
5404 unsigned long flags;
5405
5406 spin_lock_irqsave(&dev->cqp_lock, flags);
5407 while (!list_empty(&dev->cqp_cmd_head) &&
5408 !irdma_cqp_ring_full(dev->cqp)) {
5409 pcmdinfo = (struct cqp_cmds_info *)irdma_remove_cqp_head(dev);
5410 status = irdma_exec_cqp_cmd(dev, pcmdinfo);
5411 if (status)
5412 break;
5413 }
5414 spin_unlock_irqrestore(&dev->cqp_lock, flags);
5415 return status;
5416 }
5417
5418 /**
5419 * irdma_cfg_aeq- Configure AEQ interrupt
5420 * @dev: pointer to the device structure
5421 * @idx: vector index
5422 * @enable: True to enable, False disables
5423 */
5424 void
irdma_cfg_aeq(struct irdma_sc_dev * dev,u32 idx,bool enable)5425 irdma_cfg_aeq(struct irdma_sc_dev *dev, u32 idx, bool enable)
5426 {
5427 u32 reg_val;
5428
5429 reg_val = FIELD_PREP(IRDMA_PFINT_AEQCTL_CAUSE_ENA, enable) |
5430 FIELD_PREP(IRDMA_PFINT_AEQCTL_MSIX_INDX, idx) |
5431 FIELD_PREP(IRDMA_PFINT_AEQCTL_ITR_INDX, IRDMA_IDX_NOITR);
5432
5433 writel(reg_val, dev->hw_regs[IRDMA_PFINT_AEQCTL]);
5434 }
5435
5436 /**
5437 * sc_vsi_update_stats - Update statistics
5438 * @vsi: sc_vsi instance to update
5439 */
5440 void
sc_vsi_update_stats(struct irdma_sc_vsi * vsi)5441 sc_vsi_update_stats(struct irdma_sc_vsi *vsi)
5442 {
5443 struct irdma_dev_hw_stats *hw_stats = &vsi->pestat->hw_stats;
5444 struct irdma_gather_stats *gather_stats =
5445 vsi->pestat->gather_info.gather_stats_va;
5446 struct irdma_gather_stats *last_gather_stats =
5447 vsi->pestat->gather_info.last_gather_stats_va;
5448 const struct irdma_hw_stat_map *map = vsi->dev->hw_stats_map;
5449 u16 max_stat_idx = vsi->dev->hw_attrs.max_stat_idx;
5450
5451 irdma_update_stats(hw_stats, gather_stats, last_gather_stats,
5452 map, max_stat_idx);
5453 }
5454
5455 /**
5456 * irdma_wait_pe_ready - Check if firmware is ready
5457 * @dev: provides access to registers
5458 */
5459 static int
irdma_wait_pe_ready(struct irdma_sc_dev * dev)5460 irdma_wait_pe_ready(struct irdma_sc_dev *dev)
5461 {
5462 u32 statuscpu0;
5463 u32 statuscpu1;
5464 u32 statuscpu2;
5465 u32 retrycount = 0;
5466
5467 do {
5468 statuscpu0 = readl(dev->hw_regs[IRDMA_GLPE_CPUSTATUS0]);
5469 statuscpu1 = readl(dev->hw_regs[IRDMA_GLPE_CPUSTATUS1]);
5470 statuscpu2 = readl(dev->hw_regs[IRDMA_GLPE_CPUSTATUS2]);
5471 if (statuscpu0 == 0x80 && statuscpu1 == 0x80 &&
5472 statuscpu2 == 0x80)
5473 return 0;
5474 mdelay(1000);
5475 } while (retrycount++ < dev->hw_attrs.max_pe_ready_count);
5476 return -1;
5477 }
5478
5479 static inline void
irdma_sc_init_hw(struct irdma_sc_dev * dev)5480 irdma_sc_init_hw(struct irdma_sc_dev *dev)
5481 {
5482 switch (dev->hw_attrs.uk_attrs.hw_rev) {
5483 case IRDMA_GEN_2:
5484 icrdma_init_hw(dev);
5485 break;
5486 }
5487 }
5488
5489 /**
5490 * irdma_sc_dev_init - Initialize control part of device
5491 * @dev: Device pointer
5492 * @info: Device init info
5493 */
5494 int
irdma_sc_dev_init(struct irdma_sc_dev * dev,struct irdma_device_init_info * info)5495 irdma_sc_dev_init(struct irdma_sc_dev *dev, struct irdma_device_init_info *info)
5496 {
5497 u32 val;
5498 int ret_code = 0;
5499 u8 db_size;
5500
5501 INIT_LIST_HEAD(&dev->cqp_cmd_head); /* for CQP command backlog */
5502 mutex_init(&dev->ws_mutex);
5503 dev->debug_mask = info->debug_mask;
5504 dev->hmc_fn_id = info->hmc_fn_id;
5505 dev->fpm_query_buf_pa = info->fpm_query_buf_pa;
5506 dev->fpm_query_buf = info->fpm_query_buf;
5507 dev->fpm_commit_buf_pa = info->fpm_commit_buf_pa;
5508 dev->fpm_commit_buf = info->fpm_commit_buf;
5509 dev->hw = info->hw;
5510 dev->hw->hw_addr = info->bar0;
5511 /* Setup the hardware limits, hmc may limit further */
5512 dev->hw_attrs.min_hw_qp_id = IRDMA_MIN_IW_QP_ID;
5513 dev->hw_attrs.min_hw_aeq_size = IRDMA_MIN_AEQ_ENTRIES;
5514 dev->hw_attrs.max_hw_aeq_size = IRDMA_MAX_AEQ_ENTRIES;
5515 dev->hw_attrs.min_hw_ceq_size = IRDMA_MIN_CEQ_ENTRIES;
5516 dev->hw_attrs.max_hw_ceq_size = IRDMA_MAX_CEQ_ENTRIES;
5517 dev->hw_attrs.uk_attrs.min_hw_cq_size = IRDMA_MIN_CQ_SIZE;
5518 dev->hw_attrs.uk_attrs.max_hw_cq_size = IRDMA_MAX_CQ_SIZE;
5519 dev->hw_attrs.max_hw_outbound_msg_size = IRDMA_MAX_OUTBOUND_MSG_SIZE;
5520 dev->hw_attrs.max_mr_size = IRDMA_MAX_MR_SIZE;
5521 dev->hw_attrs.max_hw_inbound_msg_size = IRDMA_MAX_INBOUND_MSG_SIZE;
5522 dev->hw_attrs.uk_attrs.max_hw_inline = IRDMA_MAX_INLINE_DATA_SIZE;
5523 dev->hw_attrs.max_hw_wqes = IRDMA_MAX_WQ_ENTRIES;
5524 dev->hw_attrs.max_qp_wr = IRDMA_MAX_QP_WRS(IRDMA_MAX_QUANTA_PER_WR);
5525
5526 dev->hw_attrs.uk_attrs.max_hw_rq_quanta = IRDMA_QP_SW_MAX_RQ_QUANTA;
5527 dev->hw_attrs.uk_attrs.max_hw_wq_quanta = IRDMA_QP_SW_MAX_WQ_QUANTA;
5528 dev->hw_attrs.max_hw_pds = IRDMA_MAX_PDS;
5529 dev->hw_attrs.max_hw_ena_vf_count = IRDMA_MAX_PE_ENA_VF_COUNT;
5530
5531 dev->hw_attrs.max_pe_ready_count = 14;
5532 dev->hw_attrs.max_done_count = IRDMA_DONE_COUNT;
5533 dev->hw_attrs.max_sleep_count = IRDMA_SLEEP_COUNT;
5534 dev->hw_attrs.max_cqp_compl_wait_time_ms = CQP_COMPL_WAIT_TIME_MS;
5535
5536 irdma_sc_init_hw(dev);
5537
5538 if (irdma_wait_pe_ready(dev))
5539 return -ETIMEDOUT;
5540
5541 val = readl(dev->hw_regs[IRDMA_GLPCI_LBARCTRL]);
5542 db_size = (u8)FIELD_GET(IRDMA_GLPCI_LBARCTRL_PE_DB_SIZE, val);
5543 if (db_size != IRDMA_PE_DB_SIZE_4M && db_size != IRDMA_PE_DB_SIZE_8M) {
5544 irdma_debug(dev, IRDMA_DEBUG_DEV,
5545 "RDMA PE doorbell is not enabled in CSR val 0x%x db_size=%d\n",
5546 val, db_size);
5547 return -ENODEV;
5548 }
5549
5550 return ret_code;
5551 }
5552
5553 /**
5554 * irdma_stat_val - Extract HW counter value from statistics buffer
5555 * @stats_val: pointer to statistics buffer
5556 * @byteoff: byte offset of counter value in the buffer (8B-aligned)
5557 * @bitoff: bit offset of counter value within 8B entry
5558 * @bitmask: maximum counter value (e.g. 0xffffff for 24-bit counter)
5559 */
irdma_stat_val(const u64 * stats_val,u16 byteoff,u8 bitoff,u64 bitmask)5560 static inline u64 irdma_stat_val(const u64 *stats_val, u16 byteoff,
5561 u8 bitoff, u64 bitmask){
5562 u16 idx = byteoff / sizeof(*stats_val);
5563
5564 return (stats_val[idx] >> bitoff) & bitmask;
5565 }
5566
5567 /**
5568 * irdma_stat_delta - Calculate counter delta
5569 * @new_val: updated counter value
5570 * @old_val: last counter value
5571 * @max_val: maximum counter value (e.g. 0xffffff for 24-bit counter)
5572 */
irdma_stat_delta(u64 new_val,u64 old_val,u64 max_val)5573 static inline u64 irdma_stat_delta(u64 new_val, u64 old_val, u64 max_val) {
5574 if (new_val >= old_val)
5575 return new_val - old_val;
5576 else
5577 /* roll-over case */
5578 return max_val - old_val + new_val + 1;
5579 }
5580
5581 /**
5582 * irdma_update_stats - Update statistics
5583 * @hw_stats: hw_stats instance to update
5584 * @gather_stats: updated stat counters
5585 * @last_gather_stats: last stat counters
5586 * @map: HW stat map (hw_stats => gather_stats)
5587 * @max_stat_idx: number of HW stats
5588 */
5589 void
irdma_update_stats(struct irdma_dev_hw_stats * hw_stats,struct irdma_gather_stats * gather_stats,struct irdma_gather_stats * last_gather_stats,const struct irdma_hw_stat_map * map,u16 max_stat_idx)5590 irdma_update_stats(struct irdma_dev_hw_stats *hw_stats,
5591 struct irdma_gather_stats *gather_stats,
5592 struct irdma_gather_stats *last_gather_stats,
5593 const struct irdma_hw_stat_map *map,
5594 u16 max_stat_idx)
5595 {
5596 u64 *stats_val = hw_stats->stats_val;
5597 u16 i;
5598
5599 for (i = 0; i < max_stat_idx; i++) {
5600 u64 new_val = irdma_stat_val(gather_stats->val,
5601 map[i].byteoff, map[i].bitoff,
5602 map[i].bitmask);
5603 u64 last_val = irdma_stat_val(last_gather_stats->val,
5604 map[i].byteoff, map[i].bitoff,
5605 map[i].bitmask);
5606
5607 stats_val[i] += irdma_stat_delta(new_val, last_val,
5608 map[i].bitmask);
5609 }
5610
5611 irdma_memcpy(last_gather_stats, gather_stats,
5612 sizeof(*last_gather_stats));
5613 }
5614