1 /*-
2 * Copyright (c) 2003 Peter Wemm.
3 * Copyright (c) 1993 The Regents of the University of California.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 4. Neither the name of the University nor the names of its contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 * $FreeBSD$
31 */
32
33 /*
34 * Functions to provide access to special i386 instructions.
35 * This in included in sys/systm.h, and that file should be
36 * used in preference to this.
37 */
38
39 #ifndef _MACHINE_CPUFUNC_H_
40 #define _MACHINE_CPUFUNC_H_
41
42 #ifndef _SYS_CDEFS_H_
43 #error this file needs sys/cdefs.h as a prerequisite
44 #endif
45
46 struct region_descriptor;
47
48 #define readb(va) (*(volatile uint8_t *) (va))
49 #define readw(va) (*(volatile uint16_t *) (va))
50 #define readl(va) (*(volatile uint32_t *) (va))
51 #define readq(va) (*(volatile uint64_t *) (va))
52
53 #define writeb(va, d) (*(volatile uint8_t *) (va) = (d))
54 #define writew(va, d) (*(volatile uint16_t *) (va) = (d))
55 #define writel(va, d) (*(volatile uint32_t *) (va) = (d))
56 #define writeq(va, d) (*(volatile uint64_t *) (va) = (d))
57
58 #if defined(__GNUCLIKE_ASM) && defined(__CC_SUPPORTS___INLINE)
59
60 static __inline void
breakpoint(void)61 breakpoint(void)
62 {
63 __asm __volatile("int $3");
64 }
65
66 static __inline u_int
bsfl(u_int mask)67 bsfl(u_int mask)
68 {
69 u_int result;
70
71 __asm __volatile("bsfl %1,%0" : "=r" (result) : "rm" (mask));
72 return (result);
73 }
74
75 static __inline u_long
bsfq(u_long mask)76 bsfq(u_long mask)
77 {
78 u_long result;
79
80 __asm __volatile("bsfq %1,%0" : "=r" (result) : "rm" (mask));
81 return (result);
82 }
83
84 static __inline u_int
bsrl(u_int mask)85 bsrl(u_int mask)
86 {
87 u_int result;
88
89 __asm __volatile("bsrl %1,%0" : "=r" (result) : "rm" (mask));
90 return (result);
91 }
92
93 static __inline u_long
bsrq(u_long mask)94 bsrq(u_long mask)
95 {
96 u_long result;
97
98 __asm __volatile("bsrq %1,%0" : "=r" (result) : "rm" (mask));
99 return (result);
100 }
101
102 static __inline void
clflush(u_long addr)103 clflush(u_long addr)
104 {
105
106 __asm __volatile("clflush %0" : : "m" (*(char *)addr));
107 }
108
109 static __inline void
clts(void)110 clts(void)
111 {
112
113 __asm __volatile("clts");
114 }
115
116 static __inline void
disable_intr(void)117 disable_intr(void)
118 {
119 __asm __volatile("cli" : : : "memory");
120 }
121
122 static __inline void
do_cpuid(u_int ax,u_int * p)123 do_cpuid(u_int ax, u_int *p)
124 {
125 __asm __volatile("cpuid"
126 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
127 : "0" (ax));
128 }
129
130 static __inline void
cpuid_count(u_int ax,u_int cx,u_int * p)131 cpuid_count(u_int ax, u_int cx, u_int *p)
132 {
133 __asm __volatile("cpuid"
134 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
135 : "0" (ax), "c" (cx));
136 }
137
138 static __inline void
enable_intr(void)139 enable_intr(void)
140 {
141 __asm __volatile("sti");
142 }
143
144 #ifdef _KERNEL
145
146 #define HAVE_INLINE_FFS
147 #define ffs(x) __builtin_ffs(x)
148
149 #define HAVE_INLINE_FFSL
150
151 static __inline int
ffsl(long mask)152 ffsl(long mask)
153 {
154 return (mask == 0 ? mask : (int)bsfq((u_long)mask) + 1);
155 }
156
157 #define HAVE_INLINE_FLS
158
159 static __inline int
fls(int mask)160 fls(int mask)
161 {
162 return (mask == 0 ? mask : (int)bsrl((u_int)mask) + 1);
163 }
164
165 #define HAVE_INLINE_FLSL
166
167 static __inline int
flsl(long mask)168 flsl(long mask)
169 {
170 return (mask == 0 ? mask : (int)bsrq((u_long)mask) + 1);
171 }
172
173 #endif /* _KERNEL */
174
175 static __inline void
halt(void)176 halt(void)
177 {
178 __asm __volatile("hlt");
179 }
180
181 static __inline u_char
inb(u_int port)182 inb(u_int port)
183 {
184 u_char data;
185
186 __asm __volatile("inb %w1, %0" : "=a" (data) : "Nd" (port));
187 return (data);
188 }
189
190 static __inline u_int
inl(u_int port)191 inl(u_int port)
192 {
193 u_int data;
194
195 __asm __volatile("inl %w1, %0" : "=a" (data) : "Nd" (port));
196 return (data);
197 }
198
199 static __inline void
insb(u_int port,void * addr,size_t count)200 insb(u_int port, void *addr, size_t count)
201 {
202 __asm __volatile("cld; rep; insb"
203 : "+D" (addr), "+c" (count)
204 : "d" (port)
205 : "memory");
206 }
207
208 static __inline void
insw(u_int port,void * addr,size_t count)209 insw(u_int port, void *addr, size_t count)
210 {
211 __asm __volatile("cld; rep; insw"
212 : "+D" (addr), "+c" (count)
213 : "d" (port)
214 : "memory");
215 }
216
217 static __inline void
insl(u_int port,void * addr,size_t count)218 insl(u_int port, void *addr, size_t count)
219 {
220 __asm __volatile("cld; rep; insl"
221 : "+D" (addr), "+c" (count)
222 : "d" (port)
223 : "memory");
224 }
225
226 static __inline void
invd(void)227 invd(void)
228 {
229 __asm __volatile("invd");
230 }
231
232 static __inline u_short
inw(u_int port)233 inw(u_int port)
234 {
235 u_short data;
236
237 __asm __volatile("inw %w1, %0" : "=a" (data) : "Nd" (port));
238 return (data);
239 }
240
241 static __inline void
outb(u_int port,u_char data)242 outb(u_int port, u_char data)
243 {
244 __asm __volatile("outb %0, %w1" : : "a" (data), "Nd" (port));
245 }
246
247 static __inline void
outl(u_int port,u_int data)248 outl(u_int port, u_int data)
249 {
250 __asm __volatile("outl %0, %w1" : : "a" (data), "Nd" (port));
251 }
252
253 static __inline void
outsb(u_int port,const void * addr,size_t count)254 outsb(u_int port, const void *addr, size_t count)
255 {
256 __asm __volatile("cld; rep; outsb"
257 : "+S" (addr), "+c" (count)
258 : "d" (port));
259 }
260
261 static __inline void
outsw(u_int port,const void * addr,size_t count)262 outsw(u_int port, const void *addr, size_t count)
263 {
264 __asm __volatile("cld; rep; outsw"
265 : "+S" (addr), "+c" (count)
266 : "d" (port));
267 }
268
269 static __inline void
outsl(u_int port,const void * addr,size_t count)270 outsl(u_int port, const void *addr, size_t count)
271 {
272 __asm __volatile("cld; rep; outsl"
273 : "+S" (addr), "+c" (count)
274 : "d" (port));
275 }
276
277 static __inline void
outw(u_int port,u_short data)278 outw(u_int port, u_short data)
279 {
280 __asm __volatile("outw %0, %w1" : : "a" (data), "Nd" (port));
281 }
282
283 static __inline u_long
popcntq(u_long mask)284 popcntq(u_long mask)
285 {
286 u_long result;
287
288 __asm __volatile("popcntq %1,%0" : "=r" (result) : "rm" (mask));
289 return (result);
290 }
291
292 static __inline void
lfence(void)293 lfence(void)
294 {
295
296 __asm __volatile("lfence" : : : "memory");
297 }
298
299 static __inline void
mfence(void)300 mfence(void)
301 {
302
303 __asm __volatile("mfence" : : : "memory");
304 }
305
306 static __inline void
ia32_pause(void)307 ia32_pause(void)
308 {
309 __asm __volatile("pause");
310 }
311
312 static __inline u_long
read_rflags(void)313 read_rflags(void)
314 {
315 u_long rf;
316
317 __asm __volatile("pushfq; popq %0" : "=r" (rf));
318 return (rf);
319 }
320
321 static __inline uint64_t
rdmsr(u_int msr)322 rdmsr(u_int msr)
323 {
324 uint32_t low, high;
325
326 __asm __volatile("rdmsr" : "=a" (low), "=d" (high) : "c" (msr));
327 return (low | ((uint64_t)high << 32));
328 }
329
330 static __inline uint64_t
rdpmc(u_int pmc)331 rdpmc(u_int pmc)
332 {
333 uint32_t low, high;
334
335 __asm __volatile("rdpmc" : "=a" (low), "=d" (high) : "c" (pmc));
336 return (low | ((uint64_t)high << 32));
337 }
338
339 static __inline uint64_t
rdtsc(void)340 rdtsc(void)
341 {
342 uint32_t low, high;
343
344 __asm __volatile("rdtsc" : "=a" (low), "=d" (high));
345 return (low | ((uint64_t)high << 32));
346 }
347
348 static __inline uint32_t
rdtsc32(void)349 rdtsc32(void)
350 {
351 uint32_t rv;
352
353 __asm __volatile("rdtsc" : "=a" (rv) : : "edx");
354 return (rv);
355 }
356
357 static __inline void
wbinvd(void)358 wbinvd(void)
359 {
360 __asm __volatile("wbinvd");
361 }
362
363 static __inline void
write_rflags(u_long rf)364 write_rflags(u_long rf)
365 {
366 __asm __volatile("pushq %0; popfq" : : "r" (rf));
367 }
368
369 static __inline void
wrmsr(u_int msr,uint64_t newval)370 wrmsr(u_int msr, uint64_t newval)
371 {
372 uint32_t low, high;
373
374 low = newval;
375 high = newval >> 32;
376 __asm __volatile("wrmsr" : : "a" (low), "d" (high), "c" (msr));
377 }
378
379 static __inline void
load_cr0(u_long data)380 load_cr0(u_long data)
381 {
382
383 __asm __volatile("movq %0,%%cr0" : : "r" (data));
384 }
385
386 static __inline u_long
rcr0(void)387 rcr0(void)
388 {
389 u_long data;
390
391 __asm __volatile("movq %%cr0,%0" : "=r" (data));
392 return (data);
393 }
394
395 static __inline u_long
rcr2(void)396 rcr2(void)
397 {
398 u_long data;
399
400 __asm __volatile("movq %%cr2,%0" : "=r" (data));
401 return (data);
402 }
403
404 static __inline void
load_cr3(u_long data)405 load_cr3(u_long data)
406 {
407
408 __asm __volatile("movq %0,%%cr3" : : "r" (data) : "memory");
409 }
410
411 static __inline u_long
rcr3(void)412 rcr3(void)
413 {
414 u_long data;
415
416 __asm __volatile("movq %%cr3,%0" : "=r" (data));
417 return (data);
418 }
419
420 static __inline void
load_cr4(u_long data)421 load_cr4(u_long data)
422 {
423 __asm __volatile("movq %0,%%cr4" : : "r" (data));
424 }
425
426 static __inline u_long
rcr4(void)427 rcr4(void)
428 {
429 u_long data;
430
431 __asm __volatile("movq %%cr4,%0" : "=r" (data));
432 return (data);
433 }
434
435 static __inline u_long
rxcr(u_int reg)436 rxcr(u_int reg)
437 {
438 u_int low, high;
439
440 __asm __volatile("xgetbv" : "=a" (low), "=d" (high) : "c" (reg));
441 return (low | ((uint64_t)high << 32));
442 }
443
444 static __inline void
load_xcr(u_int reg,u_long val)445 load_xcr(u_int reg, u_long val)
446 {
447 u_int low, high;
448
449 low = val;
450 high = val >> 32;
451 __asm __volatile("xsetbv" : : "c" (reg), "a" (low), "d" (high));
452 }
453
454 /*
455 * Global TLB flush (except for thise for pages marked PG_G)
456 */
457 static __inline void
invltlb(void)458 invltlb(void)
459 {
460
461 load_cr3(rcr3());
462 }
463
464 #ifndef CR4_PGE
465 #define CR4_PGE 0x00000080 /* Page global enable */
466 #endif
467
468 /*
469 * Perform the guaranteed invalidation of all TLB entries. This
470 * includes the global entries, and entries in all PCIDs, not only the
471 * current context. The function works both on non-PCID CPUs and CPUs
472 * with the PCID turned off or on. See IA-32 SDM Vol. 3a 4.10.4.1
473 * Operations that Invalidate TLBs and Paging-Structure Caches.
474 */
475 static __inline void
invltlb_globpcid(void)476 invltlb_globpcid(void)
477 {
478 uint64_t cr4;
479
480 cr4 = rcr4();
481 load_cr4(cr4 & ~CR4_PGE);
482 /*
483 * Although preemption at this point could be detrimental to
484 * performance, it would not lead to an error. PG_G is simply
485 * ignored if CR4.PGE is clear. Moreover, in case this block
486 * is re-entered, the load_cr4() either above or below will
487 * modify CR4.PGE flushing the TLB.
488 */
489 load_cr4(cr4 | CR4_PGE);
490 }
491
492 /*
493 * TLB flush for an individual page (even if it has PG_G).
494 * Only works on 486+ CPUs (i386 does not have PG_G).
495 */
496 static __inline void
invlpg(u_long addr)497 invlpg(u_long addr)
498 {
499
500 __asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory");
501 }
502
503 #define INVPCID_ADDR 0
504 #define INVPCID_CTX 1
505 #define INVPCID_CTXGLOB 2
506 #define INVPCID_ALLCTX 3
507
508 struct invpcid_descr {
509 uint64_t pcid:12 __packed;
510 uint64_t pad:52 __packed;
511 uint64_t addr;
512 } __packed;
513
514 static __inline void
invpcid(struct invpcid_descr * d,int type)515 invpcid(struct invpcid_descr *d, int type)
516 {
517
518 /* invpcid (%rdx),%rax */
519 __asm __volatile(".byte 0x66,0x0f,0x38,0x82,0x02"
520 : : "d" (d), "a" ((u_long)type) : "memory");
521 }
522
523 static __inline u_short
rfs(void)524 rfs(void)
525 {
526 u_short sel;
527 __asm __volatile("movw %%fs,%0" : "=rm" (sel));
528 return (sel);
529 }
530
531 static __inline u_short
rgs(void)532 rgs(void)
533 {
534 u_short sel;
535 __asm __volatile("movw %%gs,%0" : "=rm" (sel));
536 return (sel);
537 }
538
539 static __inline u_short
rss(void)540 rss(void)
541 {
542 u_short sel;
543 __asm __volatile("movw %%ss,%0" : "=rm" (sel));
544 return (sel);
545 }
546
547 static __inline void
load_ds(u_short sel)548 load_ds(u_short sel)
549 {
550 __asm __volatile("movw %0,%%ds" : : "rm" (sel));
551 }
552
553 static __inline void
load_es(u_short sel)554 load_es(u_short sel)
555 {
556 __asm __volatile("movw %0,%%es" : : "rm" (sel));
557 }
558
559 static __inline void
cpu_monitor(const void * addr,u_long extensions,u_int hints)560 cpu_monitor(const void *addr, u_long extensions, u_int hints)
561 {
562
563 __asm __volatile("monitor"
564 : : "a" (addr), "c" (extensions), "d" (hints));
565 }
566
567 static __inline void
cpu_mwait(u_long extensions,u_int hints)568 cpu_mwait(u_long extensions, u_int hints)
569 {
570
571 __asm __volatile("mwait" : : "a" (hints), "c" (extensions));
572 }
573
574 #ifdef _KERNEL
575 /* This is defined in <machine/specialreg.h> but is too painful to get to */
576 #ifndef MSR_FSBASE
577 #define MSR_FSBASE 0xc0000100
578 #endif
579 static __inline void
load_fs(u_short sel)580 load_fs(u_short sel)
581 {
582 /* Preserve the fsbase value across the selector load */
583 __asm __volatile("rdmsr; movw %0,%%fs; wrmsr"
584 : : "rm" (sel), "c" (MSR_FSBASE) : "eax", "edx");
585 }
586
587 #ifndef MSR_GSBASE
588 #define MSR_GSBASE 0xc0000101
589 #endif
590 static __inline void
load_gs(u_short sel)591 load_gs(u_short sel)
592 {
593 /*
594 * Preserve the gsbase value across the selector load.
595 * Note that we have to disable interrupts because the gsbase
596 * being trashed happens to be the kernel gsbase at the time.
597 */
598 __asm __volatile("pushfq; cli; rdmsr; movw %0,%%gs; wrmsr; popfq"
599 : : "rm" (sel), "c" (MSR_GSBASE) : "eax", "edx");
600 }
601 #else
602 /* Usable by userland */
603 static __inline void
load_fs(u_short sel)604 load_fs(u_short sel)
605 {
606 __asm __volatile("movw %0,%%fs" : : "rm" (sel));
607 }
608
609 static __inline void
load_gs(u_short sel)610 load_gs(u_short sel)
611 {
612 __asm __volatile("movw %0,%%gs" : : "rm" (sel));
613 }
614 #endif
615
616 static __inline void
lidt(struct region_descriptor * addr)617 lidt(struct region_descriptor *addr)
618 {
619 __asm __volatile("lidt (%0)" : : "r" (addr));
620 }
621
622 static __inline void
lldt(u_short sel)623 lldt(u_short sel)
624 {
625 __asm __volatile("lldt %0" : : "r" (sel));
626 }
627
628 static __inline void
ltr(u_short sel)629 ltr(u_short sel)
630 {
631 __asm __volatile("ltr %0" : : "r" (sel));
632 }
633
634 static __inline uint64_t
rdr0(void)635 rdr0(void)
636 {
637 uint64_t data;
638 __asm __volatile("movq %%dr0,%0" : "=r" (data));
639 return (data);
640 }
641
642 static __inline void
load_dr0(uint64_t dr0)643 load_dr0(uint64_t dr0)
644 {
645 __asm __volatile("movq %0,%%dr0" : : "r" (dr0));
646 }
647
648 static __inline uint64_t
rdr1(void)649 rdr1(void)
650 {
651 uint64_t data;
652 __asm __volatile("movq %%dr1,%0" : "=r" (data));
653 return (data);
654 }
655
656 static __inline void
load_dr1(uint64_t dr1)657 load_dr1(uint64_t dr1)
658 {
659 __asm __volatile("movq %0,%%dr1" : : "r" (dr1));
660 }
661
662 static __inline uint64_t
rdr2(void)663 rdr2(void)
664 {
665 uint64_t data;
666 __asm __volatile("movq %%dr2,%0" : "=r" (data));
667 return (data);
668 }
669
670 static __inline void
load_dr2(uint64_t dr2)671 load_dr2(uint64_t dr2)
672 {
673 __asm __volatile("movq %0,%%dr2" : : "r" (dr2));
674 }
675
676 static __inline uint64_t
rdr3(void)677 rdr3(void)
678 {
679 uint64_t data;
680 __asm __volatile("movq %%dr3,%0" : "=r" (data));
681 return (data);
682 }
683
684 static __inline void
load_dr3(uint64_t dr3)685 load_dr3(uint64_t dr3)
686 {
687 __asm __volatile("movq %0,%%dr3" : : "r" (dr3));
688 }
689
690 static __inline uint64_t
rdr4(void)691 rdr4(void)
692 {
693 uint64_t data;
694 __asm __volatile("movq %%dr4,%0" : "=r" (data));
695 return (data);
696 }
697
698 static __inline void
load_dr4(uint64_t dr4)699 load_dr4(uint64_t dr4)
700 {
701 __asm __volatile("movq %0,%%dr4" : : "r" (dr4));
702 }
703
704 static __inline uint64_t
rdr5(void)705 rdr5(void)
706 {
707 uint64_t data;
708 __asm __volatile("movq %%dr5,%0" : "=r" (data));
709 return (data);
710 }
711
712 static __inline void
load_dr5(uint64_t dr5)713 load_dr5(uint64_t dr5)
714 {
715 __asm __volatile("movq %0,%%dr5" : : "r" (dr5));
716 }
717
718 static __inline uint64_t
rdr6(void)719 rdr6(void)
720 {
721 uint64_t data;
722 __asm __volatile("movq %%dr6,%0" : "=r" (data));
723 return (data);
724 }
725
726 static __inline void
load_dr6(uint64_t dr6)727 load_dr6(uint64_t dr6)
728 {
729 __asm __volatile("movq %0,%%dr6" : : "r" (dr6));
730 }
731
732 static __inline uint64_t
rdr7(void)733 rdr7(void)
734 {
735 uint64_t data;
736 __asm __volatile("movq %%dr7,%0" : "=r" (data));
737 return (data);
738 }
739
740 static __inline void
load_dr7(uint64_t dr7)741 load_dr7(uint64_t dr7)
742 {
743 __asm __volatile("movq %0,%%dr7" : : "r" (dr7));
744 }
745
746 static __inline register_t
intr_disable(void)747 intr_disable(void)
748 {
749 register_t rflags;
750
751 rflags = read_rflags();
752 disable_intr();
753 return (rflags);
754 }
755
756 static __inline void
intr_restore(register_t rflags)757 intr_restore(register_t rflags)
758 {
759 write_rflags(rflags);
760 }
761
762 #else /* !(__GNUCLIKE_ASM && __CC_SUPPORTS___INLINE) */
763
764 int breakpoint(void);
765 u_int bsfl(u_int mask);
766 u_int bsrl(u_int mask);
767 void clflush(u_long addr);
768 void clts(void);
769 void cpuid_count(u_int ax, u_int cx, u_int *p);
770 void disable_intr(void);
771 void do_cpuid(u_int ax, u_int *p);
772 void enable_intr(void);
773 void halt(void);
774 void ia32_pause(void);
775 u_char inb(u_int port);
776 u_int inl(u_int port);
777 void insb(u_int port, void *addr, size_t count);
778 void insl(u_int port, void *addr, size_t count);
779 void insw(u_int port, void *addr, size_t count);
780 register_t intr_disable(void);
781 void intr_restore(register_t rf);
782 void invd(void);
783 void invlpg(u_int addr);
784 void invltlb(void);
785 u_short inw(u_int port);
786 void lidt(struct region_descriptor *addr);
787 void lldt(u_short sel);
788 void load_cr0(u_long cr0);
789 void load_cr3(u_long cr3);
790 void load_cr4(u_long cr4);
791 void load_dr0(uint64_t dr0);
792 void load_dr1(uint64_t dr1);
793 void load_dr2(uint64_t dr2);
794 void load_dr3(uint64_t dr3);
795 void load_dr4(uint64_t dr4);
796 void load_dr5(uint64_t dr5);
797 void load_dr6(uint64_t dr6);
798 void load_dr7(uint64_t dr7);
799 void load_fs(u_short sel);
800 void load_gs(u_short sel);
801 void ltr(u_short sel);
802 void outb(u_int port, u_char data);
803 void outl(u_int port, u_int data);
804 void outsb(u_int port, const void *addr, size_t count);
805 void outsl(u_int port, const void *addr, size_t count);
806 void outsw(u_int port, const void *addr, size_t count);
807 void outw(u_int port, u_short data);
808 u_long rcr0(void);
809 u_long rcr2(void);
810 u_long rcr3(void);
811 u_long rcr4(void);
812 uint64_t rdmsr(u_int msr);
813 uint64_t rdpmc(u_int pmc);
814 uint64_t rdr0(void);
815 uint64_t rdr1(void);
816 uint64_t rdr2(void);
817 uint64_t rdr3(void);
818 uint64_t rdr4(void);
819 uint64_t rdr5(void);
820 uint64_t rdr6(void);
821 uint64_t rdr7(void);
822 uint64_t rdtsc(void);
823 u_long read_rflags(void);
824 u_int rfs(void);
825 u_int rgs(void);
826 void wbinvd(void);
827 void write_rflags(u_int rf);
828 void wrmsr(u_int msr, uint64_t newval);
829
830 #endif /* __GNUCLIKE_ASM && __CC_SUPPORTS___INLINE */
831
832 void reset_dbregs(void);
833
834 #ifdef _KERNEL
835 int rdmsr_safe(u_int msr, uint64_t *val);
836 int wrmsr_safe(u_int msr, uint64_t newval);
837 #endif
838
839 #endif /* !_MACHINE_CPUFUNC_H_ */
840