1 /*
2 * $FreeBSD$
3 */
4
5 #ifndef _INTEL_RINGBUFFER_H_
6 #define _INTEL_RINGBUFFER_H_
7
8 /*
9 * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use"
10 * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use"
11 * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use"
12 *
13 * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same
14 * cacheline, the Head Pointer must not be greater than the Tail
15 * Pointer."
16 */
17 #define I915_RING_FREE_SPACE 64
18
19 struct intel_hw_status_page {
20 u32 *page_addr;
21 unsigned int gfx_addr;
22 struct drm_i915_gem_object *obj;
23 };
24
25 #define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
26 #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
27
28 #define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
29 #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
30
31 #define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base))
32 #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
33
34 #define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
35 #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
36
37 #define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
38 #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
39
40 #define I915_READ_NOPID(ring) I915_READ(RING_NOPID((ring)->mmio_base))
41 #define I915_READ_SYNC_0(ring) I915_READ(RING_SYNC_0((ring)->mmio_base))
42 #define I915_READ_SYNC_1(ring) I915_READ(RING_SYNC_1((ring)->mmio_base))
43
44 struct intel_ring_buffer {
45 const char *name;
46 enum intel_ring_id {
47 RCS = 0x0,
48 VCS,
49 BCS,
50 } id;
51 #define I915_NUM_RINGS 3
52 u32 mmio_base;
53 void *virtual_start;
54 struct drm_device *dev;
55 struct drm_i915_gem_object *obj;
56
57 u32 head;
58 u32 tail;
59 int space;
60 int size;
61 int effective_size;
62 struct intel_hw_status_page status_page;
63
64 /** We track the position of the requests in the ring buffer, and
65 * when each is retired we increment last_retired_head as the GPU
66 * must have finished processing the request and so we know we
67 * can advance the ringbuffer up to that position.
68 *
69 * last_retired_head is set to -1 after the value is consumed so
70 * we can detect new retirements.
71 */
72 u32 last_retired_head;
73
74 u32 irq_refcount; /* protected by dev_priv->irq_lock */
75 u32 irq_enable_mask; /* bitmask to enable ring interrupt */
76 u32 trace_irq_seqno;
77 u32 sync_seqno[I915_NUM_RINGS-1];
78 bool (*irq_get)(struct intel_ring_buffer *ring);
79 void (*irq_put)(struct intel_ring_buffer *ring);
80
81 int (*init)(struct intel_ring_buffer *ring);
82
83 void (*write_tail)(struct intel_ring_buffer *ring,
84 u32 value);
85 int (*flush)(struct intel_ring_buffer *ring,
86 u32 invalidate_domains,
87 u32 flush_domains);
88 int (*add_request)(struct intel_ring_buffer *ring,
89 uint32_t *seqno);
90 uint32_t (*get_seqno)(struct intel_ring_buffer *ring);
91 int (*dispatch_execbuffer)(struct intel_ring_buffer *ring,
92 u32 offset, u32 length);
93 #define I915_DISPATCH_SECURE 0x1
94 #define I915_DISPATCH_PINNED 0x2
95 void (*cleanup)(struct intel_ring_buffer *ring);
96 int (*sync_to)(struct intel_ring_buffer *ring,
97 struct intel_ring_buffer *to,
98 u32 seqno);
99
100 u32 semaphore_register[3]; /*our mbox written by others */
101 u32 signal_mbox[2]; /* mboxes this ring signals to */
102 /**
103 * List of objects currently involved in rendering from the
104 * ringbuffer.
105 *
106 * Includes buffers having the contents of their GPU caches
107 * flushed, not necessarily primitives. last_rendering_seqno
108 * represents when the rendering involved will be completed.
109 *
110 * A reference is held on the buffer while on this list.
111 */
112 struct list_head active_list;
113
114 /**
115 * List of breadcrumbs associated with GPU requests currently
116 * outstanding.
117 */
118 struct list_head request_list;
119
120 /**
121 * List of objects currently pending a GPU write flush.
122 *
123 * All elements on this list will belong to either the
124 * active_list or flushing_list, last_rendering_seqno can
125 * be used to differentiate between the two elements.
126 */
127 struct list_head gpu_write_list;
128
129 /**
130 * Do we have some not yet emitted requests outstanding?
131 */
132 u32 outstanding_lazy_request;
133
134 /**
135 * Do an explicit TLB flush before MI_SET_CONTEXT
136 */
137 bool itlb_before_ctx_switch;
138 struct i915_hw_context *default_context;
139 struct drm_i915_gem_object *last_context_obj;
140
141 drm_local_map_t map;
142
143 void *private;
144 };
145
146 static inline bool
intel_ring_initialized(struct intel_ring_buffer * ring)147 intel_ring_initialized(struct intel_ring_buffer *ring)
148 {
149 return ring->obj != NULL;
150 }
151
152 static inline unsigned
intel_ring_flag(struct intel_ring_buffer * ring)153 intel_ring_flag(struct intel_ring_buffer *ring)
154 {
155 return 1 << ring->id;
156 }
157
158 static inline u32
intel_ring_sync_index(struct intel_ring_buffer * ring,struct intel_ring_buffer * other)159 intel_ring_sync_index(struct intel_ring_buffer *ring,
160 struct intel_ring_buffer *other)
161 {
162 int idx;
163
164 /*
165 * cs -> 0 = vcs, 1 = bcs
166 * vcs -> 0 = bcs, 1 = cs,
167 * bcs -> 0 = cs, 1 = vcs.
168 */
169
170 idx = (other - ring) - 1;
171 if (idx < 0)
172 idx += I915_NUM_RINGS;
173
174 return idx;
175 }
176
177 static inline u32
intel_read_status_page(struct intel_ring_buffer * ring,int reg)178 intel_read_status_page(struct intel_ring_buffer *ring,
179 int reg)
180 {
181 /* Ensure that the compiler doesn't optimize away the load. */
182 __compiler_membar();
183 return atomic_load_acq_32(ring->status_page.page_addr + reg);
184 }
185
186 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring);
187
188 int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n);
intel_wait_ring_idle(struct intel_ring_buffer * ring)189 static inline int intel_wait_ring_idle(struct intel_ring_buffer *ring)
190 {
191
192 return (intel_wait_ring_buffer(ring, ring->size - 8));
193 }
194
195 int intel_ring_begin(struct intel_ring_buffer *ring, int n);
196
intel_ring_emit(struct intel_ring_buffer * ring,u32 data)197 static inline void intel_ring_emit(struct intel_ring_buffer *ring,
198 u32 data)
199 {
200 *(volatile uint32_t *)((char *)ring->virtual_start +
201 ring->tail) = data;
202 ring->tail += 4;
203 }
204
205 void intel_ring_advance(struct intel_ring_buffer *ring);
206
207 uint32_t intel_ring_get_seqno(struct intel_ring_buffer *ring);
208
209 int intel_init_render_ring_buffer(struct drm_device *dev);
210 int intel_init_bsd_ring_buffer(struct drm_device *dev);
211 int intel_init_blt_ring_buffer(struct drm_device *dev);
212
213 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring);
214 void intel_ring_setup_status_page(struct intel_ring_buffer *ring);
215
intel_ring_get_tail(struct intel_ring_buffer * ring)216 static inline u32 intel_ring_get_tail(struct intel_ring_buffer *ring)
217 {
218 return ring->tail;
219 }
220
221 void i915_trace_irq_get(struct intel_ring_buffer *ring, uint32_t seqno);
222
223 /* DRI warts */
224 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size);
225
226 #endif /* _INTEL_RINGBUFFER_H_ */
227