1 /*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
27 */
28
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
31
32 #include <dev/drm2/drmP.h>
33 #include <dev/drm2/drm.h>
34 #include <dev/drm2/drm_crtc.h>
35 #include <dev/drm2/drm_edid.h>
36 #include <dev/drm2/i915/i915_drm.h>
37 #include <dev/drm2/i915/i915_drv.h>
38 #include <dev/drm2/i915/intel_drv.h>
39
enc_to_intel_hdmi(struct drm_encoder * encoder)40 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
41 {
42 return container_of(encoder, struct intel_hdmi, base.base);
43 }
44
intel_attached_hdmi(struct drm_connector * connector)45 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
46 {
47 return container_of(intel_attached_encoder(connector),
48 struct intel_hdmi, base);
49 }
50
intel_dip_infoframe_csum(struct dip_infoframe * frame)51 void intel_dip_infoframe_csum(struct dip_infoframe *frame)
52 {
53 uint8_t *data = (uint8_t *)frame;
54 uint8_t sum = 0;
55 unsigned i;
56
57 frame->checksum = 0;
58 frame->ecc = 0;
59
60 for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++)
61 sum += data[i];
62
63 frame->checksum = 0x100 - sum;
64 }
65
g4x_infoframe_index(struct dip_infoframe * frame)66 static u32 g4x_infoframe_index(struct dip_infoframe *frame)
67 {
68 switch (frame->type) {
69 case DIP_TYPE_AVI:
70 return VIDEO_DIP_SELECT_AVI;
71 case DIP_TYPE_SPD:
72 return VIDEO_DIP_SELECT_SPD;
73 default:
74 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
75 return 0;
76 }
77 }
78
g4x_infoframe_enable(struct dip_infoframe * frame)79 static u32 g4x_infoframe_enable(struct dip_infoframe *frame)
80 {
81 switch (frame->type) {
82 case DIP_TYPE_AVI:
83 return VIDEO_DIP_ENABLE_AVI;
84 case DIP_TYPE_SPD:
85 return VIDEO_DIP_ENABLE_SPD;
86 default:
87 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
88 return 0;
89 }
90 }
91
hsw_infoframe_enable(struct dip_infoframe * frame)92 static u32 hsw_infoframe_enable(struct dip_infoframe *frame)
93 {
94 switch (frame->type) {
95 case DIP_TYPE_AVI:
96 return VIDEO_DIP_ENABLE_AVI_HSW;
97 case DIP_TYPE_SPD:
98 return VIDEO_DIP_ENABLE_SPD_HSW;
99 default:
100 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
101 return 0;
102 }
103 }
104
hsw_infoframe_data_reg(struct dip_infoframe * frame,enum pipe pipe)105 static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame, enum pipe pipe)
106 {
107 switch (frame->type) {
108 case DIP_TYPE_AVI:
109 return HSW_TVIDEO_DIP_AVI_DATA(pipe);
110 case DIP_TYPE_SPD:
111 return HSW_TVIDEO_DIP_SPD_DATA(pipe);
112 default:
113 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
114 return 0;
115 }
116 }
117
g4x_write_infoframe(struct drm_encoder * encoder,struct dip_infoframe * frame)118 static void g4x_write_infoframe(struct drm_encoder *encoder,
119 struct dip_infoframe *frame)
120 {
121 uint32_t *data = (uint32_t *)frame;
122 struct drm_device *dev = encoder->dev;
123 struct drm_i915_private *dev_priv = dev->dev_private;
124 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
125 u32 val = I915_READ(VIDEO_DIP_CTL);
126 unsigned i, len = DIP_HEADER_SIZE + frame->len;
127
128 val &= ~VIDEO_DIP_PORT_MASK;
129 if (intel_hdmi->sdvox_reg == SDVOB)
130 val |= VIDEO_DIP_PORT_B;
131 else if (intel_hdmi->sdvox_reg == SDVOC)
132 val |= VIDEO_DIP_PORT_C;
133 else
134 return;
135
136 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
137 val |= g4x_infoframe_index(frame);
138
139 val &= ~g4x_infoframe_enable(frame);
140 val |= VIDEO_DIP_ENABLE;
141
142 I915_WRITE(VIDEO_DIP_CTL, val);
143
144 for (i = 0; i < len; i += 4) {
145 I915_WRITE(VIDEO_DIP_DATA, *data);
146 data++;
147 }
148
149 val |= g4x_infoframe_enable(frame);
150 val &= ~VIDEO_DIP_FREQ_MASK;
151 val |= VIDEO_DIP_FREQ_VSYNC;
152
153 I915_WRITE(VIDEO_DIP_CTL, val);
154 }
155
ibx_write_infoframe(struct drm_encoder * encoder,struct dip_infoframe * frame)156 static void ibx_write_infoframe(struct drm_encoder *encoder,
157 struct dip_infoframe *frame)
158 {
159 uint32_t *data = (uint32_t *)frame;
160 struct drm_device *dev = encoder->dev;
161 struct drm_i915_private *dev_priv = dev->dev_private;
162 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
163 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
164 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
165 unsigned i, len = DIP_HEADER_SIZE + frame->len;
166 u32 val = I915_READ(reg);
167
168 val &= ~VIDEO_DIP_PORT_MASK;
169 switch (intel_hdmi->sdvox_reg) {
170 case HDMIB:
171 val |= VIDEO_DIP_PORT_B;
172 break;
173 case HDMIC:
174 val |= VIDEO_DIP_PORT_C;
175 break;
176 case HDMID:
177 val |= VIDEO_DIP_PORT_D;
178 break;
179 default:
180 return;
181 }
182
183 intel_wait_for_vblank(dev, intel_crtc->pipe);
184
185 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
186 val |= g4x_infoframe_index(frame);
187
188 val &= ~g4x_infoframe_enable(frame);
189 val |= VIDEO_DIP_ENABLE;
190
191 I915_WRITE(reg, val);
192
193 for (i = 0; i < len; i += 4) {
194 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
195 data++;
196 }
197
198 val |= g4x_infoframe_enable(frame);
199 val &= ~VIDEO_DIP_FREQ_MASK;
200 val |= VIDEO_DIP_FREQ_VSYNC;
201
202 I915_WRITE(reg, val);
203 }
204
cpt_write_infoframe(struct drm_encoder * encoder,struct dip_infoframe * frame)205 static void cpt_write_infoframe(struct drm_encoder *encoder,
206 struct dip_infoframe *frame)
207 {
208 uint32_t *data = (uint32_t *)frame;
209 struct drm_device *dev = encoder->dev;
210 struct drm_i915_private *dev_priv = dev->dev_private;
211 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
212 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
213 unsigned i, len = DIP_HEADER_SIZE + frame->len;
214 u32 val = I915_READ(reg);
215
216 intel_wait_for_vblank(dev, intel_crtc->pipe);
217
218 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
219 val |= g4x_infoframe_index(frame);
220
221 /* The DIP control register spec says that we need to update the AVI
222 * infoframe without clearing its enable bit */
223 if (frame->type == DIP_TYPE_AVI)
224 val |= VIDEO_DIP_ENABLE_AVI;
225 else
226 val &= ~g4x_infoframe_enable(frame);
227
228 val |= VIDEO_DIP_ENABLE;
229
230 I915_WRITE(reg, val);
231
232 for (i = 0; i < len; i += 4) {
233 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
234 data++;
235 }
236
237 val |= g4x_infoframe_enable(frame);
238 val &= ~VIDEO_DIP_FREQ_MASK;
239 val |= VIDEO_DIP_FREQ_VSYNC;
240
241 I915_WRITE(reg, val);
242 }
243
vlv_write_infoframe(struct drm_encoder * encoder,struct dip_infoframe * frame)244 static void vlv_write_infoframe(struct drm_encoder *encoder,
245 struct dip_infoframe *frame)
246 {
247 uint32_t *data = (uint32_t *)frame;
248 struct drm_device *dev = encoder->dev;
249 struct drm_i915_private *dev_priv = dev->dev_private;
250 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
251 int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
252 unsigned i, len = DIP_HEADER_SIZE + frame->len;
253 u32 val = I915_READ(reg);
254
255 intel_wait_for_vblank(dev, intel_crtc->pipe);
256
257 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
258 val |= g4x_infoframe_index(frame);
259
260 val &= ~g4x_infoframe_enable(frame);
261 val |= VIDEO_DIP_ENABLE;
262
263 I915_WRITE(reg, val);
264
265 for (i = 0; i < len; i += 4) {
266 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
267 data++;
268 }
269
270 val |= g4x_infoframe_enable(frame);
271 val &= ~VIDEO_DIP_FREQ_MASK;
272 val |= VIDEO_DIP_FREQ_VSYNC;
273
274 I915_WRITE(reg, val);
275 }
276
hsw_write_infoframe(struct drm_encoder * encoder,struct dip_infoframe * frame)277 static void hsw_write_infoframe(struct drm_encoder *encoder,
278 struct dip_infoframe *frame)
279 {
280 uint32_t *data = (uint32_t *)frame;
281 struct drm_device *dev = encoder->dev;
282 struct drm_i915_private *dev_priv = dev->dev_private;
283 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
284 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe);
285 u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->pipe);
286 unsigned int i, len = DIP_HEADER_SIZE + frame->len;
287 u32 val = I915_READ(ctl_reg);
288
289 if (data_reg == 0)
290 return;
291
292 intel_wait_for_vblank(dev, intel_crtc->pipe);
293
294 val &= ~hsw_infoframe_enable(frame);
295 I915_WRITE(ctl_reg, val);
296
297 for (i = 0; i < len; i += 4) {
298 I915_WRITE(data_reg + i, *data);
299 data++;
300 }
301
302 val |= hsw_infoframe_enable(frame);
303 I915_WRITE(ctl_reg, val);
304 }
305
intel_set_infoframe(struct drm_encoder * encoder,struct dip_infoframe * frame)306 static void intel_set_infoframe(struct drm_encoder *encoder,
307 struct dip_infoframe *frame)
308 {
309 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
310
311 if (!intel_hdmi->has_hdmi_sink)
312 return;
313
314 intel_dip_infoframe_csum(frame);
315 intel_hdmi->write_infoframe(encoder, frame);
316 }
317
intel_hdmi_set_avi_infoframe(struct drm_encoder * encoder,struct drm_display_mode * adjusted_mode)318 void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
319 struct drm_display_mode *adjusted_mode)
320 {
321 struct dip_infoframe avi_if = {
322 .type = DIP_TYPE_AVI,
323 .ver = DIP_VERSION_AVI,
324 .len = DIP_LEN_AVI,
325 };
326
327 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
328 avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2;
329
330 intel_set_infoframe(encoder, &avi_if);
331 }
332
intel_hdmi_set_spd_infoframe(struct drm_encoder * encoder)333 void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
334 {
335 struct dip_infoframe spd_if;
336
337 memset(&spd_if, 0, sizeof(spd_if));
338 spd_if.type = DIP_TYPE_SPD;
339 spd_if.ver = DIP_VERSION_SPD;
340 spd_if.len = DIP_LEN_SPD;
341 strcpy(spd_if.body.spd.vn, "Intel");
342 strcpy(spd_if.body.spd.pd, "Integrated gfx");
343 spd_if.body.spd.sdi = DIP_SPD_PC;
344
345 intel_set_infoframe(encoder, &spd_if);
346 }
347
intel_hdmi_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)348 static void intel_hdmi_mode_set(struct drm_encoder *encoder,
349 struct drm_display_mode *mode,
350 struct drm_display_mode *adjusted_mode)
351 {
352 struct drm_device *dev = encoder->dev;
353 struct drm_i915_private *dev_priv = dev->dev_private;
354 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
355 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
356 u32 sdvox;
357
358 sdvox = SDVO_ENCODING_HDMI | SDVO_BORDER_ENABLE;
359 if (!HAS_PCH_SPLIT(dev))
360 sdvox |= intel_hdmi->color_range;
361 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
362 sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
363 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
364 sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
365
366 if (intel_crtc->bpp > 24)
367 sdvox |= COLOR_FORMAT_12bpc;
368 else
369 sdvox |= COLOR_FORMAT_8bpc;
370
371 /* Required on CPT */
372 if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
373 sdvox |= HDMI_MODE_SELECT;
374
375 if (intel_hdmi->has_audio) {
376 DRM_DEBUG_KMS("Enabling HDMI audio on pipe %c\n",
377 pipe_name(intel_crtc->pipe));
378 sdvox |= SDVO_AUDIO_ENABLE;
379 sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC;
380 intel_write_eld(encoder, adjusted_mode);
381 }
382
383 if (HAS_PCH_CPT(dev))
384 sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe);
385 else if (intel_crtc->pipe == 1)
386 sdvox |= SDVO_PIPE_B_SELECT;
387
388 I915_WRITE(intel_hdmi->sdvox_reg, sdvox);
389 POSTING_READ(intel_hdmi->sdvox_reg);
390
391 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
392 intel_hdmi_set_spd_infoframe(encoder);
393 }
394
intel_hdmi_dpms(struct drm_encoder * encoder,int mode)395 static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode)
396 {
397 struct drm_device *dev = encoder->dev;
398 struct drm_i915_private *dev_priv = dev->dev_private;
399 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
400 u32 temp;
401 u32 enable_bits = SDVO_ENABLE;
402
403 if (intel_hdmi->has_audio)
404 enable_bits |= SDVO_AUDIO_ENABLE;
405
406 temp = I915_READ(intel_hdmi->sdvox_reg);
407
408 /* HW workaround, need to toggle enable bit off and on for 12bpc, but
409 * we do this anyway which shows more stable in testing.
410 */
411 if (HAS_PCH_SPLIT(dev)) {
412 I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
413 POSTING_READ(intel_hdmi->sdvox_reg);
414 }
415
416 if (mode != DRM_MODE_DPMS_ON) {
417 temp &= ~enable_bits;
418 } else {
419 temp |= enable_bits;
420 }
421
422 I915_WRITE(intel_hdmi->sdvox_reg, temp);
423 POSTING_READ(intel_hdmi->sdvox_reg);
424
425 /* HW workaround, need to write this twice for issue that may result
426 * in first write getting masked.
427 */
428 if (HAS_PCH_SPLIT(dev)) {
429 I915_WRITE(intel_hdmi->sdvox_reg, temp);
430 POSTING_READ(intel_hdmi->sdvox_reg);
431 }
432 }
433
intel_hdmi_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)434 static int intel_hdmi_mode_valid(struct drm_connector *connector,
435 struct drm_display_mode *mode)
436 {
437 if (mode->clock > 165000)
438 return MODE_CLOCK_HIGH;
439 if (mode->clock < 20000)
440 return MODE_CLOCK_LOW;
441
442 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
443 return MODE_NO_DBLESCAN;
444
445 return MODE_OK;
446 }
447
intel_hdmi_mode_fixup(struct drm_encoder * encoder,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)448 static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
449 const struct drm_display_mode *mode,
450 struct drm_display_mode *adjusted_mode)
451 {
452 return true;
453 }
454
455 static enum drm_connector_status
intel_hdmi_detect(struct drm_connector * connector,bool force)456 intel_hdmi_detect(struct drm_connector *connector, bool force)
457 {
458 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
459 struct drm_i915_private *dev_priv = connector->dev->dev_private;
460 struct edid *edid;
461 enum drm_connector_status status = connector_status_disconnected;
462
463 intel_hdmi->has_hdmi_sink = false;
464 intel_hdmi->has_audio = false;
465 edid = drm_get_edid(connector, intel_gmbus_get_adapter(dev_priv,
466 intel_hdmi->ddc_bus));
467
468 if (edid) {
469 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
470 status = connector_status_connected;
471 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
472 intel_hdmi->has_hdmi_sink =
473 drm_detect_hdmi_monitor(edid);
474 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
475 }
476 free(edid, DRM_MEM_KMS);
477 } else {
478 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] got no edid, ddc port %d\n",
479 connector->base.id, drm_get_connector_name(connector),
480 intel_hdmi->ddc_bus);
481 }
482
483 if (status == connector_status_connected) {
484 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
485 intel_hdmi->has_audio =
486 (intel_hdmi->force_audio == HDMI_AUDIO_ON);
487 }
488
489 return status;
490 }
491
intel_hdmi_get_modes(struct drm_connector * connector)492 static int intel_hdmi_get_modes(struct drm_connector *connector)
493 {
494 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
495 struct drm_i915_private *dev_priv = connector->dev->dev_private;
496
497 /* We should parse the EDID data and find out if it's an HDMI sink so
498 * we can send audio to it.
499 */
500
501 return intel_ddc_get_modes(connector,
502 intel_gmbus_get_adapter(dev_priv,
503 intel_hdmi->ddc_bus));
504 }
505
506 static bool
intel_hdmi_detect_audio(struct drm_connector * connector)507 intel_hdmi_detect_audio(struct drm_connector *connector)
508 {
509 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
510 struct drm_i915_private *dev_priv = connector->dev->dev_private;
511 struct edid *edid;
512 bool has_audio = false;
513
514 edid = drm_get_edid(connector,
515 intel_gmbus_get_adapter(dev_priv,
516 intel_hdmi->ddc_bus));
517 if (edid) {
518 if (edid->input & DRM_EDID_INPUT_DIGITAL)
519 has_audio = drm_detect_monitor_audio(edid);
520
521 free(edid, DRM_MEM_KMS);
522 }
523
524 return has_audio;
525 }
526
527 static int
intel_hdmi_set_property(struct drm_connector * connector,struct drm_property * property,uint64_t val)528 intel_hdmi_set_property(struct drm_connector *connector,
529 struct drm_property *property,
530 uint64_t val)
531 {
532 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
533 struct drm_i915_private *dev_priv = connector->dev->dev_private;
534 int ret;
535
536 ret = drm_object_property_set_value(&connector->base, property, val);
537 if (ret)
538 return ret;
539
540 if (property == dev_priv->force_audio_property) {
541 enum hdmi_force_audio i = val;
542 bool has_audio;
543
544 if (i == intel_hdmi->force_audio)
545 return 0;
546
547 intel_hdmi->force_audio = i;
548
549 if (i == HDMI_AUDIO_AUTO)
550 has_audio = intel_hdmi_detect_audio(connector);
551 else
552 has_audio = (i == HDMI_AUDIO_ON);
553
554 if (i == HDMI_AUDIO_OFF_DVI)
555 intel_hdmi->has_hdmi_sink = 0;
556
557 intel_hdmi->has_audio = has_audio;
558 goto done;
559 }
560
561 if (property == dev_priv->broadcast_rgb_property) {
562 if (val == !!intel_hdmi->color_range)
563 return 0;
564
565 intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
566 goto done;
567 }
568
569 return -EINVAL;
570
571 done:
572 if (intel_hdmi->base.base.crtc) {
573 struct drm_crtc *crtc = intel_hdmi->base.base.crtc;
574 drm_crtc_helper_set_mode(crtc, &crtc->mode,
575 crtc->x, crtc->y,
576 crtc->fb);
577 }
578
579 return 0;
580 }
581
intel_hdmi_destroy(struct drm_connector * connector)582 static void intel_hdmi_destroy(struct drm_connector *connector)
583 {
584 #if 0
585 drm_sysfs_connector_remove(connector);
586 #endif
587 drm_connector_cleanup(connector);
588 free(connector, DRM_MEM_KMS);
589 }
590
591 static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs_hsw = {
592 .dpms = intel_ddi_dpms,
593 .mode_fixup = intel_hdmi_mode_fixup,
594 .prepare = intel_encoder_prepare,
595 .mode_set = intel_ddi_mode_set,
596 .commit = intel_encoder_commit,
597 };
598
599 static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = {
600 .dpms = intel_hdmi_dpms,
601 .mode_fixup = intel_hdmi_mode_fixup,
602 .prepare = intel_encoder_prepare,
603 .mode_set = intel_hdmi_mode_set,
604 .commit = intel_encoder_commit,
605 };
606
607 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
608 .dpms = drm_helper_connector_dpms,
609 .detect = intel_hdmi_detect,
610 .fill_modes = drm_helper_probe_single_connector_modes,
611 .set_property = intel_hdmi_set_property,
612 .destroy = intel_hdmi_destroy,
613 };
614
615 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
616 .get_modes = intel_hdmi_get_modes,
617 .mode_valid = intel_hdmi_mode_valid,
618 .best_encoder = intel_best_encoder,
619 };
620
621 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
622 .destroy = intel_encoder_destroy,
623 };
624
625 static void
intel_hdmi_add_properties(struct intel_hdmi * intel_hdmi,struct drm_connector * connector)626 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
627 {
628 intel_attach_force_audio_property(connector);
629 intel_attach_broadcast_rgb_property(connector);
630 }
631
intel_hdmi_init(struct drm_device * dev,int sdvox_reg)632 void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
633 {
634 struct drm_i915_private *dev_priv = dev->dev_private;
635 struct drm_connector *connector;
636 struct intel_encoder *intel_encoder;
637 struct intel_connector *intel_connector;
638 struct intel_hdmi *intel_hdmi;
639 int i;
640
641 intel_hdmi = malloc(sizeof(struct intel_hdmi), DRM_MEM_KMS,
642 M_WAITOK | M_ZERO);
643 intel_connector = malloc(sizeof(struct intel_connector), DRM_MEM_KMS,
644 M_WAITOK | M_ZERO);
645
646 intel_encoder = &intel_hdmi->base;
647 drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
648 DRM_MODE_ENCODER_TMDS);
649
650 connector = &intel_connector->base;
651 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
652 DRM_MODE_CONNECTOR_HDMIA);
653 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
654
655 intel_encoder->type = INTEL_OUTPUT_HDMI;
656
657 connector->polled = DRM_CONNECTOR_POLL_HPD;
658 connector->interlace_allowed = 1;
659 connector->doublescan_allowed = 0;
660 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
661
662 /* Set up the DDC bus. */
663 if (sdvox_reg == SDVOB) {
664 intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT);
665 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
666 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
667 } else if (sdvox_reg == SDVOC) {
668 intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT);
669 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
670 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
671 } else if (sdvox_reg == HDMIB) {
672 intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT);
673 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
674 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
675 } else if (sdvox_reg == HDMIC) {
676 intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT);
677 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
678 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
679 } else if (sdvox_reg == HDMID) {
680 intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT);
681 intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
682 dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
683 } else if (sdvox_reg == DDI_BUF_CTL(PORT_B)) {
684 DRM_DEBUG_DRIVER("LPT: detected output on DDI B\n");
685 intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT);
686 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
687 intel_hdmi->ddi_port = PORT_B;
688 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
689 } else if (sdvox_reg == DDI_BUF_CTL(PORT_C)) {
690 DRM_DEBUG_DRIVER("LPT: detected output on DDI C\n");
691 intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT);
692 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
693 intel_hdmi->ddi_port = PORT_C;
694 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
695 } else if (sdvox_reg == DDI_BUF_CTL(PORT_D)) {
696 DRM_DEBUG_DRIVER("LPT: detected output on DDI D\n");
697 intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT);
698 intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
699 intel_hdmi->ddi_port = PORT_D;
700 dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
701 } else {
702 /* If we got an unknown sdvox_reg, things are pretty much broken
703 * in a way that we should let the kernel know about it */
704 DRM_DEBUG_KMS("unknown sdvox_reg %d\n", sdvox_reg);
705 }
706
707 intel_hdmi->sdvox_reg = sdvox_reg;
708 if (!HAS_PCH_SPLIT(dev)) {
709 intel_hdmi->write_infoframe = g4x_write_infoframe;
710 I915_WRITE(VIDEO_DIP_CTL, 0);
711 } else if (IS_VALLEYVIEW(dev)) {
712 intel_hdmi->write_infoframe = vlv_write_infoframe;
713 for_each_pipe(i)
714 I915_WRITE(VLV_TVIDEO_DIP_CTL(i), 0);
715 } else if (IS_HASWELL(dev)) {
716 /* FIXME: Haswell has a new set of DIP frame registers, but we are
717 * just doing the minimal required for HDMI to work at this stage.
718 */
719 intel_hdmi->write_infoframe = hsw_write_infoframe;
720 for_each_pipe(i)
721 I915_WRITE(HSW_TVIDEO_DIP_CTL(i), 0);
722 } else if (HAS_PCH_IBX(dev)) {
723 intel_hdmi->write_infoframe = ibx_write_infoframe;
724 for_each_pipe(i)
725 I915_WRITE(TVIDEO_DIP_CTL(i), 0);
726 } else {
727 intel_hdmi->write_infoframe = cpt_write_infoframe;
728 for_each_pipe(i)
729 I915_WRITE(TVIDEO_DIP_CTL(i), 0);
730 }
731
732 if (IS_HASWELL(dev))
733 drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs_hsw);
734 else
735 drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs);
736
737 intel_hdmi_add_properties(intel_hdmi, connector);
738
739 intel_connector_attach_encoder(intel_connector, intel_encoder);
740 #if 0
741 drm_sysfs_connector_add(connector);
742 #endif
743
744 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
745 * 0xd. Failure to do so will result in spurious interrupts being
746 * generated on the port when a cable is not attached.
747 */
748 if (IS_G4X(dev) && !IS_GM45(dev)) {
749 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
750 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
751 }
752 }
753