1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2019 Intel Corporation
4 */
5
6 #include <drm/drm_managed.h>
7 #include <drm/intel/intel-gtt.h>
8
9 #include "gem/i915_gem_internal.h"
10 #include "gem/i915_gem_lmem.h"
11
12 #include "i915_drv.h"
13 #include "i915_perf_oa_regs.h"
14 #include "i915_reg.h"
15 #include "intel_context.h"
16 #include "intel_engine_pm.h"
17 #include "intel_engine_regs.h"
18 #include "intel_ggtt_gmch.h"
19 #include "intel_gt.h"
20 #include "intel_gt_buffer_pool.h"
21 #include "intel_gt_clock_utils.h"
22 #include "intel_gt_debugfs.h"
23 #include "intel_gt_mcr.h"
24 #include "intel_gt_pm.h"
25 #include "intel_gt_print.h"
26 #include "intel_gt_regs.h"
27 #include "intel_gt_requests.h"
28 #include "intel_migrate.h"
29 #include "intel_mocs.h"
30 #include "intel_pci_config.h"
31 #include "intel_rc6.h"
32 #include "intel_renderstate.h"
33 #include "intel_rps.h"
34 #include "intel_sa_media.h"
35 #include "intel_gt_sysfs.h"
36 #include "intel_tlb.h"
37 #include "intel_uncore.h"
38 #include "shmem_utils.h"
39
intel_gt_common_init_early(struct intel_gt * gt)40 void intel_gt_common_init_early(struct intel_gt *gt)
41 {
42 mtx_init(gt->irq_lock, IPL_TTY);
43
44 INIT_LIST_HEAD(>->closed_vma);
45 mtx_init(>->closed_lock, IPL_TTY);
46
47 init_llist_head(>->watchdog.list);
48 INIT_WORK(>->watchdog.work, intel_gt_watchdog_work);
49
50 intel_gt_init_buffer_pool(gt);
51 intel_gt_init_reset(gt);
52 intel_gt_init_requests(gt);
53 intel_gt_init_timelines(gt);
54 intel_gt_init_tlb(gt);
55 intel_gt_pm_init_early(gt);
56
57 intel_wopcm_init_early(>->wopcm);
58 intel_uc_init_early(>->uc);
59 intel_rps_init_early(>->rps);
60 }
61
62 /* Preliminary initialization of Tile 0 */
intel_root_gt_init_early(struct drm_i915_private * i915)63 int intel_root_gt_init_early(struct drm_i915_private *i915)
64 {
65 struct intel_gt *gt;
66
67 gt = drmm_kzalloc(&i915->drm, sizeof(*gt), GFP_KERNEL);
68 if (!gt)
69 return -ENOMEM;
70
71 i915->gt[0] = gt;
72
73 gt->i915 = i915;
74 gt->uncore = &i915->uncore;
75 gt->irq_lock = drmm_kzalloc(&i915->drm, sizeof(*gt->irq_lock), GFP_KERNEL);
76 if (!gt->irq_lock)
77 return -ENOMEM;
78
79 intel_gt_common_init_early(gt);
80
81 return 0;
82 }
83
intel_gt_probe_lmem(struct intel_gt * gt)84 static int intel_gt_probe_lmem(struct intel_gt *gt)
85 {
86 struct drm_i915_private *i915 = gt->i915;
87 unsigned int instance = gt->info.id;
88 int id = INTEL_REGION_LMEM_0 + instance;
89 struct intel_memory_region *mem;
90 int err;
91
92 mem = intel_gt_setup_lmem(gt);
93 if (IS_ERR(mem)) {
94 err = PTR_ERR(mem);
95 if (err == -ENODEV)
96 return 0;
97
98 gt_err(gt, "Failed to setup region(%d) type=%d\n",
99 err, INTEL_MEMORY_LOCAL);
100 return err;
101 }
102
103 mem->id = id;
104 mem->instance = instance;
105
106 intel_memory_region_set_name(mem, "local%u", mem->instance);
107
108 GEM_BUG_ON(!HAS_REGION(i915, id));
109 GEM_BUG_ON(i915->mm.regions[id]);
110 i915->mm.regions[id] = mem;
111
112 return 0;
113 }
114
intel_gt_assign_ggtt(struct intel_gt * gt)115 int intel_gt_assign_ggtt(struct intel_gt *gt)
116 {
117 /* Media GT shares primary GT's GGTT */
118 if (gt->type == GT_MEDIA) {
119 gt->ggtt = to_gt(gt->i915)->ggtt;
120 } else {
121 gt->ggtt = i915_ggtt_create(gt->i915);
122 if (IS_ERR(gt->ggtt))
123 return PTR_ERR(gt->ggtt);
124 }
125
126 list_add_tail(>->ggtt_link, >->ggtt->gt_list);
127
128 return 0;
129 }
130
intel_gt_init_mmio(struct intel_gt * gt)131 int intel_gt_init_mmio(struct intel_gt *gt)
132 {
133 intel_gt_init_clock_frequency(gt);
134
135 intel_uc_init_mmio(>->uc);
136 intel_sseu_info_init(gt);
137 intel_gt_mcr_init(gt);
138
139 return intel_engines_init_mmio(gt);
140 }
141
init_unused_ring(struct intel_gt * gt,u32 base)142 static void init_unused_ring(struct intel_gt *gt, u32 base)
143 {
144 struct intel_uncore *uncore = gt->uncore;
145
146 intel_uncore_write(uncore, RING_CTL(base), 0);
147 intel_uncore_write(uncore, RING_HEAD(base), 0);
148 intel_uncore_write(uncore, RING_TAIL(base), 0);
149 intel_uncore_write(uncore, RING_START(base), 0);
150 }
151
init_unused_rings(struct intel_gt * gt)152 static void init_unused_rings(struct intel_gt *gt)
153 {
154 struct drm_i915_private *i915 = gt->i915;
155
156 if (IS_I830(i915)) {
157 init_unused_ring(gt, PRB1_BASE);
158 init_unused_ring(gt, SRB0_BASE);
159 init_unused_ring(gt, SRB1_BASE);
160 init_unused_ring(gt, SRB2_BASE);
161 init_unused_ring(gt, SRB3_BASE);
162 } else if (GRAPHICS_VER(i915) == 2) {
163 init_unused_ring(gt, SRB0_BASE);
164 init_unused_ring(gt, SRB1_BASE);
165 } else if (GRAPHICS_VER(i915) == 3) {
166 init_unused_ring(gt, PRB1_BASE);
167 init_unused_ring(gt, PRB2_BASE);
168 }
169 }
170
intel_gt_init_hw(struct intel_gt * gt)171 int intel_gt_init_hw(struct intel_gt *gt)
172 {
173 struct drm_i915_private *i915 = gt->i915;
174 struct intel_uncore *uncore = gt->uncore;
175 int ret;
176
177 gt->last_init_time = ktime_get();
178
179 /* Double layer security blanket, see i915_gem_init() */
180 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
181
182 if (HAS_EDRAM(i915) && GRAPHICS_VER(i915) < 9)
183 intel_uncore_rmw(uncore, HSW_IDICR, 0, IDIHASHMSK(0xf));
184
185 if (IS_HASWELL(i915))
186 intel_uncore_write(uncore,
187 HSW_MI_PREDICATE_RESULT_2,
188 IS_HASWELL_GT3(i915) ?
189 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
190
191 /* Apply the GT workarounds... */
192 intel_gt_apply_workarounds(gt);
193 /* ...and determine whether they are sticking. */
194 intel_gt_verify_workarounds(gt, "init");
195
196 intel_gt_init_swizzling(gt);
197
198 /*
199 * At least 830 can leave some of the unused rings
200 * "active" (ie. head != tail) after resume which
201 * will prevent c3 entry. Makes sure all unused rings
202 * are totally idle.
203 */
204 init_unused_rings(gt);
205
206 ret = i915_ppgtt_init_hw(gt);
207 if (ret) {
208 gt_err(gt, "Enabling PPGTT failed (%d)\n", ret);
209 goto out;
210 }
211
212 /* We can't enable contexts until all firmware is loaded */
213 ret = intel_uc_init_hw(>->uc);
214 if (ret) {
215 gt_probe_error(gt, "Enabling uc failed (%d)\n", ret);
216 goto out;
217 }
218
219 intel_mocs_init(gt);
220
221 out:
222 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
223 return ret;
224 }
225
gen6_clear_engine_error_register(struct intel_engine_cs * engine)226 static void gen6_clear_engine_error_register(struct intel_engine_cs *engine)
227 {
228 GEN6_RING_FAULT_REG_RMW(engine, RING_FAULT_VALID, 0);
229 GEN6_RING_FAULT_REG_POSTING_READ(engine);
230 }
231
intel_gt_perf_limit_reasons_reg(struct intel_gt * gt)232 i915_reg_t intel_gt_perf_limit_reasons_reg(struct intel_gt *gt)
233 {
234 /* GT0_PERF_LIMIT_REASONS is available only for Gen11+ */
235 if (GRAPHICS_VER(gt->i915) < 11)
236 return INVALID_MMIO_REG;
237
238 return gt->type == GT_MEDIA ?
239 MTL_MEDIA_PERF_LIMIT_REASONS : GT0_PERF_LIMIT_REASONS;
240 }
241
242 void
intel_gt_clear_error_registers(struct intel_gt * gt,intel_engine_mask_t engine_mask)243 intel_gt_clear_error_registers(struct intel_gt *gt,
244 intel_engine_mask_t engine_mask)
245 {
246 struct drm_i915_private *i915 = gt->i915;
247 struct intel_uncore *uncore = gt->uncore;
248 u32 eir;
249
250 if (GRAPHICS_VER(i915) != 2)
251 intel_uncore_write(uncore, PGTBL_ER, 0);
252
253 if (GRAPHICS_VER(i915) < 4)
254 intel_uncore_write(uncore, IPEIR(RENDER_RING_BASE), 0);
255 else
256 intel_uncore_write(uncore, IPEIR_I965, 0);
257
258 intel_uncore_write(uncore, EIR, 0);
259 eir = intel_uncore_read(uncore, EIR);
260 if (eir) {
261 /*
262 * some errors might have become stuck,
263 * mask them.
264 */
265 gt_dbg(gt, "EIR stuck: 0x%08x, masking\n", eir);
266 intel_uncore_rmw(uncore, EMR, 0, eir);
267 intel_uncore_write(uncore, GEN2_IIR,
268 I915_MASTER_ERROR_INTERRUPT);
269 }
270
271 /*
272 * For the media GT, this ring fault register is not replicated,
273 * so don't do multicast/replicated register read/write operation on it.
274 */
275 if (MEDIA_VER(i915) >= 13 && gt->type == GT_MEDIA) {
276 intel_uncore_rmw(uncore, XELPMP_RING_FAULT_REG,
277 RING_FAULT_VALID, 0);
278 intel_uncore_posting_read(uncore,
279 XELPMP_RING_FAULT_REG);
280
281 } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {
282 intel_gt_mcr_multicast_rmw(gt, XEHP_RING_FAULT_REG,
283 RING_FAULT_VALID, 0);
284 intel_gt_mcr_read_any(gt, XEHP_RING_FAULT_REG);
285
286 } else if (GRAPHICS_VER(i915) >= 12) {
287 intel_uncore_rmw(uncore, GEN12_RING_FAULT_REG, RING_FAULT_VALID, 0);
288 intel_uncore_posting_read(uncore, GEN12_RING_FAULT_REG);
289 } else if (GRAPHICS_VER(i915) >= 8) {
290 intel_uncore_rmw(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID, 0);
291 intel_uncore_posting_read(uncore, GEN8_RING_FAULT_REG);
292 } else if (GRAPHICS_VER(i915) >= 6) {
293 struct intel_engine_cs *engine;
294 enum intel_engine_id id;
295
296 for_each_engine_masked(engine, gt, engine_mask, id)
297 gen6_clear_engine_error_register(engine);
298 }
299 }
300
gen6_check_faults(struct intel_gt * gt)301 static void gen6_check_faults(struct intel_gt *gt)
302 {
303 struct intel_engine_cs *engine;
304 enum intel_engine_id id;
305 u32 fault;
306
307 for_each_engine(engine, gt, id) {
308 fault = GEN6_RING_FAULT_REG_READ(engine);
309 if (fault & RING_FAULT_VALID) {
310 gt_dbg(gt, "Unexpected fault\n"
311 "\tAddr: 0x%08lx\n"
312 "\tAddress space: %s\n"
313 "\tSource ID: %d\n"
314 "\tType: %d\n",
315 (unsigned long)(fault & LINUX_PAGE_MASK),
316 fault & RING_FAULT_GTTSEL_MASK ?
317 "GGTT" : "PPGTT",
318 RING_FAULT_SRCID(fault),
319 RING_FAULT_FAULT_TYPE(fault));
320 }
321 }
322 }
323
xehp_check_faults(struct intel_gt * gt)324 static void xehp_check_faults(struct intel_gt *gt)
325 {
326 u32 fault;
327
328 /*
329 * Although the fault register now lives in an MCR register range,
330 * the GAM registers are special and we only truly need to read
331 * the "primary" GAM instance rather than handling each instance
332 * individually. intel_gt_mcr_read_any() will automatically steer
333 * toward the primary instance.
334 */
335 fault = intel_gt_mcr_read_any(gt, XEHP_RING_FAULT_REG);
336 if (fault & RING_FAULT_VALID) {
337 u32 fault_data0, fault_data1;
338 u64 fault_addr;
339
340 fault_data0 = intel_gt_mcr_read_any(gt, XEHP_FAULT_TLB_DATA0);
341 fault_data1 = intel_gt_mcr_read_any(gt, XEHP_FAULT_TLB_DATA1);
342
343 fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
344 ((u64)fault_data0 << 12);
345
346 gt_dbg(gt, "Unexpected fault\n"
347 "\tAddr: 0x%08x_%08x\n"
348 "\tAddress space: %s\n"
349 "\tEngine ID: %d\n"
350 "\tSource ID: %d\n"
351 "\tType: %d\n",
352 upper_32_bits(fault_addr), lower_32_bits(fault_addr),
353 fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
354 GEN8_RING_FAULT_ENGINE_ID(fault),
355 RING_FAULT_SRCID(fault),
356 RING_FAULT_FAULT_TYPE(fault));
357 }
358 }
359
gen8_check_faults(struct intel_gt * gt)360 static void gen8_check_faults(struct intel_gt *gt)
361 {
362 struct intel_uncore *uncore = gt->uncore;
363 i915_reg_t fault_reg, fault_data0_reg, fault_data1_reg;
364 u32 fault;
365
366 if (GRAPHICS_VER(gt->i915) >= 12) {
367 fault_reg = GEN12_RING_FAULT_REG;
368 fault_data0_reg = GEN12_FAULT_TLB_DATA0;
369 fault_data1_reg = GEN12_FAULT_TLB_DATA1;
370 } else {
371 fault_reg = GEN8_RING_FAULT_REG;
372 fault_data0_reg = GEN8_FAULT_TLB_DATA0;
373 fault_data1_reg = GEN8_FAULT_TLB_DATA1;
374 }
375
376 fault = intel_uncore_read(uncore, fault_reg);
377 if (fault & RING_FAULT_VALID) {
378 u32 fault_data0, fault_data1;
379 u64 fault_addr;
380
381 fault_data0 = intel_uncore_read(uncore, fault_data0_reg);
382 fault_data1 = intel_uncore_read(uncore, fault_data1_reg);
383
384 fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
385 ((u64)fault_data0 << 12);
386
387 gt_dbg(gt, "Unexpected fault\n"
388 "\tAddr: 0x%08x_%08x\n"
389 "\tAddress space: %s\n"
390 "\tEngine ID: %d\n"
391 "\tSource ID: %d\n"
392 "\tType: %d\n",
393 upper_32_bits(fault_addr), lower_32_bits(fault_addr),
394 fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
395 GEN8_RING_FAULT_ENGINE_ID(fault),
396 RING_FAULT_SRCID(fault),
397 RING_FAULT_FAULT_TYPE(fault));
398 }
399 }
400
intel_gt_check_and_clear_faults(struct intel_gt * gt)401 void intel_gt_check_and_clear_faults(struct intel_gt *gt)
402 {
403 struct drm_i915_private *i915 = gt->i915;
404
405 /* From GEN8 onwards we only have one 'All Engine Fault Register' */
406 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
407 xehp_check_faults(gt);
408 else if (GRAPHICS_VER(i915) >= 8)
409 gen8_check_faults(gt);
410 else if (GRAPHICS_VER(i915) >= 6)
411 gen6_check_faults(gt);
412 else
413 return;
414
415 intel_gt_clear_error_registers(gt, ALL_ENGINES);
416 }
417
intel_gt_flush_ggtt_writes(struct intel_gt * gt)418 void intel_gt_flush_ggtt_writes(struct intel_gt *gt)
419 {
420 struct intel_uncore *uncore = gt->uncore;
421 intel_wakeref_t wakeref;
422
423 /*
424 * No actual flushing is required for the GTT write domain for reads
425 * from the GTT domain. Writes to it "immediately" go to main memory
426 * as far as we know, so there's no chipset flush. It also doesn't
427 * land in the GPU render cache.
428 *
429 * However, we do have to enforce the order so that all writes through
430 * the GTT land before any writes to the device, such as updates to
431 * the GATT itself.
432 *
433 * We also have to wait a bit for the writes to land from the GTT.
434 * An uncached read (i.e. mmio) seems to be ideal for the round-trip
435 * timing. This issue has only been observed when switching quickly
436 * between GTT writes and CPU reads from inside the kernel on recent hw,
437 * and it appears to only affect discrete GTT blocks (i.e. on LLC
438 * system agents we cannot reproduce this behaviour, until Cannonlake
439 * that was!).
440 */
441
442 wmb();
443
444 if (INTEL_INFO(gt->i915)->has_coherent_ggtt)
445 return;
446
447 intel_gt_chipset_flush(gt);
448
449 with_intel_runtime_pm_if_in_use(uncore->rpm, wakeref) {
450 unsigned long flags;
451
452 spin_lock_irqsave(&uncore->lock, flags);
453 intel_uncore_posting_read_fw(uncore,
454 RING_TAIL(RENDER_RING_BASE));
455 spin_unlock_irqrestore(&uncore->lock, flags);
456 }
457 }
458
intel_gt_chipset_flush(struct intel_gt * gt)459 void intel_gt_chipset_flush(struct intel_gt *gt)
460 {
461 wmb();
462 if (GRAPHICS_VER(gt->i915) < 6)
463 intel_ggtt_gmch_flush();
464 }
465
intel_gt_driver_register(struct intel_gt * gt)466 void intel_gt_driver_register(struct intel_gt *gt)
467 {
468 intel_gsc_init(>->gsc, gt->i915);
469
470 intel_rps_driver_register(>->rps);
471
472 intel_gt_debugfs_register(gt);
473 intel_gt_sysfs_register(gt);
474 }
475
intel_gt_init_scratch(struct intel_gt * gt,unsigned int size)476 static int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size)
477 {
478 struct drm_i915_private *i915 = gt->i915;
479 struct drm_i915_gem_object *obj;
480 struct i915_vma *vma;
481 int ret;
482
483 obj = i915_gem_object_create_lmem(i915, size,
484 I915_BO_ALLOC_VOLATILE |
485 I915_BO_ALLOC_GPU_ONLY);
486 if (IS_ERR(obj) && !IS_METEORLAKE(i915)) /* Wa_22018444074 */
487 obj = i915_gem_object_create_stolen(i915, size);
488 if (IS_ERR(obj))
489 obj = i915_gem_object_create_internal(i915, size);
490 if (IS_ERR(obj)) {
491 gt_err(gt, "Failed to allocate scratch page\n");
492 return PTR_ERR(obj);
493 }
494
495 vma = i915_vma_instance(obj, >->ggtt->vm, NULL);
496 if (IS_ERR(vma)) {
497 ret = PTR_ERR(vma);
498 goto err_unref;
499 }
500
501 ret = i915_ggtt_pin(vma, NULL, 0, PIN_HIGH);
502 if (ret)
503 goto err_unref;
504
505 gt->scratch = i915_vma_make_unshrinkable(vma);
506
507 return 0;
508
509 err_unref:
510 i915_gem_object_put(obj);
511 return ret;
512 }
513
intel_gt_fini_scratch(struct intel_gt * gt)514 static void intel_gt_fini_scratch(struct intel_gt *gt)
515 {
516 i915_vma_unpin_and_release(>->scratch, 0);
517 }
518
kernel_vm(struct intel_gt * gt)519 static struct i915_address_space *kernel_vm(struct intel_gt *gt)
520 {
521 if (INTEL_PPGTT(gt->i915) > INTEL_PPGTT_ALIASING)
522 return &i915_ppgtt_create(gt, I915_BO_ALLOC_PM_EARLY)->vm;
523 else
524 return i915_vm_get(>->ggtt->vm);
525 }
526
__engines_record_defaults(struct intel_gt * gt)527 static int __engines_record_defaults(struct intel_gt *gt)
528 {
529 struct i915_request *requests[I915_NUM_ENGINES] = {};
530 struct intel_engine_cs *engine;
531 enum intel_engine_id id;
532 int err = 0;
533
534 /*
535 * As we reset the gpu during very early sanitisation, the current
536 * register state on the GPU should reflect its defaults values.
537 * We load a context onto the hw (with restore-inhibit), then switch
538 * over to a second context to save that default register state. We
539 * can then prime every new context with that state so they all start
540 * from the same default HW values.
541 */
542
543 for_each_engine(engine, gt, id) {
544 struct intel_renderstate so;
545 struct intel_context *ce;
546 struct i915_request *rq;
547
548 /* We must be able to switch to something! */
549 GEM_BUG_ON(!engine->kernel_context);
550
551 ce = intel_context_create(engine);
552 if (IS_ERR(ce)) {
553 err = PTR_ERR(ce);
554 goto out;
555 }
556
557 err = intel_renderstate_init(&so, ce);
558 if (err)
559 goto err;
560
561 rq = i915_request_create(ce);
562 if (IS_ERR(rq)) {
563 err = PTR_ERR(rq);
564 goto err_fini;
565 }
566
567 err = intel_engine_emit_ctx_wa(rq);
568 if (err)
569 goto err_rq;
570
571 err = intel_renderstate_emit(&so, rq);
572 if (err)
573 goto err_rq;
574
575 err_rq:
576 requests[id] = i915_request_get(rq);
577 i915_request_add(rq);
578 err_fini:
579 intel_renderstate_fini(&so, ce);
580 err:
581 if (err) {
582 intel_context_put(ce);
583 goto out;
584 }
585 }
586
587 /* Flush the default context image to memory, and enable powersaving. */
588 if (intel_gt_wait_for_idle(gt, I915_GEM_IDLE_TIMEOUT) == -ETIME) {
589 err = -EIO;
590 goto out;
591 }
592
593 for (id = 0; id < ARRAY_SIZE(requests); id++) {
594 struct i915_request *rq;
595 struct uvm_object *state;
596
597 rq = requests[id];
598 if (!rq)
599 continue;
600
601 if (rq->fence.error) {
602 err = -EIO;
603 goto out;
604 }
605
606 GEM_BUG_ON(!test_bit(CONTEXT_ALLOC_BIT, &rq->context->flags));
607 if (!rq->context->state)
608 continue;
609
610 /* Keep a copy of the state's backing pages; free the obj */
611 #ifdef __linux__
612 state = shmem_create_from_object(rq->context->state->obj);
613 #else
614 state = uao_create_from_object(rq->context->state->obj);
615 #endif
616 if (IS_ERR(state)) {
617 err = PTR_ERR(state);
618 goto out;
619 }
620 rq->engine->default_state = state;
621 }
622
623 out:
624 /*
625 * If we have to abandon now, we expect the engines to be idle
626 * and ready to be torn-down. The quickest way we can accomplish
627 * this is by declaring ourselves wedged.
628 */
629 if (err)
630 intel_gt_set_wedged(gt);
631
632 for (id = 0; id < ARRAY_SIZE(requests); id++) {
633 struct intel_context *ce;
634 struct i915_request *rq;
635
636 rq = requests[id];
637 if (!rq)
638 continue;
639
640 ce = rq->context;
641 i915_request_put(rq);
642 intel_context_put(ce);
643 }
644 return err;
645 }
646
__engines_verify_workarounds(struct intel_gt * gt)647 static int __engines_verify_workarounds(struct intel_gt *gt)
648 {
649 struct intel_engine_cs *engine;
650 enum intel_engine_id id;
651 int err = 0;
652
653 if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
654 return 0;
655
656 for_each_engine(engine, gt, id) {
657 if (intel_engine_verify_workarounds(engine, "load"))
658 err = -EIO;
659 }
660
661 /* Flush and restore the kernel context for safety */
662 if (intel_gt_wait_for_idle(gt, I915_GEM_IDLE_TIMEOUT) == -ETIME)
663 err = -EIO;
664
665 return err;
666 }
667
__intel_gt_disable(struct intel_gt * gt)668 static void __intel_gt_disable(struct intel_gt *gt)
669 {
670 intel_gt_set_wedged_on_fini(gt);
671
672 intel_gt_suspend_prepare(gt);
673 intel_gt_suspend_late(gt);
674
675 GEM_BUG_ON(intel_gt_pm_is_awake(gt));
676 }
677
intel_gt_wait_for_idle(struct intel_gt * gt,long timeout)678 int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout)
679 {
680 long remaining_timeout;
681
682 /* If the device is asleep, we have no requests outstanding */
683 if (!intel_gt_pm_is_awake(gt))
684 return 0;
685
686 while ((timeout = intel_gt_retire_requests_timeout(gt, timeout,
687 &remaining_timeout)) > 0) {
688 cond_resched();
689 if (signal_pending(current))
690 return -EINTR;
691 }
692
693 if (timeout)
694 return timeout;
695
696 if (remaining_timeout < 0)
697 remaining_timeout = 0;
698
699 return intel_uc_wait_for_idle(>->uc, remaining_timeout);
700 }
701
intel_gt_init(struct intel_gt * gt)702 int intel_gt_init(struct intel_gt *gt)
703 {
704 int err;
705
706 err = i915_inject_probe_error(gt->i915, -ENODEV);
707 if (err)
708 return err;
709
710 intel_gt_init_workarounds(gt);
711
712 /*
713 * This is just a security blanket to placate dragons.
714 * On some systems, we very sporadically observe that the first TLBs
715 * used by the CS may be stale, despite us poking the TLB reset. If
716 * we hold the forcewake during initialisation these problems
717 * just magically go away.
718 */
719 intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
720
721 err = intel_gt_init_scratch(gt,
722 GRAPHICS_VER(gt->i915) == 2 ? SZ_256K : SZ_4K);
723 if (err)
724 goto out_fw;
725
726 intel_gt_pm_init(gt);
727
728 gt->vm = kernel_vm(gt);
729 if (!gt->vm) {
730 err = -ENOMEM;
731 goto err_pm;
732 }
733
734 intel_set_mocs_index(gt);
735
736 err = intel_engines_init(gt);
737 if (err)
738 goto err_engines;
739
740 err = intel_uc_init(>->uc);
741 if (err)
742 goto err_engines;
743
744 err = intel_gt_resume(gt);
745 if (err)
746 goto err_uc_init;
747
748 err = intel_gt_init_hwconfig(gt);
749 if (err)
750 gt_err(gt, "Failed to retrieve hwconfig table: %pe\n", ERR_PTR(err));
751
752 err = __engines_record_defaults(gt);
753 if (err)
754 goto err_gt;
755
756 err = __engines_verify_workarounds(gt);
757 if (err)
758 goto err_gt;
759
760 err = i915_inject_probe_error(gt->i915, -EIO);
761 if (err)
762 goto err_gt;
763
764 intel_uc_init_late(>->uc);
765
766 intel_migrate_init(>->migrate, gt);
767
768 goto out_fw;
769 err_gt:
770 __intel_gt_disable(gt);
771 intel_uc_fini_hw(>->uc);
772 err_uc_init:
773 intel_uc_fini(>->uc);
774 err_engines:
775 intel_engines_release(gt);
776 i915_vm_put(fetch_and_zero(>->vm));
777 err_pm:
778 intel_gt_pm_fini(gt);
779 intel_gt_fini_scratch(gt);
780 out_fw:
781 if (err)
782 intel_gt_set_wedged_on_init(gt);
783 intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
784 return err;
785 }
786
intel_gt_driver_remove(struct intel_gt * gt)787 void intel_gt_driver_remove(struct intel_gt *gt)
788 {
789 __intel_gt_disable(gt);
790
791 intel_migrate_fini(>->migrate);
792 intel_uc_driver_remove(>->uc);
793
794 intel_engines_release(gt);
795
796 intel_gt_flush_buffer_pool(gt);
797 }
798
intel_gt_driver_unregister(struct intel_gt * gt)799 void intel_gt_driver_unregister(struct intel_gt *gt)
800 {
801 intel_wakeref_t wakeref;
802
803 intel_gt_sysfs_unregister(gt);
804 intel_rps_driver_unregister(>->rps);
805 intel_gsc_fini(>->gsc);
806
807 /*
808 * If we unload the driver and wedge before the GSC worker is complete,
809 * the worker will hit an error on its submission to the GSC engine and
810 * then exit. This is hard to hit for a user, but it is reproducible
811 * with skipping selftests. The error is handled gracefully by the
812 * worker, so there are no functional issues, but we still end up with
813 * an error message in dmesg, which is something we want to avoid as
814 * this is a supported scenario. We could modify the worker to better
815 * handle a wedging occurring during its execution, but that gets
816 * complicated for a couple of reasons:
817 * - We do want the error on runtime wedging, because there are
818 * implications for subsystems outside of GT (i.e., PXP, HDCP), it's
819 * only the error on driver unload that we want to silence.
820 * - The worker is responsible for multiple submissions (GSC FW load,
821 * HuC auth, SW proxy), so all of those will have to be adapted to
822 * handle the wedged_on_fini scenario.
823 * Therefore, it's much simpler to just wait for the worker to be done
824 * before wedging on driver removal, also considering that the worker
825 * will likely already be idle in the great majority of non-selftest
826 * scenarios.
827 */
828 intel_gsc_uc_flush_work(>->uc.gsc);
829
830 /*
831 * Upon unregistering the device to prevent any new users, cancel
832 * all in-flight requests so that we can quickly unbind the active
833 * resources.
834 */
835 intel_gt_set_wedged_on_fini(gt);
836
837 /* Scrub all HW state upon release */
838 with_intel_runtime_pm(gt->uncore->rpm, wakeref)
839 intel_gt_reset_all_engines(gt);
840 }
841
intel_gt_driver_release(struct intel_gt * gt)842 void intel_gt_driver_release(struct intel_gt *gt)
843 {
844 struct i915_address_space *vm;
845
846 vm = fetch_and_zero(>->vm);
847 if (vm) /* FIXME being called twice on error paths :( */
848 i915_vm_put(vm);
849
850 intel_wa_list_free(>->wa_list);
851 intel_gt_pm_fini(gt);
852 intel_gt_fini_scratch(gt);
853 intel_gt_fini_buffer_pool(gt);
854 intel_gt_fini_hwconfig(gt);
855 }
856
intel_gt_driver_late_release_all(struct drm_i915_private * i915)857 void intel_gt_driver_late_release_all(struct drm_i915_private *i915)
858 {
859 struct intel_gt *gt;
860 unsigned int id;
861
862 /* We need to wait for inflight RCU frees to release their grip */
863 rcu_barrier();
864
865 for_each_gt(gt, i915, id) {
866 intel_uc_driver_late_release(>->uc);
867 intel_gt_fini_requests(gt);
868 intel_gt_fini_reset(gt);
869 intel_gt_fini_timelines(gt);
870 intel_gt_fini_tlb(gt);
871 intel_engines_free(gt);
872 }
873 }
874
intel_gt_tile_setup(struct intel_gt * gt,phys_addr_t phys_addr)875 static int intel_gt_tile_setup(struct intel_gt *gt, phys_addr_t phys_addr)
876 {
877 int ret;
878
879 if (!gt_is_root(gt)) {
880 struct intel_uncore *uncore;
881 spinlock_t *irq_lock;
882
883 uncore = drmm_kzalloc(>->i915->drm, sizeof(*uncore), GFP_KERNEL);
884 if (!uncore)
885 return -ENOMEM;
886
887 irq_lock = drmm_kzalloc(>->i915->drm, sizeof(*irq_lock), GFP_KERNEL);
888 if (!irq_lock)
889 return -ENOMEM;
890
891 gt->uncore = uncore;
892 gt->irq_lock = irq_lock;
893
894 intel_gt_common_init_early(gt);
895 }
896
897 intel_uncore_init_early(gt->uncore, gt);
898
899 ret = intel_uncore_setup_mmio(gt->uncore, phys_addr);
900 if (ret)
901 return ret;
902
903 gt->phys_addr = phys_addr;
904
905 return 0;
906 }
907
908 #ifdef __linux__
909
intel_gt_probe_all(struct drm_i915_private * i915)910 int intel_gt_probe_all(struct drm_i915_private *i915)
911 {
912 struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
913 struct intel_gt *gt = to_gt(i915);
914 const struct intel_gt_definition *gtdef;
915 phys_addr_t phys_addr;
916 unsigned int mmio_bar;
917 unsigned int i;
918 int ret;
919
920 mmio_bar = intel_mmio_bar(GRAPHICS_VER(i915));
921 phys_addr = pci_resource_start(pdev, mmio_bar);
922
923 /*
924 * We always have at least one primary GT on any device
925 * and it has been already initialized early during probe
926 * in i915_driver_probe()
927 */
928 gt->i915 = i915;
929 gt->name = "Primary GT";
930 gt->info.engine_mask = INTEL_INFO(i915)->platform_engine_mask;
931
932 gt_dbg(gt, "Setting up %s\n", gt->name);
933 ret = intel_gt_tile_setup(gt, phys_addr);
934 if (ret)
935 return ret;
936
937 if (!HAS_EXTRA_GT_LIST(i915))
938 return 0;
939
940 for (i = 1, gtdef = &INTEL_INFO(i915)->extra_gt_list[i - 1];
941 gtdef->name != NULL;
942 i++, gtdef = &INTEL_INFO(i915)->extra_gt_list[i - 1]) {
943 gt = drmm_kzalloc(&i915->drm, sizeof(*gt), GFP_KERNEL);
944 if (!gt) {
945 ret = -ENOMEM;
946 goto err;
947 }
948
949 gt->i915 = i915;
950 gt->name = gtdef->name;
951 gt->type = gtdef->type;
952 gt->info.engine_mask = gtdef->engine_mask;
953 gt->info.id = i;
954
955 gt_dbg(gt, "Setting up %s\n", gt->name);
956 if (GEM_WARN_ON(range_overflows_t(resource_size_t,
957 gtdef->mapping_base,
958 SZ_16M,
959 pci_resource_len(pdev, mmio_bar)))) {
960 ret = -ENODEV;
961 goto err;
962 }
963
964 switch (gtdef->type) {
965 case GT_TILE:
966 ret = intel_gt_tile_setup(gt, phys_addr + gtdef->mapping_base);
967 break;
968
969 case GT_MEDIA:
970 ret = intel_sa_mediagt_setup(gt, phys_addr + gtdef->mapping_base,
971 gtdef->gsi_offset);
972 break;
973
974 case GT_PRIMARY:
975 /* Primary GT should not appear in extra GT list */
976 default:
977 MISSING_CASE(gtdef->type);
978 ret = -ENODEV;
979 }
980
981 if (ret)
982 goto err;
983
984 i915->gt[i] = gt;
985 }
986
987 return 0;
988
989 err:
990 i915_probe_error(i915, "Failed to initialize %s! (%d)\n", gtdef->name, ret);
991 return ret;
992 }
993
994 #else
995
intel_gt_probe_all(struct drm_i915_private * i915)996 int intel_gt_probe_all(struct drm_i915_private *i915)
997 {
998 struct pci_dev *pdev = i915->drm.pdev;
999 struct intel_gt *gt = to_gt(i915);
1000 const struct intel_gt_definition *gtdef;
1001 phys_addr_t phys_addr;
1002 bus_size_t len;
1003 pcireg_t type;
1004 int flags;
1005 unsigned int mmio_bar;
1006 unsigned int i;
1007 int ret;
1008
1009 mmio_bar = intel_mmio_bar(GRAPHICS_VER(i915));
1010 type = pci_mapreg_type(i915->pc, i915->tag, 0x10 + (mmio_bar * 4));
1011 ret = -pci_mapreg_info(i915->pc, i915->tag, 0x10 + (mmio_bar * 4), type,
1012 &phys_addr, &len, NULL);
1013 if (ret)
1014 return ret;
1015
1016 /*
1017 * We always have at least one primary GT on any device
1018 * and it has been already initialized early during probe
1019 * in i915_driver_probe()
1020 */
1021 gt->i915 = i915;
1022 gt->name = "Primary GT";
1023 gt->info.engine_mask = INTEL_INFO(i915)->platform_engine_mask;
1024
1025 gt_dbg(gt, "Setting up %s\n", gt->name);
1026 ret = intel_gt_tile_setup(gt, phys_addr);
1027 if (ret)
1028 return ret;
1029
1030 i915->gt[0] = gt;
1031
1032 if (!HAS_EXTRA_GT_LIST(i915))
1033 return 0;
1034
1035 for (i = 1, gtdef = &INTEL_INFO(i915)->extra_gt_list[i - 1];
1036 gtdef->name != NULL;
1037 i++, gtdef = &INTEL_INFO(i915)->extra_gt_list[i - 1]) {
1038 gt = drmm_kzalloc(&i915->drm, sizeof(*gt), GFP_KERNEL);
1039 if (!gt) {
1040 ret = -ENOMEM;
1041 goto err;
1042 }
1043
1044 gt->i915 = i915;
1045 gt->name = gtdef->name;
1046 gt->type = gtdef->type;
1047 gt->info.engine_mask = gtdef->engine_mask;
1048 gt->info.id = i;
1049
1050 gt_dbg(gt, "Setting up %s\n", gt->name);
1051 if (GEM_WARN_ON(range_overflows_t(resource_size_t,
1052 gtdef->mapping_base,
1053 SZ_16M,
1054 len))) {
1055 ret = -ENODEV;
1056 goto err;
1057 }
1058
1059 switch (gtdef->type) {
1060 case GT_TILE:
1061 ret = intel_gt_tile_setup(gt, phys_addr + gtdef->mapping_base);
1062 break;
1063
1064 case GT_MEDIA:
1065 ret = intel_sa_mediagt_setup(gt, phys_addr + gtdef->mapping_base,
1066 gtdef->gsi_offset);
1067 break;
1068
1069 case GT_PRIMARY:
1070 /* Primary GT should not appear in extra GT list */
1071 default:
1072 MISSING_CASE(gtdef->type);
1073 ret = -ENODEV;
1074 }
1075
1076 if (ret)
1077 goto err;
1078
1079 i915->gt[i] = gt;
1080 }
1081
1082 return 0;
1083
1084 err:
1085 i915_probe_error(i915, "Failed to initialize %s! (%d)\n", gtdef->name, ret);
1086 return ret;
1087 }
1088
1089 #endif
1090
intel_gt_tiles_init(struct drm_i915_private * i915)1091 int intel_gt_tiles_init(struct drm_i915_private *i915)
1092 {
1093 struct intel_gt *gt;
1094 unsigned int id;
1095 int ret;
1096
1097 for_each_gt(gt, i915, id) {
1098 ret = intel_gt_probe_lmem(gt);
1099 if (ret)
1100 return ret;
1101 }
1102
1103 return 0;
1104 }
1105
intel_gt_info_print(const struct intel_gt_info * info,struct drm_printer * p)1106 void intel_gt_info_print(const struct intel_gt_info *info,
1107 struct drm_printer *p)
1108 {
1109 drm_printf(p, "available engines: %x\n", info->engine_mask);
1110
1111 intel_sseu_dump(&info->sseu, p);
1112 }
1113
intel_gt_coherent_map_type(struct intel_gt * gt,struct drm_i915_gem_object * obj,bool always_coherent)1114 enum i915_map_type intel_gt_coherent_map_type(struct intel_gt *gt,
1115 struct drm_i915_gem_object *obj,
1116 bool always_coherent)
1117 {
1118 /*
1119 * Wa_22016122933: always return I915_MAP_WC for Media
1120 * version 13.0 when the object is on the Media GT
1121 */
1122 if (i915_gem_object_is_lmem(obj) || intel_gt_needs_wa_22016122933(gt))
1123 return I915_MAP_WC;
1124 if (HAS_LLC(gt->i915) || always_coherent)
1125 return I915_MAP_WB;
1126 else
1127 return I915_MAP_WC;
1128 }
1129
intel_gt_needs_wa_16018031267(struct intel_gt * gt)1130 bool intel_gt_needs_wa_16018031267(struct intel_gt *gt)
1131 {
1132 /* Wa_16018031267, Wa_16018063123 */
1133 return IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 55), IP_VER(12, 71));
1134 }
1135
intel_gt_needs_wa_22016122933(struct intel_gt * gt)1136 bool intel_gt_needs_wa_22016122933(struct intel_gt *gt)
1137 {
1138 return MEDIA_VER_FULL(gt->i915) == IP_VER(13, 0) && gt->type == GT_MEDIA;
1139 }
1140
__intel_gt_bind_context_set_ready(struct intel_gt * gt,bool ready)1141 static void __intel_gt_bind_context_set_ready(struct intel_gt *gt, bool ready)
1142 {
1143 struct intel_engine_cs *engine = gt->engine[BCS0];
1144
1145 if (engine && engine->bind_context)
1146 engine->bind_context_ready = ready;
1147 }
1148
1149 /**
1150 * intel_gt_bind_context_set_ready - Set the context binding as ready
1151 *
1152 * @gt: GT structure
1153 *
1154 * This function marks the binder context as ready.
1155 */
intel_gt_bind_context_set_ready(struct intel_gt * gt)1156 void intel_gt_bind_context_set_ready(struct intel_gt *gt)
1157 {
1158 __intel_gt_bind_context_set_ready(gt, true);
1159 }
1160
1161 /**
1162 * intel_gt_bind_context_set_unready - Set the context binding as ready
1163 * @gt: GT structure
1164 *
1165 * This function marks the binder context as not ready.
1166 */
1167
intel_gt_bind_context_set_unready(struct intel_gt * gt)1168 void intel_gt_bind_context_set_unready(struct intel_gt *gt)
1169 {
1170 __intel_gt_bind_context_set_ready(gt, false);
1171 }
1172
1173 /**
1174 * intel_gt_is_bind_context_ready - Check if context binding is ready
1175 *
1176 * @gt: GT structure
1177 *
1178 * This function returns binder context's ready status.
1179 */
intel_gt_is_bind_context_ready(struct intel_gt * gt)1180 bool intel_gt_is_bind_context_ready(struct intel_gt *gt)
1181 {
1182 struct intel_engine_cs *engine = gt->engine[BCS0];
1183
1184 if (engine)
1185 return engine->bind_context_ready;
1186
1187 return false;
1188 }
1189