1 /*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2008,2010 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 * Chris Wilson <chris@chris-wilson.co.uk>
28 */
29 #include <linux/i2c.h>
30 #include <linux/i2c-algo-bit.h>
31 #include <linux/export.h>
32 #include <drm/drmP.h>
33 #include "intel_drv.h"
34 #include <drm/i915_drm.h>
35 #include "i915_drv.h"
36
37 struct gmbus_pin {
38 const char *name;
39 i915_reg_t reg;
40 };
41
42 /* Map gmbus pin pairs to names and registers. */
43 static const struct gmbus_pin gmbus_pins[] = {
44 [GMBUS_PIN_SSC] = { "ssc", GPIOB },
45 [GMBUS_PIN_VGADDC] = { "vga", GPIOA },
46 [GMBUS_PIN_PANEL] = { "panel", GPIOC },
47 [GMBUS_PIN_DPC] = { "dpc", GPIOD },
48 [GMBUS_PIN_DPB] = { "dpb", GPIOE },
49 [GMBUS_PIN_DPD] = { "dpd", GPIOF },
50 };
51
52 static const struct gmbus_pin gmbus_pins_bdw[] = {
53 [GMBUS_PIN_VGADDC] = { "vga", GPIOA },
54 [GMBUS_PIN_DPC] = { "dpc", GPIOD },
55 [GMBUS_PIN_DPB] = { "dpb", GPIOE },
56 [GMBUS_PIN_DPD] = { "dpd", GPIOF },
57 };
58
59 static const struct gmbus_pin gmbus_pins_skl[] = {
60 [GMBUS_PIN_DPC] = { "dpc", GPIOD },
61 [GMBUS_PIN_DPB] = { "dpb", GPIOE },
62 [GMBUS_PIN_DPD] = { "dpd", GPIOF },
63 };
64
65 static const struct gmbus_pin gmbus_pins_bxt[] = {
66 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
67 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
68 [GMBUS_PIN_3_BXT] = { "misc", GPIOD },
69 };
70
71 static const struct gmbus_pin gmbus_pins_cnp[] = {
72 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
73 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
74 [GMBUS_PIN_3_BXT] = { "misc", GPIOD },
75 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
76 };
77
78 /* pin is expected to be valid */
get_gmbus_pin(struct drm_i915_private * dev_priv,unsigned int pin)79 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
80 unsigned int pin)
81 {
82 if (HAS_PCH_CNP(dev_priv))
83 return &gmbus_pins_cnp[pin];
84 else if (IS_GEN9_LP(dev_priv))
85 return &gmbus_pins_bxt[pin];
86 else if (IS_GEN9_BC(dev_priv))
87 return &gmbus_pins_skl[pin];
88 else if (IS_BROADWELL(dev_priv))
89 return &gmbus_pins_bdw[pin];
90 else
91 return &gmbus_pins[pin];
92 }
93
intel_gmbus_is_valid_pin(struct drm_i915_private * dev_priv,unsigned int pin)94 bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
95 unsigned int pin)
96 {
97 unsigned int size;
98
99 if (HAS_PCH_CNP(dev_priv))
100 size = ARRAY_SIZE(gmbus_pins_cnp);
101 else if (IS_GEN9_LP(dev_priv))
102 size = ARRAY_SIZE(gmbus_pins_bxt);
103 else if (IS_GEN9_BC(dev_priv))
104 size = ARRAY_SIZE(gmbus_pins_skl);
105 else if (IS_BROADWELL(dev_priv))
106 size = ARRAY_SIZE(gmbus_pins_bdw);
107 else
108 size = ARRAY_SIZE(gmbus_pins);
109
110 return pin < size &&
111 i915_mmio_reg_valid(get_gmbus_pin(dev_priv, pin)->reg);
112 }
113
114 /* Intel GPIO access functions */
115
116 #define I2C_RISEFALL_TIME 10
117
118 static inline struct intel_gmbus *
to_intel_gmbus(struct i2c_adapter * i2c)119 to_intel_gmbus(struct i2c_adapter *i2c)
120 {
121 return container_of(i2c, struct intel_gmbus, adapter);
122 }
123
124 void
intel_i2c_reset(struct drm_i915_private * dev_priv)125 intel_i2c_reset(struct drm_i915_private *dev_priv)
126 {
127 I915_WRITE(GMBUS0, 0);
128 I915_WRITE(GMBUS4, 0);
129 }
130
intel_i2c_quirk_set(struct drm_i915_private * dev_priv,bool enable)131 static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
132 {
133 u32 val;
134
135 /* When using bit bashing for I2C, this bit needs to be set to 1 */
136 if (!IS_PINEVIEW(dev_priv))
137 return;
138
139 val = I915_READ(DSPCLK_GATE_D);
140 if (enable)
141 val |= DPCUNIT_CLOCK_GATE_DISABLE;
142 else
143 val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
144 I915_WRITE(DSPCLK_GATE_D, val);
145 }
146
get_reserved(struct intel_gmbus * bus)147 static u32 get_reserved(struct intel_gmbus *bus)
148 {
149 struct drm_i915_private *dev_priv = bus->dev_priv;
150 u32 reserved = 0;
151
152 /* On most chips, these bits must be preserved in software. */
153 if (!IS_I830(dev_priv) && !IS_I845G(dev_priv))
154 reserved = I915_READ_NOTRACE(bus->gpio_reg) &
155 (GPIO_DATA_PULLUP_DISABLE |
156 GPIO_CLOCK_PULLUP_DISABLE);
157
158 return reserved;
159 }
160
get_clock(void * data)161 static int get_clock(void *data)
162 {
163 struct intel_gmbus *bus = data;
164 struct drm_i915_private *dev_priv = bus->dev_priv;
165 u32 reserved = get_reserved(bus);
166 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
167 I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
168 return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
169 }
170
get_data(void * data)171 static int get_data(void *data)
172 {
173 struct intel_gmbus *bus = data;
174 struct drm_i915_private *dev_priv = bus->dev_priv;
175 u32 reserved = get_reserved(bus);
176 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
177 I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
178 return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
179 }
180
set_clock(void * data,int state_high)181 static void set_clock(void *data, int state_high)
182 {
183 struct intel_gmbus *bus = data;
184 struct drm_i915_private *dev_priv = bus->dev_priv;
185 u32 reserved = get_reserved(bus);
186 u32 clock_bits;
187
188 if (state_high)
189 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
190 else
191 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
192 GPIO_CLOCK_VAL_MASK;
193
194 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits);
195 POSTING_READ(bus->gpio_reg);
196 }
197
set_data(void * data,int state_high)198 static void set_data(void *data, int state_high)
199 {
200 struct intel_gmbus *bus = data;
201 struct drm_i915_private *dev_priv = bus->dev_priv;
202 u32 reserved = get_reserved(bus);
203 u32 data_bits;
204
205 if (state_high)
206 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
207 else
208 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
209 GPIO_DATA_VAL_MASK;
210
211 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits);
212 POSTING_READ(bus->gpio_reg);
213 }
214
215 static int
intel_gpio_pre_xfer(struct i2c_adapter * adapter)216 intel_gpio_pre_xfer(struct i2c_adapter *adapter)
217 {
218 struct intel_gmbus *bus = container_of(adapter,
219 struct intel_gmbus,
220 adapter);
221 struct drm_i915_private *dev_priv = bus->dev_priv;
222
223 intel_i2c_reset(dev_priv);
224 intel_i2c_quirk_set(dev_priv, true);
225 set_data(bus, 1);
226 set_clock(bus, 1);
227 udelay(I2C_RISEFALL_TIME);
228 return 0;
229 }
230
231 static void
intel_gpio_post_xfer(struct i2c_adapter * adapter)232 intel_gpio_post_xfer(struct i2c_adapter *adapter)
233 {
234 struct intel_gmbus *bus = container_of(adapter,
235 struct intel_gmbus,
236 adapter);
237 struct drm_i915_private *dev_priv = bus->dev_priv;
238
239 set_data(bus, 1);
240 set_clock(bus, 1);
241 intel_i2c_quirk_set(dev_priv, false);
242 }
243
244 static void
intel_gpio_setup(struct intel_gmbus * bus,unsigned int pin)245 intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin)
246 {
247 struct drm_i915_private *dev_priv = bus->dev_priv;
248 struct i2c_algo_bit_data *algo;
249
250 algo = &bus->bit_algo;
251
252 bus->gpio_reg = _MMIO(dev_priv->gpio_mmio_base +
253 i915_mmio_reg_offset(get_gmbus_pin(dev_priv, pin)->reg));
254 bus->adapter.algo_data = algo;
255 algo->setsda = set_data;
256 algo->setscl = set_clock;
257 algo->getsda = get_data;
258 algo->getscl = get_clock;
259 algo->pre_xfer = intel_gpio_pre_xfer;
260 algo->post_xfer = intel_gpio_post_xfer;
261 algo->udelay = I2C_RISEFALL_TIME;
262 algo->timeout = usecs_to_jiffies(2200);
263 algo->data = bus;
264 }
265
gmbus_wait(struct drm_i915_private * dev_priv,u32 status,u32 irq_en)266 static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en)
267 {
268 DEFINE_WAIT(wait);
269 u32 gmbus2;
270 int ret;
271
272 /* Important: The hw handles only the first bit, so set only one! Since
273 * we also need to check for NAKs besides the hw ready/idle signal, we
274 * need to wake up periodically and check that ourselves.
275 */
276 if (!HAS_GMBUS_IRQ(dev_priv))
277 irq_en = 0;
278
279 add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
280 I915_WRITE_FW(GMBUS4, irq_en);
281
282 status |= GMBUS_SATOER;
283 ret = wait_for_us((gmbus2 = I915_READ_FW(GMBUS2)) & status, 2);
284 if (ret)
285 ret = wait_for((gmbus2 = I915_READ_FW(GMBUS2)) & status, 50);
286
287 I915_WRITE_FW(GMBUS4, 0);
288 remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
289
290 if (gmbus2 & GMBUS_SATOER)
291 return -ENXIO;
292
293 return ret;
294 }
295
296 static int
gmbus_wait_idle(struct drm_i915_private * dev_priv)297 gmbus_wait_idle(struct drm_i915_private *dev_priv)
298 {
299 DEFINE_WAIT(wait);
300 u32 irq_enable;
301 int ret;
302
303 /* Important: The hw handles only the first bit, so set only one! */
304 irq_enable = 0;
305 if (HAS_GMBUS_IRQ(dev_priv))
306 irq_enable = GMBUS_IDLE_EN;
307
308 add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
309 I915_WRITE_FW(GMBUS4, irq_enable);
310
311 ret = intel_wait_for_register_fw(dev_priv,
312 GMBUS2, GMBUS_ACTIVE, 0,
313 10);
314
315 I915_WRITE_FW(GMBUS4, 0);
316 remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
317
318 return ret;
319 }
320
321 static int
gmbus_xfer_read_chunk(struct drm_i915_private * dev_priv,unsigned short addr,u8 * buf,unsigned int len,u32 gmbus1_index)322 gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
323 unsigned short addr, u8 *buf, unsigned int len,
324 u32 gmbus1_index)
325 {
326 I915_WRITE_FW(GMBUS1,
327 gmbus1_index |
328 GMBUS_CYCLE_WAIT |
329 (len << GMBUS_BYTE_COUNT_SHIFT) |
330 (addr << GMBUS_SLAVE_ADDR_SHIFT) |
331 GMBUS_SLAVE_READ | GMBUS_SW_RDY);
332 while (len) {
333 int ret;
334 u32 val, loop = 0;
335
336 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
337 if (ret)
338 return ret;
339
340 val = I915_READ_FW(GMBUS3);
341 do {
342 *buf++ = val & 0xff;
343 val >>= 8;
344 } while (--len && ++loop < 4);
345 }
346
347 return 0;
348 }
349
350 static int
gmbus_xfer_read(struct drm_i915_private * dev_priv,struct i2c_msg * msg,u32 gmbus1_index)351 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
352 u32 gmbus1_index)
353 {
354 u8 *buf = msg->buf;
355 unsigned int rx_size = msg->len;
356 unsigned int len;
357 int ret;
358
359 do {
360 len = min(rx_size, GMBUS_BYTE_COUNT_MAX);
361
362 ret = gmbus_xfer_read_chunk(dev_priv, msg->addr,
363 buf, len, gmbus1_index);
364 if (ret)
365 return ret;
366
367 rx_size -= len;
368 buf += len;
369 } while (rx_size != 0);
370
371 return 0;
372 }
373
374 static int
gmbus_xfer_write_chunk(struct drm_i915_private * dev_priv,unsigned short addr,u8 * buf,unsigned int len)375 gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
376 unsigned short addr, u8 *buf, unsigned int len)
377 {
378 unsigned int chunk_size = len;
379 u32 val, loop;
380
381 val = loop = 0;
382 while (len && loop < 4) {
383 val |= *buf++ << (8 * loop++);
384 len -= 1;
385 }
386
387 I915_WRITE_FW(GMBUS3, val);
388 I915_WRITE_FW(GMBUS1,
389 GMBUS_CYCLE_WAIT |
390 (chunk_size << GMBUS_BYTE_COUNT_SHIFT) |
391 (addr << GMBUS_SLAVE_ADDR_SHIFT) |
392 GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
393 while (len) {
394 int ret;
395
396 val = loop = 0;
397 do {
398 val |= *buf++ << (8 * loop);
399 } while (--len && ++loop < 4);
400
401 I915_WRITE_FW(GMBUS3, val);
402
403 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
404 if (ret)
405 return ret;
406 }
407
408 return 0;
409 }
410
411 static int
gmbus_xfer_write(struct drm_i915_private * dev_priv,struct i2c_msg * msg)412 gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg)
413 {
414 u8 *buf = msg->buf;
415 unsigned int tx_size = msg->len;
416 unsigned int len;
417 int ret;
418
419 do {
420 len = min(tx_size, GMBUS_BYTE_COUNT_MAX);
421
422 ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len);
423 if (ret)
424 return ret;
425
426 buf += len;
427 tx_size -= len;
428 } while (tx_size != 0);
429
430 return 0;
431 }
432
433 /*
434 * The gmbus controller can combine a 1 or 2 byte write with a read that
435 * immediately follows it by using an "INDEX" cycle.
436 */
437 static bool
gmbus_is_index_read(struct i2c_msg * msgs,int i,int num)438 gmbus_is_index_read(struct i2c_msg *msgs, int i, int num)
439 {
440 return (i + 1 < num &&
441 msgs[i].addr == msgs[i + 1].addr &&
442 !(msgs[i].flags & I2C_M_RD) &&
443 (msgs[i].len == 1 || msgs[i].len == 2) &&
444 (msgs[i + 1].flags & I2C_M_RD));
445 }
446
447 static int
gmbus_xfer_index_read(struct drm_i915_private * dev_priv,struct i2c_msg * msgs)448 gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
449 {
450 u32 gmbus1_index = 0;
451 u32 gmbus5 = 0;
452 int ret;
453
454 if (msgs[0].len == 2)
455 gmbus5 = GMBUS_2BYTE_INDEX_EN |
456 msgs[0].buf[1] | (msgs[0].buf[0] << 8);
457 if (msgs[0].len == 1)
458 gmbus1_index = GMBUS_CYCLE_INDEX |
459 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
460
461 /* GMBUS5 holds 16-bit index */
462 if (gmbus5)
463 I915_WRITE_FW(GMBUS5, gmbus5);
464
465 ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);
466
467 /* Clear GMBUS5 after each index transfer */
468 if (gmbus5)
469 I915_WRITE_FW(GMBUS5, 0);
470
471 return ret;
472 }
473
474 static int
do_gmbus_xfer(struct i2c_adapter * adapter,struct i2c_msg * msgs,int num)475 do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
476 {
477 struct intel_gmbus *bus = container_of(adapter,
478 struct intel_gmbus,
479 adapter);
480 struct drm_i915_private *dev_priv = bus->dev_priv;
481 int i = 0, inc, try = 0;
482 int ret = 0;
483
484 retry:
485 I915_WRITE_FW(GMBUS0, bus->reg0);
486
487 for (; i < num; i += inc) {
488 inc = 1;
489 if (gmbus_is_index_read(msgs, i, num)) {
490 ret = gmbus_xfer_index_read(dev_priv, &msgs[i]);
491 inc = 2; /* an index read is two msgs */
492 } else if (msgs[i].flags & I2C_M_RD) {
493 ret = gmbus_xfer_read(dev_priv, &msgs[i], 0);
494 } else {
495 ret = gmbus_xfer_write(dev_priv, &msgs[i]);
496 }
497
498 if (!ret)
499 ret = gmbus_wait(dev_priv,
500 GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN);
501 if (ret == -ETIMEDOUT)
502 goto timeout;
503 else if (ret)
504 goto clear_err;
505 }
506
507 /* Generate a STOP condition on the bus. Note that gmbus can't generata
508 * a STOP on the very first cycle. To simplify the code we
509 * unconditionally generate the STOP condition with an additional gmbus
510 * cycle. */
511 I915_WRITE_FW(GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
512
513 /* Mark the GMBUS interface as disabled after waiting for idle.
514 * We will re-enable it at the start of the next xfer,
515 * till then let it sleep.
516 */
517 if (gmbus_wait_idle(dev_priv)) {
518 DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n",
519 adapter->name);
520 ret = -ETIMEDOUT;
521 }
522 I915_WRITE_FW(GMBUS0, 0);
523 ret = ret ?: i;
524 goto out;
525
526 clear_err:
527 /*
528 * Wait for bus to IDLE before clearing NAK.
529 * If we clear the NAK while bus is still active, then it will stay
530 * active and the next transaction may fail.
531 *
532 * If no ACK is received during the address phase of a transaction, the
533 * adapter must report -ENXIO. It is not clear what to return if no ACK
534 * is received at other times. But we have to be careful to not return
535 * spurious -ENXIO because that will prevent i2c and drm edid functions
536 * from retrying. So return -ENXIO only when gmbus properly quiescents -
537 * timing out seems to happen when there _is_ a ddc chip present, but
538 * it's slow responding and only answers on the 2nd retry.
539 */
540 ret = -ENXIO;
541 if (gmbus_wait_idle(dev_priv)) {
542 DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n",
543 adapter->name);
544 ret = -ETIMEDOUT;
545 }
546
547 /* Toggle the Software Clear Interrupt bit. This has the effect
548 * of resetting the GMBUS controller and so clearing the
549 * BUS_ERROR raised by the slave's NAK.
550 */
551 I915_WRITE_FW(GMBUS1, GMBUS_SW_CLR_INT);
552 I915_WRITE_FW(GMBUS1, 0);
553 I915_WRITE_FW(GMBUS0, 0);
554
555 DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n",
556 adapter->name, msgs[i].addr,
557 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
558
559 /*
560 * Passive adapters sometimes NAK the first probe. Retry the first
561 * message once on -ENXIO for GMBUS transfers; the bit banging algorithm
562 * has retries internally. See also the retry loop in
563 * drm_do_probe_ddc_edid, which bails out on the first -ENXIO.
564 */
565 if (ret == -ENXIO && i == 0 && try++ == 0) {
566 DRM_DEBUG_KMS("GMBUS [%s] NAK on first message, retry\n",
567 adapter->name);
568 goto retry;
569 }
570
571 goto out;
572
573 timeout:
574 DRM_DEBUG_KMS("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
575 bus->adapter.name, bus->reg0 & 0xff);
576 I915_WRITE_FW(GMBUS0, 0);
577
578 /*
579 * Hardware may not support GMBUS over these pins? Try GPIO bitbanging
580 * instead. Use EAGAIN to have i2c core retry.
581 */
582 ret = -EAGAIN;
583
584 out:
585 return ret;
586 }
587
588 static int
gmbus_xfer(struct i2c_adapter * adapter,struct i2c_msg * msgs,int num)589 gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
590 {
591 struct intel_gmbus *bus = container_of(adapter, struct intel_gmbus,
592 adapter);
593 struct drm_i915_private *dev_priv = bus->dev_priv;
594 int ret;
595
596 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
597
598 if (bus->force_bit) {
599 ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
600 if (ret < 0)
601 bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY;
602 } else {
603 ret = do_gmbus_xfer(adapter, msgs, num);
604 if (ret == -EAGAIN)
605 bus->force_bit |= GMBUS_FORCE_BIT_RETRY;
606 }
607
608 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
609
610 return ret;
611 }
612
gmbus_func(struct i2c_adapter * adapter)613 static u32 gmbus_func(struct i2c_adapter *adapter)
614 {
615 return i2c_bit_algo.functionality(adapter) &
616 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
617 /* I2C_FUNC_10BIT_ADDR | */
618 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
619 I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
620 }
621
622 static const struct i2c_algorithm gmbus_algorithm = {
623 .master_xfer = gmbus_xfer,
624 .functionality = gmbus_func
625 };
626
gmbus_lock_bus(struct i2c_adapter * adapter,unsigned int flags)627 static void gmbus_lock_bus(struct i2c_adapter *adapter,
628 unsigned int flags)
629 {
630 struct intel_gmbus *bus = to_intel_gmbus(adapter);
631 struct drm_i915_private *dev_priv = bus->dev_priv;
632
633 mutex_lock(&dev_priv->gmbus_mutex);
634 }
635
gmbus_trylock_bus(struct i2c_adapter * adapter,unsigned int flags)636 static int gmbus_trylock_bus(struct i2c_adapter *adapter,
637 unsigned int flags)
638 {
639 struct intel_gmbus *bus = to_intel_gmbus(adapter);
640 struct drm_i915_private *dev_priv = bus->dev_priv;
641
642 return mutex_trylock(&dev_priv->gmbus_mutex);
643 }
644
gmbus_unlock_bus(struct i2c_adapter * adapter,unsigned int flags)645 static void gmbus_unlock_bus(struct i2c_adapter *adapter,
646 unsigned int flags)
647 {
648 struct intel_gmbus *bus = to_intel_gmbus(adapter);
649 struct drm_i915_private *dev_priv = bus->dev_priv;
650
651 mutex_unlock(&dev_priv->gmbus_mutex);
652 }
653
654 static const struct i2c_lock_operations gmbus_lock_ops = {
655 .lock_bus = gmbus_lock_bus,
656 .trylock_bus = gmbus_trylock_bus,
657 .unlock_bus = gmbus_unlock_bus,
658 };
659
660 /**
661 * intel_gmbus_setup - instantiate all Intel i2c GMBuses
662 * @dev_priv: i915 device private
663 */
intel_setup_gmbus(struct drm_i915_private * dev_priv)664 int intel_setup_gmbus(struct drm_i915_private *dev_priv)
665 {
666 struct pci_dev *pdev = dev_priv->drm.pdev;
667 struct intel_gmbus *bus;
668 unsigned int pin;
669 int ret;
670
671 if (HAS_PCH_NOP(dev_priv))
672 return 0;
673
674 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
675 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
676 else if (!HAS_GMCH_DISPLAY(dev_priv))
677 dev_priv->gpio_mmio_base =
678 i915_mmio_reg_offset(PCH_GPIOA) -
679 i915_mmio_reg_offset(GPIOA);
680
681 lockinit(&dev_priv->gmbus_mutex, "gmbus", 0, LK_CANRECURSE);
682 init_waitqueue_head(&dev_priv->gmbus_wait_queue);
683
684 for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
685 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
686 continue;
687
688 bus = &dev_priv->gmbus[pin];
689
690 #if 0
691 bus->adapter.owner = THIS_MODULE;
692 bus->adapter.class = I2C_CLASS_DDC;
693 #endif
694 ksnprintf(bus->adapter.name,
695 sizeof(bus->adapter.name),
696 "i915 gmbus %s",
697 get_gmbus_pin(dev_priv, pin)->name);
698
699 bus->adapter.dev.parent = &pdev->dev;
700 bus->dev_priv = dev_priv;
701
702 bus->adapter.algo = &gmbus_algorithm;
703 bus->adapter.lock_ops = &gmbus_lock_ops;
704
705 /*
706 * We wish to retry with bit banging
707 * after a timed out GMBUS attempt.
708 */
709 bus->adapter.retries = 1;
710
711 /* By default use a conservative clock rate */
712 bus->reg0 = pin | GMBUS_RATE_100KHZ;
713
714 /* gmbus seems to be broken on i830 */
715 if (IS_I830(dev_priv))
716 bus->force_bit = 1;
717
718 intel_gpio_setup(bus, pin);
719
720 ret = i2c_add_adapter(&bus->adapter);
721 if (ret)
722 goto err;
723 }
724
725 intel_i2c_reset(dev_priv);
726
727 return 0;
728
729 err:
730 while (pin--) {
731 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
732 continue;
733
734 bus = &dev_priv->gmbus[pin];
735 i2c_del_adapter(&bus->adapter);
736 }
737 return ret;
738 }
739
intel_gmbus_get_adapter(struct drm_i915_private * dev_priv,unsigned int pin)740 struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
741 unsigned int pin)
742 {
743 if (WARN_ON(!intel_gmbus_is_valid_pin(dev_priv, pin)))
744 return NULL;
745
746 return &dev_priv->gmbus[pin].adapter;
747 }
748
intel_gmbus_set_speed(struct i2c_adapter * adapter,int speed)749 void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
750 {
751 struct intel_gmbus *bus = to_intel_gmbus(adapter);
752
753 bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed;
754 }
755
intel_gmbus_force_bit(struct i2c_adapter * adapter,bool force_bit)756 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
757 {
758 struct intel_gmbus *bus = to_intel_gmbus(adapter);
759 struct drm_i915_private *dev_priv = bus->dev_priv;
760
761 mutex_lock(&dev_priv->gmbus_mutex);
762
763 bus->force_bit += force_bit ? 1 : -1;
764 DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n",
765 force_bit ? "en" : "dis", adapter->name,
766 bus->force_bit);
767
768 mutex_unlock(&dev_priv->gmbus_mutex);
769 }
770
intel_teardown_gmbus(struct drm_i915_private * dev_priv)771 void intel_teardown_gmbus(struct drm_i915_private *dev_priv)
772 {
773 struct intel_gmbus *bus;
774 unsigned int pin;
775
776 for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
777 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
778 continue;
779
780 bus = &dev_priv->gmbus[pin];
781 i2c_del_adapter(&bus->adapter);
782 }
783 }
784