1 /*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2008,2010 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 * Chris Wilson <chris@chris-wilson.co.uk>
28 *
29 * Copyright (c) 2011 The FreeBSD Foundation
30 * All rights reserved.
31 *
32 * This software was developed by Konstantin Belousov under sponsorship from
33 * the FreeBSD Foundation.
34 *
35 * Redistribution and use in source and binary forms, with or without
36 * modification, are permitted provided that the following conditions
37 * are met:
38 * 1. Redistributions of source code must retain the above copyright
39 * notice, this list of conditions and the following disclaimer.
40 * 2. Redistributions in binary form must reproduce the above copyright
41 * notice, this list of conditions and the following disclaimer in the
42 * documentation and/or other materials provided with the distribution.
43 *
44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
45 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
46 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
47 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
48 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
49 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
50 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
51 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
52 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
53 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
54 * SUCH DAMAGE.
55 */
56 #include <sys/cdefs.h>
57 __FBSDID("$FreeBSD$");
58
59 #include <dev/drm2/drmP.h>
60 #include <dev/drm2/drm.h>
61 #include <dev/drm2/i915/i915_drm.h>
62 #include <dev/drm2/i915/i915_drv.h>
63 #include <dev/drm2/i915/intel_drv.h>
64 #include <dev/iicbus/iic.h>
65 #include <dev/iicbus/iiconf.h>
66 #include <dev/iicbus/iicbus.h>
67 #include "iicbus_if.h"
68 #include "iicbb_if.h"
69
70 static void intel_teardown_gmbus_m(struct drm_device *dev, int m);
71
72 struct gmbus_port {
73 const char *name;
74 int reg;
75 };
76
77 static const struct gmbus_port gmbus_ports[] = {
78 { "ssc", GPIOB },
79 { "vga", GPIOA },
80 { "panel", GPIOC },
81 { "dpc", GPIOD },
82 { "dpb", GPIOE },
83 { "dpd", GPIOF },
84 };
85
86 /* Intel GPIO access functions */
87
88 #define I2C_RISEFALL_TIME 10
89
90 struct intel_iic_softc {
91 struct drm_device *drm_dev;
92 device_t iic_dev;
93 bool force_bit_dev;
94 char name[32];
95 uint32_t reg;
96 uint32_t reg0;
97 };
98
99 static void
intel_iic_quirk_set(struct drm_i915_private * dev_priv,bool enable)100 intel_iic_quirk_set(struct drm_i915_private *dev_priv, bool enable)
101 {
102 u32 val;
103
104 /* When using bit bashing for I2C, this bit needs to be set to 1 */
105 if (!IS_PINEVIEW(dev_priv->dev))
106 return;
107
108 val = I915_READ(DSPCLK_GATE_D);
109 if (enable)
110 val |= DPCUNIT_CLOCK_GATE_DISABLE;
111 else
112 val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
113 I915_WRITE(DSPCLK_GATE_D, val);
114 }
115
116 static u32
intel_iic_get_reserved(device_t idev)117 intel_iic_get_reserved(device_t idev)
118 {
119 struct intel_iic_softc *sc;
120 struct drm_device *dev;
121 struct drm_i915_private *dev_priv;
122 u32 reserved;
123
124 sc = device_get_softc(idev);
125 dev = sc->drm_dev;
126 dev_priv = dev->dev_private;
127
128 if (!IS_I830(dev) && !IS_845G(dev)) {
129 reserved = I915_READ_NOTRACE(sc->reg) &
130 (GPIO_DATA_PULLUP_DISABLE | GPIO_CLOCK_PULLUP_DISABLE);
131 } else {
132 reserved = 0;
133 }
134
135 return (reserved);
136 }
137
138 void
intel_iic_reset(struct drm_device * dev)139 intel_iic_reset(struct drm_device *dev)
140 {
141 struct drm_i915_private *dev_priv;
142
143 dev_priv = dev->dev_private;
144 I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0);
145 }
146
147 static int
intel_iicbus_reset(device_t idev,u_char speed,u_char addr,u_char * oldaddr)148 intel_iicbus_reset(device_t idev, u_char speed, u_char addr, u_char *oldaddr)
149 {
150 struct intel_iic_softc *sc;
151 struct drm_device *dev;
152
153 sc = device_get_softc(idev);
154 dev = sc->drm_dev;
155
156 intel_iic_reset(dev);
157 return (0);
158 }
159
160 static void
intel_iicbb_setsda(device_t idev,int val)161 intel_iicbb_setsda(device_t idev, int val)
162 {
163 struct intel_iic_softc *sc;
164 struct drm_i915_private *dev_priv;
165 u32 reserved;
166 u32 data_bits;
167
168 sc = device_get_softc(idev);
169 dev_priv = sc->drm_dev->dev_private;
170
171 reserved = intel_iic_get_reserved(idev);
172 if (val)
173 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
174 else
175 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
176 GPIO_DATA_VAL_MASK;
177
178 I915_WRITE_NOTRACE(sc->reg, reserved | data_bits);
179 POSTING_READ(sc->reg);
180 }
181
182 static void
intel_iicbb_setscl(device_t idev,int val)183 intel_iicbb_setscl(device_t idev, int val)
184 {
185 struct intel_iic_softc *sc;
186 struct drm_i915_private *dev_priv;
187 u32 clock_bits, reserved;
188
189 sc = device_get_softc(idev);
190 dev_priv = sc->drm_dev->dev_private;
191
192 reserved = intel_iic_get_reserved(idev);
193 if (val)
194 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
195 else
196 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
197 GPIO_CLOCK_VAL_MASK;
198
199 I915_WRITE_NOTRACE(sc->reg, reserved | clock_bits);
200 POSTING_READ(sc->reg);
201 }
202
203 static int
intel_iicbb_getsda(device_t idev)204 intel_iicbb_getsda(device_t idev)
205 {
206 struct intel_iic_softc *sc;
207 struct drm_i915_private *dev_priv;
208 u32 reserved;
209
210 sc = device_get_softc(idev);
211 dev_priv = sc->drm_dev->dev_private;
212
213 reserved = intel_iic_get_reserved(idev);
214
215 I915_WRITE_NOTRACE(sc->reg, reserved | GPIO_DATA_DIR_MASK);
216 I915_WRITE_NOTRACE(sc->reg, reserved);
217 return ((I915_READ_NOTRACE(sc->reg) & GPIO_DATA_VAL_IN) != 0);
218 }
219
220 static int
intel_iicbb_getscl(device_t idev)221 intel_iicbb_getscl(device_t idev)
222 {
223 struct intel_iic_softc *sc;
224 struct drm_i915_private *dev_priv;
225 u32 reserved;
226
227 sc = device_get_softc(idev);
228 dev_priv = sc->drm_dev->dev_private;
229
230 reserved = intel_iic_get_reserved(idev);
231
232 I915_WRITE_NOTRACE(sc->reg, reserved | GPIO_CLOCK_DIR_MASK);
233 I915_WRITE_NOTRACE(sc->reg, reserved);
234 return ((I915_READ_NOTRACE(sc->reg) & GPIO_CLOCK_VAL_IN) != 0);
235 }
236
237 static int
gmbus_xfer_read(struct drm_i915_private * dev_priv,struct iic_msg * msg,u32 gmbus1_index)238 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct iic_msg *msg,
239 u32 gmbus1_index)
240 {
241 int reg_offset = dev_priv->gpio_mmio_base;
242 u16 len = msg->len;
243 u8 *buf = msg->buf;
244
245 I915_WRITE(GMBUS1 + reg_offset,
246 gmbus1_index |
247 GMBUS_CYCLE_WAIT |
248 (len << GMBUS_BYTE_COUNT_SHIFT) |
249 (msg->slave << (GMBUS_SLAVE_ADDR_SHIFT - 1)) |
250 GMBUS_SLAVE_READ | GMBUS_SW_RDY);
251 while (len) {
252 int ret;
253 u32 val, loop = 0;
254 u32 gmbus2;
255
256 ret = _intel_wait_for(sc->drm_dev,
257 ((gmbus2 = I915_READ(GMBUS2 + reg_offset)) &
258 (GMBUS_SATOER | GMBUS_HW_RDY)),
259 50, 1, "915gbr");
260 if (ret)
261 return (-ETIMEDOUT);
262 if (gmbus2 & GMBUS_SATOER)
263 return (-ENXIO);
264
265 val = I915_READ(GMBUS3 + reg_offset);
266 do {
267 *buf++ = val & 0xff;
268 val >>= 8;
269 } while (--len != 0 && ++loop < 4);
270 }
271
272 return 0;
273 }
274
275 static int
gmbus_xfer_write(struct drm_i915_private * dev_priv,struct iic_msg * msg)276 gmbus_xfer_write(struct drm_i915_private *dev_priv, struct iic_msg *msg)
277 {
278 int reg_offset = dev_priv->gpio_mmio_base;
279 u16 len = msg->len;
280 u8 *buf = msg->buf;
281 u32 val, loop;
282
283 val = loop = 0;
284 while (len && loop < 4) {
285 val |= *buf++ << (8 * loop++);
286 len -= 1;
287 }
288
289 I915_WRITE(GMBUS3 + reg_offset, val);
290 I915_WRITE(GMBUS1 + reg_offset,
291 GMBUS_CYCLE_WAIT |
292 (msg->len << GMBUS_BYTE_COUNT_SHIFT) |
293 (msg->slave << (GMBUS_SLAVE_ADDR_SHIFT - 1)) |
294 GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
295 while (len) {
296 int ret;
297 u32 gmbus2;
298
299 val = loop = 0;
300 do {
301 val |= *buf++ << (8 * loop);
302 } while (--len != 0 && ++loop < 4);
303
304 I915_WRITE(GMBUS3 + reg_offset, val);
305
306 ret = _intel_wait_for(sc->drm_dev,
307 ((gmbus2 = I915_READ(GMBUS2 + reg_offset)) &
308 (GMBUS_SATOER | GMBUS_HW_RDY)),
309 50, 1, "915gbw");
310 if (ret)
311 return (-ETIMEDOUT);
312 if (gmbus2 & GMBUS_SATOER)
313 return (-ENXIO);
314 }
315 return 0;
316 }
317
318 /*
319 * The gmbus controller can combine a 1 or 2 byte write with a read that
320 * immediately follows it by using an "INDEX" cycle.
321 */
322 static bool
gmbus_is_index_read(struct iic_msg * msgs,int i,int num)323 gmbus_is_index_read(struct iic_msg *msgs, int i, int num)
324 {
325 return (i + 1 < num &&
326 !(msgs[i].flags & IIC_M_RD) && msgs[i].len <= 2 &&
327 (msgs[i + 1].flags & IIC_M_RD));
328 }
329
330 static int
gmbus_xfer_index_read(struct drm_i915_private * dev_priv,struct iic_msg * msgs)331 gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct iic_msg *msgs)
332 {
333 int reg_offset = dev_priv->gpio_mmio_base;
334 u32 gmbus1_index = 0;
335 u32 gmbus5 = 0;
336 int ret;
337
338 if (msgs[0].len == 2)
339 gmbus5 = GMBUS_2BYTE_INDEX_EN |
340 msgs[0].buf[1] | (msgs[0].buf[0] << 8);
341 if (msgs[0].len == 1)
342 gmbus1_index = GMBUS_CYCLE_INDEX |
343 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
344
345 /* GMBUS5 holds 16-bit index */
346 if (gmbus5)
347 I915_WRITE(GMBUS5 + reg_offset, gmbus5);
348
349 ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);
350
351 /* Clear GMBUS5 after each index transfer */
352 if (gmbus5)
353 I915_WRITE(GMBUS5 + reg_offset, 0);
354
355 return ret;
356 }
357
358 static int
intel_gmbus_transfer(device_t idev,struct iic_msg * msgs,uint32_t nmsgs)359 intel_gmbus_transfer(device_t idev, struct iic_msg *msgs, uint32_t nmsgs)
360 {
361 struct intel_iic_softc *sc;
362 struct drm_i915_private *dev_priv;
363 int error, i, ret, reg_offset, unit;
364
365 error = 0;
366 sc = device_get_softc(idev);
367 dev_priv = sc->drm_dev->dev_private;
368 unit = device_get_unit(idev);
369
370 sx_xlock(&dev_priv->gmbus_sx);
371 if (sc->force_bit_dev) {
372 error = -IICBUS_TRANSFER(dev_priv->bbbus[unit], msgs, nmsgs);
373 goto out;
374 }
375
376 reg_offset = dev_priv->gpio_mmio_base;
377
378 I915_WRITE(GMBUS0 + reg_offset, sc->reg0);
379
380 for (i = 0; i < nmsgs; i++) {
381 u32 gmbus2;
382
383 if (gmbus_is_index_read(msgs, i, nmsgs)) {
384 error = gmbus_xfer_index_read(dev_priv, &msgs[i]);
385 i += 1; /* set i to the index of the read xfer */
386 } else if (msgs[i].flags & IIC_M_RD) {
387 error = gmbus_xfer_read(dev_priv, &msgs[i], 0);
388 } else {
389 error = gmbus_xfer_write(dev_priv, &msgs[i]);
390 }
391
392 if (error == -ETIMEDOUT)
393 goto timeout;
394 if (error == -ENXIO)
395 goto clear_err;
396
397 ret = _intel_wait_for(sc->drm_dev,
398 ((gmbus2 = I915_READ(GMBUS2 + reg_offset)) &
399 (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE)),
400 50, 1, "915gbh");
401 if (ret)
402 goto timeout;
403 if (gmbus2 & GMBUS_SATOER)
404 goto clear_err;
405 }
406
407 /* Generate a STOP condition on the bus. Note that gmbus can't generata
408 * a STOP on the very first cycle. To simplify the code we
409 * unconditionally generate the STOP condition with an additional gmbus
410 * cycle. */
411 I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
412
413 /* Mark the GMBUS interface as disabled after waiting for idle.
414 * We will re-enable it at the start of the next xfer,
415 * till then let it sleep.
416 */
417 if (_intel_wait_for(dev,
418 (I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0,
419 10, 1, "915gbu")) {
420 DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n",
421 sc->name);
422 error = -ETIMEDOUT;
423 }
424 I915_WRITE(GMBUS0 + reg_offset, 0);
425 goto out;
426
427 clear_err:
428 /*
429 * Wait for bus to IDLE before clearing NAK.
430 * If we clear the NAK while bus is still active, then it will stay
431 * active and the next transaction may fail.
432 */
433 if (_intel_wait_for(dev,
434 (I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0,
435 10, 1, "915gbu"))
436 DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n", sc->name);
437
438 /* Toggle the Software Clear Interrupt bit. This has the effect
439 * of resetting the GMBUS controller and so clearing the
440 * BUS_ERROR raised by the slave's NAK.
441 */
442 I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
443 I915_WRITE(GMBUS1 + reg_offset, 0);
444 I915_WRITE(GMBUS0 + reg_offset, 0);
445
446 DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n",
447 sc->name, msgs[i].slave,
448 (msgs[i].flags & IIC_M_RD) ? 'r' : 'w', msgs[i].len);
449
450 /*
451 * If no ACK is received during the address phase of a transaction,
452 * the adapter must report -ENXIO.
453 * It is not clear what to return if no ACK is received at other times.
454 * So, we always return -ENXIO in all NAK cases, to ensure we send
455 * it at least during the one case that is specified.
456 */
457 error = -ENXIO;
458 goto out;
459
460 timeout:
461 DRM_INFO("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
462 sc->name, sc->reg0 & 0xff);
463 I915_WRITE(GMBUS0 + reg_offset, 0);
464
465 /*
466 * Hardware may not support GMBUS over these pins?
467 * Try GPIO bitbanging instead.
468 */
469 sc->force_bit_dev = true;
470 error = -IICBUS_TRANSFER(idev, msgs, nmsgs);
471 goto out;
472
473 out:
474 sx_xunlock(&dev_priv->gmbus_sx);
475 return (-error);
476 }
477
478 device_t
intel_gmbus_get_adapter(struct drm_i915_private * dev_priv,unsigned port)479 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
480 unsigned port)
481 {
482
483 if (!intel_gmbus_is_port_valid(port))
484 DRM_ERROR("GMBUS get adapter %d: invalid port\n", port);
485 return (intel_gmbus_is_port_valid(port) ? dev_priv->gmbus[port - 1] :
486 NULL);
487 }
488
489 void
intel_gmbus_set_speed(device_t idev,int speed)490 intel_gmbus_set_speed(device_t idev, int speed)
491 {
492 struct intel_iic_softc *sc;
493
494 sc = device_get_softc(device_get_parent(idev));
495
496 sc->reg0 = (sc->reg0 & ~(0x3 << 8)) | speed;
497 }
498
499 void
intel_gmbus_force_bit(device_t idev,bool force_bit)500 intel_gmbus_force_bit(device_t idev, bool force_bit)
501 {
502 struct intel_iic_softc *sc;
503
504 sc = device_get_softc(device_get_parent(idev));
505 sc->force_bit_dev = force_bit;
506 }
507
508 static int
intel_iicbb_pre_xfer(device_t idev)509 intel_iicbb_pre_xfer(device_t idev)
510 {
511 struct intel_iic_softc *sc;
512 struct drm_i915_private *dev_priv;
513
514 sc = device_get_softc(idev);
515 dev_priv = sc->drm_dev->dev_private;
516
517 intel_iic_reset(sc->drm_dev);
518 intel_iic_quirk_set(dev_priv, true);
519 IICBB_SETSDA(idev, 1);
520 IICBB_SETSCL(idev, 1);
521 DELAY(I2C_RISEFALL_TIME);
522 return (0);
523 }
524
525 static void
intel_iicbb_post_xfer(device_t idev)526 intel_iicbb_post_xfer(device_t idev)
527 {
528 struct intel_iic_softc *sc;
529 struct drm_i915_private *dev_priv;
530
531 sc = device_get_softc(idev);
532 dev_priv = sc->drm_dev->dev_private;
533
534 IICBB_SETSDA(idev, 1);
535 IICBB_SETSCL(idev, 1);
536 intel_iic_quirk_set(dev_priv, false);
537 }
538
539 static int
intel_gmbus_probe(device_t dev)540 intel_gmbus_probe(device_t dev)
541 {
542
543 return (BUS_PROBE_SPECIFIC);
544 }
545
546 static int
intel_gmbus_attach(device_t idev)547 intel_gmbus_attach(device_t idev)
548 {
549 struct drm_i915_private *dev_priv;
550 struct intel_iic_softc *sc;
551 int pin, port;
552
553 sc = device_get_softc(idev);
554 sc->drm_dev = device_get_softc(device_get_parent(idev));
555 dev_priv = sc->drm_dev->dev_private;
556 pin = device_get_unit(idev);
557 port = pin + 1;
558
559 snprintf(sc->name, sizeof(sc->name), "gmbus %s",
560 intel_gmbus_is_port_valid(port) ? gmbus_ports[pin].name :
561 "reserved");
562 device_set_desc(idev, sc->name);
563
564 /* By default use a conservative clock rate */
565 sc->reg0 = port | GMBUS_RATE_100KHZ;
566
567 /* gmbus seems to be broken on i830 */
568 if (IS_I830(sc->drm_dev))
569 sc->force_bit_dev = true;
570 #if 0
571 if (IS_GEN2(sc->drm_dev)) {
572 sc->force_bit_dev = true;
573 }
574 #endif
575
576 /* add bus interface device */
577 sc->iic_dev = device_add_child(idev, "iicbus", -1);
578 if (sc->iic_dev == NULL)
579 return (ENXIO);
580 device_quiet(sc->iic_dev);
581 bus_generic_attach(idev);
582
583 return (0);
584 }
585
586 static int
intel_gmbus_detach(device_t idev)587 intel_gmbus_detach(device_t idev)
588 {
589 struct intel_iic_softc *sc;
590 struct drm_i915_private *dev_priv;
591 device_t child;
592 int u;
593
594 sc = device_get_softc(idev);
595 u = device_get_unit(idev);
596 dev_priv = sc->drm_dev->dev_private;
597
598 child = sc->iic_dev;
599 bus_generic_detach(idev);
600 if (child != NULL)
601 device_delete_child(idev, child);
602
603 return (0);
604 }
605
606 static int
intel_iicbb_probe(device_t dev)607 intel_iicbb_probe(device_t dev)
608 {
609
610 return (BUS_PROBE_DEFAULT);
611 }
612
613 static int
intel_iicbb_attach(device_t idev)614 intel_iicbb_attach(device_t idev)
615 {
616 struct intel_iic_softc *sc;
617 struct drm_i915_private *dev_priv;
618 int pin, port;
619
620 sc = device_get_softc(idev);
621 sc->drm_dev = device_get_softc(device_get_parent(idev));
622 dev_priv = sc->drm_dev->dev_private;
623 pin = device_get_unit(idev);
624 port = pin + 1;
625
626 snprintf(sc->name, sizeof(sc->name), "i915 iicbb %s",
627 intel_gmbus_is_port_valid(port) ? gmbus_ports[pin].name :
628 "reserved");
629 device_set_desc(idev, sc->name);
630
631 if (!intel_gmbus_is_port_valid(port))
632 pin = 1 ; /* GPIOA, VGA */
633 sc->reg0 = pin | GMBUS_RATE_100KHZ;
634 sc->reg = dev_priv->gpio_mmio_base + gmbus_ports[pin].reg;
635
636 /* add generic bit-banging code */
637 sc->iic_dev = device_add_child(idev, "iicbb", -1);
638 if (sc->iic_dev == NULL)
639 return (ENXIO);
640 device_quiet(sc->iic_dev);
641 bus_generic_attach(idev);
642 iicbus_set_nostop(idev, true);
643
644 return (0);
645 }
646
647 static int
intel_iicbb_detach(device_t idev)648 intel_iicbb_detach(device_t idev)
649 {
650 struct intel_iic_softc *sc;
651 device_t child;
652
653 sc = device_get_softc(idev);
654 child = sc->iic_dev;
655 bus_generic_detach(idev);
656 if (child)
657 device_delete_child(idev, child);
658 return (0);
659 }
660
661 static device_method_t intel_gmbus_methods[] = {
662 DEVMETHOD(device_probe, intel_gmbus_probe),
663 DEVMETHOD(device_attach, intel_gmbus_attach),
664 DEVMETHOD(device_detach, intel_gmbus_detach),
665 DEVMETHOD(iicbus_reset, intel_iicbus_reset),
666 DEVMETHOD(iicbus_transfer, intel_gmbus_transfer),
667 DEVMETHOD_END
668 };
669 static driver_t intel_gmbus_driver = {
670 "intel_gmbus",
671 intel_gmbus_methods,
672 sizeof(struct intel_iic_softc)
673 };
674 static devclass_t intel_gmbus_devclass;
675 DRIVER_MODULE_ORDERED(intel_gmbus, drmn, intel_gmbus_driver,
676 intel_gmbus_devclass, 0, 0, SI_ORDER_FIRST);
677 DRIVER_MODULE(iicbus, intel_gmbus, iicbus_driver, iicbus_devclass, 0, 0);
678
679 static device_method_t intel_iicbb_methods[] = {
680 DEVMETHOD(device_probe, intel_iicbb_probe),
681 DEVMETHOD(device_attach, intel_iicbb_attach),
682 DEVMETHOD(device_detach, intel_iicbb_detach),
683
684 DEVMETHOD(bus_add_child, bus_generic_add_child),
685 DEVMETHOD(bus_print_child, bus_generic_print_child),
686
687 DEVMETHOD(iicbb_callback, iicbus_null_callback),
688 DEVMETHOD(iicbb_reset, intel_iicbus_reset),
689 DEVMETHOD(iicbb_setsda, intel_iicbb_setsda),
690 DEVMETHOD(iicbb_setscl, intel_iicbb_setscl),
691 DEVMETHOD(iicbb_getsda, intel_iicbb_getsda),
692 DEVMETHOD(iicbb_getscl, intel_iicbb_getscl),
693 DEVMETHOD(iicbb_pre_xfer, intel_iicbb_pre_xfer),
694 DEVMETHOD(iicbb_post_xfer, intel_iicbb_post_xfer),
695 DEVMETHOD_END
696 };
697 static driver_t intel_iicbb_driver = {
698 "intel_iicbb",
699 intel_iicbb_methods,
700 sizeof(struct intel_iic_softc)
701 };
702 static devclass_t intel_iicbb_devclass;
703 DRIVER_MODULE_ORDERED(intel_iicbb, drmn, intel_iicbb_driver,
704 intel_iicbb_devclass, 0, 0, SI_ORDER_FIRST);
705 DRIVER_MODULE(iicbb, intel_iicbb, iicbb_driver, iicbb_devclass, 0, 0);
706
707 int
intel_setup_gmbus(struct drm_device * dev)708 intel_setup_gmbus(struct drm_device *dev)
709 {
710 struct drm_i915_private *dev_priv;
711 device_t iic_dev;
712 int i, ret;
713
714 dev_priv = dev->dev_private;
715 sx_init(&dev_priv->gmbus_sx, "gmbus");
716 if (HAS_PCH_SPLIT(dev))
717 dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA;
718 else
719 dev_priv->gpio_mmio_base = 0;
720
721 /*
722 * The Giant there is recursed, most likely. Normally, the
723 * intel_setup_gmbus() is called from the attach method of the
724 * driver.
725 */
726 mtx_lock(&Giant);
727 for (i = 0; i <= GMBUS_NUM_PORTS; i++) {
728 /*
729 * Initialized bbbus_bridge before gmbus_bridge, since
730 * gmbus may decide to force quirk transfer in the
731 * attachment code.
732 */
733 dev_priv->bbbus_bridge[i] = device_add_child(dev->dev,
734 "intel_iicbb", i);
735 if (dev_priv->bbbus_bridge[i] == NULL) {
736 DRM_ERROR("bbbus bridge %d creation failed\n", i);
737 ret = -ENXIO;
738 goto err;
739 }
740 device_quiet(dev_priv->bbbus_bridge[i]);
741 ret = -device_probe_and_attach(dev_priv->bbbus_bridge[i]);
742 if (ret != 0) {
743 DRM_ERROR("bbbus bridge %d attach failed, %d\n", i,
744 ret);
745 goto err;
746 }
747
748 iic_dev = device_find_child(dev_priv->bbbus_bridge[i], "iicbb",
749 -1);
750 if (iic_dev == NULL) {
751 DRM_ERROR("bbbus bridge doesn't have iicbb child\n");
752 goto err;
753 }
754 iic_dev = device_find_child(iic_dev, "iicbus", -1);
755 if (iic_dev == NULL) {
756 DRM_ERROR(
757 "bbbus bridge doesn't have iicbus grandchild\n");
758 goto err;
759 }
760
761 dev_priv->bbbus[i] = iic_dev;
762
763 dev_priv->gmbus_bridge[i] = device_add_child(dev->dev,
764 "intel_gmbus", i);
765 if (dev_priv->gmbus_bridge[i] == NULL) {
766 DRM_ERROR("gmbus bridge %d creation failed\n", i);
767 ret = -ENXIO;
768 goto err;
769 }
770 device_quiet(dev_priv->gmbus_bridge[i]);
771 ret = -device_probe_and_attach(dev_priv->gmbus_bridge[i]);
772 if (ret != 0) {
773 DRM_ERROR("gmbus bridge %d attach failed, %d\n", i,
774 ret);
775 ret = -ENXIO;
776 goto err;
777 }
778
779 iic_dev = device_find_child(dev_priv->gmbus_bridge[i],
780 "iicbus", -1);
781 if (iic_dev == NULL) {
782 DRM_ERROR("gmbus bridge doesn't have iicbus child\n");
783 goto err;
784 }
785 dev_priv->gmbus[i] = iic_dev;
786
787 intel_iic_reset(dev);
788 }
789
790 mtx_unlock(&Giant);
791 return (0);
792
793 err:
794 intel_teardown_gmbus_m(dev, i);
795 mtx_unlock(&Giant);
796 return (ret);
797 }
798
799 static void
intel_teardown_gmbus_m(struct drm_device * dev,int m)800 intel_teardown_gmbus_m(struct drm_device *dev, int m)
801 {
802 struct drm_i915_private *dev_priv;
803
804 dev_priv = dev->dev_private;
805
806 sx_destroy(&dev_priv->gmbus_sx);
807 }
808
809 void
intel_teardown_gmbus(struct drm_device * dev)810 intel_teardown_gmbus(struct drm_device *dev)
811 {
812
813 mtx_lock(&Giant);
814 intel_teardown_gmbus_m(dev, GMBUS_NUM_PORTS);
815 mtx_unlock(&Giant);
816 }
817