1 /*-
2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4 * Copyright (c) 1997 KATO Takenori.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to Berkeley by
8 * William Jolitz.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the University of
21 * California, Berkeley and its contributors.
22 * 4. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * SUCH DAMAGE.
37 *
38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
39 */
40
41 #include <sys/cdefs.h>
42 #include "opt_cpu.h"
43
44 #include <sys/param.h>
45 #include <sys/bus.h>
46 #include <sys/cpu.h>
47 #include <sys/eventhandler.h>
48 #include <sys/limits.h>
49 #include <sys/systm.h>
50 #include <sys/kernel.h>
51 #include <sys/sysctl.h>
52 #include <sys/power.h>
53
54 #include <vm/vm.h>
55 #include <vm/pmap.h>
56
57 #include <machine/asmacros.h>
58 #include <machine/clock.h>
59 #include <machine/cputypes.h>
60 #include <machine/frame.h>
61 #include <machine/intr_machdep.h>
62 #include <machine/md_var.h>
63 #include <machine/segments.h>
64 #include <machine/specialreg.h>
65
66 #include <amd64/vmm/intel/vmx_controls.h>
67 #include <x86/isa/icu.h>
68 #include <x86/vmware.h>
69
70 #ifdef __i386__
71 #define IDENTBLUE_CYRIX486 0
72 #define IDENTBLUE_IBMCPU 1
73 #define IDENTBLUE_CYRIXM2 2
74
75 static void identifycyrix(void);
76 static void print_transmeta_info(void);
77 #endif
78 static u_int find_cpu_vendor_id(void);
79 static void print_AMD_info(void);
80 static void print_INTEL_info(void);
81 static void print_INTEL_TLB(u_int data);
82 static void print_hypervisor_info(void);
83 static void print_svm_info(void);
84 static void print_via_padlock_info(void);
85 static void print_vmx_info(void);
86
87 #ifdef __i386__
88 int cpu; /* Are we 386, 386sx, 486, etc? */
89 int cpu_class;
90 #endif
91 u_int cpu_feature; /* Feature flags */
92 u_int cpu_feature2; /* Feature flags */
93 u_int amd_feature; /* AMD feature flags */
94 u_int amd_feature2; /* AMD feature flags */
95 u_int amd_rascap; /* AMD RAS capabilities */
96 u_int amd_pminfo; /* AMD advanced power management info */
97 u_int amd_extended_feature_extensions;
98 u_int via_feature_rng; /* VIA RNG features */
99 u_int via_feature_xcrypt; /* VIA ACE features */
100 u_int cpu_high; /* Highest arg to CPUID */
101 u_int cpu_exthigh; /* Highest arg to extended CPUID */
102 u_int cpu_id; /* Stepping ID */
103 u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */
104 u_int cpu_procinfo2; /* Multicore info */
105 u_int cpu_procinfo3;
106 char cpu_vendor[20]; /* CPU Origin code */
107 u_int cpu_vendor_id; /* CPU vendor ID */
108 u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */
109 u_int cpu_clflush_line_size = 32;
110 /* leaf 7 %ecx = 0 */
111 u_int cpu_stdext_feature; /* %ebx */
112 u_int cpu_stdext_feature2; /* %ecx */
113 u_int cpu_stdext_feature3; /* %edx */
114 /* leaf 7 %ecx = 1 */
115 u_int cpu_stdext_feature4; /* %eax */
116 uint64_t cpu_ia32_arch_caps;
117 u_int cpu_max_ext_state_size;
118 u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */
119 u_int cpu_mon_mwait_edx; /* MONITOR/MWAIT supported on AMD (CPUID.05H.EDX) */
120 u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */
121 u_int cpu_mon_max_size; /* MONITOR minimum range size, bytes */
122 u_int cpu_maxphyaddr; /* Max phys addr width in bits */
123 u_int cpu_power_eax; /* 06H: Power management leaf, %eax */
124 u_int cpu_power_ebx; /* 06H: Power management leaf, %ebx */
125 u_int cpu_power_ecx; /* 06H: Power management leaf, %ecx */
126 u_int cpu_power_edx; /* 06H: Power management leaf, %edx */
127 const char machine[] = MACHINE;
128
129 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
130 &via_feature_rng, 0,
131 "VIA RNG feature available in CPU");
132 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
133 &via_feature_xcrypt, 0,
134 "VIA xcrypt feature available in CPU");
135
136 #ifdef __amd64__
137 #ifdef SCTL_MASK32
138 extern int adaptive_machine_arch;
139 #endif
140
141 static int
sysctl_hw_machine(SYSCTL_HANDLER_ARGS)142 sysctl_hw_machine(SYSCTL_HANDLER_ARGS)
143 {
144 #ifdef SCTL_MASK32
145 static const char machine32[] = "i386";
146 #endif
147 int error;
148
149 #ifdef SCTL_MASK32
150 if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch)
151 error = SYSCTL_OUT(req, machine32, sizeof(machine32));
152 else
153 #endif
154 error = SYSCTL_OUT(req, machine, sizeof(machine));
155 return (error);
156
157 }
158 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD |
159 CTLFLAG_CAPRD | CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A", "Machine class");
160 #else
161 SYSCTL_CONST_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD | CTLFLAG_CAPRD,
162 machine, "Machine class");
163 #endif
164
165 char cpu_model[128];
166 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD | CTLFLAG_CAPRD,
167 cpu_model, 0, "Machine model");
168
169 static int hw_clockrate;
170 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
171 &hw_clockrate, 0, "CPU instruction clock rate");
172
173 u_int hv_base;
174 u_int hv_high;
175 char hv_vendor[16];
176 SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD, hv_vendor,
177 0, "Hypervisor vendor");
178
179 static eventhandler_tag tsc_post_tag;
180
181 static char cpu_brand[48];
182
183 #ifdef __i386__
184 #define MAX_BRAND_INDEX 8
185
186 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
187 NULL, /* No brand */
188 "Intel Celeron",
189 "Intel Pentium III",
190 "Intel Pentium III Xeon",
191 NULL,
192 NULL,
193 NULL,
194 NULL,
195 "Intel Pentium 4"
196 };
197
198 static struct {
199 char *cpu_name;
200 int cpu_class;
201 } cpus[] = {
202 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */
203 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */
204 { "i386DX", CPUCLASS_386 }, /* CPU_386 */
205 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */
206 { "i486DX", CPUCLASS_486 }, /* CPU_486 */
207 { "Pentium", CPUCLASS_586 }, /* CPU_586 */
208 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */
209 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */
210 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */
211 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */
212 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */
213 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */
214 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */
215 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */
216 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */
217 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */
218 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */
219 };
220 #endif
221
222 static struct {
223 char *vendor;
224 u_int vendor_id;
225 } cpu_vendors[] = {
226 { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */
227 { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */
228 { HYGON_VENDOR_ID, CPU_VENDOR_HYGON }, /* HygonGenuine */
229 { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */
230 #ifdef __i386__
231 { NSC_VENDOR_ID, CPU_VENDOR_NSC }, /* Geode by NSC */
232 { CYRIX_VENDOR_ID, CPU_VENDOR_CYRIX }, /* CyrixInstead */
233 { TRANSMETA_VENDOR_ID, CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
234 { SIS_VENDOR_ID, CPU_VENDOR_SIS }, /* SiS SiS SiS */
235 { UMC_VENDOR_ID, CPU_VENDOR_UMC }, /* UMC UMC UMC */
236 { NEXGEN_VENDOR_ID, CPU_VENDOR_NEXGEN }, /* NexGenDriven */
237 { RISE_VENDOR_ID, CPU_VENDOR_RISE }, /* RiseRiseRise */
238 #if 0
239 /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
240 { "TransmetaCPU", CPU_VENDOR_TRANSMETA },
241 #endif
242 #endif
243 };
244
245 void
printcpuinfo(void)246 printcpuinfo(void)
247 {
248 u_int regs[4], i;
249 char *brand;
250
251 printf("CPU: ");
252 #ifdef __i386__
253 cpu_class = cpus[cpu].cpu_class;
254 strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model));
255 #else
256 strncpy(cpu_model, "Hammer", sizeof (cpu_model));
257 #endif
258
259 /* Check for extended CPUID information and a processor name. */
260 if (cpu_exthigh >= 0x80000004) {
261 brand = cpu_brand;
262 for (i = 0x80000002; i < 0x80000005; i++) {
263 do_cpuid(i, regs);
264 memcpy(brand, regs, sizeof(regs));
265 brand += sizeof(regs);
266 }
267 }
268
269 switch (cpu_vendor_id) {
270 case CPU_VENDOR_INTEL:
271 #ifdef __i386__
272 if ((cpu_id & 0xf00) > 0x300) {
273 u_int brand_index;
274
275 cpu_model[0] = '\0';
276
277 switch (cpu_id & 0x3000) {
278 case 0x1000:
279 strcpy(cpu_model, "Overdrive ");
280 break;
281 case 0x2000:
282 strcpy(cpu_model, "Dual ");
283 break;
284 }
285
286 switch (cpu_id & 0xf00) {
287 case 0x400:
288 strcat(cpu_model, "i486 ");
289 /* Check the particular flavor of 486 */
290 switch (cpu_id & 0xf0) {
291 case 0x00:
292 case 0x10:
293 strcat(cpu_model, "DX");
294 break;
295 case 0x20:
296 strcat(cpu_model, "SX");
297 break;
298 case 0x30:
299 strcat(cpu_model, "DX2");
300 break;
301 case 0x40:
302 strcat(cpu_model, "SL");
303 break;
304 case 0x50:
305 strcat(cpu_model, "SX2");
306 break;
307 case 0x70:
308 strcat(cpu_model,
309 "DX2 Write-Back Enhanced");
310 break;
311 case 0x80:
312 strcat(cpu_model, "DX4");
313 break;
314 }
315 break;
316 case 0x500:
317 /* Check the particular flavor of 586 */
318 strcat(cpu_model, "Pentium");
319 switch (cpu_id & 0xf0) {
320 case 0x00:
321 strcat(cpu_model, " A-step");
322 break;
323 case 0x10:
324 strcat(cpu_model, "/P5");
325 break;
326 case 0x20:
327 strcat(cpu_model, "/P54C");
328 break;
329 case 0x30:
330 strcat(cpu_model, "/P24T");
331 break;
332 case 0x40:
333 strcat(cpu_model, "/P55C");
334 break;
335 case 0x70:
336 strcat(cpu_model, "/P54C");
337 break;
338 case 0x80:
339 strcat(cpu_model, "/P55C (quarter-micron)");
340 break;
341 default:
342 /* nothing */
343 break;
344 }
345 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
346 /*
347 * XXX - If/when Intel fixes the bug, this
348 * should also check the version of the
349 * CPU, not just that it's a Pentium.
350 */
351 has_f00f_bug = 1;
352 #endif
353 break;
354 case 0x600:
355 /* Check the particular flavor of 686 */
356 switch (cpu_id & 0xf0) {
357 case 0x00:
358 strcat(cpu_model, "Pentium Pro A-step");
359 break;
360 case 0x10:
361 strcat(cpu_model, "Pentium Pro");
362 break;
363 case 0x30:
364 case 0x50:
365 case 0x60:
366 strcat(cpu_model,
367 "Pentium II/Pentium II Xeon/Celeron");
368 cpu = CPU_PII;
369 break;
370 case 0x70:
371 case 0x80:
372 case 0xa0:
373 case 0xb0:
374 strcat(cpu_model,
375 "Pentium III/Pentium III Xeon/Celeron");
376 cpu = CPU_PIII;
377 break;
378 default:
379 strcat(cpu_model, "Unknown 80686");
380 break;
381 }
382 break;
383 case 0xf00:
384 strcat(cpu_model, "Pentium 4");
385 cpu = CPU_P4;
386 break;
387 default:
388 strcat(cpu_model, "unknown");
389 break;
390 }
391
392 /*
393 * If we didn't get a brand name from the extended
394 * CPUID, try to look it up in the brand table.
395 */
396 if (cpu_high > 0 && *cpu_brand == '\0') {
397 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
398 if (brand_index <= MAX_BRAND_INDEX &&
399 cpu_brandtable[brand_index] != NULL)
400 strcpy(cpu_brand,
401 cpu_brandtable[brand_index]);
402 }
403 }
404 #else
405 /* Please make up your mind folks! */
406 strcat(cpu_model, "EM64T");
407 #endif
408 break;
409 case CPU_VENDOR_AMD:
410 /*
411 * Values taken from AMD Processor Recognition
412 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
413 * (also describes ``Features'' encodings.
414 */
415 strcpy(cpu_model, "AMD ");
416 #ifdef __i386__
417 switch (cpu_id & 0xFF0) {
418 case 0x410:
419 strcat(cpu_model, "Standard Am486DX");
420 break;
421 case 0x430:
422 strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
423 break;
424 case 0x470:
425 strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
426 break;
427 case 0x480:
428 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
429 break;
430 case 0x490:
431 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
432 break;
433 case 0x4E0:
434 strcat(cpu_model, "Am5x86 Write-Through");
435 break;
436 case 0x4F0:
437 strcat(cpu_model, "Am5x86 Write-Back");
438 break;
439 case 0x500:
440 strcat(cpu_model, "K5 model 0");
441 break;
442 case 0x510:
443 strcat(cpu_model, "K5 model 1");
444 break;
445 case 0x520:
446 strcat(cpu_model, "K5 PR166 (model 2)");
447 break;
448 case 0x530:
449 strcat(cpu_model, "K5 PR200 (model 3)");
450 break;
451 case 0x560:
452 strcat(cpu_model, "K6");
453 break;
454 case 0x570:
455 strcat(cpu_model, "K6 266 (model 1)");
456 break;
457 case 0x580:
458 strcat(cpu_model, "K6-2");
459 break;
460 case 0x590:
461 strcat(cpu_model, "K6-III");
462 break;
463 case 0x5a0:
464 strcat(cpu_model, "Geode LX");
465 break;
466 default:
467 strcat(cpu_model, "Unknown");
468 break;
469 }
470 #else
471 if ((cpu_id & 0xf00) == 0xf00)
472 strcat(cpu_model, "AMD64 Processor");
473 else
474 strcat(cpu_model, "Unknown");
475 #endif
476 break;
477 #ifdef __i386__
478 case CPU_VENDOR_CYRIX:
479 strcpy(cpu_model, "Cyrix ");
480 switch (cpu_id & 0xff0) {
481 case 0x440:
482 strcat(cpu_model, "MediaGX");
483 break;
484 case 0x520:
485 strcat(cpu_model, "6x86");
486 break;
487 case 0x540:
488 cpu_class = CPUCLASS_586;
489 strcat(cpu_model, "GXm");
490 break;
491 case 0x600:
492 strcat(cpu_model, "6x86MX");
493 break;
494 default:
495 /*
496 * Even though CPU supports the cpuid
497 * instruction, it can be disabled.
498 * Therefore, this routine supports all Cyrix
499 * CPUs.
500 */
501 switch (cyrix_did & 0xf0) {
502 case 0x00:
503 switch (cyrix_did & 0x0f) {
504 case 0x00:
505 strcat(cpu_model, "486SLC");
506 break;
507 case 0x01:
508 strcat(cpu_model, "486DLC");
509 break;
510 case 0x02:
511 strcat(cpu_model, "486SLC2");
512 break;
513 case 0x03:
514 strcat(cpu_model, "486DLC2");
515 break;
516 case 0x04:
517 strcat(cpu_model, "486SRx");
518 break;
519 case 0x05:
520 strcat(cpu_model, "486DRx");
521 break;
522 case 0x06:
523 strcat(cpu_model, "486SRx2");
524 break;
525 case 0x07:
526 strcat(cpu_model, "486DRx2");
527 break;
528 case 0x08:
529 strcat(cpu_model, "486SRu");
530 break;
531 case 0x09:
532 strcat(cpu_model, "486DRu");
533 break;
534 case 0x0a:
535 strcat(cpu_model, "486SRu2");
536 break;
537 case 0x0b:
538 strcat(cpu_model, "486DRu2");
539 break;
540 default:
541 strcat(cpu_model, "Unknown");
542 break;
543 }
544 break;
545 case 0x10:
546 switch (cyrix_did & 0x0f) {
547 case 0x00:
548 strcat(cpu_model, "486S");
549 break;
550 case 0x01:
551 strcat(cpu_model, "486S2");
552 break;
553 case 0x02:
554 strcat(cpu_model, "486Se");
555 break;
556 case 0x03:
557 strcat(cpu_model, "486S2e");
558 break;
559 case 0x0a:
560 strcat(cpu_model, "486DX");
561 break;
562 case 0x0b:
563 strcat(cpu_model, "486DX2");
564 break;
565 case 0x0f:
566 strcat(cpu_model, "486DX4");
567 break;
568 default:
569 strcat(cpu_model, "Unknown");
570 break;
571 }
572 break;
573 case 0x20:
574 if ((cyrix_did & 0x0f) < 8)
575 strcat(cpu_model, "6x86"); /* Where did you get it? */
576 else
577 strcat(cpu_model, "5x86");
578 break;
579 case 0x30:
580 strcat(cpu_model, "6x86");
581 break;
582 case 0x40:
583 if ((cyrix_did & 0xf000) == 0x3000) {
584 cpu_class = CPUCLASS_586;
585 strcat(cpu_model, "GXm");
586 } else
587 strcat(cpu_model, "MediaGX");
588 break;
589 case 0x50:
590 strcat(cpu_model, "6x86MX");
591 break;
592 case 0xf0:
593 switch (cyrix_did & 0x0f) {
594 case 0x0d:
595 strcat(cpu_model, "Overdrive CPU");
596 break;
597 case 0x0e:
598 strcpy(cpu_model, "Texas Instruments 486SXL");
599 break;
600 case 0x0f:
601 strcat(cpu_model, "486SLC/DLC");
602 break;
603 default:
604 strcat(cpu_model, "Unknown");
605 break;
606 }
607 break;
608 default:
609 strcat(cpu_model, "Unknown");
610 break;
611 }
612 break;
613 }
614 break;
615 case CPU_VENDOR_RISE:
616 strcpy(cpu_model, "Rise ");
617 switch (cpu_id & 0xff0) {
618 case 0x500: /* 6401 and 6441 (Kirin) */
619 case 0x520: /* 6510 (Lynx) */
620 strcat(cpu_model, "mP6");
621 break;
622 default:
623 strcat(cpu_model, "Unknown");
624 }
625 break;
626 #endif
627 case CPU_VENDOR_CENTAUR:
628 #ifdef __i386__
629 switch (cpu_id & 0xff0) {
630 case 0x540:
631 strcpy(cpu_model, "IDT WinChip C6");
632 break;
633 case 0x580:
634 strcpy(cpu_model, "IDT WinChip 2");
635 break;
636 case 0x590:
637 strcpy(cpu_model, "IDT WinChip 3");
638 break;
639 case 0x660:
640 strcpy(cpu_model, "VIA C3 Samuel");
641 break;
642 case 0x670:
643 if (cpu_id & 0x8)
644 strcpy(cpu_model, "VIA C3 Ezra");
645 else
646 strcpy(cpu_model, "VIA C3 Samuel 2");
647 break;
648 case 0x680:
649 strcpy(cpu_model, "VIA C3 Ezra-T");
650 break;
651 case 0x690:
652 strcpy(cpu_model, "VIA C3 Nehemiah");
653 break;
654 case 0x6a0:
655 case 0x6d0:
656 strcpy(cpu_model, "VIA C7 Esther");
657 break;
658 case 0x6f0:
659 strcpy(cpu_model, "VIA Nano");
660 break;
661 default:
662 strcpy(cpu_model, "VIA/IDT Unknown");
663 }
664 #else
665 strcpy(cpu_model, "VIA ");
666 if ((cpu_id & 0xff0) == 0x6f0)
667 strcat(cpu_model, "Nano Processor");
668 else
669 strcat(cpu_model, "Unknown");
670 #endif
671 break;
672 #ifdef __i386__
673 case CPU_VENDOR_IBM:
674 strcpy(cpu_model, "Blue Lightning CPU");
675 break;
676 case CPU_VENDOR_NSC:
677 switch (cpu_id & 0xff0) {
678 case 0x540:
679 strcpy(cpu_model, "Geode SC1100");
680 cpu = CPU_GEODE1100;
681 break;
682 default:
683 strcpy(cpu_model, "Geode/NSC unknown");
684 break;
685 }
686 break;
687 #endif
688 case CPU_VENDOR_HYGON:
689 strcpy(cpu_model, "Hygon ");
690 #ifdef __i386__
691 strcat(cpu_model, "Unknown");
692 #else
693 if ((cpu_id & 0xf00) == 0xf00)
694 strcat(cpu_model, "AMD64 Processor");
695 else
696 strcat(cpu_model, "Unknown");
697 #endif
698 break;
699
700 default:
701 strcat(cpu_model, "Unknown");
702 break;
703 }
704
705 /*
706 * Replace cpu_model with cpu_brand minus leading spaces if
707 * we have one.
708 */
709 brand = cpu_brand;
710 while (*brand == ' ')
711 ++brand;
712 if (*brand != '\0')
713 strcpy(cpu_model, brand);
714
715 printf("%s (", cpu_model);
716 if (tsc_freq != 0) {
717 hw_clockrate = (tsc_freq + 5000) / 1000000;
718 printf("%jd.%02d-MHz ",
719 (intmax_t)(tsc_freq + 4999) / 1000000,
720 (u_int)((tsc_freq + 4999) / 10000) % 100);
721 }
722 #ifdef __i386__
723 switch(cpu_class) {
724 case CPUCLASS_286:
725 printf("286");
726 break;
727 case CPUCLASS_386:
728 printf("386");
729 break;
730 #if defined(I486_CPU)
731 case CPUCLASS_486:
732 printf("486");
733 break;
734 #endif
735 #if defined(I586_CPU)
736 case CPUCLASS_586:
737 printf("586");
738 break;
739 #endif
740 #if defined(I686_CPU)
741 case CPUCLASS_686:
742 printf("686");
743 break;
744 #endif
745 default:
746 printf("Unknown"); /* will panic below... */
747 }
748 #else
749 printf("K8");
750 #endif
751 printf("-class CPU)\n");
752 if (*cpu_vendor)
753 printf(" Origin=\"%s\"", cpu_vendor);
754 if (cpu_id)
755 printf(" Id=0x%x", cpu_id);
756
757 if (cpu_vendor_id == CPU_VENDOR_INTEL ||
758 cpu_vendor_id == CPU_VENDOR_AMD ||
759 cpu_vendor_id == CPU_VENDOR_HYGON ||
760 cpu_vendor_id == CPU_VENDOR_CENTAUR ||
761 #ifdef __i386__
762 cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
763 cpu_vendor_id == CPU_VENDOR_RISE ||
764 cpu_vendor_id == CPU_VENDOR_NSC ||
765 (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) ||
766 #endif
767 0) {
768 printf(" Family=0x%x", CPUID_TO_FAMILY(cpu_id));
769 printf(" Model=0x%x", CPUID_TO_MODEL(cpu_id));
770 printf(" Stepping=%u", cpu_id & CPUID_STEPPING);
771 #ifdef __i386__
772 if (cpu_vendor_id == CPU_VENDOR_CYRIX)
773 printf("\n DIR=0x%04x", cyrix_did);
774 #endif
775
776 /*
777 * AMD CPUID Specification
778 * http://support.amd.com/us/Embedded_TechDocs/25481.pdf
779 *
780 * Intel Processor Identification and CPUID Instruction
781 * http://www.intel.com/assets/pdf/appnote/241618.pdf
782 */
783 if (cpu_high > 0) {
784 /*
785 * Here we should probably set up flags indicating
786 * whether or not various features are available.
787 * The interesting ones are probably VME, PSE, PAE,
788 * and PGE. The code already assumes without bothering
789 * to check that all CPUs >= Pentium have a TSC and
790 * MSRs.
791 */
792 printf("\n Features=0x%b", cpu_feature,
793 "\020"
794 "\001FPU" /* Integral FPU */
795 "\002VME" /* Extended VM86 mode support */
796 "\003DE" /* Debugging Extensions (CR4.DE) */
797 "\004PSE" /* 4MByte page tables */
798 "\005TSC" /* Timestamp counter */
799 "\006MSR" /* Machine specific registers */
800 "\007PAE" /* Physical address extension */
801 "\010MCE" /* Machine Check support */
802 "\011CX8" /* CMPEXCH8 instruction */
803 "\012APIC" /* SMP local APIC */
804 "\013oldMTRR" /* Previous implementation of MTRR */
805 "\014SEP" /* Fast System Call */
806 "\015MTRR" /* Memory Type Range Registers */
807 "\016PGE" /* PG_G (global bit) support */
808 "\017MCA" /* Machine Check Architecture */
809 "\020CMOV" /* CMOV instruction */
810 "\021PAT" /* Page attributes table */
811 "\022PSE36" /* 36 bit address space support */
812 "\023PN" /* Processor Serial number */
813 "\024CLFLUSH" /* Has the CLFLUSH instruction */
814 "\025<b20>"
815 "\026DTS" /* Debug Trace Store */
816 "\027ACPI" /* ACPI support */
817 "\030MMX" /* MMX instructions */
818 "\031FXSR" /* FXSAVE/FXRSTOR */
819 "\032SSE" /* Streaming SIMD Extensions */
820 "\033SSE2" /* Streaming SIMD Extensions #2 */
821 "\034SS" /* Self snoop */
822 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */
823 "\036TM" /* Thermal Monitor clock slowdown */
824 "\037IA64" /* CPU can execute IA64 instructions */
825 "\040PBE" /* Pending Break Enable */
826 );
827
828 if (cpu_feature2 != 0) {
829 printf("\n Features2=0x%b", cpu_feature2,
830 "\020"
831 "\001SSE3" /* SSE3 */
832 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
833 "\003DTES64" /* 64-bit Debug Trace */
834 "\004MON" /* MONITOR/MWAIT Instructions */
835 "\005DS_CPL" /* CPL Qualified Debug Store */
836 "\006VMX" /* Virtual Machine Extensions */
837 "\007SMX" /* Safer Mode Extensions */
838 "\010EST" /* Enhanced SpeedStep */
839 "\011TM2" /* Thermal Monitor 2 */
840 "\012SSSE3" /* SSSE3 */
841 "\013CNXT-ID" /* L1 context ID available */
842 "\014SDBG" /* IA32 silicon debug */
843 "\015FMA" /* Fused Multiply Add */
844 "\016CX16" /* CMPXCHG16B Instruction */
845 "\017xTPR" /* Send Task Priority Messages*/
846 "\020PDCM" /* Perf/Debug Capability MSR */
847 "\021<b16>"
848 "\022PCID" /* Process-context Identifiers*/
849 "\023DCA" /* Direct Cache Access */
850 "\024SSE4.1" /* SSE 4.1 */
851 "\025SSE4.2" /* SSE 4.2 */
852 "\026x2APIC" /* xAPIC Extensions */
853 "\027MOVBE" /* MOVBE Instruction */
854 "\030POPCNT" /* POPCNT Instruction */
855 "\031TSCDLT" /* TSC-Deadline Timer */
856 "\032AESNI" /* AES Crypto */
857 "\033XSAVE" /* XSAVE/XRSTOR States */
858 "\034OSXSAVE" /* OS-Enabled State Management*/
859 "\035AVX" /* Advanced Vector Extensions */
860 "\036F16C" /* Half-precision conversions */
861 "\037RDRAND" /* RDRAND Instruction */
862 "\040HV" /* Hypervisor */
863 );
864 }
865
866 if (amd_feature != 0) {
867 printf("\n AMD Features=0x%b", amd_feature,
868 "\020" /* in hex */
869 "\001<s0>" /* Same */
870 "\002<s1>" /* Same */
871 "\003<s2>" /* Same */
872 "\004<s3>" /* Same */
873 "\005<s4>" /* Same */
874 "\006<s5>" /* Same */
875 "\007<s6>" /* Same */
876 "\010<s7>" /* Same */
877 "\011<s8>" /* Same */
878 "\012<s9>" /* Same */
879 "\013<b10>" /* Undefined */
880 "\014SYSCALL" /* Have SYSCALL/SYSRET */
881 "\015<s12>" /* Same */
882 "\016<s13>" /* Same */
883 "\017<s14>" /* Same */
884 "\020<s15>" /* Same */
885 "\021<s16>" /* Same */
886 "\022<s17>" /* Same */
887 "\023<b18>" /* Reserved, unknown */
888 "\024MP" /* Multiprocessor Capable */
889 "\025NX" /* Has EFER.NXE, NX */
890 "\026<b21>" /* Undefined */
891 "\027MMX+" /* AMD MMX Extensions */
892 "\030<s23>" /* Same */
893 "\031<s24>" /* Same */
894 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */
895 "\033Page1GB" /* 1-GB large page support */
896 "\034RDTSCP" /* RDTSCP */
897 "\035<b28>" /* Undefined */
898 "\036LM" /* 64 bit long mode */
899 "\0373DNow!+" /* AMD 3DNow! Extensions */
900 "\0403DNow!" /* AMD 3DNow! */
901 );
902 }
903
904 if (amd_feature2 != 0) {
905 printf("\n AMD Features2=0x%b", amd_feature2,
906 "\020"
907 "\001LAHF" /* LAHF/SAHF in long mode */
908 "\002CMP" /* CMP legacy */
909 "\003SVM" /* Secure Virtual Mode */
910 "\004ExtAPIC" /* Extended APIC register */
911 "\005CR8" /* CR8 in legacy mode */
912 "\006ABM" /* LZCNT instruction */
913 "\007SSE4A" /* SSE4A */
914 "\010MAS" /* Misaligned SSE mode */
915 "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */
916 "\012OSVW" /* OS visible workaround */
917 "\013IBS" /* Instruction based sampling */
918 "\014XOP" /* XOP extended instructions */
919 "\015SKINIT" /* SKINIT/STGI */
920 "\016WDT" /* Watchdog timer */
921 "\017<b14>"
922 "\020LWP" /* Lightweight Profiling */
923 "\021FMA4" /* 4-operand FMA instructions */
924 "\022TCE" /* Translation Cache Extension */
925 "\023<b18>"
926 "\024NodeId" /* NodeId MSR support */
927 "\025<b20>"
928 "\026TBM" /* Trailing Bit Manipulation */
929 "\027Topology" /* Topology Extensions */
930 "\030PCXC" /* Core perf count */
931 "\031PNXC" /* NB perf count */
932 "\032<b25>"
933 "\033DBE" /* Data Breakpoint extension */
934 "\034PTSC" /* Performance TSC */
935 "\035PL2I" /* L2I perf count */
936 "\036MWAITX" /* MONITORX/MWAITX instructions */
937 "\037ADMSKX" /* Address mask extension */
938 "\040<b31>"
939 );
940 }
941
942 if (cpu_stdext_feature != 0) {
943 printf("\n Structured Extended Features=0x%b",
944 cpu_stdext_feature,
945 "\020"
946 /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
947 "\001FSGSBASE"
948 "\002TSCADJ"
949 "\003SGX"
950 /* Bit Manipulation Instructions */
951 "\004BMI1"
952 /* Hardware Lock Elision */
953 "\005HLE"
954 /* Advanced Vector Instructions 2 */
955 "\006AVX2"
956 /* FDP_EXCPTN_ONLY */
957 "\007FDPEXC"
958 /* Supervisor Mode Execution Prot. */
959 "\010SMEP"
960 /* Bit Manipulation Instructions */
961 "\011BMI2"
962 "\012ERMS"
963 /* Invalidate Processor Context ID */
964 "\013INVPCID"
965 /* Restricted Transactional Memory */
966 "\014RTM"
967 "\015PQM"
968 "\016NFPUSG"
969 /* Intel Memory Protection Extensions */
970 "\017MPX"
971 "\020PQE"
972 /* AVX512 Foundation */
973 "\021AVX512F"
974 "\022AVX512DQ"
975 /* Enhanced NRBG */
976 "\023RDSEED"
977 /* ADCX + ADOX */
978 "\024ADX"
979 /* Supervisor Mode Access Prevention */
980 "\025SMAP"
981 "\026AVX512IFMA"
982 /* Formerly PCOMMIT */
983 "\027<b22>"
984 "\030CLFLUSHOPT"
985 "\031CLWB"
986 "\032PROCTRACE"
987 "\033AVX512PF"
988 "\034AVX512ER"
989 "\035AVX512CD"
990 "\036SHA"
991 "\037AVX512BW"
992 "\040AVX512VL"
993 );
994 }
995
996 if (cpu_stdext_feature2 != 0) {
997 printf("\n Structured Extended Features2=0x%b",
998 cpu_stdext_feature2,
999 "\020"
1000 "\001PREFETCHWT1"
1001 "\002AVX512VBMI"
1002 "\003UMIP"
1003 "\004PKU"
1004 "\005OSPKE"
1005 "\006WAITPKG"
1006 "\007AVX512VBMI2"
1007 "\011GFNI"
1008 "\012VAES"
1009 "\013VPCLMULQDQ"
1010 "\014AVX512VNNI"
1011 "\015AVX512BITALG"
1012 "\016TME"
1013 "\017AVX512VPOPCNTDQ"
1014 "\021LA57"
1015 "\027RDPID"
1016 "\032CLDEMOTE"
1017 "\034MOVDIRI"
1018 "\035MOVDIR64B"
1019 "\036ENQCMD"
1020 "\037SGXLC"
1021 );
1022 }
1023
1024 if (cpu_stdext_feature3 != 0) {
1025 printf("\n Structured Extended Features3=0x%b",
1026 cpu_stdext_feature3,
1027 "\020"
1028 "\003AVX512_4VNNIW"
1029 "\004AVX512_4FMAPS"
1030 "\005FSRM"
1031 "\011AVX512VP2INTERSECT"
1032 "\012MCUOPT"
1033 "\013MD_CLEAR"
1034 "\016TSXFA"
1035 "\023PCONFIG"
1036 "\025IBT"
1037 "\033IBPB"
1038 "\034STIBP"
1039 "\035L1DFL"
1040 "\036ARCH_CAP"
1041 "\037CORE_CAP"
1042 "\040SSBD"
1043 );
1044 }
1045 #define STDEXT4_MASK (CPUID_STDEXT4_LASS | CPUID_STDEXT4_LAM)
1046 if ((cpu_stdext_feature4 & STDEXT4_MASK) != 0) {
1047 printf("\n Structured Extended Features4=0x%b",
1048 cpu_stdext_feature4 & STDEXT4_MASK,
1049 "\020"
1050 "\007LASS"
1051 "\033LAM"
1052 );
1053 }
1054 #undef STDEXT4_MASK
1055
1056 if ((cpu_feature2 & CPUID2_XSAVE) != 0) {
1057 cpuid_count(0xd, 0x1, regs);
1058 if (regs[0] != 0) {
1059 printf("\n XSAVE Features=0x%b",
1060 regs[0],
1061 "\020"
1062 "\001XSAVEOPT"
1063 "\002XSAVEC"
1064 "\003XINUSE"
1065 "\004XSAVES");
1066 }
1067 }
1068
1069 if (cpu_ia32_arch_caps != 0) {
1070 printf("\n IA32_ARCH_CAPS=0x%b",
1071 (u_int)cpu_ia32_arch_caps,
1072 "\020"
1073 "\001RDCL_NO"
1074 "\002IBRS_ALL"
1075 "\003RSBA"
1076 "\004SKIP_L1DFL_VME"
1077 "\005SSB_NO"
1078 "\006MDS_NO"
1079 "\010TSX_CTRL"
1080 "\011TAA_NO"
1081 );
1082 }
1083
1084 if (amd_extended_feature_extensions != 0) {
1085 u_int amd_fe_masked;
1086
1087 amd_fe_masked = amd_extended_feature_extensions;
1088 if ((amd_fe_masked & AMDFEID_IBRS) == 0)
1089 amd_fe_masked &=
1090 ~(AMDFEID_IBRS_ALWAYSON |
1091 AMDFEID_PREFER_IBRS);
1092 if ((amd_fe_masked & AMDFEID_STIBP) == 0)
1093 amd_fe_masked &=
1094 ~AMDFEID_STIBP_ALWAYSON;
1095
1096 printf("\n "
1097 "AMD Extended Feature Extensions ID EBX="
1098 "0x%b", amd_fe_masked,
1099 "\020"
1100 "\001CLZERO"
1101 "\002IRPerf"
1102 "\003XSaveErPtr"
1103 "\004INVLPGB"
1104 "\005RDPRU"
1105 "\007BE"
1106 "\011MCOMMIT"
1107 "\012WBNOINVD"
1108 "\015IBPB"
1109 "\016INT_WBINVD"
1110 "\017IBRS"
1111 "\020STIBP"
1112 "\021IBRS_ALWAYSON"
1113 "\022STIBP_ALWAYSON"
1114 "\023PREFER_IBRS"
1115 "\024SAMEMODE_IBRS"
1116 "\025NOLMSLE"
1117 "\026INVLPGBNEST"
1118 "\030PPIN"
1119 "\031SSBD"
1120 "\032VIRT_SSBD"
1121 "\033SSB_NO"
1122 "\034CPPC"
1123 "\035PSFD"
1124 "\036BTC_NO"
1125 "\037IBPB_RET"
1126 );
1127 }
1128
1129 if (via_feature_rng != 0 || via_feature_xcrypt != 0)
1130 print_via_padlock_info();
1131
1132 if (cpu_feature2 & CPUID2_VMX)
1133 print_vmx_info();
1134
1135 if (amd_feature2 & AMDID2_SVM)
1136 print_svm_info();
1137
1138 if ((cpu_feature & CPUID_HTT) &&
1139 (cpu_vendor_id == CPU_VENDOR_AMD ||
1140 cpu_vendor_id == CPU_VENDOR_HYGON))
1141 cpu_feature &= ~CPUID_HTT;
1142
1143 /*
1144 * If this CPU supports P-state invariant TSC then
1145 * mention the capability.
1146 */
1147 if (tsc_is_invariant) {
1148 printf("\n TSC: P-state invariant");
1149 if (tsc_perf_stat)
1150 printf(", performance statistics");
1151 }
1152 }
1153 #ifdef __i386__
1154 } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1155 printf(" DIR=0x%04x", cyrix_did);
1156 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12);
1157 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8);
1158 #ifndef CYRIX_CACHE_REALLY_WORKS
1159 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
1160 printf("\n CPU cache: write-through mode");
1161 #endif
1162 #endif
1163 }
1164
1165 /* Avoid ugly blank lines: only print newline when we have to. */
1166 if (*cpu_vendor || cpu_id)
1167 printf("\n");
1168
1169 if (bootverbose) {
1170 if (cpu_vendor_id == CPU_VENDOR_AMD ||
1171 cpu_vendor_id == CPU_VENDOR_HYGON)
1172 print_AMD_info();
1173 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
1174 print_INTEL_info();
1175 #ifdef __i386__
1176 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
1177 print_transmeta_info();
1178 #endif
1179 }
1180
1181 print_hypervisor_info();
1182 }
1183
1184 #ifdef __i386__
1185 void
panicifcpuunsupported(void)1186 panicifcpuunsupported(void)
1187 {
1188
1189 #if !defined(lint)
1190 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
1191 #error This kernel is not configured for one of the supported CPUs
1192 #endif
1193 #else /* lint */
1194 #endif /* lint */
1195 /*
1196 * Now that we have told the user what they have,
1197 * let them know if that machine type isn't configured.
1198 */
1199 switch (cpu_class) {
1200 case CPUCLASS_286: /* a 286 should not make it this far, anyway */
1201 case CPUCLASS_386:
1202 #if !defined(I486_CPU)
1203 case CPUCLASS_486:
1204 #endif
1205 #if !defined(I586_CPU)
1206 case CPUCLASS_586:
1207 #endif
1208 #if !defined(I686_CPU)
1209 case CPUCLASS_686:
1210 #endif
1211 panic("CPU class not configured");
1212 default:
1213 break;
1214 }
1215 }
1216
1217 static volatile u_int trap_by_rdmsr;
1218
1219 /*
1220 * Special exception 6 handler.
1221 * The rdmsr instruction generates invalid opcodes fault on 486-class
1222 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the
1223 * function identblue() when this handler is called. Stacked eip should
1224 * be advanced.
1225 */
1226 inthand_t bluetrap6;
1227 __asm
1228 (" \n\
1229 .text \n\
1230 .p2align 2,0x90 \n\
1231 .type " __XSTRING(CNAME(bluetrap6)) ",@function \n\
1232 " __XSTRING(CNAME(bluetrap6)) ": \n\
1233 ss \n\
1234 movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
1235 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
1236 iret \n\
1237 ");
1238
1239 /*
1240 * Special exception 13 handler.
1241 * Accessing non-existent MSR generates general protection fault.
1242 */
1243 inthand_t bluetrap13;
1244 __asm
1245 (" \n\
1246 .text \n\
1247 .p2align 2,0x90 \n\
1248 .type " __XSTRING(CNAME(bluetrap13)) ",@function \n\
1249 " __XSTRING(CNAME(bluetrap13)) ": \n\
1250 ss \n\
1251 movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
1252 popl %eax /* discard error code */ \n\
1253 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
1254 iret \n\
1255 ");
1256
1257 /*
1258 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
1259 * support cpuid instruction. This function should be called after
1260 * loading interrupt descriptor table register.
1261 *
1262 * I don't like this method that handles fault, but I couldn't get
1263 * information for any other methods. Does blue giant know?
1264 */
1265 static int
identblue(void)1266 identblue(void)
1267 {
1268
1269 trap_by_rdmsr = 0;
1270
1271 /*
1272 * Cyrix 486-class CPU does not support rdmsr instruction.
1273 * The rdmsr instruction generates invalid opcode fault, and exception
1274 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The
1275 * bluetrap6() set the magic number to trap_by_rdmsr.
1276 */
1277 setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
1278 GSEL(GCODE_SEL, SEL_KPL));
1279
1280 /*
1281 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
1282 * In this case, rdmsr generates general protection fault, and
1283 * exception will be trapped by bluetrap13().
1284 */
1285 setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
1286 GSEL(GCODE_SEL, SEL_KPL));
1287
1288 rdmsr(0x1002); /* Cyrix CPU generates fault. */
1289
1290 if (trap_by_rdmsr == 0xa8c1d)
1291 return IDENTBLUE_CYRIX486;
1292 else if (trap_by_rdmsr == 0xa89c4)
1293 return IDENTBLUE_CYRIXM2;
1294 return IDENTBLUE_IBMCPU;
1295 }
1296
1297 /*
1298 * identifycyrix() set lower 16 bits of cyrix_did as follows:
1299 *
1300 * F E D C B A 9 8 7 6 5 4 3 2 1 0
1301 * +-------+-------+---------------+
1302 * | SID | RID | Device ID |
1303 * | (DIR 1) | (DIR 0) |
1304 * +-------+-------+---------------+
1305 */
1306 static void
identifycyrix(void)1307 identifycyrix(void)
1308 {
1309 register_t saveintr;
1310 int ccr2_test = 0, dir_test = 0;
1311 u_char ccr2, ccr3;
1312
1313 saveintr = intr_disable();
1314
1315 ccr2 = read_cyrix_reg(CCR2);
1316 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
1317 read_cyrix_reg(CCR2);
1318 if (read_cyrix_reg(CCR2) != ccr2)
1319 ccr2_test = 1;
1320 write_cyrix_reg(CCR2, ccr2);
1321
1322 ccr3 = read_cyrix_reg(CCR3);
1323 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
1324 read_cyrix_reg(CCR3);
1325 if (read_cyrix_reg(CCR3) != ccr3)
1326 dir_test = 1; /* CPU supports DIRs. */
1327 write_cyrix_reg(CCR3, ccr3);
1328
1329 if (dir_test) {
1330 /* Device ID registers are available. */
1331 cyrix_did = read_cyrix_reg(DIR1) << 8;
1332 cyrix_did += read_cyrix_reg(DIR0);
1333 } else if (ccr2_test)
1334 cyrix_did = 0x0010; /* 486S A-step */
1335 else
1336 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */
1337
1338 intr_restore(saveintr);
1339 }
1340 #endif
1341
1342 /* Update TSC freq with the value indicated by the caller. */
1343 static void
tsc_freq_changed(void * arg __unused,const struct cf_level * level,int status)1344 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status)
1345 {
1346
1347 /* If there was an error during the transition, don't do anything. */
1348 if (status != 0)
1349 return;
1350
1351 /* Total setting for this level gives the new frequency in MHz. */
1352 hw_clockrate = level->total_set.freq;
1353 }
1354
1355 static void
hook_tsc_freq(void * arg __unused)1356 hook_tsc_freq(void *arg __unused)
1357 {
1358
1359 if (tsc_is_invariant)
1360 return;
1361
1362 tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change,
1363 tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY);
1364 }
1365
1366 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL);
1367
1368 static struct {
1369 const char *vm_cpuid;
1370 int vm_guest;
1371 } vm_cpuids[] = {
1372 { "XenVMMXenVMM", VM_GUEST_XEN }, /* XEN */
1373 { "Microsoft Hv", VM_GUEST_HV }, /* Microsoft Hyper-V */
1374 { "VMwareVMware", VM_GUEST_VMWARE }, /* VMware VM */
1375 { "KVMKVMKVM", VM_GUEST_KVM }, /* KVM */
1376 { "bhyve bhyve ", VM_GUEST_BHYVE }, /* bhyve */
1377 { "VBoxVBoxVBox", VM_GUEST_VBOX }, /* VirtualBox */
1378 { "___ NVMM ___", VM_GUEST_NVMM }, /* NVMM */
1379 };
1380
1381 static void
identify_hypervisor_cpuid_base(void)1382 identify_hypervisor_cpuid_base(void)
1383 {
1384 u_int leaf, regs[4];
1385 int i;
1386
1387 /*
1388 * [RFC] CPUID usage for interaction between Hypervisors and Linux.
1389 * http://lkml.org/lkml/2008/10/1/246
1390 *
1391 * KB1009458: Mechanisms to determine if software is running in
1392 * a VMware virtual machine
1393 * http://kb.vmware.com/kb/1009458
1394 *
1395 * Search for a hypervisor that we recognize. If we cannot find
1396 * a specific hypervisor, return the first information about the
1397 * hypervisor that we found, as others may be able to use.
1398 */
1399 for (leaf = 0x40000000; leaf < 0x40010000; leaf += 0x100) {
1400 do_cpuid(leaf, regs);
1401
1402 /*
1403 * KVM from Linux kernels prior to commit
1404 * 57c22e5f35aa4b9b2fe11f73f3e62bbf9ef36190 set %eax
1405 * to 0 rather than a valid hv_high value. Check for
1406 * the KVM signature bytes and fixup %eax to the
1407 * highest supported leaf in that case.
1408 */
1409 if (regs[0] == 0 && regs[1] == 0x4b4d564b &&
1410 regs[2] == 0x564b4d56 && regs[3] == 0x0000004d)
1411 regs[0] = leaf + 1;
1412
1413 if (regs[0] >= leaf) {
1414 for (i = 0; i < nitems(vm_cpuids); i++)
1415 if (strncmp((const char *)®s[1],
1416 vm_cpuids[i].vm_cpuid, 12) == 0) {
1417 vm_guest = vm_cpuids[i].vm_guest;
1418 break;
1419 }
1420
1421 /*
1422 * If this is the first entry or we found a
1423 * specific hypervisor, record the base, high value,
1424 * and vendor identifier.
1425 */
1426 if (vm_guest != VM_GUEST_VM || leaf == 0x40000000) {
1427 hv_base = leaf;
1428 hv_high = regs[0];
1429 ((u_int *)&hv_vendor)[0] = regs[1];
1430 ((u_int *)&hv_vendor)[1] = regs[2];
1431 ((u_int *)&hv_vendor)[2] = regs[3];
1432 hv_vendor[12] = '\0';
1433
1434 /*
1435 * If we found a specific hypervisor, then
1436 * we are finished.
1437 */
1438 if (vm_guest != VM_GUEST_VM)
1439 return;
1440 }
1441 }
1442 }
1443 }
1444
1445 void
identify_hypervisor(void)1446 identify_hypervisor(void)
1447 {
1448 u_int regs[4];
1449 char *p;
1450
1451 TSENTER();
1452 /*
1453 * If CPUID2_HV is set, we are running in a hypervisor environment.
1454 */
1455 if (cpu_feature2 & CPUID2_HV) {
1456 vm_guest = VM_GUEST_VM;
1457 identify_hypervisor_cpuid_base();
1458
1459 /* If we have a definitive vendor, we can return now. */
1460 if (*hv_vendor != '\0') {
1461 TSEXIT();
1462 return;
1463 }
1464 }
1465
1466 /*
1467 * Examine SMBIOS strings for older hypervisors.
1468 */
1469 p = kern_getenv("smbios.system.serial");
1470 if (p != NULL) {
1471 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) {
1472 vmware_hvcall(VMW_HVCMD_GETVERSION, regs);
1473 if (regs[1] == VMW_HVMAGIC) {
1474 vm_guest = VM_GUEST_VMWARE;
1475 freeenv(p);
1476 TSEXIT();
1477 return;
1478 }
1479 }
1480 freeenv(p);
1481 }
1482 TSEXIT();
1483 }
1484
1485 bool
fix_cpuid(void)1486 fix_cpuid(void)
1487 {
1488 uint64_t msr;
1489
1490 /*
1491 * Clear "Limit CPUID Maxval" bit and return true if the caller should
1492 * get the largest standard CPUID function number again if it is set
1493 * from BIOS. It is necessary for probing correct CPU topology later
1494 * and for the correct operation of the AVX-aware userspace.
1495 */
1496 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
1497 ((CPUID_TO_FAMILY(cpu_id) == 0xf &&
1498 CPUID_TO_MODEL(cpu_id) >= 0x3) ||
1499 (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1500 CPUID_TO_MODEL(cpu_id) >= 0xe))) {
1501 msr = rdmsr(MSR_IA32_MISC_ENABLE);
1502 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) {
1503 msr &= ~IA32_MISC_EN_LIMCPUID;
1504 wrmsr(MSR_IA32_MISC_ENABLE, msr);
1505 return (true);
1506 }
1507 }
1508
1509 /*
1510 * Re-enable AMD Topology Extension that could be disabled by BIOS
1511 * on some notebook processors. Without the extension it's really
1512 * hard to determine the correct CPU cache topology.
1513 * See BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h
1514 * Models 60h-6Fh Processors, Publication # 50742.
1515 */
1516 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_AMD &&
1517 CPUID_TO_FAMILY(cpu_id) == 0x15) {
1518 msr = rdmsr(MSR_EXTFEATURES);
1519 if ((msr & ((uint64_t)1 << 54)) == 0) {
1520 msr |= (uint64_t)1 << 54;
1521 wrmsr(MSR_EXTFEATURES, msr);
1522 return (true);
1523 }
1524 }
1525 return (false);
1526 }
1527
1528 void
identify_cpu1(void)1529 identify_cpu1(void)
1530 {
1531 u_int regs[4];
1532
1533 do_cpuid(0, regs);
1534 cpu_high = regs[0];
1535 ((u_int *)&cpu_vendor)[0] = regs[1];
1536 ((u_int *)&cpu_vendor)[1] = regs[3];
1537 ((u_int *)&cpu_vendor)[2] = regs[2];
1538 cpu_vendor[12] = '\0';
1539
1540 do_cpuid(1, regs);
1541 cpu_id = regs[0];
1542 cpu_procinfo = regs[1];
1543 cpu_feature = regs[3];
1544 cpu_feature2 = regs[2];
1545 }
1546
1547 void
identify_cpu2(void)1548 identify_cpu2(void)
1549 {
1550 u_int regs[4], cpu_stdext_disable, max_eax_l7;
1551
1552 if (cpu_high >= 6) {
1553 cpuid_count(6, 0, regs);
1554 cpu_power_eax = regs[0];
1555 cpu_power_ebx = regs[1];
1556 cpu_power_ecx = regs[2];
1557 cpu_power_edx = regs[3];
1558 }
1559
1560 if (cpu_high >= 7) {
1561 cpuid_count(7, 0, regs);
1562 cpu_stdext_feature = regs[1];
1563 max_eax_l7 = regs[0];
1564
1565 /*
1566 * Some hypervisors failed to filter out unsupported
1567 * extended features. Allow to disable the
1568 * extensions, activation of which requires setting a
1569 * bit in CR4, and which VM monitors do not support.
1570 */
1571 cpu_stdext_disable = 0;
1572 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable);
1573 cpu_stdext_feature &= ~cpu_stdext_disable;
1574
1575 cpu_stdext_feature2 = regs[2];
1576 cpu_stdext_feature3 = regs[3];
1577
1578 if ((cpu_stdext_feature3 & CPUID_STDEXT3_ARCH_CAP) != 0)
1579 cpu_ia32_arch_caps = rdmsr(MSR_IA32_ARCH_CAP);
1580
1581 if (max_eax_l7 >= 1) {
1582 cpuid_count(7, 1, regs);
1583 cpu_stdext_feature4 = regs[0];
1584 }
1585 }
1586 }
1587
1588 void
identify_cpu_ext_features(void)1589 identify_cpu_ext_features(void)
1590 {
1591 u_int regs[4];
1592
1593 if (cpu_high >= 7) {
1594 cpuid_count(7, 0, regs);
1595 cpu_stdext_feature2 = regs[2];
1596 cpu_stdext_feature3 = regs[3];
1597 }
1598 }
1599
1600 void
identify_cpu_fixup_bsp(void)1601 identify_cpu_fixup_bsp(void)
1602 {
1603 u_int regs[4];
1604
1605 cpu_vendor_id = find_cpu_vendor_id();
1606
1607 if (fix_cpuid()) {
1608 do_cpuid(0, regs);
1609 cpu_high = regs[0];
1610 }
1611 }
1612
1613 /*
1614 * Final stage of CPU identification.
1615 */
1616 void
finishidentcpu(void)1617 finishidentcpu(void)
1618 {
1619 u_int regs[4];
1620 #ifdef __i386__
1621 u_char ccr3;
1622 #endif
1623
1624 identify_cpu_fixup_bsp();
1625
1626 if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) {
1627 do_cpuid(5, regs);
1628 cpu_mon_mwait_flags = regs[2];
1629 cpu_mon_mwait_edx = regs[3];
1630 cpu_mon_min_size = regs[0] & CPUID5_MON_MIN_SIZE;
1631 cpu_mon_max_size = regs[1] & CPUID5_MON_MAX_SIZE;
1632 }
1633
1634 identify_cpu2();
1635
1636 #ifdef __i386__
1637 if (cpu_high > 0 &&
1638 (cpu_vendor_id == CPU_VENDOR_INTEL ||
1639 cpu_vendor_id == CPU_VENDOR_AMD ||
1640 cpu_vendor_id == CPU_VENDOR_HYGON ||
1641 cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
1642 cpu_vendor_id == CPU_VENDOR_CENTAUR ||
1643 cpu_vendor_id == CPU_VENDOR_NSC)) {
1644 do_cpuid(0x80000000, regs);
1645 if (regs[0] >= 0x80000000)
1646 cpu_exthigh = regs[0];
1647 }
1648 #else
1649 if (cpu_vendor_id == CPU_VENDOR_INTEL ||
1650 cpu_vendor_id == CPU_VENDOR_AMD ||
1651 cpu_vendor_id == CPU_VENDOR_HYGON ||
1652 cpu_vendor_id == CPU_VENDOR_CENTAUR) {
1653 do_cpuid(0x80000000, regs);
1654 cpu_exthigh = regs[0];
1655 }
1656 #endif
1657 if (cpu_exthigh >= 0x80000001) {
1658 do_cpuid(0x80000001, regs);
1659 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
1660 amd_feature2 = regs[2];
1661 }
1662 if (cpu_exthigh >= 0x80000007) {
1663 do_cpuid(0x80000007, regs);
1664 amd_rascap = regs[1];
1665 amd_pminfo = regs[3];
1666 }
1667 if (cpu_exthigh >= 0x80000008) {
1668 do_cpuid(0x80000008, regs);
1669 cpu_maxphyaddr = regs[0] & 0xff;
1670 amd_extended_feature_extensions = regs[1];
1671 cpu_procinfo2 = regs[2];
1672 cpu_procinfo3 = regs[3];
1673 } else {
1674 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32;
1675 }
1676
1677 #ifdef __i386__
1678 if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1679 if (cpu == CPU_486) {
1680 /*
1681 * These conditions are equivalent to:
1682 * - CPU does not support cpuid instruction.
1683 * - Cyrix/IBM CPU is detected.
1684 */
1685 if (identblue() == IDENTBLUE_IBMCPU) {
1686 strcpy(cpu_vendor, "IBM");
1687 cpu_vendor_id = CPU_VENDOR_IBM;
1688 cpu = CPU_BLUE;
1689 return;
1690 }
1691 }
1692 switch (cpu_id & 0xf00) {
1693 case 0x600:
1694 /*
1695 * Cyrix's datasheet does not describe DIRs.
1696 * Therefor, I assume it does not have them
1697 * and use the result of the cpuid instruction.
1698 * XXX they seem to have it for now at least. -Peter
1699 */
1700 identifycyrix();
1701 cpu = CPU_M2;
1702 break;
1703 default:
1704 identifycyrix();
1705 /*
1706 * This routine contains a trick.
1707 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
1708 */
1709 switch (cyrix_did & 0x00f0) {
1710 case 0x00:
1711 case 0xf0:
1712 cpu = CPU_486DLC;
1713 break;
1714 case 0x10:
1715 cpu = CPU_CY486DX;
1716 break;
1717 case 0x20:
1718 if ((cyrix_did & 0x000f) < 8)
1719 cpu = CPU_M1;
1720 else
1721 cpu = CPU_M1SC;
1722 break;
1723 case 0x30:
1724 cpu = CPU_M1;
1725 break;
1726 case 0x40:
1727 /* MediaGX CPU */
1728 cpu = CPU_M1SC;
1729 break;
1730 default:
1731 /* M2 and later CPUs are treated as M2. */
1732 cpu = CPU_M2;
1733
1734 /*
1735 * enable cpuid instruction.
1736 */
1737 ccr3 = read_cyrix_reg(CCR3);
1738 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1739 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1740 write_cyrix_reg(CCR3, ccr3);
1741
1742 do_cpuid(0, regs);
1743 cpu_high = regs[0]; /* eax */
1744 do_cpuid(1, regs);
1745 cpu_id = regs[0]; /* eax */
1746 cpu_feature = regs[3]; /* edx */
1747 break;
1748 }
1749 }
1750 } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1751 /*
1752 * There are BlueLightning CPUs that do not change
1753 * undefined flags by dividing 5 by 2. In this case,
1754 * the CPU identification routine in locore.s leaves
1755 * cpu_vendor null string and puts CPU_486 into the
1756 * cpu.
1757 */
1758 if (identblue() == IDENTBLUE_IBMCPU) {
1759 strcpy(cpu_vendor, "IBM");
1760 cpu_vendor_id = CPU_VENDOR_IBM;
1761 cpu = CPU_BLUE;
1762 return;
1763 }
1764 }
1765 #endif
1766 }
1767
1768 int
pti_get_default(void)1769 pti_get_default(void)
1770 {
1771
1772 if (strcmp(cpu_vendor, AMD_VENDOR_ID) == 0 ||
1773 strcmp(cpu_vendor, HYGON_VENDOR_ID) == 0)
1774 return (0);
1775 if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_RDCL_NO) != 0)
1776 return (0);
1777 return (1);
1778 }
1779
1780 static u_int
find_cpu_vendor_id(void)1781 find_cpu_vendor_id(void)
1782 {
1783 int i;
1784
1785 for (i = 0; i < nitems(cpu_vendors); i++)
1786 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
1787 return (cpu_vendors[i].vendor_id);
1788 return (0);
1789 }
1790
1791 static void
print_AMD_assoc(int i)1792 print_AMD_assoc(int i)
1793 {
1794 if (i == 255)
1795 printf(", fully associative\n");
1796 else
1797 printf(", %d-way associative\n", i);
1798 }
1799
1800 static void
print_AMD_l2_assoc(int i)1801 print_AMD_l2_assoc(int i)
1802 {
1803 switch (i & 0x0f) {
1804 case 0: printf(", disabled/not present\n"); break;
1805 case 1: printf(", direct mapped\n"); break;
1806 case 2: printf(", 2-way associative\n"); break;
1807 case 4: printf(", 4-way associative\n"); break;
1808 case 6: printf(", 8-way associative\n"); break;
1809 case 8: printf(", 16-way associative\n"); break;
1810 case 15: printf(", fully associative\n"); break;
1811 default: printf(", reserved configuration\n"); break;
1812 }
1813 }
1814
1815 static void
print_AMD_info(void)1816 print_AMD_info(void)
1817 {
1818 #ifdef __i386__
1819 uint64_t amd_whcr;
1820 #endif
1821 u_int regs[4];
1822
1823 if (cpu_exthigh >= 0x80000005) {
1824 do_cpuid(0x80000005, regs);
1825 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
1826 print_AMD_assoc(regs[0] >> 24);
1827
1828 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
1829 print_AMD_assoc((regs[0] >> 8) & 0xff);
1830
1831 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
1832 print_AMD_assoc(regs[1] >> 24);
1833
1834 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
1835 print_AMD_assoc((regs[1] >> 8) & 0xff);
1836
1837 printf("L1 data cache: %d kbytes", regs[2] >> 24);
1838 printf(", %d bytes/line", regs[2] & 0xff);
1839 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1840 print_AMD_assoc((regs[2] >> 16) & 0xff);
1841
1842 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1843 printf(", %d bytes/line", regs[3] & 0xff);
1844 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1845 print_AMD_assoc((regs[3] >> 16) & 0xff);
1846 }
1847
1848 if (cpu_exthigh >= 0x80000006) {
1849 do_cpuid(0x80000006, regs);
1850 if ((regs[0] >> 16) != 0) {
1851 printf("L2 2MB data TLB: %d entries",
1852 (regs[0] >> 16) & 0xfff);
1853 print_AMD_l2_assoc(regs[0] >> 28);
1854 printf("L2 2MB instruction TLB: %d entries",
1855 regs[0] & 0xfff);
1856 print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1857 } else {
1858 printf("L2 2MB unified TLB: %d entries",
1859 regs[0] & 0xfff);
1860 print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1861 }
1862 if ((regs[1] >> 16) != 0) {
1863 printf("L2 4KB data TLB: %d entries",
1864 (regs[1] >> 16) & 0xfff);
1865 print_AMD_l2_assoc(regs[1] >> 28);
1866
1867 printf("L2 4KB instruction TLB: %d entries",
1868 (regs[1] >> 16) & 0xfff);
1869 print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1870 } else {
1871 printf("L2 4KB unified TLB: %d entries",
1872 (regs[1] >> 16) & 0xfff);
1873 print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1874 }
1875 printf("L2 unified cache: %d kbytes", regs[2] >> 16);
1876 printf(", %d bytes/line", regs[2] & 0xff);
1877 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1878 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
1879 }
1880
1881 #ifdef __i386__
1882 if (((cpu_id & 0xf00) == 0x500)
1883 && (((cpu_id & 0x0f0) > 0x80)
1884 || (((cpu_id & 0x0f0) == 0x80)
1885 && (cpu_id & 0x00f) > 0x07))) {
1886 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1887 amd_whcr = rdmsr(0xc0000082);
1888 if (!(amd_whcr & (0x3ff << 22))) {
1889 printf("Write Allocate Disable\n");
1890 } else {
1891 printf("Write Allocate Enable Limit: %dM bytes\n",
1892 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1893 printf("Write Allocate 15-16M bytes: %s\n",
1894 (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1895 }
1896 } else if (((cpu_id & 0xf00) == 0x500)
1897 && ((cpu_id & 0x0f0) > 0x50)) {
1898 /* K6, K6-2(old core) */
1899 amd_whcr = rdmsr(0xc0000082);
1900 if (!(amd_whcr & (0x7f << 1))) {
1901 printf("Write Allocate Disable\n");
1902 } else {
1903 printf("Write Allocate Enable Limit: %dM bytes\n",
1904 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1905 printf("Write Allocate 15-16M bytes: %s\n",
1906 (amd_whcr & 0x0001) ? "Enable" : "Disable");
1907 printf("Hardware Write Allocate Control: %s\n",
1908 (amd_whcr & 0x0100) ? "Enable" : "Disable");
1909 }
1910 }
1911 #endif
1912 /*
1913 * Opteron Rev E shows a bug as in very rare occasions a read memory
1914 * barrier is not performed as expected if it is followed by a
1915 * non-atomic read-modify-write instruction.
1916 * As long as that bug pops up very rarely (intensive machine usage
1917 * on other operating systems generally generates one unexplainable
1918 * crash any 2 months) and as long as a model specific fix would be
1919 * impractical at this stage, print out a warning string if the broken
1920 * model and family are identified.
1921 */
1922 if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
1923 CPUID_TO_MODEL(cpu_id) <= 0x3f)
1924 printf("WARNING: This architecture revision has known SMP "
1925 "hardware bugs which may cause random instability\n");
1926 }
1927
1928 static void
print_INTEL_info(void)1929 print_INTEL_info(void)
1930 {
1931 u_int regs[4];
1932 u_int rounds, regnum;
1933 u_int nwaycode, nway;
1934
1935 if (cpu_high >= 2) {
1936 rounds = 0;
1937 do {
1938 do_cpuid(0x2, regs);
1939 if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1940 break; /* we have a buggy CPU */
1941
1942 for (regnum = 0; regnum <= 3; ++regnum) {
1943 if (regs[regnum] & (1<<31))
1944 continue;
1945 if (regnum != 0)
1946 print_INTEL_TLB(regs[regnum] & 0xff);
1947 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
1948 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
1949 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
1950 }
1951 } while (--rounds > 0);
1952 }
1953
1954 if (cpu_exthigh >= 0x80000006) {
1955 do_cpuid(0x80000006, regs);
1956 nwaycode = (regs[2] >> 12) & 0x0f;
1957 if (nwaycode >= 0x02 && nwaycode <= 0x08)
1958 nway = 1 << (nwaycode / 2);
1959 else
1960 nway = 0;
1961 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n",
1962 (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
1963 }
1964 }
1965
1966 static void
print_INTEL_TLB(u_int data)1967 print_INTEL_TLB(u_int data)
1968 {
1969 switch (data) {
1970 case 0x0:
1971 case 0x40:
1972 default:
1973 break;
1974 case 0x1:
1975 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n");
1976 break;
1977 case 0x2:
1978 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n");
1979 break;
1980 case 0x3:
1981 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n");
1982 break;
1983 case 0x4:
1984 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n");
1985 break;
1986 case 0x6:
1987 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n");
1988 break;
1989 case 0x8:
1990 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n");
1991 break;
1992 case 0x9:
1993 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n");
1994 break;
1995 case 0xa:
1996 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n");
1997 break;
1998 case 0xb:
1999 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n");
2000 break;
2001 case 0xc:
2002 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n");
2003 break;
2004 case 0xd:
2005 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size");
2006 break;
2007 case 0xe:
2008 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n");
2009 break;
2010 case 0x1d:
2011 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n");
2012 break;
2013 case 0x21:
2014 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n");
2015 break;
2016 case 0x22:
2017 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2018 break;
2019 case 0x23:
2020 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2021 break;
2022 case 0x24:
2023 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n");
2024 break;
2025 case 0x25:
2026 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2027 break;
2028 case 0x29:
2029 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2030 break;
2031 case 0x2c:
2032 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n");
2033 break;
2034 case 0x30:
2035 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n");
2036 break;
2037 case 0x39: /* De-listed in SDM rev. 54 */
2038 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2039 break;
2040 case 0x3b: /* De-listed in SDM rev. 54 */
2041 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n");
2042 break;
2043 case 0x3c: /* De-listed in SDM rev. 54 */
2044 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2045 break;
2046 case 0x41:
2047 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n");
2048 break;
2049 case 0x42:
2050 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n");
2051 break;
2052 case 0x43:
2053 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n");
2054 break;
2055 case 0x44:
2056 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n");
2057 break;
2058 case 0x45:
2059 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n");
2060 break;
2061 case 0x46:
2062 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n");
2063 break;
2064 case 0x47:
2065 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n");
2066 break;
2067 case 0x48:
2068 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n");
2069 break;
2070 case 0x49:
2071 if (CPUID_TO_FAMILY(cpu_id) == 0xf &&
2072 CPUID_TO_MODEL(cpu_id) == 0x6)
2073 printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n");
2074 else
2075 printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size");
2076 break;
2077 case 0x4a:
2078 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n");
2079 break;
2080 case 0x4b:
2081 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n");
2082 break;
2083 case 0x4c:
2084 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n");
2085 break;
2086 case 0x4d:
2087 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n");
2088 break;
2089 case 0x4e:
2090 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n");
2091 break;
2092 case 0x4f:
2093 printf("Instruction TLB: 4 KByte pages, 32 entries\n");
2094 break;
2095 case 0x50:
2096 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n");
2097 break;
2098 case 0x51:
2099 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n");
2100 break;
2101 case 0x52:
2102 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n");
2103 break;
2104 case 0x55:
2105 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n");
2106 break;
2107 case 0x56:
2108 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n");
2109 break;
2110 case 0x57:
2111 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n");
2112 break;
2113 case 0x59:
2114 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n");
2115 break;
2116 case 0x5a:
2117 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n");
2118 break;
2119 case 0x5b:
2120 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n");
2121 break;
2122 case 0x5c:
2123 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n");
2124 break;
2125 case 0x5d:
2126 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n");
2127 break;
2128 case 0x60:
2129 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2130 break;
2131 case 0x61:
2132 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n");
2133 break;
2134 case 0x63:
2135 printf("Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries\n");
2136 break;
2137 case 0x64:
2138 printf("Data TLB: 4 KBytes pages, 4-way set associative, 512 entries\n");
2139 break;
2140 case 0x66:
2141 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2142 break;
2143 case 0x67:
2144 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2145 break;
2146 case 0x68:
2147 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n");
2148 break;
2149 case 0x6a:
2150 printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n");
2151 break;
2152 case 0x6b:
2153 printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n");
2154 break;
2155 case 0x6c:
2156 printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n");
2157 break;
2158 case 0x6d:
2159 printf("DTLB: 1 GByte pages, fully associative, 16 entries\n");
2160 break;
2161 case 0x70:
2162 printf("Trace cache: 12K-uops, 8-way set associative\n");
2163 break;
2164 case 0x71:
2165 printf("Trace cache: 16K-uops, 8-way set associative\n");
2166 break;
2167 case 0x72:
2168 printf("Trace cache: 32K-uops, 8-way set associative\n");
2169 break;
2170 case 0x76:
2171 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n");
2172 break;
2173 case 0x78:
2174 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n");
2175 break;
2176 case 0x79:
2177 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2178 break;
2179 case 0x7a:
2180 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2181 break;
2182 case 0x7b:
2183 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2184 break;
2185 case 0x7c:
2186 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2187 break;
2188 case 0x7d:
2189 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n");
2190 break;
2191 case 0x7f:
2192 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n");
2193 break;
2194 case 0x80:
2195 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n");
2196 break;
2197 case 0x82:
2198 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n");
2199 break;
2200 case 0x83:
2201 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n");
2202 break;
2203 case 0x84:
2204 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n");
2205 break;
2206 case 0x85:
2207 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n");
2208 break;
2209 case 0x86:
2210 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n");
2211 break;
2212 case 0x87:
2213 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n");
2214 break;
2215 case 0xa0:
2216 printf("DTLB: 4k pages, fully associative, 32 entries\n");
2217 break;
2218 case 0xb0:
2219 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2220 break;
2221 case 0xb1:
2222 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n");
2223 break;
2224 case 0xb2:
2225 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n");
2226 break;
2227 case 0xb3:
2228 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2229 break;
2230 case 0xb4:
2231 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n");
2232 break;
2233 case 0xb5:
2234 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n");
2235 break;
2236 case 0xb6:
2237 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n");
2238 break;
2239 case 0xba:
2240 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n");
2241 break;
2242 case 0xc0:
2243 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n");
2244 break;
2245 case 0xc1:
2246 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n");
2247 break;
2248 case 0xc2:
2249 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n");
2250 break;
2251 case 0xc3:
2252 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n");
2253 break;
2254 case 0xc4:
2255 printf("DTLB: 2M/4M Byte pages, 4-way associative, 32 entries\n");
2256 break;
2257 case 0xca:
2258 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n");
2259 break;
2260 case 0xd0:
2261 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n");
2262 break;
2263 case 0xd1:
2264 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n");
2265 break;
2266 case 0xd2:
2267 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n");
2268 break;
2269 case 0xd6:
2270 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n");
2271 break;
2272 case 0xd7:
2273 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n");
2274 break;
2275 case 0xd8:
2276 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n");
2277 break;
2278 case 0xdc:
2279 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n");
2280 break;
2281 case 0xdd:
2282 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n");
2283 break;
2284 case 0xde:
2285 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n");
2286 break;
2287 case 0xe2:
2288 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n");
2289 break;
2290 case 0xe3:
2291 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n");
2292 break;
2293 case 0xe4:
2294 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n");
2295 break;
2296 case 0xea:
2297 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n");
2298 break;
2299 case 0xeb:
2300 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n");
2301 break;
2302 case 0xec:
2303 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n");
2304 break;
2305 case 0xf0:
2306 printf("64-Byte prefetching\n");
2307 break;
2308 case 0xf1:
2309 printf("128-Byte prefetching\n");
2310 break;
2311 }
2312 }
2313
2314 static void
print_svm_info(void)2315 print_svm_info(void)
2316 {
2317 u_int features, regs[4];
2318 uint64_t msr;
2319 int comma;
2320
2321 printf("\n SVM: ");
2322 do_cpuid(0x8000000A, regs);
2323 features = regs[3];
2324
2325 msr = rdmsr(MSR_VM_CR);
2326 if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS)
2327 printf("(disabled in BIOS) ");
2328
2329 if (!bootverbose) {
2330 comma = 0;
2331 if (features & (1 << 0)) {
2332 printf("%sNP", comma ? "," : "");
2333 comma = 1;
2334 }
2335 if (features & (1 << 3)) {
2336 printf("%sNRIP", comma ? "," : "");
2337 comma = 1;
2338 }
2339 if (features & (1 << 5)) {
2340 printf("%sVClean", comma ? "," : "");
2341 comma = 1;
2342 }
2343 if (features & (1 << 6)) {
2344 printf("%sAFlush", comma ? "," : "");
2345 comma = 1;
2346 }
2347 if (features & (1 << 7)) {
2348 printf("%sDAssist", comma ? "," : "");
2349 comma = 1;
2350 }
2351 printf("%sNAsids=%d", comma ? "," : "", regs[1]);
2352 return;
2353 }
2354
2355 printf("Features=0x%b", features,
2356 "\020"
2357 "\001NP" /* Nested paging */
2358 "\002LbrVirt" /* LBR virtualization */
2359 "\003SVML" /* SVM lock */
2360 "\004NRIPS" /* NRIP save */
2361 "\005TscRateMsr" /* MSR based TSC rate control */
2362 "\006VmcbClean" /* VMCB clean bits */
2363 "\007FlushByAsid" /* Flush by ASID */
2364 "\010DecodeAssist" /* Decode assist */
2365 "\011<b8>"
2366 "\012<b9>"
2367 "\013PauseFilter" /* PAUSE intercept filter */
2368 "\014EncryptedMcodePatch"
2369 "\015PauseFilterThreshold" /* PAUSE filter threshold */
2370 "\016AVIC" /* virtual interrupt controller */
2371 "\017<b14>"
2372 "\020V_VMSAVE_VMLOAD"
2373 "\021vGIF"
2374 "\022GMET" /* Guest Mode Execute Trap */
2375 "\023<b18>"
2376 "\024<b19>"
2377 "\025GuesSpecCtl" /* Guest Spec_ctl */
2378 "\026<b21>"
2379 "\027<b22>"
2380 "\030<b23>"
2381 "\031<b24>"
2382 "\032<b25>"
2383 "\033<b26>"
2384 "\034<b27>"
2385 "\035<b28>"
2386 "\036<b29>"
2387 "\037<b30>"
2388 "\040<b31>"
2389 );
2390 printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]);
2391 }
2392
2393 #ifdef __i386__
2394 static void
print_transmeta_info(void)2395 print_transmeta_info(void)
2396 {
2397 u_int regs[4], nreg = 0;
2398
2399 do_cpuid(0x80860000, regs);
2400 nreg = regs[0];
2401 if (nreg >= 0x80860001) {
2402 do_cpuid(0x80860001, regs);
2403 printf(" Processor revision %u.%u.%u.%u\n",
2404 (regs[1] >> 24) & 0xff,
2405 (regs[1] >> 16) & 0xff,
2406 (regs[1] >> 8) & 0xff,
2407 regs[1] & 0xff);
2408 }
2409 if (nreg >= 0x80860002) {
2410 do_cpuid(0x80860002, regs);
2411 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n",
2412 (regs[1] >> 24) & 0xff,
2413 (regs[1] >> 16) & 0xff,
2414 (regs[1] >> 8) & 0xff,
2415 regs[1] & 0xff,
2416 regs[2]);
2417 }
2418 if (nreg >= 0x80860006) {
2419 char info[65];
2420 do_cpuid(0x80860003, (u_int*) &info[0]);
2421 do_cpuid(0x80860004, (u_int*) &info[16]);
2422 do_cpuid(0x80860005, (u_int*) &info[32]);
2423 do_cpuid(0x80860006, (u_int*) &info[48]);
2424 info[64] = 0;
2425 printf(" %s\n", info);
2426 }
2427 }
2428 #endif
2429
2430 static void
print_via_padlock_info(void)2431 print_via_padlock_info(void)
2432 {
2433 u_int regs[4];
2434
2435 do_cpuid(0xc0000001, regs);
2436 printf("\n VIA Padlock Features=0x%b", regs[3],
2437 "\020"
2438 "\003RNG" /* RNG */
2439 "\007AES" /* ACE */
2440 "\011AES-CTR" /* ACE2 */
2441 "\013SHA1,SHA256" /* PHE */
2442 "\015RSA" /* PMM */
2443 );
2444 }
2445
2446 static uint32_t
vmx_settable(uint64_t basic,int msr,int true_msr)2447 vmx_settable(uint64_t basic, int msr, int true_msr)
2448 {
2449 uint64_t val;
2450
2451 if (basic & (1ULL << 55))
2452 val = rdmsr(true_msr);
2453 else
2454 val = rdmsr(msr);
2455
2456 /* Just report the controls that can be set to 1. */
2457 return (val >> 32);
2458 }
2459
2460 static void
print_vmx_info(void)2461 print_vmx_info(void)
2462 {
2463 uint64_t basic, msr;
2464 uint32_t entry, exit, mask, pin, proc, proc2;
2465 int comma;
2466
2467 printf("\n VT-x: ");
2468 msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
2469 if (!(msr & IA32_FEATURE_CONTROL_VMX_EN))
2470 printf("(disabled in BIOS) ");
2471 basic = rdmsr(MSR_VMX_BASIC);
2472 pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS,
2473 MSR_VMX_TRUE_PINBASED_CTLS);
2474 proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS,
2475 MSR_VMX_TRUE_PROCBASED_CTLS);
2476 if (proc & PROCBASED_SECONDARY_CONTROLS)
2477 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2,
2478 MSR_VMX_PROCBASED_CTLS2);
2479 else
2480 proc2 = 0;
2481 exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS);
2482 entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS);
2483
2484 if (!bootverbose) {
2485 comma = 0;
2486 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT &&
2487 entry & VM_ENTRY_LOAD_PAT) {
2488 printf("%sPAT", comma ? "," : "");
2489 comma = 1;
2490 }
2491 if (proc & PROCBASED_HLT_EXITING) {
2492 printf("%sHLT", comma ? "," : "");
2493 comma = 1;
2494 }
2495 if (proc & PROCBASED_MTF) {
2496 printf("%sMTF", comma ? "," : "");
2497 comma = 1;
2498 }
2499 if (proc & PROCBASED_PAUSE_EXITING) {
2500 printf("%sPAUSE", comma ? "," : "");
2501 comma = 1;
2502 }
2503 if (proc2 & PROCBASED2_ENABLE_EPT) {
2504 printf("%sEPT", comma ? "," : "");
2505 comma = 1;
2506 }
2507 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) {
2508 printf("%sUG", comma ? "," : "");
2509 comma = 1;
2510 }
2511 if (proc2 & PROCBASED2_ENABLE_VPID) {
2512 printf("%sVPID", comma ? "," : "");
2513 comma = 1;
2514 }
2515 if (proc & PROCBASED_USE_TPR_SHADOW &&
2516 proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES &&
2517 proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE &&
2518 proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION &&
2519 proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) {
2520 printf("%sVID", comma ? "," : "");
2521 comma = 1;
2522 if (pin & PINBASED_POSTED_INTERRUPT)
2523 printf(",PostIntr");
2524 }
2525 return;
2526 }
2527
2528 mask = basic >> 32;
2529 printf("Basic Features=0x%b", mask,
2530 "\020"
2531 "\02132PA" /* 32-bit physical addresses */
2532 "\022SMM" /* SMM dual-monitor */
2533 "\027INS/OUTS" /* VM-exit info for INS and OUTS */
2534 "\030TRUE" /* TRUE_CTLS MSRs */
2535 );
2536 printf("\n Pin-Based Controls=0x%b", pin,
2537 "\020"
2538 "\001ExtINT" /* External-interrupt exiting */
2539 "\004NMI" /* NMI exiting */
2540 "\006VNMI" /* Virtual NMIs */
2541 "\007PreTmr" /* Activate VMX-preemption timer */
2542 "\010PostIntr" /* Process posted interrupts */
2543 );
2544 printf("\n Primary Processor Controls=0x%b", proc,
2545 "\020"
2546 "\003INTWIN" /* Interrupt-window exiting */
2547 "\004TSCOff" /* Use TSC offsetting */
2548 "\010HLT" /* HLT exiting */
2549 "\012INVLPG" /* INVLPG exiting */
2550 "\013MWAIT" /* MWAIT exiting */
2551 "\014RDPMC" /* RDPMC exiting */
2552 "\015RDTSC" /* RDTSC exiting */
2553 "\020CR3-LD" /* CR3-load exiting */
2554 "\021CR3-ST" /* CR3-store exiting */
2555 "\024CR8-LD" /* CR8-load exiting */
2556 "\025CR8-ST" /* CR8-store exiting */
2557 "\026TPR" /* Use TPR shadow */
2558 "\027NMIWIN" /* NMI-window exiting */
2559 "\030MOV-DR" /* MOV-DR exiting */
2560 "\031IO" /* Unconditional I/O exiting */
2561 "\032IOmap" /* Use I/O bitmaps */
2562 "\034MTF" /* Monitor trap flag */
2563 "\035MSRmap" /* Use MSR bitmaps */
2564 "\036MONITOR" /* MONITOR exiting */
2565 "\037PAUSE" /* PAUSE exiting */
2566 );
2567 if (proc & PROCBASED_SECONDARY_CONTROLS)
2568 printf("\n Secondary Processor Controls=0x%b", proc2,
2569 "\020"
2570 "\001APIC" /* Virtualize APIC accesses */
2571 "\002EPT" /* Enable EPT */
2572 "\003DT" /* Descriptor-table exiting */
2573 "\004RDTSCP" /* Enable RDTSCP */
2574 "\005x2APIC" /* Virtualize x2APIC mode */
2575 "\006VPID" /* Enable VPID */
2576 "\007WBINVD" /* WBINVD exiting */
2577 "\010UG" /* Unrestricted guest */
2578 "\011APIC-reg" /* APIC-register virtualization */
2579 "\012VID" /* Virtual-interrupt delivery */
2580 "\013PAUSE-loop" /* PAUSE-loop exiting */
2581 "\014RDRAND" /* RDRAND exiting */
2582 "\015INVPCID" /* Enable INVPCID */
2583 "\016VMFUNC" /* Enable VM functions */
2584 "\017VMCS" /* VMCS shadowing */
2585 "\020EPT#VE" /* EPT-violation #VE */
2586 "\021XSAVES" /* Enable XSAVES/XRSTORS */
2587 );
2588 printf("\n Exit Controls=0x%b", mask,
2589 "\020"
2590 "\003DR" /* Save debug controls */
2591 /* Ignore Host address-space size */
2592 "\015PERF" /* Load MSR_PERF_GLOBAL_CTRL */
2593 "\020AckInt" /* Acknowledge interrupt on exit */
2594 "\023PAT-SV" /* Save MSR_PAT */
2595 "\024PAT-LD" /* Load MSR_PAT */
2596 "\025EFER-SV" /* Save MSR_EFER */
2597 "\026EFER-LD" /* Load MSR_EFER */
2598 "\027PTMR-SV" /* Save VMX-preemption timer value */
2599 );
2600 printf("\n Entry Controls=0x%b", mask,
2601 "\020"
2602 "\003DR" /* Save debug controls */
2603 /* Ignore IA-32e mode guest */
2604 /* Ignore Entry to SMM */
2605 /* Ignore Deactivate dual-monitor treatment */
2606 "\016PERF" /* Load MSR_PERF_GLOBAL_CTRL */
2607 "\017PAT" /* Load MSR_PAT */
2608 "\020EFER" /* Load MSR_EFER */
2609 );
2610 if (proc & PROCBASED_SECONDARY_CONTROLS &&
2611 (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) {
2612 msr = rdmsr(MSR_VMX_EPT_VPID_CAP);
2613 mask = msr;
2614 printf("\n EPT Features=0x%b", mask,
2615 "\020"
2616 "\001XO" /* Execute-only translations */
2617 "\007PW4" /* Page-walk length of 4 */
2618 "\011UC" /* EPT paging-structure mem can be UC */
2619 "\017WB" /* EPT paging-structure mem can be WB */
2620 "\0212M" /* EPT PDE can map a 2-Mbyte page */
2621 "\0221G" /* EPT PDPTE can map a 1-Gbyte page */
2622 "\025INVEPT" /* INVEPT is supported */
2623 "\026AD" /* Accessed and dirty flags for EPT */
2624 "\032single" /* INVEPT single-context type */
2625 "\033all" /* INVEPT all-context type */
2626 );
2627 mask = msr >> 32;
2628 printf("\n VPID Features=0x%b", mask,
2629 "\020"
2630 "\001INVVPID" /* INVVPID is supported */
2631 "\011individual" /* INVVPID individual-address type */
2632 "\012single" /* INVVPID single-context type */
2633 "\013all" /* INVVPID all-context type */
2634 /* INVVPID single-context-retaining-globals type */
2635 "\014single-globals"
2636 );
2637 }
2638 }
2639
2640 static void
print_hypervisor_info(void)2641 print_hypervisor_info(void)
2642 {
2643
2644 if (*hv_vendor != '\0')
2645 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor);
2646 }
2647
2648 /*
2649 * Returns the maximum physical address that can be used with the
2650 * current system.
2651 */
2652 vm_paddr_t
cpu_getmaxphyaddr(void)2653 cpu_getmaxphyaddr(void)
2654 {
2655
2656 #if defined(__i386__)
2657 if (!pae_mode)
2658 return (0xffffffff);
2659 #endif
2660 return ((1ULL << cpu_maxphyaddr) - 1);
2661 }
2662