1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
2 */
3 /*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD: stable/9/sys/dev/drm2/i915/i915_dma.c 239965 2012-09-01 05:35:48Z kib $");
31
32 #include <dev/drm2/drmP.h>
33 #include <dev/drm2/drm.h>
34 #include <dev/drm2/i915/i915_drm.h>
35 #include <dev/drm2/i915/i915_drv.h>
36 #include <dev/drm2/i915/intel_drv.h>
37 #include <dev/drm2/i915/intel_ringbuffer.h>
38
39 static struct drm_i915_private *i915_mch_dev;
40 /*
41 * Lock protecting IPS related data structures
42 * - i915_mch_dev
43 * - dev_priv->max_delay
44 * - dev_priv->min_delay
45 * - dev_priv->fmax
46 * - dev_priv->gpu_busy
47 */
48 static struct mtx mchdev_lock;
49 MTX_SYSINIT(mchdev, &mchdev_lock, "mchdev", MTX_DEF);
50
51 static void i915_pineview_get_mem_freq(struct drm_device *dev);
52 static void i915_ironlake_get_mem_freq(struct drm_device *dev);
53 static int i915_driver_unload_int(struct drm_device *dev, bool locked);
54
i915_write_hws_pga(struct drm_device * dev)55 static void i915_write_hws_pga(struct drm_device *dev)
56 {
57 drm_i915_private_t *dev_priv = dev->dev_private;
58 u32 addr;
59
60 addr = dev_priv->status_page_dmah->busaddr;
61 if (INTEL_INFO(dev)->gen >= 4)
62 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
63 I915_WRITE(HWS_PGA, addr);
64 }
65
66 /**
67 * Sets up the hardware status page for devices that need a physical address
68 * in the register.
69 */
i915_init_phys_hws(struct drm_device * dev)70 static int i915_init_phys_hws(struct drm_device *dev)
71 {
72 drm_i915_private_t *dev_priv = dev->dev_private;
73 struct intel_ring_buffer *ring = LP_RING(dev_priv);
74
75 /*
76 * Program Hardware Status Page
77 * XXXKIB Keep 4GB limit for allocation for now. This method
78 * of allocation is used on <= 965 hardware, that has several
79 * erratas regarding the use of physical memory > 4 GB.
80 */
81 DRM_UNLOCK(dev);
82 dev_priv->status_page_dmah =
83 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
84 DRM_LOCK(dev);
85 if (!dev_priv->status_page_dmah) {
86 DRM_ERROR("Can not allocate hardware status page\n");
87 return -ENOMEM;
88 }
89 ring->status_page.page_addr = dev_priv->hw_status_page =
90 dev_priv->status_page_dmah->vaddr;
91 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
92
93 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
94
95 i915_write_hws_pga(dev);
96 DRM_DEBUG("Enabled hardware status page, phys %jx\n",
97 (uintmax_t)dev_priv->dma_status_page);
98 return 0;
99 }
100
101 /**
102 * Frees the hardware status page, whether it's a physical address or a virtual
103 * address set up by the X Server.
104 */
i915_free_hws(struct drm_device * dev)105 static void i915_free_hws(struct drm_device *dev)
106 {
107 drm_i915_private_t *dev_priv = dev->dev_private;
108 struct intel_ring_buffer *ring = LP_RING(dev_priv);
109
110 if (dev_priv->status_page_dmah) {
111 drm_pci_free(dev, dev_priv->status_page_dmah);
112 dev_priv->status_page_dmah = NULL;
113 }
114
115 if (dev_priv->status_gfx_addr) {
116 dev_priv->status_gfx_addr = 0;
117 ring->status_page.gfx_addr = 0;
118 drm_core_ioremapfree(&dev_priv->hws_map, dev);
119 }
120
121 /* Need to rewrite hardware status page */
122 I915_WRITE(HWS_PGA, 0x1ffff000);
123 }
124
i915_kernel_lost_context(struct drm_device * dev)125 void i915_kernel_lost_context(struct drm_device * dev)
126 {
127 drm_i915_private_t *dev_priv = dev->dev_private;
128 struct intel_ring_buffer *ring = LP_RING(dev_priv);
129
130 /*
131 * We should never lose context on the ring with modesetting
132 * as we don't expose it to userspace
133 */
134 if (drm_core_check_feature(dev, DRIVER_MODESET))
135 return;
136
137 ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
138 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
139 ring->space = ring->head - (ring->tail + 8);
140 if (ring->space < 0)
141 ring->space += ring->size;
142
143 #if 1
144 KIB_NOTYET();
145 #else
146 if (!dev->primary->master)
147 return;
148 #endif
149
150 if (ring->head == ring->tail && dev_priv->sarea_priv)
151 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
152 }
153
i915_dma_cleanup(struct drm_device * dev)154 static int i915_dma_cleanup(struct drm_device * dev)
155 {
156 drm_i915_private_t *dev_priv = dev->dev_private;
157 int i;
158
159
160 /* Make sure interrupts are disabled here because the uninstall ioctl
161 * may not have been called from userspace and after dev_private
162 * is freed, it's too late.
163 */
164 if (dev->irq_enabled)
165 drm_irq_uninstall(dev);
166
167 for (i = 0; i < I915_NUM_RINGS; i++)
168 intel_cleanup_ring_buffer(&dev_priv->rings[i]);
169
170 /* Clear the HWS virtual address at teardown */
171 if (I915_NEED_GFX_HWS(dev))
172 i915_free_hws(dev);
173
174 return 0;
175 }
176
i915_initialize(struct drm_device * dev,drm_i915_init_t * init)177 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
178 {
179 drm_i915_private_t *dev_priv = dev->dev_private;
180 int ret;
181
182 dev_priv->sarea = drm_getsarea(dev);
183 if (!dev_priv->sarea) {
184 DRM_ERROR("can not find sarea!\n");
185 i915_dma_cleanup(dev);
186 return -EINVAL;
187 }
188
189 dev_priv->sarea_priv = (drm_i915_sarea_t *)
190 ((u8 *) dev_priv->sarea->virtual + init->sarea_priv_offset);
191
192 if (init->ring_size != 0) {
193 if (LP_RING(dev_priv)->obj != NULL) {
194 i915_dma_cleanup(dev);
195 DRM_ERROR("Client tried to initialize ringbuffer in "
196 "GEM mode\n");
197 return -EINVAL;
198 }
199
200 ret = intel_render_ring_init_dri(dev,
201 init->ring_start,
202 init->ring_size);
203 if (ret) {
204 i915_dma_cleanup(dev);
205 return ret;
206 }
207 }
208
209 dev_priv->cpp = init->cpp;
210 dev_priv->back_offset = init->back_offset;
211 dev_priv->front_offset = init->front_offset;
212 dev_priv->current_page = 0;
213 dev_priv->sarea_priv->pf_current_page = 0;
214
215 /* Allow hardware batchbuffers unless told otherwise.
216 */
217 dev_priv->allow_batchbuffer = 1;
218
219 return 0;
220 }
221
i915_dma_resume(struct drm_device * dev)222 static int i915_dma_resume(struct drm_device * dev)
223 {
224 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
225 struct intel_ring_buffer *ring = LP_RING(dev_priv);
226
227 DRM_DEBUG("\n");
228
229 if (ring->map.handle == NULL) {
230 DRM_ERROR("can not ioremap virtual address for"
231 " ring buffer\n");
232 return -ENOMEM;
233 }
234
235 /* Program Hardware Status Page */
236 if (!ring->status_page.page_addr) {
237 DRM_ERROR("Can not find hardware status page\n");
238 return -EINVAL;
239 }
240 DRM_DEBUG("hw status page @ %p\n", ring->status_page.page_addr);
241 if (ring->status_page.gfx_addr != 0)
242 intel_ring_setup_status_page(ring);
243 else
244 i915_write_hws_pga(dev);
245
246 DRM_DEBUG("Enabled hardware status page\n");
247
248 return 0;
249 }
250
i915_dma_init(struct drm_device * dev,void * data,struct drm_file * file_priv)251 static int i915_dma_init(struct drm_device *dev, void *data,
252 struct drm_file *file_priv)
253 {
254 drm_i915_init_t *init = data;
255 int retcode = 0;
256
257 switch (init->func) {
258 case I915_INIT_DMA:
259 retcode = i915_initialize(dev, init);
260 break;
261 case I915_CLEANUP_DMA:
262 retcode = i915_dma_cleanup(dev);
263 break;
264 case I915_RESUME_DMA:
265 retcode = i915_dma_resume(dev);
266 break;
267 default:
268 retcode = -EINVAL;
269 break;
270 }
271
272 return retcode;
273 }
274
275 /* Implement basically the same security restrictions as hardware does
276 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
277 *
278 * Most of the calculations below involve calculating the size of a
279 * particular instruction. It's important to get the size right as
280 * that tells us where the next instruction to check is. Any illegal
281 * instruction detected will be given a size of zero, which is a
282 * signal to abort the rest of the buffer.
283 */
do_validate_cmd(int cmd)284 static int do_validate_cmd(int cmd)
285 {
286 switch (((cmd >> 29) & 0x7)) {
287 case 0x0:
288 switch ((cmd >> 23) & 0x3f) {
289 case 0x0:
290 return 1; /* MI_NOOP */
291 case 0x4:
292 return 1; /* MI_FLUSH */
293 default:
294 return 0; /* disallow everything else */
295 }
296 break;
297 case 0x1:
298 return 0; /* reserved */
299 case 0x2:
300 return (cmd & 0xff) + 2; /* 2d commands */
301 case 0x3:
302 if (((cmd >> 24) & 0x1f) <= 0x18)
303 return 1;
304
305 switch ((cmd >> 24) & 0x1f) {
306 case 0x1c:
307 return 1;
308 case 0x1d:
309 switch ((cmd >> 16) & 0xff) {
310 case 0x3:
311 return (cmd & 0x1f) + 2;
312 case 0x4:
313 return (cmd & 0xf) + 2;
314 default:
315 return (cmd & 0xffff) + 2;
316 }
317 case 0x1e:
318 if (cmd & (1 << 23))
319 return (cmd & 0xffff) + 1;
320 else
321 return 1;
322 case 0x1f:
323 if ((cmd & (1 << 23)) == 0) /* inline vertices */
324 return (cmd & 0x1ffff) + 2;
325 else if (cmd & (1 << 17)) /* indirect random */
326 if ((cmd & 0xffff) == 0)
327 return 0; /* unknown length, too hard */
328 else
329 return (((cmd & 0xffff) + 1) / 2) + 1;
330 else
331 return 2; /* indirect sequential */
332 default:
333 return 0;
334 }
335 default:
336 return 0;
337 }
338
339 return 0;
340 }
341
validate_cmd(int cmd)342 static int validate_cmd(int cmd)
343 {
344 int ret = do_validate_cmd(cmd);
345
346 /* printk("validate_cmd( %x ): %d\n", cmd, ret); */
347
348 return ret;
349 }
350
i915_emit_cmds(struct drm_device * dev,int __user * buffer,int dwords)351 static int i915_emit_cmds(struct drm_device *dev, int __user *buffer,
352 int dwords)
353 {
354 drm_i915_private_t *dev_priv = dev->dev_private;
355 int i;
356
357 if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
358 return -EINVAL;
359
360 BEGIN_LP_RING((dwords+1)&~1);
361
362 for (i = 0; i < dwords;) {
363 int cmd, sz;
364
365 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
366 return -EINVAL;
367
368 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
369 return -EINVAL;
370
371 OUT_RING(cmd);
372
373 while (++i, --sz) {
374 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
375 sizeof(cmd))) {
376 return -EINVAL;
377 }
378 OUT_RING(cmd);
379 }
380 }
381
382 if (dwords & 1)
383 OUT_RING(0);
384
385 ADVANCE_LP_RING();
386
387 return 0;
388 }
389
i915_emit_box(struct drm_device * dev,struct drm_clip_rect * boxes,int i,int DR1,int DR4)390 int i915_emit_box(struct drm_device * dev,
391 struct drm_clip_rect *boxes,
392 int i, int DR1, int DR4)
393 {
394 struct drm_clip_rect box;
395
396 if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
397 return -EFAULT;
398 }
399
400 return (i915_emit_box_p(dev, &box, DR1, DR4));
401 }
402
403 int
i915_emit_box_p(struct drm_device * dev,struct drm_clip_rect * box,int DR1,int DR4)404 i915_emit_box_p(struct drm_device *dev, struct drm_clip_rect *box,
405 int DR1, int DR4)
406 {
407 drm_i915_private_t *dev_priv = dev->dev_private;
408 int ret;
409
410 if (box->y2 <= box->y1 || box->x2 <= box->x1 || box->y2 <= 0 ||
411 box->x2 <= 0) {
412 DRM_ERROR("Bad box %d,%d..%d,%d\n",
413 box->x1, box->y1, box->x2, box->y2);
414 return -EINVAL;
415 }
416
417 if (INTEL_INFO(dev)->gen >= 4) {
418 ret = BEGIN_LP_RING(4);
419 if (ret != 0)
420 return (ret);
421
422 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
423 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
424 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
425 OUT_RING(DR4);
426 } else {
427 ret = BEGIN_LP_RING(6);
428 if (ret != 0)
429 return (ret);
430
431 OUT_RING(GFX_OP_DRAWRECT_INFO);
432 OUT_RING(DR1);
433 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
434 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
435 OUT_RING(DR4);
436 OUT_RING(0);
437 }
438 ADVANCE_LP_RING();
439
440 return 0;
441 }
442
443 /* XXX: Emitting the counter should really be moved to part of the IRQ
444 * emit. For now, do it in both places:
445 */
446
i915_emit_breadcrumb(struct drm_device * dev)447 static void i915_emit_breadcrumb(struct drm_device *dev)
448 {
449 drm_i915_private_t *dev_priv = dev->dev_private;
450
451 if (++dev_priv->counter > 0x7FFFFFFFUL)
452 dev_priv->counter = 0;
453 if (dev_priv->sarea_priv)
454 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
455
456 if (BEGIN_LP_RING(4) == 0) {
457 OUT_RING(MI_STORE_DWORD_INDEX);
458 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
459 OUT_RING(dev_priv->counter);
460 OUT_RING(0);
461 ADVANCE_LP_RING();
462 }
463 }
464
i915_dispatch_cmdbuffer(struct drm_device * dev,drm_i915_cmdbuffer_t * cmd,struct drm_clip_rect * cliprects,void * cmdbuf)465 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
466 drm_i915_cmdbuffer_t * cmd, struct drm_clip_rect *cliprects, void *cmdbuf)
467 {
468 int nbox = cmd->num_cliprects;
469 int i = 0, count, ret;
470
471 if (cmd->sz & 0x3) {
472 DRM_ERROR("alignment\n");
473 return -EINVAL;
474 }
475
476 i915_kernel_lost_context(dev);
477
478 count = nbox ? nbox : 1;
479
480 for (i = 0; i < count; i++) {
481 if (i < nbox) {
482 ret = i915_emit_box_p(dev, &cmd->cliprects[i],
483 cmd->DR1, cmd->DR4);
484 if (ret)
485 return ret;
486 }
487
488 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
489 if (ret)
490 return ret;
491 }
492
493 i915_emit_breadcrumb(dev);
494 return 0;
495 }
496
497 static int
i915_dispatch_batchbuffer(struct drm_device * dev,drm_i915_batchbuffer_t * batch,struct drm_clip_rect * cliprects)498 i915_dispatch_batchbuffer(struct drm_device * dev,
499 drm_i915_batchbuffer_t * batch, struct drm_clip_rect *cliprects)
500 {
501 drm_i915_private_t *dev_priv = dev->dev_private;
502 int nbox = batch->num_cliprects;
503 int i, count, ret;
504
505 if ((batch->start | batch->used) & 0x7) {
506 DRM_ERROR("alignment\n");
507 return -EINVAL;
508 }
509
510 i915_kernel_lost_context(dev);
511
512 count = nbox ? nbox : 1;
513
514 for (i = 0; i < count; i++) {
515 if (i < nbox) {
516 int ret = i915_emit_box_p(dev, &cliprects[i],
517 batch->DR1, batch->DR4);
518 if (ret)
519 return ret;
520 }
521
522 if (!IS_I830(dev) && !IS_845G(dev)) {
523 ret = BEGIN_LP_RING(2);
524 if (ret != 0)
525 return (ret);
526
527 if (INTEL_INFO(dev)->gen >= 4) {
528 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) |
529 MI_BATCH_NON_SECURE_I965);
530 OUT_RING(batch->start);
531 } else {
532 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
533 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
534 }
535 } else {
536 ret = BEGIN_LP_RING(4);
537 if (ret != 0)
538 return (ret);
539
540 OUT_RING(MI_BATCH_BUFFER);
541 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
542 OUT_RING(batch->start + batch->used - 4);
543 OUT_RING(0);
544 }
545 ADVANCE_LP_RING();
546 }
547
548 i915_emit_breadcrumb(dev);
549
550 return 0;
551 }
552
i915_dispatch_flip(struct drm_device * dev)553 static int i915_dispatch_flip(struct drm_device * dev)
554 {
555 drm_i915_private_t *dev_priv = dev->dev_private;
556 int ret;
557
558 if (!dev_priv->sarea_priv)
559 return -EINVAL;
560
561 DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
562 __func__,
563 dev_priv->current_page,
564 dev_priv->sarea_priv->pf_current_page);
565
566 i915_kernel_lost_context(dev);
567
568 ret = BEGIN_LP_RING(10);
569 if (ret)
570 return ret;
571 OUT_RING(MI_FLUSH | MI_READ_FLUSH);
572 OUT_RING(0);
573
574 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
575 OUT_RING(0);
576 if (dev_priv->current_page == 0) {
577 OUT_RING(dev_priv->back_offset);
578 dev_priv->current_page = 1;
579 } else {
580 OUT_RING(dev_priv->front_offset);
581 dev_priv->current_page = 0;
582 }
583 OUT_RING(0);
584
585 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
586 OUT_RING(0);
587
588 ADVANCE_LP_RING();
589
590 if (++dev_priv->counter > 0x7FFFFFFFUL)
591 dev_priv->counter = 0;
592 if (dev_priv->sarea_priv)
593 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
594
595 if (BEGIN_LP_RING(4) == 0) {
596 OUT_RING(MI_STORE_DWORD_INDEX);
597 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
598 OUT_RING(dev_priv->counter);
599 OUT_RING(0);
600 ADVANCE_LP_RING();
601 }
602
603 dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
604 return 0;
605 }
606
607 static int
i915_quiescent(struct drm_device * dev)608 i915_quiescent(struct drm_device *dev)
609 {
610 struct intel_ring_buffer *ring = LP_RING(dev->dev_private);
611
612 i915_kernel_lost_context(dev);
613 return (intel_wait_ring_idle(ring));
614 }
615
616 static int
i915_flush_ioctl(struct drm_device * dev,void * data,struct drm_file * file_priv)617 i915_flush_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv)
618 {
619 int ret;
620
621 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
622
623 DRM_LOCK(dev);
624 ret = i915_quiescent(dev);
625 DRM_UNLOCK(dev);
626
627 return (ret);
628 }
629
i915_batchbuffer(struct drm_device * dev,void * data,struct drm_file * file_priv)630 int i915_batchbuffer(struct drm_device *dev, void *data,
631 struct drm_file *file_priv)
632 {
633 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
634 drm_i915_sarea_t *sarea_priv;
635 drm_i915_batchbuffer_t *batch = data;
636 struct drm_clip_rect *cliprects;
637 size_t cliplen;
638 int ret;
639
640 if (!dev_priv->allow_batchbuffer) {
641 DRM_ERROR("Batchbuffer ioctl disabled\n");
642 return -EINVAL;
643 }
644 DRM_UNLOCK(dev);
645
646 DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
647 batch->start, batch->used, batch->num_cliprects);
648
649 cliplen = batch->num_cliprects * sizeof(struct drm_clip_rect);
650 if (batch->num_cliprects < 0)
651 return -EFAULT;
652 if (batch->num_cliprects != 0) {
653 cliprects = malloc(batch->num_cliprects *
654 sizeof(struct drm_clip_rect), DRM_MEM_DMA,
655 M_WAITOK | M_ZERO);
656
657 ret = -copyin(batch->cliprects, cliprects,
658 batch->num_cliprects * sizeof(struct drm_clip_rect));
659 if (ret != 0) {
660 DRM_LOCK(dev);
661 goto fail_free;
662 }
663 } else
664 cliprects = NULL;
665
666 DRM_LOCK(dev);
667 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
668 ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
669
670 sarea_priv = (drm_i915_sarea_t *)dev_priv->sarea_priv;
671 if (sarea_priv)
672 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
673
674 fail_free:
675 free(cliprects, DRM_MEM_DMA);
676 return ret;
677 }
678
i915_cmdbuffer(struct drm_device * dev,void * data,struct drm_file * file_priv)679 int i915_cmdbuffer(struct drm_device *dev, void *data,
680 struct drm_file *file_priv)
681 {
682 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
683 drm_i915_sarea_t *sarea_priv;
684 drm_i915_cmdbuffer_t *cmdbuf = data;
685 struct drm_clip_rect *cliprects = NULL;
686 void *batch_data;
687 int ret;
688
689 DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
690 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
691
692 if (cmdbuf->num_cliprects < 0)
693 return -EINVAL;
694
695 DRM_UNLOCK(dev);
696
697 batch_data = malloc(cmdbuf->sz, DRM_MEM_DMA, M_WAITOK);
698
699 ret = -copyin(cmdbuf->buf, batch_data, cmdbuf->sz);
700 if (ret != 0) {
701 DRM_LOCK(dev);
702 goto fail_batch_free;
703 }
704
705 if (cmdbuf->num_cliprects) {
706 cliprects = malloc(cmdbuf->num_cliprects *
707 sizeof(struct drm_clip_rect), DRM_MEM_DMA,
708 M_WAITOK | M_ZERO);
709 ret = -copyin(cmdbuf->cliprects, cliprects,
710 cmdbuf->num_cliprects * sizeof(struct drm_clip_rect));
711 if (ret != 0) {
712 DRM_LOCK(dev);
713 goto fail_clip_free;
714 }
715 }
716
717 DRM_LOCK(dev);
718 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
719 ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
720 if (ret) {
721 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
722 goto fail_clip_free;
723 }
724
725 sarea_priv = (drm_i915_sarea_t *)dev_priv->sarea_priv;
726 if (sarea_priv)
727 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
728
729 fail_clip_free:
730 free(cliprects, DRM_MEM_DMA);
731 fail_batch_free:
732 free(batch_data, DRM_MEM_DMA);
733 return ret;
734 }
735
i915_flip_bufs(struct drm_device * dev,void * data,struct drm_file * file_priv)736 static int i915_flip_bufs(struct drm_device *dev, void *data,
737 struct drm_file *file_priv)
738 {
739 int ret;
740
741 DRM_DEBUG("%s\n", __func__);
742
743 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
744
745 ret = i915_dispatch_flip(dev);
746
747 return ret;
748 }
749
i915_getparam(struct drm_device * dev,void * data,struct drm_file * file_priv)750 int i915_getparam(struct drm_device *dev, void *data,
751 struct drm_file *file_priv)
752 {
753 drm_i915_private_t *dev_priv = dev->dev_private;
754 drm_i915_getparam_t *param = data;
755 int value;
756
757 if (!dev_priv) {
758 DRM_ERROR("called with no initialization\n");
759 return -EINVAL;
760 }
761
762 switch (param->param) {
763 case I915_PARAM_IRQ_ACTIVE:
764 value = dev->irq_enabled ? 1 : 0;
765 break;
766 case I915_PARAM_ALLOW_BATCHBUFFER:
767 value = dev_priv->allow_batchbuffer ? 1 : 0;
768 break;
769 case I915_PARAM_LAST_DISPATCH:
770 value = READ_BREADCRUMB(dev_priv);
771 break;
772 case I915_PARAM_CHIPSET_ID:
773 value = dev->pci_device;
774 break;
775 case I915_PARAM_HAS_GEM:
776 value = 1;
777 break;
778 case I915_PARAM_NUM_FENCES_AVAIL:
779 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
780 break;
781 case I915_PARAM_HAS_OVERLAY:
782 value = dev_priv->overlay ? 1 : 0;
783 break;
784 case I915_PARAM_HAS_PAGEFLIPPING:
785 value = 1;
786 break;
787 case I915_PARAM_HAS_EXECBUF2:
788 value = 1;
789 break;
790 case I915_PARAM_HAS_BSD:
791 value = HAS_BSD(dev);
792 break;
793 case I915_PARAM_HAS_BLT:
794 value = HAS_BLT(dev);
795 break;
796 case I915_PARAM_HAS_RELAXED_FENCING:
797 value = 1;
798 break;
799 case I915_PARAM_HAS_COHERENT_RINGS:
800 value = 1;
801 break;
802 case I915_PARAM_HAS_EXEC_CONSTANTS:
803 value = INTEL_INFO(dev)->gen >= 4;
804 break;
805 case I915_PARAM_HAS_RELAXED_DELTA:
806 value = 1;
807 break;
808 case I915_PARAM_HAS_GEN7_SOL_RESET:
809 value = 1;
810 break;
811 case I915_PARAM_HAS_LLC:
812 value = HAS_LLC(dev);
813 break;
814 default:
815 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
816 param->param);
817 return -EINVAL;
818 }
819
820 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
821 DRM_ERROR("DRM_COPY_TO_USER failed\n");
822 return -EFAULT;
823 }
824
825 return 0;
826 }
827
i915_setparam(struct drm_device * dev,void * data,struct drm_file * file_priv)828 static int i915_setparam(struct drm_device *dev, void *data,
829 struct drm_file *file_priv)
830 {
831 drm_i915_private_t *dev_priv = dev->dev_private;
832 drm_i915_setparam_t *param = data;
833
834 if (!dev_priv) {
835 DRM_ERROR("called with no initialization\n");
836 return -EINVAL;
837 }
838
839 switch (param->param) {
840 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
841 break;
842 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
843 dev_priv->tex_lru_log_granularity = param->value;
844 break;
845 case I915_SETPARAM_ALLOW_BATCHBUFFER:
846 dev_priv->allow_batchbuffer = param->value;
847 break;
848 case I915_SETPARAM_NUM_USED_FENCES:
849 if (param->value > dev_priv->num_fence_regs ||
850 param->value < 0)
851 return -EINVAL;
852 /* Userspace can use first N regs */
853 dev_priv->fence_reg_start = param->value;
854 break;
855 default:
856 DRM_DEBUG("unknown parameter %d\n", param->param);
857 return -EINVAL;
858 }
859
860 return 0;
861 }
862
i915_set_status_page(struct drm_device * dev,void * data,struct drm_file * file_priv)863 static int i915_set_status_page(struct drm_device *dev, void *data,
864 struct drm_file *file_priv)
865 {
866 drm_i915_private_t *dev_priv = dev->dev_private;
867 drm_i915_hws_addr_t *hws = data;
868 struct intel_ring_buffer *ring = LP_RING(dev_priv);
869
870 if (!I915_NEED_GFX_HWS(dev))
871 return -EINVAL;
872
873 if (!dev_priv) {
874 DRM_ERROR("called with no initialization\n");
875 return -EINVAL;
876 }
877
878 DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws->addr);
879 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
880 DRM_ERROR("tried to set status page when mode setting active\n");
881 return 0;
882 }
883
884 ring->status_page.gfx_addr = dev_priv->status_gfx_addr =
885 hws->addr & (0x1ffff<<12);
886
887 dev_priv->hws_map.offset = dev->agp->base + hws->addr;
888 dev_priv->hws_map.size = 4*1024;
889 dev_priv->hws_map.type = 0;
890 dev_priv->hws_map.flags = 0;
891 dev_priv->hws_map.mtrr = 0;
892
893 drm_core_ioremap_wc(&dev_priv->hws_map, dev);
894 if (dev_priv->hws_map.virtual == NULL) {
895 i915_dma_cleanup(dev);
896 ring->status_page.gfx_addr = dev_priv->status_gfx_addr = 0;
897 DRM_ERROR("can not ioremap virtual address for"
898 " G33 hw status page\n");
899 return -ENOMEM;
900 }
901 ring->status_page.page_addr = dev_priv->hw_status_page =
902 dev_priv->hws_map.virtual;
903
904 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
905 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
906 DRM_DEBUG("load hws HWS_PGA with gfx mem 0x%x\n",
907 dev_priv->status_gfx_addr);
908 DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
909 return 0;
910 }
911
912 static bool
intel_enable_ppgtt(struct drm_device * dev)913 intel_enable_ppgtt(struct drm_device *dev)
914 {
915 if (i915_enable_ppgtt >= 0)
916 return i915_enable_ppgtt;
917
918 /* Disable ppgtt on SNB if VT-d is on. */
919 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_enabled)
920 return false;
921
922 return true;
923 }
924
925 static int
i915_load_gem_init(struct drm_device * dev)926 i915_load_gem_init(struct drm_device *dev)
927 {
928 struct drm_i915_private *dev_priv = dev->dev_private;
929 unsigned long prealloc_size, gtt_size, mappable_size;
930 int ret;
931
932 prealloc_size = dev_priv->mm.gtt.stolen_size;
933 gtt_size = dev_priv->mm.gtt.gtt_total_entries << PAGE_SHIFT;
934 mappable_size = dev_priv->mm.gtt.gtt_mappable_entries << PAGE_SHIFT;
935
936 /* Basic memrange allocator for stolen space */
937 drm_mm_init(&dev_priv->mm.stolen, 0, prealloc_size);
938
939 DRM_LOCK(dev);
940 if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
941 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
942 * aperture accordingly when using aliasing ppgtt. */
943 gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
944 /* For paranoia keep the guard page in between. */
945 gtt_size -= PAGE_SIZE;
946
947 i915_gem_do_init(dev, 0, mappable_size, gtt_size);
948
949 ret = i915_gem_init_aliasing_ppgtt(dev);
950 if (ret) {
951 DRM_UNLOCK(dev);
952 return ret;
953 }
954 } else {
955 /* Let GEM Manage all of the aperture.
956 *
957 * However, leave one page at the end still bound to the scratch
958 * page. There are a number of places where the hardware
959 * apparently prefetches past the end of the object, and we've
960 * seen multiple hangs with the GPU head pointer stuck in a
961 * batchbuffer bound at the last page of the aperture. One page
962 * should be enough to keep any prefetching inside of the
963 * aperture.
964 */
965 i915_gem_do_init(dev, 0, mappable_size, gtt_size - PAGE_SIZE);
966 }
967
968 ret = i915_gem_init_hw(dev);
969 DRM_UNLOCK(dev);
970 if (ret != 0) {
971 i915_gem_cleanup_aliasing_ppgtt(dev);
972 return (ret);
973 }
974
975 #if 0
976 /* Try to set up FBC with a reasonable compressed buffer size */
977 if (I915_HAS_FBC(dev) && i915_powersave) {
978 int cfb_size;
979
980 /* Leave 1M for line length buffer & misc. */
981
982 /* Try to get a 32M buffer... */
983 if (prealloc_size > (36*1024*1024))
984 cfb_size = 32*1024*1024;
985 else /* fall back to 7/8 of the stolen space */
986 cfb_size = prealloc_size * 7 / 8;
987 i915_setup_compression(dev, cfb_size);
988 }
989 #endif
990
991 /* Allow hardware batchbuffers unless told otherwise. */
992 dev_priv->allow_batchbuffer = 1;
993 return 0;
994 }
995
996 static int
i915_load_modeset_init(struct drm_device * dev)997 i915_load_modeset_init(struct drm_device *dev)
998 {
999 struct drm_i915_private *dev_priv = dev->dev_private;
1000 int ret;
1001
1002 ret = intel_parse_bios(dev);
1003 if (ret)
1004 DRM_INFO("failed to find VBIOS tables\n");
1005
1006 #if 0
1007 intel_register_dsm_handler();
1008 #endif
1009
1010 /* IIR "flip pending" bit means done if this bit is set */
1011 if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE))
1012 dev_priv->flip_pending_is_done = true;
1013
1014 intel_modeset_init(dev);
1015
1016 ret = i915_load_gem_init(dev);
1017 if (ret != 0)
1018 goto cleanup_gem;
1019
1020 intel_modeset_gem_init(dev);
1021
1022 ret = drm_irq_install(dev);
1023 if (ret)
1024 goto cleanup_gem;
1025
1026 dev->vblank_disable_allowed = 1;
1027
1028 ret = intel_fbdev_init(dev);
1029 if (ret)
1030 goto cleanup_gem;
1031
1032 drm_kms_helper_poll_init(dev);
1033
1034 /* We're off and running w/KMS */
1035 dev_priv->mm.suspended = 0;
1036
1037 return (0);
1038
1039 cleanup_gem:
1040 DRM_LOCK(dev);
1041 i915_gem_cleanup_ringbuffer(dev);
1042 DRM_UNLOCK(dev);
1043 i915_gem_cleanup_aliasing_ppgtt(dev);
1044 return (ret);
1045 }
1046
1047 static int
i915_get_bridge_dev(struct drm_device * dev)1048 i915_get_bridge_dev(struct drm_device *dev)
1049 {
1050 struct drm_i915_private *dev_priv;
1051
1052 dev_priv = dev->dev_private;
1053
1054 dev_priv->bridge_dev = intel_gtt_get_bridge_device();
1055 if (dev_priv->bridge_dev == NULL) {
1056 DRM_ERROR("bridge device not found\n");
1057 return (-1);
1058 }
1059 return (0);
1060 }
1061
1062 #define MCHBAR_I915 0x44
1063 #define MCHBAR_I965 0x48
1064 #define MCHBAR_SIZE (4*4096)
1065
1066 #define DEVEN_REG 0x54
1067 #define DEVEN_MCHBAR_EN (1 << 28)
1068
1069 /* Allocate space for the MCH regs if needed, return nonzero on error */
1070 static int
intel_alloc_mchbar_resource(struct drm_device * dev)1071 intel_alloc_mchbar_resource(struct drm_device *dev)
1072 {
1073 drm_i915_private_t *dev_priv;
1074 device_t vga;
1075 int reg;
1076 u32 temp_lo, temp_hi;
1077 u64 mchbar_addr, temp;
1078
1079 dev_priv = dev->dev_private;
1080 reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1081
1082 if (INTEL_INFO(dev)->gen >= 4)
1083 temp_hi = pci_read_config(dev_priv->bridge_dev, reg + 4, 4);
1084 else
1085 temp_hi = 0;
1086 temp_lo = pci_read_config(dev_priv->bridge_dev, reg, 4);
1087 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
1088
1089 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
1090 #ifdef XXX_CONFIG_PNP
1091 if (mchbar_addr &&
1092 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
1093 return 0;
1094 #endif
1095
1096 /* Get some space for it */
1097 vga = device_get_parent(dev->device);
1098 dev_priv->mch_res_rid = 0x100;
1099 dev_priv->mch_res = BUS_ALLOC_RESOURCE(device_get_parent(vga),
1100 dev->device, SYS_RES_MEMORY, &dev_priv->mch_res_rid, 0, ~0UL,
1101 MCHBAR_SIZE, RF_ACTIVE | RF_SHAREABLE);
1102 if (dev_priv->mch_res == NULL) {
1103 DRM_ERROR("failed mchbar resource alloc\n");
1104 return (-ENOMEM);
1105 }
1106
1107 if (INTEL_INFO(dev)->gen >= 4) {
1108 temp = rman_get_start(dev_priv->mch_res);
1109 temp >>= 32;
1110 pci_write_config(dev_priv->bridge_dev, reg + 4, temp, 4);
1111 }
1112 pci_write_config(dev_priv->bridge_dev, reg,
1113 rman_get_start(dev_priv->mch_res) & UINT32_MAX, 4);
1114 return (0);
1115 }
1116
1117 static void
intel_setup_mchbar(struct drm_device * dev)1118 intel_setup_mchbar(struct drm_device *dev)
1119 {
1120 drm_i915_private_t *dev_priv;
1121 int mchbar_reg;
1122 u32 temp;
1123 bool enabled;
1124
1125 dev_priv = dev->dev_private;
1126 mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1127
1128 dev_priv->mchbar_need_disable = false;
1129
1130 if (IS_I915G(dev) || IS_I915GM(dev)) {
1131 temp = pci_read_config(dev_priv->bridge_dev, DEVEN_REG, 4);
1132 enabled = (temp & DEVEN_MCHBAR_EN) != 0;
1133 } else {
1134 temp = pci_read_config(dev_priv->bridge_dev, mchbar_reg, 4);
1135 enabled = temp & 1;
1136 }
1137
1138 /* If it's already enabled, don't have to do anything */
1139 if (enabled) {
1140 DRM_DEBUG("mchbar already enabled\n");
1141 return;
1142 }
1143
1144 if (intel_alloc_mchbar_resource(dev))
1145 return;
1146
1147 dev_priv->mchbar_need_disable = true;
1148
1149 /* Space is allocated or reserved, so enable it. */
1150 if (IS_I915G(dev) || IS_I915GM(dev)) {
1151 pci_write_config(dev_priv->bridge_dev, DEVEN_REG,
1152 temp | DEVEN_MCHBAR_EN, 4);
1153 } else {
1154 temp = pci_read_config(dev_priv->bridge_dev, mchbar_reg, 4);
1155 pci_write_config(dev_priv->bridge_dev, mchbar_reg, temp | 1, 4);
1156 }
1157 }
1158
1159 static void
intel_teardown_mchbar(struct drm_device * dev)1160 intel_teardown_mchbar(struct drm_device *dev)
1161 {
1162 drm_i915_private_t *dev_priv;
1163 device_t vga;
1164 int mchbar_reg;
1165 u32 temp;
1166
1167 dev_priv = dev->dev_private;
1168 mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1169
1170 if (dev_priv->mchbar_need_disable) {
1171 if (IS_I915G(dev) || IS_I915GM(dev)) {
1172 temp = pci_read_config(dev_priv->bridge_dev,
1173 DEVEN_REG, 4);
1174 temp &= ~DEVEN_MCHBAR_EN;
1175 pci_write_config(dev_priv->bridge_dev, DEVEN_REG,
1176 temp, 4);
1177 } else {
1178 temp = pci_read_config(dev_priv->bridge_dev,
1179 mchbar_reg, 4);
1180 temp &= ~1;
1181 pci_write_config(dev_priv->bridge_dev, mchbar_reg,
1182 temp, 4);
1183 }
1184 }
1185
1186 if (dev_priv->mch_res != NULL) {
1187 vga = device_get_parent(dev->device);
1188 BUS_DEACTIVATE_RESOURCE(device_get_parent(vga), dev->device,
1189 SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1190 BUS_RELEASE_RESOURCE(device_get_parent(vga), dev->device,
1191 SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1192 dev_priv->mch_res = NULL;
1193 }
1194 }
1195
1196 int
i915_driver_load(struct drm_device * dev,unsigned long flags)1197 i915_driver_load(struct drm_device *dev, unsigned long flags)
1198 {
1199 struct drm_i915_private *dev_priv = dev->dev_private;
1200 unsigned long base, size;
1201 int mmio_bar, ret;
1202
1203 ret = 0;
1204
1205 /* i915 has 4 more counters */
1206 dev->counters += 4;
1207 dev->types[6] = _DRM_STAT_IRQ;
1208 dev->types[7] = _DRM_STAT_PRIMARY;
1209 dev->types[8] = _DRM_STAT_SECONDARY;
1210 dev->types[9] = _DRM_STAT_DMA;
1211
1212 dev_priv = malloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER,
1213 M_ZERO | M_WAITOK);
1214 if (dev_priv == NULL)
1215 return -ENOMEM;
1216
1217 dev->dev_private = (void *)dev_priv;
1218 dev_priv->dev = dev;
1219 dev_priv->info = i915_get_device_id(dev->pci_device);
1220
1221 if (i915_get_bridge_dev(dev)) {
1222 free(dev_priv, DRM_MEM_DRIVER);
1223 return (-EIO);
1224 }
1225 dev_priv->mm.gtt = intel_gtt_get();
1226
1227 /* Add register map (needed for suspend/resume) */
1228 mmio_bar = IS_GEN2(dev) ? 1 : 0;
1229 base = drm_get_resource_start(dev, mmio_bar);
1230 size = drm_get_resource_len(dev, mmio_bar);
1231
1232 ret = drm_addmap(dev, base, size, _DRM_REGISTERS,
1233 _DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio_map);
1234
1235 dev_priv->tq = taskqueue_create("915", M_WAITOK,
1236 taskqueue_thread_enqueue, &dev_priv->tq);
1237 taskqueue_start_threads(&dev_priv->tq, 1, PWAIT, "i915 taskq");
1238 mtx_init(&dev_priv->gt_lock, "915gt", NULL, MTX_DEF);
1239 mtx_init(&dev_priv->error_lock, "915err", NULL, MTX_DEF);
1240 mtx_init(&dev_priv->error_completion_lock, "915cmp", NULL, MTX_DEF);
1241 mtx_init(&dev_priv->rps_lock, "915rps", NULL, MTX_DEF);
1242
1243 dev_priv->has_gem = 1;
1244 intel_irq_init(dev);
1245
1246 intel_setup_mchbar(dev);
1247 intel_setup_gmbus(dev);
1248 intel_opregion_setup(dev);
1249
1250 intel_setup_bios(dev);
1251
1252 i915_gem_load(dev);
1253
1254 /* Init HWS */
1255 if (!I915_NEED_GFX_HWS(dev)) {
1256 ret = i915_init_phys_hws(dev);
1257 if (ret != 0) {
1258 drm_rmmap(dev, dev_priv->mmio_map);
1259 drm_free(dev_priv, sizeof(struct drm_i915_private),
1260 DRM_MEM_DRIVER);
1261 return ret;
1262 }
1263 }
1264
1265 if (IS_PINEVIEW(dev))
1266 i915_pineview_get_mem_freq(dev);
1267 else if (IS_GEN5(dev))
1268 i915_ironlake_get_mem_freq(dev);
1269
1270 mtx_init(&dev_priv->irq_lock, "userirq", NULL, MTX_DEF);
1271
1272 if (IS_IVYBRIDGE(dev))
1273 dev_priv->num_pipe = 3;
1274 else if (IS_MOBILE(dev) || !IS_GEN2(dev))
1275 dev_priv->num_pipe = 2;
1276 else
1277 dev_priv->num_pipe = 1;
1278
1279 ret = drm_vblank_init(dev, dev_priv->num_pipe);
1280 if (ret)
1281 goto out_gem_unload;
1282
1283 /* Start out suspended */
1284 dev_priv->mm.suspended = 1;
1285
1286 intel_detect_pch(dev);
1287
1288 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1289 DRM_UNLOCK(dev);
1290 ret = i915_load_modeset_init(dev);
1291 DRM_LOCK(dev);
1292 if (ret < 0) {
1293 DRM_ERROR("failed to init modeset\n");
1294 goto out_gem_unload;
1295 }
1296 }
1297
1298 intel_opregion_init(dev);
1299
1300 callout_init(&dev_priv->hangcheck_timer, 1);
1301 callout_reset(&dev_priv->hangcheck_timer, DRM_I915_HANGCHECK_PERIOD,
1302 i915_hangcheck_elapsed, dev);
1303
1304 if (IS_GEN5(dev)) {
1305 mtx_lock(&mchdev_lock);
1306 i915_mch_dev = dev_priv;
1307 dev_priv->mchdev_lock = &mchdev_lock;
1308 mtx_unlock(&mchdev_lock);
1309 }
1310
1311 return (0);
1312
1313 out_gem_unload:
1314 /* XXXKIB */
1315 (void) i915_driver_unload_int(dev, true);
1316 return (ret);
1317 }
1318
1319 static int
i915_driver_unload_int(struct drm_device * dev,bool locked)1320 i915_driver_unload_int(struct drm_device *dev, bool locked)
1321 {
1322 struct drm_i915_private *dev_priv = dev->dev_private;
1323 int ret;
1324
1325 if (!locked)
1326 DRM_LOCK(dev);
1327 ret = i915_gpu_idle(dev, true);
1328 if (ret)
1329 DRM_ERROR("failed to idle hardware: %d\n", ret);
1330 if (!locked)
1331 DRM_UNLOCK(dev);
1332
1333 i915_free_hws(dev);
1334
1335 intel_teardown_mchbar(dev);
1336
1337 if (locked)
1338 DRM_UNLOCK(dev);
1339 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1340 intel_fbdev_fini(dev);
1341 intel_modeset_cleanup(dev);
1342 }
1343
1344 /* Free error state after interrupts are fully disabled. */
1345 callout_stop(&dev_priv->hangcheck_timer);
1346 callout_drain(&dev_priv->hangcheck_timer);
1347
1348 i915_destroy_error_state(dev);
1349
1350 intel_opregion_fini(dev);
1351
1352 if (locked)
1353 DRM_LOCK(dev);
1354
1355 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1356 if (!locked)
1357 DRM_LOCK(dev);
1358 i915_gem_free_all_phys_object(dev);
1359 i915_gem_cleanup_ringbuffer(dev);
1360 if (!locked)
1361 DRM_UNLOCK(dev);
1362 i915_gem_cleanup_aliasing_ppgtt(dev);
1363 #if 1
1364 KIB_NOTYET();
1365 #else
1366 if (I915_HAS_FBC(dev) && i915_powersave)
1367 i915_cleanup_compression(dev);
1368 #endif
1369 drm_mm_takedown(&dev_priv->mm.stolen);
1370
1371 intel_cleanup_overlay(dev);
1372
1373 if (!I915_NEED_GFX_HWS(dev))
1374 i915_free_hws(dev);
1375 }
1376
1377 i915_gem_unload(dev);
1378
1379 mtx_destroy(&dev_priv->irq_lock);
1380
1381 if (dev_priv->tq != NULL)
1382 taskqueue_free(dev_priv->tq);
1383
1384 bus_generic_detach(dev->device);
1385 drm_rmmap(dev, dev_priv->mmio_map);
1386 intel_teardown_gmbus(dev);
1387
1388 mtx_destroy(&dev_priv->error_lock);
1389 mtx_destroy(&dev_priv->error_completion_lock);
1390 mtx_destroy(&dev_priv->rps_lock);
1391 drm_free(dev->dev_private, sizeof(drm_i915_private_t),
1392 DRM_MEM_DRIVER);
1393
1394 return (0);
1395 }
1396
1397 int
i915_driver_unload(struct drm_device * dev)1398 i915_driver_unload(struct drm_device *dev)
1399 {
1400
1401 return (i915_driver_unload_int(dev, true));
1402 }
1403
1404 int
i915_driver_open(struct drm_device * dev,struct drm_file * file_priv)1405 i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
1406 {
1407 struct drm_i915_file_private *i915_file_priv;
1408
1409 i915_file_priv = malloc(sizeof(*i915_file_priv), DRM_MEM_FILES,
1410 M_WAITOK | M_ZERO);
1411
1412 mtx_init(&i915_file_priv->mm.lck, "915fp", NULL, MTX_DEF);
1413 INIT_LIST_HEAD(&i915_file_priv->mm.request_list);
1414 file_priv->driver_priv = i915_file_priv;
1415
1416 return (0);
1417 }
1418
1419 void
i915_driver_lastclose(struct drm_device * dev)1420 i915_driver_lastclose(struct drm_device * dev)
1421 {
1422 drm_i915_private_t *dev_priv = dev->dev_private;
1423
1424 if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
1425 #if 1
1426 KIB_NOTYET();
1427 #else
1428 drm_fb_helper_restore();
1429 vga_switcheroo_process_delayed_switch();
1430 #endif
1431 return;
1432 }
1433 i915_gem_lastclose(dev);
1434 i915_dma_cleanup(dev);
1435 }
1436
i915_driver_preclose(struct drm_device * dev,struct drm_file * file_priv)1437 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1438 {
1439
1440 i915_gem_release(dev, file_priv);
1441 }
1442
i915_driver_postclose(struct drm_device * dev,struct drm_file * file_priv)1443 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
1444 {
1445 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1446
1447 mtx_destroy(&i915_file_priv->mm.lck);
1448 drm_free(i915_file_priv, sizeof(*i915_file_priv), DRM_MEM_FILES);
1449 }
1450
1451 struct drm_ioctl_desc i915_ioctls[] = {
1452 DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1453 DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1454 DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
1455 DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1456 DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1457 DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1458 DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
1459 DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1460 DRM_IOCTL_DEF(DRM_I915_ALLOC, drm_noop, DRM_AUTH),
1461 DRM_IOCTL_DEF(DRM_I915_FREE, drm_noop, DRM_AUTH),
1462 DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1463 DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1464 DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1465 DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1466 DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH ),
1467 DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1468 DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1469 DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1470 DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH | DRM_UNLOCKED),
1471 DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH | DRM_UNLOCKED),
1472 DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1473 DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1474 DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
1475 DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH),
1476 DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1477 DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1478 DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, 0),
1479 DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
1480 DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
1481 DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0),
1482 DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
1483 DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
1484 DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
1485 DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0),
1486 DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0),
1487 DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
1488 DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1489 DRM_IOCTL_DEF(DRM_I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
1490 DRM_IOCTL_DEF(DRM_I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1491 DRM_IOCTL_DEF(DRM_I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1492 DRM_IOCTL_DEF(DRM_I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1493 DRM_IOCTL_DEF(DRM_I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1494 };
1495
1496 #ifdef COMPAT_FREEBSD32
1497 extern drm_ioctl_desc_t i915_compat_ioctls[];
1498 extern int i915_compat_ioctls_nr;
1499 #endif
1500
1501 struct drm_driver_info i915_driver_info = {
1502 .driver_features = DRIVER_USE_AGP | DRIVER_REQUIRE_AGP |
1503 DRIVER_USE_MTRR | DRIVER_HAVE_IRQ | DRIVER_LOCKLESS_IRQ |
1504 DRIVER_GEM /*| DRIVER_MODESET*/,
1505
1506 .buf_priv_size = sizeof(drm_i915_private_t),
1507 .load = i915_driver_load,
1508 .open = i915_driver_open,
1509 .unload = i915_driver_unload,
1510 .preclose = i915_driver_preclose,
1511 .lastclose = i915_driver_lastclose,
1512 .postclose = i915_driver_postclose,
1513 .device_is_agp = i915_driver_device_is_agp,
1514 .gem_init_object = i915_gem_init_object,
1515 .gem_free_object = i915_gem_free_object,
1516 .gem_pager_ops = &i915_gem_pager_ops,
1517 .dumb_create = i915_gem_dumb_create,
1518 .dumb_map_offset = i915_gem_mmap_gtt,
1519 .dumb_destroy = i915_gem_dumb_destroy,
1520 .sysctl_init = i915_sysctl_init,
1521 .sysctl_cleanup = i915_sysctl_cleanup,
1522
1523 .ioctls = i915_ioctls,
1524 #ifdef COMPAT_FREEBSD32
1525 .compat_ioctls = i915_compat_ioctls,
1526 .compat_ioctls_nr = &i915_compat_ioctls_nr,
1527 #endif
1528 .max_ioctl = DRM_ARRAY_SIZE(i915_ioctls),
1529
1530 .name = DRIVER_NAME,
1531 .desc = DRIVER_DESC,
1532 .date = DRIVER_DATE,
1533 .major = DRIVER_MAJOR,
1534 .minor = DRIVER_MINOR,
1535 .patchlevel = DRIVER_PATCHLEVEL,
1536 };
1537
1538 /**
1539 * Determine if the device really is AGP or not.
1540 *
1541 * All Intel graphics chipsets are treated as AGP, even if they are really
1542 * built-in.
1543 *
1544 * \param dev The device to be tested.
1545 *
1546 * \returns
1547 * A value of 1 is always retured to indictate every i9x5 is AGP.
1548 */
i915_driver_device_is_agp(struct drm_device * dev)1549 int i915_driver_device_is_agp(struct drm_device * dev)
1550 {
1551 return 1;
1552 }
1553
i915_pineview_get_mem_freq(struct drm_device * dev)1554 static void i915_pineview_get_mem_freq(struct drm_device *dev)
1555 {
1556 drm_i915_private_t *dev_priv = dev->dev_private;
1557 u32 tmp;
1558
1559 tmp = I915_READ(CLKCFG);
1560
1561 switch (tmp & CLKCFG_FSB_MASK) {
1562 case CLKCFG_FSB_533:
1563 dev_priv->fsb_freq = 533; /* 133*4 */
1564 break;
1565 case CLKCFG_FSB_800:
1566 dev_priv->fsb_freq = 800; /* 200*4 */
1567 break;
1568 case CLKCFG_FSB_667:
1569 dev_priv->fsb_freq = 667; /* 167*4 */
1570 break;
1571 case CLKCFG_FSB_400:
1572 dev_priv->fsb_freq = 400; /* 100*4 */
1573 break;
1574 }
1575
1576 switch (tmp & CLKCFG_MEM_MASK) {
1577 case CLKCFG_MEM_533:
1578 dev_priv->mem_freq = 533;
1579 break;
1580 case CLKCFG_MEM_667:
1581 dev_priv->mem_freq = 667;
1582 break;
1583 case CLKCFG_MEM_800:
1584 dev_priv->mem_freq = 800;
1585 break;
1586 }
1587
1588 /* detect pineview DDR3 setting */
1589 tmp = I915_READ(CSHRDDR3CTL);
1590 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
1591 }
1592
i915_ironlake_get_mem_freq(struct drm_device * dev)1593 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
1594 {
1595 drm_i915_private_t *dev_priv = dev->dev_private;
1596 u16 ddrpll, csipll;
1597
1598 ddrpll = I915_READ16(DDRMPLL1);
1599 csipll = I915_READ16(CSIPLL0);
1600
1601 switch (ddrpll & 0xff) {
1602 case 0xc:
1603 dev_priv->mem_freq = 800;
1604 break;
1605 case 0x10:
1606 dev_priv->mem_freq = 1066;
1607 break;
1608 case 0x14:
1609 dev_priv->mem_freq = 1333;
1610 break;
1611 case 0x18:
1612 dev_priv->mem_freq = 1600;
1613 break;
1614 default:
1615 DRM_DEBUG("unknown memory frequency 0x%02x\n",
1616 ddrpll & 0xff);
1617 dev_priv->mem_freq = 0;
1618 break;
1619 }
1620
1621 dev_priv->r_t = dev_priv->mem_freq;
1622
1623 switch (csipll & 0x3ff) {
1624 case 0x00c:
1625 dev_priv->fsb_freq = 3200;
1626 break;
1627 case 0x00e:
1628 dev_priv->fsb_freq = 3733;
1629 break;
1630 case 0x010:
1631 dev_priv->fsb_freq = 4266;
1632 break;
1633 case 0x012:
1634 dev_priv->fsb_freq = 4800;
1635 break;
1636 case 0x014:
1637 dev_priv->fsb_freq = 5333;
1638 break;
1639 case 0x016:
1640 dev_priv->fsb_freq = 5866;
1641 break;
1642 case 0x018:
1643 dev_priv->fsb_freq = 6400;
1644 break;
1645 default:
1646 DRM_DEBUG("unknown fsb frequency 0x%04x\n",
1647 csipll & 0x3ff);
1648 dev_priv->fsb_freq = 0;
1649 break;
1650 }
1651
1652 if (dev_priv->fsb_freq == 3200) {
1653 dev_priv->c_m = 0;
1654 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
1655 dev_priv->c_m = 1;
1656 } else {
1657 dev_priv->c_m = 2;
1658 }
1659 }
1660
1661 static const struct cparams {
1662 u16 i;
1663 u16 t;
1664 u16 m;
1665 u16 c;
1666 } cparams[] = {
1667 { 1, 1333, 301, 28664 },
1668 { 1, 1066, 294, 24460 },
1669 { 1, 800, 294, 25192 },
1670 { 0, 1333, 276, 27605 },
1671 { 0, 1066, 276, 27605 },
1672 { 0, 800, 231, 23784 },
1673 };
1674
i915_chipset_val(struct drm_i915_private * dev_priv)1675 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
1676 {
1677 u64 total_count, diff, ret;
1678 u32 count1, count2, count3, m = 0, c = 0;
1679 unsigned long now = jiffies_to_msecs(jiffies), diff1;
1680 int i;
1681
1682 diff1 = now - dev_priv->last_time1;
1683 /*
1684 * sysctl(8) reads the value of sysctl twice in rapid
1685 * succession. There is high chance that it happens in the
1686 * same timer tick. Use the cached value to not divide by
1687 * zero and give the hw a chance to gather more samples.
1688 */
1689 if (diff1 <= 10)
1690 return (dev_priv->chipset_power);
1691
1692 count1 = I915_READ(DMIEC);
1693 count2 = I915_READ(DDREC);
1694 count3 = I915_READ(CSIEC);
1695
1696 total_count = count1 + count2 + count3;
1697
1698 /* FIXME: handle per-counter overflow */
1699 if (total_count < dev_priv->last_count1) {
1700 diff = ~0UL - dev_priv->last_count1;
1701 diff += total_count;
1702 } else {
1703 diff = total_count - dev_priv->last_count1;
1704 }
1705
1706 for (i = 0; i < DRM_ARRAY_SIZE(cparams); i++) {
1707 if (cparams[i].i == dev_priv->c_m &&
1708 cparams[i].t == dev_priv->r_t) {
1709 m = cparams[i].m;
1710 c = cparams[i].c;
1711 break;
1712 }
1713 }
1714
1715 diff = diff / diff1;
1716 ret = ((m * diff) + c);
1717 ret = ret / 10;
1718
1719 dev_priv->last_count1 = total_count;
1720 dev_priv->last_time1 = now;
1721
1722 dev_priv->chipset_power = ret;
1723 return (ret);
1724 }
1725
i915_mch_val(struct drm_i915_private * dev_priv)1726 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
1727 {
1728 unsigned long m, x, b;
1729 u32 tsfs;
1730
1731 tsfs = I915_READ(TSFS);
1732
1733 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
1734 x = I915_READ8(I915_TR1);
1735
1736 b = tsfs & TSFS_INTR_MASK;
1737
1738 return ((m * x) / 127) - b;
1739 }
1740
pvid_to_extvid(struct drm_i915_private * dev_priv,u8 pxvid)1741 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
1742 {
1743 static const struct v_table {
1744 u16 vd; /* in .1 mil */
1745 u16 vm; /* in .1 mil */
1746 } v_table[] = {
1747 { 0, 0, },
1748 { 375, 0, },
1749 { 500, 0, },
1750 { 625, 0, },
1751 { 750, 0, },
1752 { 875, 0, },
1753 { 1000, 0, },
1754 { 1125, 0, },
1755 { 4125, 3000, },
1756 { 4125, 3000, },
1757 { 4125, 3000, },
1758 { 4125, 3000, },
1759 { 4125, 3000, },
1760 { 4125, 3000, },
1761 { 4125, 3000, },
1762 { 4125, 3000, },
1763 { 4125, 3000, },
1764 { 4125, 3000, },
1765 { 4125, 3000, },
1766 { 4125, 3000, },
1767 { 4125, 3000, },
1768 { 4125, 3000, },
1769 { 4125, 3000, },
1770 { 4125, 3000, },
1771 { 4125, 3000, },
1772 { 4125, 3000, },
1773 { 4125, 3000, },
1774 { 4125, 3000, },
1775 { 4125, 3000, },
1776 { 4125, 3000, },
1777 { 4125, 3000, },
1778 { 4125, 3000, },
1779 { 4250, 3125, },
1780 { 4375, 3250, },
1781 { 4500, 3375, },
1782 { 4625, 3500, },
1783 { 4750, 3625, },
1784 { 4875, 3750, },
1785 { 5000, 3875, },
1786 { 5125, 4000, },
1787 { 5250, 4125, },
1788 { 5375, 4250, },
1789 { 5500, 4375, },
1790 { 5625, 4500, },
1791 { 5750, 4625, },
1792 { 5875, 4750, },
1793 { 6000, 4875, },
1794 { 6125, 5000, },
1795 { 6250, 5125, },
1796 { 6375, 5250, },
1797 { 6500, 5375, },
1798 { 6625, 5500, },
1799 { 6750, 5625, },
1800 { 6875, 5750, },
1801 { 7000, 5875, },
1802 { 7125, 6000, },
1803 { 7250, 6125, },
1804 { 7375, 6250, },
1805 { 7500, 6375, },
1806 { 7625, 6500, },
1807 { 7750, 6625, },
1808 { 7875, 6750, },
1809 { 8000, 6875, },
1810 { 8125, 7000, },
1811 { 8250, 7125, },
1812 { 8375, 7250, },
1813 { 8500, 7375, },
1814 { 8625, 7500, },
1815 { 8750, 7625, },
1816 { 8875, 7750, },
1817 { 9000, 7875, },
1818 { 9125, 8000, },
1819 { 9250, 8125, },
1820 { 9375, 8250, },
1821 { 9500, 8375, },
1822 { 9625, 8500, },
1823 { 9750, 8625, },
1824 { 9875, 8750, },
1825 { 10000, 8875, },
1826 { 10125, 9000, },
1827 { 10250, 9125, },
1828 { 10375, 9250, },
1829 { 10500, 9375, },
1830 { 10625, 9500, },
1831 { 10750, 9625, },
1832 { 10875, 9750, },
1833 { 11000, 9875, },
1834 { 11125, 10000, },
1835 { 11250, 10125, },
1836 { 11375, 10250, },
1837 { 11500, 10375, },
1838 { 11625, 10500, },
1839 { 11750, 10625, },
1840 { 11875, 10750, },
1841 { 12000, 10875, },
1842 { 12125, 11000, },
1843 { 12250, 11125, },
1844 { 12375, 11250, },
1845 { 12500, 11375, },
1846 { 12625, 11500, },
1847 { 12750, 11625, },
1848 { 12875, 11750, },
1849 { 13000, 11875, },
1850 { 13125, 12000, },
1851 { 13250, 12125, },
1852 { 13375, 12250, },
1853 { 13500, 12375, },
1854 { 13625, 12500, },
1855 { 13750, 12625, },
1856 { 13875, 12750, },
1857 { 14000, 12875, },
1858 { 14125, 13000, },
1859 { 14250, 13125, },
1860 { 14375, 13250, },
1861 { 14500, 13375, },
1862 { 14625, 13500, },
1863 { 14750, 13625, },
1864 { 14875, 13750, },
1865 { 15000, 13875, },
1866 { 15125, 14000, },
1867 { 15250, 14125, },
1868 { 15375, 14250, },
1869 { 15500, 14375, },
1870 { 15625, 14500, },
1871 { 15750, 14625, },
1872 { 15875, 14750, },
1873 { 16000, 14875, },
1874 { 16125, 15000, },
1875 };
1876 if (dev_priv->info->is_mobile)
1877 return v_table[pxvid].vm;
1878 else
1879 return v_table[pxvid].vd;
1880 }
1881
i915_update_gfx_val(struct drm_i915_private * dev_priv)1882 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
1883 {
1884 struct timespec now, diff1;
1885 u64 diff;
1886 unsigned long diffms;
1887 u32 count;
1888
1889 if (dev_priv->info->gen != 5)
1890 return;
1891
1892 nanotime(&now);
1893 diff1 = now;
1894 timespecsub(&diff1, &dev_priv->last_time2);
1895
1896 /* Don't divide by 0 */
1897 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
1898 if (!diffms)
1899 return;
1900
1901 count = I915_READ(GFXEC);
1902
1903 if (count < dev_priv->last_count2) {
1904 diff = ~0UL - dev_priv->last_count2;
1905 diff += count;
1906 } else {
1907 diff = count - dev_priv->last_count2;
1908 }
1909
1910 dev_priv->last_count2 = count;
1911 dev_priv->last_time2 = now;
1912
1913 /* More magic constants... */
1914 diff = diff * 1181;
1915 diff = diff / (diffms * 10);
1916 dev_priv->gfx_power = diff;
1917 }
1918
i915_gfx_val(struct drm_i915_private * dev_priv)1919 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
1920 {
1921 unsigned long t, corr, state1, corr2, state2;
1922 u32 pxvid, ext_v;
1923
1924 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4));
1925 pxvid = (pxvid >> 24) & 0x7f;
1926 ext_v = pvid_to_extvid(dev_priv, pxvid);
1927
1928 state1 = ext_v;
1929
1930 t = i915_mch_val(dev_priv);
1931
1932 /* Revel in the empirically derived constants */
1933
1934 /* Correction factor in 1/100000 units */
1935 if (t > 80)
1936 corr = ((t * 2349) + 135940);
1937 else if (t >= 50)
1938 corr = ((t * 964) + 29317);
1939 else /* < 50 */
1940 corr = ((t * 301) + 1004);
1941
1942 corr = corr * ((150142 * state1) / 10000 - 78642);
1943 corr /= 100000;
1944 corr2 = (corr * dev_priv->corr);
1945
1946 state2 = (corr2 * state1) / 10000;
1947 state2 /= 100; /* convert to mW */
1948
1949 i915_update_gfx_val(dev_priv);
1950
1951 return dev_priv->gfx_power + state2;
1952 }
1953
1954 /**
1955 * i915_read_mch_val - return value for IPS use
1956 *
1957 * Calculate and return a value for the IPS driver to use when deciding whether
1958 * we have thermal and power headroom to increase CPU or GPU power budget.
1959 */
i915_read_mch_val(void)1960 unsigned long i915_read_mch_val(void)
1961 {
1962 struct drm_i915_private *dev_priv;
1963 unsigned long chipset_val, graphics_val, ret = 0;
1964
1965 mtx_lock(&mchdev_lock);
1966 if (!i915_mch_dev)
1967 goto out_unlock;
1968 dev_priv = i915_mch_dev;
1969
1970 chipset_val = i915_chipset_val(dev_priv);
1971 graphics_val = i915_gfx_val(dev_priv);
1972
1973 ret = chipset_val + graphics_val;
1974
1975 out_unlock:
1976 mtx_unlock(&mchdev_lock);
1977
1978 return ret;
1979 }
1980
1981 /**
1982 * i915_gpu_raise - raise GPU frequency limit
1983 *
1984 * Raise the limit; IPS indicates we have thermal headroom.
1985 */
i915_gpu_raise(void)1986 bool i915_gpu_raise(void)
1987 {
1988 struct drm_i915_private *dev_priv;
1989 bool ret = true;
1990
1991 mtx_lock(&mchdev_lock);
1992 if (!i915_mch_dev) {
1993 ret = false;
1994 goto out_unlock;
1995 }
1996 dev_priv = i915_mch_dev;
1997
1998 if (dev_priv->max_delay > dev_priv->fmax)
1999 dev_priv->max_delay--;
2000
2001 out_unlock:
2002 mtx_unlock(&mchdev_lock);
2003
2004 return ret;
2005 }
2006
2007 /**
2008 * i915_gpu_lower - lower GPU frequency limit
2009 *
2010 * IPS indicates we're close to a thermal limit, so throttle back the GPU
2011 * frequency maximum.
2012 */
i915_gpu_lower(void)2013 bool i915_gpu_lower(void)
2014 {
2015 struct drm_i915_private *dev_priv;
2016 bool ret = true;
2017
2018 mtx_lock(&mchdev_lock);
2019 if (!i915_mch_dev) {
2020 ret = false;
2021 goto out_unlock;
2022 }
2023 dev_priv = i915_mch_dev;
2024
2025 if (dev_priv->max_delay < dev_priv->min_delay)
2026 dev_priv->max_delay++;
2027
2028 out_unlock:
2029 mtx_unlock(&mchdev_lock);
2030
2031 return ret;
2032 }
2033
2034 /**
2035 * i915_gpu_busy - indicate GPU business to IPS
2036 *
2037 * Tell the IPS driver whether or not the GPU is busy.
2038 */
i915_gpu_busy(void)2039 bool i915_gpu_busy(void)
2040 {
2041 struct drm_i915_private *dev_priv;
2042 bool ret = false;
2043
2044 mtx_lock(&mchdev_lock);
2045 if (!i915_mch_dev)
2046 goto out_unlock;
2047 dev_priv = i915_mch_dev;
2048
2049 ret = dev_priv->busy;
2050
2051 out_unlock:
2052 mtx_unlock(&mchdev_lock);
2053
2054 return ret;
2055 }
2056
2057 /**
2058 * i915_gpu_turbo_disable - disable graphics turbo
2059 *
2060 * Disable graphics turbo by resetting the max frequency and setting the
2061 * current frequency to the default.
2062 */
i915_gpu_turbo_disable(void)2063 bool i915_gpu_turbo_disable(void)
2064 {
2065 struct drm_i915_private *dev_priv;
2066 bool ret = true;
2067
2068 mtx_lock(&mchdev_lock);
2069 if (!i915_mch_dev) {
2070 ret = false;
2071 goto out_unlock;
2072 }
2073 dev_priv = i915_mch_dev;
2074
2075 dev_priv->max_delay = dev_priv->fstart;
2076
2077 if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart))
2078 ret = false;
2079
2080 out_unlock:
2081 mtx_unlock(&mchdev_lock);
2082
2083 return ret;
2084 }
2085