1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #include "drmP.h"
30 #include "drm.h"
31 #include "i915_drm.h"
32 #include "i915_drv.h"
33
34 /* Really want an OS-independent resettable timer. Would like to have
35 * this loop run for (eg) 3 sec, but have the timer reset every time
36 * the head pointer changes, so that EBUSY only happens if the ring
37 * actually stalls for (eg) 3 seconds.
38 */
i915_wait_ring(struct drm_device * dev,int n,const char * caller)39 int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
40 {
41 drm_i915_private_t *dev_priv = dev->dev_private;
42 drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
43 u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
44 u32 acthd_reg = IS_I965G(dev) ? ACTHD_I965 : ACTHD;
45 u32 last_acthd = I915_READ(acthd_reg);
46 u32 acthd;
47 int i;
48
49 for (i = 0; i < 100000; i++) {
50 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
51 acthd = I915_READ(acthd_reg);
52 ring->space = ring->head - (ring->tail + 8);
53 if (ring->space < 0)
54 ring->space += ring->Size;
55 if (ring->space >= n)
56 return 0;
57
58 if (dev_priv->sarea_priv)
59 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
60
61 if (ring->head != last_head)
62 i = 0;
63
64 if (acthd != last_acthd)
65 i = 0;
66
67 last_head = ring->head;
68 last_acthd = acthd;
69 DRM_UDELAY(10 * 1000);
70 }
71
72 return -EBUSY;
73 }
74
75 /**
76 * Sets up the hardware status page for devices that need a physical address
77 * in the register.
78 */
i915_init_phys_hws(struct drm_device * dev)79 static int i915_init_phys_hws(struct drm_device *dev)
80 {
81 drm_i915_private_t *dev_priv = dev->dev_private;
82
83 /* Program Hardware Status Page */
84 DRM_UNLOCK();
85 dev_priv->status_page_dmah =
86 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
87 DRM_LOCK();
88 if (!dev_priv->status_page_dmah) {
89 DRM_ERROR("Can not allocate hardware status page\n");
90 return -ENOMEM;
91 }
92 dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
93 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
94
95 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
96
97 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
98 DRM_DEBUG("Enabled hardware status page\n");
99 return 0;
100 }
101
102 /**
103 * Frees the hardware status page, whether it's a physical address or a virtual
104 * address set up by the X Server.
105 */
i915_free_hws(struct drm_device * dev)106 static void i915_free_hws(struct drm_device *dev)
107 {
108 drm_i915_private_t *dev_priv = dev->dev_private;
109 if (dev_priv->status_page_dmah) {
110 drm_pci_free(dev, dev_priv->status_page_dmah);
111 dev_priv->status_page_dmah = NULL;
112 }
113
114 if (dev_priv->status_gfx_addr) {
115 dev_priv->status_gfx_addr = 0;
116 drm_core_ioremapfree(&dev_priv->hws_map, dev);
117 }
118
119 /* Need to rewrite hardware status page */
120 I915_WRITE(HWS_PGA, 0x1ffff000);
121 }
122
i915_kernel_lost_context(struct drm_device * dev)123 void i915_kernel_lost_context(struct drm_device * dev)
124 {
125 drm_i915_private_t *dev_priv = dev->dev_private;
126 drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
127
128 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
129 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
130 ring->space = ring->head - (ring->tail + 8);
131 if (ring->space < 0)
132 ring->space += ring->Size;
133
134 if (ring->head == ring->tail && dev_priv->sarea_priv)
135 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
136 }
137
i915_dma_cleanup(struct drm_device * dev)138 static int i915_dma_cleanup(struct drm_device * dev)
139 {
140 drm_i915_private_t *dev_priv = dev->dev_private;
141 /* Make sure interrupts are disabled here because the uninstall ioctl
142 * may not have been called from userspace and after dev_private
143 * is freed, it's too late.
144 */
145 if (dev->irq_enabled)
146 drm_irq_uninstall(dev);
147
148 if (dev_priv->ring.virtual_start) {
149 drm_core_ioremapfree(&dev_priv->ring.map, dev);
150 dev_priv->ring.virtual_start = NULL;
151 dev_priv->ring.map.handle = NULL;
152 dev_priv->ring.map.size = 0;
153 }
154
155 /* Clear the HWS virtual address at teardown */
156 if (I915_NEED_GFX_HWS(dev))
157 i915_free_hws(dev);
158
159 return 0;
160 }
161
i915_initialize(struct drm_device * dev,drm_i915_init_t * init)162 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
163 {
164 drm_i915_private_t *dev_priv = dev->dev_private;
165
166 dev_priv->sarea = drm_getsarea(dev);
167 if (!dev_priv->sarea) {
168 DRM_ERROR("can not find sarea!\n");
169 i915_dma_cleanup(dev);
170 return -EINVAL;
171 }
172
173 dev_priv->sarea_priv = (drm_i915_sarea_t *)
174 ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset);
175
176 if (init->ring_size != 0) {
177 if (dev_priv->ring.ring_obj != NULL) {
178 i915_dma_cleanup(dev);
179 DRM_ERROR("Client tried to initialize ringbuffer in "
180 "GEM mode\n");
181 return -EINVAL;
182 }
183
184 dev_priv->ring.Size = init->ring_size;
185 dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
186
187 dev_priv->ring.map.offset = init->ring_start;
188 dev_priv->ring.map.size = init->ring_size;
189 dev_priv->ring.map.type = 0;
190 dev_priv->ring.map.flags = 0;
191 dev_priv->ring.map.mtrr = 0;
192
193 drm_core_ioremap(&dev_priv->ring.map, dev);
194
195 if (dev_priv->ring.map.handle == NULL) {
196 i915_dma_cleanup(dev);
197 DRM_ERROR("can not ioremap virtual address for"
198 " ring buffer\n");
199 return -ENOMEM;
200 }
201 }
202
203 dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
204
205 dev_priv->cpp = init->cpp;
206 dev_priv->back_offset = init->back_offset;
207 dev_priv->front_offset = init->front_offset;
208 dev_priv->current_page = 0;
209 dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
210
211 /* Allow hardware batchbuffers unless told otherwise.
212 */
213 dev_priv->allow_batchbuffer = 1;
214
215 return 0;
216 }
217
i915_dma_resume(struct drm_device * dev)218 static int i915_dma_resume(struct drm_device * dev)
219 {
220 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
221
222 DRM_DEBUG("\n");
223
224 if (!dev_priv->sarea) {
225 DRM_ERROR("can not find sarea!\n");
226 return -EINVAL;
227 }
228
229 if (dev_priv->ring.map.handle == NULL) {
230 DRM_ERROR("can not ioremap virtual address for"
231 " ring buffer\n");
232 return -ENOMEM;
233 }
234
235 /* Program Hardware Status Page */
236 if (!dev_priv->hw_status_page) {
237 DRM_ERROR("Can not find hardware status page\n");
238 return -EINVAL;
239 }
240 DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
241
242 if (dev_priv->status_gfx_addr != 0)
243 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
244 else
245 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
246 DRM_DEBUG("Enabled hardware status page\n");
247
248 return 0;
249 }
250
i915_dma_init(struct drm_device * dev,void * data,struct drm_file * file_priv)251 static int i915_dma_init(struct drm_device *dev, void *data,
252 struct drm_file *file_priv)
253 {
254 drm_i915_init_t *init = data;
255 int retcode = 0;
256
257 switch (init->func) {
258 case I915_INIT_DMA:
259 retcode = i915_initialize(dev, init);
260 break;
261 case I915_CLEANUP_DMA:
262 retcode = i915_dma_cleanup(dev);
263 break;
264 case I915_RESUME_DMA:
265 retcode = i915_dma_resume(dev);
266 break;
267 default:
268 retcode = -EINVAL;
269 break;
270 }
271
272 return retcode;
273 }
274
275 /* Implement basically the same security restrictions as hardware does
276 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
277 *
278 * Most of the calculations below involve calculating the size of a
279 * particular instruction. It's important to get the size right as
280 * that tells us where the next instruction to check is. Any illegal
281 * instruction detected will be given a size of zero, which is a
282 * signal to abort the rest of the buffer.
283 */
do_validate_cmd(int cmd)284 static int do_validate_cmd(int cmd)
285 {
286 switch (((cmd >> 29) & 0x7)) {
287 case 0x0:
288 switch ((cmd >> 23) & 0x3f) {
289 case 0x0:
290 return 1; /* MI_NOOP */
291 case 0x4:
292 return 1; /* MI_FLUSH */
293 default:
294 return 0; /* disallow everything else */
295 }
296 break;
297 case 0x1:
298 return 0; /* reserved */
299 case 0x2:
300 return (cmd & 0xff) + 2; /* 2d commands */
301 case 0x3:
302 if (((cmd >> 24) & 0x1f) <= 0x18)
303 return 1;
304
305 switch ((cmd >> 24) & 0x1f) {
306 case 0x1c:
307 return 1;
308 case 0x1d:
309 switch ((cmd >> 16) & 0xff) {
310 case 0x3:
311 return (cmd & 0x1f) + 2;
312 case 0x4:
313 return (cmd & 0xf) + 2;
314 default:
315 return (cmd & 0xffff) + 2;
316 }
317 case 0x1e:
318 if (cmd & (1 << 23))
319 return (cmd & 0xffff) + 1;
320 else
321 return 1;
322 case 0x1f:
323 if ((cmd & (1 << 23)) == 0) /* inline vertices */
324 return (cmd & 0x1ffff) + 2;
325 else if (cmd & (1 << 17)) /* indirect random */
326 if ((cmd & 0xffff) == 0)
327 return 0; /* unknown length, too hard */
328 else
329 return (((cmd & 0xffff) + 1) / 2) + 1;
330 else
331 return 2; /* indirect sequential */
332 default:
333 return 0;
334 }
335 default:
336 return 0;
337 }
338
339 return 0;
340 }
341
validate_cmd(int cmd)342 static int validate_cmd(int cmd)
343 {
344 int ret = do_validate_cmd(cmd);
345
346 /* printk("validate_cmd( %x ): %d\n", cmd, ret); */
347
348 return ret;
349 }
350
i915_emit_cmds(struct drm_device * dev,int __user * buffer,int dwords)351 static int i915_emit_cmds(struct drm_device *dev, int __user *buffer,
352 int dwords)
353 {
354 drm_i915_private_t *dev_priv = dev->dev_private;
355 int i;
356 RING_LOCALS;
357
358 if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
359 return -EINVAL;
360
361 BEGIN_LP_RING((dwords+1)&~1);
362
363 for (i = 0; i < dwords;) {
364 int cmd, sz;
365
366 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
367 return -EINVAL;
368
369 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
370 return -EINVAL;
371
372 OUT_RING(cmd);
373
374 while (++i, --sz) {
375 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
376 sizeof(cmd))) {
377 return -EINVAL;
378 }
379 OUT_RING(cmd);
380 }
381 }
382
383 if (dwords & 1)
384 OUT_RING(0);
385
386 ADVANCE_LP_RING();
387
388 return 0;
389 }
390
i915_emit_box(struct drm_device * dev,struct drm_clip_rect __user * boxes,int i,int DR1,int DR4)391 int i915_emit_box(struct drm_device * dev,
392 struct drm_clip_rect __user * boxes,
393 int i, int DR1, int DR4)
394 {
395 drm_i915_private_t *dev_priv = dev->dev_private;
396 struct drm_clip_rect box;
397 RING_LOCALS;
398
399 if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
400 return -EFAULT;
401 }
402
403 if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
404 DRM_ERROR("Bad box %d,%d..%d,%d\n",
405 box.x1, box.y1, box.x2, box.y2);
406 return -EINVAL;
407 }
408
409 if (IS_I965G(dev)) {
410 BEGIN_LP_RING(4);
411 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
412 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
413 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
414 OUT_RING(DR4);
415 ADVANCE_LP_RING();
416 } else {
417 BEGIN_LP_RING(6);
418 OUT_RING(GFX_OP_DRAWRECT_INFO);
419 OUT_RING(DR1);
420 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
421 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
422 OUT_RING(DR4);
423 OUT_RING(0);
424 ADVANCE_LP_RING();
425 }
426
427 return 0;
428 }
429
430 /* XXX: Emitting the counter should really be moved to part of the IRQ
431 * emit. For now, do it in both places:
432 */
433
i915_emit_breadcrumb(struct drm_device * dev)434 static void i915_emit_breadcrumb(struct drm_device *dev)
435 {
436 drm_i915_private_t *dev_priv = dev->dev_private;
437 RING_LOCALS;
438
439 dev_priv->counter++;
440 if (dev_priv->counter > 0x7FFFFFFFUL)
441 dev_priv->counter = 0;
442 if (dev_priv->sarea_priv)
443 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
444
445 BEGIN_LP_RING(4);
446 OUT_RING(MI_STORE_DWORD_INDEX);
447 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
448 OUT_RING(dev_priv->counter);
449 OUT_RING(0);
450 ADVANCE_LP_RING();
451 }
452
i915_dispatch_cmdbuffer(struct drm_device * dev,drm_i915_cmdbuffer_t * cmd)453 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
454 drm_i915_cmdbuffer_t * cmd)
455 {
456 int nbox = cmd->num_cliprects;
457 int i = 0, count, ret;
458
459 if (cmd->sz & 0x3) {
460 DRM_ERROR("alignment\n");
461 return -EINVAL;
462 }
463
464 i915_kernel_lost_context(dev);
465
466 count = nbox ? nbox : 1;
467
468 for (i = 0; i < count; i++) {
469 if (i < nbox) {
470 ret = i915_emit_box(dev, cmd->cliprects, i,
471 cmd->DR1, cmd->DR4);
472 if (ret)
473 return ret;
474 }
475
476 ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4);
477 if (ret)
478 return ret;
479 }
480
481 i915_emit_breadcrumb(dev);
482 return 0;
483 }
484
i915_dispatch_batchbuffer(struct drm_device * dev,drm_i915_batchbuffer_t * batch)485 static int i915_dispatch_batchbuffer(struct drm_device * dev,
486 drm_i915_batchbuffer_t * batch)
487 {
488 drm_i915_private_t *dev_priv = dev->dev_private;
489 struct drm_clip_rect __user *boxes = batch->cliprects;
490 int nbox = batch->num_cliprects;
491 int i = 0, count;
492 RING_LOCALS;
493
494 if ((batch->start | batch->used) & 0x7) {
495 DRM_ERROR("alignment\n");
496 return -EINVAL;
497 }
498
499 i915_kernel_lost_context(dev);
500
501 count = nbox ? nbox : 1;
502
503 for (i = 0; i < count; i++) {
504 if (i < nbox) {
505 int ret = i915_emit_box(dev, boxes, i,
506 batch->DR1, batch->DR4);
507 if (ret)
508 return ret;
509 }
510
511 if (!IS_I830(dev) && !IS_845G(dev)) {
512 BEGIN_LP_RING(2);
513 if (IS_I965G(dev)) {
514 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
515 OUT_RING(batch->start);
516 } else {
517 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
518 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
519 }
520 ADVANCE_LP_RING();
521 } else {
522 BEGIN_LP_RING(4);
523 OUT_RING(MI_BATCH_BUFFER);
524 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
525 OUT_RING(batch->start + batch->used - 4);
526 OUT_RING(0);
527 ADVANCE_LP_RING();
528 }
529 }
530
531 i915_emit_breadcrumb(dev);
532
533 return 0;
534 }
535
i915_dispatch_flip(struct drm_device * dev)536 static int i915_dispatch_flip(struct drm_device * dev)
537 {
538 drm_i915_private_t *dev_priv = dev->dev_private;
539 RING_LOCALS;
540
541 if (!dev_priv->sarea_priv)
542 return -EINVAL;
543
544 DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
545 __func__,
546 dev_priv->current_page,
547 dev_priv->sarea_priv->pf_current_page);
548
549 i915_kernel_lost_context(dev);
550
551 BEGIN_LP_RING(2);
552 OUT_RING(MI_FLUSH | MI_READ_FLUSH);
553 OUT_RING(0);
554 ADVANCE_LP_RING();
555
556 BEGIN_LP_RING(6);
557 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
558 OUT_RING(0);
559 if (dev_priv->current_page == 0) {
560 OUT_RING(dev_priv->back_offset);
561 dev_priv->current_page = 1;
562 } else {
563 OUT_RING(dev_priv->front_offset);
564 dev_priv->current_page = 0;
565 }
566 OUT_RING(0);
567 ADVANCE_LP_RING();
568
569 BEGIN_LP_RING(2);
570 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
571 OUT_RING(0);
572 ADVANCE_LP_RING();
573
574 dev_priv->sarea_priv->last_enqueue = dev_priv->counter++;
575
576 BEGIN_LP_RING(4);
577 OUT_RING(MI_STORE_DWORD_INDEX);
578 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
579 OUT_RING(dev_priv->counter);
580 OUT_RING(0);
581 ADVANCE_LP_RING();
582
583 dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
584 return 0;
585 }
586
i915_quiescent(struct drm_device * dev)587 static int i915_quiescent(struct drm_device * dev)
588 {
589 drm_i915_private_t *dev_priv = dev->dev_private;
590
591 i915_kernel_lost_context(dev);
592 return i915_wait_ring(dev, dev_priv->ring.Size - 8, __func__);
593 }
594
i915_flush_ioctl(struct drm_device * dev,void * data,struct drm_file * file_priv)595 static int i915_flush_ioctl(struct drm_device *dev, void *data,
596 struct drm_file *file_priv)
597 {
598 int ret;
599
600 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
601
602 ret = i915_quiescent(dev);
603
604 return ret;
605 }
606
i915_batchbuffer(struct drm_device * dev,void * data,struct drm_file * file_priv)607 static int i915_batchbuffer(struct drm_device *dev, void *data,
608 struct drm_file *file_priv)
609 {
610 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
611 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
612 dev_priv->sarea_priv;
613 drm_i915_batchbuffer_t *batch = data;
614 size_t cliplen;
615 int ret;
616
617 if (!dev_priv->allow_batchbuffer) {
618 DRM_ERROR("Batchbuffer ioctl disabled\n");
619 return -EINVAL;
620 }
621
622 DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
623 batch->start, batch->used, batch->num_cliprects);
624
625 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
626
627 DRM_UNLOCK();
628 cliplen = batch->num_cliprects * sizeof(struct drm_clip_rect);
629 if (batch->num_cliprects && DRM_VERIFYAREA_READ(batch->cliprects,
630 cliplen)) {
631 DRM_LOCK();
632 return -EFAULT;
633 }
634 if (batch->num_cliprects) {
635 ret = vslock(batch->cliprects, cliplen);
636 if (ret) {
637 DRM_ERROR("Fault wiring cliprects\n");
638 DRM_LOCK();
639 return -EFAULT;
640 }
641 }
642 DRM_LOCK();
643
644 ret = i915_dispatch_batchbuffer(dev, batch);
645
646 if (sarea_priv)
647 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
648
649 DRM_UNLOCK();
650 if (batch->num_cliprects)
651 vsunlock(batch->cliprects, cliplen);
652 DRM_LOCK();
653
654 return ret;
655 }
656
i915_cmdbuffer(struct drm_device * dev,void * data,struct drm_file * file_priv)657 static int i915_cmdbuffer(struct drm_device *dev, void *data,
658 struct drm_file *file_priv)
659 {
660 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
661 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
662 dev_priv->sarea_priv;
663 drm_i915_cmdbuffer_t *cmdbuf = data;
664 size_t cliplen;
665 int ret;
666
667 DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
668 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
669
670 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
671
672 DRM_UNLOCK();
673 cliplen = cmdbuf->num_cliprects * sizeof(struct drm_clip_rect);
674 if (cmdbuf->num_cliprects && DRM_VERIFYAREA_READ(cmdbuf->cliprects,
675 cliplen)) {
676 DRM_ERROR("Fault accessing cliprects\n");
677 DRM_LOCK();
678 return -EFAULT;
679 }
680 if (cmdbuf->num_cliprects) {
681 ret = vslock(cmdbuf->cliprects, cliplen);
682 if (ret) {
683 DRM_ERROR("Fault wiring cliprects\n");
684 DRM_LOCK();
685 return -EFAULT;
686 }
687 ret = vslock(cmdbuf->buf, cmdbuf->sz);
688 if (ret) {
689 vsunlock(cmdbuf->cliprects, cliplen);
690 DRM_ERROR("Fault wiring cmds\n");
691 DRM_LOCK();
692 return -EFAULT;
693 }
694 }
695 DRM_LOCK();
696
697 ret = i915_dispatch_cmdbuffer(dev, cmdbuf);
698 DRM_UNLOCK();
699 if (cmdbuf->num_cliprects) {
700 vsunlock(cmdbuf->buf, cmdbuf->sz);
701 vsunlock(cmdbuf->cliprects, cliplen);
702 }
703 DRM_LOCK();
704 if (ret) {
705 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
706 return ret;
707 }
708
709 if (sarea_priv)
710 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
711 return 0;
712 }
713
i915_flip_bufs(struct drm_device * dev,void * data,struct drm_file * file_priv)714 static int i915_flip_bufs(struct drm_device *dev, void *data,
715 struct drm_file *file_priv)
716 {
717 int ret;
718
719 DRM_DEBUG("%s\n", __func__);
720
721 LOCK_TEST_WITH_RETURN(dev, file_priv);
722
723 ret = i915_dispatch_flip(dev);
724
725 return ret;
726 }
727
i915_getparam(struct drm_device * dev,void * data,struct drm_file * file_priv)728 static int i915_getparam(struct drm_device *dev, void *data,
729 struct drm_file *file_priv)
730 {
731 drm_i915_private_t *dev_priv = dev->dev_private;
732 drm_i915_getparam_t *param = data;
733 int value;
734
735 if (!dev_priv) {
736 DRM_ERROR("called with no initialization\n");
737 return -EINVAL;
738 }
739
740 switch (param->param) {
741 case I915_PARAM_IRQ_ACTIVE:
742 value = dev->irq_enabled ? 1 : 0;
743 break;
744 case I915_PARAM_ALLOW_BATCHBUFFER:
745 value = dev_priv->allow_batchbuffer ? 1 : 0;
746 break;
747 case I915_PARAM_LAST_DISPATCH:
748 value = READ_BREADCRUMB(dev_priv);
749 break;
750 case I915_PARAM_CHIPSET_ID:
751 value = dev->pci_device;
752 break;
753 case I915_PARAM_HAS_GEM:
754 value = 0;
755 break;
756 default:
757 DRM_ERROR("Unknown parameter %d\n", param->param);
758 return -EINVAL;
759 }
760
761 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
762 DRM_ERROR("DRM_COPY_TO_USER failed\n");
763 return -EFAULT;
764 }
765
766 return 0;
767 }
768
i915_setparam(struct drm_device * dev,void * data,struct drm_file * file_priv)769 static int i915_setparam(struct drm_device *dev, void *data,
770 struct drm_file *file_priv)
771 {
772 drm_i915_private_t *dev_priv = dev->dev_private;
773 drm_i915_setparam_t *param = data;
774
775 if (!dev_priv) {
776 DRM_ERROR("called with no initialization\n");
777 return -EINVAL;
778 }
779
780 switch (param->param) {
781 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
782 break;
783 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
784 dev_priv->tex_lru_log_granularity = param->value;
785 break;
786 case I915_SETPARAM_ALLOW_BATCHBUFFER:
787 dev_priv->allow_batchbuffer = param->value;
788 break;
789 default:
790 DRM_ERROR("unknown parameter %d\n", param->param);
791 return -EINVAL;
792 }
793
794 return 0;
795 }
796
i915_set_status_page(struct drm_device * dev,void * data,struct drm_file * file_priv)797 static int i915_set_status_page(struct drm_device *dev, void *data,
798 struct drm_file *file_priv)
799 {
800 drm_i915_private_t *dev_priv = dev->dev_private;
801 drm_i915_hws_addr_t *hws = data;
802
803 if (!I915_NEED_GFX_HWS(dev))
804 return -EINVAL;
805
806 if (!dev_priv) {
807 DRM_ERROR("called with no initialization\n");
808 return -EINVAL;
809 }
810
811 DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws->addr);
812
813 dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12);
814
815 dev_priv->hws_map.offset = dev->agp->base + hws->addr;
816 dev_priv->hws_map.size = 4*1024;
817 dev_priv->hws_map.type = 0;
818 dev_priv->hws_map.flags = 0;
819 dev_priv->hws_map.mtrr = 0;
820
821 drm_core_ioremap(&dev_priv->hws_map, dev);
822 if (dev_priv->hws_map.handle == NULL) {
823 i915_dma_cleanup(dev);
824 dev_priv->status_gfx_addr = 0;
825 DRM_ERROR("can not ioremap virtual address for"
826 " G33 hw status page\n");
827 return -ENOMEM;
828 }
829 dev_priv->hw_status_page = dev_priv->hws_map.handle;
830
831 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
832 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
833 DRM_DEBUG("load hws HWS_PGA with gfx mem 0x%x\n",
834 dev_priv->status_gfx_addr);
835 DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
836 return 0;
837 }
838
i915_driver_load(struct drm_device * dev,unsigned long flags)839 int i915_driver_load(struct drm_device *dev, unsigned long flags)
840 {
841 struct drm_i915_private *dev_priv = dev->dev_private;
842 unsigned long base, size;
843 int ret = 0, mmio_bar = IS_I9XX(dev) ? 0 : 1;
844
845 /* i915 has 4 more counters */
846 dev->counters += 4;
847 dev->types[6] = _DRM_STAT_IRQ;
848 dev->types[7] = _DRM_STAT_PRIMARY;
849 dev->types[8] = _DRM_STAT_SECONDARY;
850 dev->types[9] = _DRM_STAT_DMA;
851
852 dev_priv = drm_alloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER);
853 if (dev_priv == NULL)
854 return -ENOMEM;
855
856 memset(dev_priv, 0, sizeof(drm_i915_private_t));
857
858 dev->dev_private = (void *)dev_priv;
859 dev_priv->dev = dev;
860
861 /* Add register map (needed for suspend/resume) */
862 base = drm_get_resource_start(dev, mmio_bar);
863 size = drm_get_resource_len(dev, mmio_bar);
864
865 ret = drm_addmap(dev, base, size, _DRM_REGISTERS,
866 _DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio_map);
867
868 if (IS_GM45(dev))
869 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
870 else
871 dev->driver->get_vblank_counter = i915_get_vblank_counter;
872
873 #ifdef I915_HAVE_GEM
874 i915_gem_load(dev);
875 #endif
876 /* Init HWS */
877 if (!I915_NEED_GFX_HWS(dev)) {
878 ret = i915_init_phys_hws(dev);
879 if (ret != 0)
880 return ret;
881 }
882 #ifdef __linux__
883 /* On the 945G/GM, the chipset reports the MSI capability on the
884 * integrated graphics even though the support isn't actually there
885 * according to the published specs. It doesn't appear to function
886 * correctly in testing on 945G.
887 * This may be a side effect of MSI having been made available for PEG
888 * and the registers being closely associated.
889 *
890 * According to chipset errata, on the 965GM, MSI interrupts may
891 * be lost or delayed
892 */
893 if (!IS_I945G(dev) && !IS_I945GM(dev) && !IS_I965GM(dev))
894 if (pci_enable_msi(dev->pdev))
895 DRM_ERROR("failed to enable MSI\n");
896
897 intel_opregion_init(dev);
898 #endif
899 DRM_SPININIT(&dev_priv->user_irq_lock, "userirq");
900
901 ret = drm_vblank_init(dev, I915_NUM_PIPE);
902
903 if (ret) {
904 (void) i915_driver_unload(dev);
905 return ret;
906 }
907
908 return ret;
909 }
910
i915_driver_unload(struct drm_device * dev)911 int i915_driver_unload(struct drm_device *dev)
912 {
913 struct drm_i915_private *dev_priv = dev->dev_private;
914
915 i915_free_hws(dev);
916
917 drm_rmmap(dev, dev_priv->mmio_map);
918 #ifdef __linux__
919 intel_opregion_free(dev);
920 #endif
921 DRM_SPINUNINIT(&dev_priv->user_irq_lock);
922
923 drm_free(dev->dev_private, sizeof(drm_i915_private_t),
924 DRM_MEM_DRIVER);
925
926 return 0;
927 }
928
i915_driver_open(struct drm_device * dev,struct drm_file * file_priv)929 int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
930 {
931 struct drm_i915_file_private *i915_file_priv;
932
933 DRM_DEBUG("\n");
934 i915_file_priv = (struct drm_i915_file_private *)
935 drm_alloc(sizeof(*i915_file_priv), DRM_MEM_FILES);
936
937 if (!i915_file_priv)
938 return -ENOMEM;
939
940 file_priv->driver_priv = i915_file_priv;
941
942 i915_file_priv->mm.last_gem_seqno = 0;
943 i915_file_priv->mm.last_gem_throttle_seqno = 0;
944
945 return 0;
946 }
947
i915_driver_lastclose(struct drm_device * dev)948 void i915_driver_lastclose(struct drm_device * dev)
949 {
950 drm_i915_private_t *dev_priv = dev->dev_private;
951
952 if (!dev_priv)
953 return;
954 #ifdef I915_HAVE_GEM
955 i915_gem_lastclose(dev);
956 #endif
957 if (dev_priv->agp_heap)
958 i915_mem_takedown(&(dev_priv->agp_heap));
959
960 i915_dma_cleanup(dev);
961 }
962
i915_driver_preclose(struct drm_device * dev,struct drm_file * file_priv)963 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
964 {
965 drm_i915_private_t *dev_priv = dev->dev_private;
966 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
967 }
968
i915_driver_postclose(struct drm_device * dev,struct drm_file * file_priv)969 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
970 {
971 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
972
973 drm_free(i915_file_priv, sizeof(*i915_file_priv), DRM_MEM_FILES);
974 }
975
976 struct drm_ioctl_desc i915_ioctls[] = {
977 DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
978 DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
979 DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
980 DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
981 DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
982 DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
983 DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
984 DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
985 DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
986 DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
987 DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
988 DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
989 DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
990 DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
991 DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH ),
992 DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
993 DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
994 #ifdef I915_HAVE_GEM
995 DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
996 DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
997 DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
998 DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
999 DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH),
1000 DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH),
1001 DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1002 DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1003 DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, 0),
1004 DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, 0),
1005 DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, 0),
1006 DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0),
1007 DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, 0),
1008 DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, 0),
1009 DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0),
1010 DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0),
1011 #endif
1012 };
1013
1014 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1015
1016 /**
1017 * Determine if the device really is AGP or not.
1018 *
1019 * All Intel graphics chipsets are treated as AGP, even if they are really
1020 * PCI-e.
1021 *
1022 * \param dev The device to be tested.
1023 *
1024 * \returns
1025 * A value of 1 is always retured to indictate every i9x5 is AGP.
1026 */
i915_driver_device_is_agp(struct drm_device * dev)1027 int i915_driver_device_is_agp(struct drm_device * dev)
1028 {
1029 return 1;
1030 }
1031