1 /*-
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * $FreeBSD$
27 *
28 */
29
30 #ifndef _PCIVAR_H_
31 #define _PCIVAR_H_
32
33 #include <sys/queue.h>
34
35 /* some PCI bus constants */
36 #define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */
37 #define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */
38 #define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */
39
40 typedef uint64_t pci_addr_t;
41
42 /* Config registers for PCI-PCI and PCI-Cardbus bridges. */
43 struct pcicfg_bridge {
44 uint8_t br_seclat;
45 uint8_t br_subbus;
46 uint8_t br_secbus;
47 uint8_t br_pribus;
48 uint16_t br_control;
49 };
50
51 /* Interesting values for PCI power management */
52 struct pcicfg_pp {
53 uint16_t pp_cap; /* PCI power management capabilities */
54 uint8_t pp_status; /* conf. space addr. of PM control/status reg */
55 uint8_t pp_bse; /* conf. space addr. of PM BSE reg */
56 uint8_t pp_data; /* conf. space addr. of PM data reg */
57 };
58
59 struct pci_map {
60 pci_addr_t pm_value; /* Raw BAR value */
61 pci_addr_t pm_size;
62 uint8_t pm_reg;
63 STAILQ_ENTRY(pci_map) pm_link;
64 };
65
66 struct vpd_readonly {
67 char keyword[2];
68 char *value;
69 int len;
70 };
71
72 struct vpd_write {
73 char keyword[2];
74 char *value;
75 int start;
76 int len;
77 };
78
79 struct pcicfg_vpd {
80 uint8_t vpd_reg; /* base register, + 2 for addr, + 4 data */
81 char vpd_cached;
82 char *vpd_ident; /* string identifier */
83 int vpd_rocnt;
84 struct vpd_readonly *vpd_ros;
85 int vpd_wcnt;
86 struct vpd_write *vpd_w;
87 };
88
89 /* Interesting values for PCI MSI */
90 struct pcicfg_msi {
91 uint16_t msi_ctrl; /* Message Control */
92 uint8_t msi_location; /* Offset of MSI capability registers. */
93 uint8_t msi_msgnum; /* Number of messages */
94 int msi_alloc; /* Number of allocated messages. */
95 uint64_t msi_addr; /* Contents of address register. */
96 uint16_t msi_data; /* Contents of data register. */
97 u_int msi_handlers;
98 };
99
100 /* Interesting values for PCI MSI-X */
101 struct msix_vector {
102 uint64_t mv_address; /* Contents of address register. */
103 uint32_t mv_data; /* Contents of data register. */
104 int mv_irq;
105 };
106
107 struct msix_table_entry {
108 u_int mte_vector; /* 1-based index into msix_vectors array. */
109 u_int mte_handlers;
110 };
111
112 struct pcicfg_msix {
113 uint16_t msix_ctrl; /* Message Control */
114 uint16_t msix_msgnum; /* Number of messages */
115 uint8_t msix_location; /* Offset of MSI-X capability registers. */
116 uint8_t msix_table_bar; /* BAR containing vector table. */
117 uint8_t msix_pba_bar; /* BAR containing PBA. */
118 uint32_t msix_table_offset;
119 uint32_t msix_pba_offset;
120 int msix_alloc; /* Number of allocated vectors. */
121 int msix_table_len; /* Length of virtual table. */
122 struct msix_table_entry *msix_table; /* Virtual table. */
123 struct msix_vector *msix_vectors; /* Array of allocated vectors. */
124 struct resource *msix_table_res; /* Resource containing vector table. */
125 struct resource *msix_pba_res; /* Resource containing PBA. */
126 };
127
128 /* Interesting values for HyperTransport */
129 struct pcicfg_ht {
130 uint8_t ht_slave; /* Non-zero if device is an HT slave. */
131 uint8_t ht_msimap; /* Offset of MSI mapping cap registers. */
132 uint16_t ht_msictrl; /* MSI mapping control */
133 uint64_t ht_msiaddr; /* MSI mapping base address */
134 };
135
136 /* Interesting values for PCI-express */
137 struct pcicfg_pcie {
138 uint8_t pcie_location; /* Offset of PCI-e capability registers. */
139 uint8_t pcie_type; /* Device type. */
140 uint16_t pcie_flags; /* Device capabilities register. */
141 uint16_t pcie_device_ctl; /* Device control register. */
142 uint16_t pcie_link_ctl; /* Link control register. */
143 uint16_t pcie_slot_ctl; /* Slot control register. */
144 uint16_t pcie_root_ctl; /* Root control register. */
145 uint16_t pcie_device_ctl2; /* Second device control register. */
146 uint16_t pcie_link_ctl2; /* Second link control register. */
147 uint16_t pcie_slot_ctl2; /* Second slot control register. */
148 };
149
150 struct pcicfg_pcix {
151 uint16_t pcix_command;
152 uint8_t pcix_location; /* Offset of PCI-X capability registers. */
153 };
154
155 /* config header information common to all header types */
156 typedef struct pcicfg {
157 struct device *dev; /* device which owns this */
158
159 STAILQ_HEAD(, pci_map) maps; /* BARs */
160
161 uint16_t subvendor; /* card vendor ID */
162 uint16_t subdevice; /* card device ID, assigned by card vendor */
163 uint16_t vendor; /* chip vendor ID */
164 uint16_t device; /* chip device ID, assigned by chip vendor */
165
166 uint16_t cmdreg; /* disable/enable chip and PCI options */
167 uint16_t statreg; /* supported PCI features and error state */
168
169 uint8_t baseclass; /* chip PCI class */
170 uint8_t subclass; /* chip PCI subclass */
171 uint8_t progif; /* chip PCI programming interface */
172 uint8_t revid; /* chip revision ID */
173
174 uint8_t hdrtype; /* chip config header type */
175 uint8_t cachelnsz; /* cache line size in 4byte units */
176 uint8_t intpin; /* PCI interrupt pin */
177 uint8_t intline; /* interrupt line (IRQ for PC arch) */
178
179 uint8_t mingnt; /* min. useful bus grant time in 250ns units */
180 uint8_t maxlat; /* max. tolerated bus grant latency in 250ns */
181 uint8_t lattimer; /* latency timer in units of 30ns bus cycles */
182
183 uint8_t mfdev; /* multi-function device (from hdrtype reg) */
184 uint8_t nummaps; /* actual number of PCI maps used */
185
186 uint32_t domain; /* PCI domain */
187 uint8_t bus; /* config space bus address */
188 uint8_t slot; /* config space slot address */
189 uint8_t func; /* config space function number */
190
191 struct pcicfg_bridge bridge; /* Bridges */
192 struct pcicfg_pp pp; /* Power management */
193 struct pcicfg_vpd vpd; /* Vital product data */
194 struct pcicfg_msi msi; /* PCI MSI */
195 struct pcicfg_msix msix; /* PCI MSI-X */
196 struct pcicfg_ht ht; /* HyperTransport */
197 struct pcicfg_pcie pcie; /* PCI Express */
198 struct pcicfg_pcix pcix; /* PCI-X */
199 } pcicfgregs;
200
201 /* additional type 1 device config header information (PCI to PCI bridge) */
202
203 #define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff)
204 #define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff)
205 #define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff)
206 #define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff)
207
208 typedef struct {
209 pci_addr_t pmembase; /* base address of prefetchable memory */
210 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */
211 uint32_t membase; /* base address of memory window */
212 uint32_t memlimit; /* topmost address of memory window */
213 uint32_t iobase; /* base address of port window */
214 uint32_t iolimit; /* topmost address of port window */
215 uint16_t secstat; /* secondary bus status register */
216 uint16_t bridgectl; /* bridge control register */
217 uint8_t seclat; /* CardBus latency timer */
218 } pcih1cfgregs;
219
220 /* additional type 2 device config header information (CardBus bridge) */
221
222 typedef struct {
223 uint32_t membase0; /* base address of memory window */
224 uint32_t memlimit0; /* topmost address of memory window */
225 uint32_t membase1; /* base address of memory window */
226 uint32_t memlimit1; /* topmost address of memory window */
227 uint32_t iobase0; /* base address of port window */
228 uint32_t iolimit0; /* topmost address of port window */
229 uint32_t iobase1; /* base address of port window */
230 uint32_t iolimit1; /* topmost address of port window */
231 uint32_t pccardif; /* PC Card 16bit IF legacy more base addr. */
232 uint16_t secstat; /* secondary bus status register */
233 uint16_t bridgectl; /* bridge control register */
234 uint8_t seclat; /* CardBus latency timer */
235 } pcih2cfgregs;
236
237 extern uint32_t pci_numdevs;
238
239 /* Only if the prerequisites are present */
240 #if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_)
241 struct pci_devinfo {
242 STAILQ_ENTRY(pci_devinfo) pci_links;
243 struct resource_list resources;
244 pcicfgregs cfg;
245 struct pci_conf conf;
246 };
247 #endif
248
249 #ifdef _SYS_BUS_H_
250
251 #include "pci_if.h"
252
253 enum pci_device_ivars {
254 PCI_IVAR_SUBVENDOR,
255 PCI_IVAR_SUBDEVICE,
256 PCI_IVAR_VENDOR,
257 PCI_IVAR_DEVICE,
258 PCI_IVAR_DEVID,
259 PCI_IVAR_CLASS,
260 PCI_IVAR_SUBCLASS,
261 PCI_IVAR_PROGIF,
262 PCI_IVAR_REVID,
263 PCI_IVAR_INTPIN,
264 PCI_IVAR_IRQ,
265 PCI_IVAR_DOMAIN,
266 PCI_IVAR_BUS,
267 PCI_IVAR_SLOT,
268 PCI_IVAR_FUNCTION,
269 PCI_IVAR_ETHADDR,
270 PCI_IVAR_CMDREG,
271 PCI_IVAR_CACHELNSZ,
272 PCI_IVAR_MINGNT,
273 PCI_IVAR_MAXLAT,
274 PCI_IVAR_LATTIMER
275 };
276
277 /*
278 * Simplified accessors for pci devices
279 */
280 #define PCI_ACCESSOR(var, ivar, type) \
281 __BUS_ACCESSOR(pci, var, PCI, ivar, type)
282
PCI_ACCESSOR(subvendor,SUBVENDOR,uint16_t)283 PCI_ACCESSOR(subvendor, SUBVENDOR, uint16_t)
284 PCI_ACCESSOR(subdevice, SUBDEVICE, uint16_t)
285 PCI_ACCESSOR(vendor, VENDOR, uint16_t)
286 PCI_ACCESSOR(device, DEVICE, uint16_t)
287 PCI_ACCESSOR(devid, DEVID, uint32_t)
288 PCI_ACCESSOR(class, CLASS, uint8_t)
289 PCI_ACCESSOR(subclass, SUBCLASS, uint8_t)
290 PCI_ACCESSOR(progif, PROGIF, uint8_t)
291 PCI_ACCESSOR(revid, REVID, uint8_t)
292 PCI_ACCESSOR(intpin, INTPIN, uint8_t)
293 PCI_ACCESSOR(irq, IRQ, uint8_t)
294 PCI_ACCESSOR(domain, DOMAIN, uint32_t)
295 PCI_ACCESSOR(bus, BUS, uint8_t)
296 PCI_ACCESSOR(slot, SLOT, uint8_t)
297 PCI_ACCESSOR(function, FUNCTION, uint8_t)
298 PCI_ACCESSOR(ether, ETHADDR, uint8_t *)
299 PCI_ACCESSOR(cmdreg, CMDREG, uint8_t)
300 PCI_ACCESSOR(cachelnsz, CACHELNSZ, uint8_t)
301 PCI_ACCESSOR(mingnt, MINGNT, uint8_t)
302 PCI_ACCESSOR(maxlat, MAXLAT, uint8_t)
303 PCI_ACCESSOR(lattimer, LATTIMER, uint8_t)
304
305 #undef PCI_ACCESSOR
306
307 /*
308 * Operations on configuration space.
309 */
310 static __inline uint32_t
311 pci_read_config(device_t dev, int reg, int width)
312 {
313 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width);
314 }
315
316 static __inline void
pci_write_config(device_t dev,int reg,uint32_t val,int width)317 pci_write_config(device_t dev, int reg, uint32_t val, int width)
318 {
319 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width);
320 }
321
322 /*
323 * Ivars for pci bridges.
324 */
325
326 /*typedef enum pci_device_ivars pcib_device_ivars;*/
327 enum pcib_device_ivars {
328 PCIB_IVAR_DOMAIN,
329 PCIB_IVAR_BUS
330 };
331
332 #define PCIB_ACCESSOR(var, ivar, type) \
333 __BUS_ACCESSOR(pcib, var, PCIB, ivar, type)
334
PCIB_ACCESSOR(domain,DOMAIN,uint32_t)335 PCIB_ACCESSOR(domain, DOMAIN, uint32_t)
336 PCIB_ACCESSOR(bus, BUS, uint32_t)
337
338 #undef PCIB_ACCESSOR
339
340 /*
341 * PCI interrupt validation. Invalid interrupt values such as 0 or 128
342 * on i386 or other platforms should be mapped out in the MD pcireadconf
343 * code and not here, since the only MI invalid IRQ is 255.
344 */
345 #define PCI_INVALID_IRQ 255
346 #define PCI_INTERRUPT_VALID(x) ((x) != PCI_INVALID_IRQ)
347
348 /*
349 * Convenience functions.
350 *
351 * These should be used in preference to manually manipulating
352 * configuration space.
353 */
354 static __inline int
355 pci_enable_busmaster(device_t dev)
356 {
357 return(PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev));
358 }
359
360 static __inline int
pci_disable_busmaster(device_t dev)361 pci_disable_busmaster(device_t dev)
362 {
363 return(PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev));
364 }
365
366 static __inline int
pci_enable_io(device_t dev,int space)367 pci_enable_io(device_t dev, int space)
368 {
369 return(PCI_ENABLE_IO(device_get_parent(dev), dev, space));
370 }
371
372 static __inline int
pci_disable_io(device_t dev,int space)373 pci_disable_io(device_t dev, int space)
374 {
375 return(PCI_DISABLE_IO(device_get_parent(dev), dev, space));
376 }
377
378 static __inline int
pci_get_vpd_ident(device_t dev,const char ** identptr)379 pci_get_vpd_ident(device_t dev, const char **identptr)
380 {
381 return(PCI_GET_VPD_IDENT(device_get_parent(dev), dev, identptr));
382 }
383
384 static __inline int
pci_get_vpd_readonly(device_t dev,const char * kw,const char ** vptr)385 pci_get_vpd_readonly(device_t dev, const char *kw, const char **vptr)
386 {
387 return(PCI_GET_VPD_READONLY(device_get_parent(dev), dev, kw, vptr));
388 }
389
390 /*
391 * Check if the address range falls within the VGA defined address range(s)
392 */
393 static __inline int
pci_is_vga_ioport_range(u_long start,u_long end)394 pci_is_vga_ioport_range(u_long start, u_long end)
395 {
396
397 return (((start >= 0x3b0 && end <= 0x3bb) ||
398 (start >= 0x3c0 && end <= 0x3df)) ? 1 : 0);
399 }
400
401 static __inline int
pci_is_vga_memory_range(u_long start,u_long end)402 pci_is_vga_memory_range(u_long start, u_long end)
403 {
404
405 return ((start >= 0xa0000 && end <= 0xbffff) ? 1 : 0);
406 }
407
408 /*
409 * PCI power states are as defined by ACPI:
410 *
411 * D0 State in which device is on and running. It is receiving full
412 * power from the system and delivering full functionality to the user.
413 * D1 Class-specific low-power state in which device context may or may not
414 * be lost. Buses in D1 cannot do anything to the bus that would force
415 * devices on that bus to lose context.
416 * D2 Class-specific low-power state in which device context may or may
417 * not be lost. Attains greater power savings than D1. Buses in D2
418 * can cause devices on that bus to lose some context. Devices in D2
419 * must be prepared for the bus to be in D2 or higher.
420 * D3 State in which the device is off and not running. Device context is
421 * lost. Power can be removed from the device.
422 */
423 #define PCI_POWERSTATE_D0 0
424 #define PCI_POWERSTATE_D1 1
425 #define PCI_POWERSTATE_D2 2
426 #define PCI_POWERSTATE_D3 3
427 #define PCI_POWERSTATE_UNKNOWN -1
428
429 static __inline int
pci_set_powerstate(device_t dev,int state)430 pci_set_powerstate(device_t dev, int state)
431 {
432 return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state);
433 }
434
435 static __inline int
pci_get_powerstate(device_t dev)436 pci_get_powerstate(device_t dev)
437 {
438 return PCI_GET_POWERSTATE(device_get_parent(dev), dev);
439 }
440
441 static __inline int
pci_find_cap(device_t dev,int capability,int * capreg)442 pci_find_cap(device_t dev, int capability, int *capreg)
443 {
444 return (PCI_FIND_CAP(device_get_parent(dev), dev, capability, capreg));
445 }
446
447 static __inline int
pci_find_extcap(device_t dev,int capability,int * capreg)448 pci_find_extcap(device_t dev, int capability, int *capreg)
449 {
450 return (PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg));
451 }
452
453 static __inline int
pci_find_htcap(device_t dev,int capability,int * capreg)454 pci_find_htcap(device_t dev, int capability, int *capreg)
455 {
456 return (PCI_FIND_HTCAP(device_get_parent(dev), dev, capability, capreg));
457 }
458
459 static __inline int
pci_alloc_msi(device_t dev,int * count)460 pci_alloc_msi(device_t dev, int *count)
461 {
462 return (PCI_ALLOC_MSI(device_get_parent(dev), dev, count));
463 }
464
465 static __inline int
pci_alloc_msix(device_t dev,int * count)466 pci_alloc_msix(device_t dev, int *count)
467 {
468 return (PCI_ALLOC_MSIX(device_get_parent(dev), dev, count));
469 }
470
471 static __inline int
pci_remap_msix(device_t dev,int count,const u_int * vectors)472 pci_remap_msix(device_t dev, int count, const u_int *vectors)
473 {
474 return (PCI_REMAP_MSIX(device_get_parent(dev), dev, count, vectors));
475 }
476
477 static __inline int
pci_release_msi(device_t dev)478 pci_release_msi(device_t dev)
479 {
480 return (PCI_RELEASE_MSI(device_get_parent(dev), dev));
481 }
482
483 static __inline int
pci_msi_count(device_t dev)484 pci_msi_count(device_t dev)
485 {
486 return (PCI_MSI_COUNT(device_get_parent(dev), dev));
487 }
488
489 static __inline int
pci_msix_count(device_t dev)490 pci_msix_count(device_t dev)
491 {
492 return (PCI_MSIX_COUNT(device_get_parent(dev), dev));
493 }
494
495 static __inline uint16_t
pci_get_rid(device_t dev)496 pci_get_rid(device_t dev)
497 {
498 return (PCI_GET_RID(device_get_parent(dev), dev));
499 }
500
501 device_t pci_find_bsf(uint8_t, uint8_t, uint8_t);
502 device_t pci_find_dbsf(uint32_t, uint8_t, uint8_t, uint8_t);
503 device_t pci_find_device(uint16_t, uint16_t);
504 device_t pci_find_class(uint8_t class, uint8_t subclass);
505
506 /* Can be used by drivers to manage the MSI-X table. */
507 int pci_pending_msix(device_t dev, u_int index);
508
509 int pci_msi_device_blacklisted(device_t dev);
510 int pci_msix_device_blacklisted(device_t dev);
511
512 void pci_ht_map_msi(device_t dev, uint64_t addr);
513
514 int pci_get_max_read_req(device_t dev);
515 void pci_restore_state(device_t dev);
516 void pci_save_state(device_t dev);
517 int pci_set_max_read_req(device_t dev, int size);
518
519
520 #ifdef BUS_SPACE_MAXADDR
521 #if (BUS_SPACE_MAXADDR > 0xFFFFFFFF)
522 #define PCI_DMA_BOUNDARY 0x100000000
523 #else
524 #define PCI_DMA_BOUNDARY 0
525 #endif
526 #endif
527
528 #endif /* _SYS_BUS_H_ */
529
530 /*
531 * cdev switch for control device, initialised in generic PCI code
532 */
533 extern struct cdevsw pcicdev;
534
535 /*
536 * List of all PCI devices, generation count for the list.
537 */
538 STAILQ_HEAD(devlist, pci_devinfo);
539
540 extern struct devlist pci_devq;
541 extern uint32_t pci_generation;
542
543 struct pci_map *pci_find_bar(device_t dev, int reg);
544 int pci_bar_enabled(device_t dev, struct pci_map *pm);
545 struct pcicfg_vpd *pci_fetch_vpd_list(device_t dev);
546
547 #define VGA_PCI_BIOS_SHADOW_ADDR 0xC0000
548 #define VGA_PCI_BIOS_SHADOW_SIZE 131072
549
550 int vga_pci_is_boot_display(device_t dev);
551 void * vga_pci_map_bios(device_t dev, size_t *size);
552 void vga_pci_unmap_bios(device_t dev, void *bios);
553
554 #endif /* _PCIVAR_H_ */
555