1 /* $NetBSD: machdep.c,v 1.35 2024/03/05 14:15:31 thorpej Exp $ */
2
3 /*
4 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
5 * Copyright (C) 1995, 1996 TooLs GmbH.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by TooLs GmbH.
19 * 4. The name of TooLs GmbH may not be used to endorse or promote products
20 * derived from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
27 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
28 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
30 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
31 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #include <sys/cdefs.h>
35 __KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.35 2024/03/05 14:15:31 thorpej Exp $");
36
37 #include "opt_marvell.h"
38 #include "opt_modular.h"
39 #include "opt_ev64260.h"
40 #include "opt_compat_netbsd.h"
41 #include "opt_ddb.h"
42 #include "opt_inet.h"
43 #include "opt_ccitt.h"
44 #include "opt_ns.h"
45
46 #define _POWERPC_BUS_DMA_PRIVATE
47
48 #include <sys/param.h>
49 #include <sys/bus.h>
50 #include <sys/conf.h>
51 #include <sys/device.h>
52 #include <sys/extent.h>
53 #include <sys/kernel.h>
54 #include <sys/ksyms.h>
55 #include <sys/mount.h>
56 #include <sys/reboot.h>
57 #include <sys/systm.h>
58 #include <sys/termios.h>
59 #include <sys/vnode.h>
60
61 #include <uvm/uvm_extern.h>
62
63 #include <machine/powerpc.h>
64
65 #include <powerpc/db_machdep.h>
66 #include <powerpc/pmap.h>
67
68 #include <powerpc/oea/bat.h>
69 #include <powerpc/pic/picvar.h>
70 #include <powerpc/pio.h>
71
72 #include <ddb/db_extern.h>
73
74 #include <dev/cons.h>
75
76 #include "com.h"
77 #if (NCOM > 0)
78 #include <dev/ic/comreg.h>
79 #include <dev/ic/comvar.h>
80 #endif
81
82 #include <dev/marvell/gtreg.h>
83 #include <dev/marvell/gtvar.h>
84
85 #include "gtmpsc.h"
86 #if (NGTMPSC > 0)
87 #include <dev/marvell/gtbrgreg.h>
88 #include <dev/marvell/gtsdmareg.h>
89 #include <dev/marvell/gtmpscreg.h>
90 #include <dev/marvell/gtmpscvar.h>
91 #endif
92
93 #include "ksyms.h"
94 #include "locators.h"
95
96
97 /*
98 * Global variables used here and there
99 */
100 #define PMONMEMREGIONS 32
101 struct mem_region physmemr[PMONMEMREGIONS], availmemr[PMONMEMREGIONS];
102
103 void initppc(u_int, u_int, u_int, void *); /* Called from locore */
104 static void gt_bus_space_init(void);
105 static inline void gt_record_memory(int, paddr_t, paddr_t, paddr_t);
106 static void gt_find_memory(paddr_t);
107
108 bus_addr_t gt_base = 0;
109
110 extern int primary_pic;
111 struct pic_ops *discovery_pic;
112 struct pic_ops *discovery_gpp_pic[4];
113
114
115 struct powerpc_bus_space ev64260_pci0_mem_bs_tag = {
116 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE,
117 0x00000000, 0x00000000, 0x00000000,
118 };
119 struct powerpc_bus_space ev64260_pci0_io_bs_tag = {
120 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_IO_TYPE,
121 0x00000000, 0x00000000, 0x00000000,
122 };
123 struct powerpc_bus_space ev64260_pci1_mem_bs_tag = {
124 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE,
125 0x00000000, 0x00000000, 0x00000000,
126 };
127 struct powerpc_bus_space ev64260_pci1_io_bs_tag = {
128 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_IO_TYPE,
129 0x00000000, 0x00000000, 0x00000000,
130 };
131 struct powerpc_bus_space ev64260_obio0_bs_tag = {
132 _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE|OBIO0_STRIDE,
133 0x00000000, 0x00000000, 0x00000000,
134 };
135 struct powerpc_bus_space ev64260_obio1_bs_tag = {
136 _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE|OBIO1_STRIDE,
137 0x00000000, 0x00000000, 0x00000000,
138 };
139 struct powerpc_bus_space ev64260_obio2_bs_tag = {
140 _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE|OBIO2_STRIDE,
141 0x00000000, 0x00000000, 0x00000000,
142 };
143 struct powerpc_bus_space ev64260_obio3_bs_tag = {
144 _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE|OBIO3_STRIDE,
145 0x00000000, 0x00000000, 0x00000000,
146 };
147 struct powerpc_bus_space ev64260_bootcs_bs_tag = {
148 _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE,
149 0x00000000, 0x00000000, 0x00000000,
150 };
151 struct powerpc_bus_space ev64260_gt_bs_tag = {
152 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE,
153 0x00000000, 0x00000000, GT_SIZE,
154 };
155
156 struct powerpc_bus_space *ev64260_obio_bs_tags[5] = {
157 &ev64260_obio0_bs_tag, &ev64260_obio1_bs_tag, &ev64260_obio2_bs_tag,
158 &ev64260_obio3_bs_tag, &ev64260_bootcs_bs_tag
159 };
160
161 static char ex_storage[10][EXTENT_FIXED_STORAGE_SIZE(8)]
162 __attribute__((aligned(8)));
163
164 const struct gt_decode_info {
165 bus_addr_t low_decode;
166 bus_addr_t high_decode;
167 } decode_regs[] = {
168 { GT_SCS0_Low_Decode, GT_SCS0_High_Decode },
169 { GT_SCS1_Low_Decode, GT_SCS1_High_Decode },
170 { GT_SCS2_Low_Decode, GT_SCS2_High_Decode },
171 { GT_SCS3_Low_Decode, GT_SCS3_High_Decode },
172 { GT_CS0_Low_Decode, GT_CS0_High_Decode },
173 { GT_CS1_Low_Decode, GT_CS1_High_Decode },
174 { GT_CS2_Low_Decode, GT_CS2_High_Decode },
175 { GT_CS3_Low_Decode, GT_CS3_High_Decode },
176 { GT_BootCS_Low_Decode, GT_BootCS_High_Decode },
177 };
178
179 struct powerpc_bus_dma_tag ev64260_bus_dma_tag = {
180 0, /* _bounce_thresh */
181 _bus_dmamap_create,
182 _bus_dmamap_destroy,
183 _bus_dmamap_load,
184 _bus_dmamap_load_mbuf,
185 _bus_dmamap_load_uio,
186 _bus_dmamap_load_raw,
187 _bus_dmamap_unload,
188 _bus_dmamap_sync,
189 _bus_dmamem_alloc,
190 _bus_dmamem_free,
191 _bus_dmamem_map,
192 _bus_dmamem_unmap,
193 _bus_dmamem_mmap,
194 };
195
196
197 void
initppc(u_int startkernel,u_int endkernel,u_int args,void * btinfo)198 initppc(u_int startkernel, u_int endkernel, u_int args, void *btinfo)
199 {
200 extern struct cfdata cfdata[];
201 cfdata_t cf = &cfdata[0];
202
203 /* Get mapped address of gt(System Controller) */
204 while (cf->cf_name != NULL) {
205 if (strcmp(cf->cf_name, "gt") == 0 &&
206 *cf->cf_loc != MAINBUSCF_ADDR_DEFAULT)
207 break;
208 cf++;
209 }
210 if (cf->cf_name == NULL)
211 panic("where is gt?");
212 gt_base = *cf->cf_loc;
213
214 ev64260_gt_bs_tag.pbs_offset = gt_base;
215 ev64260_gt_bs_tag.pbs_base = gt_base;
216 ev64260_gt_bs_tag.pbs_limit += gt_base;
217 oea_batinit(gt_base, BAT_BL_256M, 0);
218
219 oea_init(NULL);
220
221 gt_bus_space_init();
222 gt_find_memory(roundup(endkernel, PAGE_SIZE));
223
224 consinit();
225
226 uvm_md_init();
227
228 /*
229 * Initialize pmap module.
230 */
231 pmap_bootstrap(startkernel, endkernel);
232
233 #if NKSYMS || defined(DDB) || defined(MODULAR)
234 {
235 extern void *startsym, *endsym;
236 ksyms_addsyms_elf((int)((u_int)endsym - (u_int)startsym),
237 startsym, endsym);
238 }
239 #endif
240 }
241
242 /*
243 * Machine dependent startup code.
244 */
245 void
cpu_startup(void)246 cpu_startup(void)
247 {
248 register_t msr;
249
250 oea_startup(NULL);
251
252 pic_init();
253 discovery_pic = setup_discovery_pic();
254 primary_pic = 0;
255 discovery_gpp_pic[0] = setup_discovery_gpp_pic(discovery_pic, 0);
256 discovery_gpp_pic[1] = setup_discovery_gpp_pic(discovery_pic, 8);
257 discovery_gpp_pic[2] = setup_discovery_gpp_pic(discovery_pic, 16);
258 discovery_gpp_pic[3] = setup_discovery_gpp_pic(discovery_pic, 24);
259 /*
260 * GPP interrupts establishes later.
261 */
262
263 oea_install_extint(pic_ext_intr);
264
265 /*
266 * Now that we have VM, malloc()s are OK in bus_space.
267 */
268 bus_space_mallocok();
269
270 /*
271 * Now allow hardware interrupts.
272 */
273 splraise(-1);
274 __asm volatile ("mfmsr %0; ori %0,%0,%1; mtmsr %0"
275 : "=r"(msr)
276 : "K"(PSL_EE));
277 }
278
279 /*
280 * consinit
281 * Initialize system console.
282 */
283 void
consinit(void)284 consinit(void)
285 {
286
287 #ifdef MPSC_CONSOLE
288 /* PMON using MPSC0 @ 9600 */
289 const int brg = GTMPSC_CRR_BRG0;
290 const int baud = 9600;
291 uint32_t cr;
292
293 #if 1
294 /*
295 * XXX HACK FIXME
296 * PMON output has not been flushed. give him a chance
297 */
298 DELAY(100000); /* XXX */
299 #endif
300 /* Setup MPSC Routing Registers */
301 out32rb(gt_base + GTMPSC_MRR, GTMPSC_MRR_RES);
302 cr = in32rb(gt_base + GTMPSC_RCRR);
303 cr &= ~GTMPSC_CRR(MPSC_CONSOLE, GTMPSC_CRR_MASK);
304 cr |= GTMPSC_CRR(MPSC_CONSOLE, brg);
305 out32rb(gt_base + GTMPSC_RCRR, cr);
306 out32rb(gt_base + GTMPSC_TCRR, cr);
307
308 /* Setup Baud Rate Configuration Register of Baud Rate Generator */
309 out32rb(gt_base + BRG_BCR(brg),
310 BRG_BCR_EN | GT_MPSC_CLOCK_SOURCE | compute_cdv(baud));
311
312 gtmpsccnattach(&ev64260_gt_bs_tag, &ev64260_bus_dma_tag, gt_base,
313 MPSC_CONSOLE, brg, baud,
314 (TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8);
315 #else
316 /* PPCBOOT using COM1 @ 57600 */
317 comcnattach(>_obio2_bs_tag, 0, 57600,
318 COM_FREQ*2, COM_TYPE_NORMAL,
319 (TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8);
320 #endif
321 }
322
323 /*
324 * Halt or reboot the machine after syncing/dumping according to howto.
325 */
326 void
cpu_reboot(int howto,char * what)327 cpu_reboot(int howto, char *what)
328 {
329 static int syncing;
330 static char str[256];
331 char *ap = str, *ap1 = ap;
332
333 boothowto = howto;
334 if (!cold && !(howto & RB_NOSYNC) && !syncing) {
335 syncing = 1;
336 vfs_shutdown(); /* sync */
337 }
338 splhigh();
339 if (howto & RB_HALT) {
340 doshutdownhooks();
341 pmf_system_shutdown(boothowto);
342 printf("halted\n\n");
343 cnhalt();
344 while(1);
345 }
346 if (!cold && (howto & RB_DUMP))
347 oea_dumpsys();
348 doshutdownhooks();
349
350 pmf_system_shutdown(boothowto);
351 printf("rebooting\n\n");
352 if (what && *what) {
353 if (strlen(what) > sizeof str - 5)
354 printf("boot string too large, ignored\n");
355 else {
356 strcpy(str, what);
357 ap1 = ap = str + strlen(str);
358 *ap++ = ' ';
359 }
360 }
361 *ap++ = '-';
362 if (howto & RB_SINGLE)
363 *ap++ = 's';
364 if (howto & RB_KDB)
365 *ap++ = 'd';
366 *ap++ = 0;
367 if (ap[-2] == '-')
368 *ap1 = 0;
369 gt_watchdog_reset();
370 /* NOTREACHED */
371 while (1);
372 }
373
374 void
mem_regions(struct mem_region ** mem,struct mem_region ** avail)375 mem_regions(struct mem_region **mem, struct mem_region **avail)
376 {
377
378 *mem = physmemr;
379 *avail = availmemr;
380 }
381
382 static void
gt_bus_space_init(void)383 gt_bus_space_init(void)
384 {
385 const struct gt_decode_info *di;
386 uint32_t datal, datah;
387 int bs, i;
388
389 bs = 0;
390 bus_space_init(&ev64260_gt_bs_tag, "gt",
391 ex_storage[bs], sizeof(ex_storage[bs]));
392 bs++;
393
394 for (i = 0, di = &decode_regs[4]; i < 5; i++, di++) {
395 struct powerpc_bus_space *memt = ev64260_obio_bs_tags[i];
396
397 datal = in32rb(gt_base + di->low_decode);
398 datah = in32rb(gt_base + di->high_decode);
399
400 if (GT_LowAddr_GET(datal) >= GT_HighAddr_GET(datal)) {
401 ev64260_obio_bs_tags[i] = NULL;
402 continue;
403 }
404 memt->pbs_offset = GT_LowAddr_GET(datal);
405 memt->pbs_limit = GT_HighAddr_GET(datah) + 1 -
406 memt->pbs_offset;
407
408 bus_space_init(memt, "obio2",
409 ex_storage[bs], sizeof(ex_storage[bs]));
410 bs++;
411 }
412
413 datal = in32rb(gt_base + GT_PCI0_Mem0_Low_Decode);
414 datah = in32rb(gt_base + GT_PCI0_Mem0_High_Decode);
415 #if defined(GT_PCI0_MEMBASE)
416 datal &= ~0xfff;
417 datal |= (GT_PCI0_MEMBASE >> 20);
418 out32rb(gt_base + GT_PCI0_Mem0_Low_Decode, datal);
419 #endif
420 #if defined(GT_PCI0_MEMSIZE)
421 datah &= ~0xfff;
422 datah |= (GT_PCI0_MEMSIZE + GT_LowAddr_GET(datal) - 1) >> 20;
423 out32rb(gt_base + GT_PCI0_Mem0_High_Decode, datal);
424 #endif
425 ev64260_pci0_mem_bs_tag.pbs_base = GT_LowAddr_GET(datal);
426 ev64260_pci0_mem_bs_tag.pbs_limit = GT_HighAddr_GET(datah) + 1;
427
428 bus_space_init(&ev64260_pci0_mem_bs_tag, "pci0-mem",
429 ex_storage[bs], sizeof(ex_storage[bs]));
430 bs++;
431
432 #if 1 /* XXXXXX */
433 /*
434 * Make sure PCI0 Memory is BAT mapped.
435 */
436 if (GT_LowAddr_GET(datal) < GT_HighAddr_GET(datal))
437 oea_iobat_add(ev64260_pci0_mem_bs_tag.pbs_base & SEGMENT_MASK,
438 BAT_BL_256M);
439 #endif
440
441 /*
442 * Make sure that I/O space start at 0.
443 */
444 out32rb(gt_base + GT_PCI1_IO_Remap, 0);
445
446 datal = in32rb(gt_base + GT_PCI0_IO_Low_Decode);
447 datah = in32rb(gt_base + GT_PCI0_IO_High_Decode);
448 #if defined(GT_PCI0_IOBASE)
449 datal &= ~0xfff;
450 datal |= (GT_PCI0_IOBASE >> 20);
451 out32rb(gt_base + GT_PCI0_IO_Low_Decode, datal);
452 #endif
453 #if defined(GT_PCI0_IOSIZE)
454 datah &= ~0xfff;
455 datah |= (GT_PCI0_IOSIZE + GT_LowAddr_GET(datal) - 1) >> 20;
456 out32rb(gt_base + GT_PCI0_IO_High_Decode, datal);
457 #endif
458 ev64260_pci0_io_bs_tag.pbs_offset = GT_LowAddr_GET(datal);
459 ev64260_pci0_io_bs_tag.pbs_limit = GT_HighAddr_GET(datah) + 1 -
460 ev64260_pci0_io_bs_tag.pbs_offset;
461
462 bus_space_init(&ev64260_pci0_io_bs_tag, "pci0-ioport",
463 ex_storage[bs], sizeof(ex_storage[bs]));
464 bs++;
465
466 datal = in32rb(gt_base + GT_PCI1_Mem0_Low_Decode);
467 datah = in32rb(gt_base + GT_PCI1_Mem0_High_Decode);
468 #if defined(GT_PCI1_MEMBASE)
469 datal &= ~0xfff;
470 datal |= (GT_PCI1_MEMBASE >> 20);
471 out32rb(gt_base + GT_PCI1_Mem0_Low_Decode, datal);
472 #endif
473 #if defined(GT_PCI1_MEMSIZE)
474 datah &= ~0xfff;
475 datah |= (GT_PCI1_MEMSIZE + GT_LowAddr_GET(datal) - 1) >> 20;
476 out32rb(gt_base + GT_PCI1_Mem0_High_Decode, datal);
477 #endif
478 ev64260_pci1_mem_bs_tag.pbs_base = GT_LowAddr_GET(datal);
479 ev64260_pci1_mem_bs_tag.pbs_limit = GT_HighAddr_GET(datah) + 1;
480
481 bus_space_init(&ev64260_pci1_mem_bs_tag, "pci1-mem",
482 ex_storage[bs], sizeof(ex_storage[bs]));
483 bs++;
484
485 #if 1 /* XXXXXX */
486 /*
487 * Make sure PCI1 Memory is BAT mapped.
488 */
489 if (GT_LowAddr_GET(datal) < GT_HighAddr_GET(datal))
490 oea_iobat_add(ev64260_pci1_mem_bs_tag.pbs_base & SEGMENT_MASK,
491 BAT_BL_256M);
492 #endif
493
494 /*
495 * Make sure that I/O space start at 0.
496 */
497 out32rb(gt_base + GT_PCI1_IO_Remap, 0);
498
499 datal = in32rb(gt_base + GT_PCI1_IO_Low_Decode);
500 datah = in32rb(gt_base + GT_PCI1_IO_High_Decode);
501 #if defined(GT_PCI1_IOBASE)
502 datal &= ~0xfff;
503 datal |= (GT_PCI1_IOBASE >> 20);
504 out32rb(gt_base + GT_PCI1_IO_Low_Decode, datal);
505 #endif
506 #if defined(GT_PCI1_IOSIZE)
507 datah &= ~0xfff;
508 datah |= (GT_PCI1_IOSIZE + GT_LowAddr_GET(datal) - 1) >> 20;
509 out32rb(gt_base + GT_PCI1_IO_High_Decode, datal);
510 #endif
511 ev64260_pci1_io_bs_tag.pbs_offset = GT_LowAddr_GET(datal);
512 ev64260_pci1_io_bs_tag.pbs_limit = GT_HighAddr_GET(datah) + 1 -
513 ev64260_pci1_io_bs_tag.pbs_offset;
514
515 bus_space_init(&ev64260_pci1_io_bs_tag, "pci1-ioport",
516 ex_storage[bs], sizeof(ex_storage[bs]));
517 bs++;
518 }
519
520 static inline void
gt_record_memory(int j,paddr_t start,paddr_t end,paddr_t endkernel)521 gt_record_memory(int j, paddr_t start, paddr_t end, paddr_t endkernel)
522 {
523 physmemr[j].start = start;
524 physmemr[j].size = end - start;
525 if (start < endkernel)
526 start = endkernel;
527 availmemr[j].start = start;
528 availmemr[j].size = end - start;
529 }
530
531 static void
gt_find_memory(paddr_t endkernel)532 gt_find_memory(paddr_t endkernel)
533 {
534 paddr_t start = ~0, end = 0;
535 const struct gt_decode_info *di;
536 int i, j = 0, first = 1;
537
538 /*
539 * Round kernel end to a page boundary.
540 */
541 for (i = 0; i < 4; i++) {
542 paddr_t nstart, nend;
543
544 di = &decode_regs[i];
545 nstart = GT_LowAddr_GET(in32rb(gt_base + di->low_decode));
546 nend = GT_HighAddr_GET(in32rb(gt_base + di->high_decode)) + 1;
547 if (nstart >= nend)
548 continue;
549 if (first) {
550 /*
551 * First entry? Just remember it.
552 */
553 start = nstart;
554 end = nend;
555 first = 0;
556 } else if (nstart == end) {
557 /*
558 * Contiguous? Just update the end.
559 */
560 end = nend;
561 } else {
562 /*
563 * Disjoint? record it.
564 */
565 gt_record_memory(j, start, end, endkernel);
566 start = nstart;
567 end = nend;
568 j++;
569 }
570 }
571 gt_record_memory(j, start, end, endkernel);
572 }
573