1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27
28 #include "resource.h"
29 #include "include/irq_service_interface.h"
30 #include "link_encoder.h"
31 #include "stream_encoder.h"
32 #include "opp.h"
33 #include "timing_generator.h"
34 #include "transform.h"
35 #include "dccg.h"
36 #include "dchubbub.h"
37 #include "dpp.h"
38 #include "core_types.h"
39 #include "set_mode_types.h"
40 #include "virtual/virtual_stream_encoder.h"
41 #include "dpcd_defs.h"
42 #include "link_enc_cfg.h"
43 #include "link.h"
44 #include "clk_mgr.h"
45 #include "dc_state_priv.h"
46 #include "dc_stream_priv.h"
47
48 #include "virtual/virtual_link_hwss.h"
49 #include "link/hwss/link_hwss_dio.h"
50 #include "link/hwss/link_hwss_dpia.h"
51 #include "link/hwss/link_hwss_hpo_dp.h"
52 #include "link/hwss/link_hwss_dio_fixed_vs_pe_retimer.h"
53 #include "link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.h"
54
55 #if defined(CONFIG_DRM_AMD_DC_SI)
56 #include "dce60/dce60_resource.h"
57 #endif
58 #include "dce80/dce80_resource.h"
59 #include "dce100/dce100_resource.h"
60 #include "dce110/dce110_resource.h"
61 #include "dce112/dce112_resource.h"
62 #include "dce120/dce120_resource.h"
63 #include "dcn10/dcn10_resource.h"
64 #include "dcn20/dcn20_resource.h"
65 #include "dcn21/dcn21_resource.h"
66 #include "dcn201/dcn201_resource.h"
67 #include "dcn30/dcn30_resource.h"
68 #include "dcn301/dcn301_resource.h"
69 #include "dcn302/dcn302_resource.h"
70 #include "dcn303/dcn303_resource.h"
71 #include "dcn31/dcn31_resource.h"
72 #include "dcn314/dcn314_resource.h"
73 #include "dcn315/dcn315_resource.h"
74 #include "dcn316/dcn316_resource.h"
75 #include "dcn32/dcn32_resource.h"
76 #include "dcn321/dcn321_resource.h"
77 #include "dcn35/dcn35_resource.h"
78 #include "dcn351/dcn351_resource.h"
79 #include "dcn401/dcn401_resource.h"
80 #if defined(CONFIG_DRM_AMD_DC_FP)
81 #include "dc_spl_translate.h"
82 #endif
83
84 #define VISUAL_CONFIRM_BASE_DEFAULT 3
85 #define VISUAL_CONFIRM_BASE_MIN 1
86 #define VISUAL_CONFIRM_BASE_MAX 10
87 /* we choose 240 because it is a common denominator of common v addressable
88 * such as 2160, 1440, 1200, 960. So we take 1/240 portion of v addressable as
89 * the visual confirm dpp offset height. So visual confirm height can stay
90 * relatively the same independent from timing used.
91 */
92 #define VISUAL_CONFIRM_DPP_OFFSET_DENO 240
93
94 #define DC_LOGGER \
95 dc->ctx->logger
96 #define DC_LOGGER_INIT(logger)
97
98 #include "dml2/dml2_wrapper.h"
99
100 #define UNABLE_TO_SPLIT -1
101
resource_parse_asic_id(struct hw_asic_id asic_id)102 enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
103 {
104 enum dce_version dc_version = DCE_VERSION_UNKNOWN;
105
106 switch (asic_id.chip_family) {
107
108 #if defined(CONFIG_DRM_AMD_DC_SI)
109 case FAMILY_SI:
110 if (ASIC_REV_IS_TAHITI_P(asic_id.hw_internal_rev) ||
111 ASIC_REV_IS_PITCAIRN_PM(asic_id.hw_internal_rev) ||
112 ASIC_REV_IS_CAPEVERDE_M(asic_id.hw_internal_rev))
113 dc_version = DCE_VERSION_6_0;
114 else if (ASIC_REV_IS_OLAND_M(asic_id.hw_internal_rev))
115 dc_version = DCE_VERSION_6_4;
116 else
117 dc_version = DCE_VERSION_6_1;
118 break;
119 #endif
120 case FAMILY_CI:
121 dc_version = DCE_VERSION_8_0;
122 break;
123 case FAMILY_KV:
124 if (ASIC_REV_IS_KALINDI(asic_id.hw_internal_rev) ||
125 ASIC_REV_IS_BHAVANI(asic_id.hw_internal_rev) ||
126 ASIC_REV_IS_GODAVARI(asic_id.hw_internal_rev))
127 dc_version = DCE_VERSION_8_3;
128 else
129 dc_version = DCE_VERSION_8_1;
130 break;
131 case FAMILY_CZ:
132 dc_version = DCE_VERSION_11_0;
133 break;
134
135 case FAMILY_VI:
136 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
137 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
138 dc_version = DCE_VERSION_10_0;
139 break;
140 }
141 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
142 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
143 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
144 dc_version = DCE_VERSION_11_2;
145 }
146 if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev))
147 dc_version = DCE_VERSION_11_22;
148 break;
149 case FAMILY_AI:
150 if (ASICREV_IS_VEGA20_P(asic_id.hw_internal_rev))
151 dc_version = DCE_VERSION_12_1;
152 else
153 dc_version = DCE_VERSION_12_0;
154 break;
155 case FAMILY_RV:
156 dc_version = DCN_VERSION_1_0;
157 if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev))
158 dc_version = DCN_VERSION_1_01;
159 if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev))
160 dc_version = DCN_VERSION_2_1;
161 if (ASICREV_IS_GREEN_SARDINE(asic_id.hw_internal_rev))
162 dc_version = DCN_VERSION_2_1;
163 break;
164
165 case FAMILY_NV:
166 dc_version = DCN_VERSION_2_0;
167 if (asic_id.chip_id == DEVICE_ID_NV_13FE || asic_id.chip_id == DEVICE_ID_NV_143F) {
168 dc_version = DCN_VERSION_2_01;
169 break;
170 }
171 if (ASICREV_IS_SIENNA_CICHLID_P(asic_id.hw_internal_rev))
172 dc_version = DCN_VERSION_3_0;
173 if (ASICREV_IS_DIMGREY_CAVEFISH_P(asic_id.hw_internal_rev))
174 dc_version = DCN_VERSION_3_02;
175 if (ASICREV_IS_BEIGE_GOBY_P(asic_id.hw_internal_rev))
176 dc_version = DCN_VERSION_3_03;
177 break;
178
179 case FAMILY_VGH:
180 dc_version = DCN_VERSION_3_01;
181 break;
182
183 case FAMILY_YELLOW_CARP:
184 if (ASICREV_IS_YELLOW_CARP(asic_id.hw_internal_rev))
185 dc_version = DCN_VERSION_3_1;
186 break;
187 case AMDGPU_FAMILY_GC_10_3_6:
188 if (ASICREV_IS_GC_10_3_6(asic_id.hw_internal_rev))
189 dc_version = DCN_VERSION_3_15;
190 break;
191 case AMDGPU_FAMILY_GC_10_3_7:
192 if (ASICREV_IS_GC_10_3_7(asic_id.hw_internal_rev))
193 dc_version = DCN_VERSION_3_16;
194 break;
195 case AMDGPU_FAMILY_GC_11_0_0:
196 dc_version = DCN_VERSION_3_2;
197 if (ASICREV_IS_GC_11_0_2(asic_id.hw_internal_rev))
198 dc_version = DCN_VERSION_3_21;
199 break;
200 case AMDGPU_FAMILY_GC_11_0_1:
201 dc_version = DCN_VERSION_3_14;
202 break;
203 case AMDGPU_FAMILY_GC_11_5_0:
204 dc_version = DCN_VERSION_3_5;
205 if (ASICREV_IS_GC_11_0_4(asic_id.hw_internal_rev))
206 dc_version = DCN_VERSION_3_51;
207 break;
208 case AMDGPU_FAMILY_GC_12_0_0:
209 if (ASICREV_IS_GC_12_0_1_A0(asic_id.hw_internal_rev) ||
210 ASICREV_IS_GC_12_0_0_A0(asic_id.hw_internal_rev))
211 dc_version = DCN_VERSION_4_01;
212 break;
213 default:
214 dc_version = DCE_VERSION_UNKNOWN;
215 break;
216 }
217 return dc_version;
218 }
219
dc_create_resource_pool(struct dc * dc,const struct dc_init_data * init_data,enum dce_version dc_version)220 struct resource_pool *dc_create_resource_pool(struct dc *dc,
221 const struct dc_init_data *init_data,
222 enum dce_version dc_version)
223 {
224 struct resource_pool *res_pool = NULL;
225
226 switch (dc_version) {
227 #if defined(CONFIG_DRM_AMD_DC_SI)
228 case DCE_VERSION_6_0:
229 res_pool = dce60_create_resource_pool(
230 init_data->num_virtual_links, dc);
231 break;
232 case DCE_VERSION_6_1:
233 res_pool = dce61_create_resource_pool(
234 init_data->num_virtual_links, dc);
235 break;
236 case DCE_VERSION_6_4:
237 res_pool = dce64_create_resource_pool(
238 init_data->num_virtual_links, dc);
239 break;
240 #endif
241 case DCE_VERSION_8_0:
242 res_pool = dce80_create_resource_pool(
243 init_data->num_virtual_links, dc);
244 break;
245 case DCE_VERSION_8_1:
246 res_pool = dce81_create_resource_pool(
247 init_data->num_virtual_links, dc);
248 break;
249 case DCE_VERSION_8_3:
250 res_pool = dce83_create_resource_pool(
251 init_data->num_virtual_links, dc);
252 break;
253 case DCE_VERSION_10_0:
254 res_pool = dce100_create_resource_pool(
255 init_data->num_virtual_links, dc);
256 break;
257 case DCE_VERSION_11_0:
258 res_pool = dce110_create_resource_pool(
259 init_data->num_virtual_links, dc,
260 init_data->asic_id);
261 break;
262 case DCE_VERSION_11_2:
263 case DCE_VERSION_11_22:
264 res_pool = dce112_create_resource_pool(
265 init_data->num_virtual_links, dc);
266 break;
267 case DCE_VERSION_12_0:
268 case DCE_VERSION_12_1:
269 res_pool = dce120_create_resource_pool(
270 init_data->num_virtual_links, dc);
271 break;
272
273 #if defined(CONFIG_DRM_AMD_DC_FP)
274 case DCN_VERSION_1_0:
275 case DCN_VERSION_1_01:
276 res_pool = dcn10_create_resource_pool(init_data, dc);
277 break;
278 case DCN_VERSION_2_0:
279 res_pool = dcn20_create_resource_pool(init_data, dc);
280 break;
281 case DCN_VERSION_2_1:
282 res_pool = dcn21_create_resource_pool(init_data, dc);
283 break;
284 case DCN_VERSION_2_01:
285 res_pool = dcn201_create_resource_pool(init_data, dc);
286 break;
287 case DCN_VERSION_3_0:
288 res_pool = dcn30_create_resource_pool(init_data, dc);
289 break;
290 case DCN_VERSION_3_01:
291 res_pool = dcn301_create_resource_pool(init_data, dc);
292 break;
293 case DCN_VERSION_3_02:
294 res_pool = dcn302_create_resource_pool(init_data, dc);
295 break;
296 case DCN_VERSION_3_03:
297 res_pool = dcn303_create_resource_pool(init_data, dc);
298 break;
299 case DCN_VERSION_3_1:
300 res_pool = dcn31_create_resource_pool(init_data, dc);
301 break;
302 case DCN_VERSION_3_14:
303 res_pool = dcn314_create_resource_pool(init_data, dc);
304 break;
305 case DCN_VERSION_3_15:
306 res_pool = dcn315_create_resource_pool(init_data, dc);
307 break;
308 case DCN_VERSION_3_16:
309 res_pool = dcn316_create_resource_pool(init_data, dc);
310 break;
311 case DCN_VERSION_3_2:
312 res_pool = dcn32_create_resource_pool(init_data, dc);
313 break;
314 case DCN_VERSION_3_21:
315 res_pool = dcn321_create_resource_pool(init_data, dc);
316 break;
317 case DCN_VERSION_3_5:
318 res_pool = dcn35_create_resource_pool(init_data, dc);
319 break;
320 case DCN_VERSION_3_51:
321 res_pool = dcn351_create_resource_pool(init_data, dc);
322 break;
323 case DCN_VERSION_4_01:
324 res_pool = dcn401_create_resource_pool(init_data, dc);
325 break;
326 #endif /* CONFIG_DRM_AMD_DC_FP */
327 default:
328 break;
329 }
330
331 if (res_pool != NULL) {
332 if (dc->ctx->dc_bios->fw_info_valid) {
333 res_pool->ref_clocks.xtalin_clock_inKhz =
334 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
335 /* initialize with firmware data first, no all
336 * ASIC have DCCG SW component. FPGA or
337 * simulation need initialization of
338 * dccg_ref_clock_inKhz, dchub_ref_clock_inKhz
339 * with xtalin_clock_inKhz
340 */
341 res_pool->ref_clocks.dccg_ref_clock_inKhz =
342 res_pool->ref_clocks.xtalin_clock_inKhz;
343 res_pool->ref_clocks.dchub_ref_clock_inKhz =
344 res_pool->ref_clocks.xtalin_clock_inKhz;
345 } else
346 ASSERT_CRITICAL(false);
347 }
348
349 return res_pool;
350 }
351
dc_destroy_resource_pool(struct dc * dc)352 void dc_destroy_resource_pool(struct dc *dc)
353 {
354 if (dc) {
355 if (dc->res_pool)
356 dc->res_pool->funcs->destroy(&dc->res_pool);
357
358 kfree(dc->hwseq);
359 }
360 }
361
update_num_audio(const struct resource_straps * straps,unsigned int * num_audio,struct audio_support * aud_support)362 static void update_num_audio(
363 const struct resource_straps *straps,
364 unsigned int *num_audio,
365 struct audio_support *aud_support)
366 {
367 aud_support->dp_audio = true;
368 aud_support->hdmi_audio_native = false;
369 aud_support->hdmi_audio_on_dongle = false;
370
371 if (straps->hdmi_disable == 0) {
372 if (straps->dc_pinstraps_audio & 0x2) {
373 aud_support->hdmi_audio_on_dongle = true;
374 aud_support->hdmi_audio_native = true;
375 }
376 }
377
378 switch (straps->audio_stream_number) {
379 case 0: /* multi streams supported */
380 break;
381 case 1: /* multi streams not supported */
382 *num_audio = 1;
383 break;
384 default:
385 DC_ERR("DC: unexpected audio fuse!\n");
386 }
387 }
388
resource_construct(unsigned int num_virtual_links,struct dc * dc,struct resource_pool * pool,const struct resource_create_funcs * create_funcs)389 bool resource_construct(
390 unsigned int num_virtual_links,
391 struct dc *dc,
392 struct resource_pool *pool,
393 const struct resource_create_funcs *create_funcs)
394 {
395 struct dc_context *ctx = dc->ctx;
396 const struct resource_caps *caps = pool->res_cap;
397 int i;
398 unsigned int num_audio = caps->num_audio;
399 struct resource_straps straps = {0};
400
401 if (create_funcs->read_dce_straps)
402 create_funcs->read_dce_straps(dc->ctx, &straps);
403
404 pool->audio_count = 0;
405 if (create_funcs->create_audio) {
406 /* find the total number of streams available via the
407 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
408 * registers (one for each pin) starting from pin 1
409 * up to the max number of audio pins.
410 * We stop on the first pin where
411 * PORT_CONNECTIVITY == 1 (as instructed by HW team).
412 */
413 update_num_audio(&straps, &num_audio, &pool->audio_support);
414 for (i = 0; i < caps->num_audio; i++) {
415 struct audio *aud = create_funcs->create_audio(ctx, i);
416
417 if (aud == NULL) {
418 DC_ERR("DC: failed to create audio!\n");
419 return false;
420 }
421 if (!aud->funcs->endpoint_valid(aud)) {
422 aud->funcs->destroy(&aud);
423 break;
424 }
425 pool->audios[i] = aud;
426 pool->audio_count++;
427 }
428 }
429
430 pool->stream_enc_count = 0;
431 if (create_funcs->create_stream_encoder) {
432 for (i = 0; i < caps->num_stream_encoder; i++) {
433 pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx);
434 if (pool->stream_enc[i] == NULL)
435 DC_ERR("DC: failed to create stream_encoder!\n");
436 pool->stream_enc_count++;
437 }
438 }
439
440 pool->hpo_dp_stream_enc_count = 0;
441 if (create_funcs->create_hpo_dp_stream_encoder) {
442 for (i = 0; i < caps->num_hpo_dp_stream_encoder; i++) {
443 pool->hpo_dp_stream_enc[i] = create_funcs->create_hpo_dp_stream_encoder(i+ENGINE_ID_HPO_DP_0, ctx);
444 if (pool->hpo_dp_stream_enc[i] == NULL)
445 DC_ERR("DC: failed to create HPO DP stream encoder!\n");
446 pool->hpo_dp_stream_enc_count++;
447
448 }
449 }
450
451 pool->hpo_dp_link_enc_count = 0;
452 if (create_funcs->create_hpo_dp_link_encoder) {
453 for (i = 0; i < caps->num_hpo_dp_link_encoder; i++) {
454 pool->hpo_dp_link_enc[i] = create_funcs->create_hpo_dp_link_encoder(i, ctx);
455 if (pool->hpo_dp_link_enc[i] == NULL)
456 DC_ERR("DC: failed to create HPO DP link encoder!\n");
457 pool->hpo_dp_link_enc_count++;
458 }
459 }
460
461 for (i = 0; i < caps->num_mpc_3dlut; i++) {
462 pool->mpc_lut[i] = dc_create_3dlut_func();
463 if (pool->mpc_lut[i] == NULL)
464 DC_ERR("DC: failed to create MPC 3dlut!\n");
465 pool->mpc_shaper[i] = dc_create_transfer_func();
466 if (pool->mpc_shaper[i] == NULL)
467 DC_ERR("DC: failed to create MPC shaper!\n");
468 }
469
470 dc->caps.dynamic_audio = false;
471 if (pool->audio_count < pool->stream_enc_count) {
472 dc->caps.dynamic_audio = true;
473 }
474 for (i = 0; i < num_virtual_links; i++) {
475 pool->stream_enc[pool->stream_enc_count] =
476 virtual_stream_encoder_create(
477 ctx, ctx->dc_bios);
478 if (pool->stream_enc[pool->stream_enc_count] == NULL) {
479 DC_ERR("DC: failed to create stream_encoder!\n");
480 return false;
481 }
482 pool->stream_enc_count++;
483 }
484
485 dc->hwseq = create_funcs->create_hwseq(ctx);
486
487 return true;
488 }
find_matching_clock_source(const struct resource_pool * pool,struct clock_source * clock_source)489 static int find_matching_clock_source(
490 const struct resource_pool *pool,
491 struct clock_source *clock_source)
492 {
493
494 int i;
495
496 for (i = 0; i < pool->clk_src_count; i++) {
497 if (pool->clock_sources[i] == clock_source)
498 return i;
499 }
500 return -1;
501 }
502
resource_unreference_clock_source(struct resource_context * res_ctx,const struct resource_pool * pool,struct clock_source * clock_source)503 void resource_unreference_clock_source(
504 struct resource_context *res_ctx,
505 const struct resource_pool *pool,
506 struct clock_source *clock_source)
507 {
508 int i = find_matching_clock_source(pool, clock_source);
509
510 if (i > -1)
511 res_ctx->clock_source_ref_count[i]--;
512
513 if (pool->dp_clock_source == clock_source)
514 res_ctx->dp_clock_source_ref_count--;
515 }
516
resource_reference_clock_source(struct resource_context * res_ctx,const struct resource_pool * pool,struct clock_source * clock_source)517 void resource_reference_clock_source(
518 struct resource_context *res_ctx,
519 const struct resource_pool *pool,
520 struct clock_source *clock_source)
521 {
522 int i = find_matching_clock_source(pool, clock_source);
523
524 if (i > -1)
525 res_ctx->clock_source_ref_count[i]++;
526
527 if (pool->dp_clock_source == clock_source)
528 res_ctx->dp_clock_source_ref_count++;
529 }
530
resource_get_clock_source_reference(struct resource_context * res_ctx,const struct resource_pool * pool,struct clock_source * clock_source)531 int resource_get_clock_source_reference(
532 struct resource_context *res_ctx,
533 const struct resource_pool *pool,
534 struct clock_source *clock_source)
535 {
536 int i = find_matching_clock_source(pool, clock_source);
537
538 if (i > -1)
539 return res_ctx->clock_source_ref_count[i];
540
541 if (pool->dp_clock_source == clock_source)
542 return res_ctx->dp_clock_source_ref_count;
543
544 return -1;
545 }
546
resource_are_vblanks_synchronizable(struct dc_stream_state * stream1,struct dc_stream_state * stream2)547 bool resource_are_vblanks_synchronizable(
548 struct dc_stream_state *stream1,
549 struct dc_stream_state *stream2)
550 {
551 uint32_t base60_refresh_rates[] = {10, 20, 5};
552 uint8_t i;
553 uint8_t rr_count = ARRAY_SIZE(base60_refresh_rates);
554 uint64_t frame_time_diff;
555
556 if (stream1->ctx->dc->config.vblank_alignment_dto_params &&
557 stream1->ctx->dc->config.vblank_alignment_max_frame_time_diff > 0 &&
558 dc_is_dp_signal(stream1->signal) &&
559 dc_is_dp_signal(stream2->signal) &&
560 false == stream1->has_non_synchronizable_pclk &&
561 false == stream2->has_non_synchronizable_pclk &&
562 stream1->timing.flags.VBLANK_SYNCHRONIZABLE &&
563 stream2->timing.flags.VBLANK_SYNCHRONIZABLE) {
564 /* disable refresh rates higher than 60Hz for now */
565 if (stream1->timing.pix_clk_100hz*100/stream1->timing.h_total/
566 stream1->timing.v_total > 60)
567 return false;
568 if (stream2->timing.pix_clk_100hz*100/stream2->timing.h_total/
569 stream2->timing.v_total > 60)
570 return false;
571 frame_time_diff = (uint64_t)10000 *
572 stream1->timing.h_total *
573 stream1->timing.v_total *
574 stream2->timing.pix_clk_100hz;
575 frame_time_diff = div_u64(frame_time_diff, stream1->timing.pix_clk_100hz);
576 frame_time_diff = div_u64(frame_time_diff, stream2->timing.h_total);
577 frame_time_diff = div_u64(frame_time_diff, stream2->timing.v_total);
578 for (i = 0; i < rr_count; i++) {
579 int64_t diff = (int64_t)div_u64(frame_time_diff * base60_refresh_rates[i], 10) - 10000;
580
581 if (diff < 0)
582 diff = -diff;
583 if (diff < stream1->ctx->dc->config.vblank_alignment_max_frame_time_diff)
584 return true;
585 }
586 }
587 return false;
588 }
589
resource_are_streams_timing_synchronizable(struct dc_stream_state * stream1,struct dc_stream_state * stream2)590 bool resource_are_streams_timing_synchronizable(
591 struct dc_stream_state *stream1,
592 struct dc_stream_state *stream2)
593 {
594 if (stream1->timing.h_total != stream2->timing.h_total)
595 return false;
596
597 if (stream1->timing.v_total != stream2->timing.v_total)
598 return false;
599
600 if (stream1->timing.h_addressable
601 != stream2->timing.h_addressable)
602 return false;
603
604 if (stream1->timing.v_addressable
605 != stream2->timing.v_addressable)
606 return false;
607
608 if (stream1->timing.v_front_porch
609 != stream2->timing.v_front_porch)
610 return false;
611
612 if (stream1->timing.pix_clk_100hz
613 != stream2->timing.pix_clk_100hz)
614 return false;
615
616 if (stream1->clamping.c_depth != stream2->clamping.c_depth)
617 return false;
618
619 if (stream1->phy_pix_clk != stream2->phy_pix_clk
620 && (!dc_is_dp_signal(stream1->signal)
621 || !dc_is_dp_signal(stream2->signal)))
622 return false;
623
624 if (stream1->view_format != stream2->view_format)
625 return false;
626
627 if (stream1->ignore_msa_timing_param || stream2->ignore_msa_timing_param)
628 return false;
629
630 return true;
631 }
is_dp_and_hdmi_sharable(struct dc_stream_state * stream1,struct dc_stream_state * stream2)632 static bool is_dp_and_hdmi_sharable(
633 struct dc_stream_state *stream1,
634 struct dc_stream_state *stream2)
635 {
636 if (stream1->ctx->dc->caps.disable_dp_clk_share)
637 return false;
638
639 if (stream1->clamping.c_depth != COLOR_DEPTH_888 ||
640 stream2->clamping.c_depth != COLOR_DEPTH_888)
641 return false;
642
643 return true;
644
645 }
646
is_sharable_clk_src(const struct pipe_ctx * pipe_with_clk_src,const struct pipe_ctx * pipe)647 static bool is_sharable_clk_src(
648 const struct pipe_ctx *pipe_with_clk_src,
649 const struct pipe_ctx *pipe)
650 {
651 if (pipe_with_clk_src->clock_source == NULL)
652 return false;
653
654 if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL)
655 return false;
656
657 if (dc_is_dp_signal(pipe_with_clk_src->stream->signal) ||
658 (dc_is_dp_signal(pipe->stream->signal) &&
659 !is_dp_and_hdmi_sharable(pipe_with_clk_src->stream,
660 pipe->stream)))
661 return false;
662
663 if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal)
664 && dc_is_dual_link_signal(pipe->stream->signal))
665 return false;
666
667 if (dc_is_hdmi_signal(pipe->stream->signal)
668 && dc_is_dual_link_signal(pipe_with_clk_src->stream->signal))
669 return false;
670
671 if (!resource_are_streams_timing_synchronizable(
672 pipe_with_clk_src->stream, pipe->stream))
673 return false;
674
675 return true;
676 }
677
resource_find_used_clk_src_for_sharing(struct resource_context * res_ctx,struct pipe_ctx * pipe_ctx)678 struct clock_source *resource_find_used_clk_src_for_sharing(
679 struct resource_context *res_ctx,
680 struct pipe_ctx *pipe_ctx)
681 {
682 int i;
683
684 for (i = 0; i < MAX_PIPES; i++) {
685 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx))
686 return res_ctx->pipe_ctx[i].clock_source;
687 }
688
689 return NULL;
690 }
691
convert_pixel_format_to_dalsurface(enum surface_pixel_format surface_pixel_format)692 static enum pixel_format convert_pixel_format_to_dalsurface(
693 enum surface_pixel_format surface_pixel_format)
694 {
695 enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
696
697 switch (surface_pixel_format) {
698 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
699 dal_pixel_format = PIXEL_FORMAT_INDEX8;
700 break;
701 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
702 dal_pixel_format = PIXEL_FORMAT_RGB565;
703 break;
704 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
705 dal_pixel_format = PIXEL_FORMAT_RGB565;
706 break;
707 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
708 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
709 break;
710 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
711 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
712 break;
713 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
714 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
715 break;
716 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
717 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
718 break;
719 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
720 dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS;
721 break;
722 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
723 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
724 dal_pixel_format = PIXEL_FORMAT_FP16;
725 break;
726 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
727 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
728 dal_pixel_format = PIXEL_FORMAT_420BPP8;
729 break;
730 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
731 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
732 dal_pixel_format = PIXEL_FORMAT_420BPP10;
733 break;
734 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
735 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
736 default:
737 dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
738 break;
739 }
740 return dal_pixel_format;
741 }
742
get_vp_scan_direction(enum dc_rotation_angle rotation,bool horizontal_mirror,bool * orthogonal_rotation,bool * flip_vert_scan_dir,bool * flip_horz_scan_dir)743 static inline void get_vp_scan_direction(
744 enum dc_rotation_angle rotation,
745 bool horizontal_mirror,
746 bool *orthogonal_rotation,
747 bool *flip_vert_scan_dir,
748 bool *flip_horz_scan_dir)
749 {
750 *orthogonal_rotation = false;
751 *flip_vert_scan_dir = false;
752 *flip_horz_scan_dir = false;
753 if (rotation == ROTATION_ANGLE_180) {
754 *flip_vert_scan_dir = true;
755 *flip_horz_scan_dir = true;
756 } else if (rotation == ROTATION_ANGLE_90) {
757 *orthogonal_rotation = true;
758 *flip_horz_scan_dir = true;
759 } else if (rotation == ROTATION_ANGLE_270) {
760 *orthogonal_rotation = true;
761 *flip_vert_scan_dir = true;
762 }
763
764 if (horizontal_mirror)
765 *flip_horz_scan_dir = !*flip_horz_scan_dir;
766 }
767
intersect_rec(const struct rect * r0,const struct rect * r1)768 static struct rect intersect_rec(const struct rect *r0, const struct rect *r1)
769 {
770 struct rect rec;
771 int r0_x_end = r0->x + r0->width;
772 int r1_x_end = r1->x + r1->width;
773 int r0_y_end = r0->y + r0->height;
774 int r1_y_end = r1->y + r1->height;
775
776 rec.x = r0->x > r1->x ? r0->x : r1->x;
777 rec.width = r0_x_end > r1_x_end ? r1_x_end - rec.x : r0_x_end - rec.x;
778 rec.y = r0->y > r1->y ? r0->y : r1->y;
779 rec.height = r0_y_end > r1_y_end ? r1_y_end - rec.y : r0_y_end - rec.y;
780
781 /* in case that there is no intersection */
782 if (rec.width < 0 || rec.height < 0)
783 memset(&rec, 0, sizeof(rec));
784
785 return rec;
786 }
787
shift_rec(const struct rect * rec_in,int x,int y)788 static struct rect shift_rec(const struct rect *rec_in, int x, int y)
789 {
790 struct rect rec_out = *rec_in;
791
792 rec_out.x += x;
793 rec_out.y += y;
794
795 return rec_out;
796 }
797
calculate_plane_rec_in_timing_active(struct pipe_ctx * pipe_ctx,const struct rect * rec_in)798 static struct rect calculate_plane_rec_in_timing_active(
799 struct pipe_ctx *pipe_ctx,
800 const struct rect *rec_in)
801 {
802 /*
803 * The following diagram shows an example where we map a 1920x1200
804 * desktop to a 2560x1440 timing with a plane rect in the middle
805 * of the screen. To map a plane rect from Stream Source to Timing
806 * Active space, we first multiply stream scaling ratios (i.e 2304/1920
807 * horizontal and 1440/1200 vertical) to the plane's x and y, then
808 * we add stream destination offsets (i.e 128 horizontal, 0 vertical).
809 * This will give us a plane rect's position in Timing Active. However
810 * we have to remove the fractional. The rule is that we find left/right
811 * and top/bottom positions and round the value to the adjacent integer.
812 *
813 * Stream Source Space
814 * ------------
815 * __________________________________________________
816 * |Stream Source (1920 x 1200) ^ |
817 * | y |
818 * | <------- w --------|> |
819 * | __________________V |
820 * |<-- x -->|Plane//////////////| ^ |
821 * | |(pre scale)////////| | |
822 * | |///////////////////| | |
823 * | |///////////////////| h |
824 * | |///////////////////| | |
825 * | |///////////////////| | |
826 * | |///////////////////| V |
827 * | |
828 * | |
829 * |__________________________________________________|
830 *
831 *
832 * Timing Active Space
833 * ---------------------------------
834 *
835 * Timing Active (2560 x 1440)
836 * __________________________________________________
837 * |*****| Stteam Destination (2304 x 1440) |*****|
838 * |*****| |*****|
839 * |<128>| |*****|
840 * |*****| __________________ |*****|
841 * |*****| |Plane/////////////| |*****|
842 * |*****| |(post scale)//////| |*****|
843 * |*****| |//////////////////| |*****|
844 * |*****| |//////////////////| |*****|
845 * |*****| |//////////////////| |*****|
846 * |*****| |//////////////////| |*****|
847 * |*****| |*****|
848 * |*****| |*****|
849 * |*****| |*****|
850 * |*****|______________________________________|*****|
851 *
852 * So the resulting formulas are shown below:
853 *
854 * recout_x = 128 + round(plane_x * 2304 / 1920)
855 * recout_w = 128 + round((plane_x + plane_w) * 2304 / 1920) - recout_x
856 * recout_y = 0 + round(plane_y * 1440 / 1280)
857 * recout_h = 0 + round((plane_y + plane_h) * 1440 / 1200) - recout_y
858 *
859 * NOTE: fixed point division is not error free. To reduce errors
860 * introduced by fixed point division, we divide only after
861 * multiplication is complete.
862 */
863 const struct dc_stream_state *stream = pipe_ctx->stream;
864 struct rect rec_out = {0};
865 struct fixed31_32 temp;
866
867 temp = dc_fixpt_from_fraction(rec_in->x * (long long)stream->dst.width,
868 stream->src.width);
869 rec_out.x = stream->dst.x + dc_fixpt_round(temp);
870
871 temp = dc_fixpt_from_fraction(
872 (rec_in->x + rec_in->width) * (long long)stream->dst.width,
873 stream->src.width);
874 rec_out.width = stream->dst.x + dc_fixpt_round(temp) - rec_out.x;
875
876 temp = dc_fixpt_from_fraction(rec_in->y * (long long)stream->dst.height,
877 stream->src.height);
878 rec_out.y = stream->dst.y + dc_fixpt_round(temp);
879
880 temp = dc_fixpt_from_fraction(
881 (rec_in->y + rec_in->height) * (long long)stream->dst.height,
882 stream->src.height);
883 rec_out.height = stream->dst.y + dc_fixpt_round(temp) - rec_out.y;
884
885 return rec_out;
886 }
887
calculate_mpc_slice_in_timing_active(struct pipe_ctx * pipe_ctx,struct rect * plane_clip_rec)888 static struct rect calculate_mpc_slice_in_timing_active(
889 struct pipe_ctx *pipe_ctx,
890 struct rect *plane_clip_rec)
891 {
892 const struct dc_stream_state *stream = pipe_ctx->stream;
893 int mpc_slice_count = resource_get_mpc_slice_count(pipe_ctx);
894 int mpc_slice_idx = resource_get_mpc_slice_index(pipe_ctx);
895 int epimo = mpc_slice_count - plane_clip_rec->width % mpc_slice_count - 1;
896 struct rect mpc_rec;
897
898 mpc_rec.width = plane_clip_rec->width / mpc_slice_count;
899 mpc_rec.x = plane_clip_rec->x + mpc_rec.width * mpc_slice_idx;
900 mpc_rec.height = plane_clip_rec->height;
901 mpc_rec.y = plane_clip_rec->y;
902 ASSERT(mpc_slice_count == 1 ||
903 stream->view_format != VIEW_3D_FORMAT_SIDE_BY_SIDE ||
904 mpc_rec.width % 2 == 0);
905
906 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
907 mpc_rec.x -= (mpc_rec.width * mpc_slice_idx);
908
909 /* extra pixels in the division remainder need to go to pipes after
910 * the extra pixel index minus one(epimo) defined here as:
911 */
912 if (mpc_slice_idx > epimo) {
913 mpc_rec.x += mpc_slice_idx - epimo - 1;
914 mpc_rec.width += 1;
915 }
916
917 if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) {
918 ASSERT(mpc_rec.height % 2 == 0);
919 mpc_rec.height /= 2;
920 }
921 return mpc_rec;
922 }
923
calculate_adjust_recout_for_visual_confirm(struct pipe_ctx * pipe_ctx,int * base_offset,int * dpp_offset)924 static void calculate_adjust_recout_for_visual_confirm(struct pipe_ctx *pipe_ctx,
925 int *base_offset, int *dpp_offset)
926 {
927 struct dc *dc = pipe_ctx->stream->ctx->dc;
928 *base_offset = 0;
929 *dpp_offset = 0;
930
931 if (dc->debug.visual_confirm == VISUAL_CONFIRM_DISABLE || !pipe_ctx->plane_res.dpp)
932 return;
933
934 *dpp_offset = pipe_ctx->stream->timing.v_addressable / VISUAL_CONFIRM_DPP_OFFSET_DENO;
935 *dpp_offset *= pipe_ctx->plane_res.dpp->inst;
936
937 if ((dc->debug.visual_confirm_rect_height >= VISUAL_CONFIRM_BASE_MIN) &&
938 dc->debug.visual_confirm_rect_height <= VISUAL_CONFIRM_BASE_MAX)
939 *base_offset = dc->debug.visual_confirm_rect_height;
940 else
941 *base_offset = VISUAL_CONFIRM_BASE_DEFAULT;
942 }
943
adjust_recout_for_visual_confirm(struct rect * recout,struct pipe_ctx * pipe_ctx)944 static void adjust_recout_for_visual_confirm(struct rect *recout,
945 struct pipe_ctx *pipe_ctx)
946 {
947 int dpp_offset, base_offset;
948
949 calculate_adjust_recout_for_visual_confirm(pipe_ctx, &base_offset,
950 &dpp_offset);
951 recout->height -= base_offset;
952 recout->height -= dpp_offset;
953 }
954
955 /*
956 * The function maps a plane clip from Stream Source Space to ODM Slice Space
957 * and calculates the rec of the overlapping area of MPC slice of the plane
958 * clip, ODM slice associated with the pipe context and stream destination rec.
959 */
calculate_recout(struct pipe_ctx * pipe_ctx)960 static void calculate_recout(struct pipe_ctx *pipe_ctx)
961 {
962 /*
963 * A plane clip represents the desired plane size and position in Stream
964 * Source Space. Stream Source is the destination where all planes are
965 * blended (i.e. positioned, scaled and overlaid). It is a canvas where
966 * all planes associated with the current stream are drawn together.
967 * After Stream Source is completed, we will further scale and
968 * reposition the entire canvas of the stream source to Stream
969 * Destination in Timing Active Space. This could be due to display
970 * overscan adjustment where we will need to rescale and reposition all
971 * the planes so they can fit into a TV with overscan or downscale
972 * upscale features such as GPU scaling or VSR.
973 *
974 * This two step blending is a virtual procedure in software. In
975 * hardware there is no such thing as Stream Source. all planes are
976 * blended once in Timing Active Space. Software virtualizes a Stream
977 * Source space to decouple the math complicity so scaling param
978 * calculation focuses on one step at a time.
979 *
980 * In the following two diagrams, user applied 10% overscan adjustment
981 * so the Stream Source needs to be scaled down a little before mapping
982 * to Timing Active Space. As a result the Plane Clip is also scaled
983 * down by the same ratio, Plane Clip position (i.e. x and y) with
984 * respect to Stream Source is also scaled down. To map it in Timing
985 * Active Space additional x and y offsets from Stream Destination are
986 * added to Plane Clip as well.
987 *
988 * Stream Source Space
989 * ------------
990 * __________________________________________________
991 * |Stream Source (3840 x 2160) ^ |
992 * | y |
993 * | | |
994 * | __________________V |
995 * |<-- x -->|Plane Clip/////////| |
996 * | |(pre scale)////////| |
997 * | |///////////////////| |
998 * | |///////////////////| |
999 * | |///////////////////| |
1000 * | |///////////////////| |
1001 * | |///////////////////| |
1002 * | |
1003 * | |
1004 * |__________________________________________________|
1005 *
1006 *
1007 * Timing Active Space (3840 x 2160)
1008 * ---------------------------------
1009 *
1010 * Timing Active
1011 * __________________________________________________
1012 * | y_____________________________________________ |
1013 * |x |Stream Destination (3456 x 1944) | |
1014 * | | | |
1015 * | | __________________ | |
1016 * | | |Plane Clip////////| | |
1017 * | | |(post scale)//////| | |
1018 * | | |//////////////////| | |
1019 * | | |//////////////////| | |
1020 * | | |//////////////////| | |
1021 * | | |//////////////////| | |
1022 * | | | |
1023 * | | | |
1024 * | |____________________________________________| |
1025 * |__________________________________________________|
1026 *
1027 *
1028 * In Timing Active Space a plane clip could be further sliced into
1029 * pieces called MPC slices. Each Pipe Context is responsible for
1030 * processing only one MPC slice so the plane processing workload can be
1031 * distributed to multiple DPP Pipes. MPC slices could be blended
1032 * together to a single ODM slice. Each ODM slice is responsible for
1033 * processing a portion of Timing Active divided horizontally so the
1034 * output pixel processing workload can be distributed to multiple OPP
1035 * pipes. All ODM slices are mapped together in ODM block so all MPC
1036 * slices belong to different ODM slices could be pieced together to
1037 * form a single image in Timing Active. MPC slices must belong to
1038 * single ODM slice. If an MPC slice goes across ODM slice boundary, it
1039 * needs to be divided into two MPC slices one for each ODM slice.
1040 *
1041 * In the following diagram the output pixel processing workload is
1042 * divided horizontally into two ODM slices one for each OPP blend tree.
1043 * OPP0 blend tree is responsible for processing left half of Timing
1044 * Active, while OPP2 blend tree is responsible for processing right
1045 * half.
1046 *
1047 * The plane has two MPC slices. However since the right MPC slice goes
1048 * across ODM boundary, two DPP pipes are needed one for each OPP blend
1049 * tree. (i.e. DPP1 for OPP0 blend tree and DPP2 for OPP2 blend tree).
1050 *
1051 * Assuming that we have a Pipe Context associated with OPP0 and DPP1
1052 * working on processing the plane in the diagram. We want to know the
1053 * width and height of the shaded rectangle and its relative position
1054 * with respect to the ODM slice0. This is called the recout of the pipe
1055 * context.
1056 *
1057 * Planes can be at arbitrary size and position and there could be an
1058 * arbitrary number of MPC and ODM slices. The algorithm needs to take
1059 * all scenarios into account.
1060 *
1061 * Timing Active Space (3840 x 2160)
1062 * ---------------------------------
1063 *
1064 * Timing Active
1065 * __________________________________________________
1066 * |OPP0(ODM slice0)^ |OPP2(ODM slice1) |
1067 * | y | |
1068 * | | <- w -> |
1069 * | _____V________|____ |
1070 * | |DPP0 ^ |DPP1 |DPP2| |
1071 * |<------ x |-----|->|/////| | |
1072 * | | | |/////| | |
1073 * | | h |/////| | |
1074 * | | | |/////| | |
1075 * | |_____V__|/////|____| |
1076 * | | |
1077 * | | |
1078 * | | |
1079 * |_________________________|________________________|
1080 *
1081 *
1082 */
1083 struct rect plane_clip;
1084 struct rect mpc_slice_of_plane_clip;
1085 struct rect odm_slice_src;
1086 struct rect overlapping_area;
1087
1088 plane_clip = calculate_plane_rec_in_timing_active(pipe_ctx,
1089 &pipe_ctx->plane_state->clip_rect);
1090 /* guard plane clip from drawing beyond stream dst here */
1091 plane_clip = intersect_rec(&plane_clip,
1092 &pipe_ctx->stream->dst);
1093 mpc_slice_of_plane_clip = calculate_mpc_slice_in_timing_active(
1094 pipe_ctx, &plane_clip);
1095 odm_slice_src = resource_get_odm_slice_src_rect(pipe_ctx);
1096 overlapping_area = intersect_rec(&mpc_slice_of_plane_clip, &odm_slice_src);
1097 if (overlapping_area.height > 0 &&
1098 overlapping_area.width > 0) {
1099 /* shift the overlapping area so it is with respect to current
1100 * ODM slice source's position
1101 */
1102 pipe_ctx->plane_res.scl_data.recout = shift_rec(
1103 &overlapping_area,
1104 -odm_slice_src.x, -odm_slice_src.y);
1105 adjust_recout_for_visual_confirm(
1106 &pipe_ctx->plane_res.scl_data.recout,
1107 pipe_ctx);
1108 } else {
1109 /* if there is no overlap, zero recout */
1110 memset(&pipe_ctx->plane_res.scl_data.recout, 0,
1111 sizeof(struct rect));
1112 }
1113
1114 }
1115
calculate_scaling_ratios(struct pipe_ctx * pipe_ctx)1116 static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
1117 {
1118 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1119 const struct dc_stream_state *stream = pipe_ctx->stream;
1120 struct rect surf_src = plane_state->src_rect;
1121 const int in_w = stream->src.width;
1122 const int in_h = stream->src.height;
1123 const int out_w = stream->dst.width;
1124 const int out_h = stream->dst.height;
1125
1126 /*Swap surf_src height and width since scaling ratios are in recout rotation*/
1127 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
1128 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
1129 swap(surf_src.height, surf_src.width);
1130
1131 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction(
1132 surf_src.width,
1133 plane_state->dst_rect.width);
1134 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction(
1135 surf_src.height,
1136 plane_state->dst_rect.height);
1137
1138 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
1139 pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2;
1140 else if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
1141 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2;
1142
1143 pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64(
1144 pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h);
1145 pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64(
1146 pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w);
1147
1148 pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz;
1149 pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert;
1150
1151 if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8
1152 || pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) {
1153 pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2;
1154 pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2;
1155 }
1156 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_truncate(
1157 pipe_ctx->plane_res.scl_data.ratios.horz, 19);
1158 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_truncate(
1159 pipe_ctx->plane_res.scl_data.ratios.vert, 19);
1160 pipe_ctx->plane_res.scl_data.ratios.horz_c = dc_fixpt_truncate(
1161 pipe_ctx->plane_res.scl_data.ratios.horz_c, 19);
1162 pipe_ctx->plane_res.scl_data.ratios.vert_c = dc_fixpt_truncate(
1163 pipe_ctx->plane_res.scl_data.ratios.vert_c, 19);
1164 }
1165
1166
1167 /*
1168 * We completely calculate vp offset, size and inits here based entirely on scaling
1169 * ratios and recout for pixel perfect pipe combine.
1170 */
calculate_init_and_vp(bool flip_scan_dir,int recout_offset_within_recout_full,int recout_size,int src_size,int taps,struct fixed31_32 ratio,struct fixed31_32 * init,int * vp_offset,int * vp_size)1171 static void calculate_init_and_vp(
1172 bool flip_scan_dir,
1173 int recout_offset_within_recout_full,
1174 int recout_size,
1175 int src_size,
1176 int taps,
1177 struct fixed31_32 ratio,
1178 struct fixed31_32 *init,
1179 int *vp_offset,
1180 int *vp_size)
1181 {
1182 struct fixed31_32 temp;
1183 int int_part;
1184
1185 /*
1186 * First of the taps starts sampling pixel number <init_int_part> corresponding to recout
1187 * pixel 1. Next recout pixel samples int part of <init + scaling ratio> and so on.
1188 * All following calculations are based on this logic.
1189 *
1190 * Init calculated according to formula:
1191 * init = (scaling_ratio + number_of_taps + 1) / 2
1192 * init_bot = init + scaling_ratio
1193 * to get pixel perfect combine add the fraction from calculating vp offset
1194 */
1195 temp = dc_fixpt_mul_int(ratio, recout_offset_within_recout_full);
1196 *vp_offset = dc_fixpt_floor(temp);
1197 temp.value &= 0xffffffff;
1198 *init = dc_fixpt_truncate(dc_fixpt_add(dc_fixpt_div_int(
1199 dc_fixpt_add_int(ratio, taps + 1), 2), temp), 19);
1200 /*
1201 * If viewport has non 0 offset and there are more taps than covered by init then
1202 * we should decrease the offset and increase init so we are never sampling
1203 * outside of viewport.
1204 */
1205 int_part = dc_fixpt_floor(*init);
1206 if (int_part < taps) {
1207 int_part = taps - int_part;
1208 if (int_part > *vp_offset)
1209 int_part = *vp_offset;
1210 *vp_offset -= int_part;
1211 *init = dc_fixpt_add_int(*init, int_part);
1212 }
1213 /*
1214 * If taps are sampling outside of viewport at end of recout and there are more pixels
1215 * available in the surface we should increase the viewport size, regardless set vp to
1216 * only what is used.
1217 */
1218 temp = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_size - 1));
1219 *vp_size = dc_fixpt_floor(temp);
1220 if (*vp_size + *vp_offset > src_size)
1221 *vp_size = src_size - *vp_offset;
1222
1223 /* We did all the math assuming we are scanning same direction as display does,
1224 * however mirror/rotation changes how vp scans vs how it is offset. If scan direction
1225 * is flipped we simply need to calculate offset from the other side of plane.
1226 * Note that outside of viewport all scaling hardware works in recout space.
1227 */
1228 if (flip_scan_dir)
1229 *vp_offset = src_size - *vp_offset - *vp_size;
1230 }
1231
calculate_inits_and_viewports(struct pipe_ctx * pipe_ctx)1232 static void calculate_inits_and_viewports(struct pipe_ctx *pipe_ctx)
1233 {
1234 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1235 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
1236 struct rect src = plane_state->src_rect;
1237 struct rect recout_dst_in_active_timing;
1238 struct rect recout_clip_in_active_timing;
1239 struct rect recout_clip_in_recout_dst;
1240 struct rect overlap_in_active_timing;
1241 struct rect odm_slice_src = resource_get_odm_slice_src_rect(pipe_ctx);
1242 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
1243 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
1244 bool orthogonal_rotation, flip_vert_scan_dir, flip_horz_scan_dir;
1245
1246 recout_clip_in_active_timing = shift_rec(
1247 &data->recout, odm_slice_src.x, odm_slice_src.y);
1248 recout_dst_in_active_timing = calculate_plane_rec_in_timing_active(
1249 pipe_ctx, &plane_state->dst_rect);
1250 overlap_in_active_timing = intersect_rec(&recout_clip_in_active_timing,
1251 &recout_dst_in_active_timing);
1252 if (overlap_in_active_timing.width > 0 &&
1253 overlap_in_active_timing.height > 0)
1254 recout_clip_in_recout_dst = shift_rec(&overlap_in_active_timing,
1255 -recout_dst_in_active_timing.x,
1256 -recout_dst_in_active_timing.y);
1257 else
1258 memset(&recout_clip_in_recout_dst, 0, sizeof(struct rect));
1259
1260 /*
1261 * Work in recout rotation since that requires less transformations
1262 */
1263 get_vp_scan_direction(
1264 plane_state->rotation,
1265 plane_state->horizontal_mirror,
1266 &orthogonal_rotation,
1267 &flip_vert_scan_dir,
1268 &flip_horz_scan_dir);
1269
1270 if (orthogonal_rotation) {
1271 swap(src.width, src.height);
1272 swap(flip_vert_scan_dir, flip_horz_scan_dir);
1273 }
1274
1275 calculate_init_and_vp(
1276 flip_horz_scan_dir,
1277 recout_clip_in_recout_dst.x,
1278 data->recout.width,
1279 src.width,
1280 data->taps.h_taps,
1281 data->ratios.horz,
1282 &data->inits.h,
1283 &data->viewport.x,
1284 &data->viewport.width);
1285 calculate_init_and_vp(
1286 flip_horz_scan_dir,
1287 recout_clip_in_recout_dst.x,
1288 data->recout.width,
1289 src.width / vpc_div,
1290 data->taps.h_taps_c,
1291 data->ratios.horz_c,
1292 &data->inits.h_c,
1293 &data->viewport_c.x,
1294 &data->viewport_c.width);
1295 calculate_init_and_vp(
1296 flip_vert_scan_dir,
1297 recout_clip_in_recout_dst.y,
1298 data->recout.height,
1299 src.height,
1300 data->taps.v_taps,
1301 data->ratios.vert,
1302 &data->inits.v,
1303 &data->viewport.y,
1304 &data->viewport.height);
1305 calculate_init_and_vp(
1306 flip_vert_scan_dir,
1307 recout_clip_in_recout_dst.y,
1308 data->recout.height,
1309 src.height / vpc_div,
1310 data->taps.v_taps_c,
1311 data->ratios.vert_c,
1312 &data->inits.v_c,
1313 &data->viewport_c.y,
1314 &data->viewport_c.height);
1315 if (orthogonal_rotation) {
1316 swap(data->viewport.x, data->viewport.y);
1317 swap(data->viewport.width, data->viewport.height);
1318 swap(data->viewport_c.x, data->viewport_c.y);
1319 swap(data->viewport_c.width, data->viewport_c.height);
1320 }
1321 data->viewport.x += src.x;
1322 data->viewport.y += src.y;
1323 ASSERT(src.x % vpc_div == 0 && src.y % vpc_div == 0);
1324 data->viewport_c.x += src.x / vpc_div;
1325 data->viewport_c.y += src.y / vpc_div;
1326 }
1327
is_subvp_high_refresh_candidate(struct dc_stream_state * stream)1328 static bool is_subvp_high_refresh_candidate(struct dc_stream_state *stream)
1329 {
1330 uint32_t refresh_rate;
1331 struct dc *dc = stream->ctx->dc;
1332
1333 refresh_rate = (stream->timing.pix_clk_100hz * (uint64_t)100 +
1334 stream->timing.v_total * stream->timing.h_total - (uint64_t)1);
1335 refresh_rate = div_u64(refresh_rate, stream->timing.v_total);
1336 refresh_rate = div_u64(refresh_rate, stream->timing.h_total);
1337
1338 /* If there's any stream that fits the SubVP high refresh criteria,
1339 * we must return true. This is because cursor updates are asynchronous
1340 * with full updates, so we could transition into a SubVP config and
1341 * remain in HW cursor mode if there's no cursor update which will
1342 * then cause corruption.
1343 */
1344 if ((refresh_rate >= 120 && refresh_rate <= 175 &&
1345 stream->timing.v_addressable >= 1080 &&
1346 stream->timing.v_addressable <= 2160) &&
1347 (dc->current_state->stream_count > 1 ||
1348 (dc->current_state->stream_count == 1 && !stream->allow_freesync)))
1349 return true;
1350
1351 return false;
1352 }
1353
convert_dp_to_controller_test_pattern(enum dp_test_pattern test_pattern)1354 static enum controller_dp_test_pattern convert_dp_to_controller_test_pattern(
1355 enum dp_test_pattern test_pattern)
1356 {
1357 enum controller_dp_test_pattern controller_test_pattern;
1358
1359 switch (test_pattern) {
1360 case DP_TEST_PATTERN_COLOR_SQUARES:
1361 controller_test_pattern =
1362 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
1363 break;
1364 case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
1365 controller_test_pattern =
1366 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA;
1367 break;
1368 case DP_TEST_PATTERN_VERTICAL_BARS:
1369 controller_test_pattern =
1370 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS;
1371 break;
1372 case DP_TEST_PATTERN_HORIZONTAL_BARS:
1373 controller_test_pattern =
1374 CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS;
1375 break;
1376 case DP_TEST_PATTERN_COLOR_RAMP:
1377 controller_test_pattern =
1378 CONTROLLER_DP_TEST_PATTERN_COLORRAMP;
1379 break;
1380 default:
1381 controller_test_pattern =
1382 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
1383 break;
1384 }
1385
1386 return controller_test_pattern;
1387 }
1388
convert_dp_to_controller_color_space(enum dp_test_pattern_color_space color_space)1389 static enum controller_dp_color_space convert_dp_to_controller_color_space(
1390 enum dp_test_pattern_color_space color_space)
1391 {
1392 enum controller_dp_color_space controller_color_space;
1393
1394 switch (color_space) {
1395 case DP_TEST_PATTERN_COLOR_SPACE_RGB:
1396 controller_color_space = CONTROLLER_DP_COLOR_SPACE_RGB;
1397 break;
1398 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
1399 controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR601;
1400 break;
1401 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
1402 controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR709;
1403 break;
1404 case DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED:
1405 default:
1406 controller_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED;
1407 break;
1408 }
1409
1410 return controller_color_space;
1411 }
1412
resource_build_test_pattern_params(struct resource_context * res_ctx,struct pipe_ctx * otg_master)1413 void resource_build_test_pattern_params(struct resource_context *res_ctx,
1414 struct pipe_ctx *otg_master)
1415 {
1416 struct pipe_ctx *opp_heads[MAX_PIPES];
1417 struct test_pattern_params *params;
1418 int odm_cnt;
1419 enum controller_dp_test_pattern controller_test_pattern;
1420 enum controller_dp_color_space controller_color_space;
1421 enum dc_color_depth color_depth = otg_master->stream->timing.display_color_depth;
1422 struct rect odm_slice_src;
1423 int i;
1424
1425 controller_test_pattern = convert_dp_to_controller_test_pattern(
1426 otg_master->stream->test_pattern.type);
1427 controller_color_space = convert_dp_to_controller_color_space(
1428 otg_master->stream->test_pattern.color_space);
1429
1430 if (controller_test_pattern == CONTROLLER_DP_TEST_PATTERN_VIDEOMODE)
1431 return;
1432
1433 odm_cnt = resource_get_opp_heads_for_otg_master(otg_master, res_ctx, opp_heads);
1434
1435 for (i = 0; i < odm_cnt; i++) {
1436 odm_slice_src = resource_get_odm_slice_src_rect(opp_heads[i]);
1437 params = &opp_heads[i]->stream_res.test_pattern_params;
1438 params->test_pattern = controller_test_pattern;
1439 params->color_space = controller_color_space;
1440 params->color_depth = color_depth;
1441 params->height = odm_slice_src.height;
1442 params->offset = odm_slice_src.x;
1443 params->width = odm_slice_src.width;
1444 }
1445 }
1446
resource_build_scaling_params(struct pipe_ctx * pipe_ctx)1447 bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
1448 {
1449 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1450 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
1451 const struct rect odm_slice_src = resource_get_odm_slice_src_rect(pipe_ctx);
1452 struct scaling_taps temp = {0};
1453 bool res = false;
1454
1455 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
1456
1457 /* Invalid input */
1458 if (!plane_state->dst_rect.width ||
1459 !plane_state->dst_rect.height ||
1460 !plane_state->src_rect.width ||
1461 !plane_state->src_rect.height) {
1462 ASSERT(0);
1463 return false;
1464 }
1465
1466 /* Timing borders are part of vactive that we are also supposed to skip in addition
1467 * to any stream dst offset. Since dm logic assumes dst is in addressable
1468 * space we need to add the left and top borders to dst offsets temporarily.
1469 * TODO: fix in DM, stream dst is supposed to be in vactive
1470 */
1471 pipe_ctx->stream->dst.x += timing->h_border_left;
1472 pipe_ctx->stream->dst.y += timing->v_border_top;
1473
1474 /* Calculate H and V active size */
1475 pipe_ctx->plane_res.scl_data.h_active = odm_slice_src.width;
1476 pipe_ctx->plane_res.scl_data.v_active = odm_slice_src.height;
1477 pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(
1478 pipe_ctx->plane_state->format);
1479
1480 #if defined(CONFIG_DRM_AMD_DC_FP)
1481 if ((pipe_ctx->stream->ctx->dc->config.use_spl) && (!pipe_ctx->stream->ctx->dc->debug.disable_spl)) {
1482 struct spl_in *spl_in = &pipe_ctx->plane_res.spl_in;
1483 struct spl_out *spl_out = &pipe_ctx->plane_res.spl_out;
1484
1485 if (plane_state->ctx->dce_version > DCE_VERSION_MAX)
1486 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_36BPP;
1487 else
1488 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
1489
1490 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = plane_state->per_pixel_alpha;
1491
1492 // Convert pipe_ctx to respective input params for SPL
1493 translate_SPL_in_params_from_pipe_ctx(pipe_ctx, spl_in);
1494 /* Pass visual confirm debug information */
1495 calculate_adjust_recout_for_visual_confirm(pipe_ctx,
1496 &spl_in->debug.visual_confirm_base_offset,
1497 &spl_in->debug.visual_confirm_dpp_offset);
1498 // Set SPL output parameters to dscl_prog_data to be used for hw registers
1499 spl_out->dscl_prog_data = resource_get_dscl_prog_data(pipe_ctx);
1500 // Calculate scaler parameters from SPL
1501 res = spl_calculate_scaler_params(spl_in, spl_out);
1502 // Convert respective out params from SPL to scaler data
1503 translate_SPL_out_params_to_pipe_ctx(pipe_ctx, spl_out);
1504
1505 /* Ignore scaler failure if pipe context plane is phantom plane */
1506 if (!res && plane_state->is_phantom)
1507 res = true;
1508 } else {
1509 #endif
1510 /* depends on h_active */
1511 calculate_recout(pipe_ctx);
1512 /* depends on pixel format */
1513 calculate_scaling_ratios(pipe_ctx);
1514
1515 /*
1516 * LB calculations depend on vp size, h/v_active and scaling ratios
1517 * Setting line buffer pixel depth to 24bpp yields banding
1518 * on certain displays, such as the Sharp 4k. 36bpp is needed
1519 * to support SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 and
1520 * SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 with actual > 10 bpc
1521 * precision on DCN display engines, but apparently not for DCE, as
1522 * far as testing on DCE-11.2 and DCE-8 showed. Various DCE parts have
1523 * problems: Carrizo with DCE_VERSION_11_0 does not like 36 bpp lb depth,
1524 * neither do DCE-8 at 4k resolution, or DCE-11.2 (broken identify pixel
1525 * passthrough). Therefore only use 36 bpp on DCN where it is actually needed.
1526 */
1527 if (plane_state->ctx->dce_version > DCE_VERSION_MAX)
1528 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_36BPP;
1529 else
1530 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
1531
1532 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = plane_state->per_pixel_alpha;
1533
1534 // get TAP value with 100x100 dummy data for max scaling qualify, override
1535 // if a new scaling quality required
1536 pipe_ctx->plane_res.scl_data.viewport.width = 100;
1537 pipe_ctx->plane_res.scl_data.viewport.height = 100;
1538 pipe_ctx->plane_res.scl_data.viewport_c.width = 100;
1539 pipe_ctx->plane_res.scl_data.viewport_c.height = 100;
1540 if (pipe_ctx->plane_res.xfm != NULL)
1541 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
1542 pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
1543
1544 if (pipe_ctx->plane_res.dpp != NULL)
1545 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
1546 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
1547
1548 temp = pipe_ctx->plane_res.scl_data.taps;
1549
1550 calculate_inits_and_viewports(pipe_ctx);
1551
1552 if (pipe_ctx->plane_res.xfm != NULL)
1553 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
1554 pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
1555
1556 if (pipe_ctx->plane_res.dpp != NULL)
1557 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
1558 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
1559
1560
1561 if (!res) {
1562 /* Try 24 bpp linebuffer */
1563 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP;
1564
1565 if (pipe_ctx->plane_res.xfm != NULL)
1566 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
1567 pipe_ctx->plane_res.xfm,
1568 &pipe_ctx->plane_res.scl_data,
1569 &plane_state->scaling_quality);
1570
1571 if (pipe_ctx->plane_res.dpp != NULL)
1572 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
1573 pipe_ctx->plane_res.dpp,
1574 &pipe_ctx->plane_res.scl_data,
1575 &plane_state->scaling_quality);
1576 }
1577
1578 /* Ignore scaler failure if pipe context plane is phantom plane */
1579 if (!res && plane_state->is_phantom)
1580 res = true;
1581
1582 if (res && (pipe_ctx->plane_res.scl_data.taps.v_taps != temp.v_taps ||
1583 pipe_ctx->plane_res.scl_data.taps.h_taps != temp.h_taps ||
1584 pipe_ctx->plane_res.scl_data.taps.v_taps_c != temp.v_taps_c ||
1585 pipe_ctx->plane_res.scl_data.taps.h_taps_c != temp.h_taps_c))
1586 calculate_inits_and_viewports(pipe_ctx);
1587
1588 /*
1589 * Handle side by side and top bottom 3d recout offsets after vp calculation
1590 * since 3d is special and needs to calculate vp as if there is no recout offset
1591 * This may break with rotation, good thing we aren't mixing hw rotation and 3d
1592 */
1593 if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->plane_state == plane_state) {
1594 ASSERT(plane_state->rotation == ROTATION_ANGLE_0 ||
1595 (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_TOP_AND_BOTTOM &&
1596 pipe_ctx->stream->view_format != VIEW_3D_FORMAT_SIDE_BY_SIDE));
1597 if (pipe_ctx->stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
1598 pipe_ctx->plane_res.scl_data.recout.y += pipe_ctx->plane_res.scl_data.recout.height;
1599 else if (pipe_ctx->stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
1600 pipe_ctx->plane_res.scl_data.recout.x += pipe_ctx->plane_res.scl_data.recout.width;
1601 }
1602
1603 /* Clamp minimum viewport size */
1604 if (pipe_ctx->plane_res.scl_data.viewport.height < MIN_VIEWPORT_SIZE)
1605 pipe_ctx->plane_res.scl_data.viewport.height = MIN_VIEWPORT_SIZE;
1606 if (pipe_ctx->plane_res.scl_data.viewport.width < MIN_VIEWPORT_SIZE)
1607 pipe_ctx->plane_res.scl_data.viewport.width = MIN_VIEWPORT_SIZE;
1608 #ifdef CONFIG_DRM_AMD_DC_FP
1609 }
1610 #endif
1611 DC_LOG_SCALER("%s pipe %d:\nViewport: height:%d width:%d x:%d y:%d Recout: height:%d width:%d x:%d y:%d HACTIVE:%d VACTIVE:%d\n"
1612 "src_rect: height:%d width:%d x:%d y:%d dst_rect: height:%d width:%d x:%d y:%d clip_rect: height:%d width:%d x:%d y:%d\n",
1613 __func__,
1614 pipe_ctx->pipe_idx,
1615 pipe_ctx->plane_res.scl_data.viewport.height,
1616 pipe_ctx->plane_res.scl_data.viewport.width,
1617 pipe_ctx->plane_res.scl_data.viewport.x,
1618 pipe_ctx->plane_res.scl_data.viewport.y,
1619 pipe_ctx->plane_res.scl_data.recout.height,
1620 pipe_ctx->plane_res.scl_data.recout.width,
1621 pipe_ctx->plane_res.scl_data.recout.x,
1622 pipe_ctx->plane_res.scl_data.recout.y,
1623 pipe_ctx->plane_res.scl_data.h_active,
1624 pipe_ctx->plane_res.scl_data.v_active,
1625 plane_state->src_rect.height,
1626 plane_state->src_rect.width,
1627 plane_state->src_rect.x,
1628 plane_state->src_rect.y,
1629 plane_state->dst_rect.height,
1630 plane_state->dst_rect.width,
1631 plane_state->dst_rect.x,
1632 plane_state->dst_rect.y,
1633 plane_state->clip_rect.height,
1634 plane_state->clip_rect.width,
1635 plane_state->clip_rect.x,
1636 plane_state->clip_rect.y);
1637
1638 pipe_ctx->stream->dst.x -= timing->h_border_left;
1639 pipe_ctx->stream->dst.y -= timing->v_border_top;
1640
1641 return res;
1642 }
1643
1644
resource_build_scaling_params_for_context(const struct dc * dc,struct dc_state * context)1645 enum dc_status resource_build_scaling_params_for_context(
1646 const struct dc *dc,
1647 struct dc_state *context)
1648 {
1649 int i;
1650
1651 for (i = 0; i < MAX_PIPES; i++) {
1652 if (context->res_ctx.pipe_ctx[i].plane_state != NULL &&
1653 context->res_ctx.pipe_ctx[i].stream != NULL)
1654 if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i]))
1655 return DC_FAIL_SCALING;
1656 }
1657
1658 return DC_OK;
1659 }
1660
resource_find_free_secondary_pipe_legacy(struct resource_context * res_ctx,const struct resource_pool * pool,const struct pipe_ctx * primary_pipe)1661 struct pipe_ctx *resource_find_free_secondary_pipe_legacy(
1662 struct resource_context *res_ctx,
1663 const struct resource_pool *pool,
1664 const struct pipe_ctx *primary_pipe)
1665 {
1666 int i;
1667 struct pipe_ctx *secondary_pipe = NULL;
1668
1669 /*
1670 * We add a preferred pipe mapping to avoid the chance that
1671 * MPCCs already in use will need to be reassigned to other trees.
1672 * For example, if we went with the strict, assign backwards logic:
1673 *
1674 * (State 1)
1675 * Display A on, no surface, top pipe = 0
1676 * Display B on, no surface, top pipe = 1
1677 *
1678 * (State 2)
1679 * Display A on, no surface, top pipe = 0
1680 * Display B on, surface enable, top pipe = 1, bottom pipe = 5
1681 *
1682 * (State 3)
1683 * Display A on, surface enable, top pipe = 0, bottom pipe = 5
1684 * Display B on, surface enable, top pipe = 1, bottom pipe = 4
1685 *
1686 * The state 2->3 transition requires remapping MPCC 5 from display B
1687 * to display A.
1688 *
1689 * However, with the preferred pipe logic, state 2 would look like:
1690 *
1691 * (State 2)
1692 * Display A on, no surface, top pipe = 0
1693 * Display B on, surface enable, top pipe = 1, bottom pipe = 4
1694 *
1695 * This would then cause 2->3 to not require remapping any MPCCs.
1696 */
1697 if (primary_pipe) {
1698 int preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx;
1699 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
1700 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
1701 secondary_pipe->pipe_idx = preferred_pipe_idx;
1702 }
1703 }
1704
1705 /*
1706 * search backwards for the second pipe to keep pipe
1707 * assignment more consistent
1708 */
1709 if (!secondary_pipe)
1710 for (i = pool->pipe_count - 1; i >= 0; i--) {
1711 if (res_ctx->pipe_ctx[i].stream == NULL) {
1712 secondary_pipe = &res_ctx->pipe_ctx[i];
1713 secondary_pipe->pipe_idx = i;
1714 break;
1715 }
1716 }
1717
1718 return secondary_pipe;
1719 }
1720
resource_find_free_pipe_used_as_sec_opp_head_by_cur_otg_master(const struct resource_context * cur_res_ctx,struct resource_context * new_res_ctx,const struct pipe_ctx * cur_otg_master)1721 int resource_find_free_pipe_used_as_sec_opp_head_by_cur_otg_master(
1722 const struct resource_context *cur_res_ctx,
1723 struct resource_context *new_res_ctx,
1724 const struct pipe_ctx *cur_otg_master)
1725 {
1726 const struct pipe_ctx *cur_sec_opp_head = cur_otg_master->next_odm_pipe;
1727 struct pipe_ctx *new_pipe;
1728 int free_pipe_idx = FREE_PIPE_INDEX_NOT_FOUND;
1729
1730 while (cur_sec_opp_head) {
1731 new_pipe = &new_res_ctx->pipe_ctx[cur_sec_opp_head->pipe_idx];
1732 if (resource_is_pipe_type(new_pipe, FREE_PIPE)) {
1733 free_pipe_idx = cur_sec_opp_head->pipe_idx;
1734 break;
1735 }
1736 cur_sec_opp_head = cur_sec_opp_head->next_odm_pipe;
1737 }
1738
1739 return free_pipe_idx;
1740 }
1741
resource_find_free_pipe_used_in_cur_mpc_blending_tree(const struct resource_context * cur_res_ctx,struct resource_context * new_res_ctx,const struct pipe_ctx * cur_opp_head)1742 int resource_find_free_pipe_used_in_cur_mpc_blending_tree(
1743 const struct resource_context *cur_res_ctx,
1744 struct resource_context *new_res_ctx,
1745 const struct pipe_ctx *cur_opp_head)
1746 {
1747 const struct pipe_ctx *cur_sec_dpp = cur_opp_head->bottom_pipe;
1748 struct pipe_ctx *new_pipe;
1749 int free_pipe_idx = FREE_PIPE_INDEX_NOT_FOUND;
1750
1751 while (cur_sec_dpp) {
1752 /* find a free pipe used in current opp blend tree,
1753 * this is to avoid MPO pipe switching to different opp blending
1754 * tree
1755 */
1756 new_pipe = &new_res_ctx->pipe_ctx[cur_sec_dpp->pipe_idx];
1757 if (resource_is_pipe_type(new_pipe, FREE_PIPE)) {
1758 free_pipe_idx = cur_sec_dpp->pipe_idx;
1759 break;
1760 }
1761 cur_sec_dpp = cur_sec_dpp->bottom_pipe;
1762 }
1763
1764 return free_pipe_idx;
1765 }
1766
recource_find_free_pipe_not_used_in_cur_res_ctx(const struct resource_context * cur_res_ctx,struct resource_context * new_res_ctx,const struct resource_pool * pool)1767 int recource_find_free_pipe_not_used_in_cur_res_ctx(
1768 const struct resource_context *cur_res_ctx,
1769 struct resource_context *new_res_ctx,
1770 const struct resource_pool *pool)
1771 {
1772 int free_pipe_idx = FREE_PIPE_INDEX_NOT_FOUND;
1773 const struct pipe_ctx *new_pipe, *cur_pipe;
1774 int i;
1775
1776 for (i = 0; i < pool->pipe_count; i++) {
1777 cur_pipe = &cur_res_ctx->pipe_ctx[i];
1778 new_pipe = &new_res_ctx->pipe_ctx[i];
1779
1780 if (resource_is_pipe_type(cur_pipe, FREE_PIPE) &&
1781 resource_is_pipe_type(new_pipe, FREE_PIPE)) {
1782 free_pipe_idx = i;
1783 break;
1784 }
1785 }
1786
1787 return free_pipe_idx;
1788 }
1789
recource_find_free_pipe_used_as_otg_master_in_cur_res_ctx(const struct resource_context * cur_res_ctx,struct resource_context * new_res_ctx,const struct resource_pool * pool)1790 int recource_find_free_pipe_used_as_otg_master_in_cur_res_ctx(
1791 const struct resource_context *cur_res_ctx,
1792 struct resource_context *new_res_ctx,
1793 const struct resource_pool *pool)
1794 {
1795 int free_pipe_idx = FREE_PIPE_INDEX_NOT_FOUND;
1796 const struct pipe_ctx *new_pipe, *cur_pipe;
1797 int i;
1798
1799 for (i = 0; i < pool->pipe_count; i++) {
1800 cur_pipe = &cur_res_ctx->pipe_ctx[i];
1801 new_pipe = &new_res_ctx->pipe_ctx[i];
1802
1803 if (resource_is_pipe_type(cur_pipe, OTG_MASTER) &&
1804 resource_is_pipe_type(new_pipe, FREE_PIPE)) {
1805 free_pipe_idx = i;
1806 break;
1807 }
1808 }
1809
1810 return free_pipe_idx;
1811 }
1812
resource_find_free_pipe_used_as_cur_sec_dpp(const struct resource_context * cur_res_ctx,struct resource_context * new_res_ctx,const struct resource_pool * pool)1813 int resource_find_free_pipe_used_as_cur_sec_dpp(
1814 const struct resource_context *cur_res_ctx,
1815 struct resource_context *new_res_ctx,
1816 const struct resource_pool *pool)
1817 {
1818 int free_pipe_idx = FREE_PIPE_INDEX_NOT_FOUND;
1819 const struct pipe_ctx *new_pipe, *cur_pipe;
1820 int i;
1821
1822 for (i = 0; i < pool->pipe_count; i++) {
1823 cur_pipe = &cur_res_ctx->pipe_ctx[i];
1824 new_pipe = &new_res_ctx->pipe_ctx[i];
1825
1826 if (resource_is_pipe_type(cur_pipe, DPP_PIPE) &&
1827 !resource_is_pipe_type(cur_pipe, OPP_HEAD) &&
1828 resource_is_pipe_type(new_pipe, FREE_PIPE)) {
1829 free_pipe_idx = i;
1830 break;
1831 }
1832 }
1833
1834 return free_pipe_idx;
1835 }
1836
resource_find_free_pipe_used_as_cur_sec_dpp_in_mpcc_combine(const struct resource_context * cur_res_ctx,struct resource_context * new_res_ctx,const struct resource_pool * pool)1837 int resource_find_free_pipe_used_as_cur_sec_dpp_in_mpcc_combine(
1838 const struct resource_context *cur_res_ctx,
1839 struct resource_context *new_res_ctx,
1840 const struct resource_pool *pool)
1841 {
1842 int free_pipe_idx = FREE_PIPE_INDEX_NOT_FOUND;
1843 const struct pipe_ctx *new_pipe, *cur_pipe;
1844 int i;
1845
1846 for (i = 0; i < pool->pipe_count; i++) {
1847 cur_pipe = &cur_res_ctx->pipe_ctx[i];
1848 new_pipe = &new_res_ctx->pipe_ctx[i];
1849
1850 if (resource_is_pipe_type(cur_pipe, DPP_PIPE) &&
1851 !resource_is_pipe_type(cur_pipe, OPP_HEAD) &&
1852 resource_get_mpc_slice_index(cur_pipe) > 0 &&
1853 resource_is_pipe_type(new_pipe, FREE_PIPE)) {
1854 free_pipe_idx = i;
1855 break;
1856 }
1857 }
1858
1859 return free_pipe_idx;
1860 }
1861
resource_find_any_free_pipe(struct resource_context * new_res_ctx,const struct resource_pool * pool)1862 int resource_find_any_free_pipe(struct resource_context *new_res_ctx,
1863 const struct resource_pool *pool)
1864 {
1865 int free_pipe_idx = FREE_PIPE_INDEX_NOT_FOUND;
1866 const struct pipe_ctx *new_pipe;
1867 int i;
1868
1869 for (i = 0; i < pool->pipe_count; i++) {
1870 new_pipe = &new_res_ctx->pipe_ctx[i];
1871
1872 if (resource_is_pipe_type(new_pipe, FREE_PIPE)) {
1873 free_pipe_idx = i;
1874 break;
1875 }
1876 }
1877
1878 return free_pipe_idx;
1879 }
1880
resource_is_pipe_type(const struct pipe_ctx * pipe_ctx,enum pipe_type type)1881 bool resource_is_pipe_type(const struct pipe_ctx *pipe_ctx, enum pipe_type type)
1882 {
1883 switch (type) {
1884 case OTG_MASTER:
1885 return !pipe_ctx->prev_odm_pipe &&
1886 !pipe_ctx->top_pipe &&
1887 pipe_ctx->stream;
1888 case OPP_HEAD:
1889 return !pipe_ctx->top_pipe && pipe_ctx->stream;
1890 case DPP_PIPE:
1891 return pipe_ctx->plane_state && pipe_ctx->stream;
1892 case FREE_PIPE:
1893 return !pipe_ctx->plane_state && !pipe_ctx->stream;
1894 default:
1895 return false;
1896 }
1897 }
1898
resource_get_otg_master_for_stream(struct resource_context * res_ctx,const struct dc_stream_state * stream)1899 struct pipe_ctx *resource_get_otg_master_for_stream(
1900 struct resource_context *res_ctx,
1901 const struct dc_stream_state *stream)
1902 {
1903 int i;
1904
1905 for (i = 0; i < MAX_PIPES; i++) {
1906 if (res_ctx->pipe_ctx[i].stream == stream &&
1907 resource_is_pipe_type(&res_ctx->pipe_ctx[i], OTG_MASTER))
1908 return &res_ctx->pipe_ctx[i];
1909 }
1910 return NULL;
1911 }
1912
resource_get_opp_heads_for_otg_master(const struct pipe_ctx * otg_master,struct resource_context * res_ctx,struct pipe_ctx * opp_heads[MAX_PIPES])1913 int resource_get_opp_heads_for_otg_master(const struct pipe_ctx *otg_master,
1914 struct resource_context *res_ctx,
1915 struct pipe_ctx *opp_heads[MAX_PIPES])
1916 {
1917 struct pipe_ctx *opp_head = &res_ctx->pipe_ctx[otg_master->pipe_idx];
1918 struct dc *dc = otg_master->stream->ctx->dc;
1919 int i = 0;
1920
1921 DC_LOGGER_INIT(dc->ctx->logger);
1922
1923 if (!resource_is_pipe_type(otg_master, OTG_MASTER)) {
1924 DC_LOG_WARNING("%s called from a non OTG master, something "
1925 "is wrong in the pipe configuration",
1926 __func__);
1927 ASSERT(0);
1928 return 0;
1929 }
1930 while (opp_head) {
1931 ASSERT(i < MAX_PIPES);
1932 opp_heads[i++] = opp_head;
1933 opp_head = opp_head->next_odm_pipe;
1934 }
1935 return i;
1936 }
1937
resource_get_dpp_pipes_for_opp_head(const struct pipe_ctx * opp_head,struct resource_context * res_ctx,struct pipe_ctx * dpp_pipes[MAX_PIPES])1938 int resource_get_dpp_pipes_for_opp_head(const struct pipe_ctx *opp_head,
1939 struct resource_context *res_ctx,
1940 struct pipe_ctx *dpp_pipes[MAX_PIPES])
1941 {
1942 struct pipe_ctx *pipe = &res_ctx->pipe_ctx[opp_head->pipe_idx];
1943 int i = 0;
1944
1945 if (!resource_is_pipe_type(opp_head, OPP_HEAD)) {
1946 ASSERT(0);
1947 return 0;
1948 }
1949 while (pipe && resource_is_pipe_type(pipe, DPP_PIPE)) {
1950 ASSERT(i < MAX_PIPES);
1951 dpp_pipes[i++] = pipe;
1952 pipe = pipe->bottom_pipe;
1953 }
1954 return i;
1955 }
1956
resource_get_dpp_pipes_for_plane(const struct dc_plane_state * plane,struct resource_context * res_ctx,struct pipe_ctx * dpp_pipes[MAX_PIPES])1957 int resource_get_dpp_pipes_for_plane(const struct dc_plane_state *plane,
1958 struct resource_context *res_ctx,
1959 struct pipe_ctx *dpp_pipes[MAX_PIPES])
1960 {
1961 int i = 0, j;
1962 struct pipe_ctx *pipe;
1963
1964 for (j = 0; j < MAX_PIPES; j++) {
1965 pipe = &res_ctx->pipe_ctx[j];
1966 if (pipe->plane_state == plane && pipe->prev_odm_pipe == NULL) {
1967 if (resource_is_pipe_type(pipe, OPP_HEAD) ||
1968 pipe->top_pipe->plane_state != plane)
1969 break;
1970 }
1971 }
1972
1973 if (j < MAX_PIPES) {
1974 if (pipe->next_odm_pipe)
1975 while (pipe) {
1976 dpp_pipes[i++] = pipe;
1977 pipe = pipe->next_odm_pipe;
1978 }
1979 else
1980 while (pipe && pipe->plane_state == plane) {
1981 dpp_pipes[i++] = pipe;
1982 pipe = pipe->bottom_pipe;
1983 }
1984 }
1985 return i;
1986 }
1987
resource_get_otg_master(const struct pipe_ctx * pipe_ctx)1988 struct pipe_ctx *resource_get_otg_master(const struct pipe_ctx *pipe_ctx)
1989 {
1990 struct pipe_ctx *otg_master = resource_get_opp_head(pipe_ctx);
1991
1992 while (otg_master->prev_odm_pipe)
1993 otg_master = otg_master->prev_odm_pipe;
1994 return otg_master;
1995 }
1996
resource_get_opp_head(const struct pipe_ctx * pipe_ctx)1997 struct pipe_ctx *resource_get_opp_head(const struct pipe_ctx *pipe_ctx)
1998 {
1999 struct pipe_ctx *opp_head = (struct pipe_ctx *) pipe_ctx;
2000
2001 ASSERT(!resource_is_pipe_type(opp_head, FREE_PIPE));
2002 while (opp_head->top_pipe)
2003 opp_head = opp_head->top_pipe;
2004 return opp_head;
2005 }
2006
resource_get_primary_dpp_pipe(const struct pipe_ctx * dpp_pipe)2007 struct pipe_ctx *resource_get_primary_dpp_pipe(const struct pipe_ctx *dpp_pipe)
2008 {
2009 struct pipe_ctx *pri_dpp_pipe = (struct pipe_ctx *) dpp_pipe;
2010
2011 ASSERT(resource_is_pipe_type(dpp_pipe, DPP_PIPE));
2012 while (pri_dpp_pipe->prev_odm_pipe)
2013 pri_dpp_pipe = pri_dpp_pipe->prev_odm_pipe;
2014 while (pri_dpp_pipe->top_pipe &&
2015 pri_dpp_pipe->top_pipe->plane_state == pri_dpp_pipe->plane_state)
2016 pri_dpp_pipe = pri_dpp_pipe->top_pipe;
2017 return pri_dpp_pipe;
2018 }
2019
2020
resource_get_mpc_slice_index(const struct pipe_ctx * pipe_ctx)2021 int resource_get_mpc_slice_index(const struct pipe_ctx *pipe_ctx)
2022 {
2023 struct pipe_ctx *split_pipe = pipe_ctx->top_pipe;
2024 int index = 0;
2025
2026 while (split_pipe && split_pipe->plane_state == pipe_ctx->plane_state) {
2027 index++;
2028 split_pipe = split_pipe->top_pipe;
2029 }
2030
2031 return index;
2032 }
2033
resource_get_mpc_slice_count(const struct pipe_ctx * pipe)2034 int resource_get_mpc_slice_count(const struct pipe_ctx *pipe)
2035 {
2036 int mpc_split_count = 1;
2037 const struct pipe_ctx *other_pipe = pipe->bottom_pipe;
2038
2039 while (other_pipe && other_pipe->plane_state == pipe->plane_state) {
2040 mpc_split_count++;
2041 other_pipe = other_pipe->bottom_pipe;
2042 }
2043 other_pipe = pipe->top_pipe;
2044 while (other_pipe && other_pipe->plane_state == pipe->plane_state) {
2045 mpc_split_count++;
2046 other_pipe = other_pipe->top_pipe;
2047 }
2048
2049 return mpc_split_count;
2050 }
2051
resource_get_odm_slice_count(const struct pipe_ctx * pipe)2052 int resource_get_odm_slice_count(const struct pipe_ctx *pipe)
2053 {
2054 int odm_split_count = 1;
2055
2056 pipe = resource_get_otg_master(pipe);
2057
2058 while (pipe->next_odm_pipe) {
2059 odm_split_count++;
2060 pipe = pipe->next_odm_pipe;
2061 }
2062 return odm_split_count;
2063 }
2064
resource_get_odm_slice_index(const struct pipe_ctx * pipe_ctx)2065 int resource_get_odm_slice_index(const struct pipe_ctx *pipe_ctx)
2066 {
2067 int index = 0;
2068
2069 pipe_ctx = resource_get_opp_head(pipe_ctx);
2070 if (!pipe_ctx)
2071 return 0;
2072
2073 while (pipe_ctx->prev_odm_pipe) {
2074 index++;
2075 pipe_ctx = pipe_ctx->prev_odm_pipe;
2076 }
2077
2078 return index;
2079 }
2080
resource_get_odm_slice_dst_width(struct pipe_ctx * otg_master,bool is_last_segment)2081 int resource_get_odm_slice_dst_width(struct pipe_ctx *otg_master,
2082 bool is_last_segment)
2083 {
2084 const struct dc_crtc_timing *timing;
2085 int count;
2086 int h_active;
2087 int width;
2088 bool two_pixel_alignment_required = false;
2089
2090 if (!otg_master || !otg_master->stream)
2091 return 0;
2092
2093 timing = &otg_master->stream->timing;
2094 count = resource_get_odm_slice_count(otg_master);
2095 h_active = timing->h_addressable +
2096 timing->h_border_left +
2097 timing->h_border_right;
2098 width = h_active / count;
2099
2100 if (otg_master->stream_res.tg)
2101 two_pixel_alignment_required =
2102 otg_master->stream_res.tg->funcs->is_two_pixels_per_container(timing) ||
2103 /*
2104 * 422 is sub-sampled horizontally. 1 set of chromas
2105 * (Cb/Cr) is shared for 2 lumas (i.e 2 Y values).
2106 * Therefore even if 422 is still 1 pixel per container,
2107 * ODM segment width still needs to be 2 pixel aligned.
2108 */
2109 timing->pixel_encoding == PIXEL_ENCODING_YCBCR422;
2110 if ((width % 2) && two_pixel_alignment_required)
2111 width++;
2112
2113 return is_last_segment ?
2114 h_active - width * (count - 1) :
2115 width;
2116 }
2117
resource_get_odm_slice_dst_rect(struct pipe_ctx * pipe_ctx)2118 struct rect resource_get_odm_slice_dst_rect(struct pipe_ctx *pipe_ctx)
2119 {
2120 const struct dc_stream_state *stream = pipe_ctx->stream;
2121 bool is_last_odm_slice = pipe_ctx->next_odm_pipe == NULL;
2122 struct pipe_ctx *otg_master = resource_get_otg_master(pipe_ctx);
2123 int odm_slice_idx = resource_get_odm_slice_index(pipe_ctx);
2124 int odm_segment_offset = resource_get_odm_slice_dst_width(otg_master, false);
2125 struct rect odm_slice_dst;
2126
2127 odm_slice_dst.x = odm_segment_offset * odm_slice_idx;
2128 odm_slice_dst.width = resource_get_odm_slice_dst_width(otg_master, is_last_odm_slice);
2129 odm_slice_dst.y = 0;
2130 odm_slice_dst.height = stream->timing.v_addressable +
2131 stream->timing.v_border_bottom +
2132 stream->timing.v_border_top;
2133
2134 return odm_slice_dst;
2135 }
2136
resource_get_odm_slice_src_rect(struct pipe_ctx * pipe_ctx)2137 struct rect resource_get_odm_slice_src_rect(struct pipe_ctx *pipe_ctx)
2138 {
2139 struct rect odm_slice_dst;
2140 struct rect odm_slice_src;
2141 struct pipe_ctx *opp_head = resource_get_opp_head(pipe_ctx);
2142 struct output_pixel_processor *opp = opp_head->stream_res.opp;
2143 uint32_t left_edge_extra_pixel_count;
2144
2145 odm_slice_dst = resource_get_odm_slice_dst_rect(opp_head);
2146 odm_slice_src = odm_slice_dst;
2147
2148 if (opp && opp->funcs->opp_get_left_edge_extra_pixel_count)
2149 left_edge_extra_pixel_count =
2150 opp->funcs->opp_get_left_edge_extra_pixel_count(
2151 opp, pipe_ctx->stream->timing.pixel_encoding,
2152 resource_is_pipe_type(opp_head, OTG_MASTER));
2153 else
2154 left_edge_extra_pixel_count = 0;
2155
2156 odm_slice_src.x -= left_edge_extra_pixel_count;
2157 odm_slice_src.width += left_edge_extra_pixel_count;
2158
2159 return odm_slice_src;
2160 }
2161
resource_is_pipe_topology_changed(const struct dc_state * state_a,const struct dc_state * state_b)2162 bool resource_is_pipe_topology_changed(const struct dc_state *state_a,
2163 const struct dc_state *state_b)
2164 {
2165 int i;
2166 const struct pipe_ctx *pipe_a, *pipe_b;
2167
2168 if (state_a->stream_count != state_b->stream_count)
2169 return true;
2170
2171 for (i = 0; i < MAX_PIPES; i++) {
2172 pipe_a = &state_a->res_ctx.pipe_ctx[i];
2173 pipe_b = &state_b->res_ctx.pipe_ctx[i];
2174
2175 if (pipe_a->stream && !pipe_b->stream)
2176 return true;
2177 else if (!pipe_a->stream && pipe_b->stream)
2178 return true;
2179
2180 if (pipe_a->plane_state && !pipe_b->plane_state)
2181 return true;
2182 else if (!pipe_a->plane_state && pipe_b->plane_state)
2183 return true;
2184
2185 if (pipe_a->bottom_pipe && pipe_b->bottom_pipe) {
2186 if (pipe_a->bottom_pipe->pipe_idx != pipe_b->bottom_pipe->pipe_idx)
2187 return true;
2188 if ((pipe_a->bottom_pipe->plane_state == pipe_a->plane_state) &&
2189 (pipe_b->bottom_pipe->plane_state != pipe_b->plane_state))
2190 return true;
2191 else if ((pipe_a->bottom_pipe->plane_state != pipe_a->plane_state) &&
2192 (pipe_b->bottom_pipe->plane_state == pipe_b->plane_state))
2193 return true;
2194 } else if (pipe_a->bottom_pipe || pipe_b->bottom_pipe) {
2195 return true;
2196 }
2197
2198 if (pipe_a->next_odm_pipe && pipe_b->next_odm_pipe) {
2199 if (pipe_a->next_odm_pipe->pipe_idx != pipe_b->next_odm_pipe->pipe_idx)
2200 return true;
2201 } else if (pipe_a->next_odm_pipe || pipe_b->next_odm_pipe) {
2202 return true;
2203 }
2204 }
2205 return false;
2206 }
2207
resource_is_odm_topology_changed(const struct pipe_ctx * otg_master_a,const struct pipe_ctx * otg_master_b)2208 bool resource_is_odm_topology_changed(const struct pipe_ctx *otg_master_a,
2209 const struct pipe_ctx *otg_master_b)
2210 {
2211 const struct pipe_ctx *opp_head_a = otg_master_a;
2212 const struct pipe_ctx *opp_head_b = otg_master_b;
2213
2214 if (!resource_is_pipe_type(otg_master_a, OTG_MASTER) ||
2215 !resource_is_pipe_type(otg_master_b, OTG_MASTER))
2216 return true;
2217
2218 while (opp_head_a && opp_head_b) {
2219 if (opp_head_a->stream_res.opp != opp_head_b->stream_res.opp)
2220 return true;
2221 if ((opp_head_a->next_odm_pipe && !opp_head_b->next_odm_pipe) ||
2222 (!opp_head_a->next_odm_pipe && opp_head_b->next_odm_pipe))
2223 return true;
2224 opp_head_a = opp_head_a->next_odm_pipe;
2225 opp_head_b = opp_head_b->next_odm_pipe;
2226 }
2227
2228 return false;
2229 }
2230
2231 /*
2232 * Sample log:
2233 * pipe topology update
2234 * ________________________
2235 * | plane0 slice0 stream0|
2236 * |DPP0----OPP0----OTG0----| <--- case 0 (OTG master pipe with plane)
2237 * | plane1 | | |
2238 * |DPP1----| | | <--- case 5 (DPP pipe not in last slice)
2239 * | plane0 slice1 | |
2240 * |DPP2----OPP2----| | <--- case 2 (OPP head pipe with plane)
2241 * | plane1 | |
2242 * |DPP3----| | <--- case 4 (DPP pipe in last slice)
2243 * | slice0 stream1|
2244 * |DPG4----OPP4----OTG4----| <--- case 1 (OTG master pipe without plane)
2245 * | slice1 | |
2246 * |DPG5----OPP5----| | <--- case 3 (OPP head pipe without plane)
2247 * |________________________|
2248 */
2249
resource_log_pipe(struct dc * dc,struct pipe_ctx * pipe,int stream_idx,int slice_idx,int plane_idx,int slice_count,bool is_primary)2250 static void resource_log_pipe(struct dc *dc, struct pipe_ctx *pipe,
2251 int stream_idx, int slice_idx, int plane_idx, int slice_count,
2252 bool is_primary)
2253 {
2254 DC_LOGGER_INIT(dc->ctx->logger);
2255
2256 if (slice_idx == 0 && plane_idx == 0 && is_primary) {
2257 /* case 0 (OTG master pipe with plane) */
2258 DC_LOG_DC(" | plane%d slice%d stream%d|",
2259 plane_idx, slice_idx, stream_idx);
2260 DC_LOG_DC(" |DPP%d----OPP%d----OTG%d----|",
2261 pipe->plane_res.dpp->inst,
2262 pipe->stream_res.opp->inst,
2263 pipe->stream_res.tg->inst);
2264 } else if (slice_idx == 0 && plane_idx == -1) {
2265 /* case 1 (OTG master pipe without plane) */
2266 DC_LOG_DC(" | slice%d stream%d|",
2267 slice_idx, stream_idx);
2268 DC_LOG_DC(" |DPG%d----OPP%d----OTG%d----|",
2269 pipe->stream_res.opp->inst,
2270 pipe->stream_res.opp->inst,
2271 pipe->stream_res.tg->inst);
2272 } else if (slice_idx != 0 && plane_idx == 0 && is_primary) {
2273 /* case 2 (OPP head pipe with plane) */
2274 DC_LOG_DC(" | plane%d slice%d | |",
2275 plane_idx, slice_idx);
2276 DC_LOG_DC(" |DPP%d----OPP%d----| |",
2277 pipe->plane_res.dpp->inst,
2278 pipe->stream_res.opp->inst);
2279 } else if (slice_idx != 0 && plane_idx == -1) {
2280 /* case 3 (OPP head pipe without plane) */
2281 DC_LOG_DC(" | slice%d | |", slice_idx);
2282 DC_LOG_DC(" |DPG%d----OPP%d----| |",
2283 pipe->plane_res.dpp->inst,
2284 pipe->stream_res.opp->inst);
2285 } else if (slice_idx == slice_count - 1) {
2286 /* case 4 (DPP pipe in last slice) */
2287 DC_LOG_DC(" | plane%d | |", plane_idx);
2288 DC_LOG_DC(" |DPP%d----| |",
2289 pipe->plane_res.dpp->inst);
2290 } else {
2291 /* case 5 (DPP pipe not in last slice) */
2292 DC_LOG_DC(" | plane%d | | |", plane_idx);
2293 DC_LOG_DC(" |DPP%d----| | |",
2294 pipe->plane_res.dpp->inst);
2295 }
2296 }
2297
resource_log_pipe_for_stream(struct dc * dc,struct dc_state * state,struct pipe_ctx * otg_master,int stream_idx)2298 static void resource_log_pipe_for_stream(struct dc *dc, struct dc_state *state,
2299 struct pipe_ctx *otg_master, int stream_idx)
2300 {
2301 struct pipe_ctx *opp_heads[MAX_PIPES];
2302 struct pipe_ctx *dpp_pipes[MAX_PIPES];
2303
2304 int slice_idx, dpp_idx, plane_idx, slice_count, dpp_count;
2305 bool is_primary;
2306 DC_LOGGER_INIT(dc->ctx->logger);
2307
2308 slice_count = resource_get_opp_heads_for_otg_master(otg_master,
2309 &state->res_ctx, opp_heads);
2310 for (slice_idx = 0; slice_idx < slice_count; slice_idx++) {
2311 plane_idx = -1;
2312 if (opp_heads[slice_idx]->plane_state) {
2313 dpp_count = resource_get_dpp_pipes_for_opp_head(
2314 opp_heads[slice_idx],
2315 &state->res_ctx,
2316 dpp_pipes);
2317 for (dpp_idx = 0; dpp_idx < dpp_count; dpp_idx++) {
2318 is_primary = !dpp_pipes[dpp_idx]->top_pipe ||
2319 dpp_pipes[dpp_idx]->top_pipe->plane_state != dpp_pipes[dpp_idx]->plane_state;
2320 if (is_primary)
2321 plane_idx++;
2322 resource_log_pipe(dc, dpp_pipes[dpp_idx],
2323 stream_idx, slice_idx,
2324 plane_idx, slice_count,
2325 is_primary);
2326 }
2327 } else {
2328 resource_log_pipe(dc, opp_heads[slice_idx],
2329 stream_idx, slice_idx, plane_idx,
2330 slice_count, true);
2331 }
2332
2333 }
2334 }
2335
resource_stream_to_stream_idx(struct dc_state * state,struct dc_stream_state * stream)2336 static int resource_stream_to_stream_idx(struct dc_state *state,
2337 struct dc_stream_state *stream)
2338 {
2339 int i, stream_idx = -1;
2340
2341 for (i = 0; i < state->stream_count; i++)
2342 if (state->streams[i] == stream) {
2343 stream_idx = i;
2344 break;
2345 }
2346
2347 /* never return negative array index */
2348 if (stream_idx == -1) {
2349 ASSERT(0);
2350 return 0;
2351 }
2352
2353 return stream_idx;
2354 }
2355
resource_log_pipe_topology_update(struct dc * dc,struct dc_state * state)2356 void resource_log_pipe_topology_update(struct dc *dc, struct dc_state *state)
2357 {
2358 struct pipe_ctx *otg_master;
2359 int stream_idx, phantom_stream_idx;
2360 DC_LOGGER_INIT(dc->ctx->logger);
2361
2362 DC_LOG_DC(" pipe topology update");
2363 DC_LOG_DC(" ________________________");
2364 for (stream_idx = 0; stream_idx < state->stream_count; stream_idx++) {
2365 if (state->streams[stream_idx]->is_phantom)
2366 continue;
2367
2368 otg_master = resource_get_otg_master_for_stream(
2369 &state->res_ctx, state->streams[stream_idx]);
2370
2371 if (!otg_master)
2372 continue;
2373
2374 resource_log_pipe_for_stream(dc, state, otg_master, stream_idx);
2375 }
2376 if (state->phantom_stream_count > 0) {
2377 DC_LOG_DC(" | (phantom pipes) |");
2378 for (stream_idx = 0; stream_idx < state->stream_count; stream_idx++) {
2379 if (state->stream_status[stream_idx].mall_stream_config.type != SUBVP_MAIN)
2380 continue;
2381
2382 phantom_stream_idx = resource_stream_to_stream_idx(state,
2383 state->stream_status[stream_idx].mall_stream_config.paired_stream);
2384 otg_master = resource_get_otg_master_for_stream(
2385 &state->res_ctx, state->streams[phantom_stream_idx]);
2386 if (!otg_master)
2387 continue;
2388
2389 resource_log_pipe_for_stream(dc, state, otg_master, stream_idx);
2390 }
2391 }
2392 DC_LOG_DC(" |________________________|\n");
2393 }
2394
get_tail_pipe(struct pipe_ctx * head_pipe)2395 static struct pipe_ctx *get_tail_pipe(
2396 struct pipe_ctx *head_pipe)
2397 {
2398 struct pipe_ctx *tail_pipe = head_pipe->bottom_pipe;
2399
2400 while (tail_pipe) {
2401 head_pipe = tail_pipe;
2402 tail_pipe = tail_pipe->bottom_pipe;
2403 }
2404
2405 return head_pipe;
2406 }
2407
get_last_opp_head(struct pipe_ctx * opp_head)2408 static struct pipe_ctx *get_last_opp_head(
2409 struct pipe_ctx *opp_head)
2410 {
2411 ASSERT(resource_is_pipe_type(opp_head, OPP_HEAD));
2412 while (opp_head->next_odm_pipe)
2413 opp_head = opp_head->next_odm_pipe;
2414 return opp_head;
2415 }
2416
get_last_dpp_pipe_in_mpcc_combine(struct pipe_ctx * dpp_pipe)2417 static struct pipe_ctx *get_last_dpp_pipe_in_mpcc_combine(
2418 struct pipe_ctx *dpp_pipe)
2419 {
2420 ASSERT(resource_is_pipe_type(dpp_pipe, DPP_PIPE));
2421 while (dpp_pipe->bottom_pipe &&
2422 dpp_pipe->plane_state == dpp_pipe->bottom_pipe->plane_state)
2423 dpp_pipe = dpp_pipe->bottom_pipe;
2424 return dpp_pipe;
2425 }
2426
update_pipe_params_after_odm_slice_count_change(struct pipe_ctx * otg_master,struct dc_state * context,const struct resource_pool * pool)2427 static bool update_pipe_params_after_odm_slice_count_change(
2428 struct pipe_ctx *otg_master,
2429 struct dc_state *context,
2430 const struct resource_pool *pool)
2431 {
2432 int i;
2433 struct pipe_ctx *pipe;
2434 bool result = true;
2435
2436 for (i = 0; i < pool->pipe_count && result; i++) {
2437 pipe = &context->res_ctx.pipe_ctx[i];
2438 if (pipe->stream == otg_master->stream && pipe->plane_state)
2439 result = resource_build_scaling_params(pipe);
2440 }
2441
2442 if (pool->funcs->build_pipe_pix_clk_params)
2443 pool->funcs->build_pipe_pix_clk_params(otg_master);
2444
2445 resource_build_test_pattern_params(&context->res_ctx, otg_master);
2446
2447 return result;
2448 }
2449
update_pipe_params_after_mpc_slice_count_change(const struct dc_plane_state * plane,struct dc_state * context,const struct resource_pool * pool)2450 static bool update_pipe_params_after_mpc_slice_count_change(
2451 const struct dc_plane_state *plane,
2452 struct dc_state *context,
2453 const struct resource_pool *pool)
2454 {
2455 int i;
2456 struct pipe_ctx *pipe;
2457 bool result = true;
2458
2459 for (i = 0; i < pool->pipe_count && result; i++) {
2460 pipe = &context->res_ctx.pipe_ctx[i];
2461 if (pipe->plane_state == plane)
2462 result = resource_build_scaling_params(pipe);
2463 }
2464 return result;
2465 }
2466
acquire_first_split_pipe(struct resource_context * res_ctx,const struct resource_pool * pool,struct dc_stream_state * stream)2467 static int acquire_first_split_pipe(
2468 struct resource_context *res_ctx,
2469 const struct resource_pool *pool,
2470 struct dc_stream_state *stream)
2471 {
2472 int i;
2473
2474 for (i = 0; i < pool->pipe_count; i++) {
2475 struct pipe_ctx *split_pipe = &res_ctx->pipe_ctx[i];
2476
2477 if (split_pipe->top_pipe &&
2478 split_pipe->top_pipe->plane_state == split_pipe->plane_state) {
2479 split_pipe->top_pipe->bottom_pipe = split_pipe->bottom_pipe;
2480 if (split_pipe->bottom_pipe)
2481 split_pipe->bottom_pipe->top_pipe = split_pipe->top_pipe;
2482
2483 if (split_pipe->top_pipe->plane_state)
2484 resource_build_scaling_params(split_pipe->top_pipe);
2485
2486 memset(split_pipe, 0, sizeof(*split_pipe));
2487 split_pipe->stream_res.tg = pool->timing_generators[i];
2488 split_pipe->plane_res.hubp = pool->hubps[i];
2489 split_pipe->plane_res.ipp = pool->ipps[i];
2490 split_pipe->plane_res.dpp = pool->dpps[i];
2491 split_pipe->stream_res.opp = pool->opps[i];
2492 split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst;
2493 split_pipe->pipe_idx = i;
2494
2495 split_pipe->stream = stream;
2496 return i;
2497 }
2498 }
2499 return FREE_PIPE_INDEX_NOT_FOUND;
2500 }
2501
update_stream_engine_usage(struct resource_context * res_ctx,const struct resource_pool * pool,struct stream_encoder * stream_enc,bool acquired)2502 static void update_stream_engine_usage(
2503 struct resource_context *res_ctx,
2504 const struct resource_pool *pool,
2505 struct stream_encoder *stream_enc,
2506 bool acquired)
2507 {
2508 int i;
2509
2510 for (i = 0; i < pool->stream_enc_count; i++) {
2511 if (pool->stream_enc[i] == stream_enc)
2512 res_ctx->is_stream_enc_acquired[i] = acquired;
2513 }
2514 }
2515
update_hpo_dp_stream_engine_usage(struct resource_context * res_ctx,const struct resource_pool * pool,struct hpo_dp_stream_encoder * hpo_dp_stream_enc,bool acquired)2516 static void update_hpo_dp_stream_engine_usage(
2517 struct resource_context *res_ctx,
2518 const struct resource_pool *pool,
2519 struct hpo_dp_stream_encoder *hpo_dp_stream_enc,
2520 bool acquired)
2521 {
2522 int i;
2523
2524 for (i = 0; i < pool->hpo_dp_stream_enc_count; i++) {
2525 if (pool->hpo_dp_stream_enc[i] == hpo_dp_stream_enc)
2526 res_ctx->is_hpo_dp_stream_enc_acquired[i] = acquired;
2527 }
2528 }
2529
find_acquired_hpo_dp_link_enc_for_link(const struct resource_context * res_ctx,const struct dc_link * link)2530 static inline int find_acquired_hpo_dp_link_enc_for_link(
2531 const struct resource_context *res_ctx,
2532 const struct dc_link *link)
2533 {
2534 int i;
2535
2536 for (i = 0; i < ARRAY_SIZE(res_ctx->hpo_dp_link_enc_to_link_idx); i++)
2537 if (res_ctx->hpo_dp_link_enc_ref_cnts[i] > 0 &&
2538 res_ctx->hpo_dp_link_enc_to_link_idx[i] == link->link_index)
2539 return i;
2540
2541 return -1;
2542 }
2543
find_free_hpo_dp_link_enc(const struct resource_context * res_ctx,const struct resource_pool * pool)2544 static inline int find_free_hpo_dp_link_enc(const struct resource_context *res_ctx,
2545 const struct resource_pool *pool)
2546 {
2547 int i;
2548
2549 for (i = 0; i < ARRAY_SIZE(res_ctx->hpo_dp_link_enc_ref_cnts); i++)
2550 if (res_ctx->hpo_dp_link_enc_ref_cnts[i] == 0)
2551 break;
2552
2553 return (i < ARRAY_SIZE(res_ctx->hpo_dp_link_enc_ref_cnts) &&
2554 i < pool->hpo_dp_link_enc_count) ? i : -1;
2555 }
2556
acquire_hpo_dp_link_enc(struct resource_context * res_ctx,unsigned int link_index,int enc_index)2557 static inline void acquire_hpo_dp_link_enc(
2558 struct resource_context *res_ctx,
2559 unsigned int link_index,
2560 int enc_index)
2561 {
2562 res_ctx->hpo_dp_link_enc_to_link_idx[enc_index] = link_index;
2563 res_ctx->hpo_dp_link_enc_ref_cnts[enc_index] = 1;
2564 }
2565
retain_hpo_dp_link_enc(struct resource_context * res_ctx,int enc_index)2566 static inline void retain_hpo_dp_link_enc(
2567 struct resource_context *res_ctx,
2568 int enc_index)
2569 {
2570 res_ctx->hpo_dp_link_enc_ref_cnts[enc_index]++;
2571 }
2572
release_hpo_dp_link_enc(struct resource_context * res_ctx,int enc_index)2573 static inline void release_hpo_dp_link_enc(
2574 struct resource_context *res_ctx,
2575 int enc_index)
2576 {
2577 ASSERT(res_ctx->hpo_dp_link_enc_ref_cnts[enc_index] > 0);
2578 res_ctx->hpo_dp_link_enc_ref_cnts[enc_index]--;
2579 }
2580
add_hpo_dp_link_enc_to_ctx(struct resource_context * res_ctx,const struct resource_pool * pool,struct pipe_ctx * pipe_ctx,struct dc_stream_state * stream)2581 static bool add_hpo_dp_link_enc_to_ctx(struct resource_context *res_ctx,
2582 const struct resource_pool *pool,
2583 struct pipe_ctx *pipe_ctx,
2584 struct dc_stream_state *stream)
2585 {
2586 int enc_index;
2587
2588 enc_index = find_acquired_hpo_dp_link_enc_for_link(res_ctx, stream->link);
2589
2590 if (enc_index >= 0) {
2591 retain_hpo_dp_link_enc(res_ctx, enc_index);
2592 } else {
2593 enc_index = find_free_hpo_dp_link_enc(res_ctx, pool);
2594 if (enc_index >= 0)
2595 acquire_hpo_dp_link_enc(res_ctx, stream->link->link_index, enc_index);
2596 }
2597
2598 if (enc_index >= 0)
2599 pipe_ctx->link_res.hpo_dp_link_enc = pool->hpo_dp_link_enc[enc_index];
2600
2601 return pipe_ctx->link_res.hpo_dp_link_enc != NULL;
2602 }
2603
remove_hpo_dp_link_enc_from_ctx(struct resource_context * res_ctx,struct pipe_ctx * pipe_ctx,struct dc_stream_state * stream)2604 static void remove_hpo_dp_link_enc_from_ctx(struct resource_context *res_ctx,
2605 struct pipe_ctx *pipe_ctx,
2606 struct dc_stream_state *stream)
2607 {
2608 int enc_index;
2609
2610 enc_index = find_acquired_hpo_dp_link_enc_for_link(res_ctx, stream->link);
2611
2612 if (enc_index >= 0) {
2613 release_hpo_dp_link_enc(res_ctx, enc_index);
2614 pipe_ctx->link_res.hpo_dp_link_enc = NULL;
2615 }
2616 }
2617
get_num_of_free_pipes(const struct resource_pool * pool,const struct dc_state * context)2618 static int get_num_of_free_pipes(const struct resource_pool *pool, const struct dc_state *context)
2619 {
2620 int i;
2621 int count = 0;
2622
2623 for (i = 0; i < pool->pipe_count; i++)
2624 if (resource_is_pipe_type(&context->res_ctx.pipe_ctx[i], FREE_PIPE))
2625 count++;
2626 return count;
2627 }
2628
resource_add_otg_master_for_stream_output(struct dc_state * new_ctx,const struct resource_pool * pool,struct dc_stream_state * stream)2629 enum dc_status resource_add_otg_master_for_stream_output(struct dc_state *new_ctx,
2630 const struct resource_pool *pool,
2631 struct dc_stream_state *stream)
2632 {
2633 struct dc *dc = stream->ctx->dc;
2634
2635 return dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream);
2636 }
2637
resource_remove_otg_master_for_stream_output(struct dc_state * context,const struct resource_pool * pool,struct dc_stream_state * stream)2638 void resource_remove_otg_master_for_stream_output(struct dc_state *context,
2639 const struct resource_pool *pool,
2640 struct dc_stream_state *stream)
2641 {
2642 struct pipe_ctx *otg_master = resource_get_otg_master_for_stream(
2643 &context->res_ctx, stream);
2644
2645 if (!otg_master)
2646 return;
2647
2648 ASSERT(resource_get_odm_slice_count(otg_master) == 1);
2649 ASSERT(otg_master->plane_state == NULL);
2650 ASSERT(otg_master->stream_res.stream_enc);
2651 update_stream_engine_usage(
2652 &context->res_ctx,
2653 pool,
2654 otg_master->stream_res.stream_enc,
2655 false);
2656
2657 if (stream->ctx->dc->link_srv->dp_is_128b_132b_signal(otg_master)) {
2658 update_hpo_dp_stream_engine_usage(
2659 &context->res_ctx, pool,
2660 otg_master->stream_res.hpo_dp_stream_enc,
2661 false);
2662 remove_hpo_dp_link_enc_from_ctx(
2663 &context->res_ctx, otg_master, stream);
2664 }
2665 if (otg_master->stream_res.audio)
2666 update_audio_usage(
2667 &context->res_ctx,
2668 pool,
2669 otg_master->stream_res.audio,
2670 false);
2671
2672 resource_unreference_clock_source(&context->res_ctx,
2673 pool,
2674 otg_master->clock_source);
2675
2676 if (pool->funcs->remove_stream_from_ctx)
2677 pool->funcs->remove_stream_from_ctx(
2678 stream->ctx->dc, context, stream);
2679 memset(otg_master, 0, sizeof(*otg_master));
2680 }
2681
2682 /* For each OPP head of an OTG master, add top plane at plane index 0.
2683 *
2684 * In the following example, the stream has 2 ODM slices without a top plane.
2685 * By adding a plane 0 to OPP heads, we are configuring our hardware to render
2686 * plane 0 by using each OPP head's DPP.
2687 *
2688 * Inter-pipe Relation (Before Adding Plane)
2689 * __________________________________________________
2690 * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
2691 * | | | slice 0 | |
2692 * | 0 | |blank ----ODM----------- |
2693 * | | | slice 1 | | |
2694 * | 1 | |blank ---- | |
2695 * |________|_______________|___________|_____________|
2696 *
2697 * Inter-pipe Relation (After Adding Plane)
2698 * __________________________________________________
2699 * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
2700 * | | plane 0 | slice 0 | |
2701 * | 0 | -------------------------ODM----------- |
2702 * | | plane 0 | slice 1 | | |
2703 * | 1 | ------------------------- | |
2704 * |________|_______________|___________|_____________|
2705 */
add_plane_to_opp_head_pipes(struct pipe_ctx * otg_master_pipe,struct dc_plane_state * plane_state,struct dc_state * context)2706 static bool add_plane_to_opp_head_pipes(struct pipe_ctx *otg_master_pipe,
2707 struct dc_plane_state *plane_state,
2708 struct dc_state *context)
2709 {
2710 struct pipe_ctx *opp_head_pipe = otg_master_pipe;
2711
2712 while (opp_head_pipe) {
2713 if (opp_head_pipe->plane_state) {
2714 ASSERT(0);
2715 return false;
2716 }
2717 opp_head_pipe->plane_state = plane_state;
2718 opp_head_pipe = opp_head_pipe->next_odm_pipe;
2719 }
2720
2721 return true;
2722 }
2723
2724 /* For each OPP head of an OTG master, acquire a secondary DPP pipe and add
2725 * the plane. So the plane is added to all ODM slices associated with the OTG
2726 * master pipe in the bottom layer.
2727 *
2728 * In the following example, the stream has 2 ODM slices and a top plane 0.
2729 * By acquiring secondary DPP pipes and adding a plane 1, we are configuring our
2730 * hardware to render the plane 1 by acquiring a new pipe for each ODM slice and
2731 * render plane 1 using new pipes' DPP in the Z axis below plane 0.
2732 *
2733 * Inter-pipe Relation (Before Adding Plane)
2734 * __________________________________________________
2735 * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
2736 * | | plane 0 | slice 0 | |
2737 * | 0 | -------------------------ODM----------- |
2738 * | | plane 0 | slice 1 | | |
2739 * | 1 | ------------------------- | |
2740 * |________|_______________|___________|_____________|
2741 *
2742 * Inter-pipe Relation (After Acquiring and Adding Plane)
2743 * __________________________________________________
2744 * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
2745 * | | plane 0 | slice 0 | |
2746 * | 0 | -------------MPC---------ODM----------- |
2747 * | | plane 1 | | | | |
2748 * | 2 | ------------- | | | |
2749 * | | plane 0 | slice 1 | | |
2750 * | 1 | -------------MPC--------- | |
2751 * | | plane 1 | | | |
2752 * | 3 | ------------- | | |
2753 * |________|_______________|___________|_____________|
2754 */
acquire_secondary_dpp_pipes_and_add_plane(struct pipe_ctx * otg_master_pipe,struct dc_plane_state * plane_state,struct dc_state * new_ctx,struct dc_state * cur_ctx,struct resource_pool * pool)2755 static bool acquire_secondary_dpp_pipes_and_add_plane(
2756 struct pipe_ctx *otg_master_pipe,
2757 struct dc_plane_state *plane_state,
2758 struct dc_state *new_ctx,
2759 struct dc_state *cur_ctx,
2760 struct resource_pool *pool)
2761 {
2762 struct pipe_ctx *sec_pipe, *tail_pipe;
2763 struct pipe_ctx *opp_heads[MAX_PIPES];
2764 int opp_head_count;
2765 int i;
2766
2767 if (!pool->funcs->acquire_free_pipe_as_secondary_dpp_pipe) {
2768 ASSERT(0);
2769 return false;
2770 }
2771
2772 opp_head_count = resource_get_opp_heads_for_otg_master(otg_master_pipe,
2773 &new_ctx->res_ctx, opp_heads);
2774 if (get_num_of_free_pipes(pool, new_ctx) < opp_head_count)
2775 /* not enough free pipes */
2776 return false;
2777
2778 for (i = 0; i < opp_head_count; i++) {
2779 sec_pipe = pool->funcs->acquire_free_pipe_as_secondary_dpp_pipe(
2780 cur_ctx,
2781 new_ctx,
2782 pool,
2783 opp_heads[i]);
2784 ASSERT(sec_pipe);
2785 sec_pipe->plane_state = plane_state;
2786
2787 /* establish pipe relationship */
2788 tail_pipe = get_tail_pipe(opp_heads[i]);
2789 tail_pipe->bottom_pipe = sec_pipe;
2790 sec_pipe->top_pipe = tail_pipe;
2791 sec_pipe->bottom_pipe = NULL;
2792 if (tail_pipe->prev_odm_pipe) {
2793 ASSERT(tail_pipe->prev_odm_pipe->bottom_pipe);
2794 sec_pipe->prev_odm_pipe = tail_pipe->prev_odm_pipe->bottom_pipe;
2795 tail_pipe->prev_odm_pipe->bottom_pipe->next_odm_pipe = sec_pipe;
2796 } else {
2797 sec_pipe->prev_odm_pipe = NULL;
2798 }
2799 }
2800 return true;
2801 }
2802
resource_append_dpp_pipes_for_plane_composition(struct dc_state * new_ctx,struct dc_state * cur_ctx,struct resource_pool * pool,struct pipe_ctx * otg_master_pipe,struct dc_plane_state * plane_state)2803 bool resource_append_dpp_pipes_for_plane_composition(
2804 struct dc_state *new_ctx,
2805 struct dc_state *cur_ctx,
2806 struct resource_pool *pool,
2807 struct pipe_ctx *otg_master_pipe,
2808 struct dc_plane_state *plane_state)
2809 {
2810 bool success;
2811
2812 if (otg_master_pipe->plane_state == NULL)
2813 success = add_plane_to_opp_head_pipes(otg_master_pipe,
2814 plane_state, new_ctx);
2815 else
2816 success = acquire_secondary_dpp_pipes_and_add_plane(
2817 otg_master_pipe, plane_state, new_ctx,
2818 cur_ctx, pool);
2819 if (success) {
2820 /* when appending a plane mpc slice count changes from 0 to 1 */
2821 success = update_pipe_params_after_mpc_slice_count_change(
2822 plane_state, new_ctx, pool);
2823 if (!success)
2824 resource_remove_dpp_pipes_for_plane_composition(new_ctx,
2825 pool, plane_state);
2826 }
2827
2828 return success;
2829 }
2830
resource_remove_dpp_pipes_for_plane_composition(struct dc_state * context,const struct resource_pool * pool,const struct dc_plane_state * plane_state)2831 void resource_remove_dpp_pipes_for_plane_composition(
2832 struct dc_state *context,
2833 const struct resource_pool *pool,
2834 const struct dc_plane_state *plane_state)
2835 {
2836 int i;
2837
2838 for (i = pool->pipe_count - 1; i >= 0; i--) {
2839 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2840
2841 if (pipe_ctx->plane_state == plane_state) {
2842 if (pipe_ctx->top_pipe)
2843 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
2844
2845 /* Second condition is to avoid setting NULL to top pipe
2846 * of tail pipe making it look like head pipe in subsequent
2847 * deletes
2848 */
2849 if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe)
2850 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
2851
2852 /*
2853 * For head pipe detach surfaces from pipe for tail
2854 * pipe just zero it out
2855 */
2856 if (!pipe_ctx->top_pipe)
2857 pipe_ctx->plane_state = NULL;
2858 else
2859 memset(pipe_ctx, 0, sizeof(*pipe_ctx));
2860 }
2861 }
2862 }
2863
2864 /*
2865 * Increase ODM slice count by 1 by acquiring pipes and adding a new ODM slice
2866 * at the last index.
2867 * return - true if a new ODM slice is added and required pipes are acquired.
2868 * false if new_ctx is no longer a valid state after new ODM slice is added.
2869 *
2870 * This is achieved by duplicating MPC blending tree from previous ODM slice.
2871 * In the following example, we have a single MPC tree and 1 ODM slice 0. We
2872 * want to add a new odm slice by duplicating the MPC blending tree and add
2873 * ODM slice 1.
2874 *
2875 * Inter-pipe Relation (Before Acquiring and Adding ODM Slice)
2876 * __________________________________________________
2877 * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
2878 * | | plane 0 | slice 0 | |
2879 * | 0 | -------------MPC---------ODM----------- |
2880 * | | plane 1 | | | |
2881 * | 1 | ------------- | | |
2882 * |________|_______________|___________|_____________|
2883 *
2884 * Inter-pipe Relation (After Acquiring and Adding ODM Slice)
2885 * __________________________________________________
2886 * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
2887 * | | plane 0 | slice 0 | |
2888 * | 0 | -------------MPC---------ODM----------- |
2889 * | | plane 1 | | | | |
2890 * | 1 | ------------- | | | |
2891 * | | plane 0 | slice 1 | | |
2892 * | 2 | -------------MPC--------- | |
2893 * | | plane 1 | | | |
2894 * | 3 | ------------- | | |
2895 * |________|_______________|___________|_____________|
2896 */
acquire_pipes_and_add_odm_slice(struct pipe_ctx * otg_master_pipe,struct dc_state * new_ctx,const struct dc_state * cur_ctx,const struct resource_pool * pool)2897 static bool acquire_pipes_and_add_odm_slice(
2898 struct pipe_ctx *otg_master_pipe,
2899 struct dc_state *new_ctx,
2900 const struct dc_state *cur_ctx,
2901 const struct resource_pool *pool)
2902 {
2903 struct pipe_ctx *last_opp_head = get_last_opp_head(otg_master_pipe);
2904 struct pipe_ctx *new_opp_head;
2905 struct pipe_ctx *last_top_dpp_pipe, *last_bottom_dpp_pipe,
2906 *new_top_dpp_pipe, *new_bottom_dpp_pipe;
2907
2908 if (!pool->funcs->acquire_free_pipe_as_secondary_opp_head) {
2909 ASSERT(0);
2910 return false;
2911 }
2912 new_opp_head = pool->funcs->acquire_free_pipe_as_secondary_opp_head(
2913 cur_ctx, new_ctx, pool,
2914 otg_master_pipe);
2915 if (!new_opp_head)
2916 return false;
2917
2918 last_opp_head->next_odm_pipe = new_opp_head;
2919 new_opp_head->prev_odm_pipe = last_opp_head;
2920 new_opp_head->next_odm_pipe = NULL;
2921 new_opp_head->plane_state = last_opp_head->plane_state;
2922 last_top_dpp_pipe = last_opp_head;
2923 new_top_dpp_pipe = new_opp_head;
2924
2925 while (last_top_dpp_pipe->bottom_pipe) {
2926 last_bottom_dpp_pipe = last_top_dpp_pipe->bottom_pipe;
2927 new_bottom_dpp_pipe = pool->funcs->acquire_free_pipe_as_secondary_dpp_pipe(
2928 cur_ctx, new_ctx, pool,
2929 new_opp_head);
2930 if (!new_bottom_dpp_pipe)
2931 return false;
2932
2933 new_bottom_dpp_pipe->plane_state = last_bottom_dpp_pipe->plane_state;
2934 new_top_dpp_pipe->bottom_pipe = new_bottom_dpp_pipe;
2935 new_bottom_dpp_pipe->top_pipe = new_top_dpp_pipe;
2936 last_bottom_dpp_pipe->next_odm_pipe = new_bottom_dpp_pipe;
2937 new_bottom_dpp_pipe->prev_odm_pipe = last_bottom_dpp_pipe;
2938 new_bottom_dpp_pipe->next_odm_pipe = NULL;
2939 last_top_dpp_pipe = last_bottom_dpp_pipe;
2940 }
2941
2942 return true;
2943 }
2944
2945 /*
2946 * Decrease ODM slice count by 1 by releasing pipes and removing the ODM slice
2947 * at the last index.
2948 * return - true if the last ODM slice is removed and related pipes are
2949 * released. false if there is no removable ODM slice.
2950 *
2951 * In the following example, we have 2 MPC trees and ODM slice 0 and slice 1.
2952 * We want to remove the last ODM i.e slice 1. We are releasing secondary DPP
2953 * pipe 3 and OPP head pipe 2.
2954 *
2955 * Inter-pipe Relation (Before Releasing and Removing ODM Slice)
2956 * __________________________________________________
2957 * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
2958 * | | plane 0 | slice 0 | |
2959 * | 0 | -------------MPC---------ODM----------- |
2960 * | | plane 1 | | | | |
2961 * | 1 | ------------- | | | |
2962 * | | plane 0 | slice 1 | | |
2963 * | 2 | -------------MPC--------- | |
2964 * | | plane 1 | | | |
2965 * | 3 | ------------- | | |
2966 * |________|_______________|___________|_____________|
2967 *
2968 * Inter-pipe Relation (After Releasing and Removing ODM Slice)
2969 * __________________________________________________
2970 * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
2971 * | | plane 0 | slice 0 | |
2972 * | 0 | -------------MPC---------ODM----------- |
2973 * | | plane 1 | | | |
2974 * | 1 | ------------- | | |
2975 * |________|_______________|___________|_____________|
2976 */
release_pipes_and_remove_odm_slice(struct pipe_ctx * otg_master_pipe,struct dc_state * context,const struct resource_pool * pool)2977 static bool release_pipes_and_remove_odm_slice(
2978 struct pipe_ctx *otg_master_pipe,
2979 struct dc_state *context,
2980 const struct resource_pool *pool)
2981 {
2982 struct pipe_ctx *last_opp_head = get_last_opp_head(otg_master_pipe);
2983 struct pipe_ctx *tail_pipe = get_tail_pipe(last_opp_head);
2984
2985 if (!pool->funcs->release_pipe) {
2986 ASSERT(0);
2987 return false;
2988 }
2989
2990 if (resource_is_pipe_type(last_opp_head, OTG_MASTER))
2991 return false;
2992
2993 while (tail_pipe->top_pipe) {
2994 tail_pipe->prev_odm_pipe->next_odm_pipe = NULL;
2995 tail_pipe = tail_pipe->top_pipe;
2996 pool->funcs->release_pipe(context, tail_pipe->bottom_pipe, pool);
2997 tail_pipe->bottom_pipe = NULL;
2998 }
2999 last_opp_head->prev_odm_pipe->next_odm_pipe = NULL;
3000 pool->funcs->release_pipe(context, last_opp_head, pool);
3001
3002 return true;
3003 }
3004
3005 /*
3006 * Increase MPC slice count by 1 by acquiring a new DPP pipe and add it as the
3007 * last MPC slice of the plane associated with dpp_pipe.
3008 *
3009 * return - true if a new MPC slice is added and required pipes are acquired.
3010 * false if new_ctx is no longer a valid state after new MPC slice is added.
3011 *
3012 * In the following example, we add a new MPC slice for plane 0 into the
3013 * new_ctx. To do so we pass pipe 0 as dpp_pipe. The function acquires a new DPP
3014 * pipe 2 for plane 0 as the bottom most pipe for plane 0.
3015 *
3016 * Inter-pipe Relation (Before Acquiring and Adding MPC Slice)
3017 * __________________________________________________
3018 * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
3019 * | | plane 0 | | |
3020 * | 0 | -------------MPC----------------------- |
3021 * | | plane 1 | | | |
3022 * | 1 | ------------- | | |
3023 * |________|_______________|___________|_____________|
3024 *
3025 * Inter-pipe Relation (After Acquiring and Adding MPC Slice)
3026 * __________________________________________________
3027 * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
3028 * | | plane 0 | | |
3029 * | 0 | -------------MPC----------------------- |
3030 * | | plane 0 | | | |
3031 * | 2 | ------------- | | |
3032 * | | plane 1 | | | |
3033 * | 1 | ------------- | | |
3034 * |________|_______________|___________|_____________|
3035 */
acquire_dpp_pipe_and_add_mpc_slice(struct pipe_ctx * dpp_pipe,struct dc_state * new_ctx,const struct dc_state * cur_ctx,const struct resource_pool * pool)3036 static bool acquire_dpp_pipe_and_add_mpc_slice(
3037 struct pipe_ctx *dpp_pipe,
3038 struct dc_state *new_ctx,
3039 const struct dc_state *cur_ctx,
3040 const struct resource_pool *pool)
3041 {
3042 struct pipe_ctx *last_dpp_pipe =
3043 get_last_dpp_pipe_in_mpcc_combine(dpp_pipe);
3044 struct pipe_ctx *opp_head = resource_get_opp_head(dpp_pipe);
3045 struct pipe_ctx *new_dpp_pipe;
3046
3047 if (!pool->funcs->acquire_free_pipe_as_secondary_dpp_pipe) {
3048 ASSERT(0);
3049 return false;
3050 }
3051 new_dpp_pipe = pool->funcs->acquire_free_pipe_as_secondary_dpp_pipe(
3052 cur_ctx, new_ctx, pool, opp_head);
3053 if (!new_dpp_pipe || resource_get_odm_slice_count(dpp_pipe) > 1)
3054 return false;
3055
3056 new_dpp_pipe->bottom_pipe = last_dpp_pipe->bottom_pipe;
3057 if (new_dpp_pipe->bottom_pipe)
3058 new_dpp_pipe->bottom_pipe->top_pipe = new_dpp_pipe;
3059 new_dpp_pipe->top_pipe = last_dpp_pipe;
3060 last_dpp_pipe->bottom_pipe = new_dpp_pipe;
3061 new_dpp_pipe->plane_state = last_dpp_pipe->plane_state;
3062
3063 return true;
3064 }
3065
3066 /*
3067 * Reduce MPC slice count by 1 by releasing the bottom DPP pipe in MPCC combine
3068 * with dpp_pipe and removing last MPC slice of the plane associated with
3069 * dpp_pipe.
3070 *
3071 * return - true if the last MPC slice of the plane associated with dpp_pipe is
3072 * removed and last DPP pipe in MPCC combine with dpp_pipe is released.
3073 * false if there is no removable MPC slice.
3074 *
3075 * In the following example, we remove an MPC slice for plane 0 from the
3076 * context. To do so we pass pipe 0 as dpp_pipe. The function releases pipe 1 as
3077 * it is the last pipe for plane 0.
3078 *
3079 * Inter-pipe Relation (Before Releasing and Removing MPC Slice)
3080 * __________________________________________________
3081 * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
3082 * | | plane 0 | | |
3083 * | 0 | -------------MPC----------------------- |
3084 * | | plane 0 | | | |
3085 * | 1 | ------------- | | |
3086 * | | plane 1 | | | |
3087 * | 2 | ------------- | | |
3088 * |________|_______________|___________|_____________|
3089 *
3090 * Inter-pipe Relation (After Releasing and Removing MPC Slice)
3091 * __________________________________________________
3092 * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
3093 * | | plane 0 | | |
3094 * | 0 | -------------MPC----------------------- |
3095 * | | plane 1 | | | |
3096 * | 2 | ------------- | | |
3097 * |________|_______________|___________|_____________|
3098 */
release_dpp_pipe_and_remove_mpc_slice(struct pipe_ctx * dpp_pipe,struct dc_state * context,const struct resource_pool * pool)3099 static bool release_dpp_pipe_and_remove_mpc_slice(
3100 struct pipe_ctx *dpp_pipe,
3101 struct dc_state *context,
3102 const struct resource_pool *pool)
3103 {
3104 struct pipe_ctx *last_dpp_pipe =
3105 get_last_dpp_pipe_in_mpcc_combine(dpp_pipe);
3106
3107 if (!pool->funcs->release_pipe) {
3108 ASSERT(0);
3109 return false;
3110 }
3111
3112 if (resource_is_pipe_type(last_dpp_pipe, OPP_HEAD) ||
3113 resource_get_odm_slice_count(dpp_pipe) > 1)
3114 return false;
3115
3116 last_dpp_pipe->top_pipe->bottom_pipe = last_dpp_pipe->bottom_pipe;
3117 if (last_dpp_pipe->bottom_pipe)
3118 last_dpp_pipe->bottom_pipe->top_pipe = last_dpp_pipe->top_pipe;
3119 pool->funcs->release_pipe(context, last_dpp_pipe, pool);
3120
3121 return true;
3122 }
3123
resource_update_pipes_for_stream_with_slice_count(struct dc_state * new_ctx,const struct dc_state * cur_ctx,const struct resource_pool * pool,const struct dc_stream_state * stream,int new_slice_count)3124 bool resource_update_pipes_for_stream_with_slice_count(
3125 struct dc_state *new_ctx,
3126 const struct dc_state *cur_ctx,
3127 const struct resource_pool *pool,
3128 const struct dc_stream_state *stream,
3129 int new_slice_count)
3130 {
3131 int i;
3132 struct pipe_ctx *otg_master = resource_get_otg_master_for_stream(
3133 &new_ctx->res_ctx, stream);
3134 int cur_slice_count;
3135 bool result = true;
3136
3137 if (!otg_master)
3138 return false;
3139
3140 cur_slice_count = resource_get_odm_slice_count(otg_master);
3141
3142 if (new_slice_count == cur_slice_count)
3143 return result;
3144
3145 if (new_slice_count > cur_slice_count)
3146 for (i = 0; i < new_slice_count - cur_slice_count && result; i++)
3147 result = acquire_pipes_and_add_odm_slice(
3148 otg_master, new_ctx, cur_ctx, pool);
3149 else
3150 for (i = 0; i < cur_slice_count - new_slice_count && result; i++)
3151 result = release_pipes_and_remove_odm_slice(
3152 otg_master, new_ctx, pool);
3153 if (result)
3154 result = update_pipe_params_after_odm_slice_count_change(
3155 otg_master, new_ctx, pool);
3156 return result;
3157 }
3158
resource_update_pipes_for_plane_with_slice_count(struct dc_state * new_ctx,const struct dc_state * cur_ctx,const struct resource_pool * pool,const struct dc_plane_state * plane,int new_slice_count)3159 bool resource_update_pipes_for_plane_with_slice_count(
3160 struct dc_state *new_ctx,
3161 const struct dc_state *cur_ctx,
3162 const struct resource_pool *pool,
3163 const struct dc_plane_state *plane,
3164 int new_slice_count)
3165 {
3166 int i;
3167 int dpp_pipe_count;
3168 int cur_slice_count;
3169 struct pipe_ctx *dpp_pipes[MAX_PIPES] = {0};
3170 bool result = true;
3171
3172 dpp_pipe_count = resource_get_dpp_pipes_for_plane(plane,
3173 &new_ctx->res_ctx, dpp_pipes);
3174 ASSERT(dpp_pipe_count > 0);
3175 cur_slice_count = resource_get_mpc_slice_count(dpp_pipes[0]);
3176
3177 if (new_slice_count == cur_slice_count)
3178 return result;
3179
3180 if (new_slice_count > cur_slice_count)
3181 for (i = 0; i < new_slice_count - cur_slice_count && result; i++)
3182 result = acquire_dpp_pipe_and_add_mpc_slice(
3183 dpp_pipes[0], new_ctx, cur_ctx, pool);
3184 else
3185 for (i = 0; i < cur_slice_count - new_slice_count && result; i++)
3186 result = release_dpp_pipe_and_remove_mpc_slice(
3187 dpp_pipes[0], new_ctx, pool);
3188 if (result)
3189 result = update_pipe_params_after_mpc_slice_count_change(
3190 dpp_pipes[0]->plane_state, new_ctx, pool);
3191 return result;
3192 }
3193
dc_is_timing_changed(struct dc_stream_state * cur_stream,struct dc_stream_state * new_stream)3194 bool dc_is_timing_changed(struct dc_stream_state *cur_stream,
3195 struct dc_stream_state *new_stream)
3196 {
3197 if (cur_stream == NULL)
3198 return true;
3199
3200 /* If output color space is changed, need to reprogram info frames */
3201 if (cur_stream->output_color_space != new_stream->output_color_space)
3202 return true;
3203
3204 return memcmp(
3205 &cur_stream->timing,
3206 &new_stream->timing,
3207 sizeof(struct dc_crtc_timing)) != 0;
3208 }
3209
are_stream_backends_same(struct dc_stream_state * stream_a,struct dc_stream_state * stream_b)3210 static bool are_stream_backends_same(
3211 struct dc_stream_state *stream_a, struct dc_stream_state *stream_b)
3212 {
3213 if (stream_a == stream_b)
3214 return true;
3215
3216 if (stream_a == NULL || stream_b == NULL)
3217 return false;
3218
3219 if (dc_is_timing_changed(stream_a, stream_b))
3220 return false;
3221
3222 if (stream_a->signal != stream_b->signal)
3223 return false;
3224
3225 if (stream_a->dpms_off != stream_b->dpms_off)
3226 return false;
3227
3228 return true;
3229 }
3230
3231 /*
3232 * dc_is_stream_unchanged() - Compare two stream states for equivalence.
3233 *
3234 * Checks if there a difference between the two states
3235 * that would require a mode change.
3236 *
3237 * Does not compare cursor position or attributes.
3238 */
dc_is_stream_unchanged(struct dc_stream_state * old_stream,struct dc_stream_state * stream)3239 bool dc_is_stream_unchanged(
3240 struct dc_stream_state *old_stream, struct dc_stream_state *stream)
3241 {
3242 if (!old_stream || !stream)
3243 return false;
3244
3245 if (!are_stream_backends_same(old_stream, stream))
3246 return false;
3247
3248 if (old_stream->ignore_msa_timing_param != stream->ignore_msa_timing_param)
3249 return false;
3250
3251 /*compare audio info*/
3252 if (memcmp(&old_stream->audio_info, &stream->audio_info, sizeof(stream->audio_info)) != 0)
3253 return false;
3254
3255 return true;
3256 }
3257
3258 /*
3259 * dc_is_stream_scaling_unchanged() - Compare scaling rectangles of two streams.
3260 */
dc_is_stream_scaling_unchanged(struct dc_stream_state * old_stream,struct dc_stream_state * stream)3261 bool dc_is_stream_scaling_unchanged(struct dc_stream_state *old_stream,
3262 struct dc_stream_state *stream)
3263 {
3264 if (old_stream == stream)
3265 return true;
3266
3267 if (old_stream == NULL || stream == NULL)
3268 return false;
3269
3270 if (memcmp(&old_stream->src,
3271 &stream->src,
3272 sizeof(struct rect)) != 0)
3273 return false;
3274
3275 if (memcmp(&old_stream->dst,
3276 &stream->dst,
3277 sizeof(struct rect)) != 0)
3278 return false;
3279
3280 return true;
3281 }
3282
3283 /* TODO: release audio object */
update_audio_usage(struct resource_context * res_ctx,const struct resource_pool * pool,struct audio * audio,bool acquired)3284 void update_audio_usage(
3285 struct resource_context *res_ctx,
3286 const struct resource_pool *pool,
3287 struct audio *audio,
3288 bool acquired)
3289 {
3290 int i;
3291 for (i = 0; i < pool->audio_count; i++) {
3292 if (pool->audios[i] == audio)
3293 res_ctx->is_audio_acquired[i] = acquired;
3294 }
3295 }
3296
find_first_free_match_hpo_dp_stream_enc_for_link(struct resource_context * res_ctx,const struct resource_pool * pool,struct dc_stream_state * stream)3297 static struct hpo_dp_stream_encoder *find_first_free_match_hpo_dp_stream_enc_for_link(
3298 struct resource_context *res_ctx,
3299 const struct resource_pool *pool,
3300 struct dc_stream_state *stream)
3301 {
3302 int i;
3303
3304 for (i = 0; i < pool->hpo_dp_stream_enc_count; i++) {
3305 if (!res_ctx->is_hpo_dp_stream_enc_acquired[i] &&
3306 pool->hpo_dp_stream_enc[i]) {
3307
3308 return pool->hpo_dp_stream_enc[i];
3309 }
3310 }
3311
3312 return NULL;
3313 }
3314
find_first_free_audio(struct resource_context * res_ctx,const struct resource_pool * pool,enum engine_id id,enum dce_version dc_version)3315 static struct audio *find_first_free_audio(
3316 struct resource_context *res_ctx,
3317 const struct resource_pool *pool,
3318 enum engine_id id,
3319 enum dce_version dc_version)
3320 {
3321 int i, available_audio_count;
3322
3323 if (id == ENGINE_ID_UNKNOWN)
3324 return NULL;
3325
3326 available_audio_count = pool->audio_count;
3327
3328 for (i = 0; i < available_audio_count; i++) {
3329 if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) {
3330 /*we have enough audio endpoint, find the matching inst*/
3331 if (id != i)
3332 continue;
3333 return pool->audios[i];
3334 }
3335 }
3336
3337 /* use engine id to find free audio */
3338 if ((id < available_audio_count) && (res_ctx->is_audio_acquired[id] == false)) {
3339 return pool->audios[id];
3340 }
3341 /*not found the matching one, first come first serve*/
3342 for (i = 0; i < available_audio_count; i++) {
3343 if (res_ctx->is_audio_acquired[i] == false) {
3344 return pool->audios[i];
3345 }
3346 }
3347 return NULL;
3348 }
3349
find_pll_sharable_stream(struct dc_stream_state * stream_needs_pll,struct dc_state * context)3350 static struct dc_stream_state *find_pll_sharable_stream(
3351 struct dc_stream_state *stream_needs_pll,
3352 struct dc_state *context)
3353 {
3354 int i;
3355
3356 for (i = 0; i < context->stream_count; i++) {
3357 struct dc_stream_state *stream_has_pll = context->streams[i];
3358
3359 /* We are looking for non dp, non virtual stream */
3360 if (resource_are_streams_timing_synchronizable(
3361 stream_needs_pll, stream_has_pll)
3362 && !dc_is_dp_signal(stream_has_pll->signal)
3363 && stream_has_pll->link->connector_signal
3364 != SIGNAL_TYPE_VIRTUAL)
3365 return stream_has_pll;
3366
3367 }
3368
3369 return NULL;
3370 }
3371
get_norm_pix_clk(const struct dc_crtc_timing * timing)3372 static int get_norm_pix_clk(const struct dc_crtc_timing *timing)
3373 {
3374 uint32_t pix_clk = timing->pix_clk_100hz;
3375 uint32_t normalized_pix_clk = pix_clk;
3376
3377 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
3378 pix_clk /= 2;
3379 if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
3380 switch (timing->display_color_depth) {
3381 case COLOR_DEPTH_666:
3382 case COLOR_DEPTH_888:
3383 normalized_pix_clk = pix_clk;
3384 break;
3385 case COLOR_DEPTH_101010:
3386 normalized_pix_clk = (pix_clk * 30) / 24;
3387 break;
3388 case COLOR_DEPTH_121212:
3389 normalized_pix_clk = (pix_clk * 36) / 24;
3390 break;
3391 case COLOR_DEPTH_161616:
3392 normalized_pix_clk = (pix_clk * 48) / 24;
3393 break;
3394 default:
3395 ASSERT(0);
3396 break;
3397 }
3398 }
3399 return normalized_pix_clk;
3400 }
3401
calculate_phy_pix_clks(struct dc_stream_state * stream)3402 static void calculate_phy_pix_clks(struct dc_stream_state *stream)
3403 {
3404 /* update actual pixel clock on all streams */
3405 if (dc_is_hdmi_signal(stream->signal))
3406 stream->phy_pix_clk = get_norm_pix_clk(
3407 &stream->timing) / 10;
3408 else
3409 stream->phy_pix_clk =
3410 stream->timing.pix_clk_100hz / 10;
3411
3412 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
3413 stream->phy_pix_clk *= 2;
3414 }
3415
acquire_resource_from_hw_enabled_state(struct resource_context * res_ctx,const struct resource_pool * pool,struct dc_stream_state * stream)3416 static int acquire_resource_from_hw_enabled_state(
3417 struct resource_context *res_ctx,
3418 const struct resource_pool *pool,
3419 struct dc_stream_state *stream)
3420 {
3421 struct dc_link *link = stream->link;
3422 unsigned int i, inst, tg_inst = 0;
3423 uint32_t numPipes = 1;
3424 uint32_t id_src[4] = {0};
3425
3426 /* Check for enabled DIG to identify enabled display */
3427 if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
3428 return -1;
3429
3430 inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
3431
3432 if (inst == ENGINE_ID_UNKNOWN)
3433 return -1;
3434
3435 for (i = 0; i < pool->stream_enc_count; i++) {
3436 if (pool->stream_enc[i]->id == inst) {
3437 tg_inst = pool->stream_enc[i]->funcs->dig_source_otg(
3438 pool->stream_enc[i]);
3439 break;
3440 }
3441 }
3442
3443 // tg_inst not found
3444 if (i == pool->stream_enc_count)
3445 return -1;
3446
3447 if (tg_inst >= pool->timing_generator_count)
3448 return -1;
3449
3450 if (!res_ctx->pipe_ctx[tg_inst].stream) {
3451 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst];
3452
3453 pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
3454 id_src[0] = tg_inst;
3455
3456 if (pipe_ctx->stream_res.tg->funcs->get_optc_source)
3457 pipe_ctx->stream_res.tg->funcs->get_optc_source(pipe_ctx->stream_res.tg,
3458 &numPipes, &id_src[0], &id_src[1]);
3459
3460 if (id_src[0] == 0xf && id_src[1] == 0xf) {
3461 id_src[0] = tg_inst;
3462 numPipes = 1;
3463 }
3464
3465 for (i = 0; i < numPipes; i++) {
3466 //Check if src id invalid
3467 if (id_src[i] == 0xf)
3468 return -1;
3469
3470 pipe_ctx = &res_ctx->pipe_ctx[id_src[i]];
3471
3472 pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
3473 pipe_ctx->plane_res.mi = pool->mis[id_src[i]];
3474 pipe_ctx->plane_res.hubp = pool->hubps[id_src[i]];
3475 pipe_ctx->plane_res.ipp = pool->ipps[id_src[i]];
3476 pipe_ctx->plane_res.xfm = pool->transforms[id_src[i]];
3477 pipe_ctx->plane_res.dpp = pool->dpps[id_src[i]];
3478 pipe_ctx->stream_res.opp = pool->opps[id_src[i]];
3479
3480 if (pool->dpps[id_src[i]]) {
3481 pipe_ctx->plane_res.mpcc_inst = pool->dpps[id_src[i]]->inst;
3482
3483 if (pool->mpc->funcs->read_mpcc_state) {
3484 struct mpcc_state s = {0};
3485
3486 pool->mpc->funcs->read_mpcc_state(pool->mpc, pipe_ctx->plane_res.mpcc_inst, &s);
3487
3488 if (s.dpp_id < MAX_MPCC)
3489 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].dpp_id =
3490 s.dpp_id;
3491
3492 if (s.bot_mpcc_id < MAX_MPCC)
3493 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].mpcc_bot =
3494 &pool->mpc->mpcc_array[s.bot_mpcc_id];
3495
3496 if (s.opp_id < MAX_OPP)
3497 pipe_ctx->stream_res.opp->mpc_tree_params.opp_id = s.opp_id;
3498 }
3499 }
3500 pipe_ctx->pipe_idx = id_src[i];
3501
3502 if (id_src[i] >= pool->timing_generator_count) {
3503 id_src[i] = pool->timing_generator_count - 1;
3504
3505 pipe_ctx->stream_res.tg = pool->timing_generators[id_src[i]];
3506 pipe_ctx->stream_res.opp = pool->opps[id_src[i]];
3507 }
3508
3509 pipe_ctx->stream = stream;
3510 }
3511
3512 if (numPipes == 2) {
3513 stream->apply_boot_odm_mode = dm_odm_combine_policy_2to1;
3514 res_ctx->pipe_ctx[id_src[0]].next_odm_pipe = &res_ctx->pipe_ctx[id_src[1]];
3515 res_ctx->pipe_ctx[id_src[0]].prev_odm_pipe = NULL;
3516 res_ctx->pipe_ctx[id_src[1]].next_odm_pipe = NULL;
3517 res_ctx->pipe_ctx[id_src[1]].prev_odm_pipe = &res_ctx->pipe_ctx[id_src[0]];
3518 } else
3519 stream->apply_boot_odm_mode = dm_odm_combine_mode_disabled;
3520
3521 return id_src[0];
3522 }
3523
3524 return -1;
3525 }
3526
mark_seamless_boot_stream(const struct dc * dc,struct dc_stream_state * stream)3527 static void mark_seamless_boot_stream(
3528 const struct dc *dc,
3529 struct dc_stream_state *stream)
3530 {
3531 struct dc_bios *dcb = dc->ctx->dc_bios;
3532
3533 if (dc->config.allow_seamless_boot_optimization &&
3534 !dcb->funcs->is_accelerated_mode(dcb)) {
3535 if (dc_validate_boot_timing(dc, stream->sink, &stream->timing))
3536 stream->apply_seamless_boot_optimization = true;
3537 }
3538 }
3539
3540 /*
3541 * Acquire a pipe as OTG master and assign to the stream in new dc context.
3542 * return - true if OTG master pipe is acquired and new dc context is updated.
3543 * false if it fails to acquire an OTG master pipe for this stream.
3544 *
3545 * In the example below, we acquired pipe 0 as OTG master pipe for the stream.
3546 * After the function its Inter-pipe Relation is represented by the diagram
3547 * below.
3548 *
3549 * Inter-pipe Relation
3550 * __________________________________________________
3551 * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
3552 * | | | | |
3553 * | 0 | |blank ------------------ |
3554 * |________|_______________|___________|_____________|
3555 */
acquire_otg_master_pipe_for_stream(const struct dc_state * cur_ctx,struct dc_state * new_ctx,const struct resource_pool * pool,struct dc_stream_state * stream)3556 static bool acquire_otg_master_pipe_for_stream(
3557 const struct dc_state *cur_ctx,
3558 struct dc_state *new_ctx,
3559 const struct resource_pool *pool,
3560 struct dc_stream_state *stream)
3561 {
3562 /* TODO: Move this function to DCN specific resource file and acquire
3563 * DSC resource here. The reason is that the function should have the
3564 * same level of responsibility as when we acquire secondary OPP head.
3565 * We acquire DSC when we acquire secondary OPP head, so we should
3566 * acquire DSC when we acquire OTG master.
3567 */
3568 int pipe_idx;
3569 struct pipe_ctx *pipe_ctx = NULL;
3570
3571 /*
3572 * Upper level code is responsible to optimize unnecessary addition and
3573 * removal for unchanged streams. So unchanged stream will keep the same
3574 * OTG master instance allocated. When current stream is removed and a
3575 * new stream is added, we want to reuse the OTG instance made available
3576 * by the removed stream first. If not found, we try to avoid of using
3577 * any free pipes already used in current context as this could tear
3578 * down exiting ODM/MPC/MPO configuration unnecessarily.
3579 */
3580
3581 /*
3582 * Try to acquire the same OTG master already in use. This is not
3583 * optimal because resetting an enabled OTG master pipe for a new stream
3584 * requires an extra frame of wait. However there are test automation
3585 * and eDP assumptions that rely on reusing the same OTG master pipe
3586 * during mode change. We have to keep this logic as is for now.
3587 */
3588 pipe_idx = recource_find_free_pipe_used_as_otg_master_in_cur_res_ctx(
3589 &cur_ctx->res_ctx, &new_ctx->res_ctx, pool);
3590 /*
3591 * Try to acquire a pipe not used in current resource context to avoid
3592 * pipe swapping.
3593 */
3594 if (pipe_idx == FREE_PIPE_INDEX_NOT_FOUND)
3595 pipe_idx = recource_find_free_pipe_not_used_in_cur_res_ctx(
3596 &cur_ctx->res_ctx, &new_ctx->res_ctx, pool);
3597 /*
3598 * If pipe swapping is unavoidable, try to acquire pipe used as
3599 * secondary DPP pipe in current state as we prioritize to support more
3600 * streams over supporting MPO planes.
3601 */
3602 if (pipe_idx == FREE_PIPE_INDEX_NOT_FOUND)
3603 pipe_idx = resource_find_free_pipe_used_as_cur_sec_dpp(
3604 &cur_ctx->res_ctx, &new_ctx->res_ctx, pool);
3605 if (pipe_idx == FREE_PIPE_INDEX_NOT_FOUND)
3606 pipe_idx = resource_find_any_free_pipe(&new_ctx->res_ctx, pool);
3607 if (pipe_idx != FREE_PIPE_INDEX_NOT_FOUND) {
3608 pipe_ctx = &new_ctx->res_ctx.pipe_ctx[pipe_idx];
3609 memset(pipe_ctx, 0, sizeof(*pipe_ctx));
3610 pipe_ctx->pipe_idx = pipe_idx;
3611 pipe_ctx->stream_res.tg = pool->timing_generators[pipe_idx];
3612 pipe_ctx->plane_res.mi = pool->mis[pipe_idx];
3613 pipe_ctx->plane_res.hubp = pool->hubps[pipe_idx];
3614 pipe_ctx->plane_res.ipp = pool->ipps[pipe_idx];
3615 pipe_ctx->plane_res.xfm = pool->transforms[pipe_idx];
3616 pipe_ctx->plane_res.dpp = pool->dpps[pipe_idx];
3617 pipe_ctx->stream_res.opp = pool->opps[pipe_idx];
3618 if (pool->dpps[pipe_idx])
3619 pipe_ctx->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;
3620
3621 if (pipe_idx >= pool->timing_generator_count && pool->timing_generator_count != 0) {
3622 int tg_inst = pool->timing_generator_count - 1;
3623
3624 pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
3625 pipe_ctx->stream_res.opp = pool->opps[tg_inst];
3626 }
3627
3628 pipe_ctx->stream = stream;
3629 } else {
3630 pipe_idx = acquire_first_split_pipe(&new_ctx->res_ctx, pool, stream);
3631 }
3632
3633 return pipe_idx != FREE_PIPE_INDEX_NOT_FOUND;
3634 }
3635
resource_map_pool_resources(const struct dc * dc,struct dc_state * context,struct dc_stream_state * stream)3636 enum dc_status resource_map_pool_resources(
3637 const struct dc *dc,
3638 struct dc_state *context,
3639 struct dc_stream_state *stream)
3640 {
3641 const struct resource_pool *pool = dc->res_pool;
3642 int i;
3643 struct dc_context *dc_ctx = dc->ctx;
3644 struct pipe_ctx *pipe_ctx = NULL;
3645 int pipe_idx = -1;
3646 bool acquired = false;
3647
3648 calculate_phy_pix_clks(stream);
3649
3650 mark_seamless_boot_stream(dc, stream);
3651
3652 if (stream->apply_seamless_boot_optimization) {
3653 pipe_idx = acquire_resource_from_hw_enabled_state(
3654 &context->res_ctx,
3655 pool,
3656 stream);
3657 if (pipe_idx < 0)
3658 /* hw resource was assigned to other stream */
3659 stream->apply_seamless_boot_optimization = false;
3660 else
3661 acquired = true;
3662 }
3663
3664 if (!acquired)
3665 /* acquire new resources */
3666 acquired = acquire_otg_master_pipe_for_stream(dc->current_state,
3667 context, pool, stream);
3668
3669 pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);
3670
3671 if (!pipe_ctx || pipe_ctx->stream_res.tg == NULL)
3672 return DC_NO_CONTROLLER_RESOURCE;
3673
3674 pipe_ctx->stream_res.stream_enc =
3675 dc->res_pool->funcs->find_first_free_match_stream_enc_for_link(
3676 &context->res_ctx, pool, stream);
3677
3678 if (!pipe_ctx->stream_res.stream_enc)
3679 return DC_NO_STREAM_ENC_RESOURCE;
3680
3681 update_stream_engine_usage(
3682 &context->res_ctx, pool,
3683 pipe_ctx->stream_res.stream_enc,
3684 true);
3685
3686 /* Allocate DP HPO Stream Encoder based on signal, hw capabilities
3687 * and link settings
3688 */
3689 if (dc_is_dp_signal(stream->signal) ||
3690 dc_is_virtual_signal(stream->signal)) {
3691 if (!dc->link_srv->dp_decide_link_settings(stream,
3692 &pipe_ctx->link_config.dp_link_settings))
3693 return DC_FAIL_DP_LINK_BANDWIDTH;
3694 if (dc->link_srv->dp_get_encoding_format(
3695 &pipe_ctx->link_config.dp_link_settings) == DP_128b_132b_ENCODING) {
3696 pipe_ctx->stream_res.hpo_dp_stream_enc =
3697 find_first_free_match_hpo_dp_stream_enc_for_link(
3698 &context->res_ctx, pool, stream);
3699
3700 if (!pipe_ctx->stream_res.hpo_dp_stream_enc)
3701 return DC_NO_STREAM_ENC_RESOURCE;
3702
3703 update_hpo_dp_stream_engine_usage(
3704 &context->res_ctx, pool,
3705 pipe_ctx->stream_res.hpo_dp_stream_enc,
3706 true);
3707 if (!add_hpo_dp_link_enc_to_ctx(&context->res_ctx, pool, pipe_ctx, stream))
3708 return DC_NO_LINK_ENC_RESOURCE;
3709 }
3710 }
3711
3712 /* TODO: Add check if ASIC support and EDID audio */
3713 if (!stream->converter_disable_audio &&
3714 dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
3715 stream->audio_info.mode_count && stream->audio_info.flags.all) {
3716 pipe_ctx->stream_res.audio = find_first_free_audio(
3717 &context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id, dc_ctx->dce_version);
3718
3719 /*
3720 * Audio assigned in order first come first get.
3721 * There are asics which has number of audio
3722 * resources less then number of pipes
3723 */
3724 if (pipe_ctx->stream_res.audio)
3725 update_audio_usage(&context->res_ctx, pool,
3726 pipe_ctx->stream_res.audio, true);
3727 }
3728
3729 /* Add ABM to the resource if on EDP */
3730 if (pipe_ctx->stream && dc_is_embedded_signal(pipe_ctx->stream->signal)) {
3731 if (pool->abm)
3732 pipe_ctx->stream_res.abm = pool->abm;
3733 else
3734 pipe_ctx->stream_res.abm = pool->multiple_abms[pipe_ctx->stream_res.tg->inst];
3735 }
3736
3737 for (i = 0; i < context->stream_count; i++)
3738 if (context->streams[i] == stream) {
3739 context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst;
3740 context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->stream_enc_inst;
3741 context->stream_status[i].audio_inst =
3742 pipe_ctx->stream_res.audio ? pipe_ctx->stream_res.audio->inst : -1;
3743
3744 return DC_OK;
3745 }
3746
3747 DC_ERROR("Stream %p not found in new ctx!\n", stream);
3748 return DC_ERROR_UNEXPECTED;
3749 }
3750
dc_resource_is_dsc_encoding_supported(const struct dc * dc)3751 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc)
3752 {
3753 if (dc->res_pool == NULL)
3754 return false;
3755
3756 return dc->res_pool->res_cap->num_dsc > 0;
3757 }
3758
planes_changed_for_existing_stream(struct dc_state * context,struct dc_stream_state * stream,const struct dc_validation_set set[],int set_count)3759 static bool planes_changed_for_existing_stream(struct dc_state *context,
3760 struct dc_stream_state *stream,
3761 const struct dc_validation_set set[],
3762 int set_count)
3763 {
3764 int i, j;
3765 struct dc_stream_status *stream_status = NULL;
3766
3767 for (i = 0; i < context->stream_count; i++) {
3768 if (context->streams[i] == stream) {
3769 stream_status = &context->stream_status[i];
3770 break;
3771 }
3772 }
3773
3774 if (!stream_status) {
3775 ASSERT(0);
3776 return false;
3777 }
3778
3779 for (i = 0; i < set_count; i++)
3780 if (set[i].stream == stream)
3781 break;
3782
3783 if (i == set_count)
3784 ASSERT(0);
3785
3786 if (set[i].plane_count != stream_status->plane_count)
3787 return true;
3788
3789 for (j = 0; j < set[i].plane_count; j++)
3790 if (set[i].plane_states[j] != stream_status->plane_states[j])
3791 return true;
3792
3793 return false;
3794 }
3795
add_all_planes_for_stream(const struct dc * dc,struct dc_stream_state * stream,const struct dc_validation_set set[],int set_count,struct dc_state * state)3796 static bool add_all_planes_for_stream(
3797 const struct dc *dc,
3798 struct dc_stream_state *stream,
3799 const struct dc_validation_set set[],
3800 int set_count,
3801 struct dc_state *state)
3802 {
3803 int i, j;
3804
3805 for (i = 0; i < set_count; i++)
3806 if (set[i].stream == stream)
3807 break;
3808
3809 if (i == set_count) {
3810 dm_error("Stream %p not found in set!\n", stream);
3811 return false;
3812 }
3813
3814 for (j = 0; j < set[i].plane_count; j++)
3815 if (!dc_state_add_plane(dc, stream, set[i].plane_states[j], state))
3816 return false;
3817
3818 return true;
3819 }
3820
3821 /**
3822 * dc_validate_with_context - Validate and update the potential new stream in the context object
3823 *
3824 * @dc: Used to get the current state status
3825 * @set: An array of dc_validation_set with all the current streams reference
3826 * @set_count: Total of streams
3827 * @context: New context
3828 * @fast_validate: Enable or disable fast validation
3829 *
3830 * This function updates the potential new stream in the context object. It
3831 * creates multiple lists for the add, remove, and unchanged streams. In
3832 * particular, if the unchanged streams have a plane that changed, it is
3833 * necessary to remove all planes from the unchanged streams. In summary, this
3834 * function is responsible for validating the new context.
3835 *
3836 * Return:
3837 * In case of success, return DC_OK (1), otherwise, return a DC error.
3838 */
dc_validate_with_context(struct dc * dc,const struct dc_validation_set set[],int set_count,struct dc_state * context,bool fast_validate)3839 enum dc_status dc_validate_with_context(struct dc *dc,
3840 const struct dc_validation_set set[],
3841 int set_count,
3842 struct dc_state *context,
3843 bool fast_validate)
3844 {
3845 struct dc_stream_state *unchanged_streams[MAX_PIPES] = { 0 };
3846 struct dc_stream_state *del_streams[MAX_PIPES] = { 0 };
3847 struct dc_stream_state *add_streams[MAX_PIPES] = { 0 };
3848 int old_stream_count = context->stream_count;
3849 enum dc_status res = DC_ERROR_UNEXPECTED;
3850 int unchanged_streams_count = 0;
3851 int del_streams_count = 0;
3852 int add_streams_count = 0;
3853 bool found = false;
3854 int i, j, k;
3855
3856 DC_LOGGER_INIT(dc->ctx->logger);
3857
3858 /* First build a list of streams to be remove from current context */
3859 for (i = 0; i < old_stream_count; i++) {
3860 struct dc_stream_state *stream = context->streams[i];
3861
3862 for (j = 0; j < set_count; j++) {
3863 if (stream == set[j].stream) {
3864 found = true;
3865 break;
3866 }
3867 }
3868
3869 if (!found)
3870 del_streams[del_streams_count++] = stream;
3871
3872 found = false;
3873 }
3874
3875 /* Second, build a list of new streams */
3876 for (i = 0; i < set_count; i++) {
3877 struct dc_stream_state *stream = set[i].stream;
3878
3879 for (j = 0; j < old_stream_count; j++) {
3880 if (stream == context->streams[j]) {
3881 found = true;
3882 break;
3883 }
3884 }
3885
3886 if (!found)
3887 add_streams[add_streams_count++] = stream;
3888
3889 found = false;
3890 }
3891
3892 /* Build a list of unchanged streams which is necessary for handling
3893 * planes change such as added, removed, and updated.
3894 */
3895 for (i = 0; i < set_count; i++) {
3896 /* Check if stream is part of the delete list */
3897 for (j = 0; j < del_streams_count; j++) {
3898 if (set[i].stream == del_streams[j]) {
3899 found = true;
3900 break;
3901 }
3902 }
3903
3904 if (!found) {
3905 /* Check if stream is part of the add list */
3906 for (j = 0; j < add_streams_count; j++) {
3907 if (set[i].stream == add_streams[j]) {
3908 found = true;
3909 break;
3910 }
3911 }
3912 }
3913
3914 if (!found)
3915 unchanged_streams[unchanged_streams_count++] = set[i].stream;
3916
3917 found = false;
3918 }
3919
3920 /* Remove all planes for unchanged streams if planes changed */
3921 for (i = 0; i < unchanged_streams_count; i++) {
3922 if (planes_changed_for_existing_stream(context,
3923 unchanged_streams[i],
3924 set,
3925 set_count)) {
3926
3927 if (!dc_state_rem_all_planes_for_stream(dc,
3928 unchanged_streams[i],
3929 context)) {
3930 res = DC_FAIL_DETACH_SURFACES;
3931 goto fail;
3932 }
3933 }
3934 }
3935
3936 /* Remove all planes for removed streams and then remove the streams */
3937 for (i = 0; i < del_streams_count; i++) {
3938 /* Need to cpy the dwb data from the old stream in order to efc to work */
3939 if (del_streams[i]->num_wb_info > 0) {
3940 for (j = 0; j < add_streams_count; j++) {
3941 if (del_streams[i]->sink == add_streams[j]->sink) {
3942 add_streams[j]->num_wb_info = del_streams[i]->num_wb_info;
3943 for (k = 0; k < del_streams[i]->num_wb_info; k++)
3944 add_streams[j]->writeback_info[k] = del_streams[i]->writeback_info[k];
3945 }
3946 }
3947 }
3948
3949 if (dc_state_get_stream_subvp_type(context, del_streams[i]) == SUBVP_PHANTOM) {
3950 /* remove phantoms specifically */
3951 if (!dc_state_rem_all_phantom_planes_for_stream(dc, del_streams[i], context, true)) {
3952 res = DC_FAIL_DETACH_SURFACES;
3953 goto fail;
3954 }
3955
3956 res = dc_state_remove_phantom_stream(dc, context, del_streams[i]);
3957 dc_state_release_phantom_stream(dc, context, del_streams[i]);
3958 } else {
3959 if (!dc_state_rem_all_planes_for_stream(dc, del_streams[i], context)) {
3960 res = DC_FAIL_DETACH_SURFACES;
3961 goto fail;
3962 }
3963
3964 res = dc_state_remove_stream(dc, context, del_streams[i]);
3965 }
3966
3967 if (res != DC_OK)
3968 goto fail;
3969 }
3970
3971 /* Swap seamless boot stream to pipe 0 (if needed) to ensure pipe_ctx
3972 * matches. This may change in the future if seamless_boot_stream can be
3973 * multiple.
3974 */
3975 for (i = 0; i < add_streams_count; i++) {
3976 mark_seamless_boot_stream(dc, add_streams[i]);
3977 if (add_streams[i]->apply_seamless_boot_optimization && i != 0) {
3978 struct dc_stream_state *temp = add_streams[0];
3979
3980 add_streams[0] = add_streams[i];
3981 add_streams[i] = temp;
3982 break;
3983 }
3984 }
3985
3986 /* Add new streams and then add all planes for the new stream */
3987 for (i = 0; i < add_streams_count; i++) {
3988 calculate_phy_pix_clks(add_streams[i]);
3989 res = dc_state_add_stream(dc, context, add_streams[i]);
3990 if (res != DC_OK)
3991 goto fail;
3992
3993 if (!add_all_planes_for_stream(dc, add_streams[i], set, set_count, context)) {
3994 res = DC_FAIL_ATTACH_SURFACES;
3995 goto fail;
3996 }
3997 }
3998
3999 /* Add all planes for unchanged streams if planes changed */
4000 for (i = 0; i < unchanged_streams_count; i++) {
4001 if (planes_changed_for_existing_stream(context,
4002 unchanged_streams[i],
4003 set,
4004 set_count)) {
4005 if (!add_all_planes_for_stream(dc, unchanged_streams[i], set, set_count, context)) {
4006 res = DC_FAIL_ATTACH_SURFACES;
4007 goto fail;
4008 }
4009 }
4010 }
4011
4012 res = dc_validate_global_state(dc, context, fast_validate);
4013
4014 /* calculate pixel rate divider after deciding pxiel clock & odm combine */
4015 if ((dc->hwss.calculate_pix_rate_divider) && (res == DC_OK)) {
4016 for (i = 0; i < add_streams_count; i++)
4017 dc->hwss.calculate_pix_rate_divider(dc, context, add_streams[i]);
4018 }
4019
4020 fail:
4021 if (res != DC_OK)
4022 DC_LOG_WARNING("%s:resource validation failed, dc_status:%d\n",
4023 __func__,
4024 res);
4025
4026 return res;
4027 }
4028
4029 /**
4030 * dc_validate_global_state() - Determine if hardware can support a given state
4031 *
4032 * @dc: dc struct for this driver
4033 * @new_ctx: state to be validated
4034 * @fast_validate: set to true if only yes/no to support matters
4035 *
4036 * Checks hardware resource availability and bandwidth requirement.
4037 *
4038 * Return:
4039 * DC_OK if the result can be programmed. Otherwise, an error code.
4040 */
dc_validate_global_state(struct dc * dc,struct dc_state * new_ctx,bool fast_validate)4041 enum dc_status dc_validate_global_state(
4042 struct dc *dc,
4043 struct dc_state *new_ctx,
4044 bool fast_validate)
4045 {
4046 enum dc_status result = DC_ERROR_UNEXPECTED;
4047 int i, j;
4048
4049 if (!new_ctx)
4050 return DC_ERROR_UNEXPECTED;
4051
4052 if (dc->res_pool->funcs->validate_global) {
4053 result = dc->res_pool->funcs->validate_global(dc, new_ctx);
4054 if (result != DC_OK)
4055 return result;
4056 }
4057
4058 for (i = 0; i < new_ctx->stream_count; i++) {
4059 struct dc_stream_state *stream = new_ctx->streams[i];
4060
4061 for (j = 0; j < dc->res_pool->pipe_count; j++) {
4062 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j];
4063
4064 if (pipe_ctx->stream != stream)
4065 continue;
4066
4067 if (dc->res_pool->funcs->patch_unknown_plane_state &&
4068 pipe_ctx->plane_state &&
4069 pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) {
4070 result = dc->res_pool->funcs->patch_unknown_plane_state(pipe_ctx->plane_state);
4071 if (result != DC_OK)
4072 return result;
4073 }
4074
4075 /* Switch to dp clock source only if there is
4076 * no non dp stream that shares the same timing
4077 * with the dp stream.
4078 */
4079 if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
4080 !find_pll_sharable_stream(stream, new_ctx)) {
4081
4082 resource_unreference_clock_source(
4083 &new_ctx->res_ctx,
4084 dc->res_pool,
4085 pipe_ctx->clock_source);
4086
4087 pipe_ctx->clock_source = dc->res_pool->dp_clock_source;
4088 resource_reference_clock_source(
4089 &new_ctx->res_ctx,
4090 dc->res_pool,
4091 pipe_ctx->clock_source);
4092 }
4093 }
4094 }
4095
4096 result = resource_build_scaling_params_for_context(dc, new_ctx);
4097
4098 if (result == DC_OK)
4099 if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx, fast_validate))
4100 result = DC_FAIL_BANDWIDTH_VALIDATE;
4101
4102 /*
4103 * Only update link encoder to stream assignment after bandwidth validation passed.
4104 * TODO: Split out assignment and validation.
4105 */
4106 if (result == DC_OK && dc->res_pool->funcs->link_encs_assign && fast_validate == false)
4107 dc->res_pool->funcs->link_encs_assign(
4108 dc, new_ctx, new_ctx->streams, new_ctx->stream_count);
4109
4110 return result;
4111 }
4112
patch_gamut_packet_checksum(struct dc_info_packet * gamut_packet)4113 static void patch_gamut_packet_checksum(
4114 struct dc_info_packet *gamut_packet)
4115 {
4116 /* For gamut we recalc checksum */
4117 if (gamut_packet->valid) {
4118 uint8_t chk_sum = 0;
4119 uint8_t *ptr;
4120 uint8_t i;
4121
4122 /*start of the Gamut data. */
4123 ptr = &gamut_packet->sb[3];
4124
4125 for (i = 0; i <= gamut_packet->sb[1]; i++)
4126 chk_sum += ptr[i];
4127
4128 gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum);
4129 }
4130 }
4131
set_avi_info_frame(struct dc_info_packet * info_packet,struct pipe_ctx * pipe_ctx)4132 static void set_avi_info_frame(
4133 struct dc_info_packet *info_packet,
4134 struct pipe_ctx *pipe_ctx)
4135 {
4136 struct dc_stream_state *stream = pipe_ctx->stream;
4137 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
4138 uint32_t pixel_encoding = 0;
4139 enum scanning_type scan_type = SCANNING_TYPE_NODATA;
4140 enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA;
4141 uint8_t *check_sum = NULL;
4142 uint8_t byte_index = 0;
4143 union hdmi_info_packet hdmi_info;
4144 unsigned int vic = pipe_ctx->stream->timing.vic;
4145 unsigned int rid = pipe_ctx->stream->timing.rid;
4146 unsigned int fr_ind = pipe_ctx->stream->timing.fr_index;
4147 enum dc_timing_3d_format format;
4148
4149 memset(&hdmi_info, 0, sizeof(union hdmi_info_packet));
4150
4151 color_space = pipe_ctx->stream->output_color_space;
4152 if (color_space == COLOR_SPACE_UNKNOWN)
4153 color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ?
4154 COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709;
4155
4156 /* Initialize header */
4157 hdmi_info.bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI;
4158 /* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall
4159 * not be used in HDMI 2.0 (Section 10.1) */
4160 hdmi_info.bits.header.version = 2;
4161 hdmi_info.bits.header.length = HDMI_AVI_INFOFRAME_SIZE;
4162
4163 /*
4164 * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built
4165 * according to HDMI 2.0 spec (Section 10.1)
4166 */
4167
4168 switch (stream->timing.pixel_encoding) {
4169 case PIXEL_ENCODING_YCBCR422:
4170 pixel_encoding = 1;
4171 break;
4172
4173 case PIXEL_ENCODING_YCBCR444:
4174 pixel_encoding = 2;
4175 break;
4176 case PIXEL_ENCODING_YCBCR420:
4177 pixel_encoding = 3;
4178 break;
4179
4180 case PIXEL_ENCODING_RGB:
4181 default:
4182 pixel_encoding = 0;
4183 }
4184
4185 /* Y0_Y1_Y2 : The pixel encoding */
4186 /* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
4187 hdmi_info.bits.Y0_Y1_Y2 = pixel_encoding;
4188
4189 /* A0 = 1 Active Format Information valid */
4190 hdmi_info.bits.A0 = ACTIVE_FORMAT_VALID;
4191
4192 /* B0, B1 = 3; Bar info data is valid */
4193 hdmi_info.bits.B0_B1 = BAR_INFO_BOTH_VALID;
4194
4195 hdmi_info.bits.SC0_SC1 = PICTURE_SCALING_UNIFORM;
4196
4197 /* S0, S1 : Underscan / Overscan */
4198 /* TODO: un-hardcode scan type */
4199 scan_type = SCANNING_TYPE_UNDERSCAN;
4200 hdmi_info.bits.S0_S1 = scan_type;
4201
4202 /* C0, C1 : Colorimetry */
4203 switch (color_space) {
4204 case COLOR_SPACE_YCBCR709:
4205 case COLOR_SPACE_YCBCR709_LIMITED:
4206 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709;
4207 break;
4208 case COLOR_SPACE_YCBCR601:
4209 case COLOR_SPACE_YCBCR601_LIMITED:
4210 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU601;
4211 break;
4212 case COLOR_SPACE_2020_RGB_FULLRANGE:
4213 case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
4214 case COLOR_SPACE_2020_YCBCR:
4215 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;
4216 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
4217 break;
4218 case COLOR_SPACE_ADOBERGB:
4219 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB;
4220 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
4221 break;
4222 case COLOR_SPACE_SRGB:
4223 default:
4224 hdmi_info.bits.C0_C1 = COLORIMETRY_NO_DATA;
4225 break;
4226 }
4227
4228 if (pixel_encoding && color_space == COLOR_SPACE_2020_YCBCR &&
4229 stream->out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22) {
4230 hdmi_info.bits.EC0_EC2 = 0;
4231 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709;
4232 }
4233
4234 /* TODO: un-hardcode aspect ratio */
4235 aspect = stream->timing.aspect_ratio;
4236
4237 switch (aspect) {
4238 case ASPECT_RATIO_4_3:
4239 case ASPECT_RATIO_16_9:
4240 hdmi_info.bits.M0_M1 = aspect;
4241 break;
4242
4243 case ASPECT_RATIO_NO_DATA:
4244 case ASPECT_RATIO_64_27:
4245 case ASPECT_RATIO_256_135:
4246 default:
4247 hdmi_info.bits.M0_M1 = 0;
4248 }
4249
4250 /* Active Format Aspect ratio - same as Picture Aspect Ratio. */
4251 hdmi_info.bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
4252
4253 switch (stream->content_type) {
4254 case DISPLAY_CONTENT_TYPE_NO_DATA:
4255 hdmi_info.bits.CN0_CN1 = 0;
4256 hdmi_info.bits.ITC = 1;
4257 break;
4258 case DISPLAY_CONTENT_TYPE_GRAPHICS:
4259 hdmi_info.bits.CN0_CN1 = 0;
4260 hdmi_info.bits.ITC = 1;
4261 break;
4262 case DISPLAY_CONTENT_TYPE_PHOTO:
4263 hdmi_info.bits.CN0_CN1 = 1;
4264 hdmi_info.bits.ITC = 1;
4265 break;
4266 case DISPLAY_CONTENT_TYPE_CINEMA:
4267 hdmi_info.bits.CN0_CN1 = 2;
4268 hdmi_info.bits.ITC = 1;
4269 break;
4270 case DISPLAY_CONTENT_TYPE_GAME:
4271 hdmi_info.bits.CN0_CN1 = 3;
4272 hdmi_info.bits.ITC = 1;
4273 break;
4274 }
4275
4276 if (stream->qs_bit == 1) {
4277 if (color_space == COLOR_SPACE_SRGB ||
4278 color_space == COLOR_SPACE_2020_RGB_FULLRANGE)
4279 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE;
4280 else if (color_space == COLOR_SPACE_SRGB_LIMITED ||
4281 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE)
4282 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_LIMITED_RANGE;
4283 else
4284 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
4285 } else
4286 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
4287
4288 /* TODO : We should handle YCC quantization */
4289 /* but we do not have matrix calculation */
4290 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
4291
4292 ///VIC
4293 if (pipe_ctx->stream->timing.hdmi_vic != 0)
4294 vic = 0;
4295 format = stream->timing.timing_3d_format;
4296 /*todo, add 3DStereo support*/
4297 if (format != TIMING_3D_FORMAT_NONE) {
4298 // Based on HDMI specs hdmi vic needs to be converted to cea vic when 3D is enabled
4299 switch (pipe_ctx->stream->timing.hdmi_vic) {
4300 case 1:
4301 vic = 95;
4302 break;
4303 case 2:
4304 vic = 94;
4305 break;
4306 case 3:
4307 vic = 93;
4308 break;
4309 case 4:
4310 vic = 98;
4311 break;
4312 default:
4313 break;
4314 }
4315 }
4316 /* If VIC >= 128, the Source shall use AVI InfoFrame Version 3*/
4317 hdmi_info.bits.VIC0_VIC7 = vic;
4318 if (vic >= 128)
4319 hdmi_info.bits.header.version = 3;
4320 /* If (C1, C0)=(1, 1) and (EC2, EC1, EC0)=(1, 1, 1),
4321 * the Source shall use 20 AVI InfoFrame Version 4
4322 */
4323 if (hdmi_info.bits.C0_C1 == COLORIMETRY_EXTENDED &&
4324 hdmi_info.bits.EC0_EC2 == COLORIMETRYEX_RESERVED) {
4325 hdmi_info.bits.header.version = 4;
4326 hdmi_info.bits.header.length = 14;
4327 }
4328
4329 if (rid != 0 && fr_ind != 0) {
4330 hdmi_info.bits.header.version = 4;
4331 hdmi_info.bits.header.length = 15;
4332
4333 hdmi_info.bits.FR0_FR3 = fr_ind & 0xF;
4334 hdmi_info.bits.FR4 = (fr_ind >> 4) & 0x1;
4335 hdmi_info.bits.RID0_RID5 = rid;
4336 }
4337
4338 /* pixel repetition
4339 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
4340 * repetition start from 1 */
4341 hdmi_info.bits.PR0_PR3 = 0;
4342
4343 /* Bar Info
4344 * barTop: Line Number of End of Top Bar.
4345 * barBottom: Line Number of Start of Bottom Bar.
4346 * barLeft: Pixel Number of End of Left Bar.
4347 * barRight: Pixel Number of Start of Right Bar. */
4348 hdmi_info.bits.bar_top = stream->timing.v_border_top;
4349 hdmi_info.bits.bar_bottom = (stream->timing.v_total
4350 - stream->timing.v_border_bottom + 1);
4351 hdmi_info.bits.bar_left = stream->timing.h_border_left;
4352 hdmi_info.bits.bar_right = (stream->timing.h_total
4353 - stream->timing.h_border_right + 1);
4354
4355 /* Additional Colorimetry Extension
4356 * Used in conduction with C0-C1 and EC0-EC2
4357 * 0 = DCI-P3 RGB (D65)
4358 * 1 = DCI-P3 RGB (theater)
4359 */
4360 hdmi_info.bits.ACE0_ACE3 = 0;
4361
4362 /* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */
4363 check_sum = &hdmi_info.packet_raw_data.sb[0];
4364
4365 *check_sum = HDMI_INFOFRAME_TYPE_AVI + hdmi_info.bits.header.length + hdmi_info.bits.header.version;
4366
4367 for (byte_index = 1; byte_index <= hdmi_info.bits.header.length; byte_index++)
4368 *check_sum += hdmi_info.packet_raw_data.sb[byte_index];
4369
4370 /* one byte complement */
4371 *check_sum = (uint8_t) (0x100 - *check_sum);
4372
4373 /* Store in hw_path_mode */
4374 info_packet->hb0 = hdmi_info.packet_raw_data.hb0;
4375 info_packet->hb1 = hdmi_info.packet_raw_data.hb1;
4376 info_packet->hb2 = hdmi_info.packet_raw_data.hb2;
4377
4378 for (byte_index = 0; byte_index < sizeof(hdmi_info.packet_raw_data.sb); byte_index++)
4379 info_packet->sb[byte_index] = hdmi_info.packet_raw_data.sb[byte_index];
4380
4381 info_packet->valid = true;
4382 }
4383
set_vendor_info_packet(struct dc_info_packet * info_packet,struct dc_stream_state * stream)4384 static void set_vendor_info_packet(
4385 struct dc_info_packet *info_packet,
4386 struct dc_stream_state *stream)
4387 {
4388 /* SPD info packet for FreeSync */
4389
4390 /* Check if Freesync is supported. Return if false. If true,
4391 * set the corresponding bit in the info packet
4392 */
4393 if (!stream->vsp_infopacket.valid)
4394 return;
4395
4396 *info_packet = stream->vsp_infopacket;
4397 }
4398
set_spd_info_packet(struct dc_info_packet * info_packet,struct dc_stream_state * stream)4399 static void set_spd_info_packet(
4400 struct dc_info_packet *info_packet,
4401 struct dc_stream_state *stream)
4402 {
4403 /* SPD info packet for FreeSync */
4404
4405 /* Check if Freesync is supported. Return if false. If true,
4406 * set the corresponding bit in the info packet
4407 */
4408 if (!stream->vrr_infopacket.valid)
4409 return;
4410
4411 *info_packet = stream->vrr_infopacket;
4412 }
4413
set_hdr_static_info_packet(struct dc_info_packet * info_packet,struct dc_stream_state * stream)4414 static void set_hdr_static_info_packet(
4415 struct dc_info_packet *info_packet,
4416 struct dc_stream_state *stream)
4417 {
4418 /* HDR Static Metadata info packet for HDR10 */
4419
4420 if (!stream->hdr_static_metadata.valid ||
4421 stream->use_dynamic_meta)
4422 return;
4423
4424 *info_packet = stream->hdr_static_metadata;
4425 }
4426
set_vsc_info_packet(struct dc_info_packet * info_packet,struct dc_stream_state * stream)4427 static void set_vsc_info_packet(
4428 struct dc_info_packet *info_packet,
4429 struct dc_stream_state *stream)
4430 {
4431 if (!stream->vsc_infopacket.valid)
4432 return;
4433
4434 *info_packet = stream->vsc_infopacket;
4435 }
set_hfvs_info_packet(struct dc_info_packet * info_packet,struct dc_stream_state * stream)4436 static void set_hfvs_info_packet(
4437 struct dc_info_packet *info_packet,
4438 struct dc_stream_state *stream)
4439 {
4440 if (!stream->hfvsif_infopacket.valid)
4441 return;
4442
4443 *info_packet = stream->hfvsif_infopacket;
4444 }
4445
adaptive_sync_override_dp_info_packets_sdp_line_num(const struct dc_crtc_timing * timing,struct enc_sdp_line_num * sdp_line_num,struct _vcs_dpi_display_pipe_dest_params_st * pipe_dlg_param)4446 static void adaptive_sync_override_dp_info_packets_sdp_line_num(
4447 const struct dc_crtc_timing *timing,
4448 struct enc_sdp_line_num *sdp_line_num,
4449 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dlg_param)
4450 {
4451 uint32_t asic_blank_start = 0;
4452 uint32_t asic_blank_end = 0;
4453 uint32_t v_update = 0;
4454
4455 const struct dc_crtc_timing *tg = timing;
4456
4457 /* blank_start = frame end - front porch */
4458 asic_blank_start = tg->v_total - tg->v_front_porch;
4459
4460 /* blank_end = blank_start - active */
4461 asic_blank_end = (asic_blank_start - tg->v_border_bottom -
4462 tg->v_addressable - tg->v_border_top);
4463
4464 if (pipe_dlg_param->vstartup_start > asic_blank_end) {
4465 v_update = (tg->v_total - (pipe_dlg_param->vstartup_start - asic_blank_end));
4466 sdp_line_num->adaptive_sync_line_num_valid = true;
4467 sdp_line_num->adaptive_sync_line_num = (tg->v_total - v_update - 1);
4468 } else {
4469 sdp_line_num->adaptive_sync_line_num_valid = false;
4470 sdp_line_num->adaptive_sync_line_num = 0;
4471 }
4472 }
4473
set_adaptive_sync_info_packet(struct dc_info_packet * info_packet,const struct dc_stream_state * stream,struct encoder_info_frame * info_frame,struct _vcs_dpi_display_pipe_dest_params_st * pipe_dlg_param)4474 static void set_adaptive_sync_info_packet(
4475 struct dc_info_packet *info_packet,
4476 const struct dc_stream_state *stream,
4477 struct encoder_info_frame *info_frame,
4478 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dlg_param)
4479 {
4480 if (!stream->adaptive_sync_infopacket.valid)
4481 return;
4482
4483 adaptive_sync_override_dp_info_packets_sdp_line_num(
4484 &stream->timing,
4485 &info_frame->sdp_line_num,
4486 pipe_dlg_param);
4487
4488 *info_packet = stream->adaptive_sync_infopacket;
4489 }
4490
set_vtem_info_packet(struct dc_info_packet * info_packet,struct dc_stream_state * stream)4491 static void set_vtem_info_packet(
4492 struct dc_info_packet *info_packet,
4493 struct dc_stream_state *stream)
4494 {
4495 if (!stream->vtem_infopacket.valid)
4496 return;
4497
4498 *info_packet = stream->vtem_infopacket;
4499 }
4500
dc_resource_find_first_free_pll(struct resource_context * res_ctx,const struct resource_pool * pool)4501 struct clock_source *dc_resource_find_first_free_pll(
4502 struct resource_context *res_ctx,
4503 const struct resource_pool *pool)
4504 {
4505 int i;
4506
4507 for (i = 0; i < pool->clk_src_count; ++i) {
4508 if (res_ctx->clock_source_ref_count[i] == 0)
4509 return pool->clock_sources[i];
4510 }
4511
4512 return NULL;
4513 }
4514
resource_build_info_frame(struct pipe_ctx * pipe_ctx)4515 void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
4516 {
4517 enum amd_signal_type signal = SIGNAL_TYPE_NONE;
4518 struct encoder_info_frame *info = &pipe_ctx->stream_res.encoder_info_frame;
4519
4520 /* default all packets to invalid */
4521 info->avi.valid = false;
4522 info->gamut.valid = false;
4523 info->vendor.valid = false;
4524 info->spd.valid = false;
4525 info->hdrsmd.valid = false;
4526 info->vsc.valid = false;
4527 info->hfvsif.valid = false;
4528 info->vtem.valid = false;
4529 info->adaptive_sync.valid = false;
4530 signal = pipe_ctx->stream->signal;
4531
4532 /* HDMi and DP have different info packets*/
4533 if (dc_is_hdmi_signal(signal)) {
4534 set_avi_info_frame(&info->avi, pipe_ctx);
4535
4536 set_vendor_info_packet(&info->vendor, pipe_ctx->stream);
4537 set_hfvs_info_packet(&info->hfvsif, pipe_ctx->stream);
4538 set_vtem_info_packet(&info->vtem, pipe_ctx->stream);
4539
4540 set_spd_info_packet(&info->spd, pipe_ctx->stream);
4541
4542 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
4543
4544 } else if (dc_is_dp_signal(signal)) {
4545 set_vsc_info_packet(&info->vsc, pipe_ctx->stream);
4546
4547 set_spd_info_packet(&info->spd, pipe_ctx->stream);
4548
4549 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
4550 set_adaptive_sync_info_packet(&info->adaptive_sync,
4551 pipe_ctx->stream,
4552 info,
4553 &pipe_ctx->pipe_dlg_param);
4554 }
4555
4556 patch_gamut_packet_checksum(&info->gamut);
4557 }
4558
resource_map_clock_resources(const struct dc * dc,struct dc_state * context,struct dc_stream_state * stream)4559 enum dc_status resource_map_clock_resources(
4560 const struct dc *dc,
4561 struct dc_state *context,
4562 struct dc_stream_state *stream)
4563 {
4564 /* acquire new resources */
4565 const struct resource_pool *pool = dc->res_pool;
4566 struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(
4567 &context->res_ctx, stream);
4568
4569 if (!pipe_ctx)
4570 return DC_ERROR_UNEXPECTED;
4571
4572 if (dc_is_dp_signal(pipe_ctx->stream->signal)
4573 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
4574 pipe_ctx->clock_source = pool->dp_clock_source;
4575 else {
4576 pipe_ctx->clock_source = NULL;
4577
4578 if (!dc->config.disable_disp_pll_sharing)
4579 pipe_ctx->clock_source = resource_find_used_clk_src_for_sharing(
4580 &context->res_ctx,
4581 pipe_ctx);
4582
4583 if (pipe_ctx->clock_source == NULL)
4584 pipe_ctx->clock_source =
4585 dc_resource_find_first_free_pll(
4586 &context->res_ctx,
4587 pool);
4588 }
4589
4590 if (pipe_ctx->clock_source == NULL)
4591 return DC_NO_CLOCK_SOURCE_RESOURCE;
4592
4593 resource_reference_clock_source(
4594 &context->res_ctx, pool,
4595 pipe_ctx->clock_source);
4596
4597 return DC_OK;
4598 }
4599
4600 /*
4601 * Note: We need to disable output if clock sources change,
4602 * since bios does optimization and doesn't apply if changing
4603 * PHY when not already disabled.
4604 */
pipe_need_reprogram(struct pipe_ctx * pipe_ctx_old,struct pipe_ctx * pipe_ctx)4605 bool pipe_need_reprogram(
4606 struct pipe_ctx *pipe_ctx_old,
4607 struct pipe_ctx *pipe_ctx)
4608 {
4609 if (!pipe_ctx_old->stream)
4610 return false;
4611
4612 if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink)
4613 return true;
4614
4615 if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal)
4616 return true;
4617
4618 if (pipe_ctx_old->stream_res.audio != pipe_ctx->stream_res.audio)
4619 return true;
4620
4621 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source
4622 && pipe_ctx_old->stream != pipe_ctx->stream)
4623 return true;
4624
4625 if (pipe_ctx_old->stream_res.stream_enc != pipe_ctx->stream_res.stream_enc)
4626 return true;
4627
4628 if (dc_is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream))
4629 return true;
4630
4631 if (pipe_ctx_old->stream->dpms_off != pipe_ctx->stream->dpms_off)
4632 return true;
4633
4634 if (false == pipe_ctx_old->stream->link->link_state_valid &&
4635 false == pipe_ctx_old->stream->dpms_off)
4636 return true;
4637
4638 if (pipe_ctx_old->stream_res.dsc != pipe_ctx->stream_res.dsc)
4639 return true;
4640
4641 if (pipe_ctx_old->stream_res.hpo_dp_stream_enc != pipe_ctx->stream_res.hpo_dp_stream_enc)
4642 return true;
4643 if (pipe_ctx_old->link_res.hpo_dp_link_enc != pipe_ctx->link_res.hpo_dp_link_enc)
4644 return true;
4645
4646 /* DIG link encoder resource assignment for stream changed. */
4647 if (pipe_ctx_old->stream->ctx->dc->res_pool->funcs->link_encs_assign) {
4648 bool need_reprogram = false;
4649 struct dc *dc = pipe_ctx_old->stream->ctx->dc;
4650 struct link_encoder *link_enc_prev =
4651 link_enc_cfg_get_link_enc_used_by_stream_current(dc, pipe_ctx_old->stream);
4652
4653 if (link_enc_prev != pipe_ctx->stream->link_enc)
4654 need_reprogram = true;
4655
4656 return need_reprogram;
4657 }
4658
4659 return false;
4660 }
4661
resource_build_bit_depth_reduction_params(struct dc_stream_state * stream,struct bit_depth_reduction_params * fmt_bit_depth)4662 void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,
4663 struct bit_depth_reduction_params *fmt_bit_depth)
4664 {
4665 enum dc_dither_option option = stream->dither_option;
4666 enum dc_pixel_encoding pixel_encoding =
4667 stream->timing.pixel_encoding;
4668
4669 memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth));
4670
4671 if (option == DITHER_OPTION_DEFAULT) {
4672 switch (stream->timing.display_color_depth) {
4673 case COLOR_DEPTH_666:
4674 option = DITHER_OPTION_SPATIAL6;
4675 break;
4676 case COLOR_DEPTH_888:
4677 option = DITHER_OPTION_SPATIAL8;
4678 break;
4679 case COLOR_DEPTH_101010:
4680 option = DITHER_OPTION_TRUN10;
4681 break;
4682 default:
4683 option = DITHER_OPTION_DISABLE;
4684 }
4685 }
4686
4687 if (option == DITHER_OPTION_DISABLE)
4688 return;
4689
4690 if (option == DITHER_OPTION_TRUN6) {
4691 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
4692 fmt_bit_depth->flags.TRUNCATE_DEPTH = 0;
4693 } else if (option == DITHER_OPTION_TRUN8 ||
4694 option == DITHER_OPTION_TRUN8_SPATIAL6 ||
4695 option == DITHER_OPTION_TRUN8_FM6) {
4696 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
4697 fmt_bit_depth->flags.TRUNCATE_DEPTH = 1;
4698 } else if (option == DITHER_OPTION_TRUN10 ||
4699 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
4700 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
4701 option == DITHER_OPTION_TRUN10_FM8 ||
4702 option == DITHER_OPTION_TRUN10_FM6 ||
4703 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
4704 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
4705 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
4706 if (option == DITHER_OPTION_TRUN10)
4707 fmt_bit_depth->flags.TRUNCATE_MODE = 1;
4708 }
4709
4710 /* special case - Formatter can only reduce by 4 bits at most.
4711 * When reducing from 12 to 6 bits,
4712 * HW recommends we use trunc with round mode
4713 * (if we did nothing, trunc to 10 bits would be used)
4714 * note that any 12->10 bit reduction is ignored prior to DCE8,
4715 * as the input was 10 bits.
4716 */
4717 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
4718 option == DITHER_OPTION_SPATIAL6 ||
4719 option == DITHER_OPTION_FM6) {
4720 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
4721 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
4722 fmt_bit_depth->flags.TRUNCATE_MODE = 1;
4723 }
4724
4725 /* spatial dither
4726 * note that spatial modes 1-3 are never used
4727 */
4728 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
4729 option == DITHER_OPTION_SPATIAL6 ||
4730 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
4731 option == DITHER_OPTION_TRUN8_SPATIAL6) {
4732 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
4733 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 0;
4734 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
4735 fmt_bit_depth->flags.RGB_RANDOM =
4736 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
4737 } else if (option == DITHER_OPTION_SPATIAL8_FRAME_RANDOM ||
4738 option == DITHER_OPTION_SPATIAL8 ||
4739 option == DITHER_OPTION_SPATIAL8_FM6 ||
4740 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
4741 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
4742 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
4743 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1;
4744 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
4745 fmt_bit_depth->flags.RGB_RANDOM =
4746 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
4747 } else if (option == DITHER_OPTION_SPATIAL10_FRAME_RANDOM ||
4748 option == DITHER_OPTION_SPATIAL10 ||
4749 option == DITHER_OPTION_SPATIAL10_FM8 ||
4750 option == DITHER_OPTION_SPATIAL10_FM6) {
4751 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
4752 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 2;
4753 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
4754 fmt_bit_depth->flags.RGB_RANDOM =
4755 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
4756 }
4757
4758 if (option == DITHER_OPTION_SPATIAL6 ||
4759 option == DITHER_OPTION_SPATIAL8 ||
4760 option == DITHER_OPTION_SPATIAL10) {
4761 fmt_bit_depth->flags.FRAME_RANDOM = 0;
4762 } else {
4763 fmt_bit_depth->flags.FRAME_RANDOM = 1;
4764 }
4765
4766 //////////////////////
4767 //// temporal dither
4768 //////////////////////
4769 if (option == DITHER_OPTION_FM6 ||
4770 option == DITHER_OPTION_SPATIAL8_FM6 ||
4771 option == DITHER_OPTION_SPATIAL10_FM6 ||
4772 option == DITHER_OPTION_TRUN10_FM6 ||
4773 option == DITHER_OPTION_TRUN8_FM6 ||
4774 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
4775 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
4776 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 0;
4777 } else if (option == DITHER_OPTION_FM8 ||
4778 option == DITHER_OPTION_SPATIAL10_FM8 ||
4779 option == DITHER_OPTION_TRUN10_FM8) {
4780 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
4781 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 1;
4782 } else if (option == DITHER_OPTION_FM10) {
4783 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
4784 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 2;
4785 }
4786
4787 fmt_bit_depth->pixel_encoding = pixel_encoding;
4788 }
4789
dc_validate_stream(struct dc * dc,struct dc_stream_state * stream)4790 enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream)
4791 {
4792 if (dc == NULL || stream == NULL)
4793 return DC_ERROR_UNEXPECTED;
4794
4795 struct dc_link *link = stream->link;
4796 struct timing_generator *tg = dc->res_pool->timing_generators[0];
4797 enum dc_status res = DC_OK;
4798
4799 calculate_phy_pix_clks(stream);
4800
4801 if (!tg->funcs->validate_timing(tg, &stream->timing))
4802 res = DC_FAIL_CONTROLLER_VALIDATE;
4803
4804 if (res == DC_OK) {
4805 if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
4806 !link->link_enc->funcs->validate_output_with_stream(
4807 link->link_enc, stream))
4808 res = DC_FAIL_ENC_VALIDATE;
4809 }
4810
4811 /* TODO: validate audio ASIC caps, encoder */
4812
4813 if (res == DC_OK)
4814 res = dc->link_srv->validate_mode_timing(stream,
4815 link,
4816 &stream->timing);
4817
4818 return res;
4819 }
4820
dc_validate_plane(struct dc * dc,const struct dc_plane_state * plane_state)4821 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state)
4822 {
4823 enum dc_status res = DC_OK;
4824
4825 /* check if surface has invalid dimensions */
4826 if (plane_state->src_rect.width == 0 || plane_state->src_rect.height == 0 ||
4827 plane_state->dst_rect.width == 0 || plane_state->dst_rect.height == 0)
4828 return DC_FAIL_SURFACE_VALIDATE;
4829
4830 /* TODO For now validates pixel format only */
4831 if (dc->res_pool->funcs->validate_plane)
4832 return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps);
4833
4834 return res;
4835 }
4836
resource_pixel_format_to_bpp(enum surface_pixel_format format)4837 unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format)
4838 {
4839 switch (format) {
4840 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
4841 return 8;
4842 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
4843 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
4844 return 12;
4845 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
4846 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
4847 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
4848 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
4849 return 16;
4850 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
4851 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
4852 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
4853 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
4854 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
4855 case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
4856 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
4857 return 32;
4858 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
4859 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
4860 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
4861 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
4862 return 64;
4863 default:
4864 ASSERT_CRITICAL(false);
4865 return -1;
4866 }
4867 }
get_max_audio_sample_rate(struct audio_mode * modes)4868 static unsigned int get_max_audio_sample_rate(struct audio_mode *modes)
4869 {
4870 if (modes) {
4871 if (modes->sample_rates.rate.RATE_192)
4872 return 192000;
4873 if (modes->sample_rates.rate.RATE_176_4)
4874 return 176400;
4875 if (modes->sample_rates.rate.RATE_96)
4876 return 96000;
4877 if (modes->sample_rates.rate.RATE_88_2)
4878 return 88200;
4879 if (modes->sample_rates.rate.RATE_48)
4880 return 48000;
4881 if (modes->sample_rates.rate.RATE_44_1)
4882 return 44100;
4883 if (modes->sample_rates.rate.RATE_32)
4884 return 32000;
4885 }
4886 /*original logic when no audio info*/
4887 return 441000;
4888 }
4889
get_audio_check(struct audio_info * aud_modes,struct audio_check * audio_chk)4890 void get_audio_check(struct audio_info *aud_modes,
4891 struct audio_check *audio_chk)
4892 {
4893 unsigned int i;
4894 unsigned int max_sample_rate = 0;
4895
4896 if (aud_modes) {
4897 audio_chk->audio_packet_type = 0x2;/*audio sample packet AP = .25 for layout0, 1 for layout1*/
4898
4899 audio_chk->max_audiosample_rate = 0;
4900 for (i = 0; i < aud_modes->mode_count; i++) {
4901 max_sample_rate = get_max_audio_sample_rate(&aud_modes->modes[i]);
4902 if (audio_chk->max_audiosample_rate < max_sample_rate)
4903 audio_chk->max_audiosample_rate = max_sample_rate;
4904 /*dts takes the same as type 2: AP = 0.25*/
4905 }
4906 /*check which one take more bandwidth*/
4907 if (audio_chk->max_audiosample_rate > 192000)
4908 audio_chk->audio_packet_type = 0x9;/*AP =1*/
4909 audio_chk->acat = 0;/*not support*/
4910 }
4911 }
4912
get_temp_hpo_dp_link_enc(const struct resource_context * res_ctx,const struct resource_pool * const pool,const struct dc_link * link)4913 static struct hpo_dp_link_encoder *get_temp_hpo_dp_link_enc(
4914 const struct resource_context *res_ctx,
4915 const struct resource_pool *const pool,
4916 const struct dc_link *link)
4917 {
4918 struct hpo_dp_link_encoder *hpo_dp_link_enc = NULL;
4919 int enc_index;
4920
4921 enc_index = find_acquired_hpo_dp_link_enc_for_link(res_ctx, link);
4922
4923 if (enc_index < 0)
4924 enc_index = find_free_hpo_dp_link_enc(res_ctx, pool);
4925
4926 if (enc_index >= 0)
4927 hpo_dp_link_enc = pool->hpo_dp_link_enc[enc_index];
4928
4929 return hpo_dp_link_enc;
4930 }
4931
get_temp_dp_link_res(struct dc_link * link,struct link_resource * link_res,struct dc_link_settings * link_settings)4932 bool get_temp_dp_link_res(struct dc_link *link,
4933 struct link_resource *link_res,
4934 struct dc_link_settings *link_settings)
4935 {
4936 const struct dc *dc = link->dc;
4937 const struct resource_context *res_ctx = &dc->current_state->res_ctx;
4938
4939 memset(link_res, 0, sizeof(*link_res));
4940
4941 if (dc->link_srv->dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING) {
4942 link_res->hpo_dp_link_enc = get_temp_hpo_dp_link_enc(res_ctx,
4943 dc->res_pool, link);
4944 if (!link_res->hpo_dp_link_enc)
4945 return false;
4946 }
4947 return true;
4948 }
4949
reset_syncd_pipes_from_disabled_pipes(struct dc * dc,struct dc_state * context)4950 void reset_syncd_pipes_from_disabled_pipes(struct dc *dc,
4951 struct dc_state *context)
4952 {
4953 int i, j;
4954 struct pipe_ctx *pipe_ctx_old, *pipe_ctx, *pipe_ctx_syncd;
4955
4956 /* If pipe backend is reset, need to reset pipe syncd status */
4957 for (i = 0; i < dc->res_pool->pipe_count; i++) {
4958 pipe_ctx_old = &dc->current_state->res_ctx.pipe_ctx[i];
4959 pipe_ctx = &context->res_ctx.pipe_ctx[i];
4960
4961 if (!resource_is_pipe_type(pipe_ctx_old, OTG_MASTER))
4962 continue;
4963
4964 if (!pipe_ctx->stream ||
4965 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
4966
4967 /* Reset all the syncd pipes from the disabled pipe */
4968 for (j = 0; j < dc->res_pool->pipe_count; j++) {
4969 pipe_ctx_syncd = &context->res_ctx.pipe_ctx[j];
4970 if ((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx_syncd) == pipe_ctx_old->pipe_idx) ||
4971 !IS_PIPE_SYNCD_VALID(pipe_ctx_syncd))
4972 SET_PIPE_SYNCD_TO_PIPE(pipe_ctx_syncd, j);
4973 }
4974 }
4975 }
4976 }
4977
check_syncd_pipes_for_disabled_master_pipe(struct dc * dc,struct dc_state * context,uint8_t disabled_master_pipe_idx)4978 void check_syncd_pipes_for_disabled_master_pipe(struct dc *dc,
4979 struct dc_state *context,
4980 uint8_t disabled_master_pipe_idx)
4981 {
4982 int i;
4983 struct pipe_ctx *pipe_ctx, *pipe_ctx_check;
4984
4985 pipe_ctx = &context->res_ctx.pipe_ctx[disabled_master_pipe_idx];
4986 if ((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx) != disabled_master_pipe_idx) ||
4987 !IS_PIPE_SYNCD_VALID(pipe_ctx))
4988 SET_PIPE_SYNCD_TO_PIPE(pipe_ctx, disabled_master_pipe_idx);
4989
4990 /* for the pipe disabled, check if any slave pipe exists and assert */
4991 for (i = 0; i < dc->res_pool->pipe_count; i++) {
4992 pipe_ctx_check = &context->res_ctx.pipe_ctx[i];
4993
4994 if ((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx_check) == disabled_master_pipe_idx) &&
4995 IS_PIPE_SYNCD_VALID(pipe_ctx_check) && (i != disabled_master_pipe_idx)) {
4996 struct pipe_ctx *first_pipe = pipe_ctx_check;
4997
4998 while (first_pipe->prev_odm_pipe)
4999 first_pipe = first_pipe->prev_odm_pipe;
5000 /* When ODM combine is enabled, this case is expected. If the disabled pipe
5001 * is part of the ODM tree, then we should not print an error.
5002 * */
5003 if (first_pipe->pipe_idx == disabled_master_pipe_idx)
5004 continue;
5005
5006 DC_ERR("DC: Failure: pipe_idx[%d] syncd with disabled master pipe_idx[%d]\n",
5007 i, disabled_master_pipe_idx);
5008 }
5009 }
5010 }
5011
reset_sync_context_for_pipe(const struct dc * dc,struct dc_state * context,uint8_t pipe_idx)5012 void reset_sync_context_for_pipe(const struct dc *dc,
5013 struct dc_state *context,
5014 uint8_t pipe_idx)
5015 {
5016 int i;
5017 struct pipe_ctx *pipe_ctx_reset;
5018
5019 /* reset the otg sync context for the pipe and its slave pipes if any */
5020 for (i = 0; i < dc->res_pool->pipe_count; i++) {
5021 pipe_ctx_reset = &context->res_ctx.pipe_ctx[i];
5022
5023 if (((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx_reset) == pipe_idx) &&
5024 IS_PIPE_SYNCD_VALID(pipe_ctx_reset)) || (i == pipe_idx))
5025 SET_PIPE_SYNCD_TO_PIPE(pipe_ctx_reset, i);
5026 }
5027 }
5028
resource_transmitter_to_phy_idx(const struct dc * dc,enum transmitter transmitter)5029 uint8_t resource_transmitter_to_phy_idx(const struct dc *dc, enum transmitter transmitter)
5030 {
5031 /* TODO - get transmitter to phy idx mapping from DMUB */
5032 uint8_t phy_idx = transmitter - TRANSMITTER_UNIPHY_A;
5033
5034 if (dc->ctx->dce_version == DCN_VERSION_3_1 &&
5035 dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) {
5036 switch (transmitter) {
5037 case TRANSMITTER_UNIPHY_A:
5038 phy_idx = 0;
5039 break;
5040 case TRANSMITTER_UNIPHY_B:
5041 phy_idx = 1;
5042 break;
5043 case TRANSMITTER_UNIPHY_C:
5044 phy_idx = 5;
5045 break;
5046 case TRANSMITTER_UNIPHY_D:
5047 phy_idx = 6;
5048 break;
5049 case TRANSMITTER_UNIPHY_E:
5050 phy_idx = 4;
5051 break;
5052 default:
5053 phy_idx = 0;
5054 break;
5055 }
5056 }
5057
5058 return phy_idx;
5059 }
5060
get_link_hwss(const struct dc_link * link,const struct link_resource * link_res)5061 const struct link_hwss *get_link_hwss(const struct dc_link *link,
5062 const struct link_resource *link_res)
5063 {
5064 /* Link_hwss is only accessible by getter function instead of accessing
5065 * by pointers in dc with the intent to protect against breaking polymorphism.
5066 */
5067 if (can_use_hpo_dp_link_hwss(link, link_res))
5068 /* TODO: some assumes that if decided link settings is 128b/132b
5069 * channel coding format hpo_dp_link_enc should be used.
5070 * Others believe that if hpo_dp_link_enc is available in link
5071 * resource then hpo_dp_link_enc must be used. This bound between
5072 * hpo_dp_link_enc != NULL and decided link settings is loosely coupled
5073 * with a premise that both hpo_dp_link_enc pointer and decided link
5074 * settings are determined based on single policy function like
5075 * "decide_link_settings" from upper layer. This "convention"
5076 * cannot be maintained and enforced at current level.
5077 * Therefore a refactor is due so we can enforce a strong bound
5078 * between those two parameters at this level.
5079 *
5080 * To put it simple, we want to make enforcement at low level so that
5081 * we will not return link hwss if caller plans to do 8b/10b
5082 * with an hpo encoder. Or we can return a very dummy one that doesn't
5083 * do work for all functions
5084 */
5085 return (requires_fixed_vs_pe_retimer_hpo_link_hwss(link) ?
5086 get_hpo_fixed_vs_pe_retimer_dp_link_hwss() : get_hpo_dp_link_hwss());
5087 else if (can_use_dpia_link_hwss(link, link_res))
5088 return get_dpia_link_hwss();
5089 else if (can_use_dio_link_hwss(link, link_res))
5090 return (requires_fixed_vs_pe_retimer_dio_link_hwss(link)) ?
5091 get_dio_fixed_vs_pe_retimer_link_hwss() : get_dio_link_hwss();
5092 else
5093 return get_virtual_link_hwss();
5094 }
5095
is_h_timing_divisible_by_2(struct dc_stream_state * stream)5096 bool is_h_timing_divisible_by_2(struct dc_stream_state *stream)
5097 {
5098 bool divisible = false;
5099 uint16_t h_blank_start = 0;
5100 uint16_t h_blank_end = 0;
5101
5102 if (stream) {
5103 h_blank_start = stream->timing.h_total - stream->timing.h_front_porch;
5104 h_blank_end = h_blank_start - stream->timing.h_addressable;
5105
5106 /* HTOTAL, Hblank start/end, and Hsync start/end all must be
5107 * divisible by 2 in order for the horizontal timing params
5108 * to be considered divisible by 2. Hsync start is always 0.
5109 */
5110 divisible = (stream->timing.h_total % 2 == 0) &&
5111 (h_blank_start % 2 == 0) &&
5112 (h_blank_end % 2 == 0) &&
5113 (stream->timing.h_sync_width % 2 == 0);
5114 }
5115 return divisible;
5116 }
5117
5118 /* This interface is deprecated for new DCNs. It is replaced by the following
5119 * new interfaces. These two interfaces encapsulate pipe selection priority
5120 * with DCN specific minimum hardware transition optimization algorithm. With
5121 * the new interfaces caller no longer needs to know the implementation detail
5122 * of a pipe topology.
5123 *
5124 * resource_update_pipes_with_odm_slice_count
5125 * resource_update_pipes_with_mpc_slice_count
5126 *
5127 */
dc_resource_acquire_secondary_pipe_for_mpc_odm_legacy(const struct dc * dc,struct dc_state * state,struct pipe_ctx * pri_pipe,struct pipe_ctx * sec_pipe,bool odm)5128 bool dc_resource_acquire_secondary_pipe_for_mpc_odm_legacy(
5129 const struct dc *dc,
5130 struct dc_state *state,
5131 struct pipe_ctx *pri_pipe,
5132 struct pipe_ctx *sec_pipe,
5133 bool odm)
5134 {
5135 int pipe_idx = sec_pipe->pipe_idx;
5136 struct pipe_ctx *sec_top, *sec_bottom, *sec_next, *sec_prev;
5137 const struct resource_pool *pool = dc->res_pool;
5138
5139 sec_top = sec_pipe->top_pipe;
5140 sec_bottom = sec_pipe->bottom_pipe;
5141 sec_next = sec_pipe->next_odm_pipe;
5142 sec_prev = sec_pipe->prev_odm_pipe;
5143
5144 if (pri_pipe == NULL)
5145 return false;
5146
5147 *sec_pipe = *pri_pipe;
5148
5149 sec_pipe->top_pipe = sec_top;
5150 sec_pipe->bottom_pipe = sec_bottom;
5151 sec_pipe->next_odm_pipe = sec_next;
5152 sec_pipe->prev_odm_pipe = sec_prev;
5153
5154 sec_pipe->pipe_idx = pipe_idx;
5155 sec_pipe->plane_res.mi = pool->mis[pipe_idx];
5156 sec_pipe->plane_res.hubp = pool->hubps[pipe_idx];
5157 sec_pipe->plane_res.ipp = pool->ipps[pipe_idx];
5158 sec_pipe->plane_res.xfm = pool->transforms[pipe_idx];
5159 sec_pipe->plane_res.dpp = pool->dpps[pipe_idx];
5160 sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;
5161 sec_pipe->stream_res.dsc = NULL;
5162 if (odm) {
5163 if (!sec_pipe->top_pipe)
5164 sec_pipe->stream_res.opp = pool->opps[pipe_idx];
5165 else
5166 sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp;
5167 if (sec_pipe->stream->timing.flags.DSC == 1) {
5168 #if defined(CONFIG_DRM_AMD_DC_FP)
5169 dcn20_acquire_dsc(dc, &state->res_ctx, &sec_pipe->stream_res.dsc, sec_pipe->stream_res.opp->inst);
5170 #endif
5171 ASSERT(sec_pipe->stream_res.dsc);
5172 if (sec_pipe->stream_res.dsc == NULL)
5173 return false;
5174 }
5175 #if defined(CONFIG_DRM_AMD_DC_FP)
5176 dcn20_build_mapped_resource(dc, state, sec_pipe->stream);
5177 #endif
5178 }
5179
5180 return true;
5181 }
5182
update_dp_encoder_resources_for_test_harness(const struct dc * dc,struct dc_state * context,struct pipe_ctx * pipe_ctx)5183 enum dc_status update_dp_encoder_resources_for_test_harness(const struct dc *dc,
5184 struct dc_state *context,
5185 struct pipe_ctx *pipe_ctx)
5186 {
5187 if (dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings) == DP_128b_132b_ENCODING) {
5188 if (pipe_ctx->stream_res.hpo_dp_stream_enc == NULL) {
5189 pipe_ctx->stream_res.hpo_dp_stream_enc =
5190 find_first_free_match_hpo_dp_stream_enc_for_link(
5191 &context->res_ctx, dc->res_pool, pipe_ctx->stream);
5192
5193 if (!pipe_ctx->stream_res.hpo_dp_stream_enc)
5194 return DC_NO_STREAM_ENC_RESOURCE;
5195
5196 update_hpo_dp_stream_engine_usage(
5197 &context->res_ctx, dc->res_pool,
5198 pipe_ctx->stream_res.hpo_dp_stream_enc,
5199 true);
5200 }
5201
5202 if (pipe_ctx->link_res.hpo_dp_link_enc == NULL) {
5203 if (!add_hpo_dp_link_enc_to_ctx(&context->res_ctx, dc->res_pool, pipe_ctx, pipe_ctx->stream))
5204 return DC_NO_LINK_ENC_RESOURCE;
5205 }
5206 } else {
5207 if (pipe_ctx->stream_res.hpo_dp_stream_enc) {
5208 update_hpo_dp_stream_engine_usage(
5209 &context->res_ctx, dc->res_pool,
5210 pipe_ctx->stream_res.hpo_dp_stream_enc,
5211 false);
5212 pipe_ctx->stream_res.hpo_dp_stream_enc = NULL;
5213 }
5214 if (pipe_ctx->link_res.hpo_dp_link_enc)
5215 remove_hpo_dp_link_enc_from_ctx(&context->res_ctx, pipe_ctx, pipe_ctx->stream);
5216 }
5217
5218 return DC_OK;
5219 }
5220
check_subvp_sw_cursor_fallback_req(const struct dc * dc,struct dc_stream_state * stream)5221 bool check_subvp_sw_cursor_fallback_req(const struct dc *dc, struct dc_stream_state *stream)
5222 {
5223 if (!dc->debug.disable_subvp_high_refresh && is_subvp_high_refresh_candidate(stream))
5224 return true;
5225 if (dc->current_state->stream_count == 1 && stream->timing.v_addressable >= 2880 &&
5226 ((stream->timing.pix_clk_100hz * 100) / stream->timing.v_total / stream->timing.h_total) < 120)
5227 return true;
5228 else if (dc->current_state->stream_count > 1 && stream->timing.v_addressable >= 1080 &&
5229 ((stream->timing.pix_clk_100hz * 100) / stream->timing.v_total / stream->timing.h_total) < 120)
5230 return true;
5231
5232 return false;
5233 }
5234
resource_get_dscl_prog_data(struct pipe_ctx * pipe_ctx)5235 struct dscl_prog_data *resource_get_dscl_prog_data(struct pipe_ctx *pipe_ctx)
5236 {
5237 return &pipe_ctx->plane_res.scl_data.dscl_prog_data;
5238 }
5239
resource_init_common_dml2_callbacks(struct dc * dc,struct dml2_configuration_options * dml2_options)5240 void resource_init_common_dml2_callbacks(struct dc *dc, struct dml2_configuration_options *dml2_options)
5241 {
5242 dml2_options->callbacks.dc = dc;
5243 dml2_options->callbacks.build_scaling_params = &resource_build_scaling_params;
5244 dml2_options->callbacks.build_test_pattern_params = &resource_build_test_pattern_params;
5245 dml2_options->callbacks.acquire_secondary_pipe_for_mpc_odm = &dc_resource_acquire_secondary_pipe_for_mpc_odm_legacy;
5246 dml2_options->callbacks.update_pipes_for_stream_with_slice_count = &resource_update_pipes_for_stream_with_slice_count;
5247 dml2_options->callbacks.update_pipes_for_plane_with_slice_count = &resource_update_pipes_for_plane_with_slice_count;
5248 dml2_options->callbacks.get_mpc_slice_index = &resource_get_mpc_slice_index;
5249 dml2_options->callbacks.get_mpc_slice_count = &resource_get_mpc_slice_count;
5250 dml2_options->callbacks.get_odm_slice_index = &resource_get_odm_slice_index;
5251 dml2_options->callbacks.get_odm_slice_count = &resource_get_odm_slice_count;
5252 dml2_options->callbacks.get_opp_head = &resource_get_opp_head;
5253 dml2_options->callbacks.get_otg_master_for_stream = &resource_get_otg_master_for_stream;
5254 dml2_options->callbacks.get_opp_heads_for_otg_master = &resource_get_opp_heads_for_otg_master;
5255 dml2_options->callbacks.get_dpp_pipes_for_plane = &resource_get_dpp_pipes_for_plane;
5256 dml2_options->callbacks.get_stream_status = &dc_state_get_stream_status;
5257 dml2_options->callbacks.get_stream_from_id = &dc_state_get_stream_from_id;
5258 dml2_options->callbacks.get_max_flickerless_instant_vtotal_increase = &dc_stream_get_max_flickerless_instant_vtotal_increase;
5259
5260 dml2_options->svp_pstate.callbacks.dc = dc;
5261 dml2_options->svp_pstate.callbacks.add_phantom_plane = &dc_state_add_phantom_plane;
5262 dml2_options->svp_pstate.callbacks.add_phantom_stream = &dc_state_add_phantom_stream;
5263 dml2_options->svp_pstate.callbacks.build_scaling_params = &resource_build_scaling_params;
5264 dml2_options->svp_pstate.callbacks.create_phantom_plane = &dc_state_create_phantom_plane;
5265 dml2_options->svp_pstate.callbacks.remove_phantom_plane = &dc_state_remove_phantom_plane;
5266 dml2_options->svp_pstate.callbacks.remove_phantom_stream = &dc_state_remove_phantom_stream;
5267 dml2_options->svp_pstate.callbacks.create_phantom_stream = &dc_state_create_phantom_stream;
5268 dml2_options->svp_pstate.callbacks.release_phantom_plane = &dc_state_release_phantom_plane;
5269 dml2_options->svp_pstate.callbacks.release_phantom_stream = &dc_state_release_phantom_stream;
5270 dml2_options->svp_pstate.callbacks.get_pipe_subvp_type = &dc_state_get_pipe_subvp_type;
5271 dml2_options->svp_pstate.callbacks.get_stream_subvp_type = &dc_state_get_stream_subvp_type;
5272 dml2_options->svp_pstate.callbacks.get_paired_subvp_stream = &dc_state_get_paired_subvp_stream;
5273 dml2_options->svp_pstate.callbacks.remove_phantom_streams_and_planes = &dc_state_remove_phantom_streams_and_planes;
5274 dml2_options->svp_pstate.callbacks.release_phantom_streams_and_planes = &dc_state_release_phantom_streams_and_planes;
5275 }
5276
5277 /* Returns number of DET segments allocated for a given OTG_MASTER pipe */
resource_calculate_det_for_stream(struct dc_state * state,struct pipe_ctx * otg_master)5278 int resource_calculate_det_for_stream(struct dc_state *state, struct pipe_ctx *otg_master)
5279 {
5280 struct pipe_ctx *opp_heads[MAX_PIPES];
5281 struct pipe_ctx *dpp_pipes[MAX_PIPES];
5282
5283 int dpp_count = 0;
5284 int det_segments = 0;
5285
5286 if (!otg_master->stream)
5287 return 0;
5288
5289 int slice_count = resource_get_opp_heads_for_otg_master(otg_master,
5290 &state->res_ctx, opp_heads);
5291
5292 for (int slice_idx = 0; slice_idx < slice_count; slice_idx++) {
5293 if (opp_heads[slice_idx]->plane_state) {
5294 dpp_count = resource_get_dpp_pipes_for_opp_head(
5295 opp_heads[slice_idx],
5296 &state->res_ctx,
5297 dpp_pipes);
5298 for (int dpp_idx = 0; dpp_idx < dpp_count; dpp_idx++)
5299 det_segments += dpp_pipes[dpp_idx]->hubp_regs.det_size;
5300 }
5301 }
5302 return det_segments;
5303 }
5304
resource_is_hpo_acquired(struct dc_state * context)5305 bool resource_is_hpo_acquired(struct dc_state *context)
5306 {
5307 int i;
5308
5309 for (i = 0; i < MAX_HPO_DP2_ENCODERS; i++) {
5310 if (context->res_ctx.is_hpo_dp_stream_enc_acquired[i]) {
5311 return true;
5312 }
5313 }
5314
5315 return false;
5316 }
5317