1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
5
6 This file is part of GCC.
7
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 2, or (at your option) any later
11 version.
12
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
21 02110-1301, USA. */
22
23 #include "config.h"
24 #include "system.h"
25 #include "coretypes.h"
26 #include "tm.h"
27
28 #include "machmode.h"
29 #include "hard-reg-set.h"
30 #include "rtl.h"
31 #include "tm_p.h"
32 #include "obstack.h"
33 #include "insn-config.h"
34 #include "flags.h"
35 #include "function.h"
36 #include "expr.h"
37 #include "optabs.h"
38 #include "regs.h"
39 #include "addresses.h"
40 #include "basic-block.h"
41 #include "reload.h"
42 #include "recog.h"
43 #include "output.h"
44 #include "real.h"
45 #include "toplev.h"
46 #include "except.h"
47 #include "tree.h"
48 #include "target.h"
49
50 /* This file contains the reload pass of the compiler, which is
51 run after register allocation has been done. It checks that
52 each insn is valid (operands required to be in registers really
53 are in registers of the proper class) and fixes up invalid ones
54 by copying values temporarily into registers for the insns
55 that need them.
56
57 The results of register allocation are described by the vector
58 reg_renumber; the insns still contain pseudo regs, but reg_renumber
59 can be used to find which hard reg, if any, a pseudo reg is in.
60
61 The technique we always use is to free up a few hard regs that are
62 called ``reload regs'', and for each place where a pseudo reg
63 must be in a hard reg, copy it temporarily into one of the reload regs.
64
65 Reload regs are allocated locally for every instruction that needs
66 reloads. When there are pseudos which are allocated to a register that
67 has been chosen as a reload reg, such pseudos must be ``spilled''.
68 This means that they go to other hard regs, or to stack slots if no other
69 available hard regs can be found. Spilling can invalidate more
70 insns, requiring additional need for reloads, so we must keep checking
71 until the process stabilizes.
72
73 For machines with different classes of registers, we must keep track
74 of the register class needed for each reload, and make sure that
75 we allocate enough reload registers of each class.
76
77 The file reload.c contains the code that checks one insn for
78 validity and reports the reloads that it needs. This file
79 is in charge of scanning the entire rtl code, accumulating the
80 reload needs, spilling, assigning reload registers to use for
81 fixing up each insn, and generating the new insns to copy values
82 into the reload registers. */
83
84 /* During reload_as_needed, element N contains a REG rtx for the hard reg
85 into which reg N has been reloaded (perhaps for a previous insn). */
86 static rtx *reg_last_reload_reg;
87
88 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
89 for an output reload that stores into reg N. */
90 static regset_head reg_has_output_reload;
91
92 /* Indicates which hard regs are reload-registers for an output reload
93 in the current insn. */
94 static HARD_REG_SET reg_is_output_reload;
95
96 /* Element N is the constant value to which pseudo reg N is equivalent,
97 or zero if pseudo reg N is not equivalent to a constant.
98 find_reloads looks at this in order to replace pseudo reg N
99 with the constant it stands for. */
100 rtx *reg_equiv_constant;
101
102 /* Element N is an invariant value to which pseudo reg N is equivalent.
103 eliminate_regs_in_insn uses this to replace pseudos in particular
104 contexts. */
105 rtx *reg_equiv_invariant;
106
107 /* Element N is a memory location to which pseudo reg N is equivalent,
108 prior to any register elimination (such as frame pointer to stack
109 pointer). Depending on whether or not it is a valid address, this value
110 is transferred to either reg_equiv_address or reg_equiv_mem. */
111 rtx *reg_equiv_memory_loc;
112
113 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
114 collector can keep track of what is inside. */
115 VEC(rtx,gc) *reg_equiv_memory_loc_vec;
116
117 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
118 This is used when the address is not valid as a memory address
119 (because its displacement is too big for the machine.) */
120 rtx *reg_equiv_address;
121
122 /* Element N is the memory slot to which pseudo reg N is equivalent,
123 or zero if pseudo reg N is not equivalent to a memory slot. */
124 rtx *reg_equiv_mem;
125
126 /* Element N is an EXPR_LIST of REG_EQUIVs containing MEMs with
127 alternate representations of the location of pseudo reg N. */
128 rtx *reg_equiv_alt_mem_list;
129
130 /* Widest width in which each pseudo reg is referred to (via subreg). */
131 static unsigned int *reg_max_ref_width;
132
133 /* Element N is the list of insns that initialized reg N from its equivalent
134 constant or memory slot. */
135 rtx *reg_equiv_init;
136 int reg_equiv_init_size;
137
138 /* Vector to remember old contents of reg_renumber before spilling. */
139 static short *reg_old_renumber;
140
141 /* During reload_as_needed, element N contains the last pseudo regno reloaded
142 into hard register N. If that pseudo reg occupied more than one register,
143 reg_reloaded_contents points to that pseudo for each spill register in
144 use; all of these must remain set for an inheritance to occur. */
145 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
146
147 /* During reload_as_needed, element N contains the insn for which
148 hard register N was last used. Its contents are significant only
149 when reg_reloaded_valid is set for this register. */
150 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
151
152 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
153 static HARD_REG_SET reg_reloaded_valid;
154 /* Indicate if the register was dead at the end of the reload.
155 This is only valid if reg_reloaded_contents is set and valid. */
156 static HARD_REG_SET reg_reloaded_dead;
157
158 /* Indicate whether the register's current value is one that is not
159 safe to retain across a call, even for registers that are normally
160 call-saved. */
161 static HARD_REG_SET reg_reloaded_call_part_clobbered;
162
163 /* Number of spill-regs so far; number of valid elements of spill_regs. */
164 static int n_spills;
165
166 /* In parallel with spill_regs, contains REG rtx's for those regs.
167 Holds the last rtx used for any given reg, or 0 if it has never
168 been used for spilling yet. This rtx is reused, provided it has
169 the proper mode. */
170 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
171
172 /* In parallel with spill_regs, contains nonzero for a spill reg
173 that was stored after the last time it was used.
174 The precise value is the insn generated to do the store. */
175 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
176
177 /* This is the register that was stored with spill_reg_store. This is a
178 copy of reload_out / reload_out_reg when the value was stored; if
179 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
180 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
181
182 /* This table is the inverse mapping of spill_regs:
183 indexed by hard reg number,
184 it contains the position of that reg in spill_regs,
185 or -1 for something that is not in spill_regs.
186
187 ?!? This is no longer accurate. */
188 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
189
190 /* This reg set indicates registers that can't be used as spill registers for
191 the currently processed insn. These are the hard registers which are live
192 during the insn, but not allocated to pseudos, as well as fixed
193 registers. */
194 static HARD_REG_SET bad_spill_regs;
195
196 /* These are the hard registers that can't be used as spill register for any
197 insn. This includes registers used for user variables and registers that
198 we can't eliminate. A register that appears in this set also can't be used
199 to retry register allocation. */
200 static HARD_REG_SET bad_spill_regs_global;
201
202 /* Describes order of use of registers for reloading
203 of spilled pseudo-registers. `n_spills' is the number of
204 elements that are actually valid; new ones are added at the end.
205
206 Both spill_regs and spill_reg_order are used on two occasions:
207 once during find_reload_regs, where they keep track of the spill registers
208 for a single insn, but also during reload_as_needed where they show all
209 the registers ever used by reload. For the latter case, the information
210 is calculated during finish_spills. */
211 static short spill_regs[FIRST_PSEUDO_REGISTER];
212
213 /* This vector of reg sets indicates, for each pseudo, which hard registers
214 may not be used for retrying global allocation because the register was
215 formerly spilled from one of them. If we allowed reallocating a pseudo to
216 a register that it was already allocated to, reload might not
217 terminate. */
218 static HARD_REG_SET *pseudo_previous_regs;
219
220 /* This vector of reg sets indicates, for each pseudo, which hard
221 registers may not be used for retrying global allocation because they
222 are used as spill registers during one of the insns in which the
223 pseudo is live. */
224 static HARD_REG_SET *pseudo_forbidden_regs;
225
226 /* All hard regs that have been used as spill registers for any insn are
227 marked in this set. */
228 static HARD_REG_SET used_spill_regs;
229
230 /* Index of last register assigned as a spill register. We allocate in
231 a round-robin fashion. */
232 static int last_spill_reg;
233
234 /* Nonzero if indirect addressing is supported on the machine; this means
235 that spilling (REG n) does not require reloading it into a register in
236 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
237 value indicates the level of indirect addressing supported, e.g., two
238 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
239 a hard register. */
240 static char spill_indirect_levels;
241
242 /* Nonzero if indirect addressing is supported when the innermost MEM is
243 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
244 which these are valid is the same as spill_indirect_levels, above. */
245 char indirect_symref_ok;
246
247 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
248 char double_reg_address_ok;
249
250 /* Record the stack slot for each spilled hard register. */
251 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
252
253 /* Width allocated so far for that stack slot. */
254 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
255
256 /* Record which pseudos needed to be spilled. */
257 static regset_head spilled_pseudos;
258
259 /* Used for communication between order_regs_for_reload and count_pseudo.
260 Used to avoid counting one pseudo twice. */
261 static regset_head pseudos_counted;
262
263 /* First uid used by insns created by reload in this function.
264 Used in find_equiv_reg. */
265 int reload_first_uid;
266
267 /* Flag set by local-alloc or global-alloc if anything is live in
268 a call-clobbered reg across calls. */
269 int caller_save_needed;
270
271 /* Set to 1 while reload_as_needed is operating.
272 Required by some machines to handle any generated moves differently. */
273 int reload_in_progress = 0;
274
275 /* These arrays record the insn_code of insns that may be needed to
276 perform input and output reloads of special objects. They provide a
277 place to pass a scratch register. */
278 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
279 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
280
281 /* This obstack is used for allocation of rtl during register elimination.
282 The allocated storage can be freed once find_reloads has processed the
283 insn. */
284 static struct obstack reload_obstack;
285
286 /* Points to the beginning of the reload_obstack. All insn_chain structures
287 are allocated first. */
288 static char *reload_startobj;
289
290 /* The point after all insn_chain structures. Used to quickly deallocate
291 memory allocated in copy_reloads during calculate_needs_all_insns. */
292 static char *reload_firstobj;
293
294 /* This points before all local rtl generated by register elimination.
295 Used to quickly free all memory after processing one insn. */
296 static char *reload_insn_firstobj;
297
298 /* List of insn_chain instructions, one for every insn that reload needs to
299 examine. */
300 struct insn_chain *reload_insn_chain;
301
302 /* List of all insns needing reloads. */
303 static struct insn_chain *insns_need_reload;
304
305 /* This structure is used to record information about register eliminations.
306 Each array entry describes one possible way of eliminating a register
307 in favor of another. If there is more than one way of eliminating a
308 particular register, the most preferred should be specified first. */
309
310 struct elim_table
311 {
312 int from; /* Register number to be eliminated. */
313 int to; /* Register number used as replacement. */
314 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
315 int can_eliminate; /* Nonzero if this elimination can be done. */
316 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
317 insns made by reload. */
318 HOST_WIDE_INT offset; /* Current offset between the two regs. */
319 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
320 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
321 rtx from_rtx; /* REG rtx for the register to be eliminated.
322 We cannot simply compare the number since
323 we might then spuriously replace a hard
324 register corresponding to a pseudo
325 assigned to the reg to be eliminated. */
326 rtx to_rtx; /* REG rtx for the replacement. */
327 };
328
329 static struct elim_table *reg_eliminate = 0;
330
331 /* This is an intermediate structure to initialize the table. It has
332 exactly the members provided by ELIMINABLE_REGS. */
333 static const struct elim_table_1
334 {
335 const int from;
336 const int to;
337 } reg_eliminate_1[] =
338
339 /* If a set of eliminable registers was specified, define the table from it.
340 Otherwise, default to the normal case of the frame pointer being
341 replaced by the stack pointer. */
342
343 #ifdef ELIMINABLE_REGS
344 ELIMINABLE_REGS;
345 #else
346 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
347 #endif
348
349 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
350
351 /* Record the number of pending eliminations that have an offset not equal
352 to their initial offset. If nonzero, we use a new copy of each
353 replacement result in any insns encountered. */
354 int num_not_at_initial_offset;
355
356 /* Count the number of registers that we may be able to eliminate. */
357 static int num_eliminable;
358 /* And the number of registers that are equivalent to a constant that
359 can be eliminated to frame_pointer / arg_pointer + constant. */
360 static int num_eliminable_invariants;
361
362 /* For each label, we record the offset of each elimination. If we reach
363 a label by more than one path and an offset differs, we cannot do the
364 elimination. This information is indexed by the difference of the
365 number of the label and the first label number. We can't offset the
366 pointer itself as this can cause problems on machines with segmented
367 memory. The first table is an array of flags that records whether we
368 have yet encountered a label and the second table is an array of arrays,
369 one entry in the latter array for each elimination. */
370
371 static int first_label_num;
372 static char *offsets_known_at;
373 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
374
375 /* Number of labels in the current function. */
376
377 static int num_labels;
378
379 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
380 static void maybe_fix_stack_asms (void);
381 static void copy_reloads (struct insn_chain *);
382 static void calculate_needs_all_insns (int);
383 static int find_reg (struct insn_chain *, int);
384 static void find_reload_regs (struct insn_chain *);
385 static void select_reload_regs (void);
386 static void delete_caller_save_insns (void);
387
388 static void spill_failure (rtx, enum reg_class);
389 static void count_spilled_pseudo (int, int, int);
390 static void delete_dead_insn (rtx);
391 static void alter_reg (int, int);
392 static void set_label_offsets (rtx, rtx, int);
393 static void check_eliminable_occurrences (rtx);
394 static void elimination_effects (rtx, enum machine_mode);
395 static int eliminate_regs_in_insn (rtx, int);
396 static void update_eliminable_offsets (void);
397 static void mark_not_eliminable (rtx, rtx, void *);
398 static void set_initial_elim_offsets (void);
399 static bool verify_initial_elim_offsets (void);
400 static void set_initial_label_offsets (void);
401 static void set_offsets_for_label (rtx);
402 static void init_elim_table (void);
403 static void update_eliminables (HARD_REG_SET *);
404 static void spill_hard_reg (unsigned int, int);
405 static int finish_spills (int);
406 static void scan_paradoxical_subregs (rtx);
407 static void count_pseudo (int);
408 static void order_regs_for_reload (struct insn_chain *);
409 static void reload_as_needed (int);
410 static void forget_old_reloads_1 (rtx, rtx, void *);
411 static void forget_marked_reloads (regset);
412 static int reload_reg_class_lower (const void *, const void *);
413 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
414 enum machine_mode);
415 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
416 enum machine_mode);
417 static int reload_reg_free_p (unsigned int, int, enum reload_type);
418 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
419 rtx, rtx, int, int);
420 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
421 rtx, rtx, int, int);
422 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
423 static int allocate_reload_reg (struct insn_chain *, int, int);
424 static int conflicts_with_override (rtx);
425 static void failed_reload (rtx, int);
426 static int set_reload_reg (int, int);
427 static void choose_reload_regs_init (struct insn_chain *, rtx *);
428 static void choose_reload_regs (struct insn_chain *);
429 static void merge_assigned_reloads (rtx);
430 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
431 rtx, int);
432 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
433 int);
434 static void do_input_reload (struct insn_chain *, struct reload *, int);
435 static void do_output_reload (struct insn_chain *, struct reload *, int);
436 static bool inherit_piecemeal_p (int, int);
437 static void emit_reload_insns (struct insn_chain *);
438 static void delete_output_reload (rtx, int, int);
439 static void delete_address_reloads (rtx, rtx);
440 static void delete_address_reloads_1 (rtx, rtx, rtx);
441 static rtx inc_for_reload (rtx, rtx, rtx, int);
442 #ifdef AUTO_INC_DEC
443 static void add_auto_inc_notes (rtx, rtx);
444 #endif
445 static void copy_eh_notes (rtx, rtx);
446 static int reloads_conflict (int, int);
447 static rtx gen_reload (rtx, rtx, int, enum reload_type);
448 static rtx emit_insn_if_valid_for_reload (rtx);
449
450 /* Initialize the reload pass once per compilation. */
451
452 void
init_reload(void)453 init_reload (void)
454 {
455 int i;
456
457 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
458 Set spill_indirect_levels to the number of levels such addressing is
459 permitted, zero if it is not permitted at all. */
460
461 rtx tem
462 = gen_rtx_MEM (Pmode,
463 gen_rtx_PLUS (Pmode,
464 gen_rtx_REG (Pmode,
465 LAST_VIRTUAL_REGISTER + 1),
466 GEN_INT (4)));
467 spill_indirect_levels = 0;
468
469 while (memory_address_p (QImode, tem))
470 {
471 spill_indirect_levels++;
472 tem = gen_rtx_MEM (Pmode, tem);
473 }
474
475 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
476
477 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
478 indirect_symref_ok = memory_address_p (QImode, tem);
479
480 /* See if reg+reg is a valid (and offsettable) address. */
481
482 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
483 {
484 tem = gen_rtx_PLUS (Pmode,
485 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
486 gen_rtx_REG (Pmode, i));
487
488 /* This way, we make sure that reg+reg is an offsettable address. */
489 tem = plus_constant (tem, 4);
490
491 if (memory_address_p (QImode, tem))
492 {
493 double_reg_address_ok = 1;
494 break;
495 }
496 }
497
498 /* Initialize obstack for our rtl allocation. */
499 gcc_obstack_init (&reload_obstack);
500 reload_startobj = obstack_alloc (&reload_obstack, 0);
501
502 INIT_REG_SET (&spilled_pseudos);
503 INIT_REG_SET (&pseudos_counted);
504 }
505
506 /* List of insn chains that are currently unused. */
507 static struct insn_chain *unused_insn_chains = 0;
508
509 /* Allocate an empty insn_chain structure. */
510 struct insn_chain *
new_insn_chain(void)511 new_insn_chain (void)
512 {
513 struct insn_chain *c;
514
515 if (unused_insn_chains == 0)
516 {
517 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
518 INIT_REG_SET (&c->live_throughout);
519 INIT_REG_SET (&c->dead_or_set);
520 }
521 else
522 {
523 c = unused_insn_chains;
524 unused_insn_chains = c->next;
525 }
526 c->is_caller_save_insn = 0;
527 c->need_operand_change = 0;
528 c->need_reload = 0;
529 c->need_elim = 0;
530 return c;
531 }
532
533 /* Small utility function to set all regs in hard reg set TO which are
534 allocated to pseudos in regset FROM. */
535
536 void
compute_use_by_pseudos(HARD_REG_SET * to,regset from)537 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
538 {
539 unsigned int regno;
540 reg_set_iterator rsi;
541
542 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
543 {
544 int r = reg_renumber[regno];
545 int nregs;
546
547 if (r < 0)
548 {
549 /* reload_combine uses the information from
550 BASIC_BLOCK->global_live_at_start, which might still
551 contain registers that have not actually been allocated
552 since they have an equivalence. */
553 gcc_assert (reload_completed);
554 }
555 else
556 {
557 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)];
558 while (nregs-- > 0)
559 SET_HARD_REG_BIT (*to, r + nregs);
560 }
561 }
562 }
563
564 /* Replace all pseudos found in LOC with their corresponding
565 equivalences. */
566
567 static void
replace_pseudos_in(rtx * loc,enum machine_mode mem_mode,rtx usage)568 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
569 {
570 rtx x = *loc;
571 enum rtx_code code;
572 const char *fmt;
573 int i, j;
574
575 if (! x)
576 return;
577
578 code = GET_CODE (x);
579 if (code == REG)
580 {
581 unsigned int regno = REGNO (x);
582
583 if (regno < FIRST_PSEUDO_REGISTER)
584 return;
585
586 x = eliminate_regs (x, mem_mode, usage);
587 if (x != *loc)
588 {
589 *loc = x;
590 replace_pseudos_in (loc, mem_mode, usage);
591 return;
592 }
593
594 if (reg_equiv_constant[regno])
595 *loc = reg_equiv_constant[regno];
596 else if (reg_equiv_mem[regno])
597 *loc = reg_equiv_mem[regno];
598 else if (reg_equiv_address[regno])
599 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
600 else
601 {
602 gcc_assert (!REG_P (regno_reg_rtx[regno])
603 || REGNO (regno_reg_rtx[regno]) != regno);
604 *loc = regno_reg_rtx[regno];
605 }
606
607 return;
608 }
609 else if (code == MEM)
610 {
611 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
612 return;
613 }
614
615 /* Process each of our operands recursively. */
616 fmt = GET_RTX_FORMAT (code);
617 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
618 if (*fmt == 'e')
619 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
620 else if (*fmt == 'E')
621 for (j = 0; j < XVECLEN (x, i); j++)
622 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
623 }
624
625
626 /* Global variables used by reload and its subroutines. */
627
628 /* Set during calculate_needs if an insn needs register elimination. */
629 static int something_needs_elimination;
630 /* Set during calculate_needs if an insn needs an operand changed. */
631 static int something_needs_operands_changed;
632
633 /* Nonzero means we couldn't get enough spill regs. */
634 static int failure;
635
636 /* Main entry point for the reload pass.
637
638 FIRST is the first insn of the function being compiled.
639
640 GLOBAL nonzero means we were called from global_alloc
641 and should attempt to reallocate any pseudoregs that we
642 displace from hard regs we will use for reloads.
643 If GLOBAL is zero, we do not have enough information to do that,
644 so any pseudo reg that is spilled must go to the stack.
645
646 Return value is nonzero if reload failed
647 and we must not do any more for this function. */
648
649 int
reload(rtx first,int global)650 reload (rtx first, int global)
651 {
652 int i;
653 rtx insn;
654 struct elim_table *ep;
655 basic_block bb;
656
657 /* Make sure even insns with volatile mem refs are recognizable. */
658 init_recog ();
659
660 failure = 0;
661
662 reload_firstobj = obstack_alloc (&reload_obstack, 0);
663
664 /* Make sure that the last insn in the chain
665 is not something that needs reloading. */
666 emit_note (NOTE_INSN_DELETED);
667
668 /* Enable find_equiv_reg to distinguish insns made by reload. */
669 reload_first_uid = get_max_uid ();
670
671 #ifdef SECONDARY_MEMORY_NEEDED
672 /* Initialize the secondary memory table. */
673 clear_secondary_mem ();
674 #endif
675
676 /* We don't have a stack slot for any spill reg yet. */
677 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
678 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
679
680 /* Initialize the save area information for caller-save, in case some
681 are needed. */
682 init_save_areas ();
683
684 /* Compute which hard registers are now in use
685 as homes for pseudo registers.
686 This is done here rather than (eg) in global_alloc
687 because this point is reached even if not optimizing. */
688 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
689 mark_home_live (i);
690
691 /* A function that receives a nonlocal goto must save all call-saved
692 registers. */
693 if (current_function_has_nonlocal_label)
694 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
695 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
696 regs_ever_live[i] = 1;
697
698 /* Find all the pseudo registers that didn't get hard regs
699 but do have known equivalent constants or memory slots.
700 These include parameters (known equivalent to parameter slots)
701 and cse'd or loop-moved constant memory addresses.
702
703 Record constant equivalents in reg_equiv_constant
704 so they will be substituted by find_reloads.
705 Record memory equivalents in reg_mem_equiv so they can
706 be substituted eventually by altering the REG-rtx's. */
707
708 reg_equiv_constant = XCNEWVEC (rtx, max_regno);
709 reg_equiv_invariant = XCNEWVEC (rtx, max_regno);
710 reg_equiv_mem = XCNEWVEC (rtx, max_regno);
711 reg_equiv_alt_mem_list = XCNEWVEC (rtx, max_regno);
712 reg_equiv_address = XCNEWVEC (rtx, max_regno);
713 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
714 reg_old_renumber = XCNEWVEC (short, max_regno);
715 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
716 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
717 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
718
719 CLEAR_HARD_REG_SET (bad_spill_regs_global);
720
721 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
722 to. Also find all paradoxical subregs and find largest such for
723 each pseudo. */
724
725 num_eliminable_invariants = 0;
726 for (insn = first; insn; insn = NEXT_INSN (insn))
727 {
728 rtx set = single_set (insn);
729
730 /* We may introduce USEs that we want to remove at the end, so
731 we'll mark them with QImode. Make sure there are no
732 previously-marked insns left by say regmove. */
733 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
734 && GET_MODE (insn) != VOIDmode)
735 PUT_MODE (insn, VOIDmode);
736
737 if (INSN_P (insn))
738 scan_paradoxical_subregs (PATTERN (insn));
739
740 if (set != 0 && REG_P (SET_DEST (set)))
741 {
742 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
743 rtx x;
744
745 if (! note)
746 continue;
747
748 i = REGNO (SET_DEST (set));
749 x = XEXP (note, 0);
750
751 if (i <= LAST_VIRTUAL_REGISTER)
752 continue;
753
754 if (! function_invariant_p (x)
755 || ! flag_pic
756 /* A function invariant is often CONSTANT_P but may
757 include a register. We promise to only pass
758 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
759 || (CONSTANT_P (x)
760 && LEGITIMATE_PIC_OPERAND_P (x)))
761 {
762 /* It can happen that a REG_EQUIV note contains a MEM
763 that is not a legitimate memory operand. As later
764 stages of reload assume that all addresses found
765 in the reg_equiv_* arrays were originally legitimate,
766 we ignore such REG_EQUIV notes. */
767 if (memory_operand (x, VOIDmode))
768 {
769 /* Always unshare the equivalence, so we can
770 substitute into this insn without touching the
771 equivalence. */
772 reg_equiv_memory_loc[i] = copy_rtx (x);
773 }
774 else if (function_invariant_p (x))
775 {
776 if (GET_CODE (x) == PLUS)
777 {
778 /* This is PLUS of frame pointer and a constant,
779 and might be shared. Unshare it. */
780 reg_equiv_invariant[i] = copy_rtx (x);
781 num_eliminable_invariants++;
782 }
783 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
784 {
785 reg_equiv_invariant[i] = x;
786 num_eliminable_invariants++;
787 }
788 else if (LEGITIMATE_CONSTANT_P (x))
789 reg_equiv_constant[i] = x;
790 else
791 {
792 reg_equiv_memory_loc[i]
793 = force_const_mem (GET_MODE (SET_DEST (set)), x);
794 if (! reg_equiv_memory_loc[i])
795 reg_equiv_init[i] = NULL_RTX;
796 }
797 }
798 else
799 {
800 reg_equiv_init[i] = NULL_RTX;
801 continue;
802 }
803 }
804 else
805 reg_equiv_init[i] = NULL_RTX;
806 }
807 }
808
809 if (dump_file)
810 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
811 if (reg_equiv_init[i])
812 {
813 fprintf (dump_file, "init_insns for %u: ", i);
814 print_inline_rtx (dump_file, reg_equiv_init[i], 20);
815 fprintf (dump_file, "\n");
816 }
817
818 init_elim_table ();
819
820 first_label_num = get_first_label_num ();
821 num_labels = max_label_num () - first_label_num;
822
823 /* Allocate the tables used to store offset information at labels. */
824 /* We used to use alloca here, but the size of what it would try to
825 allocate would occasionally cause it to exceed the stack limit and
826 cause a core dump. */
827 offsets_known_at = XNEWVEC (char, num_labels);
828 offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
829
830 /* Alter each pseudo-reg rtx to contain its hard reg number.
831 Assign stack slots to the pseudos that lack hard regs or equivalents.
832 Do not touch virtual registers. */
833
834 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
835 alter_reg (i, -1);
836
837 /* If we have some registers we think can be eliminated, scan all insns to
838 see if there is an insn that sets one of these registers to something
839 other than itself plus a constant. If so, the register cannot be
840 eliminated. Doing this scan here eliminates an extra pass through the
841 main reload loop in the most common case where register elimination
842 cannot be done. */
843 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
844 if (INSN_P (insn))
845 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
846
847 maybe_fix_stack_asms ();
848
849 insns_need_reload = 0;
850 something_needs_elimination = 0;
851
852 /* Initialize to -1, which means take the first spill register. */
853 last_spill_reg = -1;
854
855 /* Spill any hard regs that we know we can't eliminate. */
856 CLEAR_HARD_REG_SET (used_spill_regs);
857 /* There can be multiple ways to eliminate a register;
858 they should be listed adjacently.
859 Elimination for any register fails only if all possible ways fail. */
860 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
861 {
862 int from = ep->from;
863 int can_eliminate = 0;
864 do
865 {
866 can_eliminate |= ep->can_eliminate;
867 ep++;
868 }
869 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
870 if (! can_eliminate)
871 spill_hard_reg (from, 1);
872 }
873
874 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
875 if (frame_pointer_needed)
876 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
877 #endif
878 finish_spills (global);
879
880 /* From now on, we may need to generate moves differently. We may also
881 allow modifications of insns which cause them to not be recognized.
882 Any such modifications will be cleaned up during reload itself. */
883 reload_in_progress = 1;
884
885 /* This loop scans the entire function each go-round
886 and repeats until one repetition spills no additional hard regs. */
887 for (;;)
888 {
889 int something_changed;
890 int did_spill;
891
892 HOST_WIDE_INT starting_frame_size;
893
894 /* Round size of stack frame to stack_alignment_needed. This must be done
895 here because the stack size may be a part of the offset computation
896 for register elimination, and there might have been new stack slots
897 created in the last iteration of this loop. */
898 if (cfun->stack_alignment_needed)
899 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
900
901 starting_frame_size = get_frame_size ();
902
903 set_initial_elim_offsets ();
904 set_initial_label_offsets ();
905
906 /* For each pseudo register that has an equivalent location defined,
907 try to eliminate any eliminable registers (such as the frame pointer)
908 assuming initial offsets for the replacement register, which
909 is the normal case.
910
911 If the resulting location is directly addressable, substitute
912 the MEM we just got directly for the old REG.
913
914 If it is not addressable but is a constant or the sum of a hard reg
915 and constant, it is probably not addressable because the constant is
916 out of range, in that case record the address; we will generate
917 hairy code to compute the address in a register each time it is
918 needed. Similarly if it is a hard register, but one that is not
919 valid as an address register.
920
921 If the location is not addressable, but does not have one of the
922 above forms, assign a stack slot. We have to do this to avoid the
923 potential of producing lots of reloads if, e.g., a location involves
924 a pseudo that didn't get a hard register and has an equivalent memory
925 location that also involves a pseudo that didn't get a hard register.
926
927 Perhaps at some point we will improve reload_when_needed handling
928 so this problem goes away. But that's very hairy. */
929
930 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
931 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
932 {
933 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
934
935 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
936 XEXP (x, 0)))
937 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
938 else if (CONSTANT_P (XEXP (x, 0))
939 || (REG_P (XEXP (x, 0))
940 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
941 || (GET_CODE (XEXP (x, 0)) == PLUS
942 && REG_P (XEXP (XEXP (x, 0), 0))
943 && (REGNO (XEXP (XEXP (x, 0), 0))
944 < FIRST_PSEUDO_REGISTER)
945 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
946 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
947 else
948 {
949 /* Make a new stack slot. Then indicate that something
950 changed so we go back and recompute offsets for
951 eliminable registers because the allocation of memory
952 below might change some offset. reg_equiv_{mem,address}
953 will be set up for this pseudo on the next pass around
954 the loop. */
955 reg_equiv_memory_loc[i] = 0;
956 reg_equiv_init[i] = 0;
957 alter_reg (i, -1);
958 }
959 }
960
961 if (caller_save_needed)
962 setup_save_areas ();
963
964 /* If we allocated another stack slot, redo elimination bookkeeping. */
965 if (starting_frame_size != get_frame_size ())
966 continue;
967
968 if (caller_save_needed)
969 {
970 save_call_clobbered_regs ();
971 /* That might have allocated new insn_chain structures. */
972 reload_firstobj = obstack_alloc (&reload_obstack, 0);
973 }
974
975 calculate_needs_all_insns (global);
976
977 CLEAR_REG_SET (&spilled_pseudos);
978 did_spill = 0;
979
980 something_changed = 0;
981
982 /* If we allocated any new memory locations, make another pass
983 since it might have changed elimination offsets. */
984 if (starting_frame_size != get_frame_size ())
985 something_changed = 1;
986
987 /* Even if the frame size remained the same, we might still have
988 changed elimination offsets, e.g. if find_reloads called
989 force_const_mem requiring the back end to allocate a constant
990 pool base register that needs to be saved on the stack. */
991 else if (!verify_initial_elim_offsets ())
992 something_changed = 1;
993
994 {
995 HARD_REG_SET to_spill;
996 CLEAR_HARD_REG_SET (to_spill);
997 update_eliminables (&to_spill);
998 AND_COMPL_HARD_REG_SET(used_spill_regs, to_spill);
999
1000 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1001 if (TEST_HARD_REG_BIT (to_spill, i))
1002 {
1003 spill_hard_reg (i, 1);
1004 did_spill = 1;
1005
1006 /* Regardless of the state of spills, if we previously had
1007 a register that we thought we could eliminate, but now can
1008 not eliminate, we must run another pass.
1009
1010 Consider pseudos which have an entry in reg_equiv_* which
1011 reference an eliminable register. We must make another pass
1012 to update reg_equiv_* so that we do not substitute in the
1013 old value from when we thought the elimination could be
1014 performed. */
1015 something_changed = 1;
1016 }
1017 }
1018
1019 select_reload_regs ();
1020 if (failure)
1021 goto failed;
1022
1023 if (insns_need_reload != 0 || did_spill)
1024 something_changed |= finish_spills (global);
1025
1026 if (! something_changed)
1027 break;
1028
1029 if (caller_save_needed)
1030 delete_caller_save_insns ();
1031
1032 obstack_free (&reload_obstack, reload_firstobj);
1033 }
1034
1035 /* If global-alloc was run, notify it of any register eliminations we have
1036 done. */
1037 if (global)
1038 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1039 if (ep->can_eliminate)
1040 mark_elimination (ep->from, ep->to);
1041
1042 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1043 If that insn didn't set the register (i.e., it copied the register to
1044 memory), just delete that insn instead of the equivalencing insn plus
1045 anything now dead. If we call delete_dead_insn on that insn, we may
1046 delete the insn that actually sets the register if the register dies
1047 there and that is incorrect. */
1048
1049 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1050 {
1051 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1052 {
1053 rtx list;
1054 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1055 {
1056 rtx equiv_insn = XEXP (list, 0);
1057
1058 /* If we already deleted the insn or if it may trap, we can't
1059 delete it. The latter case shouldn't happen, but can
1060 if an insn has a variable address, gets a REG_EH_REGION
1061 note added to it, and then gets converted into a load
1062 from a constant address. */
1063 if (NOTE_P (equiv_insn)
1064 || can_throw_internal (equiv_insn))
1065 ;
1066 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1067 delete_dead_insn (equiv_insn);
1068 else
1069 SET_INSN_DELETED (equiv_insn);
1070 }
1071 }
1072 }
1073
1074 /* Use the reload registers where necessary
1075 by generating move instructions to move the must-be-register
1076 values into or out of the reload registers. */
1077
1078 if (insns_need_reload != 0 || something_needs_elimination
1079 || something_needs_operands_changed)
1080 {
1081 HOST_WIDE_INT old_frame_size = get_frame_size ();
1082
1083 reload_as_needed (global);
1084
1085 gcc_assert (old_frame_size == get_frame_size ());
1086
1087 gcc_assert (verify_initial_elim_offsets ());
1088 }
1089
1090 /* If we were able to eliminate the frame pointer, show that it is no
1091 longer live at the start of any basic block. If it ls live by
1092 virtue of being in a pseudo, that pseudo will be marked live
1093 and hence the frame pointer will be known to be live via that
1094 pseudo. */
1095
1096 if (! frame_pointer_needed)
1097 FOR_EACH_BB (bb)
1098 CLEAR_REGNO_REG_SET (bb->il.rtl->global_live_at_start,
1099 HARD_FRAME_POINTER_REGNUM);
1100
1101 /* Come here (with failure set nonzero) if we can't get enough spill
1102 regs. */
1103 failed:
1104
1105 CLEAR_REG_SET (&spilled_pseudos);
1106 reload_in_progress = 0;
1107
1108 /* Now eliminate all pseudo regs by modifying them into
1109 their equivalent memory references.
1110 The REG-rtx's for the pseudos are modified in place,
1111 so all insns that used to refer to them now refer to memory.
1112
1113 For a reg that has a reg_equiv_address, all those insns
1114 were changed by reloading so that no insns refer to it any longer;
1115 but the DECL_RTL of a variable decl may refer to it,
1116 and if so this causes the debugging info to mention the variable. */
1117
1118 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1119 {
1120 rtx addr = 0;
1121
1122 if (reg_equiv_mem[i])
1123 addr = XEXP (reg_equiv_mem[i], 0);
1124
1125 if (reg_equiv_address[i])
1126 addr = reg_equiv_address[i];
1127
1128 if (addr)
1129 {
1130 if (reg_renumber[i] < 0)
1131 {
1132 rtx reg = regno_reg_rtx[i];
1133
1134 REG_USERVAR_P (reg) = 0;
1135 PUT_CODE (reg, MEM);
1136 XEXP (reg, 0) = addr;
1137 if (reg_equiv_memory_loc[i])
1138 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1139 else
1140 {
1141 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1142 MEM_ATTRS (reg) = 0;
1143 }
1144 MEM_NOTRAP_P (reg) = 1;
1145 }
1146 else if (reg_equiv_mem[i])
1147 XEXP (reg_equiv_mem[i], 0) = addr;
1148 }
1149 }
1150
1151 /* We must set reload_completed now since the cleanup_subreg_operands call
1152 below will re-recognize each insn and reload may have generated insns
1153 which are only valid during and after reload. */
1154 reload_completed = 1;
1155
1156 /* Make a pass over all the insns and delete all USEs which we inserted
1157 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1158 notes. Delete all CLOBBER insns, except those that refer to the return
1159 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1160 from misarranging variable-array code, and simplify (subreg (reg))
1161 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1162 are no longer useful or accurate. Strip and regenerate REG_INC notes
1163 that may have been moved around. */
1164
1165 for (insn = first; insn; insn = NEXT_INSN (insn))
1166 if (INSN_P (insn))
1167 {
1168 rtx *pnote;
1169
1170 if (CALL_P (insn))
1171 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1172 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1173
1174 if ((GET_CODE (PATTERN (insn)) == USE
1175 /* We mark with QImode USEs introduced by reload itself. */
1176 && (GET_MODE (insn) == QImode
1177 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1178 || (GET_CODE (PATTERN (insn)) == CLOBBER
1179 && (!MEM_P (XEXP (PATTERN (insn), 0))
1180 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1181 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1182 && XEXP (XEXP (PATTERN (insn), 0), 0)
1183 != stack_pointer_rtx))
1184 && (!REG_P (XEXP (PATTERN (insn), 0))
1185 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1186 {
1187 delete_insn (insn);
1188 continue;
1189 }
1190
1191 /* Some CLOBBERs may survive until here and still reference unassigned
1192 pseudos with const equivalent, which may in turn cause ICE in later
1193 passes if the reference remains in place. */
1194 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1195 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1196 VOIDmode, PATTERN (insn));
1197
1198 /* Discard obvious no-ops, even without -O. This optimization
1199 is fast and doesn't interfere with debugging. */
1200 if (NONJUMP_INSN_P (insn)
1201 && GET_CODE (PATTERN (insn)) == SET
1202 && REG_P (SET_SRC (PATTERN (insn)))
1203 && REG_P (SET_DEST (PATTERN (insn)))
1204 && (REGNO (SET_SRC (PATTERN (insn)))
1205 == REGNO (SET_DEST (PATTERN (insn)))))
1206 {
1207 delete_insn (insn);
1208 continue;
1209 }
1210
1211 pnote = ®_NOTES (insn);
1212 while (*pnote != 0)
1213 {
1214 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1215 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1216 || REG_NOTE_KIND (*pnote) == REG_INC
1217 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1218 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1219 *pnote = XEXP (*pnote, 1);
1220 else
1221 pnote = &XEXP (*pnote, 1);
1222 }
1223
1224 #ifdef AUTO_INC_DEC
1225 add_auto_inc_notes (insn, PATTERN (insn));
1226 #endif
1227
1228 /* Simplify (subreg (reg)) if it appears as an operand. */
1229 cleanup_subreg_operands (insn);
1230
1231 /* Clean up invalid ASMs so that they don't confuse later passes.
1232 See PR 21299. */
1233 if (asm_noperands (PATTERN (insn)) >= 0)
1234 {
1235 extract_insn (insn);
1236 if (!constrain_operands (1))
1237 {
1238 error_for_asm (insn,
1239 "%<asm%> operand has impossible constraints");
1240 delete_insn (insn);
1241 continue;
1242 }
1243 }
1244 }
1245
1246 /* If we are doing stack checking, give a warning if this function's
1247 frame size is larger than we expect. */
1248 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1249 {
1250 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1251 static int verbose_warned = 0;
1252
1253 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1254 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1255 size += UNITS_PER_WORD;
1256
1257 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1258 {
1259 warning (0, "frame size too large for reliable stack checking");
1260 if (! verbose_warned)
1261 {
1262 warning (0, "try reducing the number of local variables");
1263 verbose_warned = 1;
1264 }
1265 }
1266 }
1267
1268 /* Indicate that we no longer have known memory locations or constants. */
1269 if (reg_equiv_constant)
1270 free (reg_equiv_constant);
1271 if (reg_equiv_invariant)
1272 free (reg_equiv_invariant);
1273 reg_equiv_constant = 0;
1274 reg_equiv_invariant = 0;
1275 VEC_free (rtx, gc, reg_equiv_memory_loc_vec);
1276 reg_equiv_memory_loc = 0;
1277
1278 if (offsets_known_at)
1279 free (offsets_known_at);
1280 if (offsets_at)
1281 free (offsets_at);
1282
1283 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1284 if (reg_equiv_alt_mem_list[i])
1285 free_EXPR_LIST_list (®_equiv_alt_mem_list[i]);
1286 free (reg_equiv_alt_mem_list);
1287
1288 free (reg_equiv_mem);
1289 reg_equiv_init = 0;
1290 free (reg_equiv_address);
1291 free (reg_max_ref_width);
1292 free (reg_old_renumber);
1293 free (pseudo_previous_regs);
1294 free (pseudo_forbidden_regs);
1295
1296 CLEAR_HARD_REG_SET (used_spill_regs);
1297 for (i = 0; i < n_spills; i++)
1298 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1299
1300 /* Free all the insn_chain structures at once. */
1301 obstack_free (&reload_obstack, reload_startobj);
1302 unused_insn_chains = 0;
1303 fixup_abnormal_edges ();
1304
1305 /* Replacing pseudos with their memory equivalents might have
1306 created shared rtx. Subsequent passes would get confused
1307 by this, so unshare everything here. */
1308 unshare_all_rtl_again (first);
1309
1310 #ifdef STACK_BOUNDARY
1311 /* init_emit has set the alignment of the hard frame pointer
1312 to STACK_BOUNDARY. It is very likely no longer valid if
1313 the hard frame pointer was used for register allocation. */
1314 if (!frame_pointer_needed)
1315 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1316 #endif
1317
1318 return failure;
1319 }
1320
1321 /* Yet another special case. Unfortunately, reg-stack forces people to
1322 write incorrect clobbers in asm statements. These clobbers must not
1323 cause the register to appear in bad_spill_regs, otherwise we'll call
1324 fatal_insn later. We clear the corresponding regnos in the live
1325 register sets to avoid this.
1326 The whole thing is rather sick, I'm afraid. */
1327
1328 static void
maybe_fix_stack_asms(void)1329 maybe_fix_stack_asms (void)
1330 {
1331 #ifdef STACK_REGS
1332 const char *constraints[MAX_RECOG_OPERANDS];
1333 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1334 struct insn_chain *chain;
1335
1336 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1337 {
1338 int i, noperands;
1339 HARD_REG_SET clobbered, allowed;
1340 rtx pat;
1341
1342 if (! INSN_P (chain->insn)
1343 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1344 continue;
1345 pat = PATTERN (chain->insn);
1346 if (GET_CODE (pat) != PARALLEL)
1347 continue;
1348
1349 CLEAR_HARD_REG_SET (clobbered);
1350 CLEAR_HARD_REG_SET (allowed);
1351
1352 /* First, make a mask of all stack regs that are clobbered. */
1353 for (i = 0; i < XVECLEN (pat, 0); i++)
1354 {
1355 rtx t = XVECEXP (pat, 0, i);
1356 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1357 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1358 }
1359
1360 /* Get the operand values and constraints out of the insn. */
1361 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1362 constraints, operand_mode);
1363
1364 /* For every operand, see what registers are allowed. */
1365 for (i = 0; i < noperands; i++)
1366 {
1367 const char *p = constraints[i];
1368 /* For every alternative, we compute the class of registers allowed
1369 for reloading in CLS, and merge its contents into the reg set
1370 ALLOWED. */
1371 int cls = (int) NO_REGS;
1372
1373 for (;;)
1374 {
1375 char c = *p;
1376
1377 if (c == '\0' || c == ',' || c == '#')
1378 {
1379 /* End of one alternative - mark the regs in the current
1380 class, and reset the class. */
1381 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1382 cls = NO_REGS;
1383 p++;
1384 if (c == '#')
1385 do {
1386 c = *p++;
1387 } while (c != '\0' && c != ',');
1388 if (c == '\0')
1389 break;
1390 continue;
1391 }
1392
1393 switch (c)
1394 {
1395 case '=': case '+': case '*': case '%': case '?': case '!':
1396 case '0': case '1': case '2': case '3': case '4': case 'm':
1397 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1398 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1399 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1400 case 'P':
1401 break;
1402
1403 case 'p':
1404 cls = (int) reg_class_subunion[cls]
1405 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1406 break;
1407
1408 case 'g':
1409 case 'r':
1410 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1411 break;
1412
1413 default:
1414 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1415 cls = (int) reg_class_subunion[cls]
1416 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1417 else
1418 cls = (int) reg_class_subunion[cls]
1419 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1420 }
1421 p += CONSTRAINT_LEN (c, p);
1422 }
1423 }
1424 /* Those of the registers which are clobbered, but allowed by the
1425 constraints, must be usable as reload registers. So clear them
1426 out of the life information. */
1427 AND_HARD_REG_SET (allowed, clobbered);
1428 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1429 if (TEST_HARD_REG_BIT (allowed, i))
1430 {
1431 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1432 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1433 }
1434 }
1435
1436 #endif
1437 }
1438
1439 /* Copy the global variables n_reloads and rld into the corresponding elts
1440 of CHAIN. */
1441 static void
copy_reloads(struct insn_chain * chain)1442 copy_reloads (struct insn_chain *chain)
1443 {
1444 chain->n_reloads = n_reloads;
1445 chain->rld = obstack_alloc (&reload_obstack,
1446 n_reloads * sizeof (struct reload));
1447 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1448 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1449 }
1450
1451 /* Walk the chain of insns, and determine for each whether it needs reloads
1452 and/or eliminations. Build the corresponding insns_need_reload list, and
1453 set something_needs_elimination as appropriate. */
1454 static void
calculate_needs_all_insns(int global)1455 calculate_needs_all_insns (int global)
1456 {
1457 struct insn_chain **pprev_reload = &insns_need_reload;
1458 struct insn_chain *chain, *next = 0;
1459
1460 something_needs_elimination = 0;
1461
1462 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1463 for (chain = reload_insn_chain; chain != 0; chain = next)
1464 {
1465 rtx insn = chain->insn;
1466
1467 next = chain->next;
1468
1469 /* Clear out the shortcuts. */
1470 chain->n_reloads = 0;
1471 chain->need_elim = 0;
1472 chain->need_reload = 0;
1473 chain->need_operand_change = 0;
1474
1475 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1476 include REG_LABEL), we need to see what effects this has on the
1477 known offsets at labels. */
1478
1479 if (LABEL_P (insn) || JUMP_P (insn)
1480 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1481 set_label_offsets (insn, insn, 0);
1482
1483 if (INSN_P (insn))
1484 {
1485 rtx old_body = PATTERN (insn);
1486 int old_code = INSN_CODE (insn);
1487 rtx old_notes = REG_NOTES (insn);
1488 int did_elimination = 0;
1489 int operands_changed = 0;
1490 rtx set = single_set (insn);
1491
1492 /* Skip insns that only set an equivalence. */
1493 if (set && REG_P (SET_DEST (set))
1494 && reg_renumber[REGNO (SET_DEST (set))] < 0
1495 && (reg_equiv_constant[REGNO (SET_DEST (set))]
1496 || (reg_equiv_invariant[REGNO (SET_DEST (set))]))
1497 && reg_equiv_init[REGNO (SET_DEST (set))])
1498 continue;
1499
1500 /* If needed, eliminate any eliminable registers. */
1501 if (num_eliminable || num_eliminable_invariants)
1502 did_elimination = eliminate_regs_in_insn (insn, 0);
1503
1504 /* Analyze the instruction. */
1505 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1506 global, spill_reg_order);
1507
1508 /* If a no-op set needs more than one reload, this is likely
1509 to be something that needs input address reloads. We
1510 can't get rid of this cleanly later, and it is of no use
1511 anyway, so discard it now.
1512 We only do this when expensive_optimizations is enabled,
1513 since this complements reload inheritance / output
1514 reload deletion, and it can make debugging harder. */
1515 if (flag_expensive_optimizations && n_reloads > 1)
1516 {
1517 rtx set = single_set (insn);
1518 if (set
1519 && SET_SRC (set) == SET_DEST (set)
1520 && REG_P (SET_SRC (set))
1521 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1522 {
1523 delete_insn (insn);
1524 /* Delete it from the reload chain. */
1525 if (chain->prev)
1526 chain->prev->next = next;
1527 else
1528 reload_insn_chain = next;
1529 if (next)
1530 next->prev = chain->prev;
1531 chain->next = unused_insn_chains;
1532 unused_insn_chains = chain;
1533 continue;
1534 }
1535 }
1536 if (num_eliminable)
1537 update_eliminable_offsets ();
1538
1539 /* Remember for later shortcuts which insns had any reloads or
1540 register eliminations. */
1541 chain->need_elim = did_elimination;
1542 chain->need_reload = n_reloads > 0;
1543 chain->need_operand_change = operands_changed;
1544
1545 /* Discard any register replacements done. */
1546 if (did_elimination)
1547 {
1548 obstack_free (&reload_obstack, reload_insn_firstobj);
1549 PATTERN (insn) = old_body;
1550 INSN_CODE (insn) = old_code;
1551 REG_NOTES (insn) = old_notes;
1552 something_needs_elimination = 1;
1553 }
1554
1555 something_needs_operands_changed |= operands_changed;
1556
1557 if (n_reloads != 0)
1558 {
1559 copy_reloads (chain);
1560 *pprev_reload = chain;
1561 pprev_reload = &chain->next_need_reload;
1562 }
1563 }
1564 }
1565 *pprev_reload = 0;
1566 }
1567
1568 /* Comparison function for qsort to decide which of two reloads
1569 should be handled first. *P1 and *P2 are the reload numbers. */
1570
1571 static int
reload_reg_class_lower(const void * r1p,const void * r2p)1572 reload_reg_class_lower (const void *r1p, const void *r2p)
1573 {
1574 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1575 int t;
1576
1577 /* Consider required reloads before optional ones. */
1578 t = rld[r1].optional - rld[r2].optional;
1579 if (t != 0)
1580 return t;
1581
1582 /* Count all solitary classes before non-solitary ones. */
1583 t = ((reg_class_size[(int) rld[r2].class] == 1)
1584 - (reg_class_size[(int) rld[r1].class] == 1));
1585 if (t != 0)
1586 return t;
1587
1588 /* Aside from solitaires, consider all multi-reg groups first. */
1589 t = rld[r2].nregs - rld[r1].nregs;
1590 if (t != 0)
1591 return t;
1592
1593 /* Consider reloads in order of increasing reg-class number. */
1594 t = (int) rld[r1].class - (int) rld[r2].class;
1595 if (t != 0)
1596 return t;
1597
1598 /* If reloads are equally urgent, sort by reload number,
1599 so that the results of qsort leave nothing to chance. */
1600 return r1 - r2;
1601 }
1602
1603 /* The cost of spilling each hard reg. */
1604 static int spill_cost[FIRST_PSEUDO_REGISTER];
1605
1606 /* When spilling multiple hard registers, we use SPILL_COST for the first
1607 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1608 only the first hard reg for a multi-reg pseudo. */
1609 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1610
1611 /* Update the spill cost arrays, considering that pseudo REG is live. */
1612
1613 static void
count_pseudo(int reg)1614 count_pseudo (int reg)
1615 {
1616 int freq = REG_FREQ (reg);
1617 int r = reg_renumber[reg];
1618 int nregs;
1619
1620 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1621 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1622 return;
1623
1624 SET_REGNO_REG_SET (&pseudos_counted, reg);
1625
1626 gcc_assert (r >= 0);
1627
1628 spill_add_cost[r] += freq;
1629
1630 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1631 while (nregs-- > 0)
1632 spill_cost[r + nregs] += freq;
1633 }
1634
1635 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1636 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1637
1638 static void
order_regs_for_reload(struct insn_chain * chain)1639 order_regs_for_reload (struct insn_chain *chain)
1640 {
1641 unsigned i;
1642 HARD_REG_SET used_by_pseudos;
1643 HARD_REG_SET used_by_pseudos2;
1644 reg_set_iterator rsi;
1645
1646 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1647
1648 memset (spill_cost, 0, sizeof spill_cost);
1649 memset (spill_add_cost, 0, sizeof spill_add_cost);
1650
1651 /* Count number of uses of each hard reg by pseudo regs allocated to it
1652 and then order them by decreasing use. First exclude hard registers
1653 that are live in or across this insn. */
1654
1655 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1656 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1657 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1658 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1659
1660 /* Now find out which pseudos are allocated to it, and update
1661 hard_reg_n_uses. */
1662 CLEAR_REG_SET (&pseudos_counted);
1663
1664 EXECUTE_IF_SET_IN_REG_SET
1665 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1666 {
1667 count_pseudo (i);
1668 }
1669 EXECUTE_IF_SET_IN_REG_SET
1670 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1671 {
1672 count_pseudo (i);
1673 }
1674 CLEAR_REG_SET (&pseudos_counted);
1675 }
1676
1677 /* Vector of reload-numbers showing the order in which the reloads should
1678 be processed. */
1679 static short reload_order[MAX_RELOADS];
1680
1681 /* This is used to keep track of the spill regs used in one insn. */
1682 static HARD_REG_SET used_spill_regs_local;
1683
1684 /* We decided to spill hard register SPILLED, which has a size of
1685 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1686 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1687 update SPILL_COST/SPILL_ADD_COST. */
1688
1689 static void
count_spilled_pseudo(int spilled,int spilled_nregs,int reg)1690 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1691 {
1692 int r = reg_renumber[reg];
1693 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1694
1695 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1696 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1697 return;
1698
1699 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1700
1701 spill_add_cost[r] -= REG_FREQ (reg);
1702 while (nregs-- > 0)
1703 spill_cost[r + nregs] -= REG_FREQ (reg);
1704 }
1705
1706 /* Find reload register to use for reload number ORDER. */
1707
1708 static int
find_reg(struct insn_chain * chain,int order)1709 find_reg (struct insn_chain *chain, int order)
1710 {
1711 int rnum = reload_order[order];
1712 struct reload *rl = rld + rnum;
1713 int best_cost = INT_MAX;
1714 int best_reg = -1;
1715 unsigned int i, j;
1716 int k;
1717 HARD_REG_SET not_usable;
1718 HARD_REG_SET used_by_other_reload;
1719 reg_set_iterator rsi;
1720
1721 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1722 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1723 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1724
1725 CLEAR_HARD_REG_SET (used_by_other_reload);
1726 for (k = 0; k < order; k++)
1727 {
1728 int other = reload_order[k];
1729
1730 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1731 for (j = 0; j < rld[other].nregs; j++)
1732 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1733 }
1734
1735 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1736 {
1737 unsigned int regno = i;
1738
1739 if (! TEST_HARD_REG_BIT (not_usable, regno)
1740 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1741 && HARD_REGNO_MODE_OK (regno, rl->mode))
1742 {
1743 int this_cost = spill_cost[regno];
1744 int ok = 1;
1745 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1746
1747 for (j = 1; j < this_nregs; j++)
1748 {
1749 this_cost += spill_add_cost[regno + j];
1750 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1751 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1752 ok = 0;
1753 }
1754 if (! ok)
1755 continue;
1756 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1757 this_cost--;
1758 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1759 this_cost--;
1760 if (this_cost < best_cost
1761 /* Among registers with equal cost, prefer caller-saved ones, or
1762 use REG_ALLOC_ORDER if it is defined. */
1763 || (this_cost == best_cost
1764 #ifdef REG_ALLOC_ORDER
1765 && (inv_reg_alloc_order[regno]
1766 < inv_reg_alloc_order[best_reg])
1767 #else
1768 && call_used_regs[regno]
1769 && ! call_used_regs[best_reg]
1770 #endif
1771 ))
1772 {
1773 best_reg = regno;
1774 best_cost = this_cost;
1775 }
1776 }
1777 }
1778 if (best_reg == -1)
1779 return 0;
1780
1781 if (dump_file)
1782 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1783
1784 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1785 rl->regno = best_reg;
1786
1787 EXECUTE_IF_SET_IN_REG_SET
1788 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1789 {
1790 count_spilled_pseudo (best_reg, rl->nregs, j);
1791 }
1792
1793 EXECUTE_IF_SET_IN_REG_SET
1794 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1795 {
1796 count_spilled_pseudo (best_reg, rl->nregs, j);
1797 }
1798
1799 for (i = 0; i < rl->nregs; i++)
1800 {
1801 gcc_assert (spill_cost[best_reg + i] == 0);
1802 gcc_assert (spill_add_cost[best_reg + i] == 0);
1803 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1804 }
1805 return 1;
1806 }
1807
1808 /* Find more reload regs to satisfy the remaining need of an insn, which
1809 is given by CHAIN.
1810 Do it by ascending class number, since otherwise a reg
1811 might be spilled for a big class and might fail to count
1812 for a smaller class even though it belongs to that class. */
1813
1814 static void
find_reload_regs(struct insn_chain * chain)1815 find_reload_regs (struct insn_chain *chain)
1816 {
1817 int i;
1818
1819 /* In order to be certain of getting the registers we need,
1820 we must sort the reloads into order of increasing register class.
1821 Then our grabbing of reload registers will parallel the process
1822 that provided the reload registers. */
1823 for (i = 0; i < chain->n_reloads; i++)
1824 {
1825 /* Show whether this reload already has a hard reg. */
1826 if (chain->rld[i].reg_rtx)
1827 {
1828 int regno = REGNO (chain->rld[i].reg_rtx);
1829 chain->rld[i].regno = regno;
1830 chain->rld[i].nregs
1831 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1832 }
1833 else
1834 chain->rld[i].regno = -1;
1835 reload_order[i] = i;
1836 }
1837
1838 n_reloads = chain->n_reloads;
1839 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1840
1841 CLEAR_HARD_REG_SET (used_spill_regs_local);
1842
1843 if (dump_file)
1844 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1845
1846 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1847
1848 /* Compute the order of preference for hard registers to spill. */
1849
1850 order_regs_for_reload (chain);
1851
1852 for (i = 0; i < n_reloads; i++)
1853 {
1854 int r = reload_order[i];
1855
1856 /* Ignore reloads that got marked inoperative. */
1857 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1858 && ! rld[r].optional
1859 && rld[r].regno == -1)
1860 if (! find_reg (chain, i))
1861 {
1862 if (dump_file)
1863 fprintf(dump_file, "reload failure for reload %d\n", r);
1864 spill_failure (chain->insn, rld[r].class);
1865 failure = 1;
1866 return;
1867 }
1868 }
1869
1870 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1871 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1872
1873 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1874 }
1875
1876 static void
select_reload_regs(void)1877 select_reload_regs (void)
1878 {
1879 struct insn_chain *chain;
1880
1881 /* Try to satisfy the needs for each insn. */
1882 for (chain = insns_need_reload; chain != 0;
1883 chain = chain->next_need_reload)
1884 find_reload_regs (chain);
1885 }
1886
1887 /* Delete all insns that were inserted by emit_caller_save_insns during
1888 this iteration. */
1889 static void
delete_caller_save_insns(void)1890 delete_caller_save_insns (void)
1891 {
1892 struct insn_chain *c = reload_insn_chain;
1893
1894 while (c != 0)
1895 {
1896 while (c != 0 && c->is_caller_save_insn)
1897 {
1898 struct insn_chain *next = c->next;
1899 rtx insn = c->insn;
1900
1901 if (c == reload_insn_chain)
1902 reload_insn_chain = next;
1903 delete_insn (insn);
1904
1905 if (next)
1906 next->prev = c->prev;
1907 if (c->prev)
1908 c->prev->next = next;
1909 c->next = unused_insn_chains;
1910 unused_insn_chains = c;
1911 c = next;
1912 }
1913 if (c != 0)
1914 c = c->next;
1915 }
1916 }
1917
1918 /* Handle the failure to find a register to spill.
1919 INSN should be one of the insns which needed this particular spill reg. */
1920
1921 static void
spill_failure(rtx insn,enum reg_class class)1922 spill_failure (rtx insn, enum reg_class class)
1923 {
1924 if (asm_noperands (PATTERN (insn)) >= 0)
1925 error_for_asm (insn, "can't find a register in class %qs while "
1926 "reloading %<asm%>",
1927 reg_class_names[class]);
1928 else
1929 {
1930 error ("unable to find a register to spill in class %qs",
1931 reg_class_names[class]);
1932
1933 if (dump_file)
1934 {
1935 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
1936 debug_reload_to_stream (dump_file);
1937 }
1938 fatal_insn ("this is the insn:", insn);
1939 }
1940 }
1941
1942 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1943 data that is dead in INSN. */
1944
1945 static void
delete_dead_insn(rtx insn)1946 delete_dead_insn (rtx insn)
1947 {
1948 rtx prev = prev_real_insn (insn);
1949 rtx prev_dest;
1950
1951 /* If the previous insn sets a register that dies in our insn, delete it
1952 too. */
1953 if (prev && GET_CODE (PATTERN (prev)) == SET
1954 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
1955 && reg_mentioned_p (prev_dest, PATTERN (insn))
1956 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1957 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1958 delete_dead_insn (prev);
1959
1960 SET_INSN_DELETED (insn);
1961 }
1962
1963 /* Modify the home of pseudo-reg I.
1964 The new home is present in reg_renumber[I].
1965
1966 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1967 or it may be -1, meaning there is none or it is not relevant.
1968 This is used so that all pseudos spilled from a given hard reg
1969 can share one stack slot. */
1970
1971 static void
alter_reg(int i,int from_reg)1972 alter_reg (int i, int from_reg)
1973 {
1974 /* When outputting an inline function, this can happen
1975 for a reg that isn't actually used. */
1976 if (regno_reg_rtx[i] == 0)
1977 return;
1978
1979 /* If the reg got changed to a MEM at rtl-generation time,
1980 ignore it. */
1981 if (!REG_P (regno_reg_rtx[i]))
1982 return;
1983
1984 /* Modify the reg-rtx to contain the new hard reg
1985 number or else to contain its pseudo reg number. */
1986 REGNO (regno_reg_rtx[i])
1987 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1988
1989 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1990 allocate a stack slot for it. */
1991
1992 if (reg_renumber[i] < 0
1993 && REG_N_REFS (i) > 0
1994 && reg_equiv_constant[i] == 0
1995 && (reg_equiv_invariant[i] == 0 || reg_equiv_init[i] == 0)
1996 && reg_equiv_memory_loc[i] == 0)
1997 {
1998 rtx x;
1999 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2000 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
2001 unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2002 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2003 unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;
2004 int adjust = 0;
2005
2006 /* Each pseudo reg has an inherent size which comes from its own mode,
2007 and a total size which provides room for paradoxical subregs
2008 which refer to the pseudo reg in wider modes.
2009
2010 We can use a slot already allocated if it provides both
2011 enough inherent space and enough total space.
2012 Otherwise, we allocate a new slot, making sure that it has no less
2013 inherent space, and no less total space, then the previous slot. */
2014 if (from_reg == -1)
2015 {
2016 /* No known place to spill from => no slot to reuse. */
2017 x = assign_stack_local (mode, total_size,
2018 min_align > inherent_align
2019 || total_size > inherent_size ? -1 : 0);
2020 if (BYTES_BIG_ENDIAN)
2021 /* Cancel the big-endian correction done in assign_stack_local.
2022 Get the address of the beginning of the slot.
2023 This is so we can do a big-endian correction unconditionally
2024 below. */
2025 adjust = inherent_size - total_size;
2026
2027 /* Nothing can alias this slot except this pseudo. */
2028 set_mem_alias_set (x, new_alias_set ());
2029 }
2030
2031 /* Reuse a stack slot if possible. */
2032 else if (spill_stack_slot[from_reg] != 0
2033 && spill_stack_slot_width[from_reg] >= total_size
2034 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2035 >= inherent_size)
2036 && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2037 x = spill_stack_slot[from_reg];
2038
2039 /* Allocate a bigger slot. */
2040 else
2041 {
2042 /* Compute maximum size needed, both for inherent size
2043 and for total size. */
2044 rtx stack_slot;
2045
2046 if (spill_stack_slot[from_reg])
2047 {
2048 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2049 > inherent_size)
2050 mode = GET_MODE (spill_stack_slot[from_reg]);
2051 if (spill_stack_slot_width[from_reg] > total_size)
2052 total_size = spill_stack_slot_width[from_reg];
2053 if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2054 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2055 }
2056
2057 /* Make a slot with that size. */
2058 x = assign_stack_local (mode, total_size,
2059 min_align > inherent_align
2060 || total_size > inherent_size ? -1 : 0);
2061 stack_slot = x;
2062
2063 /* All pseudos mapped to this slot can alias each other. */
2064 if (spill_stack_slot[from_reg])
2065 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
2066 else
2067 set_mem_alias_set (x, new_alias_set ());
2068
2069 if (BYTES_BIG_ENDIAN)
2070 {
2071 /* Cancel the big-endian correction done in assign_stack_local.
2072 Get the address of the beginning of the slot.
2073 This is so we can do a big-endian correction unconditionally
2074 below. */
2075 adjust = GET_MODE_SIZE (mode) - total_size;
2076 if (adjust)
2077 stack_slot
2078 = adjust_address_nv (x, mode_for_size (total_size
2079 * BITS_PER_UNIT,
2080 MODE_INT, 1),
2081 adjust);
2082 }
2083
2084 spill_stack_slot[from_reg] = stack_slot;
2085 spill_stack_slot_width[from_reg] = total_size;
2086 }
2087
2088 /* On a big endian machine, the "address" of the slot
2089 is the address of the low part that fits its inherent mode. */
2090 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2091 adjust += (total_size - inherent_size);
2092
2093 /* If we have any adjustment to make, or if the stack slot is the
2094 wrong mode, make a new stack slot. */
2095 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2096
2097 /* If we have a decl for the original register, set it for the
2098 memory. If this is a shared MEM, make a copy. */
2099 if (REG_EXPR (regno_reg_rtx[i])
2100 && DECL_P (REG_EXPR (regno_reg_rtx[i])))
2101 {
2102 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2103
2104 /* We can do this only for the DECLs home pseudo, not for
2105 any copies of it, since otherwise when the stack slot
2106 is reused, nonoverlapping_memrefs_p might think they
2107 cannot overlap. */
2108 if (decl && REG_P (decl) && REGNO (decl) == (unsigned) i)
2109 {
2110 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2111 x = copy_rtx (x);
2112
2113 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2114 }
2115 }
2116
2117 /* Save the stack slot for later. */
2118 reg_equiv_memory_loc[i] = x;
2119 }
2120 }
2121
2122 /* Mark the slots in regs_ever_live for the hard regs
2123 used by pseudo-reg number REGNO. */
2124
2125 void
mark_home_live(int regno)2126 mark_home_live (int regno)
2127 {
2128 int i, lim;
2129
2130 i = reg_renumber[regno];
2131 if (i < 0)
2132 return;
2133 lim = i + hard_regno_nregs[i][PSEUDO_REGNO_MODE (regno)];
2134 while (i < lim)
2135 regs_ever_live[i++] = 1;
2136 }
2137
2138 /* This function handles the tracking of elimination offsets around branches.
2139
2140 X is a piece of RTL being scanned.
2141
2142 INSN is the insn that it came from, if any.
2143
2144 INITIAL_P is nonzero if we are to set the offset to be the initial
2145 offset and zero if we are setting the offset of the label to be the
2146 current offset. */
2147
2148 static void
set_label_offsets(rtx x,rtx insn,int initial_p)2149 set_label_offsets (rtx x, rtx insn, int initial_p)
2150 {
2151 enum rtx_code code = GET_CODE (x);
2152 rtx tem;
2153 unsigned int i;
2154 struct elim_table *p;
2155
2156 switch (code)
2157 {
2158 case LABEL_REF:
2159 if (LABEL_REF_NONLOCAL_P (x))
2160 return;
2161
2162 x = XEXP (x, 0);
2163
2164 /* ... fall through ... */
2165
2166 case CODE_LABEL:
2167 /* If we know nothing about this label, set the desired offsets. Note
2168 that this sets the offset at a label to be the offset before a label
2169 if we don't know anything about the label. This is not correct for
2170 the label after a BARRIER, but is the best guess we can make. If
2171 we guessed wrong, we will suppress an elimination that might have
2172 been possible had we been able to guess correctly. */
2173
2174 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2175 {
2176 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2177 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2178 = (initial_p ? reg_eliminate[i].initial_offset
2179 : reg_eliminate[i].offset);
2180 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2181 }
2182
2183 /* Otherwise, if this is the definition of a label and it is
2184 preceded by a BARRIER, set our offsets to the known offset of
2185 that label. */
2186
2187 else if (x == insn
2188 && (tem = prev_nonnote_insn (insn)) != 0
2189 && BARRIER_P (tem))
2190 set_offsets_for_label (insn);
2191 else
2192 /* If neither of the above cases is true, compare each offset
2193 with those previously recorded and suppress any eliminations
2194 where the offsets disagree. */
2195
2196 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2197 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2198 != (initial_p ? reg_eliminate[i].initial_offset
2199 : reg_eliminate[i].offset))
2200 reg_eliminate[i].can_eliminate = 0;
2201
2202 return;
2203
2204 case JUMP_INSN:
2205 set_label_offsets (PATTERN (insn), insn, initial_p);
2206
2207 /* ... fall through ... */
2208
2209 case INSN:
2210 case CALL_INSN:
2211 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2212 and hence must have all eliminations at their initial offsets. */
2213 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2214 if (REG_NOTE_KIND (tem) == REG_LABEL)
2215 set_label_offsets (XEXP (tem, 0), insn, 1);
2216 return;
2217
2218 case PARALLEL:
2219 case ADDR_VEC:
2220 case ADDR_DIFF_VEC:
2221 /* Each of the labels in the parallel or address vector must be
2222 at their initial offsets. We want the first field for PARALLEL
2223 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2224
2225 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2226 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2227 insn, initial_p);
2228 return;
2229
2230 case SET:
2231 /* We only care about setting PC. If the source is not RETURN,
2232 IF_THEN_ELSE, or a label, disable any eliminations not at
2233 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2234 isn't one of those possibilities. For branches to a label,
2235 call ourselves recursively.
2236
2237 Note that this can disable elimination unnecessarily when we have
2238 a non-local goto since it will look like a non-constant jump to
2239 someplace in the current function. This isn't a significant
2240 problem since such jumps will normally be when all elimination
2241 pairs are back to their initial offsets. */
2242
2243 if (SET_DEST (x) != pc_rtx)
2244 return;
2245
2246 switch (GET_CODE (SET_SRC (x)))
2247 {
2248 case PC:
2249 case RETURN:
2250 return;
2251
2252 case LABEL_REF:
2253 set_label_offsets (SET_SRC (x), insn, initial_p);
2254 return;
2255
2256 case IF_THEN_ELSE:
2257 tem = XEXP (SET_SRC (x), 1);
2258 if (GET_CODE (tem) == LABEL_REF)
2259 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2260 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2261 break;
2262
2263 tem = XEXP (SET_SRC (x), 2);
2264 if (GET_CODE (tem) == LABEL_REF)
2265 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2266 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2267 break;
2268 return;
2269
2270 default:
2271 break;
2272 }
2273
2274 /* If we reach here, all eliminations must be at their initial
2275 offset because we are doing a jump to a variable address. */
2276 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2277 if (p->offset != p->initial_offset)
2278 p->can_eliminate = 0;
2279 break;
2280
2281 default:
2282 break;
2283 }
2284 }
2285
2286 /* Scan X and replace any eliminable registers (such as fp) with a
2287 replacement (such as sp), plus an offset.
2288
2289 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2290 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2291 MEM, we are allowed to replace a sum of a register and the constant zero
2292 with the register, which we cannot do outside a MEM. In addition, we need
2293 to record the fact that a register is referenced outside a MEM.
2294
2295 If INSN is an insn, it is the insn containing X. If we replace a REG
2296 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2297 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2298 the REG is being modified.
2299
2300 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2301 That's used when we eliminate in expressions stored in notes.
2302 This means, do not set ref_outside_mem even if the reference
2303 is outside of MEMs.
2304
2305 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2306 replacements done assuming all offsets are at their initial values. If
2307 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2308 encounter, return the actual location so that find_reloads will do
2309 the proper thing. */
2310
2311 static rtx
eliminate_regs_1(rtx x,enum machine_mode mem_mode,rtx insn,bool may_use_invariant)2312 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2313 bool may_use_invariant)
2314 {
2315 enum rtx_code code = GET_CODE (x);
2316 struct elim_table *ep;
2317 int regno;
2318 rtx new;
2319 int i, j;
2320 const char *fmt;
2321 int copied = 0;
2322
2323 if (! current_function_decl)
2324 return x;
2325
2326 switch (code)
2327 {
2328 case CONST_INT:
2329 case CONST_DOUBLE:
2330 case CONST_VECTOR:
2331 case CONST:
2332 case SYMBOL_REF:
2333 case CODE_LABEL:
2334 case PC:
2335 case CC0:
2336 case ASM_INPUT:
2337 case ADDR_VEC:
2338 case ADDR_DIFF_VEC:
2339 case RETURN:
2340 return x;
2341
2342 case REG:
2343 regno = REGNO (x);
2344
2345 /* First handle the case where we encounter a bare register that
2346 is eliminable. Replace it with a PLUS. */
2347 if (regno < FIRST_PSEUDO_REGISTER)
2348 {
2349 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2350 ep++)
2351 if (ep->from_rtx == x && ep->can_eliminate)
2352 return plus_constant (ep->to_rtx, ep->previous_offset);
2353
2354 }
2355 else if (reg_renumber && reg_renumber[regno] < 0
2356 && reg_equiv_invariant && reg_equiv_invariant[regno])
2357 {
2358 if (may_use_invariant)
2359 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]),
2360 mem_mode, insn, true);
2361 /* There exists at least one use of REGNO that cannot be
2362 eliminated. Prevent the defining insn from being deleted. */
2363 reg_equiv_init[regno] = NULL_RTX;
2364 alter_reg (regno, -1);
2365 }
2366 return x;
2367
2368 /* You might think handling MINUS in a manner similar to PLUS is a
2369 good idea. It is not. It has been tried multiple times and every
2370 time the change has had to have been reverted.
2371
2372 Other parts of reload know a PLUS is special (gen_reload for example)
2373 and require special code to handle code a reloaded PLUS operand.
2374
2375 Also consider backends where the flags register is clobbered by a
2376 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2377 lea instruction comes to mind). If we try to reload a MINUS, we
2378 may kill the flags register that was holding a useful value.
2379
2380 So, please before trying to handle MINUS, consider reload as a
2381 whole instead of this little section as well as the backend issues. */
2382 case PLUS:
2383 /* If this is the sum of an eliminable register and a constant, rework
2384 the sum. */
2385 if (REG_P (XEXP (x, 0))
2386 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2387 && CONSTANT_P (XEXP (x, 1)))
2388 {
2389 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2390 ep++)
2391 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2392 {
2393 /* The only time we want to replace a PLUS with a REG (this
2394 occurs when the constant operand of the PLUS is the negative
2395 of the offset) is when we are inside a MEM. We won't want
2396 to do so at other times because that would change the
2397 structure of the insn in a way that reload can't handle.
2398 We special-case the commonest situation in
2399 eliminate_regs_in_insn, so just replace a PLUS with a
2400 PLUS here, unless inside a MEM. */
2401 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2402 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2403 return ep->to_rtx;
2404 else
2405 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2406 plus_constant (XEXP (x, 1),
2407 ep->previous_offset));
2408 }
2409
2410 /* If the register is not eliminable, we are done since the other
2411 operand is a constant. */
2412 return x;
2413 }
2414
2415 /* If this is part of an address, we want to bring any constant to the
2416 outermost PLUS. We will do this by doing register replacement in
2417 our operands and seeing if a constant shows up in one of them.
2418
2419 Note that there is no risk of modifying the structure of the insn,
2420 since we only get called for its operands, thus we are either
2421 modifying the address inside a MEM, or something like an address
2422 operand of a load-address insn. */
2423
2424 {
2425 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2426 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2427
2428 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2429 {
2430 /* If one side is a PLUS and the other side is a pseudo that
2431 didn't get a hard register but has a reg_equiv_constant,
2432 we must replace the constant here since it may no longer
2433 be in the position of any operand. */
2434 if (GET_CODE (new0) == PLUS && REG_P (new1)
2435 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2436 && reg_renumber[REGNO (new1)] < 0
2437 && reg_equiv_constant != 0
2438 && reg_equiv_constant[REGNO (new1)] != 0)
2439 new1 = reg_equiv_constant[REGNO (new1)];
2440 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2441 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2442 && reg_renumber[REGNO (new0)] < 0
2443 && reg_equiv_constant[REGNO (new0)] != 0)
2444 new0 = reg_equiv_constant[REGNO (new0)];
2445
2446 new = form_sum (new0, new1);
2447
2448 /* As above, if we are not inside a MEM we do not want to
2449 turn a PLUS into something else. We might try to do so here
2450 for an addition of 0 if we aren't optimizing. */
2451 if (! mem_mode && GET_CODE (new) != PLUS)
2452 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2453 else
2454 return new;
2455 }
2456 }
2457 return x;
2458
2459 case MULT:
2460 /* If this is the product of an eliminable register and a
2461 constant, apply the distribute law and move the constant out
2462 so that we have (plus (mult ..) ..). This is needed in order
2463 to keep load-address insns valid. This case is pathological.
2464 We ignore the possibility of overflow here. */
2465 if (REG_P (XEXP (x, 0))
2466 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2467 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2468 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2469 ep++)
2470 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2471 {
2472 if (! mem_mode
2473 /* Refs inside notes don't count for this purpose. */
2474 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2475 || GET_CODE (insn) == INSN_LIST)))
2476 ep->ref_outside_mem = 1;
2477
2478 return
2479 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2480 ep->previous_offset * INTVAL (XEXP (x, 1)));
2481 }
2482
2483 /* ... fall through ... */
2484
2485 case CALL:
2486 case COMPARE:
2487 /* See comments before PLUS about handling MINUS. */
2488 case MINUS:
2489 case DIV: case UDIV:
2490 case MOD: case UMOD:
2491 case AND: case IOR: case XOR:
2492 case ROTATERT: case ROTATE:
2493 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2494 case NE: case EQ:
2495 case GE: case GT: case GEU: case GTU:
2496 case LE: case LT: case LEU: case LTU:
2497 {
2498 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2499 rtx new1 = XEXP (x, 1)
2500 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false) : 0;
2501
2502 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2503 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2504 }
2505 return x;
2506
2507 case EXPR_LIST:
2508 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2509 if (XEXP (x, 0))
2510 {
2511 new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2512 if (new != XEXP (x, 0))
2513 {
2514 /* If this is a REG_DEAD note, it is not valid anymore.
2515 Using the eliminated version could result in creating a
2516 REG_DEAD note for the stack or frame pointer. */
2517 if (GET_MODE (x) == REG_DEAD)
2518 return (XEXP (x, 1)
2519 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true)
2520 : NULL_RTX);
2521
2522 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2523 }
2524 }
2525
2526 /* ... fall through ... */
2527
2528 case INSN_LIST:
2529 /* Now do eliminations in the rest of the chain. If this was
2530 an EXPR_LIST, this might result in allocating more memory than is
2531 strictly needed, but it simplifies the code. */
2532 if (XEXP (x, 1))
2533 {
2534 new = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2535 if (new != XEXP (x, 1))
2536 return
2537 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2538 }
2539 return x;
2540
2541 case PRE_INC:
2542 case POST_INC:
2543 case PRE_DEC:
2544 case POST_DEC:
2545 case STRICT_LOW_PART:
2546 case NEG: case NOT:
2547 case SIGN_EXTEND: case ZERO_EXTEND:
2548 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2549 case FLOAT: case FIX:
2550 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2551 case ABS:
2552 case SQRT:
2553 case FFS:
2554 case CLZ:
2555 case CTZ:
2556 case POPCOUNT:
2557 case PARITY:
2558 case BSWAP:
2559 new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2560 if (new != XEXP (x, 0))
2561 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2562 return x;
2563
2564 case SUBREG:
2565 /* Similar to above processing, but preserve SUBREG_BYTE.
2566 Convert (subreg (mem)) to (mem) if not paradoxical.
2567 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2568 pseudo didn't get a hard reg, we must replace this with the
2569 eliminated version of the memory location because push_reload
2570 may do the replacement in certain circumstances. */
2571 if (REG_P (SUBREG_REG (x))
2572 && (GET_MODE_SIZE (GET_MODE (x))
2573 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2574 && reg_equiv_memory_loc != 0
2575 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2576 {
2577 new = SUBREG_REG (x);
2578 }
2579 else
2580 new = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false);
2581
2582 if (new != SUBREG_REG (x))
2583 {
2584 int x_size = GET_MODE_SIZE (GET_MODE (x));
2585 int new_size = GET_MODE_SIZE (GET_MODE (new));
2586
2587 if (MEM_P (new)
2588 && ((x_size < new_size
2589 #ifdef WORD_REGISTER_OPERATIONS
2590 /* On these machines, combine can create rtl of the form
2591 (set (subreg:m1 (reg:m2 R) 0) ...)
2592 where m1 < m2, and expects something interesting to
2593 happen to the entire word. Moreover, it will use the
2594 (reg:m2 R) later, expecting all bits to be preserved.
2595 So if the number of words is the same, preserve the
2596 subreg so that push_reload can see it. */
2597 && ! ((x_size - 1) / UNITS_PER_WORD
2598 == (new_size -1 ) / UNITS_PER_WORD)
2599 #endif
2600 )
2601 || x_size == new_size)
2602 )
2603 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2604 else
2605 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2606 }
2607
2608 return x;
2609
2610 case MEM:
2611 /* Our only special processing is to pass the mode of the MEM to our
2612 recursive call and copy the flags. While we are here, handle this
2613 case more efficiently. */
2614 return
2615 replace_equiv_address_nv (x,
2616 eliminate_regs_1 (XEXP (x, 0), GET_MODE (x),
2617 insn, true));
2618
2619 case USE:
2620 /* Handle insn_list USE that a call to a pure function may generate. */
2621 new = eliminate_regs_1 (XEXP (x, 0), 0, insn, false);
2622 if (new != XEXP (x, 0))
2623 return gen_rtx_USE (GET_MODE (x), new);
2624 return x;
2625
2626 case CLOBBER:
2627 case ASM_OPERANDS:
2628 case SET:
2629 gcc_unreachable ();
2630
2631 default:
2632 break;
2633 }
2634
2635 /* Process each of our operands recursively. If any have changed, make a
2636 copy of the rtx. */
2637 fmt = GET_RTX_FORMAT (code);
2638 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2639 {
2640 if (*fmt == 'e')
2641 {
2642 new = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false);
2643 if (new != XEXP (x, i) && ! copied)
2644 {
2645 x = shallow_copy_rtx (x);
2646 copied = 1;
2647 }
2648 XEXP (x, i) = new;
2649 }
2650 else if (*fmt == 'E')
2651 {
2652 int copied_vec = 0;
2653 for (j = 0; j < XVECLEN (x, i); j++)
2654 {
2655 new = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false);
2656 if (new != XVECEXP (x, i, j) && ! copied_vec)
2657 {
2658 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2659 XVEC (x, i)->elem);
2660 if (! copied)
2661 {
2662 x = shallow_copy_rtx (x);
2663 copied = 1;
2664 }
2665 XVEC (x, i) = new_v;
2666 copied_vec = 1;
2667 }
2668 XVECEXP (x, i, j) = new;
2669 }
2670 }
2671 }
2672
2673 return x;
2674 }
2675
2676 rtx
eliminate_regs(rtx x,enum machine_mode mem_mode,rtx insn)2677 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2678 {
2679 return eliminate_regs_1 (x, mem_mode, insn, false);
2680 }
2681
2682 /* Scan rtx X for modifications of elimination target registers. Update
2683 the table of eliminables to reflect the changed state. MEM_MODE is
2684 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2685
2686 static void
elimination_effects(rtx x,enum machine_mode mem_mode)2687 elimination_effects (rtx x, enum machine_mode mem_mode)
2688 {
2689 enum rtx_code code = GET_CODE (x);
2690 struct elim_table *ep;
2691 int regno;
2692 int i, j;
2693 const char *fmt;
2694
2695 switch (code)
2696 {
2697 case CONST_INT:
2698 case CONST_DOUBLE:
2699 case CONST_VECTOR:
2700 case CONST:
2701 case SYMBOL_REF:
2702 case CODE_LABEL:
2703 case PC:
2704 case CC0:
2705 case ASM_INPUT:
2706 case ADDR_VEC:
2707 case ADDR_DIFF_VEC:
2708 case RETURN:
2709 return;
2710
2711 case REG:
2712 regno = REGNO (x);
2713
2714 /* First handle the case where we encounter a bare register that
2715 is eliminable. Replace it with a PLUS. */
2716 if (regno < FIRST_PSEUDO_REGISTER)
2717 {
2718 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2719 ep++)
2720 if (ep->from_rtx == x && ep->can_eliminate)
2721 {
2722 if (! mem_mode)
2723 ep->ref_outside_mem = 1;
2724 return;
2725 }
2726
2727 }
2728 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2729 && reg_equiv_constant[regno]
2730 && ! function_invariant_p (reg_equiv_constant[regno]))
2731 elimination_effects (reg_equiv_constant[regno], mem_mode);
2732 return;
2733
2734 case PRE_INC:
2735 case POST_INC:
2736 case PRE_DEC:
2737 case POST_DEC:
2738 case POST_MODIFY:
2739 case PRE_MODIFY:
2740 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2741 if (ep->to_rtx == XEXP (x, 0))
2742 {
2743 int size = GET_MODE_SIZE (mem_mode);
2744
2745 /* If more bytes than MEM_MODE are pushed, account for them. */
2746 #ifdef PUSH_ROUNDING
2747 if (ep->to_rtx == stack_pointer_rtx)
2748 size = PUSH_ROUNDING (size);
2749 #endif
2750 if (code == PRE_DEC || code == POST_DEC)
2751 ep->offset += size;
2752 else if (code == PRE_INC || code == POST_INC)
2753 ep->offset -= size;
2754 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2755 && GET_CODE (XEXP (x, 1)) == PLUS
2756 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2757 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2758 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2759 }
2760
2761 /* These two aren't unary operators. */
2762 if (code == POST_MODIFY || code == PRE_MODIFY)
2763 break;
2764
2765 /* Fall through to generic unary operation case. */
2766 case STRICT_LOW_PART:
2767 case NEG: case NOT:
2768 case SIGN_EXTEND: case ZERO_EXTEND:
2769 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2770 case FLOAT: case FIX:
2771 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2772 case ABS:
2773 case SQRT:
2774 case FFS:
2775 case CLZ:
2776 case CTZ:
2777 case POPCOUNT:
2778 case PARITY:
2779 case BSWAP:
2780 elimination_effects (XEXP (x, 0), mem_mode);
2781 return;
2782
2783 case SUBREG:
2784 if (REG_P (SUBREG_REG (x))
2785 && (GET_MODE_SIZE (GET_MODE (x))
2786 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2787 && reg_equiv_memory_loc != 0
2788 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2789 return;
2790
2791 elimination_effects (SUBREG_REG (x), mem_mode);
2792 return;
2793
2794 case USE:
2795 /* If using a register that is the source of an eliminate we still
2796 think can be performed, note it cannot be performed since we don't
2797 know how this register is used. */
2798 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2799 if (ep->from_rtx == XEXP (x, 0))
2800 ep->can_eliminate = 0;
2801
2802 elimination_effects (XEXP (x, 0), mem_mode);
2803 return;
2804
2805 case CLOBBER:
2806 /* If clobbering a register that is the replacement register for an
2807 elimination we still think can be performed, note that it cannot
2808 be performed. Otherwise, we need not be concerned about it. */
2809 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2810 if (ep->to_rtx == XEXP (x, 0))
2811 ep->can_eliminate = 0;
2812
2813 elimination_effects (XEXP (x, 0), mem_mode);
2814 return;
2815
2816 case SET:
2817 /* Check for setting a register that we know about. */
2818 if (REG_P (SET_DEST (x)))
2819 {
2820 /* See if this is setting the replacement register for an
2821 elimination.
2822
2823 If DEST is the hard frame pointer, we do nothing because we
2824 assume that all assignments to the frame pointer are for
2825 non-local gotos and are being done at a time when they are valid
2826 and do not disturb anything else. Some machines want to
2827 eliminate a fake argument pointer (or even a fake frame pointer)
2828 with either the real frame or the stack pointer. Assignments to
2829 the hard frame pointer must not prevent this elimination. */
2830
2831 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2832 ep++)
2833 if (ep->to_rtx == SET_DEST (x)
2834 && SET_DEST (x) != hard_frame_pointer_rtx)
2835 {
2836 /* If it is being incremented, adjust the offset. Otherwise,
2837 this elimination can't be done. */
2838 rtx src = SET_SRC (x);
2839
2840 if (GET_CODE (src) == PLUS
2841 && XEXP (src, 0) == SET_DEST (x)
2842 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2843 ep->offset -= INTVAL (XEXP (src, 1));
2844 else
2845 ep->can_eliminate = 0;
2846 }
2847 }
2848
2849 elimination_effects (SET_DEST (x), 0);
2850 elimination_effects (SET_SRC (x), 0);
2851 return;
2852
2853 case MEM:
2854 /* Our only special processing is to pass the mode of the MEM to our
2855 recursive call. */
2856 elimination_effects (XEXP (x, 0), GET_MODE (x));
2857 return;
2858
2859 default:
2860 break;
2861 }
2862
2863 fmt = GET_RTX_FORMAT (code);
2864 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2865 {
2866 if (*fmt == 'e')
2867 elimination_effects (XEXP (x, i), mem_mode);
2868 else if (*fmt == 'E')
2869 for (j = 0; j < XVECLEN (x, i); j++)
2870 elimination_effects (XVECEXP (x, i, j), mem_mode);
2871 }
2872 }
2873
2874 /* Descend through rtx X and verify that no references to eliminable registers
2875 remain. If any do remain, mark the involved register as not
2876 eliminable. */
2877
2878 static void
check_eliminable_occurrences(rtx x)2879 check_eliminable_occurrences (rtx x)
2880 {
2881 const char *fmt;
2882 int i;
2883 enum rtx_code code;
2884
2885 if (x == 0)
2886 return;
2887
2888 code = GET_CODE (x);
2889
2890 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2891 {
2892 struct elim_table *ep;
2893
2894 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2895 if (ep->from_rtx == x)
2896 ep->can_eliminate = 0;
2897 return;
2898 }
2899
2900 fmt = GET_RTX_FORMAT (code);
2901 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2902 {
2903 if (*fmt == 'e')
2904 check_eliminable_occurrences (XEXP (x, i));
2905 else if (*fmt == 'E')
2906 {
2907 int j;
2908 for (j = 0; j < XVECLEN (x, i); j++)
2909 check_eliminable_occurrences (XVECEXP (x, i, j));
2910 }
2911 }
2912 }
2913
2914 /* Scan INSN and eliminate all eliminable registers in it.
2915
2916 If REPLACE is nonzero, do the replacement destructively. Also
2917 delete the insn as dead it if it is setting an eliminable register.
2918
2919 If REPLACE is zero, do all our allocations in reload_obstack.
2920
2921 If no eliminations were done and this insn doesn't require any elimination
2922 processing (these are not identical conditions: it might be updating sp,
2923 but not referencing fp; this needs to be seen during reload_as_needed so
2924 that the offset between fp and sp can be taken into consideration), zero
2925 is returned. Otherwise, 1 is returned. */
2926
2927 static int
eliminate_regs_in_insn(rtx insn,int replace)2928 eliminate_regs_in_insn (rtx insn, int replace)
2929 {
2930 int icode = recog_memoized (insn);
2931 rtx old_body = PATTERN (insn);
2932 int insn_is_asm = asm_noperands (old_body) >= 0;
2933 rtx old_set = single_set (insn);
2934 rtx new_body;
2935 int val = 0;
2936 int i;
2937 rtx substed_operand[MAX_RECOG_OPERANDS];
2938 rtx orig_operand[MAX_RECOG_OPERANDS];
2939 struct elim_table *ep;
2940 rtx plus_src, plus_cst_src;
2941
2942 if (! insn_is_asm && icode < 0)
2943 {
2944 gcc_assert (GET_CODE (PATTERN (insn)) == USE
2945 || GET_CODE (PATTERN (insn)) == CLOBBER
2946 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2947 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2948 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
2949 return 0;
2950 }
2951
2952 if (old_set != 0 && REG_P (SET_DEST (old_set))
2953 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2954 {
2955 /* Check for setting an eliminable register. */
2956 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2957 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2958 {
2959 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2960 /* If this is setting the frame pointer register to the
2961 hardware frame pointer register and this is an elimination
2962 that will be done (tested above), this insn is really
2963 adjusting the frame pointer downward to compensate for
2964 the adjustment done before a nonlocal goto. */
2965 if (ep->from == FRAME_POINTER_REGNUM
2966 && ep->to == HARD_FRAME_POINTER_REGNUM)
2967 {
2968 rtx base = SET_SRC (old_set);
2969 rtx base_insn = insn;
2970 HOST_WIDE_INT offset = 0;
2971
2972 while (base != ep->to_rtx)
2973 {
2974 rtx prev_insn, prev_set;
2975
2976 if (GET_CODE (base) == PLUS
2977 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2978 {
2979 offset += INTVAL (XEXP (base, 1));
2980 base = XEXP (base, 0);
2981 }
2982 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2983 && (prev_set = single_set (prev_insn)) != 0
2984 && rtx_equal_p (SET_DEST (prev_set), base))
2985 {
2986 base = SET_SRC (prev_set);
2987 base_insn = prev_insn;
2988 }
2989 else
2990 break;
2991 }
2992
2993 if (base == ep->to_rtx)
2994 {
2995 rtx src
2996 = plus_constant (ep->to_rtx, offset - ep->offset);
2997
2998 new_body = old_body;
2999 if (! replace)
3000 {
3001 new_body = copy_insn (old_body);
3002 if (REG_NOTES (insn))
3003 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3004 }
3005 PATTERN (insn) = new_body;
3006 old_set = single_set (insn);
3007
3008 /* First see if this insn remains valid when we
3009 make the change. If not, keep the INSN_CODE
3010 the same and let reload fit it up. */
3011 validate_change (insn, &SET_SRC (old_set), src, 1);
3012 validate_change (insn, &SET_DEST (old_set),
3013 ep->to_rtx, 1);
3014 if (! apply_change_group ())
3015 {
3016 SET_SRC (old_set) = src;
3017 SET_DEST (old_set) = ep->to_rtx;
3018 }
3019
3020 val = 1;
3021 goto done;
3022 }
3023 }
3024 #endif
3025
3026 /* In this case this insn isn't serving a useful purpose. We
3027 will delete it in reload_as_needed once we know that this
3028 elimination is, in fact, being done.
3029
3030 If REPLACE isn't set, we can't delete this insn, but needn't
3031 process it since it won't be used unless something changes. */
3032 if (replace)
3033 {
3034 delete_dead_insn (insn);
3035 return 1;
3036 }
3037 val = 1;
3038 goto done;
3039 }
3040 }
3041
3042 /* We allow one special case which happens to work on all machines we
3043 currently support: a single set with the source or a REG_EQUAL
3044 note being a PLUS of an eliminable register and a constant. */
3045 plus_src = plus_cst_src = 0;
3046 if (old_set && REG_P (SET_DEST (old_set)))
3047 {
3048 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3049 plus_src = SET_SRC (old_set);
3050 /* First see if the source is of the form (plus (...) CST). */
3051 if (plus_src
3052 && GET_CODE (XEXP (plus_src, 1)) == CONST_INT)
3053 plus_cst_src = plus_src;
3054 else if (REG_P (SET_SRC (old_set))
3055 || plus_src)
3056 {
3057 /* Otherwise, see if we have a REG_EQUAL note of the form
3058 (plus (...) CST). */
3059 rtx links;
3060 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3061 {
3062 if (REG_NOTE_KIND (links) == REG_EQUAL
3063 && GET_CODE (XEXP (links, 0)) == PLUS
3064 && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT)
3065 {
3066 plus_cst_src = XEXP (links, 0);
3067 break;
3068 }
3069 }
3070 }
3071
3072 /* Check that the first operand of the PLUS is a hard reg or
3073 the lowpart subreg of one. */
3074 if (plus_cst_src)
3075 {
3076 rtx reg = XEXP (plus_cst_src, 0);
3077 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3078 reg = SUBREG_REG (reg);
3079
3080 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3081 plus_cst_src = 0;
3082 }
3083 }
3084 if (plus_cst_src)
3085 {
3086 rtx reg = XEXP (plus_cst_src, 0);
3087 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3088
3089 if (GET_CODE (reg) == SUBREG)
3090 reg = SUBREG_REG (reg);
3091
3092 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3093 if (ep->from_rtx == reg && ep->can_eliminate)
3094 {
3095 rtx to_rtx = ep->to_rtx;
3096 offset += ep->offset;
3097 offset = trunc_int_for_mode (offset, GET_MODE (reg));
3098
3099 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3100 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3101 to_rtx);
3102 /* If we have a nonzero offset, and the source is already
3103 a simple REG, the following transformation would
3104 increase the cost of the insn by replacing a simple REG
3105 with (plus (reg sp) CST). So try only when we already
3106 had a PLUS before. */
3107 if (offset == 0 || plus_src)
3108 {
3109 rtx new_src = plus_constant (to_rtx, offset);
3110
3111 new_body = old_body;
3112 if (! replace)
3113 {
3114 new_body = copy_insn (old_body);
3115 if (REG_NOTES (insn))
3116 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3117 }
3118 PATTERN (insn) = new_body;
3119 old_set = single_set (insn);
3120
3121 /* First see if this insn remains valid when we make the
3122 change. If not, try to replace the whole pattern with
3123 a simple set (this may help if the original insn was a
3124 PARALLEL that was only recognized as single_set due to
3125 REG_UNUSED notes). If this isn't valid either, keep
3126 the INSN_CODE the same and let reload fix it up. */
3127 if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3128 {
3129 rtx new_pat = gen_rtx_SET (VOIDmode,
3130 SET_DEST (old_set), new_src);
3131
3132 if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3133 SET_SRC (old_set) = new_src;
3134 }
3135 }
3136 else
3137 break;
3138
3139 val = 1;
3140 /* This can't have an effect on elimination offsets, so skip right
3141 to the end. */
3142 goto done;
3143 }
3144 }
3145
3146 /* Determine the effects of this insn on elimination offsets. */
3147 elimination_effects (old_body, 0);
3148
3149 /* Eliminate all eliminable registers occurring in operands that
3150 can be handled by reload. */
3151 extract_insn (insn);
3152 for (i = 0; i < recog_data.n_operands; i++)
3153 {
3154 orig_operand[i] = recog_data.operand[i];
3155 substed_operand[i] = recog_data.operand[i];
3156
3157 /* For an asm statement, every operand is eliminable. */
3158 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3159 {
3160 bool is_set_src, in_plus;
3161
3162 /* Check for setting a register that we know about. */
3163 if (recog_data.operand_type[i] != OP_IN
3164 && REG_P (orig_operand[i]))
3165 {
3166 /* If we are assigning to a register that can be eliminated, it
3167 must be as part of a PARALLEL, since the code above handles
3168 single SETs. We must indicate that we can no longer
3169 eliminate this reg. */
3170 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3171 ep++)
3172 if (ep->from_rtx == orig_operand[i])
3173 ep->can_eliminate = 0;
3174 }
3175
3176 /* Companion to the above plus substitution, we can allow
3177 invariants as the source of a plain move. */
3178 is_set_src = false;
3179 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3180 is_set_src = true;
3181 in_plus = false;
3182 if (plus_src
3183 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3184 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3185 in_plus = true;
3186
3187 substed_operand[i]
3188 = eliminate_regs_1 (recog_data.operand[i], 0,
3189 replace ? insn : NULL_RTX,
3190 is_set_src || in_plus);
3191 if (substed_operand[i] != orig_operand[i])
3192 val = 1;
3193 /* Terminate the search in check_eliminable_occurrences at
3194 this point. */
3195 *recog_data.operand_loc[i] = 0;
3196
3197 /* If an output operand changed from a REG to a MEM and INSN is an
3198 insn, write a CLOBBER insn. */
3199 if (recog_data.operand_type[i] != OP_IN
3200 && REG_P (orig_operand[i])
3201 && MEM_P (substed_operand[i])
3202 && replace)
3203 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3204 insn);
3205 }
3206 }
3207
3208 for (i = 0; i < recog_data.n_dups; i++)
3209 *recog_data.dup_loc[i]
3210 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3211
3212 /* If any eliminable remain, they aren't eliminable anymore. */
3213 check_eliminable_occurrences (old_body);
3214
3215 /* Substitute the operands; the new values are in the substed_operand
3216 array. */
3217 for (i = 0; i < recog_data.n_operands; i++)
3218 *recog_data.operand_loc[i] = substed_operand[i];
3219 for (i = 0; i < recog_data.n_dups; i++)
3220 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3221
3222 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3223 re-recognize the insn. We do this in case we had a simple addition
3224 but now can do this as a load-address. This saves an insn in this
3225 common case.
3226 If re-recognition fails, the old insn code number will still be used,
3227 and some register operands may have changed into PLUS expressions.
3228 These will be handled by find_reloads by loading them into a register
3229 again. */
3230
3231 if (val)
3232 {
3233 /* If we aren't replacing things permanently and we changed something,
3234 make another copy to ensure that all the RTL is new. Otherwise
3235 things can go wrong if find_reload swaps commutative operands
3236 and one is inside RTL that has been copied while the other is not. */
3237 new_body = old_body;
3238 if (! replace)
3239 {
3240 new_body = copy_insn (old_body);
3241 if (REG_NOTES (insn))
3242 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3243 }
3244 PATTERN (insn) = new_body;
3245
3246 /* If we had a move insn but now we don't, rerecognize it. This will
3247 cause spurious re-recognition if the old move had a PARALLEL since
3248 the new one still will, but we can't call single_set without
3249 having put NEW_BODY into the insn and the re-recognition won't
3250 hurt in this rare case. */
3251 /* ??? Why this huge if statement - why don't we just rerecognize the
3252 thing always? */
3253 if (! insn_is_asm
3254 && old_set != 0
3255 && ((REG_P (SET_SRC (old_set))
3256 && (GET_CODE (new_body) != SET
3257 || !REG_P (SET_SRC (new_body))))
3258 /* If this was a load from or store to memory, compare
3259 the MEM in recog_data.operand to the one in the insn.
3260 If they are not equal, then rerecognize the insn. */
3261 || (old_set != 0
3262 && ((MEM_P (SET_SRC (old_set))
3263 && SET_SRC (old_set) != recog_data.operand[1])
3264 || (MEM_P (SET_DEST (old_set))
3265 && SET_DEST (old_set) != recog_data.operand[0])))
3266 /* If this was an add insn before, rerecognize. */
3267 || GET_CODE (SET_SRC (old_set)) == PLUS))
3268 {
3269 int new_icode = recog (PATTERN (insn), insn, 0);
3270 if (new_icode >= 0)
3271 INSN_CODE (insn) = new_icode;
3272 }
3273 }
3274
3275 /* Restore the old body. If there were any changes to it, we made a copy
3276 of it while the changes were still in place, so we'll correctly return
3277 a modified insn below. */
3278 if (! replace)
3279 {
3280 /* Restore the old body. */
3281 for (i = 0; i < recog_data.n_operands; i++)
3282 *recog_data.operand_loc[i] = orig_operand[i];
3283 for (i = 0; i < recog_data.n_dups; i++)
3284 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3285 }
3286
3287 /* Update all elimination pairs to reflect the status after the current
3288 insn. The changes we make were determined by the earlier call to
3289 elimination_effects.
3290
3291 We also detect cases where register elimination cannot be done,
3292 namely, if a register would be both changed and referenced outside a MEM
3293 in the resulting insn since such an insn is often undefined and, even if
3294 not, we cannot know what meaning will be given to it. Note that it is
3295 valid to have a register used in an address in an insn that changes it
3296 (presumably with a pre- or post-increment or decrement).
3297
3298 If anything changes, return nonzero. */
3299
3300 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3301 {
3302 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3303 ep->can_eliminate = 0;
3304
3305 ep->ref_outside_mem = 0;
3306
3307 if (ep->previous_offset != ep->offset)
3308 val = 1;
3309 }
3310
3311 done:
3312 /* If we changed something, perform elimination in REG_NOTES. This is
3313 needed even when REPLACE is zero because a REG_DEAD note might refer
3314 to a register that we eliminate and could cause a different number
3315 of spill registers to be needed in the final reload pass than in
3316 the pre-passes. */
3317 if (val && REG_NOTES (insn) != 0)
3318 REG_NOTES (insn)
3319 = eliminate_regs_1 (REG_NOTES (insn), 0, REG_NOTES (insn), true);
3320
3321 return val;
3322 }
3323
3324 /* Loop through all elimination pairs.
3325 Recalculate the number not at initial offset.
3326
3327 Compute the maximum offset (minimum offset if the stack does not
3328 grow downward) for each elimination pair. */
3329
3330 static void
update_eliminable_offsets(void)3331 update_eliminable_offsets (void)
3332 {
3333 struct elim_table *ep;
3334
3335 num_not_at_initial_offset = 0;
3336 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3337 {
3338 ep->previous_offset = ep->offset;
3339 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3340 num_not_at_initial_offset++;
3341 }
3342 }
3343
3344 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3345 replacement we currently believe is valid, mark it as not eliminable if X
3346 modifies DEST in any way other than by adding a constant integer to it.
3347
3348 If DEST is the frame pointer, we do nothing because we assume that
3349 all assignments to the hard frame pointer are nonlocal gotos and are being
3350 done at a time when they are valid and do not disturb anything else.
3351 Some machines want to eliminate a fake argument pointer with either the
3352 frame or stack pointer. Assignments to the hard frame pointer must not
3353 prevent this elimination.
3354
3355 Called via note_stores from reload before starting its passes to scan
3356 the insns of the function. */
3357
3358 static void
mark_not_eliminable(rtx dest,rtx x,void * data ATTRIBUTE_UNUSED)3359 mark_not_eliminable (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
3360 {
3361 unsigned int i;
3362
3363 /* A SUBREG of a hard register here is just changing its mode. We should
3364 not see a SUBREG of an eliminable hard register, but check just in
3365 case. */
3366 if (GET_CODE (dest) == SUBREG)
3367 dest = SUBREG_REG (dest);
3368
3369 if (dest == hard_frame_pointer_rtx)
3370 return;
3371
3372 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3373 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3374 && (GET_CODE (x) != SET
3375 || GET_CODE (SET_SRC (x)) != PLUS
3376 || XEXP (SET_SRC (x), 0) != dest
3377 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3378 {
3379 reg_eliminate[i].can_eliminate_previous
3380 = reg_eliminate[i].can_eliminate = 0;
3381 num_eliminable--;
3382 }
3383 }
3384
3385 /* Verify that the initial elimination offsets did not change since the
3386 last call to set_initial_elim_offsets. This is used to catch cases
3387 where something illegal happened during reload_as_needed that could
3388 cause incorrect code to be generated if we did not check for it. */
3389
3390 static bool
verify_initial_elim_offsets(void)3391 verify_initial_elim_offsets (void)
3392 {
3393 HOST_WIDE_INT t;
3394
3395 if (!num_eliminable)
3396 return true;
3397
3398 #ifdef ELIMINABLE_REGS
3399 {
3400 struct elim_table *ep;
3401
3402 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3403 {
3404 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3405 if (t != ep->initial_offset)
3406 return false;
3407 }
3408 }
3409 #else
3410 INITIAL_FRAME_POINTER_OFFSET (t);
3411 if (t != reg_eliminate[0].initial_offset)
3412 return false;
3413 #endif
3414
3415 return true;
3416 }
3417
3418 /* Reset all offsets on eliminable registers to their initial values. */
3419
3420 static void
set_initial_elim_offsets(void)3421 set_initial_elim_offsets (void)
3422 {
3423 struct elim_table *ep = reg_eliminate;
3424
3425 #ifdef ELIMINABLE_REGS
3426 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3427 {
3428 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3429 ep->previous_offset = ep->offset = ep->initial_offset;
3430 }
3431 #else
3432 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3433 ep->previous_offset = ep->offset = ep->initial_offset;
3434 #endif
3435
3436 num_not_at_initial_offset = 0;
3437 }
3438
3439 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3440
3441 static void
set_initial_eh_label_offset(rtx label)3442 set_initial_eh_label_offset (rtx label)
3443 {
3444 set_label_offsets (label, NULL_RTX, 1);
3445 }
3446
3447 /* Initialize the known label offsets.
3448 Set a known offset for each forced label to be at the initial offset
3449 of each elimination. We do this because we assume that all
3450 computed jumps occur from a location where each elimination is
3451 at its initial offset.
3452 For all other labels, show that we don't know the offsets. */
3453
3454 static void
set_initial_label_offsets(void)3455 set_initial_label_offsets (void)
3456 {
3457 rtx x;
3458 memset (offsets_known_at, 0, num_labels);
3459
3460 for (x = forced_labels; x; x = XEXP (x, 1))
3461 if (XEXP (x, 0))
3462 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3463
3464 for_each_eh_label (set_initial_eh_label_offset);
3465 }
3466
3467 /* Set all elimination offsets to the known values for the code label given
3468 by INSN. */
3469
3470 static void
set_offsets_for_label(rtx insn)3471 set_offsets_for_label (rtx insn)
3472 {
3473 unsigned int i;
3474 int label_nr = CODE_LABEL_NUMBER (insn);
3475 struct elim_table *ep;
3476
3477 num_not_at_initial_offset = 0;
3478 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3479 {
3480 ep->offset = ep->previous_offset
3481 = offsets_at[label_nr - first_label_num][i];
3482 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3483 num_not_at_initial_offset++;
3484 }
3485 }
3486
3487 /* See if anything that happened changes which eliminations are valid.
3488 For example, on the SPARC, whether or not the frame pointer can
3489 be eliminated can depend on what registers have been used. We need
3490 not check some conditions again (such as flag_omit_frame_pointer)
3491 since they can't have changed. */
3492
3493 static void
update_eliminables(HARD_REG_SET * pset)3494 update_eliminables (HARD_REG_SET *pset)
3495 {
3496 int previous_frame_pointer_needed = frame_pointer_needed;
3497 struct elim_table *ep;
3498
3499 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3500 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3501 #ifdef ELIMINABLE_REGS
3502 || ! CAN_ELIMINATE (ep->from, ep->to)
3503 #endif
3504 )
3505 ep->can_eliminate = 0;
3506
3507 /* Look for the case where we have discovered that we can't replace
3508 register A with register B and that means that we will now be
3509 trying to replace register A with register C. This means we can
3510 no longer replace register C with register B and we need to disable
3511 such an elimination, if it exists. This occurs often with A == ap,
3512 B == sp, and C == fp. */
3513
3514 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3515 {
3516 struct elim_table *op;
3517 int new_to = -1;
3518
3519 if (! ep->can_eliminate && ep->can_eliminate_previous)
3520 {
3521 /* Find the current elimination for ep->from, if there is a
3522 new one. */
3523 for (op = reg_eliminate;
3524 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3525 if (op->from == ep->from && op->can_eliminate)
3526 {
3527 new_to = op->to;
3528 break;
3529 }
3530
3531 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3532 disable it. */
3533 for (op = reg_eliminate;
3534 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3535 if (op->from == new_to && op->to == ep->to)
3536 op->can_eliminate = 0;
3537 }
3538 }
3539
3540 /* See if any registers that we thought we could eliminate the previous
3541 time are no longer eliminable. If so, something has changed and we
3542 must spill the register. Also, recompute the number of eliminable
3543 registers and see if the frame pointer is needed; it is if there is
3544 no elimination of the frame pointer that we can perform. */
3545
3546 frame_pointer_needed = 1;
3547 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3548 {
3549 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3550 && ep->to != HARD_FRAME_POINTER_REGNUM)
3551 frame_pointer_needed = 0;
3552
3553 if (! ep->can_eliminate && ep->can_eliminate_previous)
3554 {
3555 ep->can_eliminate_previous = 0;
3556 SET_HARD_REG_BIT (*pset, ep->from);
3557 num_eliminable--;
3558 }
3559 }
3560
3561 /* If we didn't need a frame pointer last time, but we do now, spill
3562 the hard frame pointer. */
3563 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3564 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3565 }
3566
3567 /* Initialize the table of registers to eliminate. */
3568
3569 static void
init_elim_table(void)3570 init_elim_table (void)
3571 {
3572 struct elim_table *ep;
3573 #ifdef ELIMINABLE_REGS
3574 const struct elim_table_1 *ep1;
3575 #endif
3576
3577 if (!reg_eliminate)
3578 reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3579
3580 /* Does this function require a frame pointer? */
3581
3582 frame_pointer_needed = (! flag_omit_frame_pointer
3583 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3584 and restore sp for alloca. So we can't eliminate
3585 the frame pointer in that case. At some point,
3586 we should improve this by emitting the
3587 sp-adjusting insns for this case. */
3588 || (current_function_calls_alloca
3589 && EXIT_IGNORE_STACK)
3590 || current_function_accesses_prior_frames
3591 || FRAME_POINTER_REQUIRED);
3592
3593 num_eliminable = 0;
3594
3595 #ifdef ELIMINABLE_REGS
3596 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3597 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3598 {
3599 ep->from = ep1->from;
3600 ep->to = ep1->to;
3601 ep->can_eliminate = ep->can_eliminate_previous
3602 = (CAN_ELIMINATE (ep->from, ep->to)
3603 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3604 }
3605 #else
3606 reg_eliminate[0].from = reg_eliminate_1[0].from;
3607 reg_eliminate[0].to = reg_eliminate_1[0].to;
3608 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3609 = ! frame_pointer_needed;
3610 #endif
3611
3612 /* Count the number of eliminable registers and build the FROM and TO
3613 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3614 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3615 We depend on this. */
3616 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3617 {
3618 num_eliminable += ep->can_eliminate;
3619 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3620 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3621 }
3622 }
3623
3624 /* Kick all pseudos out of hard register REGNO.
3625
3626 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3627 because we found we can't eliminate some register. In the case, no pseudos
3628 are allowed to be in the register, even if they are only in a block that
3629 doesn't require spill registers, unlike the case when we are spilling this
3630 hard reg to produce another spill register.
3631
3632 Return nonzero if any pseudos needed to be kicked out. */
3633
3634 static void
spill_hard_reg(unsigned int regno,int cant_eliminate)3635 spill_hard_reg (unsigned int regno, int cant_eliminate)
3636 {
3637 int i;
3638
3639 if (cant_eliminate)
3640 {
3641 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3642 regs_ever_live[regno] = 1;
3643 }
3644
3645 /* Spill every pseudo reg that was allocated to this reg
3646 or to something that overlaps this reg. */
3647
3648 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3649 if (reg_renumber[i] >= 0
3650 && (unsigned int) reg_renumber[i] <= regno
3651 && ((unsigned int) reg_renumber[i]
3652 + hard_regno_nregs[(unsigned int) reg_renumber[i]]
3653 [PSEUDO_REGNO_MODE (i)]
3654 > regno))
3655 SET_REGNO_REG_SET (&spilled_pseudos, i);
3656 }
3657
3658 /* After find_reload_regs has been run for all insn that need reloads,
3659 and/or spill_hard_regs was called, this function is used to actually
3660 spill pseudo registers and try to reallocate them. It also sets up the
3661 spill_regs array for use by choose_reload_regs. */
3662
3663 static int
finish_spills(int global)3664 finish_spills (int global)
3665 {
3666 struct insn_chain *chain;
3667 int something_changed = 0;
3668 unsigned i;
3669 reg_set_iterator rsi;
3670
3671 /* Build the spill_regs array for the function. */
3672 /* If there are some registers still to eliminate and one of the spill regs
3673 wasn't ever used before, additional stack space may have to be
3674 allocated to store this register. Thus, we may have changed the offset
3675 between the stack and frame pointers, so mark that something has changed.
3676
3677 One might think that we need only set VAL to 1 if this is a call-used
3678 register. However, the set of registers that must be saved by the
3679 prologue is not identical to the call-used set. For example, the
3680 register used by the call insn for the return PC is a call-used register,
3681 but must be saved by the prologue. */
3682
3683 n_spills = 0;
3684 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3685 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3686 {
3687 spill_reg_order[i] = n_spills;
3688 spill_regs[n_spills++] = i;
3689 if (num_eliminable && ! regs_ever_live[i])
3690 something_changed = 1;
3691 regs_ever_live[i] = 1;
3692 }
3693 else
3694 spill_reg_order[i] = -1;
3695
3696 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
3697 {
3698 /* Record the current hard register the pseudo is allocated to in
3699 pseudo_previous_regs so we avoid reallocating it to the same
3700 hard reg in a later pass. */
3701 gcc_assert (reg_renumber[i] >= 0);
3702
3703 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3704 /* Mark it as no longer having a hard register home. */
3705 reg_renumber[i] = -1;
3706 /* We will need to scan everything again. */
3707 something_changed = 1;
3708 }
3709
3710 /* Retry global register allocation if possible. */
3711 if (global)
3712 {
3713 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3714 /* For every insn that needs reloads, set the registers used as spill
3715 regs in pseudo_forbidden_regs for every pseudo live across the
3716 insn. */
3717 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3718 {
3719 EXECUTE_IF_SET_IN_REG_SET
3720 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
3721 {
3722 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3723 chain->used_spill_regs);
3724 }
3725 EXECUTE_IF_SET_IN_REG_SET
3726 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
3727 {
3728 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3729 chain->used_spill_regs);
3730 }
3731 }
3732
3733 /* Retry allocating the spilled pseudos. For each reg, merge the
3734 various reg sets that indicate which hard regs can't be used,
3735 and call retry_global_alloc.
3736 We change spill_pseudos here to only contain pseudos that did not
3737 get a new hard register. */
3738 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3739 if (reg_old_renumber[i] != reg_renumber[i])
3740 {
3741 HARD_REG_SET forbidden;
3742 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3743 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3744 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3745 retry_global_alloc (i, forbidden);
3746 if (reg_renumber[i] >= 0)
3747 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3748 }
3749 }
3750
3751 /* Fix up the register information in the insn chain.
3752 This involves deleting those of the spilled pseudos which did not get
3753 a new hard register home from the live_{before,after} sets. */
3754 for (chain = reload_insn_chain; chain; chain = chain->next)
3755 {
3756 HARD_REG_SET used_by_pseudos;
3757 HARD_REG_SET used_by_pseudos2;
3758
3759 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3760 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3761
3762 /* Mark any unallocated hard regs as available for spills. That
3763 makes inheritance work somewhat better. */
3764 if (chain->need_reload)
3765 {
3766 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3767 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3768 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3769
3770 /* Save the old value for the sanity test below. */
3771 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3772
3773 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3774 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3775 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3776 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3777
3778 /* Make sure we only enlarge the set. */
3779 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3780 gcc_unreachable ();
3781 ok:;
3782 }
3783 }
3784
3785 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3786 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3787 {
3788 int regno = reg_renumber[i];
3789 if (reg_old_renumber[i] == regno)
3790 continue;
3791
3792 alter_reg (i, reg_old_renumber[i]);
3793 reg_old_renumber[i] = regno;
3794 if (dump_file)
3795 {
3796 if (regno == -1)
3797 fprintf (dump_file, " Register %d now on stack.\n\n", i);
3798 else
3799 fprintf (dump_file, " Register %d now in %d.\n\n",
3800 i, reg_renumber[i]);
3801 }
3802 }
3803
3804 return something_changed;
3805 }
3806
3807 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3808
3809 static void
scan_paradoxical_subregs(rtx x)3810 scan_paradoxical_subregs (rtx x)
3811 {
3812 int i;
3813 const char *fmt;
3814 enum rtx_code code = GET_CODE (x);
3815
3816 switch (code)
3817 {
3818 case REG:
3819 case CONST_INT:
3820 case CONST:
3821 case SYMBOL_REF:
3822 case LABEL_REF:
3823 case CONST_DOUBLE:
3824 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3825 case CC0:
3826 case PC:
3827 case USE:
3828 case CLOBBER:
3829 return;
3830
3831 case SUBREG:
3832 if (REG_P (SUBREG_REG (x))
3833 && (GET_MODE_SIZE (GET_MODE (x))
3834 > reg_max_ref_width[REGNO (SUBREG_REG (x))]))
3835 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3836 = GET_MODE_SIZE (GET_MODE (x));
3837 return;
3838
3839 default:
3840 break;
3841 }
3842
3843 fmt = GET_RTX_FORMAT (code);
3844 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3845 {
3846 if (fmt[i] == 'e')
3847 scan_paradoxical_subregs (XEXP (x, i));
3848 else if (fmt[i] == 'E')
3849 {
3850 int j;
3851 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3852 scan_paradoxical_subregs (XVECEXP (x, i, j));
3853 }
3854 }
3855 }
3856
3857 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
3858 examine all of the reload insns between PREV and NEXT exclusive, and
3859 annotate all that may trap. */
3860
3861 static void
fixup_eh_region_note(rtx insn,rtx prev,rtx next)3862 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
3863 {
3864 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
3865 unsigned int trap_count;
3866 rtx i;
3867
3868 if (note == NULL)
3869 return;
3870
3871 if (may_trap_p (PATTERN (insn)))
3872 trap_count = 1;
3873 else
3874 {
3875 remove_note (insn, note);
3876 trap_count = 0;
3877 }
3878
3879 for (i = NEXT_INSN (prev); i != next; i = NEXT_INSN (i))
3880 if (INSN_P (i) && i != insn && may_trap_p (PATTERN (i)))
3881 {
3882 trap_count++;
3883 REG_NOTES (i)
3884 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (note, 0), REG_NOTES (i));
3885 }
3886 }
3887
3888 /* Reload pseudo-registers into hard regs around each insn as needed.
3889 Additional register load insns are output before the insn that needs it
3890 and perhaps store insns after insns that modify the reloaded pseudo reg.
3891
3892 reg_last_reload_reg and reg_reloaded_contents keep track of
3893 which registers are already available in reload registers.
3894 We update these for the reloads that we perform,
3895 as the insns are scanned. */
3896
3897 static void
reload_as_needed(int live_known)3898 reload_as_needed (int live_known)
3899 {
3900 struct insn_chain *chain;
3901 #if defined (AUTO_INC_DEC)
3902 int i;
3903 #endif
3904 rtx x;
3905
3906 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
3907 memset (spill_reg_store, 0, sizeof spill_reg_store);
3908 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
3909 INIT_REG_SET (®_has_output_reload);
3910 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3911 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
3912
3913 set_initial_elim_offsets ();
3914
3915 for (chain = reload_insn_chain; chain; chain = chain->next)
3916 {
3917 rtx prev = 0;
3918 rtx insn = chain->insn;
3919 rtx old_next = NEXT_INSN (insn);
3920
3921 /* If we pass a label, copy the offsets from the label information
3922 into the current offsets of each elimination. */
3923 if (LABEL_P (insn))
3924 set_offsets_for_label (insn);
3925
3926 else if (INSN_P (insn))
3927 {
3928 regset_head regs_to_forget;
3929 INIT_REG_SET (®s_to_forget);
3930 note_stores (PATTERN (insn), forget_old_reloads_1, ®s_to_forget);
3931
3932 /* If this is a USE and CLOBBER of a MEM, ensure that any
3933 references to eliminable registers have been removed. */
3934
3935 if ((GET_CODE (PATTERN (insn)) == USE
3936 || GET_CODE (PATTERN (insn)) == CLOBBER)
3937 && MEM_P (XEXP (PATTERN (insn), 0)))
3938 XEXP (XEXP (PATTERN (insn), 0), 0)
3939 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3940 GET_MODE (XEXP (PATTERN (insn), 0)),
3941 NULL_RTX);
3942
3943 /* If we need to do register elimination processing, do so.
3944 This might delete the insn, in which case we are done. */
3945 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3946 {
3947 eliminate_regs_in_insn (insn, 1);
3948 if (NOTE_P (insn))
3949 {
3950 update_eliminable_offsets ();
3951 CLEAR_REG_SET (®s_to_forget);
3952 continue;
3953 }
3954 }
3955
3956 /* If need_elim is nonzero but need_reload is zero, one might think
3957 that we could simply set n_reloads to 0. However, find_reloads
3958 could have done some manipulation of the insn (such as swapping
3959 commutative operands), and these manipulations are lost during
3960 the first pass for every insn that needs register elimination.
3961 So the actions of find_reloads must be redone here. */
3962
3963 if (! chain->need_elim && ! chain->need_reload
3964 && ! chain->need_operand_change)
3965 n_reloads = 0;
3966 /* First find the pseudo regs that must be reloaded for this insn.
3967 This info is returned in the tables reload_... (see reload.h).
3968 Also modify the body of INSN by substituting RELOAD
3969 rtx's for those pseudo regs. */
3970 else
3971 {
3972 CLEAR_REG_SET (®_has_output_reload);
3973 CLEAR_HARD_REG_SET (reg_is_output_reload);
3974
3975 find_reloads (insn, 1, spill_indirect_levels, live_known,
3976 spill_reg_order);
3977 }
3978
3979 if (n_reloads > 0)
3980 {
3981 rtx next = NEXT_INSN (insn);
3982 rtx p;
3983
3984 prev = PREV_INSN (insn);
3985
3986 /* Now compute which reload regs to reload them into. Perhaps
3987 reusing reload regs from previous insns, or else output
3988 load insns to reload them. Maybe output store insns too.
3989 Record the choices of reload reg in reload_reg_rtx. */
3990 choose_reload_regs (chain);
3991
3992 /* Merge any reloads that we didn't combine for fear of
3993 increasing the number of spill registers needed but now
3994 discover can be safely merged. */
3995 if (SMALL_REGISTER_CLASSES)
3996 merge_assigned_reloads (insn);
3997
3998 /* Generate the insns to reload operands into or out of
3999 their reload regs. */
4000 emit_reload_insns (chain);
4001
4002 /* Substitute the chosen reload regs from reload_reg_rtx
4003 into the insn's body (or perhaps into the bodies of other
4004 load and store insn that we just made for reloading
4005 and that we moved the structure into). */
4006 subst_reloads (insn);
4007
4008 /* Adjust the exception region notes for loads and stores. */
4009 if (flag_non_call_exceptions && !CALL_P (insn))
4010 fixup_eh_region_note (insn, prev, next);
4011
4012 /* If this was an ASM, make sure that all the reload insns
4013 we have generated are valid. If not, give an error
4014 and delete them. */
4015 if (asm_noperands (PATTERN (insn)) >= 0)
4016 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4017 if (p != insn && INSN_P (p)
4018 && GET_CODE (PATTERN (p)) != USE
4019 && (recog_memoized (p) < 0
4020 || (extract_insn (p), ! constrain_operands (1))))
4021 {
4022 error_for_asm (insn,
4023 "%<asm%> operand requires "
4024 "impossible reload");
4025 delete_insn (p);
4026 }
4027 }
4028
4029 if (num_eliminable && chain->need_elim)
4030 update_eliminable_offsets ();
4031
4032 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4033 is no longer validly lying around to save a future reload.
4034 Note that this does not detect pseudos that were reloaded
4035 for this insn in order to be stored in
4036 (obeying register constraints). That is correct; such reload
4037 registers ARE still valid. */
4038 forget_marked_reloads (®s_to_forget);
4039 CLEAR_REG_SET (®s_to_forget);
4040
4041 /* There may have been CLOBBER insns placed after INSN. So scan
4042 between INSN and NEXT and use them to forget old reloads. */
4043 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4044 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4045 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4046
4047 #ifdef AUTO_INC_DEC
4048 /* Likewise for regs altered by auto-increment in this insn.
4049 REG_INC notes have been changed by reloading:
4050 find_reloads_address_1 records substitutions for them,
4051 which have been performed by subst_reloads above. */
4052 for (i = n_reloads - 1; i >= 0; i--)
4053 {
4054 rtx in_reg = rld[i].in_reg;
4055 if (in_reg)
4056 {
4057 enum rtx_code code = GET_CODE (in_reg);
4058 /* PRE_INC / PRE_DEC will have the reload register ending up
4059 with the same value as the stack slot, but that doesn't
4060 hold true for POST_INC / POST_DEC. Either we have to
4061 convert the memory access to a true POST_INC / POST_DEC,
4062 or we can't use the reload register for inheritance. */
4063 if ((code == POST_INC || code == POST_DEC)
4064 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4065 REGNO (rld[i].reg_rtx))
4066 /* Make sure it is the inc/dec pseudo, and not
4067 some other (e.g. output operand) pseudo. */
4068 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4069 == REGNO (XEXP (in_reg, 0))))
4070
4071 {
4072 rtx reload_reg = rld[i].reg_rtx;
4073 enum machine_mode mode = GET_MODE (reload_reg);
4074 int n = 0;
4075 rtx p;
4076
4077 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4078 {
4079 /* We really want to ignore REG_INC notes here, so
4080 use PATTERN (p) as argument to reg_set_p . */
4081 if (reg_set_p (reload_reg, PATTERN (p)))
4082 break;
4083 n = count_occurrences (PATTERN (p), reload_reg, 0);
4084 if (! n)
4085 continue;
4086 if (n == 1)
4087 {
4088 n = validate_replace_rtx (reload_reg,
4089 gen_rtx_fmt_e (code,
4090 mode,
4091 reload_reg),
4092 p);
4093
4094 /* We must also verify that the constraints
4095 are met after the replacement. */
4096 extract_insn (p);
4097 if (n)
4098 n = constrain_operands (1);
4099 else
4100 break;
4101
4102 /* If the constraints were not met, then
4103 undo the replacement. */
4104 if (!n)
4105 {
4106 validate_replace_rtx (gen_rtx_fmt_e (code,
4107 mode,
4108 reload_reg),
4109 reload_reg, p);
4110 break;
4111 }
4112
4113 }
4114 break;
4115 }
4116 if (n == 1)
4117 {
4118 REG_NOTES (p)
4119 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4120 REG_NOTES (p));
4121 /* Mark this as having an output reload so that the
4122 REG_INC processing code below won't invalidate
4123 the reload for inheritance. */
4124 SET_HARD_REG_BIT (reg_is_output_reload,
4125 REGNO (reload_reg));
4126 SET_REGNO_REG_SET (®_has_output_reload,
4127 REGNO (XEXP (in_reg, 0)));
4128 }
4129 else
4130 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4131 NULL);
4132 }
4133 else if ((code == PRE_INC || code == PRE_DEC)
4134 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4135 REGNO (rld[i].reg_rtx))
4136 /* Make sure it is the inc/dec pseudo, and not
4137 some other (e.g. output operand) pseudo. */
4138 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4139 == REGNO (XEXP (in_reg, 0))))
4140 {
4141 SET_HARD_REG_BIT (reg_is_output_reload,
4142 REGNO (rld[i].reg_rtx));
4143 SET_REGNO_REG_SET (®_has_output_reload,
4144 REGNO (XEXP (in_reg, 0)));
4145 }
4146 }
4147 }
4148 /* If a pseudo that got a hard register is auto-incremented,
4149 we must purge records of copying it into pseudos without
4150 hard registers. */
4151 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4152 if (REG_NOTE_KIND (x) == REG_INC)
4153 {
4154 /* See if this pseudo reg was reloaded in this insn.
4155 If so, its last-reload info is still valid
4156 because it is based on this insn's reload. */
4157 for (i = 0; i < n_reloads; i++)
4158 if (rld[i].out == XEXP (x, 0))
4159 break;
4160
4161 if (i == n_reloads)
4162 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4163 }
4164 #endif
4165 }
4166 /* A reload reg's contents are unknown after a label. */
4167 if (LABEL_P (insn))
4168 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4169
4170 /* Don't assume a reload reg is still good after a call insn
4171 if it is a call-used reg, or if it contains a value that will
4172 be partially clobbered by the call. */
4173 else if (CALL_P (insn))
4174 {
4175 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4176 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4177 }
4178 }
4179
4180 /* Clean up. */
4181 free (reg_last_reload_reg);
4182 CLEAR_REG_SET (®_has_output_reload);
4183 }
4184
4185 /* Discard all record of any value reloaded from X,
4186 or reloaded in X from someplace else;
4187 unless X is an output reload reg of the current insn.
4188
4189 X may be a hard reg (the reload reg)
4190 or it may be a pseudo reg that was reloaded from.
4191
4192 When DATA is non-NULL just mark the registers in regset
4193 to be forgotten later. */
4194
4195 static void
forget_old_reloads_1(rtx x,rtx ignored ATTRIBUTE_UNUSED,void * data)4196 forget_old_reloads_1 (rtx x, rtx ignored ATTRIBUTE_UNUSED,
4197 void *data)
4198 {
4199 unsigned int regno;
4200 unsigned int nr;
4201 regset regs = (regset) data;
4202
4203 /* note_stores does give us subregs of hard regs,
4204 subreg_regno_offset requires a hard reg. */
4205 while (GET_CODE (x) == SUBREG)
4206 {
4207 /* We ignore the subreg offset when calculating the regno,
4208 because we are using the entire underlying hard register
4209 below. */
4210 x = SUBREG_REG (x);
4211 }
4212
4213 if (!REG_P (x))
4214 return;
4215
4216 regno = REGNO (x);
4217
4218 if (regno >= FIRST_PSEUDO_REGISTER)
4219 nr = 1;
4220 else
4221 {
4222 unsigned int i;
4223
4224 nr = hard_regno_nregs[regno][GET_MODE (x)];
4225 /* Storing into a spilled-reg invalidates its contents.
4226 This can happen if a block-local pseudo is allocated to that reg
4227 and it wasn't spilled because this block's total need is 0.
4228 Then some insn might have an optional reload and use this reg. */
4229 if (!regs)
4230 for (i = 0; i < nr; i++)
4231 /* But don't do this if the reg actually serves as an output
4232 reload reg in the current instruction. */
4233 if (n_reloads == 0
4234 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4235 {
4236 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4237 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, regno + i);
4238 spill_reg_store[regno + i] = 0;
4239 }
4240 }
4241
4242 if (regs)
4243 while (nr-- > 0)
4244 SET_REGNO_REG_SET (regs, regno + nr);
4245 else
4246 {
4247 /* Since value of X has changed,
4248 forget any value previously copied from it. */
4249
4250 while (nr-- > 0)
4251 /* But don't forget a copy if this is the output reload
4252 that establishes the copy's validity. */
4253 if (n_reloads == 0
4254 || !REGNO_REG_SET_P (®_has_output_reload, regno + nr))
4255 reg_last_reload_reg[regno + nr] = 0;
4256 }
4257 }
4258
4259 /* Forget the reloads marked in regset by previous function. */
4260 static void
forget_marked_reloads(regset regs)4261 forget_marked_reloads (regset regs)
4262 {
4263 unsigned int reg;
4264 reg_set_iterator rsi;
4265 EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4266 {
4267 if (reg < FIRST_PSEUDO_REGISTER
4268 /* But don't do this if the reg actually serves as an output
4269 reload reg in the current instruction. */
4270 && (n_reloads == 0
4271 || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4272 {
4273 CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4274 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, reg);
4275 spill_reg_store[reg] = 0;
4276 }
4277 if (n_reloads == 0
4278 || !REGNO_REG_SET_P (®_has_output_reload, reg))
4279 reg_last_reload_reg[reg] = 0;
4280 }
4281 }
4282
4283 /* The following HARD_REG_SETs indicate when each hard register is
4284 used for a reload of various parts of the current insn. */
4285
4286 /* If reg is unavailable for all reloads. */
4287 static HARD_REG_SET reload_reg_unavailable;
4288 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4289 static HARD_REG_SET reload_reg_used;
4290 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4291 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4292 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4293 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4294 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4295 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4296 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4297 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4298 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4299 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4300 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4301 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4302 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4303 static HARD_REG_SET reload_reg_used_in_op_addr;
4304 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4305 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4306 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4307 static HARD_REG_SET reload_reg_used_in_insn;
4308 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4309 static HARD_REG_SET reload_reg_used_in_other_addr;
4310
4311 /* If reg is in use as a reload reg for any sort of reload. */
4312 static HARD_REG_SET reload_reg_used_at_all;
4313
4314 /* If reg is use as an inherited reload. We just mark the first register
4315 in the group. */
4316 static HARD_REG_SET reload_reg_used_for_inherit;
4317
4318 /* Records which hard regs are used in any way, either as explicit use or
4319 by being allocated to a pseudo during any point of the current insn. */
4320 static HARD_REG_SET reg_used_in_insn;
4321
4322 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4323 TYPE. MODE is used to indicate how many consecutive regs are
4324 actually used. */
4325
4326 static void
mark_reload_reg_in_use(unsigned int regno,int opnum,enum reload_type type,enum machine_mode mode)4327 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4328 enum machine_mode mode)
4329 {
4330 unsigned int nregs = hard_regno_nregs[regno][mode];
4331 unsigned int i;
4332
4333 for (i = regno; i < nregs + regno; i++)
4334 {
4335 switch (type)
4336 {
4337 case RELOAD_OTHER:
4338 SET_HARD_REG_BIT (reload_reg_used, i);
4339 break;
4340
4341 case RELOAD_FOR_INPUT_ADDRESS:
4342 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4343 break;
4344
4345 case RELOAD_FOR_INPADDR_ADDRESS:
4346 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4347 break;
4348
4349 case RELOAD_FOR_OUTPUT_ADDRESS:
4350 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4351 break;
4352
4353 case RELOAD_FOR_OUTADDR_ADDRESS:
4354 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4355 break;
4356
4357 case RELOAD_FOR_OPERAND_ADDRESS:
4358 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4359 break;
4360
4361 case RELOAD_FOR_OPADDR_ADDR:
4362 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4363 break;
4364
4365 case RELOAD_FOR_OTHER_ADDRESS:
4366 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4367 break;
4368
4369 case RELOAD_FOR_INPUT:
4370 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4371 break;
4372
4373 case RELOAD_FOR_OUTPUT:
4374 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4375 break;
4376
4377 case RELOAD_FOR_INSN:
4378 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4379 break;
4380 }
4381
4382 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4383 }
4384 }
4385
4386 /* Similarly, but show REGNO is no longer in use for a reload. */
4387
4388 static void
clear_reload_reg_in_use(unsigned int regno,int opnum,enum reload_type type,enum machine_mode mode)4389 clear_reload_reg_in_use (unsigned int regno, int opnum,
4390 enum reload_type type, enum machine_mode mode)
4391 {
4392 unsigned int nregs = hard_regno_nregs[regno][mode];
4393 unsigned int start_regno, end_regno, r;
4394 int i;
4395 /* A complication is that for some reload types, inheritance might
4396 allow multiple reloads of the same types to share a reload register.
4397 We set check_opnum if we have to check only reloads with the same
4398 operand number, and check_any if we have to check all reloads. */
4399 int check_opnum = 0;
4400 int check_any = 0;
4401 HARD_REG_SET *used_in_set;
4402
4403 switch (type)
4404 {
4405 case RELOAD_OTHER:
4406 used_in_set = &reload_reg_used;
4407 break;
4408
4409 case RELOAD_FOR_INPUT_ADDRESS:
4410 used_in_set = &reload_reg_used_in_input_addr[opnum];
4411 break;
4412
4413 case RELOAD_FOR_INPADDR_ADDRESS:
4414 check_opnum = 1;
4415 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4416 break;
4417
4418 case RELOAD_FOR_OUTPUT_ADDRESS:
4419 used_in_set = &reload_reg_used_in_output_addr[opnum];
4420 break;
4421
4422 case RELOAD_FOR_OUTADDR_ADDRESS:
4423 check_opnum = 1;
4424 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4425 break;
4426
4427 case RELOAD_FOR_OPERAND_ADDRESS:
4428 used_in_set = &reload_reg_used_in_op_addr;
4429 break;
4430
4431 case RELOAD_FOR_OPADDR_ADDR:
4432 check_any = 1;
4433 used_in_set = &reload_reg_used_in_op_addr_reload;
4434 break;
4435
4436 case RELOAD_FOR_OTHER_ADDRESS:
4437 used_in_set = &reload_reg_used_in_other_addr;
4438 check_any = 1;
4439 break;
4440
4441 case RELOAD_FOR_INPUT:
4442 used_in_set = &reload_reg_used_in_input[opnum];
4443 break;
4444
4445 case RELOAD_FOR_OUTPUT:
4446 used_in_set = &reload_reg_used_in_output[opnum];
4447 break;
4448
4449 case RELOAD_FOR_INSN:
4450 used_in_set = &reload_reg_used_in_insn;
4451 break;
4452 default:
4453 gcc_unreachable ();
4454 }
4455 /* We resolve conflicts with remaining reloads of the same type by
4456 excluding the intervals of reload registers by them from the
4457 interval of freed reload registers. Since we only keep track of
4458 one set of interval bounds, we might have to exclude somewhat
4459 more than what would be necessary if we used a HARD_REG_SET here.
4460 But this should only happen very infrequently, so there should
4461 be no reason to worry about it. */
4462
4463 start_regno = regno;
4464 end_regno = regno + nregs;
4465 if (check_opnum || check_any)
4466 {
4467 for (i = n_reloads - 1; i >= 0; i--)
4468 {
4469 if (rld[i].when_needed == type
4470 && (check_any || rld[i].opnum == opnum)
4471 && rld[i].reg_rtx)
4472 {
4473 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4474 unsigned int conflict_end
4475 = (conflict_start
4476 + hard_regno_nregs[conflict_start][rld[i].mode]);
4477
4478 /* If there is an overlap with the first to-be-freed register,
4479 adjust the interval start. */
4480 if (conflict_start <= start_regno && conflict_end > start_regno)
4481 start_regno = conflict_end;
4482 /* Otherwise, if there is a conflict with one of the other
4483 to-be-freed registers, adjust the interval end. */
4484 if (conflict_start > start_regno && conflict_start < end_regno)
4485 end_regno = conflict_start;
4486 }
4487 }
4488 }
4489
4490 for (r = start_regno; r < end_regno; r++)
4491 CLEAR_HARD_REG_BIT (*used_in_set, r);
4492 }
4493
4494 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4495 specified by OPNUM and TYPE. */
4496
4497 static int
reload_reg_free_p(unsigned int regno,int opnum,enum reload_type type)4498 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4499 {
4500 int i;
4501
4502 /* In use for a RELOAD_OTHER means it's not available for anything. */
4503 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4504 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4505 return 0;
4506
4507 switch (type)
4508 {
4509 case RELOAD_OTHER:
4510 /* In use for anything means we can't use it for RELOAD_OTHER. */
4511 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4512 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4513 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4514 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4515 return 0;
4516
4517 for (i = 0; i < reload_n_operands; i++)
4518 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4519 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4520 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4521 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4522 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4523 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4524 return 0;
4525
4526 return 1;
4527
4528 case RELOAD_FOR_INPUT:
4529 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4530 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4531 return 0;
4532
4533 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4534 return 0;
4535
4536 /* If it is used for some other input, can't use it. */
4537 for (i = 0; i < reload_n_operands; i++)
4538 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4539 return 0;
4540
4541 /* If it is used in a later operand's address, can't use it. */
4542 for (i = opnum + 1; i < reload_n_operands; i++)
4543 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4544 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4545 return 0;
4546
4547 return 1;
4548
4549 case RELOAD_FOR_INPUT_ADDRESS:
4550 /* Can't use a register if it is used for an input address for this
4551 operand or used as an input in an earlier one. */
4552 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4553 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4554 return 0;
4555
4556 for (i = 0; i < opnum; i++)
4557 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4558 return 0;
4559
4560 return 1;
4561
4562 case RELOAD_FOR_INPADDR_ADDRESS:
4563 /* Can't use a register if it is used for an input address
4564 for this operand or used as an input in an earlier
4565 one. */
4566 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4567 return 0;
4568
4569 for (i = 0; i < opnum; i++)
4570 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4571 return 0;
4572
4573 return 1;
4574
4575 case RELOAD_FOR_OUTPUT_ADDRESS:
4576 /* Can't use a register if it is used for an output address for this
4577 operand or used as an output in this or a later operand. Note
4578 that multiple output operands are emitted in reverse order, so
4579 the conflicting ones are those with lower indices. */
4580 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4581 return 0;
4582
4583 for (i = 0; i <= opnum; i++)
4584 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4585 return 0;
4586
4587 return 1;
4588
4589 case RELOAD_FOR_OUTADDR_ADDRESS:
4590 /* Can't use a register if it is used for an output address
4591 for this operand or used as an output in this or a
4592 later operand. Note that multiple output operands are
4593 emitted in reverse order, so the conflicting ones are
4594 those with lower indices. */
4595 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4596 return 0;
4597
4598 for (i = 0; i <= opnum; i++)
4599 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4600 return 0;
4601
4602 return 1;
4603
4604 case RELOAD_FOR_OPERAND_ADDRESS:
4605 for (i = 0; i < reload_n_operands; i++)
4606 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4607 return 0;
4608
4609 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4610 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4611
4612 case RELOAD_FOR_OPADDR_ADDR:
4613 for (i = 0; i < reload_n_operands; i++)
4614 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4615 return 0;
4616
4617 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4618
4619 case RELOAD_FOR_OUTPUT:
4620 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4621 outputs, or an operand address for this or an earlier output.
4622 Note that multiple output operands are emitted in reverse order,
4623 so the conflicting ones are those with higher indices. */
4624 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4625 return 0;
4626
4627 for (i = 0; i < reload_n_operands; i++)
4628 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4629 return 0;
4630
4631 for (i = opnum; i < reload_n_operands; i++)
4632 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4633 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4634 return 0;
4635
4636 return 1;
4637
4638 case RELOAD_FOR_INSN:
4639 for (i = 0; i < reload_n_operands; i++)
4640 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4641 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4642 return 0;
4643
4644 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4645 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4646
4647 case RELOAD_FOR_OTHER_ADDRESS:
4648 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4649
4650 default:
4651 gcc_unreachable ();
4652 }
4653 }
4654
4655 /* Return 1 if the value in reload reg REGNO, as used by a reload
4656 needed for the part of the insn specified by OPNUM and TYPE,
4657 is still available in REGNO at the end of the insn.
4658
4659 We can assume that the reload reg was already tested for availability
4660 at the time it is needed, and we should not check this again,
4661 in case the reg has already been marked in use. */
4662
4663 static int
reload_reg_reaches_end_p(unsigned int regno,int opnum,enum reload_type type)4664 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4665 {
4666 int i;
4667
4668 switch (type)
4669 {
4670 case RELOAD_OTHER:
4671 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4672 its value must reach the end. */
4673 return 1;
4674
4675 /* If this use is for part of the insn,
4676 its value reaches if no subsequent part uses the same register.
4677 Just like the above function, don't try to do this with lots
4678 of fallthroughs. */
4679
4680 case RELOAD_FOR_OTHER_ADDRESS:
4681 /* Here we check for everything else, since these don't conflict
4682 with anything else and everything comes later. */
4683
4684 for (i = 0; i < reload_n_operands; i++)
4685 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4686 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4687 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4688 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4689 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4690 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4691 return 0;
4692
4693 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4694 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4695 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4696 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4697
4698 case RELOAD_FOR_INPUT_ADDRESS:
4699 case RELOAD_FOR_INPADDR_ADDRESS:
4700 /* Similar, except that we check only for this and subsequent inputs
4701 and the address of only subsequent inputs and we do not need
4702 to check for RELOAD_OTHER objects since they are known not to
4703 conflict. */
4704
4705 for (i = opnum; i < reload_n_operands; i++)
4706 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4707 return 0;
4708
4709 for (i = opnum + 1; i < reload_n_operands; i++)
4710 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4711 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4712 return 0;
4713
4714 for (i = 0; i < reload_n_operands; i++)
4715 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4716 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4717 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4718 return 0;
4719
4720 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4721 return 0;
4722
4723 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4724 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4725 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4726
4727 case RELOAD_FOR_INPUT:
4728 /* Similar to input address, except we start at the next operand for
4729 both input and input address and we do not check for
4730 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4731 would conflict. */
4732
4733 for (i = opnum + 1; i < reload_n_operands; i++)
4734 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4735 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4736 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4737 return 0;
4738
4739 /* ... fall through ... */
4740
4741 case RELOAD_FOR_OPERAND_ADDRESS:
4742 /* Check outputs and their addresses. */
4743
4744 for (i = 0; i < reload_n_operands; i++)
4745 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4746 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4747 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4748 return 0;
4749
4750 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4751
4752 case RELOAD_FOR_OPADDR_ADDR:
4753 for (i = 0; i < reload_n_operands; i++)
4754 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4755 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4756 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4757 return 0;
4758
4759 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4760 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4761 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4762
4763 case RELOAD_FOR_INSN:
4764 /* These conflict with other outputs with RELOAD_OTHER. So
4765 we need only check for output addresses. */
4766
4767 opnum = reload_n_operands;
4768
4769 /* ... fall through ... */
4770
4771 case RELOAD_FOR_OUTPUT:
4772 case RELOAD_FOR_OUTPUT_ADDRESS:
4773 case RELOAD_FOR_OUTADDR_ADDRESS:
4774 /* We already know these can't conflict with a later output. So the
4775 only thing to check are later output addresses.
4776 Note that multiple output operands are emitted in reverse order,
4777 so the conflicting ones are those with lower indices. */
4778 for (i = 0; i < opnum; i++)
4779 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4780 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4781 return 0;
4782
4783 return 1;
4784
4785 default:
4786 gcc_unreachable ();
4787 }
4788 }
4789
4790 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4791 Return 0 otherwise.
4792
4793 This function uses the same algorithm as reload_reg_free_p above. */
4794
4795 static int
reloads_conflict(int r1,int r2)4796 reloads_conflict (int r1, int r2)
4797 {
4798 enum reload_type r1_type = rld[r1].when_needed;
4799 enum reload_type r2_type = rld[r2].when_needed;
4800 int r1_opnum = rld[r1].opnum;
4801 int r2_opnum = rld[r2].opnum;
4802
4803 /* RELOAD_OTHER conflicts with everything. */
4804 if (r2_type == RELOAD_OTHER)
4805 return 1;
4806
4807 /* Otherwise, check conflicts differently for each type. */
4808
4809 switch (r1_type)
4810 {
4811 case RELOAD_FOR_INPUT:
4812 return (r2_type == RELOAD_FOR_INSN
4813 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4814 || r2_type == RELOAD_FOR_OPADDR_ADDR
4815 || r2_type == RELOAD_FOR_INPUT
4816 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4817 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4818 && r2_opnum > r1_opnum));
4819
4820 case RELOAD_FOR_INPUT_ADDRESS:
4821 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4822 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4823
4824 case RELOAD_FOR_INPADDR_ADDRESS:
4825 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4826 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4827
4828 case RELOAD_FOR_OUTPUT_ADDRESS:
4829 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4830 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4831
4832 case RELOAD_FOR_OUTADDR_ADDRESS:
4833 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4834 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4835
4836 case RELOAD_FOR_OPERAND_ADDRESS:
4837 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4838 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4839
4840 case RELOAD_FOR_OPADDR_ADDR:
4841 return (r2_type == RELOAD_FOR_INPUT
4842 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4843
4844 case RELOAD_FOR_OUTPUT:
4845 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4846 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4847 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4848 && r2_opnum >= r1_opnum));
4849
4850 case RELOAD_FOR_INSN:
4851 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4852 || r2_type == RELOAD_FOR_INSN
4853 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4854
4855 case RELOAD_FOR_OTHER_ADDRESS:
4856 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4857
4858 case RELOAD_OTHER:
4859 return 1;
4860
4861 default:
4862 gcc_unreachable ();
4863 }
4864 }
4865
4866 /* Indexed by reload number, 1 if incoming value
4867 inherited from previous insns. */
4868 static char reload_inherited[MAX_RELOADS];
4869
4870 /* For an inherited reload, this is the insn the reload was inherited from,
4871 if we know it. Otherwise, this is 0. */
4872 static rtx reload_inheritance_insn[MAX_RELOADS];
4873
4874 /* If nonzero, this is a place to get the value of the reload,
4875 rather than using reload_in. */
4876 static rtx reload_override_in[MAX_RELOADS];
4877
4878 /* For each reload, the hard register number of the register used,
4879 or -1 if we did not need a register for this reload. */
4880 static int reload_spill_index[MAX_RELOADS];
4881
4882 /* Subroutine of free_for_value_p, used to check a single register.
4883 START_REGNO is the starting regno of the full reload register
4884 (possibly comprising multiple hard registers) that we are considering. */
4885
4886 static int
reload_reg_free_for_value_p(int start_regno,int regno,int opnum,enum reload_type type,rtx value,rtx out,int reloadnum,int ignore_address_reloads)4887 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
4888 enum reload_type type, rtx value, rtx out,
4889 int reloadnum, int ignore_address_reloads)
4890 {
4891 int time1;
4892 /* Set if we see an input reload that must not share its reload register
4893 with any new earlyclobber, but might otherwise share the reload
4894 register with an output or input-output reload. */
4895 int check_earlyclobber = 0;
4896 int i;
4897 int copy = 0;
4898
4899 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4900 return 0;
4901
4902 if (out == const0_rtx)
4903 {
4904 copy = 1;
4905 out = NULL_RTX;
4906 }
4907
4908 /* We use some pseudo 'time' value to check if the lifetimes of the
4909 new register use would overlap with the one of a previous reload
4910 that is not read-only or uses a different value.
4911 The 'time' used doesn't have to be linear in any shape or form, just
4912 monotonic.
4913 Some reload types use different 'buckets' for each operand.
4914 So there are MAX_RECOG_OPERANDS different time values for each
4915 such reload type.
4916 We compute TIME1 as the time when the register for the prospective
4917 new reload ceases to be live, and TIME2 for each existing
4918 reload as the time when that the reload register of that reload
4919 becomes live.
4920 Where there is little to be gained by exact lifetime calculations,
4921 we just make conservative assumptions, i.e. a longer lifetime;
4922 this is done in the 'default:' cases. */
4923 switch (type)
4924 {
4925 case RELOAD_FOR_OTHER_ADDRESS:
4926 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4927 time1 = copy ? 0 : 1;
4928 break;
4929 case RELOAD_OTHER:
4930 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4931 break;
4932 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4933 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4934 respectively, to the time values for these, we get distinct time
4935 values. To get distinct time values for each operand, we have to
4936 multiply opnum by at least three. We round that up to four because
4937 multiply by four is often cheaper. */
4938 case RELOAD_FOR_INPADDR_ADDRESS:
4939 time1 = opnum * 4 + 2;
4940 break;
4941 case RELOAD_FOR_INPUT_ADDRESS:
4942 time1 = opnum * 4 + 3;
4943 break;
4944 case RELOAD_FOR_INPUT:
4945 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4946 executes (inclusive). */
4947 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4948 break;
4949 case RELOAD_FOR_OPADDR_ADDR:
4950 /* opnum * 4 + 4
4951 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4952 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4953 break;
4954 case RELOAD_FOR_OPERAND_ADDRESS:
4955 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4956 is executed. */
4957 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4958 break;
4959 case RELOAD_FOR_OUTADDR_ADDRESS:
4960 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4961 break;
4962 case RELOAD_FOR_OUTPUT_ADDRESS:
4963 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4964 break;
4965 default:
4966 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4967 }
4968
4969 for (i = 0; i < n_reloads; i++)
4970 {
4971 rtx reg = rld[i].reg_rtx;
4972 if (reg && REG_P (reg)
4973 && ((unsigned) regno - true_regnum (reg)
4974 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
4975 && i != reloadnum)
4976 {
4977 rtx other_input = rld[i].in;
4978
4979 /* If the other reload loads the same input value, that
4980 will not cause a conflict only if it's loading it into
4981 the same register. */
4982 if (true_regnum (reg) != start_regno)
4983 other_input = NULL_RTX;
4984 if (! other_input || ! rtx_equal_p (other_input, value)
4985 || rld[i].out || out)
4986 {
4987 int time2;
4988 switch (rld[i].when_needed)
4989 {
4990 case RELOAD_FOR_OTHER_ADDRESS:
4991 time2 = 0;
4992 break;
4993 case RELOAD_FOR_INPADDR_ADDRESS:
4994 /* find_reloads makes sure that a
4995 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4996 by at most one - the first -
4997 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4998 address reload is inherited, the address address reload
4999 goes away, so we can ignore this conflict. */
5000 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5001 && ignore_address_reloads
5002 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5003 Then the address address is still needed to store
5004 back the new address. */
5005 && ! rld[reloadnum].out)
5006 continue;
5007 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5008 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5009 reloads go away. */
5010 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5011 && ignore_address_reloads
5012 /* Unless we are reloading an auto_inc expression. */
5013 && ! rld[reloadnum].out)
5014 continue;
5015 time2 = rld[i].opnum * 4 + 2;
5016 break;
5017 case RELOAD_FOR_INPUT_ADDRESS:
5018 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5019 && ignore_address_reloads
5020 && ! rld[reloadnum].out)
5021 continue;
5022 time2 = rld[i].opnum * 4 + 3;
5023 break;
5024 case RELOAD_FOR_INPUT:
5025 time2 = rld[i].opnum * 4 + 4;
5026 check_earlyclobber = 1;
5027 break;
5028 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5029 == MAX_RECOG_OPERAND * 4 */
5030 case RELOAD_FOR_OPADDR_ADDR:
5031 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5032 && ignore_address_reloads
5033 && ! rld[reloadnum].out)
5034 continue;
5035 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5036 break;
5037 case RELOAD_FOR_OPERAND_ADDRESS:
5038 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5039 check_earlyclobber = 1;
5040 break;
5041 case RELOAD_FOR_INSN:
5042 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5043 break;
5044 case RELOAD_FOR_OUTPUT:
5045 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5046 instruction is executed. */
5047 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5048 break;
5049 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5050 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5051 value. */
5052 case RELOAD_FOR_OUTADDR_ADDRESS:
5053 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5054 && ignore_address_reloads
5055 && ! rld[reloadnum].out)
5056 continue;
5057 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5058 break;
5059 case RELOAD_FOR_OUTPUT_ADDRESS:
5060 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5061 break;
5062 case RELOAD_OTHER:
5063 /* If there is no conflict in the input part, handle this
5064 like an output reload. */
5065 if (! rld[i].in || rtx_equal_p (other_input, value))
5066 {
5067 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5068 /* Earlyclobbered outputs must conflict with inputs. */
5069 if (earlyclobber_operand_p (rld[i].out))
5070 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5071
5072 break;
5073 }
5074 time2 = 1;
5075 /* RELOAD_OTHER might be live beyond instruction execution,
5076 but this is not obvious when we set time2 = 1. So check
5077 here if there might be a problem with the new reload
5078 clobbering the register used by the RELOAD_OTHER. */
5079 if (out)
5080 return 0;
5081 break;
5082 default:
5083 return 0;
5084 }
5085 if ((time1 >= time2
5086 && (! rld[i].in || rld[i].out
5087 || ! rtx_equal_p (other_input, value)))
5088 || (out && rld[reloadnum].out_reg
5089 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5090 return 0;
5091 }
5092 }
5093 }
5094
5095 /* Earlyclobbered outputs must conflict with inputs. */
5096 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5097 return 0;
5098
5099 return 1;
5100 }
5101
5102 /* Return 1 if the value in reload reg REGNO, as used by a reload
5103 needed for the part of the insn specified by OPNUM and TYPE,
5104 may be used to load VALUE into it.
5105
5106 MODE is the mode in which the register is used, this is needed to
5107 determine how many hard regs to test.
5108
5109 Other read-only reloads with the same value do not conflict
5110 unless OUT is nonzero and these other reloads have to live while
5111 output reloads live.
5112 If OUT is CONST0_RTX, this is a special case: it means that the
5113 test should not be for using register REGNO as reload register, but
5114 for copying from register REGNO into the reload register.
5115
5116 RELOADNUM is the number of the reload we want to load this value for;
5117 a reload does not conflict with itself.
5118
5119 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5120 reloads that load an address for the very reload we are considering.
5121
5122 The caller has to make sure that there is no conflict with the return
5123 register. */
5124
5125 static int
free_for_value_p(int regno,enum machine_mode mode,int opnum,enum reload_type type,rtx value,rtx out,int reloadnum,int ignore_address_reloads)5126 free_for_value_p (int regno, enum machine_mode mode, int opnum,
5127 enum reload_type type, rtx value, rtx out, int reloadnum,
5128 int ignore_address_reloads)
5129 {
5130 int nregs = hard_regno_nregs[regno][mode];
5131 while (nregs-- > 0)
5132 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5133 value, out, reloadnum,
5134 ignore_address_reloads))
5135 return 0;
5136 return 1;
5137 }
5138
5139 /* Return nonzero if the rtx X is invariant over the current function. */
5140 /* ??? Actually, the places where we use this expect exactly what is
5141 tested here, and not everything that is function invariant. In
5142 particular, the frame pointer and arg pointer are special cased;
5143 pic_offset_table_rtx is not, and we must not spill these things to
5144 memory. */
5145
5146 int
function_invariant_p(rtx x)5147 function_invariant_p (rtx x)
5148 {
5149 if (CONSTANT_P (x))
5150 return 1;
5151 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
5152 return 1;
5153 if (GET_CODE (x) == PLUS
5154 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
5155 && CONSTANT_P (XEXP (x, 1)))
5156 return 1;
5157 return 0;
5158 }
5159
5160 /* Determine whether the reload reg X overlaps any rtx'es used for
5161 overriding inheritance. Return nonzero if so. */
5162
5163 static int
conflicts_with_override(rtx x)5164 conflicts_with_override (rtx x)
5165 {
5166 int i;
5167 for (i = 0; i < n_reloads; i++)
5168 if (reload_override_in[i]
5169 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5170 return 1;
5171 return 0;
5172 }
5173
5174 /* Give an error message saying we failed to find a reload for INSN,
5175 and clear out reload R. */
5176 static void
failed_reload(rtx insn,int r)5177 failed_reload (rtx insn, int r)
5178 {
5179 if (asm_noperands (PATTERN (insn)) < 0)
5180 /* It's the compiler's fault. */
5181 fatal_insn ("could not find a spill register", insn);
5182
5183 /* It's the user's fault; the operand's mode and constraint
5184 don't match. Disable this reload so we don't crash in final. */
5185 error_for_asm (insn,
5186 "%<asm%> operand constraint incompatible with operand size");
5187 rld[r].in = 0;
5188 rld[r].out = 0;
5189 rld[r].reg_rtx = 0;
5190 rld[r].optional = 1;
5191 rld[r].secondary_p = 1;
5192 }
5193
5194 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5195 for reload R. If it's valid, get an rtx for it. Return nonzero if
5196 successful. */
5197 static int
set_reload_reg(int i,int r)5198 set_reload_reg (int i, int r)
5199 {
5200 int regno;
5201 rtx reg = spill_reg_rtx[i];
5202
5203 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5204 spill_reg_rtx[i] = reg
5205 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5206
5207 regno = true_regnum (reg);
5208
5209 /* Detect when the reload reg can't hold the reload mode.
5210 This used to be one `if', but Sequent compiler can't handle that. */
5211 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5212 {
5213 enum machine_mode test_mode = VOIDmode;
5214 if (rld[r].in)
5215 test_mode = GET_MODE (rld[r].in);
5216 /* If rld[r].in has VOIDmode, it means we will load it
5217 in whatever mode the reload reg has: to wit, rld[r].mode.
5218 We have already tested that for validity. */
5219 /* Aside from that, we need to test that the expressions
5220 to reload from or into have modes which are valid for this
5221 reload register. Otherwise the reload insns would be invalid. */
5222 if (! (rld[r].in != 0 && test_mode != VOIDmode
5223 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5224 if (! (rld[r].out != 0
5225 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5226 {
5227 /* The reg is OK. */
5228 last_spill_reg = i;
5229
5230 /* Mark as in use for this insn the reload regs we use
5231 for this. */
5232 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5233 rld[r].when_needed, rld[r].mode);
5234
5235 rld[r].reg_rtx = reg;
5236 reload_spill_index[r] = spill_regs[i];
5237 return 1;
5238 }
5239 }
5240 return 0;
5241 }
5242
5243 /* Find a spill register to use as a reload register for reload R.
5244 LAST_RELOAD is nonzero if this is the last reload for the insn being
5245 processed.
5246
5247 Set rld[R].reg_rtx to the register allocated.
5248
5249 We return 1 if successful, or 0 if we couldn't find a spill reg and
5250 we didn't change anything. */
5251
5252 static int
allocate_reload_reg(struct insn_chain * chain ATTRIBUTE_UNUSED,int r,int last_reload)5253 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5254 int last_reload)
5255 {
5256 int i, pass, count;
5257
5258 /* If we put this reload ahead, thinking it is a group,
5259 then insist on finding a group. Otherwise we can grab a
5260 reg that some other reload needs.
5261 (That can happen when we have a 68000 DATA_OR_FP_REG
5262 which is a group of data regs or one fp reg.)
5263 We need not be so restrictive if there are no more reloads
5264 for this insn.
5265
5266 ??? Really it would be nicer to have smarter handling
5267 for that kind of reg class, where a problem like this is normal.
5268 Perhaps those classes should be avoided for reloading
5269 by use of more alternatives. */
5270
5271 int force_group = rld[r].nregs > 1 && ! last_reload;
5272
5273 /* If we want a single register and haven't yet found one,
5274 take any reg in the right class and not in use.
5275 If we want a consecutive group, here is where we look for it.
5276
5277 We use two passes so we can first look for reload regs to
5278 reuse, which are already in use for other reloads in this insn,
5279 and only then use additional registers.
5280 I think that maximizing reuse is needed to make sure we don't
5281 run out of reload regs. Suppose we have three reloads, and
5282 reloads A and B can share regs. These need two regs.
5283 Suppose A and B are given different regs.
5284 That leaves none for C. */
5285 for (pass = 0; pass < 2; pass++)
5286 {
5287 /* I is the index in spill_regs.
5288 We advance it round-robin between insns to use all spill regs
5289 equally, so that inherited reloads have a chance
5290 of leapfrogging each other. */
5291
5292 i = last_spill_reg;
5293
5294 for (count = 0; count < n_spills; count++)
5295 {
5296 int class = (int) rld[r].class;
5297 int regnum;
5298
5299 i++;
5300 if (i >= n_spills)
5301 i -= n_spills;
5302 regnum = spill_regs[i];
5303
5304 if ((reload_reg_free_p (regnum, rld[r].opnum,
5305 rld[r].when_needed)
5306 || (rld[r].in
5307 /* We check reload_reg_used to make sure we
5308 don't clobber the return register. */
5309 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5310 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5311 rld[r].when_needed, rld[r].in,
5312 rld[r].out, r, 1)))
5313 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5314 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5315 /* Look first for regs to share, then for unshared. But
5316 don't share regs used for inherited reloads; they are
5317 the ones we want to preserve. */
5318 && (pass
5319 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5320 regnum)
5321 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5322 regnum))))
5323 {
5324 int nr = hard_regno_nregs[regnum][rld[r].mode];
5325 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5326 (on 68000) got us two FP regs. If NR is 1,
5327 we would reject both of them. */
5328 if (force_group)
5329 nr = rld[r].nregs;
5330 /* If we need only one reg, we have already won. */
5331 if (nr == 1)
5332 {
5333 /* But reject a single reg if we demand a group. */
5334 if (force_group)
5335 continue;
5336 break;
5337 }
5338 /* Otherwise check that as many consecutive regs as we need
5339 are available here. */
5340 while (nr > 1)
5341 {
5342 int regno = regnum + nr - 1;
5343 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5344 && spill_reg_order[regno] >= 0
5345 && reload_reg_free_p (regno, rld[r].opnum,
5346 rld[r].when_needed)))
5347 break;
5348 nr--;
5349 }
5350 if (nr == 1)
5351 break;
5352 }
5353 }
5354
5355 /* If we found something on pass 1, omit pass 2. */
5356 if (count < n_spills)
5357 break;
5358 }
5359
5360 /* We should have found a spill register by now. */
5361 if (count >= n_spills)
5362 return 0;
5363
5364 /* I is the index in SPILL_REG_RTX of the reload register we are to
5365 allocate. Get an rtx for it and find its register number. */
5366
5367 return set_reload_reg (i, r);
5368 }
5369
5370 /* Initialize all the tables needed to allocate reload registers.
5371 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5372 is the array we use to restore the reg_rtx field for every reload. */
5373
5374 static void
choose_reload_regs_init(struct insn_chain * chain,rtx * save_reload_reg_rtx)5375 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5376 {
5377 int i;
5378
5379 for (i = 0; i < n_reloads; i++)
5380 rld[i].reg_rtx = save_reload_reg_rtx[i];
5381
5382 memset (reload_inherited, 0, MAX_RELOADS);
5383 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5384 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5385
5386 CLEAR_HARD_REG_SET (reload_reg_used);
5387 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5388 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5389 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5390 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5391 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5392
5393 CLEAR_HARD_REG_SET (reg_used_in_insn);
5394 {
5395 HARD_REG_SET tmp;
5396 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5397 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5398 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5399 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5400 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5401 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5402 }
5403
5404 for (i = 0; i < reload_n_operands; i++)
5405 {
5406 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5407 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5408 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5409 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5410 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5411 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5412 }
5413
5414 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5415
5416 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5417
5418 for (i = 0; i < n_reloads; i++)
5419 /* If we have already decided to use a certain register,
5420 don't use it in another way. */
5421 if (rld[i].reg_rtx)
5422 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5423 rld[i].when_needed, rld[i].mode);
5424 }
5425
5426 /* Assign hard reg targets for the pseudo-registers we must reload
5427 into hard regs for this insn.
5428 Also output the instructions to copy them in and out of the hard regs.
5429
5430 For machines with register classes, we are responsible for
5431 finding a reload reg in the proper class. */
5432
5433 static void
choose_reload_regs(struct insn_chain * chain)5434 choose_reload_regs (struct insn_chain *chain)
5435 {
5436 rtx insn = chain->insn;
5437 int i, j;
5438 unsigned int max_group_size = 1;
5439 enum reg_class group_class = NO_REGS;
5440 int pass, win, inheritance;
5441
5442 rtx save_reload_reg_rtx[MAX_RELOADS];
5443
5444 /* In order to be certain of getting the registers we need,
5445 we must sort the reloads into order of increasing register class.
5446 Then our grabbing of reload registers will parallel the process
5447 that provided the reload registers.
5448
5449 Also note whether any of the reloads wants a consecutive group of regs.
5450 If so, record the maximum size of the group desired and what
5451 register class contains all the groups needed by this insn. */
5452
5453 for (j = 0; j < n_reloads; j++)
5454 {
5455 reload_order[j] = j;
5456 if (rld[j].reg_rtx != NULL_RTX)
5457 {
5458 gcc_assert (REG_P (rld[j].reg_rtx)
5459 && HARD_REGISTER_P (rld[j].reg_rtx));
5460 reload_spill_index[j] = REGNO (rld[j].reg_rtx);
5461 }
5462 else
5463 reload_spill_index[j] = -1;
5464
5465 if (rld[j].nregs > 1)
5466 {
5467 max_group_size = MAX (rld[j].nregs, max_group_size);
5468 group_class
5469 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5470 }
5471
5472 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5473 }
5474
5475 if (n_reloads > 1)
5476 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5477
5478 /* If -O, try first with inheritance, then turning it off.
5479 If not -O, don't do inheritance.
5480 Using inheritance when not optimizing leads to paradoxes
5481 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5482 because one side of the comparison might be inherited. */
5483 win = 0;
5484 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5485 {
5486 choose_reload_regs_init (chain, save_reload_reg_rtx);
5487
5488 /* Process the reloads in order of preference just found.
5489 Beyond this point, subregs can be found in reload_reg_rtx.
5490
5491 This used to look for an existing reloaded home for all of the
5492 reloads, and only then perform any new reloads. But that could lose
5493 if the reloads were done out of reg-class order because a later
5494 reload with a looser constraint might have an old home in a register
5495 needed by an earlier reload with a tighter constraint.
5496
5497 To solve this, we make two passes over the reloads, in the order
5498 described above. In the first pass we try to inherit a reload
5499 from a previous insn. If there is a later reload that needs a
5500 class that is a proper subset of the class being processed, we must
5501 also allocate a spill register during the first pass.
5502
5503 Then make a second pass over the reloads to allocate any reloads
5504 that haven't been given registers yet. */
5505
5506 for (j = 0; j < n_reloads; j++)
5507 {
5508 int r = reload_order[j];
5509 rtx search_equiv = NULL_RTX;
5510
5511 /* Ignore reloads that got marked inoperative. */
5512 if (rld[r].out == 0 && rld[r].in == 0
5513 && ! rld[r].secondary_p)
5514 continue;
5515
5516 /* If find_reloads chose to use reload_in or reload_out as a reload
5517 register, we don't need to chose one. Otherwise, try even if it
5518 found one since we might save an insn if we find the value lying
5519 around.
5520 Try also when reload_in is a pseudo without a hard reg. */
5521 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5522 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5523 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5524 && !MEM_P (rld[r].in)
5525 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5526 continue;
5527
5528 #if 0 /* No longer needed for correct operation.
5529 It might give better code, or might not; worth an experiment? */
5530 /* If this is an optional reload, we can't inherit from earlier insns
5531 until we are sure that any non-optional reloads have been allocated.
5532 The following code takes advantage of the fact that optional reloads
5533 are at the end of reload_order. */
5534 if (rld[r].optional != 0)
5535 for (i = 0; i < j; i++)
5536 if ((rld[reload_order[i]].out != 0
5537 || rld[reload_order[i]].in != 0
5538 || rld[reload_order[i]].secondary_p)
5539 && ! rld[reload_order[i]].optional
5540 && rld[reload_order[i]].reg_rtx == 0)
5541 allocate_reload_reg (chain, reload_order[i], 0);
5542 #endif
5543
5544 /* First see if this pseudo is already available as reloaded
5545 for a previous insn. We cannot try to inherit for reloads
5546 that are smaller than the maximum number of registers needed
5547 for groups unless the register we would allocate cannot be used
5548 for the groups.
5549
5550 We could check here to see if this is a secondary reload for
5551 an object that is already in a register of the desired class.
5552 This would avoid the need for the secondary reload register.
5553 But this is complex because we can't easily determine what
5554 objects might want to be loaded via this reload. So let a
5555 register be allocated here. In `emit_reload_insns' we suppress
5556 one of the loads in the case described above. */
5557
5558 if (inheritance)
5559 {
5560 int byte = 0;
5561 int regno = -1;
5562 enum machine_mode mode = VOIDmode;
5563
5564 if (rld[r].in == 0)
5565 ;
5566 else if (REG_P (rld[r].in))
5567 {
5568 regno = REGNO (rld[r].in);
5569 mode = GET_MODE (rld[r].in);
5570 }
5571 else if (REG_P (rld[r].in_reg))
5572 {
5573 regno = REGNO (rld[r].in_reg);
5574 mode = GET_MODE (rld[r].in_reg);
5575 }
5576 else if (GET_CODE (rld[r].in_reg) == SUBREG
5577 && REG_P (SUBREG_REG (rld[r].in_reg)))
5578 {
5579 byte = SUBREG_BYTE (rld[r].in_reg);
5580 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5581 if (regno < FIRST_PSEUDO_REGISTER)
5582 regno = subreg_regno (rld[r].in_reg);
5583 mode = GET_MODE (rld[r].in_reg);
5584 }
5585 #ifdef AUTO_INC_DEC
5586 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
5587 && REG_P (XEXP (rld[r].in_reg, 0)))
5588 {
5589 regno = REGNO (XEXP (rld[r].in_reg, 0));
5590 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5591 rld[r].out = rld[r].in;
5592 }
5593 #endif
5594 #if 0
5595 /* This won't work, since REGNO can be a pseudo reg number.
5596 Also, it takes much more hair to keep track of all the things
5597 that can invalidate an inherited reload of part of a pseudoreg. */
5598 else if (GET_CODE (rld[r].in) == SUBREG
5599 && REG_P (SUBREG_REG (rld[r].in)))
5600 regno = subreg_regno (rld[r].in);
5601 #endif
5602
5603 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5604 {
5605 enum reg_class class = rld[r].class, last_class;
5606 rtx last_reg = reg_last_reload_reg[regno];
5607 enum machine_mode need_mode;
5608
5609 i = REGNO (last_reg);
5610 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5611 last_class = REGNO_REG_CLASS (i);
5612
5613 if (byte == 0)
5614 need_mode = mode;
5615 else
5616 need_mode
5617 = smallest_mode_for_size (GET_MODE_BITSIZE (mode)
5618 + byte * BITS_PER_UNIT,
5619 GET_MODE_CLASS (mode));
5620
5621 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5622 >= GET_MODE_SIZE (need_mode))
5623 #ifdef CANNOT_CHANGE_MODE_CLASS
5624 /* Verify that the register in "i" can be obtained
5625 from LAST_REG. */
5626 && !REG_CANNOT_CHANGE_MODE_P (REGNO (last_reg),
5627 GET_MODE (last_reg),
5628 mode)
5629 #endif
5630 && reg_reloaded_contents[i] == regno
5631 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5632 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5633 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5634 /* Even if we can't use this register as a reload
5635 register, we might use it for reload_override_in,
5636 if copying it to the desired class is cheap
5637 enough. */
5638 || ((REGISTER_MOVE_COST (mode, last_class, class)
5639 < MEMORY_MOVE_COST (mode, class, 1))
5640 && (secondary_reload_class (1, class, mode,
5641 last_reg)
5642 == NO_REGS)
5643 #ifdef SECONDARY_MEMORY_NEEDED
5644 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5645 mode)
5646 #endif
5647 ))
5648
5649 && (rld[r].nregs == max_group_size
5650 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5651 i))
5652 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5653 rld[r].when_needed, rld[r].in,
5654 const0_rtx, r, 1))
5655 {
5656 /* If a group is needed, verify that all the subsequent
5657 registers still have their values intact. */
5658 int nr = hard_regno_nregs[i][rld[r].mode];
5659 int k;
5660
5661 for (k = 1; k < nr; k++)
5662 if (reg_reloaded_contents[i + k] != regno
5663 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5664 break;
5665
5666 if (k == nr)
5667 {
5668 int i1;
5669 int bad_for_class;
5670
5671 last_reg = (GET_MODE (last_reg) == mode
5672 ? last_reg : gen_rtx_REG (mode, i));
5673
5674 bad_for_class = 0;
5675 for (k = 0; k < nr; k++)
5676 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5677 i+k);
5678
5679 /* We found a register that contains the
5680 value we need. If this register is the
5681 same as an `earlyclobber' operand of the
5682 current insn, just mark it as a place to
5683 reload from since we can't use it as the
5684 reload register itself. */
5685
5686 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5687 if (reg_overlap_mentioned_for_reload_p
5688 (reg_last_reload_reg[regno],
5689 reload_earlyclobbers[i1]))
5690 break;
5691
5692 if (i1 != n_earlyclobbers
5693 || ! (free_for_value_p (i, rld[r].mode,
5694 rld[r].opnum,
5695 rld[r].when_needed, rld[r].in,
5696 rld[r].out, r, 1))
5697 /* Don't use it if we'd clobber a pseudo reg. */
5698 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5699 && rld[r].out
5700 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5701 /* Don't clobber the frame pointer. */
5702 || (i == HARD_FRAME_POINTER_REGNUM
5703 && frame_pointer_needed
5704 && rld[r].out)
5705 /* Don't really use the inherited spill reg
5706 if we need it wider than we've got it. */
5707 || (GET_MODE_SIZE (rld[r].mode)
5708 > GET_MODE_SIZE (mode))
5709 || bad_for_class
5710
5711 /* If find_reloads chose reload_out as reload
5712 register, stay with it - that leaves the
5713 inherited register for subsequent reloads. */
5714 || (rld[r].out && rld[r].reg_rtx
5715 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5716 {
5717 if (! rld[r].optional)
5718 {
5719 reload_override_in[r] = last_reg;
5720 reload_inheritance_insn[r]
5721 = reg_reloaded_insn[i];
5722 }
5723 }
5724 else
5725 {
5726 int k;
5727 /* We can use this as a reload reg. */
5728 /* Mark the register as in use for this part of
5729 the insn. */
5730 mark_reload_reg_in_use (i,
5731 rld[r].opnum,
5732 rld[r].when_needed,
5733 rld[r].mode);
5734 rld[r].reg_rtx = last_reg;
5735 reload_inherited[r] = 1;
5736 reload_inheritance_insn[r]
5737 = reg_reloaded_insn[i];
5738 reload_spill_index[r] = i;
5739 for (k = 0; k < nr; k++)
5740 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5741 i + k);
5742 }
5743 }
5744 }
5745 }
5746 }
5747
5748 /* Here's another way to see if the value is already lying around. */
5749 if (inheritance
5750 && rld[r].in != 0
5751 && ! reload_inherited[r]
5752 && rld[r].out == 0
5753 && (CONSTANT_P (rld[r].in)
5754 || GET_CODE (rld[r].in) == PLUS
5755 || REG_P (rld[r].in)
5756 || MEM_P (rld[r].in))
5757 && (rld[r].nregs == max_group_size
5758 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5759 search_equiv = rld[r].in;
5760 /* If this is an output reload from a simple move insn, look
5761 if an equivalence for the input is available. */
5762 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5763 {
5764 rtx set = single_set (insn);
5765
5766 if (set
5767 && rtx_equal_p (rld[r].out, SET_DEST (set))
5768 && CONSTANT_P (SET_SRC (set)))
5769 search_equiv = SET_SRC (set);
5770 }
5771
5772 if (search_equiv)
5773 {
5774 rtx equiv
5775 = find_equiv_reg (search_equiv, insn, rld[r].class,
5776 -1, NULL, 0, rld[r].mode);
5777 int regno = 0;
5778
5779 if (equiv != 0)
5780 {
5781 if (REG_P (equiv))
5782 regno = REGNO (equiv);
5783 else
5784 {
5785 /* This must be a SUBREG of a hard register.
5786 Make a new REG since this might be used in an
5787 address and not all machines support SUBREGs
5788 there. */
5789 gcc_assert (GET_CODE (equiv) == SUBREG);
5790 regno = subreg_regno (equiv);
5791 equiv = gen_rtx_REG (rld[r].mode, regno);
5792 /* If we choose EQUIV as the reload register, but the
5793 loop below decides to cancel the inheritance, we'll
5794 end up reloading EQUIV in rld[r].mode, not the mode
5795 it had originally. That isn't safe when EQUIV isn't
5796 available as a spill register since its value might
5797 still be live at this point. */
5798 for (i = regno; i < regno + (int) rld[r].nregs; i++)
5799 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
5800 equiv = 0;
5801 }
5802 }
5803
5804 /* If we found a spill reg, reject it unless it is free
5805 and of the desired class. */
5806 if (equiv != 0)
5807 {
5808 int regs_used = 0;
5809 int bad_for_class = 0;
5810 int max_regno = regno + rld[r].nregs;
5811
5812 for (i = regno; i < max_regno; i++)
5813 {
5814 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
5815 i);
5816 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5817 i);
5818 }
5819
5820 if ((regs_used
5821 && ! free_for_value_p (regno, rld[r].mode,
5822 rld[r].opnum, rld[r].when_needed,
5823 rld[r].in, rld[r].out, r, 1))
5824 || bad_for_class)
5825 equiv = 0;
5826 }
5827
5828 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5829 equiv = 0;
5830
5831 /* We found a register that contains the value we need.
5832 If this register is the same as an `earlyclobber' operand
5833 of the current insn, just mark it as a place to reload from
5834 since we can't use it as the reload register itself. */
5835
5836 if (equiv != 0)
5837 for (i = 0; i < n_earlyclobbers; i++)
5838 if (reg_overlap_mentioned_for_reload_p (equiv,
5839 reload_earlyclobbers[i]))
5840 {
5841 if (! rld[r].optional)
5842 reload_override_in[r] = equiv;
5843 equiv = 0;
5844 break;
5845 }
5846
5847 /* If the equiv register we have found is explicitly clobbered
5848 in the current insn, it depends on the reload type if we
5849 can use it, use it for reload_override_in, or not at all.
5850 In particular, we then can't use EQUIV for a
5851 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5852
5853 if (equiv != 0)
5854 {
5855 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
5856 switch (rld[r].when_needed)
5857 {
5858 case RELOAD_FOR_OTHER_ADDRESS:
5859 case RELOAD_FOR_INPADDR_ADDRESS:
5860 case RELOAD_FOR_INPUT_ADDRESS:
5861 case RELOAD_FOR_OPADDR_ADDR:
5862 break;
5863 case RELOAD_OTHER:
5864 case RELOAD_FOR_INPUT:
5865 case RELOAD_FOR_OPERAND_ADDRESS:
5866 if (! rld[r].optional)
5867 reload_override_in[r] = equiv;
5868 /* Fall through. */
5869 default:
5870 equiv = 0;
5871 break;
5872 }
5873 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5874 switch (rld[r].when_needed)
5875 {
5876 case RELOAD_FOR_OTHER_ADDRESS:
5877 case RELOAD_FOR_INPADDR_ADDRESS:
5878 case RELOAD_FOR_INPUT_ADDRESS:
5879 case RELOAD_FOR_OPADDR_ADDR:
5880 case RELOAD_FOR_OPERAND_ADDRESS:
5881 case RELOAD_FOR_INPUT:
5882 break;
5883 case RELOAD_OTHER:
5884 if (! rld[r].optional)
5885 reload_override_in[r] = equiv;
5886 /* Fall through. */
5887 default:
5888 equiv = 0;
5889 break;
5890 }
5891 }
5892
5893 /* If we found an equivalent reg, say no code need be generated
5894 to load it, and use it as our reload reg. */
5895 if (equiv != 0
5896 && (regno != HARD_FRAME_POINTER_REGNUM
5897 || !frame_pointer_needed))
5898 {
5899 int nr = hard_regno_nregs[regno][rld[r].mode];
5900 int k;
5901 rld[r].reg_rtx = equiv;
5902 reload_inherited[r] = 1;
5903
5904 /* If reg_reloaded_valid is not set for this register,
5905 there might be a stale spill_reg_store lying around.
5906 We must clear it, since otherwise emit_reload_insns
5907 might delete the store. */
5908 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5909 spill_reg_store[regno] = NULL_RTX;
5910 /* If any of the hard registers in EQUIV are spill
5911 registers, mark them as in use for this insn. */
5912 for (k = 0; k < nr; k++)
5913 {
5914 i = spill_reg_order[regno + k];
5915 if (i >= 0)
5916 {
5917 mark_reload_reg_in_use (regno, rld[r].opnum,
5918 rld[r].when_needed,
5919 rld[r].mode);
5920 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5921 regno + k);
5922 }
5923 }
5924 }
5925 }
5926
5927 /* If we found a register to use already, or if this is an optional
5928 reload, we are done. */
5929 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5930 continue;
5931
5932 #if 0
5933 /* No longer needed for correct operation. Might or might
5934 not give better code on the average. Want to experiment? */
5935
5936 /* See if there is a later reload that has a class different from our
5937 class that intersects our class or that requires less register
5938 than our reload. If so, we must allocate a register to this
5939 reload now, since that reload might inherit a previous reload
5940 and take the only available register in our class. Don't do this
5941 for optional reloads since they will force all previous reloads
5942 to be allocated. Also don't do this for reloads that have been
5943 turned off. */
5944
5945 for (i = j + 1; i < n_reloads; i++)
5946 {
5947 int s = reload_order[i];
5948
5949 if ((rld[s].in == 0 && rld[s].out == 0
5950 && ! rld[s].secondary_p)
5951 || rld[s].optional)
5952 continue;
5953
5954 if ((rld[s].class != rld[r].class
5955 && reg_classes_intersect_p (rld[r].class,
5956 rld[s].class))
5957 || rld[s].nregs < rld[r].nregs)
5958 break;
5959 }
5960
5961 if (i == n_reloads)
5962 continue;
5963
5964 allocate_reload_reg (chain, r, j == n_reloads - 1);
5965 #endif
5966 }
5967
5968 /* Now allocate reload registers for anything non-optional that
5969 didn't get one yet. */
5970 for (j = 0; j < n_reloads; j++)
5971 {
5972 int r = reload_order[j];
5973
5974 /* Ignore reloads that got marked inoperative. */
5975 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5976 continue;
5977
5978 /* Skip reloads that already have a register allocated or are
5979 optional. */
5980 if (rld[r].reg_rtx != 0 || rld[r].optional)
5981 continue;
5982
5983 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5984 break;
5985 }
5986
5987 /* If that loop got all the way, we have won. */
5988 if (j == n_reloads)
5989 {
5990 win = 1;
5991 break;
5992 }
5993
5994 /* Loop around and try without any inheritance. */
5995 }
5996
5997 if (! win)
5998 {
5999 /* First undo everything done by the failed attempt
6000 to allocate with inheritance. */
6001 choose_reload_regs_init (chain, save_reload_reg_rtx);
6002
6003 /* Some sanity tests to verify that the reloads found in the first
6004 pass are identical to the ones we have now. */
6005 gcc_assert (chain->n_reloads == n_reloads);
6006
6007 for (i = 0; i < n_reloads; i++)
6008 {
6009 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6010 continue;
6011 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6012 for (j = 0; j < n_spills; j++)
6013 if (spill_regs[j] == chain->rld[i].regno)
6014 if (! set_reload_reg (j, i))
6015 failed_reload (chain->insn, i);
6016 }
6017 }
6018
6019 /* If we thought we could inherit a reload, because it seemed that
6020 nothing else wanted the same reload register earlier in the insn,
6021 verify that assumption, now that all reloads have been assigned.
6022 Likewise for reloads where reload_override_in has been set. */
6023
6024 /* If doing expensive optimizations, do one preliminary pass that doesn't
6025 cancel any inheritance, but removes reloads that have been needed only
6026 for reloads that we know can be inherited. */
6027 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6028 {
6029 for (j = 0; j < n_reloads; j++)
6030 {
6031 int r = reload_order[j];
6032 rtx check_reg;
6033 if (reload_inherited[r] && rld[r].reg_rtx)
6034 check_reg = rld[r].reg_rtx;
6035 else if (reload_override_in[r]
6036 && (REG_P (reload_override_in[r])
6037 || GET_CODE (reload_override_in[r]) == SUBREG))
6038 check_reg = reload_override_in[r];
6039 else
6040 continue;
6041 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6042 rld[r].opnum, rld[r].when_needed, rld[r].in,
6043 (reload_inherited[r]
6044 ? rld[r].out : const0_rtx),
6045 r, 1))
6046 {
6047 if (pass)
6048 continue;
6049 reload_inherited[r] = 0;
6050 reload_override_in[r] = 0;
6051 }
6052 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6053 reload_override_in, then we do not need its related
6054 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6055 likewise for other reload types.
6056 We handle this by removing a reload when its only replacement
6057 is mentioned in reload_in of the reload we are going to inherit.
6058 A special case are auto_inc expressions; even if the input is
6059 inherited, we still need the address for the output. We can
6060 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6061 If we succeeded removing some reload and we are doing a preliminary
6062 pass just to remove such reloads, make another pass, since the
6063 removal of one reload might allow us to inherit another one. */
6064 else if (rld[r].in
6065 && rld[r].out != rld[r].in
6066 && remove_address_replacements (rld[r].in) && pass)
6067 pass = 2;
6068 }
6069 }
6070
6071 /* Now that reload_override_in is known valid,
6072 actually override reload_in. */
6073 for (j = 0; j < n_reloads; j++)
6074 if (reload_override_in[j])
6075 rld[j].in = reload_override_in[j];
6076
6077 /* If this reload won't be done because it has been canceled or is
6078 optional and not inherited, clear reload_reg_rtx so other
6079 routines (such as subst_reloads) don't get confused. */
6080 for (j = 0; j < n_reloads; j++)
6081 if (rld[j].reg_rtx != 0
6082 && ((rld[j].optional && ! reload_inherited[j])
6083 || (rld[j].in == 0 && rld[j].out == 0
6084 && ! rld[j].secondary_p)))
6085 {
6086 int regno = true_regnum (rld[j].reg_rtx);
6087
6088 if (spill_reg_order[regno] >= 0)
6089 clear_reload_reg_in_use (regno, rld[j].opnum,
6090 rld[j].when_needed, rld[j].mode);
6091 rld[j].reg_rtx = 0;
6092 reload_spill_index[j] = -1;
6093 }
6094
6095 /* Record which pseudos and which spill regs have output reloads. */
6096 for (j = 0; j < n_reloads; j++)
6097 {
6098 int r = reload_order[j];
6099
6100 i = reload_spill_index[r];
6101
6102 /* I is nonneg if this reload uses a register.
6103 If rld[r].reg_rtx is 0, this is an optional reload
6104 that we opted to ignore. */
6105 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
6106 && rld[r].reg_rtx != 0)
6107 {
6108 int nregno = REGNO (rld[r].out_reg);
6109 int nr = 1;
6110
6111 if (nregno < FIRST_PSEUDO_REGISTER)
6112 nr = hard_regno_nregs[nregno][rld[r].mode];
6113
6114 while (--nr >= 0)
6115 SET_REGNO_REG_SET (®_has_output_reload,
6116 nregno + nr);
6117
6118 if (i >= 0)
6119 {
6120 nr = hard_regno_nregs[i][rld[r].mode];
6121 while (--nr >= 0)
6122 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6123 }
6124
6125 gcc_assert (rld[r].when_needed == RELOAD_OTHER
6126 || rld[r].when_needed == RELOAD_FOR_OUTPUT
6127 || rld[r].when_needed == RELOAD_FOR_INSN);
6128 }
6129 }
6130 }
6131
6132 /* Deallocate the reload register for reload R. This is called from
6133 remove_address_replacements. */
6134
6135 void
deallocate_reload_reg(int r)6136 deallocate_reload_reg (int r)
6137 {
6138 int regno;
6139
6140 if (! rld[r].reg_rtx)
6141 return;
6142 regno = true_regnum (rld[r].reg_rtx);
6143 rld[r].reg_rtx = 0;
6144 if (spill_reg_order[regno] >= 0)
6145 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6146 rld[r].mode);
6147 reload_spill_index[r] = -1;
6148 }
6149
6150 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6151 reloads of the same item for fear that we might not have enough reload
6152 registers. However, normally they will get the same reload register
6153 and hence actually need not be loaded twice.
6154
6155 Here we check for the most common case of this phenomenon: when we have
6156 a number of reloads for the same object, each of which were allocated
6157 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6158 reload, and is not modified in the insn itself. If we find such,
6159 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6160 This will not increase the number of spill registers needed and will
6161 prevent redundant code. */
6162
6163 static void
merge_assigned_reloads(rtx insn)6164 merge_assigned_reloads (rtx insn)
6165 {
6166 int i, j;
6167
6168 /* Scan all the reloads looking for ones that only load values and
6169 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6170 assigned and not modified by INSN. */
6171
6172 for (i = 0; i < n_reloads; i++)
6173 {
6174 int conflicting_input = 0;
6175 int max_input_address_opnum = -1;
6176 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6177
6178 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6179 || rld[i].out != 0 || rld[i].reg_rtx == 0
6180 || reg_set_p (rld[i].reg_rtx, insn))
6181 continue;
6182
6183 /* Look at all other reloads. Ensure that the only use of this
6184 reload_reg_rtx is in a reload that just loads the same value
6185 as we do. Note that any secondary reloads must be of the identical
6186 class since the values, modes, and result registers are the
6187 same, so we need not do anything with any secondary reloads. */
6188
6189 for (j = 0; j < n_reloads; j++)
6190 {
6191 if (i == j || rld[j].reg_rtx == 0
6192 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6193 rld[i].reg_rtx))
6194 continue;
6195
6196 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6197 && rld[j].opnum > max_input_address_opnum)
6198 max_input_address_opnum = rld[j].opnum;
6199
6200 /* If the reload regs aren't exactly the same (e.g, different modes)
6201 or if the values are different, we can't merge this reload.
6202 But if it is an input reload, we might still merge
6203 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6204
6205 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6206 || rld[j].out != 0 || rld[j].in == 0
6207 || ! rtx_equal_p (rld[i].in, rld[j].in))
6208 {
6209 if (rld[j].when_needed != RELOAD_FOR_INPUT
6210 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6211 || rld[i].opnum > rld[j].opnum)
6212 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6213 break;
6214 conflicting_input = 1;
6215 if (min_conflicting_input_opnum > rld[j].opnum)
6216 min_conflicting_input_opnum = rld[j].opnum;
6217 }
6218 }
6219
6220 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6221 we, in fact, found any matching reloads. */
6222
6223 if (j == n_reloads
6224 && max_input_address_opnum <= min_conflicting_input_opnum)
6225 {
6226 gcc_assert (rld[i].when_needed != RELOAD_FOR_OUTPUT);
6227
6228 for (j = 0; j < n_reloads; j++)
6229 if (i != j && rld[j].reg_rtx != 0
6230 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6231 && (! conflicting_input
6232 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6233 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6234 {
6235 rld[i].when_needed = RELOAD_OTHER;
6236 rld[j].in = 0;
6237 reload_spill_index[j] = -1;
6238 transfer_replacements (i, j);
6239 }
6240
6241 /* If this is now RELOAD_OTHER, look for any reloads that
6242 load parts of this operand and set them to
6243 RELOAD_FOR_OTHER_ADDRESS if they were for inputs,
6244 RELOAD_OTHER for outputs. Note that this test is
6245 equivalent to looking for reloads for this operand
6246 number.
6247
6248 We must take special care with RELOAD_FOR_OUTPUT_ADDRESS;
6249 it may share registers with a RELOAD_FOR_INPUT, so we can
6250 not change it to RELOAD_FOR_OTHER_ADDRESS. We should
6251 never need to, since we do not modify RELOAD_FOR_OUTPUT.
6252
6253 It is possible that the RELOAD_FOR_OPERAND_ADDRESS
6254 instruction is assigned the same register as the earlier
6255 RELOAD_FOR_OTHER_ADDRESS instruction. Merging these two
6256 instructions will cause the RELOAD_FOR_OTHER_ADDRESS
6257 instruction to be deleted later on. */
6258
6259 if (rld[i].when_needed == RELOAD_OTHER)
6260 for (j = 0; j < n_reloads; j++)
6261 if (rld[j].in != 0
6262 && rld[j].when_needed != RELOAD_OTHER
6263 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6264 && rld[j].when_needed != RELOAD_FOR_OUTPUT_ADDRESS
6265 && rld[j].when_needed != RELOAD_FOR_OPERAND_ADDRESS
6266 && (! conflicting_input
6267 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6268 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6269 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6270 rld[i].in))
6271 {
6272 int k;
6273
6274 rld[j].when_needed
6275 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6276 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6277 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6278
6279 /* Check to see if we accidentally converted two
6280 reloads that use the same reload register with
6281 different inputs to the same type. If so, the
6282 resulting code won't work. */
6283 if (rld[j].reg_rtx)
6284 for (k = 0; k < j; k++)
6285 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6286 || rld[k].when_needed != rld[j].when_needed
6287 || !rtx_equal_p (rld[k].reg_rtx,
6288 rld[j].reg_rtx)
6289 || rtx_equal_p (rld[k].in,
6290 rld[j].in));
6291 }
6292 }
6293 }
6294 }
6295
6296 /* These arrays are filled by emit_reload_insns and its subroutines. */
6297 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6298 static rtx other_input_address_reload_insns = 0;
6299 static rtx other_input_reload_insns = 0;
6300 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6301 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6302 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6303 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6304 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6305 static rtx operand_reload_insns = 0;
6306 static rtx other_operand_reload_insns = 0;
6307 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6308
6309 /* Values to be put in spill_reg_store are put here first. */
6310 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6311 static HARD_REG_SET reg_reloaded_died;
6312
6313 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
6314 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
6315 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
6316 adjusted register, and return true. Otherwise, return false. */
6317 static bool
reload_adjust_reg_for_temp(rtx * reload_reg,rtx alt_reload_reg,enum reg_class new_class,enum machine_mode new_mode)6318 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
6319 enum reg_class new_class,
6320 enum machine_mode new_mode)
6321
6322 {
6323 rtx reg;
6324
6325 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
6326 {
6327 unsigned regno = REGNO (reg);
6328
6329 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
6330 continue;
6331 if (GET_MODE (reg) != new_mode)
6332 {
6333 if (!HARD_REGNO_MODE_OK (regno, new_mode))
6334 continue;
6335 if (hard_regno_nregs[regno][new_mode]
6336 > hard_regno_nregs[regno][GET_MODE (reg)])
6337 continue;
6338 reg = reload_adjust_reg_for_mode (reg, new_mode);
6339 }
6340 *reload_reg = reg;
6341 return true;
6342 }
6343 return false;
6344 }
6345
6346 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
6347 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
6348 nonzero, if that is suitable. On success, change *RELOAD_REG to the
6349 adjusted register, and return true. Otherwise, return false. */
6350 static bool
reload_adjust_reg_for_icode(rtx * reload_reg,rtx alt_reload_reg,enum insn_code icode)6351 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
6352 enum insn_code icode)
6353
6354 {
6355 enum reg_class new_class = scratch_reload_class (icode);
6356 enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
6357
6358 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
6359 new_class, new_mode);
6360 }
6361
6362 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6363 has the number J. OLD contains the value to be used as input. */
6364
6365 static void
emit_input_reload_insns(struct insn_chain * chain,struct reload * rl,rtx old,int j)6366 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6367 rtx old, int j)
6368 {
6369 rtx insn = chain->insn;
6370 rtx reloadreg = rl->reg_rtx;
6371 rtx oldequiv_reg = 0;
6372 rtx oldequiv = 0;
6373 int special = 0;
6374 enum machine_mode mode;
6375 rtx *where;
6376
6377 /* Determine the mode to reload in.
6378 This is very tricky because we have three to choose from.
6379 There is the mode the insn operand wants (rl->inmode).
6380 There is the mode of the reload register RELOADREG.
6381 There is the intrinsic mode of the operand, which we could find
6382 by stripping some SUBREGs.
6383 It turns out that RELOADREG's mode is irrelevant:
6384 we can change that arbitrarily.
6385
6386 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6387 then the reload reg may not support QImode moves, so use SImode.
6388 If foo is in memory due to spilling a pseudo reg, this is safe,
6389 because the QImode value is in the least significant part of a
6390 slot big enough for a SImode. If foo is some other sort of
6391 memory reference, then it is impossible to reload this case,
6392 so previous passes had better make sure this never happens.
6393
6394 Then consider a one-word union which has SImode and one of its
6395 members is a float, being fetched as (SUBREG:SF union:SI).
6396 We must fetch that as SFmode because we could be loading into
6397 a float-only register. In this case OLD's mode is correct.
6398
6399 Consider an immediate integer: it has VOIDmode. Here we need
6400 to get a mode from something else.
6401
6402 In some cases, there is a fourth mode, the operand's
6403 containing mode. If the insn specifies a containing mode for
6404 this operand, it overrides all others.
6405
6406 I am not sure whether the algorithm here is always right,
6407 but it does the right things in those cases. */
6408
6409 mode = GET_MODE (old);
6410 if (mode == VOIDmode)
6411 mode = rl->inmode;
6412
6413 /* delete_output_reload is only invoked properly if old contains
6414 the original pseudo register. Since this is replaced with a
6415 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6416 find the pseudo in RELOAD_IN_REG. */
6417 if (reload_override_in[j]
6418 && REG_P (rl->in_reg))
6419 {
6420 oldequiv = old;
6421 old = rl->in_reg;
6422 }
6423 if (oldequiv == 0)
6424 oldequiv = old;
6425 else if (REG_P (oldequiv))
6426 oldequiv_reg = oldequiv;
6427 else if (GET_CODE (oldequiv) == SUBREG)
6428 oldequiv_reg = SUBREG_REG (oldequiv);
6429
6430 /* If we are reloading from a register that was recently stored in
6431 with an output-reload, see if we can prove there was
6432 actually no need to store the old value in it. */
6433
6434 if (optimize && REG_P (oldequiv)
6435 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6436 && spill_reg_store[REGNO (oldequiv)]
6437 && REG_P (old)
6438 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6439 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6440 rl->out_reg)))
6441 delete_output_reload (insn, j, REGNO (oldequiv));
6442
6443 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6444 then load RELOADREG from OLDEQUIV. Note that we cannot use
6445 gen_lowpart_common since it can do the wrong thing when
6446 RELOADREG has a multi-word mode. Note that RELOADREG
6447 must always be a REG here. */
6448
6449 if (GET_MODE (reloadreg) != mode)
6450 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6451 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6452 oldequiv = SUBREG_REG (oldequiv);
6453 if (GET_MODE (oldequiv) != VOIDmode
6454 && mode != GET_MODE (oldequiv))
6455 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6456
6457 /* Switch to the right place to emit the reload insns. */
6458 switch (rl->when_needed)
6459 {
6460 case RELOAD_OTHER:
6461 where = &other_input_reload_insns;
6462 break;
6463 case RELOAD_FOR_INPUT:
6464 where = &input_reload_insns[rl->opnum];
6465 break;
6466 case RELOAD_FOR_INPUT_ADDRESS:
6467 where = &input_address_reload_insns[rl->opnum];
6468 break;
6469 case RELOAD_FOR_INPADDR_ADDRESS:
6470 where = &inpaddr_address_reload_insns[rl->opnum];
6471 break;
6472 case RELOAD_FOR_OUTPUT_ADDRESS:
6473 where = &output_address_reload_insns[rl->opnum];
6474 break;
6475 case RELOAD_FOR_OUTADDR_ADDRESS:
6476 where = &outaddr_address_reload_insns[rl->opnum];
6477 break;
6478 case RELOAD_FOR_OPERAND_ADDRESS:
6479 where = &operand_reload_insns;
6480 break;
6481 case RELOAD_FOR_OPADDR_ADDR:
6482 where = &other_operand_reload_insns;
6483 break;
6484 case RELOAD_FOR_OTHER_ADDRESS:
6485 where = &other_input_address_reload_insns;
6486 break;
6487 default:
6488 gcc_unreachable ();
6489 }
6490
6491 push_to_sequence (*where);
6492
6493 /* Auto-increment addresses must be reloaded in a special way. */
6494 if (rl->out && ! rl->out_reg)
6495 {
6496 /* We are not going to bother supporting the case where a
6497 incremented register can't be copied directly from
6498 OLDEQUIV since this seems highly unlikely. */
6499 gcc_assert (rl->secondary_in_reload < 0);
6500
6501 if (reload_inherited[j])
6502 oldequiv = reloadreg;
6503
6504 old = XEXP (rl->in_reg, 0);
6505
6506 if (optimize && REG_P (oldequiv)
6507 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6508 && spill_reg_store[REGNO (oldequiv)]
6509 && REG_P (old)
6510 && (dead_or_set_p (insn,
6511 spill_reg_stored_to[REGNO (oldequiv)])
6512 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6513 old)))
6514 delete_output_reload (insn, j, REGNO (oldequiv));
6515
6516 /* Prevent normal processing of this reload. */
6517 special = 1;
6518 /* Output a special code sequence for this case. */
6519 new_spill_reg_store[REGNO (reloadreg)]
6520 = inc_for_reload (reloadreg, oldequiv, rl->out,
6521 rl->inc);
6522 }
6523
6524 /* If we are reloading a pseudo-register that was set by the previous
6525 insn, see if we can get rid of that pseudo-register entirely
6526 by redirecting the previous insn into our reload register. */
6527
6528 else if (optimize && REG_P (old)
6529 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6530 && dead_or_set_p (insn, old)
6531 /* This is unsafe if some other reload
6532 uses the same reg first. */
6533 && ! conflicts_with_override (reloadreg)
6534 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6535 rl->when_needed, old, rl->out, j, 0))
6536 {
6537 rtx temp = PREV_INSN (insn);
6538 while (temp && NOTE_P (temp))
6539 temp = PREV_INSN (temp);
6540 if (temp
6541 && NONJUMP_INSN_P (temp)
6542 && GET_CODE (PATTERN (temp)) == SET
6543 && SET_DEST (PATTERN (temp)) == old
6544 /* Make sure we can access insn_operand_constraint. */
6545 && asm_noperands (PATTERN (temp)) < 0
6546 /* This is unsafe if operand occurs more than once in current
6547 insn. Perhaps some occurrences aren't reloaded. */
6548 && count_occurrences (PATTERN (insn), old, 0) == 1)
6549 {
6550 rtx old = SET_DEST (PATTERN (temp));
6551 /* Store into the reload register instead of the pseudo. */
6552 SET_DEST (PATTERN (temp)) = reloadreg;
6553
6554 /* Verify that resulting insn is valid. */
6555 extract_insn (temp);
6556 if (constrain_operands (1))
6557 {
6558 /* If the previous insn is an output reload, the source is
6559 a reload register, and its spill_reg_store entry will
6560 contain the previous destination. This is now
6561 invalid. */
6562 if (REG_P (SET_SRC (PATTERN (temp)))
6563 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6564 {
6565 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6566 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6567 }
6568
6569 /* If these are the only uses of the pseudo reg,
6570 pretend for GDB it lives in the reload reg we used. */
6571 if (REG_N_DEATHS (REGNO (old)) == 1
6572 && REG_N_SETS (REGNO (old)) == 1)
6573 {
6574 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6575 alter_reg (REGNO (old), -1);
6576 }
6577 special = 1;
6578 }
6579 else
6580 {
6581 SET_DEST (PATTERN (temp)) = old;
6582 }
6583 }
6584 }
6585
6586 /* We can't do that, so output an insn to load RELOADREG. */
6587
6588 /* If we have a secondary reload, pick up the secondary register
6589 and icode, if any. If OLDEQUIV and OLD are different or
6590 if this is an in-out reload, recompute whether or not we
6591 still need a secondary register and what the icode should
6592 be. If we still need a secondary register and the class or
6593 icode is different, go back to reloading from OLD if using
6594 OLDEQUIV means that we got the wrong type of register. We
6595 cannot have different class or icode due to an in-out reload
6596 because we don't make such reloads when both the input and
6597 output need secondary reload registers. */
6598
6599 if (! special && rl->secondary_in_reload >= 0)
6600 {
6601 rtx second_reload_reg = 0;
6602 rtx third_reload_reg = 0;
6603 int secondary_reload = rl->secondary_in_reload;
6604 rtx real_oldequiv = oldequiv;
6605 rtx real_old = old;
6606 rtx tmp;
6607 enum insn_code icode;
6608 enum insn_code tertiary_icode = CODE_FOR_nothing;
6609
6610 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6611 and similarly for OLD.
6612 See comments in get_secondary_reload in reload.c. */
6613 /* If it is a pseudo that cannot be replaced with its
6614 equivalent MEM, we must fall back to reload_in, which
6615 will have all the necessary substitutions registered.
6616 Likewise for a pseudo that can't be replaced with its
6617 equivalent constant.
6618
6619 Take extra care for subregs of such pseudos. Note that
6620 we cannot use reg_equiv_mem in this case because it is
6621 not in the right mode. */
6622
6623 tmp = oldequiv;
6624 if (GET_CODE (tmp) == SUBREG)
6625 tmp = SUBREG_REG (tmp);
6626 if (REG_P (tmp)
6627 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6628 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6629 || reg_equiv_constant[REGNO (tmp)] != 0))
6630 {
6631 if (! reg_equiv_mem[REGNO (tmp)]
6632 || num_not_at_initial_offset
6633 || GET_CODE (oldequiv) == SUBREG)
6634 real_oldequiv = rl->in;
6635 else
6636 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6637 }
6638
6639 tmp = old;
6640 if (GET_CODE (tmp) == SUBREG)
6641 tmp = SUBREG_REG (tmp);
6642 if (REG_P (tmp)
6643 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6644 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6645 || reg_equiv_constant[REGNO (tmp)] != 0))
6646 {
6647 if (! reg_equiv_mem[REGNO (tmp)]
6648 || num_not_at_initial_offset
6649 || GET_CODE (old) == SUBREG)
6650 real_old = rl->in;
6651 else
6652 real_old = reg_equiv_mem[REGNO (tmp)];
6653 }
6654
6655 second_reload_reg = rld[secondary_reload].reg_rtx;
6656 if (rld[secondary_reload].secondary_in_reload >= 0)
6657 {
6658 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
6659
6660 third_reload_reg = rld[tertiary_reload].reg_rtx;
6661 tertiary_icode = rld[secondary_reload].secondary_in_icode;
6662 /* We'd have to add more code for quartary reloads. */
6663 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
6664 }
6665 icode = rl->secondary_in_icode;
6666
6667 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6668 || (rl->in != 0 && rl->out != 0))
6669 {
6670 secondary_reload_info sri, sri2;
6671 enum reg_class new_class, new_t_class;
6672
6673 sri.icode = CODE_FOR_nothing;
6674 sri.prev_sri = NULL;
6675 new_class = targetm.secondary_reload (1, real_oldequiv, rl->class,
6676 mode, &sri);
6677
6678 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
6679 second_reload_reg = 0;
6680 else if (new_class == NO_REGS)
6681 {
6682 if (reload_adjust_reg_for_icode (&second_reload_reg,
6683 third_reload_reg, sri.icode))
6684 icode = sri.icode, third_reload_reg = 0;
6685 else
6686 oldequiv = old, real_oldequiv = real_old;
6687 }
6688 else if (sri.icode != CODE_FOR_nothing)
6689 /* We currently lack a way to express this in reloads. */
6690 gcc_unreachable ();
6691 else
6692 {
6693 sri2.icode = CODE_FOR_nothing;
6694 sri2.prev_sri = &sri;
6695 new_t_class = targetm.secondary_reload (1, real_oldequiv,
6696 new_class, mode, &sri);
6697 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
6698 {
6699 if (reload_adjust_reg_for_temp (&second_reload_reg,
6700 third_reload_reg,
6701 new_class, mode))
6702 third_reload_reg = 0, tertiary_icode = sri2.icode;
6703 else
6704 oldequiv = old, real_oldequiv = real_old;
6705 }
6706 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
6707 {
6708 rtx intermediate = second_reload_reg;
6709
6710 if (reload_adjust_reg_for_temp (&intermediate, NULL,
6711 new_class, mode)
6712 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
6713 sri2.icode))
6714 {
6715 second_reload_reg = intermediate;
6716 tertiary_icode = sri2.icode;
6717 }
6718 else
6719 oldequiv = old, real_oldequiv = real_old;
6720 }
6721 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
6722 {
6723 rtx intermediate = second_reload_reg;
6724
6725 if (reload_adjust_reg_for_temp (&intermediate, NULL,
6726 new_class, mode)
6727 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
6728 new_t_class, mode))
6729 {
6730 second_reload_reg = intermediate;
6731 tertiary_icode = sri2.icode;
6732 }
6733 else
6734 oldequiv = old, real_oldequiv = real_old;
6735 }
6736 else
6737 /* This could be handled more intelligently too. */
6738 oldequiv = old, real_oldequiv = real_old;
6739 }
6740 }
6741
6742 /* If we still need a secondary reload register, check
6743 to see if it is being used as a scratch or intermediate
6744 register and generate code appropriately. If we need
6745 a scratch register, use REAL_OLDEQUIV since the form of
6746 the insn may depend on the actual address if it is
6747 a MEM. */
6748
6749 if (second_reload_reg)
6750 {
6751 if (icode != CODE_FOR_nothing)
6752 {
6753 /* We'd have to add extra code to handle this case. */
6754 gcc_assert (!third_reload_reg);
6755
6756 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6757 second_reload_reg));
6758 special = 1;
6759 }
6760 else
6761 {
6762 /* See if we need a scratch register to load the
6763 intermediate register (a tertiary reload). */
6764 if (tertiary_icode != CODE_FOR_nothing)
6765 {
6766 emit_insn ((GEN_FCN (tertiary_icode)
6767 (second_reload_reg, real_oldequiv,
6768 third_reload_reg)));
6769 }
6770 else if (third_reload_reg)
6771 {
6772 gen_reload (third_reload_reg, real_oldequiv,
6773 rl->opnum,
6774 rl->when_needed);
6775 gen_reload (second_reload_reg, third_reload_reg,
6776 rl->opnum,
6777 rl->when_needed);
6778 }
6779 else
6780 gen_reload (second_reload_reg, real_oldequiv,
6781 rl->opnum,
6782 rl->when_needed);
6783
6784 oldequiv = second_reload_reg;
6785 }
6786 }
6787 }
6788
6789 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6790 {
6791 rtx real_oldequiv = oldequiv;
6792
6793 if ((REG_P (oldequiv)
6794 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6795 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6796 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6797 || (GET_CODE (oldequiv) == SUBREG
6798 && REG_P (SUBREG_REG (oldequiv))
6799 && (REGNO (SUBREG_REG (oldequiv))
6800 >= FIRST_PSEUDO_REGISTER)
6801 && ((reg_equiv_memory_loc
6802 [REGNO (SUBREG_REG (oldequiv))] != 0)
6803 || (reg_equiv_constant
6804 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6805 || (CONSTANT_P (oldequiv)
6806 && (PREFERRED_RELOAD_CLASS (oldequiv,
6807 REGNO_REG_CLASS (REGNO (reloadreg)))
6808 == NO_REGS)))
6809 real_oldequiv = rl->in;
6810 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6811 rl->when_needed);
6812 }
6813
6814 if (flag_non_call_exceptions)
6815 copy_eh_notes (insn, get_insns ());
6816
6817 /* End this sequence. */
6818 *where = get_insns ();
6819 end_sequence ();
6820
6821 /* Update reload_override_in so that delete_address_reloads_1
6822 can see the actual register usage. */
6823 if (oldequiv_reg)
6824 reload_override_in[j] = oldequiv;
6825 }
6826
6827 /* Generate insns to for the output reload RL, which is for the insn described
6828 by CHAIN and has the number J. */
6829 static void
emit_output_reload_insns(struct insn_chain * chain,struct reload * rl,int j)6830 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
6831 int j)
6832 {
6833 rtx reloadreg = rl->reg_rtx;
6834 rtx insn = chain->insn;
6835 int special = 0;
6836 rtx old = rl->out;
6837 enum machine_mode mode = GET_MODE (old);
6838 rtx p;
6839
6840 if (rl->when_needed == RELOAD_OTHER)
6841 start_sequence ();
6842 else
6843 push_to_sequence (output_reload_insns[rl->opnum]);
6844
6845 /* Determine the mode to reload in.
6846 See comments above (for input reloading). */
6847
6848 if (mode == VOIDmode)
6849 {
6850 /* VOIDmode should never happen for an output. */
6851 if (asm_noperands (PATTERN (insn)) < 0)
6852 /* It's the compiler's fault. */
6853 fatal_insn ("VOIDmode on an output", insn);
6854 error_for_asm (insn, "output operand is constant in %<asm%>");
6855 /* Prevent crash--use something we know is valid. */
6856 mode = word_mode;
6857 old = gen_rtx_REG (mode, REGNO (reloadreg));
6858 }
6859
6860 if (GET_MODE (reloadreg) != mode)
6861 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6862
6863 /* If we need two reload regs, set RELOADREG to the intermediate
6864 one, since it will be stored into OLD. We might need a secondary
6865 register only for an input reload, so check again here. */
6866
6867 if (rl->secondary_out_reload >= 0)
6868 {
6869 rtx real_old = old;
6870 int secondary_reload = rl->secondary_out_reload;
6871 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
6872
6873 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
6874 && reg_equiv_mem[REGNO (old)] != 0)
6875 real_old = reg_equiv_mem[REGNO (old)];
6876
6877 if (secondary_reload_class (0, rl->class, mode, real_old) != NO_REGS)
6878 {
6879 rtx second_reloadreg = reloadreg;
6880 reloadreg = rld[secondary_reload].reg_rtx;
6881
6882 /* See if RELOADREG is to be used as a scratch register
6883 or as an intermediate register. */
6884 if (rl->secondary_out_icode != CODE_FOR_nothing)
6885 {
6886 /* We'd have to add extra code to handle this case. */
6887 gcc_assert (tertiary_reload < 0);
6888
6889 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6890 (real_old, second_reloadreg, reloadreg)));
6891 special = 1;
6892 }
6893 else
6894 {
6895 /* See if we need both a scratch and intermediate reload
6896 register. */
6897
6898 enum insn_code tertiary_icode
6899 = rld[secondary_reload].secondary_out_icode;
6900
6901 /* We'd have to add more code for quartary reloads. */
6902 gcc_assert (tertiary_reload < 0
6903 || rld[tertiary_reload].secondary_out_reload < 0);
6904
6905 if (GET_MODE (reloadreg) != mode)
6906 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6907
6908 if (tertiary_icode != CODE_FOR_nothing)
6909 {
6910 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
6911 rtx tem;
6912
6913 /* Copy primary reload reg to secondary reload reg.
6914 (Note that these have been swapped above, then
6915 secondary reload reg to OLD using our insn.) */
6916
6917 /* If REAL_OLD is a paradoxical SUBREG, remove it
6918 and try to put the opposite SUBREG on
6919 RELOADREG. */
6920 if (GET_CODE (real_old) == SUBREG
6921 && (GET_MODE_SIZE (GET_MODE (real_old))
6922 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6923 && 0 != (tem = gen_lowpart_common
6924 (GET_MODE (SUBREG_REG (real_old)),
6925 reloadreg)))
6926 real_old = SUBREG_REG (real_old), reloadreg = tem;
6927
6928 gen_reload (reloadreg, second_reloadreg,
6929 rl->opnum, rl->when_needed);
6930 emit_insn ((GEN_FCN (tertiary_icode)
6931 (real_old, reloadreg, third_reloadreg)));
6932 special = 1;
6933 }
6934
6935 else
6936 {
6937 /* Copy between the reload regs here and then to
6938 OUT later. */
6939
6940 gen_reload (reloadreg, second_reloadreg,
6941 rl->opnum, rl->when_needed);
6942 if (tertiary_reload >= 0)
6943 {
6944 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
6945
6946 gen_reload (third_reloadreg, reloadreg,
6947 rl->opnum, rl->when_needed);
6948 reloadreg = third_reloadreg;
6949 }
6950 }
6951 }
6952 }
6953 }
6954
6955 /* Output the last reload insn. */
6956 if (! special)
6957 {
6958 rtx set;
6959
6960 /* Don't output the last reload if OLD is not the dest of
6961 INSN and is in the src and is clobbered by INSN. */
6962 if (! flag_expensive_optimizations
6963 || !REG_P (old)
6964 || !(set = single_set (insn))
6965 || rtx_equal_p (old, SET_DEST (set))
6966 || !reg_mentioned_p (old, SET_SRC (set))
6967 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
6968 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
6969 gen_reload (old, reloadreg, rl->opnum,
6970 rl->when_needed);
6971 }
6972
6973 /* Look at all insns we emitted, just to be safe. */
6974 for (p = get_insns (); p; p = NEXT_INSN (p))
6975 if (INSN_P (p))
6976 {
6977 rtx pat = PATTERN (p);
6978
6979 /* If this output reload doesn't come from a spill reg,
6980 clear any memory of reloaded copies of the pseudo reg.
6981 If this output reload comes from a spill reg,
6982 reg_has_output_reload will make this do nothing. */
6983 note_stores (pat, forget_old_reloads_1, NULL);
6984
6985 if (reg_mentioned_p (rl->reg_rtx, pat))
6986 {
6987 rtx set = single_set (insn);
6988 if (reload_spill_index[j] < 0
6989 && set
6990 && SET_SRC (set) == rl->reg_rtx)
6991 {
6992 int src = REGNO (SET_SRC (set));
6993
6994 reload_spill_index[j] = src;
6995 SET_HARD_REG_BIT (reg_is_output_reload, src);
6996 if (find_regno_note (insn, REG_DEAD, src))
6997 SET_HARD_REG_BIT (reg_reloaded_died, src);
6998 }
6999 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
7000 {
7001 int s = rl->secondary_out_reload;
7002 set = single_set (p);
7003 /* If this reload copies only to the secondary reload
7004 register, the secondary reload does the actual
7005 store. */
7006 if (s >= 0 && set == NULL_RTX)
7007 /* We can't tell what function the secondary reload
7008 has and where the actual store to the pseudo is
7009 made; leave new_spill_reg_store alone. */
7010 ;
7011 else if (s >= 0
7012 && SET_SRC (set) == rl->reg_rtx
7013 && SET_DEST (set) == rld[s].reg_rtx)
7014 {
7015 /* Usually the next instruction will be the
7016 secondary reload insn; if we can confirm
7017 that it is, setting new_spill_reg_store to
7018 that insn will allow an extra optimization. */
7019 rtx s_reg = rld[s].reg_rtx;
7020 rtx next = NEXT_INSN (p);
7021 rld[s].out = rl->out;
7022 rld[s].out_reg = rl->out_reg;
7023 set = single_set (next);
7024 if (set && SET_SRC (set) == s_reg
7025 && ! new_spill_reg_store[REGNO (s_reg)])
7026 {
7027 SET_HARD_REG_BIT (reg_is_output_reload,
7028 REGNO (s_reg));
7029 new_spill_reg_store[REGNO (s_reg)] = next;
7030 }
7031 }
7032 else
7033 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
7034 }
7035 }
7036 }
7037
7038 if (rl->when_needed == RELOAD_OTHER)
7039 {
7040 emit_insn (other_output_reload_insns[rl->opnum]);
7041 other_output_reload_insns[rl->opnum] = get_insns ();
7042 }
7043 else
7044 output_reload_insns[rl->opnum] = get_insns ();
7045
7046 if (flag_non_call_exceptions)
7047 copy_eh_notes (insn, get_insns ());
7048
7049 end_sequence ();
7050 }
7051
7052 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7053 and has the number J. */
7054 static void
do_input_reload(struct insn_chain * chain,struct reload * rl,int j)7055 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7056 {
7057 rtx insn = chain->insn;
7058 rtx old = (rl->in && MEM_P (rl->in)
7059 ? rl->in_reg : rl->in);
7060
7061 if (old != 0
7062 /* AUTO_INC reloads need to be handled even if inherited. We got an
7063 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7064 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7065 && ! rtx_equal_p (rl->reg_rtx, old)
7066 && rl->reg_rtx != 0)
7067 emit_input_reload_insns (chain, rld + j, old, j);
7068
7069 /* When inheriting a wider reload, we have a MEM in rl->in,
7070 e.g. inheriting a SImode output reload for
7071 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7072 if (optimize && reload_inherited[j] && rl->in
7073 && MEM_P (rl->in)
7074 && MEM_P (rl->in_reg)
7075 && reload_spill_index[j] >= 0
7076 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7077 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7078
7079 /* If we are reloading a register that was recently stored in with an
7080 output-reload, see if we can prove there was
7081 actually no need to store the old value in it. */
7082
7083 if (optimize
7084 /* Only attempt this for input reloads; for RELOAD_OTHER we miss
7085 that there may be multiple uses of the previous output reload.
7086 Restricting to RELOAD_FOR_INPUT is mostly paranoia. */
7087 && rl->when_needed == RELOAD_FOR_INPUT
7088 && (reload_inherited[j] || reload_override_in[j])
7089 && rl->reg_rtx
7090 && REG_P (rl->reg_rtx)
7091 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
7092 #if 0
7093 /* There doesn't seem to be any reason to restrict this to pseudos
7094 and doing so loses in the case where we are copying from a
7095 register of the wrong class. */
7096 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
7097 >= FIRST_PSEUDO_REGISTER)
7098 #endif
7099 /* The insn might have already some references to stackslots
7100 replaced by MEMs, while reload_out_reg still names the
7101 original pseudo. */
7102 && (dead_or_set_p (insn,
7103 spill_reg_stored_to[REGNO (rl->reg_rtx)])
7104 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
7105 rl->out_reg)))
7106 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
7107 }
7108
7109 /* Do output reloading for reload RL, which is for the insn described by
7110 CHAIN and has the number J.
7111 ??? At some point we need to support handling output reloads of
7112 JUMP_INSNs or insns that set cc0. */
7113 static void
do_output_reload(struct insn_chain * chain,struct reload * rl,int j)7114 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7115 {
7116 rtx note, old;
7117 rtx insn = chain->insn;
7118 /* If this is an output reload that stores something that is
7119 not loaded in this same reload, see if we can eliminate a previous
7120 store. */
7121 rtx pseudo = rl->out_reg;
7122
7123 if (pseudo
7124 && optimize
7125 && REG_P (pseudo)
7126 && ! rtx_equal_p (rl->in_reg, pseudo)
7127 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7128 && reg_last_reload_reg[REGNO (pseudo)])
7129 {
7130 int pseudo_no = REGNO (pseudo);
7131 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7132
7133 /* We don't need to test full validity of last_regno for
7134 inherit here; we only want to know if the store actually
7135 matches the pseudo. */
7136 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7137 && reg_reloaded_contents[last_regno] == pseudo_no
7138 && spill_reg_store[last_regno]
7139 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7140 delete_output_reload (insn, j, last_regno);
7141 }
7142
7143 old = rl->out_reg;
7144 if (old == 0
7145 || rl->reg_rtx == old
7146 || rl->reg_rtx == 0)
7147 return;
7148
7149 /* An output operand that dies right away does need a reload,
7150 but need not be copied from it. Show the new location in the
7151 REG_UNUSED note. */
7152 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7153 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7154 {
7155 XEXP (note, 0) = rl->reg_rtx;
7156 return;
7157 }
7158 /* Likewise for a SUBREG of an operand that dies. */
7159 else if (GET_CODE (old) == SUBREG
7160 && REG_P (SUBREG_REG (old))
7161 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7162 SUBREG_REG (old))))
7163 {
7164 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
7165 rl->reg_rtx);
7166 return;
7167 }
7168 else if (GET_CODE (old) == SCRATCH)
7169 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7170 but we don't want to make an output reload. */
7171 return;
7172
7173 /* If is a JUMP_INSN, we can't support output reloads yet. */
7174 gcc_assert (NONJUMP_INSN_P (insn));
7175
7176 emit_output_reload_insns (chain, rld + j, j);
7177 }
7178
7179 /* Reload number R reloads from or to a group of hard registers starting at
7180 register REGNO. Return true if it can be treated for inheritance purposes
7181 like a group of reloads, each one reloading a single hard register.
7182 The caller has already checked that the spill register and REGNO use
7183 the same number of registers to store the reload value. */
7184
7185 static bool
inherit_piecemeal_p(int r ATTRIBUTE_UNUSED,int regno ATTRIBUTE_UNUSED)7186 inherit_piecemeal_p (int r ATTRIBUTE_UNUSED, int regno ATTRIBUTE_UNUSED)
7187 {
7188 #ifdef CANNOT_CHANGE_MODE_CLASS
7189 return (!REG_CANNOT_CHANGE_MODE_P (reload_spill_index[r],
7190 GET_MODE (rld[r].reg_rtx),
7191 reg_raw_mode[reload_spill_index[r]])
7192 && !REG_CANNOT_CHANGE_MODE_P (regno,
7193 GET_MODE (rld[r].reg_rtx),
7194 reg_raw_mode[regno]));
7195 #else
7196 return true;
7197 #endif
7198 }
7199
7200 /* Output insns to reload values in and out of the chosen reload regs. */
7201
7202 static void
emit_reload_insns(struct insn_chain * chain)7203 emit_reload_insns (struct insn_chain *chain)
7204 {
7205 rtx insn = chain->insn;
7206
7207 int j;
7208
7209 CLEAR_HARD_REG_SET (reg_reloaded_died);
7210
7211 for (j = 0; j < reload_n_operands; j++)
7212 input_reload_insns[j] = input_address_reload_insns[j]
7213 = inpaddr_address_reload_insns[j]
7214 = output_reload_insns[j] = output_address_reload_insns[j]
7215 = outaddr_address_reload_insns[j]
7216 = other_output_reload_insns[j] = 0;
7217 other_input_address_reload_insns = 0;
7218 other_input_reload_insns = 0;
7219 operand_reload_insns = 0;
7220 other_operand_reload_insns = 0;
7221
7222 /* Dump reloads into the dump file. */
7223 if (dump_file)
7224 {
7225 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7226 debug_reload_to_stream (dump_file);
7227 }
7228
7229 /* Now output the instructions to copy the data into and out of the
7230 reload registers. Do these in the order that the reloads were reported,
7231 since reloads of base and index registers precede reloads of operands
7232 and the operands may need the base and index registers reloaded. */
7233
7234 for (j = 0; j < n_reloads; j++)
7235 {
7236 if (rld[j].reg_rtx
7237 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
7238 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
7239
7240 do_input_reload (chain, rld + j, j);
7241 do_output_reload (chain, rld + j, j);
7242 }
7243
7244 /* Now write all the insns we made for reloads in the order expected by
7245 the allocation functions. Prior to the insn being reloaded, we write
7246 the following reloads:
7247
7248 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7249
7250 RELOAD_OTHER reloads.
7251
7252 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7253 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7254 RELOAD_FOR_INPUT reload for the operand.
7255
7256 RELOAD_FOR_OPADDR_ADDRS reloads.
7257
7258 RELOAD_FOR_OPERAND_ADDRESS reloads.
7259
7260 After the insn being reloaded, we write the following:
7261
7262 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7263 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7264 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7265 reloads for the operand. The RELOAD_OTHER output reloads are
7266 output in descending order by reload number. */
7267
7268 emit_insn_before (other_input_address_reload_insns, insn);
7269 emit_insn_before (other_input_reload_insns, insn);
7270
7271 for (j = 0; j < reload_n_operands; j++)
7272 {
7273 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7274 emit_insn_before (input_address_reload_insns[j], insn);
7275 emit_insn_before (input_reload_insns[j], insn);
7276 }
7277
7278 emit_insn_before (other_operand_reload_insns, insn);
7279 emit_insn_before (operand_reload_insns, insn);
7280
7281 for (j = 0; j < reload_n_operands; j++)
7282 {
7283 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7284 x = emit_insn_after (output_address_reload_insns[j], x);
7285 x = emit_insn_after (output_reload_insns[j], x);
7286 emit_insn_after (other_output_reload_insns[j], x);
7287 }
7288
7289 /* For all the spill regs newly reloaded in this instruction,
7290 record what they were reloaded from, so subsequent instructions
7291 can inherit the reloads.
7292
7293 Update spill_reg_store for the reloads of this insn.
7294 Copy the elements that were updated in the loop above. */
7295
7296 for (j = 0; j < n_reloads; j++)
7297 {
7298 int r = reload_order[j];
7299 int i = reload_spill_index[r];
7300
7301 /* If this is a non-inherited input reload from a pseudo, we must
7302 clear any memory of a previous store to the same pseudo. Only do
7303 something if there will not be an output reload for the pseudo
7304 being reloaded. */
7305 if (rld[r].in_reg != 0
7306 && ! (reload_inherited[r] || reload_override_in[r]))
7307 {
7308 rtx reg = rld[r].in_reg;
7309
7310 if (GET_CODE (reg) == SUBREG)
7311 reg = SUBREG_REG (reg);
7312
7313 if (REG_P (reg)
7314 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7315 && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg)))
7316 {
7317 int nregno = REGNO (reg);
7318
7319 if (reg_last_reload_reg[nregno])
7320 {
7321 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7322
7323 if (reg_reloaded_contents[last_regno] == nregno)
7324 spill_reg_store[last_regno] = 0;
7325 }
7326 }
7327 }
7328
7329 /* I is nonneg if this reload used a register.
7330 If rld[r].reg_rtx is 0, this is an optional reload
7331 that we opted to ignore. */
7332
7333 if (i >= 0 && rld[r].reg_rtx != 0)
7334 {
7335 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7336 int k;
7337 int part_reaches_end = 0;
7338 int all_reaches_end = 1;
7339
7340 /* For a multi register reload, we need to check if all or part
7341 of the value lives to the end. */
7342 for (k = 0; k < nr; k++)
7343 {
7344 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7345 rld[r].when_needed))
7346 part_reaches_end = 1;
7347 else
7348 all_reaches_end = 0;
7349 }
7350
7351 /* Ignore reloads that don't reach the end of the insn in
7352 entirety. */
7353 if (all_reaches_end)
7354 {
7355 /* First, clear out memory of what used to be in this spill reg.
7356 If consecutive registers are used, clear them all. */
7357
7358 for (k = 0; k < nr; k++)
7359 {
7360 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7361 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7362 }
7363
7364 /* Maybe the spill reg contains a copy of reload_out. */
7365 if (rld[r].out != 0
7366 && (REG_P (rld[r].out)
7367 #ifdef AUTO_INC_DEC
7368 || ! rld[r].out_reg
7369 #endif
7370 || REG_P (rld[r].out_reg)))
7371 {
7372 rtx out = (REG_P (rld[r].out)
7373 ? rld[r].out
7374 : rld[r].out_reg
7375 ? rld[r].out_reg
7376 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7377 int nregno = REGNO (out);
7378 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7379 : hard_regno_nregs[nregno]
7380 [GET_MODE (rld[r].reg_rtx)]);
7381 bool piecemeal;
7382
7383 spill_reg_store[i] = new_spill_reg_store[i];
7384 spill_reg_stored_to[i] = out;
7385 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7386
7387 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7388 && nr == nnr
7389 && inherit_piecemeal_p (r, nregno));
7390
7391 /* If NREGNO is a hard register, it may occupy more than
7392 one register. If it does, say what is in the
7393 rest of the registers assuming that both registers
7394 agree on how many words the object takes. If not,
7395 invalidate the subsequent registers. */
7396
7397 if (nregno < FIRST_PSEUDO_REGISTER)
7398 for (k = 1; k < nnr; k++)
7399 reg_last_reload_reg[nregno + k]
7400 = (piecemeal
7401 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7402 : 0);
7403
7404 /* Now do the inverse operation. */
7405 for (k = 0; k < nr; k++)
7406 {
7407 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7408 reg_reloaded_contents[i + k]
7409 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7410 ? nregno
7411 : nregno + k);
7412 reg_reloaded_insn[i + k] = insn;
7413 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7414 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (out)))
7415 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7416 }
7417 }
7418
7419 /* Maybe the spill reg contains a copy of reload_in. Only do
7420 something if there will not be an output reload for
7421 the register being reloaded. */
7422 else if (rld[r].out_reg == 0
7423 && rld[r].in != 0
7424 && ((REG_P (rld[r].in)
7425 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7426 && !REGNO_REG_SET_P (®_has_output_reload,
7427 REGNO (rld[r].in)))
7428 || (REG_P (rld[r].in_reg)
7429 && !REGNO_REG_SET_P (®_has_output_reload,
7430 REGNO (rld[r].in_reg))))
7431 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7432 {
7433 int nregno;
7434 int nnr;
7435 rtx in;
7436 bool piecemeal;
7437
7438 if (REG_P (rld[r].in)
7439 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7440 in = rld[r].in;
7441 else if (REG_P (rld[r].in_reg))
7442 in = rld[r].in_reg;
7443 else
7444 in = XEXP (rld[r].in_reg, 0);
7445 nregno = REGNO (in);
7446
7447 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7448 : hard_regno_nregs[nregno]
7449 [GET_MODE (rld[r].reg_rtx)]);
7450
7451 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7452
7453 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7454 && nr == nnr
7455 && inherit_piecemeal_p (r, nregno));
7456
7457 if (nregno < FIRST_PSEUDO_REGISTER)
7458 for (k = 1; k < nnr; k++)
7459 reg_last_reload_reg[nregno + k]
7460 = (piecemeal
7461 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7462 : 0);
7463
7464 /* Unless we inherited this reload, show we haven't
7465 recently done a store.
7466 Previous stores of inherited auto_inc expressions
7467 also have to be discarded. */
7468 if (! reload_inherited[r]
7469 || (rld[r].out && ! rld[r].out_reg))
7470 spill_reg_store[i] = 0;
7471
7472 for (k = 0; k < nr; k++)
7473 {
7474 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7475 reg_reloaded_contents[i + k]
7476 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7477 ? nregno
7478 : nregno + k);
7479 reg_reloaded_insn[i + k] = insn;
7480 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7481 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (in)))
7482 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7483 }
7484 }
7485 }
7486
7487 /* However, if part of the reload reaches the end, then we must
7488 invalidate the old info for the part that survives to the end. */
7489 else if (part_reaches_end)
7490 {
7491 for (k = 0; k < nr; k++)
7492 if (reload_reg_reaches_end_p (i + k,
7493 rld[r].opnum,
7494 rld[r].when_needed))
7495 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7496 }
7497 }
7498
7499 /* The following if-statement was #if 0'd in 1.34 (or before...).
7500 It's reenabled in 1.35 because supposedly nothing else
7501 deals with this problem. */
7502
7503 /* If a register gets output-reloaded from a non-spill register,
7504 that invalidates any previous reloaded copy of it.
7505 But forget_old_reloads_1 won't get to see it, because
7506 it thinks only about the original insn. So invalidate it here.
7507 Also do the same thing for RELOAD_OTHER constraints where the
7508 output is discarded. */
7509 if (i < 0
7510 && ((rld[r].out != 0
7511 && (REG_P (rld[r].out)
7512 || (MEM_P (rld[r].out)
7513 && REG_P (rld[r].out_reg))))
7514 || (rld[r].out == 0 && rld[r].out_reg
7515 && REG_P (rld[r].out_reg))))
7516 {
7517 rtx out = ((rld[r].out && REG_P (rld[r].out))
7518 ? rld[r].out : rld[r].out_reg);
7519 int nregno = REGNO (out);
7520 if (nregno >= FIRST_PSEUDO_REGISTER)
7521 {
7522 rtx src_reg, store_insn = NULL_RTX;
7523
7524 reg_last_reload_reg[nregno] = 0;
7525
7526 /* If we can find a hard register that is stored, record
7527 the storing insn so that we may delete this insn with
7528 delete_output_reload. */
7529 src_reg = rld[r].reg_rtx;
7530
7531 /* If this is an optional reload, try to find the source reg
7532 from an input reload. */
7533 if (! src_reg)
7534 {
7535 rtx set = single_set (insn);
7536 if (set && SET_DEST (set) == rld[r].out)
7537 {
7538 int k;
7539
7540 src_reg = SET_SRC (set);
7541 store_insn = insn;
7542 for (k = 0; k < n_reloads; k++)
7543 {
7544 if (rld[k].in == src_reg)
7545 {
7546 src_reg = rld[k].reg_rtx;
7547 break;
7548 }
7549 }
7550 }
7551 }
7552 else
7553 store_insn = new_spill_reg_store[REGNO (src_reg)];
7554 if (src_reg && REG_P (src_reg)
7555 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7556 {
7557 int src_regno = REGNO (src_reg);
7558 int nr = hard_regno_nregs[src_regno][rld[r].mode];
7559 /* The place where to find a death note varies with
7560 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7561 necessarily checked exactly in the code that moves
7562 notes, so just check both locations. */
7563 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7564 if (! note && store_insn)
7565 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7566 while (nr-- > 0)
7567 {
7568 spill_reg_store[src_regno + nr] = store_insn;
7569 spill_reg_stored_to[src_regno + nr] = out;
7570 reg_reloaded_contents[src_regno + nr] = nregno;
7571 reg_reloaded_insn[src_regno + nr] = store_insn;
7572 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7573 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7574 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + nr,
7575 GET_MODE (src_reg)))
7576 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7577 src_regno + nr);
7578 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7579 if (note)
7580 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7581 else
7582 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7583 }
7584 reg_last_reload_reg[nregno] = src_reg;
7585 /* We have to set reg_has_output_reload here, or else
7586 forget_old_reloads_1 will clear reg_last_reload_reg
7587 right away. */
7588 SET_REGNO_REG_SET (®_has_output_reload,
7589 nregno);
7590 }
7591 }
7592 else
7593 {
7594 int num_regs = hard_regno_nregs[nregno][GET_MODE (out)];
7595
7596 while (num_regs-- > 0)
7597 reg_last_reload_reg[nregno + num_regs] = 0;
7598 }
7599 }
7600 }
7601 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7602 }
7603
7604 /* Go through the motions to emit INSN and test if it is strictly valid.
7605 Return the emitted insn if valid, else return NULL. */
7606
7607 static rtx
emit_insn_if_valid_for_reload(rtx insn)7608 emit_insn_if_valid_for_reload (rtx insn)
7609 {
7610 rtx last = get_last_insn ();
7611 int code;
7612
7613 insn = emit_insn (insn);
7614 code = recog_memoized (insn);
7615
7616 if (code >= 0)
7617 {
7618 extract_insn (insn);
7619 /* We want constrain operands to treat this insn strictly in its
7620 validity determination, i.e., the way it would after reload has
7621 completed. */
7622 if (constrain_operands (1))
7623 return insn;
7624 }
7625
7626 delete_insns_since (last);
7627 return NULL;
7628 }
7629
7630 /* Emit code to perform a reload from IN (which may be a reload register) to
7631 OUT (which may also be a reload register). IN or OUT is from operand
7632 OPNUM with reload type TYPE.
7633
7634 Returns first insn emitted. */
7635
7636 static rtx
gen_reload(rtx out,rtx in,int opnum,enum reload_type type)7637 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7638 {
7639 rtx last = get_last_insn ();
7640 rtx tem;
7641
7642 /* If IN is a paradoxical SUBREG, remove it and try to put the
7643 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7644 if (GET_CODE (in) == SUBREG
7645 && (GET_MODE_SIZE (GET_MODE (in))
7646 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7647 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7648 in = SUBREG_REG (in), out = tem;
7649 else if (GET_CODE (out) == SUBREG
7650 && (GET_MODE_SIZE (GET_MODE (out))
7651 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7652 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7653 out = SUBREG_REG (out), in = tem;
7654
7655 /* How to do this reload can get quite tricky. Normally, we are being
7656 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7657 register that didn't get a hard register. In that case we can just
7658 call emit_move_insn.
7659
7660 We can also be asked to reload a PLUS that adds a register or a MEM to
7661 another register, constant or MEM. This can occur during frame pointer
7662 elimination and while reloading addresses. This case is handled by
7663 trying to emit a single insn to perform the add. If it is not valid,
7664 we use a two insn sequence.
7665
7666 Or we can be asked to reload an unary operand that was a fragment of
7667 an addressing mode, into a register. If it isn't recognized as-is,
7668 we try making the unop operand and the reload-register the same:
7669 (set reg:X (unop:X expr:Y))
7670 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
7671
7672 Finally, we could be called to handle an 'o' constraint by putting
7673 an address into a register. In that case, we first try to do this
7674 with a named pattern of "reload_load_address". If no such pattern
7675 exists, we just emit a SET insn and hope for the best (it will normally
7676 be valid on machines that use 'o').
7677
7678 This entire process is made complex because reload will never
7679 process the insns we generate here and so we must ensure that
7680 they will fit their constraints and also by the fact that parts of
7681 IN might be being reloaded separately and replaced with spill registers.
7682 Because of this, we are, in some sense, just guessing the right approach
7683 here. The one listed above seems to work.
7684
7685 ??? At some point, this whole thing needs to be rethought. */
7686
7687 if (GET_CODE (in) == PLUS
7688 && (REG_P (XEXP (in, 0))
7689 || GET_CODE (XEXP (in, 0)) == SUBREG
7690 || MEM_P (XEXP (in, 0)))
7691 && (REG_P (XEXP (in, 1))
7692 || GET_CODE (XEXP (in, 1)) == SUBREG
7693 || CONSTANT_P (XEXP (in, 1))
7694 || MEM_P (XEXP (in, 1))))
7695 {
7696 /* We need to compute the sum of a register or a MEM and another
7697 register, constant, or MEM, and put it into the reload
7698 register. The best possible way of doing this is if the machine
7699 has a three-operand ADD insn that accepts the required operands.
7700
7701 The simplest approach is to try to generate such an insn and see if it
7702 is recognized and matches its constraints. If so, it can be used.
7703
7704 It might be better not to actually emit the insn unless it is valid,
7705 but we need to pass the insn as an operand to `recog' and
7706 `extract_insn' and it is simpler to emit and then delete the insn if
7707 not valid than to dummy things up. */
7708
7709 rtx op0, op1, tem, insn;
7710 int code;
7711
7712 op0 = find_replacement (&XEXP (in, 0));
7713 op1 = find_replacement (&XEXP (in, 1));
7714
7715 /* Since constraint checking is strict, commutativity won't be
7716 checked, so we need to do that here to avoid spurious failure
7717 if the add instruction is two-address and the second operand
7718 of the add is the same as the reload reg, which is frequently
7719 the case. If the insn would be A = B + A, rearrange it so
7720 it will be A = A + B as constrain_operands expects. */
7721
7722 if (REG_P (XEXP (in, 1))
7723 && REGNO (out) == REGNO (XEXP (in, 1)))
7724 tem = op0, op0 = op1, op1 = tem;
7725
7726 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7727 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7728
7729 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
7730 if (insn)
7731 return insn;
7732
7733 /* If that failed, we must use a conservative two-insn sequence.
7734
7735 Use a move to copy one operand into the reload register. Prefer
7736 to reload a constant, MEM or pseudo since the move patterns can
7737 handle an arbitrary operand. If OP1 is not a constant, MEM or
7738 pseudo and OP1 is not a valid operand for an add instruction, then
7739 reload OP1.
7740
7741 After reloading one of the operands into the reload register, add
7742 the reload register to the output register.
7743
7744 If there is another way to do this for a specific machine, a
7745 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7746 we emit below. */
7747
7748 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7749
7750 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
7751 || (REG_P (op1)
7752 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7753 || (code != CODE_FOR_nothing
7754 && ! ((*insn_data[code].operand[2].predicate)
7755 (op1, insn_data[code].operand[2].mode))))
7756 tem = op0, op0 = op1, op1 = tem;
7757
7758 gen_reload (out, op0, opnum, type);
7759
7760 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7761 This fixes a problem on the 32K where the stack pointer cannot
7762 be used as an operand of an add insn. */
7763
7764 if (rtx_equal_p (op0, op1))
7765 op1 = out;
7766
7767 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
7768 if (insn)
7769 {
7770 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7771 REG_NOTES (insn)
7772 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7773 return insn;
7774 }
7775
7776 /* If that failed, copy the address register to the reload register.
7777 Then add the constant to the reload register. */
7778
7779 gen_reload (out, op1, opnum, type);
7780 insn = emit_insn (gen_add2_insn (out, op0));
7781 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7782 }
7783
7784 #ifdef SECONDARY_MEMORY_NEEDED
7785 /* If we need a memory location to do the move, do it that way. */
7786 else if ((REG_P (in) || GET_CODE (in) == SUBREG)
7787 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7788 && (REG_P (out) || GET_CODE (out) == SUBREG)
7789 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7790 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7791 REGNO_REG_CLASS (reg_or_subregno (out)),
7792 GET_MODE (out)))
7793 {
7794 /* Get the memory to use and rewrite both registers to its mode. */
7795 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7796
7797 if (GET_MODE (loc) != GET_MODE (out))
7798 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7799
7800 if (GET_MODE (loc) != GET_MODE (in))
7801 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7802
7803 gen_reload (loc, in, opnum, type);
7804 gen_reload (out, loc, opnum, type);
7805 }
7806 #endif
7807 else if (REG_P (out) && UNARY_P (in))
7808 {
7809 rtx insn;
7810 rtx op1;
7811 rtx out_moded;
7812 rtx set;
7813
7814 op1 = find_replacement (&XEXP (in, 0));
7815 if (op1 != XEXP (in, 0))
7816 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
7817
7818 /* First, try a plain SET. */
7819 set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
7820 if (set)
7821 return set;
7822
7823 /* If that failed, move the inner operand to the reload
7824 register, and try the same unop with the inner expression
7825 replaced with the reload register. */
7826
7827 if (GET_MODE (op1) != GET_MODE (out))
7828 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
7829 else
7830 out_moded = out;
7831
7832 gen_reload (out_moded, op1, opnum, type);
7833
7834 insn
7835 = gen_rtx_SET (VOIDmode, out,
7836 gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
7837 out_moded));
7838 insn = emit_insn_if_valid_for_reload (insn);
7839 if (insn)
7840 {
7841 REG_NOTES (insn)
7842 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7843 return insn;
7844 }
7845
7846 fatal_insn ("Failure trying to reload:", set);
7847 }
7848 /* If IN is a simple operand, use gen_move_insn. */
7849 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
7850 {
7851 tem = emit_insn (gen_move_insn (out, in));
7852 /* IN may contain a LABEL_REF, if so add a REG_LABEL note. */
7853 mark_jump_label (in, tem, 0);
7854 }
7855
7856 #ifdef HAVE_reload_load_address
7857 else if (HAVE_reload_load_address)
7858 emit_insn (gen_reload_load_address (out, in));
7859 #endif
7860
7861 /* Otherwise, just write (set OUT IN) and hope for the best. */
7862 else
7863 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7864
7865 /* Return the first insn emitted.
7866 We can not just return get_last_insn, because there may have
7867 been multiple instructions emitted. Also note that gen_move_insn may
7868 emit more than one insn itself, so we can not assume that there is one
7869 insn emitted per emit_insn_before call. */
7870
7871 return last ? NEXT_INSN (last) : get_insns ();
7872 }
7873
7874 /* Delete a previously made output-reload whose result we now believe
7875 is not needed. First we double-check.
7876
7877 INSN is the insn now being processed.
7878 LAST_RELOAD_REG is the hard register number for which we want to delete
7879 the last output reload.
7880 J is the reload-number that originally used REG. The caller has made
7881 certain that reload J doesn't use REG any longer for input. */
7882
7883 static void
delete_output_reload(rtx insn,int j,int last_reload_reg)7884 delete_output_reload (rtx insn, int j, int last_reload_reg)
7885 {
7886 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7887 rtx reg = spill_reg_stored_to[last_reload_reg];
7888 int k;
7889 int n_occurrences;
7890 int n_inherited = 0;
7891 rtx i1;
7892 rtx substed;
7893
7894 /* It is possible that this reload has been only used to set another reload
7895 we eliminated earlier and thus deleted this instruction too. */
7896 if (INSN_DELETED_P (output_reload_insn))
7897 return;
7898
7899 /* Get the raw pseudo-register referred to. */
7900
7901 while (GET_CODE (reg) == SUBREG)
7902 reg = SUBREG_REG (reg);
7903 substed = reg_equiv_memory_loc[REGNO (reg)];
7904
7905 /* This is unsafe if the operand occurs more often in the current
7906 insn than it is inherited. */
7907 for (k = n_reloads - 1; k >= 0; k--)
7908 {
7909 rtx reg2 = rld[k].in;
7910 if (! reg2)
7911 continue;
7912 if (MEM_P (reg2) || reload_override_in[k])
7913 reg2 = rld[k].in_reg;
7914 #ifdef AUTO_INC_DEC
7915 if (rld[k].out && ! rld[k].out_reg)
7916 reg2 = XEXP (rld[k].in_reg, 0);
7917 #endif
7918 while (GET_CODE (reg2) == SUBREG)
7919 reg2 = SUBREG_REG (reg2);
7920 if (rtx_equal_p (reg2, reg))
7921 {
7922 if (reload_inherited[k] || reload_override_in[k] || k == j)
7923 {
7924 n_inherited++;
7925 reg2 = rld[k].out_reg;
7926 if (! reg2)
7927 continue;
7928 while (GET_CODE (reg2) == SUBREG)
7929 reg2 = XEXP (reg2, 0);
7930 if (rtx_equal_p (reg2, reg))
7931 n_inherited++;
7932 }
7933 else
7934 return;
7935 }
7936 }
7937 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7938 if (substed)
7939 n_occurrences += count_occurrences (PATTERN (insn),
7940 eliminate_regs (substed, 0,
7941 NULL_RTX), 0);
7942 for (i1 = reg_equiv_alt_mem_list [REGNO (reg)]; i1; i1 = XEXP (i1, 1))
7943 {
7944 gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
7945 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
7946 }
7947 if (n_occurrences > n_inherited)
7948 return;
7949
7950 /* If the pseudo-reg we are reloading is no longer referenced
7951 anywhere between the store into it and here,
7952 and we're within the same basic block, then the value can only
7953 pass through the reload reg and end up here.
7954 Otherwise, give up--return. */
7955 for (i1 = NEXT_INSN (output_reload_insn);
7956 i1 != insn; i1 = NEXT_INSN (i1))
7957 {
7958 if (NOTE_INSN_BASIC_BLOCK_P (i1))
7959 return;
7960 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
7961 && reg_mentioned_p (reg, PATTERN (i1)))
7962 {
7963 /* If this is USE in front of INSN, we only have to check that
7964 there are no more references than accounted for by inheritance. */
7965 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
7966 {
7967 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7968 i1 = NEXT_INSN (i1);
7969 }
7970 if (n_occurrences <= n_inherited && i1 == insn)
7971 break;
7972 return;
7973 }
7974 }
7975
7976 /* We will be deleting the insn. Remove the spill reg information. */
7977 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
7978 {
7979 spill_reg_store[last_reload_reg + k] = 0;
7980 spill_reg_stored_to[last_reload_reg + k] = 0;
7981 }
7982
7983 /* The caller has already checked that REG dies or is set in INSN.
7984 It has also checked that we are optimizing, and thus some
7985 inaccuracies in the debugging information are acceptable.
7986 So we could just delete output_reload_insn. But in some cases
7987 we can improve the debugging information without sacrificing
7988 optimization - maybe even improving the code: See if the pseudo
7989 reg has been completely replaced with reload regs. If so, delete
7990 the store insn and forget we had a stack slot for the pseudo. */
7991 if (rld[j].out != rld[j].in
7992 && REG_N_DEATHS (REGNO (reg)) == 1
7993 && REG_N_SETS (REGNO (reg)) == 1
7994 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7995 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7996 {
7997 rtx i2;
7998
7999 /* We know that it was used only between here and the beginning of
8000 the current basic block. (We also know that the last use before
8001 INSN was the output reload we are thinking of deleting, but never
8002 mind that.) Search that range; see if any ref remains. */
8003 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8004 {
8005 rtx set = single_set (i2);
8006
8007 /* Uses which just store in the pseudo don't count,
8008 since if they are the only uses, they are dead. */
8009 if (set != 0 && SET_DEST (set) == reg)
8010 continue;
8011 if (LABEL_P (i2)
8012 || JUMP_P (i2))
8013 break;
8014 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8015 && reg_mentioned_p (reg, PATTERN (i2)))
8016 {
8017 /* Some other ref remains; just delete the output reload we
8018 know to be dead. */
8019 delete_address_reloads (output_reload_insn, insn);
8020 delete_insn (output_reload_insn);
8021 return;
8022 }
8023 }
8024
8025 /* Delete the now-dead stores into this pseudo. Note that this
8026 loop also takes care of deleting output_reload_insn. */
8027 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8028 {
8029 rtx set = single_set (i2);
8030
8031 if (set != 0 && SET_DEST (set) == reg)
8032 {
8033 delete_address_reloads (i2, insn);
8034 delete_insn (i2);
8035 }
8036 if (LABEL_P (i2)
8037 || JUMP_P (i2))
8038 break;
8039 }
8040
8041 /* For the debugging info, say the pseudo lives in this reload reg. */
8042 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
8043 alter_reg (REGNO (reg), -1);
8044 }
8045 else
8046 {
8047 delete_address_reloads (output_reload_insn, insn);
8048 delete_insn (output_reload_insn);
8049 }
8050 }
8051
8052 /* We are going to delete DEAD_INSN. Recursively delete loads of
8053 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8054 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8055 static void
delete_address_reloads(rtx dead_insn,rtx current_insn)8056 delete_address_reloads (rtx dead_insn, rtx current_insn)
8057 {
8058 rtx set = single_set (dead_insn);
8059 rtx set2, dst, prev, next;
8060 if (set)
8061 {
8062 rtx dst = SET_DEST (set);
8063 if (MEM_P (dst))
8064 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8065 }
8066 /* If we deleted the store from a reloaded post_{in,de}c expression,
8067 we can delete the matching adds. */
8068 prev = PREV_INSN (dead_insn);
8069 next = NEXT_INSN (dead_insn);
8070 if (! prev || ! next)
8071 return;
8072 set = single_set (next);
8073 set2 = single_set (prev);
8074 if (! set || ! set2
8075 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8076 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
8077 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
8078 return;
8079 dst = SET_DEST (set);
8080 if (! rtx_equal_p (dst, SET_DEST (set2))
8081 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8082 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8083 || (INTVAL (XEXP (SET_SRC (set), 1))
8084 != -INTVAL (XEXP (SET_SRC (set2), 1))))
8085 return;
8086 delete_related_insns (prev);
8087 delete_related_insns (next);
8088 }
8089
8090 /* Subfunction of delete_address_reloads: process registers found in X. */
8091 static void
delete_address_reloads_1(rtx dead_insn,rtx x,rtx current_insn)8092 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
8093 {
8094 rtx prev, set, dst, i2;
8095 int i, j;
8096 enum rtx_code code = GET_CODE (x);
8097
8098 if (code != REG)
8099 {
8100 const char *fmt = GET_RTX_FORMAT (code);
8101 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8102 {
8103 if (fmt[i] == 'e')
8104 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8105 else if (fmt[i] == 'E')
8106 {
8107 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8108 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8109 current_insn);
8110 }
8111 }
8112 return;
8113 }
8114
8115 if (spill_reg_order[REGNO (x)] < 0)
8116 return;
8117
8118 /* Scan backwards for the insn that sets x. This might be a way back due
8119 to inheritance. */
8120 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8121 {
8122 code = GET_CODE (prev);
8123 if (code == CODE_LABEL || code == JUMP_INSN)
8124 return;
8125 if (!INSN_P (prev))
8126 continue;
8127 if (reg_set_p (x, PATTERN (prev)))
8128 break;
8129 if (reg_referenced_p (x, PATTERN (prev)))
8130 return;
8131 }
8132 if (! prev || INSN_UID (prev) < reload_first_uid)
8133 return;
8134 /* Check that PREV only sets the reload register. */
8135 set = single_set (prev);
8136 if (! set)
8137 return;
8138 dst = SET_DEST (set);
8139 if (!REG_P (dst)
8140 || ! rtx_equal_p (dst, x))
8141 return;
8142 if (! reg_set_p (dst, PATTERN (dead_insn)))
8143 {
8144 /* Check if DST was used in a later insn -
8145 it might have been inherited. */
8146 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8147 {
8148 if (LABEL_P (i2))
8149 break;
8150 if (! INSN_P (i2))
8151 continue;
8152 if (reg_referenced_p (dst, PATTERN (i2)))
8153 {
8154 /* If there is a reference to the register in the current insn,
8155 it might be loaded in a non-inherited reload. If no other
8156 reload uses it, that means the register is set before
8157 referenced. */
8158 if (i2 == current_insn)
8159 {
8160 for (j = n_reloads - 1; j >= 0; j--)
8161 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8162 || reload_override_in[j] == dst)
8163 return;
8164 for (j = n_reloads - 1; j >= 0; j--)
8165 if (rld[j].in && rld[j].reg_rtx == dst)
8166 break;
8167 if (j >= 0)
8168 break;
8169 }
8170 return;
8171 }
8172 if (JUMP_P (i2))
8173 break;
8174 /* If DST is still live at CURRENT_INSN, check if it is used for
8175 any reload. Note that even if CURRENT_INSN sets DST, we still
8176 have to check the reloads. */
8177 if (i2 == current_insn)
8178 {
8179 for (j = n_reloads - 1; j >= 0; j--)
8180 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8181 || reload_override_in[j] == dst)
8182 return;
8183 /* ??? We can't finish the loop here, because dst might be
8184 allocated to a pseudo in this block if no reload in this
8185 block needs any of the classes containing DST - see
8186 spill_hard_reg. There is no easy way to tell this, so we
8187 have to scan till the end of the basic block. */
8188 }
8189 if (reg_set_p (dst, PATTERN (i2)))
8190 break;
8191 }
8192 }
8193 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8194 reg_reloaded_contents[REGNO (dst)] = -1;
8195 delete_insn (prev);
8196 }
8197
8198 /* Output reload-insns to reload VALUE into RELOADREG.
8199 VALUE is an autoincrement or autodecrement RTX whose operand
8200 is a register or memory location;
8201 so reloading involves incrementing that location.
8202 IN is either identical to VALUE, or some cheaper place to reload from.
8203
8204 INC_AMOUNT is the number to increment or decrement by (always positive).
8205 This cannot be deduced from VALUE.
8206
8207 Return the instruction that stores into RELOADREG. */
8208
8209 static rtx
inc_for_reload(rtx reloadreg,rtx in,rtx value,int inc_amount)8210 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
8211 {
8212 /* REG or MEM to be copied and incremented. */
8213 rtx incloc = find_replacement (&XEXP (value, 0));
8214 /* Nonzero if increment after copying. */
8215 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
8216 || GET_CODE (value) == POST_MODIFY);
8217 rtx last;
8218 rtx inc;
8219 rtx add_insn;
8220 int code;
8221 rtx store;
8222 rtx real_in = in == value ? incloc : in;
8223
8224 /* No hard register is equivalent to this register after
8225 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
8226 we could inc/dec that register as well (maybe even using it for
8227 the source), but I'm not sure it's worth worrying about. */
8228 if (REG_P (incloc))
8229 reg_last_reload_reg[REGNO (incloc)] = 0;
8230
8231 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
8232 {
8233 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
8234 inc = find_replacement (&XEXP (XEXP (value, 1), 1));
8235 }
8236 else
8237 {
8238 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8239 inc_amount = -inc_amount;
8240
8241 inc = GEN_INT (inc_amount);
8242 }
8243
8244 /* If this is post-increment, first copy the location to the reload reg. */
8245 if (post && real_in != reloadreg)
8246 emit_insn (gen_move_insn (reloadreg, real_in));
8247
8248 if (in == value)
8249 {
8250 /* See if we can directly increment INCLOC. Use a method similar to
8251 that in gen_reload. */
8252
8253 last = get_last_insn ();
8254 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8255 gen_rtx_PLUS (GET_MODE (incloc),
8256 incloc, inc)));
8257
8258 code = recog_memoized (add_insn);
8259 if (code >= 0)
8260 {
8261 extract_insn (add_insn);
8262 if (constrain_operands (1))
8263 {
8264 /* If this is a pre-increment and we have incremented the value
8265 where it lives, copy the incremented value to RELOADREG to
8266 be used as an address. */
8267
8268 if (! post)
8269 emit_insn (gen_move_insn (reloadreg, incloc));
8270
8271 return add_insn;
8272 }
8273 }
8274 delete_insns_since (last);
8275 }
8276
8277 /* If couldn't do the increment directly, must increment in RELOADREG.
8278 The way we do this depends on whether this is pre- or post-increment.
8279 For pre-increment, copy INCLOC to the reload register, increment it
8280 there, then save back. */
8281
8282 if (! post)
8283 {
8284 if (in != reloadreg)
8285 emit_insn (gen_move_insn (reloadreg, real_in));
8286 emit_insn (gen_add2_insn (reloadreg, inc));
8287 store = emit_insn (gen_move_insn (incloc, reloadreg));
8288 }
8289 else
8290 {
8291 /* Postincrement.
8292 Because this might be a jump insn or a compare, and because RELOADREG
8293 may not be available after the insn in an input reload, we must do
8294 the incrementation before the insn being reloaded for.
8295
8296 We have already copied IN to RELOADREG. Increment the copy in
8297 RELOADREG, save that back, then decrement RELOADREG so it has
8298 the original value. */
8299
8300 emit_insn (gen_add2_insn (reloadreg, inc));
8301 store = emit_insn (gen_move_insn (incloc, reloadreg));
8302 if (GET_CODE (inc) == CONST_INT)
8303 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-INTVAL(inc))));
8304 else
8305 emit_insn (gen_sub2_insn (reloadreg, inc));
8306 }
8307
8308 return store;
8309 }
8310
8311 #ifdef AUTO_INC_DEC
8312 static void
add_auto_inc_notes(rtx insn,rtx x)8313 add_auto_inc_notes (rtx insn, rtx x)
8314 {
8315 enum rtx_code code = GET_CODE (x);
8316 const char *fmt;
8317 int i, j;
8318
8319 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8320 {
8321 REG_NOTES (insn)
8322 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
8323 return;
8324 }
8325
8326 /* Scan all the operand sub-expressions. */
8327 fmt = GET_RTX_FORMAT (code);
8328 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8329 {
8330 if (fmt[i] == 'e')
8331 add_auto_inc_notes (insn, XEXP (x, i));
8332 else if (fmt[i] == 'E')
8333 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8334 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8335 }
8336 }
8337 #endif
8338
8339 /* Copy EH notes from an insn to its reloads. */
8340 static void
copy_eh_notes(rtx insn,rtx x)8341 copy_eh_notes (rtx insn, rtx x)
8342 {
8343 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8344 if (eh_note)
8345 {
8346 for (; x != 0; x = NEXT_INSN (x))
8347 {
8348 if (may_trap_p (PATTERN (x)))
8349 REG_NOTES (x)
8350 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
8351 REG_NOTES (x));
8352 }
8353 }
8354 }
8355
8356 /* This is used by reload pass, that does emit some instructions after
8357 abnormal calls moving basic block end, but in fact it wants to emit
8358 them on the edge. Looks for abnormal call edges, find backward the
8359 proper call and fix the damage.
8360
8361 Similar handle instructions throwing exceptions internally. */
8362 void
fixup_abnormal_edges(void)8363 fixup_abnormal_edges (void)
8364 {
8365 bool inserted = false;
8366 basic_block bb;
8367
8368 FOR_EACH_BB (bb)
8369 {
8370 edge e;
8371 edge_iterator ei;
8372
8373 /* Look for cases we are interested in - calls or instructions causing
8374 exceptions. */
8375 FOR_EACH_EDGE (e, ei, bb->succs)
8376 {
8377 if (e->flags & EDGE_ABNORMAL_CALL)
8378 break;
8379 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8380 == (EDGE_ABNORMAL | EDGE_EH))
8381 break;
8382 }
8383 if (e && !CALL_P (BB_END (bb))
8384 && !can_throw_internal (BB_END (bb)))
8385 {
8386 rtx insn;
8387
8388 /* Get past the new insns generated. Allow notes, as the insns
8389 may be already deleted. */
8390 insn = BB_END (bb);
8391 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8392 && !can_throw_internal (insn)
8393 && insn != BB_HEAD (bb))
8394 insn = PREV_INSN (insn);
8395
8396 if (CALL_P (insn) || can_throw_internal (insn))
8397 {
8398 rtx stop, next;
8399
8400 stop = NEXT_INSN (BB_END (bb));
8401 BB_END (bb) = insn;
8402 insn = NEXT_INSN (insn);
8403
8404 FOR_EACH_EDGE (e, ei, bb->succs)
8405 if (e->flags & EDGE_FALLTHRU)
8406 break;
8407
8408 while (insn && insn != stop)
8409 {
8410 next = NEXT_INSN (insn);
8411 if (INSN_P (insn))
8412 {
8413 delete_insn (insn);
8414
8415 /* Sometimes there's still the return value USE.
8416 If it's placed after a trapping call (i.e. that
8417 call is the last insn anyway), we have no fallthru
8418 edge. Simply delete this use and don't try to insert
8419 on the non-existent edge. */
8420 if (GET_CODE (PATTERN (insn)) != USE)
8421 {
8422 /* We're not deleting it, we're moving it. */
8423 INSN_DELETED_P (insn) = 0;
8424 PREV_INSN (insn) = NULL_RTX;
8425 NEXT_INSN (insn) = NULL_RTX;
8426
8427 insert_insn_on_edge (insn, e);
8428 inserted = true;
8429 }
8430 }
8431 insn = next;
8432 }
8433 }
8434
8435 /* It may be that we don't find any such trapping insn. In this
8436 case we discovered quite late that the insn that had been
8437 marked as can_throw_internal in fact couldn't trap at all.
8438 So we should in fact delete the EH edges out of the block. */
8439 else
8440 purge_dead_edges (bb);
8441 }
8442 }
8443
8444 /* We've possibly turned single trapping insn into multiple ones. */
8445 if (flag_non_call_exceptions)
8446 {
8447 sbitmap blocks;
8448 blocks = sbitmap_alloc (last_basic_block);
8449 sbitmap_ones (blocks);
8450 find_many_sub_basic_blocks (blocks);
8451 }
8452
8453 if (inserted)
8454 commit_edge_insertions ();
8455
8456 #ifdef ENABLE_CHECKING
8457 /* Verify that we didn't turn one trapping insn into many, and that
8458 we found and corrected all of the problems wrt fixups on the
8459 fallthru edge. */
8460 verify_flow_info ();
8461 #endif
8462 }
8463