1 /* Copyright (C) 1997-2022 Free Software Foundation, Inc.
2 Contributed by Red Hat, Inc.
3
4 This file is part of GCC.
5
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
19
20 #define IN_TARGET_CODE 1
21
22 #include "config.h"
23 #include "system.h"
24 #include "coretypes.h"
25 #include "backend.h"
26 #include "target.h"
27 #include "rtl.h"
28 #include "tree.h"
29 #include "df.h"
30 #include "memmodel.h"
31 #include "tm_p.h"
32 #include "stringpool.h"
33 #include "attribs.h"
34 #include "optabs.h"
35 #include "regs.h"
36 #include "emit-rtl.h"
37 #include "recog.h"
38 #include "diagnostic-core.h"
39 #include "fold-const.h"
40 #include "varasm.h"
41 #include "stor-layout.h"
42 #include "output.h"
43 #include "insn-attr.h"
44 #include "explow.h"
45 #include "expr.h"
46 #include "cfgrtl.h"
47 #include "langhooks.h"
48 #include "dumpfile.h"
49 #include "builtins.h"
50 #include "ifcvt.h"
51 #include "rtl-iter.h"
52 #include "calls.h"
53 #include "opts.h"
54
55 /* This file should be included last. */
56 #include "target-def.h"
57
58 #ifndef FRV_INLINE
59 #define FRV_INLINE inline
60 #endif
61
62 /* The maximum number of distinct NOP patterns. There are three:
63 nop, fnop and mnop. */
64 #define NUM_NOP_PATTERNS 3
65
66 /* Classification of instructions and units: integer, floating-point/media,
67 branch and control. */
68 enum frv_insn_group { GROUP_I, GROUP_FM, GROUP_B, GROUP_C, NUM_GROUPS };
69
70 /* The DFA names of the units, in packet order. */
71 static const char *const frv_unit_names[] =
72 {
73 "c",
74 "i0", "f0",
75 "i1", "f1",
76 "i2", "f2",
77 "i3", "f3",
78 "b0", "b1"
79 };
80
81 /* The classification of each unit in frv_unit_names[]. */
82 static const enum frv_insn_group frv_unit_groups[ARRAY_SIZE (frv_unit_names)] =
83 {
84 GROUP_C,
85 GROUP_I, GROUP_FM,
86 GROUP_I, GROUP_FM,
87 GROUP_I, GROUP_FM,
88 GROUP_I, GROUP_FM,
89 GROUP_B, GROUP_B
90 };
91
92 /* Return the DFA unit code associated with the Nth unit of integer
93 or floating-point group GROUP, */
94 #define NTH_UNIT(GROUP, N) frv_unit_codes[(GROUP) + (N) * 2 + 1]
95
96 /* Return the number of integer or floating-point unit UNIT
97 (1 for I1, 2 for F2, etc.). */
98 #define UNIT_NUMBER(UNIT) (((UNIT) - 1) / 2)
99
100 /* The DFA unit number for each unit in frv_unit_names[]. */
101 static int frv_unit_codes[ARRAY_SIZE (frv_unit_names)];
102
103 /* FRV_TYPE_TO_UNIT[T] is the last unit in frv_unit_names[] that can issue
104 an instruction of type T. The value is ARRAY_SIZE (frv_unit_names) if
105 no instruction of type T has been seen. */
106 static unsigned int frv_type_to_unit[TYPE_UNKNOWN + 1];
107
108 /* An array of dummy nop INSNs, one for each type of nop that the
109 target supports. */
110 static GTY(()) rtx_insn *frv_nops[NUM_NOP_PATTERNS];
111
112 /* The number of nop instructions in frv_nops[]. */
113 static unsigned int frv_num_nops;
114
115 /* The type of access. FRV_IO_UNKNOWN means the access can be either
116 a read or a write. */
117 enum frv_io_type { FRV_IO_UNKNOWN, FRV_IO_READ, FRV_IO_WRITE };
118
119 /* Information about one __builtin_read or __builtin_write access, or
120 the combination of several such accesses. The most general value
121 is all-zeros (an unknown access to an unknown address). */
122 struct frv_io {
123 enum frv_io_type type;
124
125 /* The constant address being accessed, or zero if not known. */
126 HOST_WIDE_INT const_address;
127
128 /* The run-time address, as used in operand 0 of the membar pattern. */
129 rtx var_address;
130 };
131
132 /* Return true if instruction INSN should be packed with the following
133 instruction. */
134 #define PACKING_FLAG_P(INSN) (GET_MODE (INSN) == TImode)
135
136 /* Set the value of PACKING_FLAG_P(INSN). */
137 #define SET_PACKING_FLAG(INSN) PUT_MODE (INSN, TImode)
138 #define CLEAR_PACKING_FLAG(INSN) PUT_MODE (INSN, VOIDmode)
139
140 /* Loop with REG set to each hard register in rtx X. */
141 #define FOR_EACH_REGNO(REG, X) \
142 for (REG = REGNO (X); REG < END_REGNO (X); REG++)
143
144 /* This structure contains machine specific function data. */
145 struct GTY(()) machine_function
146 {
147 /* True if we have created an rtx that relies on the stack frame. */
148 int frame_needed;
149
150 /* True if this function contains at least one __builtin_{read,write}*. */
151 bool has_membar_p;
152 };
153
154 /* Temporary register allocation support structure. */
155 typedef struct frv_tmp_reg_struct
156 {
157 HARD_REG_SET regs; /* possible registers to allocate */
158 int next_reg[N_REG_CLASSES]; /* next register to allocate per class */
159 }
160 frv_tmp_reg_t;
161
162 /* Register state information for VLIW re-packing phase. */
163 #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */
164 #define REGSTATE_MODIFIED 0x08 /* reg modified in current VLIW insn */
165 #define REGSTATE_IF_TRUE 0x10 /* reg modified in cond exec true */
166 #define REGSTATE_IF_FALSE 0x20 /* reg modified in cond exec false */
167
168 #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE)
169
170 typedef unsigned char regstate_t;
171
172 /* Used in frv_frame_accessor_t to indicate the direction of a register-to-
173 memory move. */
174 enum frv_stack_op
175 {
176 FRV_LOAD,
177 FRV_STORE
178 };
179
180 /* Information required by frv_frame_access. */
181 typedef struct
182 {
183 /* This field is FRV_LOAD if registers are to be loaded from the stack and
184 FRV_STORE if they should be stored onto the stack. FRV_STORE implies
185 the move is being done by the prologue code while FRV_LOAD implies it
186 is being done by the epilogue. */
187 enum frv_stack_op op;
188
189 /* The base register to use when accessing the stack. This may be the
190 frame pointer, stack pointer, or a temporary. The choice of register
191 depends on which part of the frame is being accessed and how big the
192 frame is. */
193 rtx base;
194
195 /* The offset of BASE from the bottom of the current frame, in bytes. */
196 int base_offset;
197 } frv_frame_accessor_t;
198
199 /* Conditional execution support gathered together in one structure. */
200 typedef struct
201 {
202 /* Linked list of insns to add if the conditional execution conversion was
203 successful. Each link points to an EXPR_LIST which points to the pattern
204 of the insn to add, and the insn to be inserted before. */
205 rtx added_insns_list;
206
207 /* Identify which registers are safe to allocate for if conversions to
208 conditional execution. We keep the last allocated register in the
209 register classes between COND_EXEC statements. This will mean we allocate
210 different registers for each different COND_EXEC group if we can. This
211 might allow the scheduler to intermix two different COND_EXEC sections. */
212 frv_tmp_reg_t tmp_reg;
213
214 /* For nested IFs, identify which CC registers are used outside of setting
215 via a compare isnsn, and using via a check insn. This will allow us to
216 know if we can rewrite the register to use a different register that will
217 be paired with the CR register controlling the nested IF-THEN blocks. */
218 HARD_REG_SET nested_cc_ok_rewrite;
219
220 /* Temporary registers allocated to hold constants during conditional
221 execution. */
222 rtx scratch_regs[FIRST_PSEUDO_REGISTER];
223
224 /* Current number of temp registers available. */
225 int cur_scratch_regs;
226
227 /* Number of nested conditional execution blocks. */
228 int num_nested_cond_exec;
229
230 /* Map of insns that set up constants in scratch registers. */
231 bitmap scratch_insns_bitmap;
232
233 /* Conditional execution test register (CC0..CC7). */
234 rtx cr_reg;
235
236 /* Conditional execution compare register that is paired with cr_reg, so that
237 nested compares can be done. The csubcc and caddcc instructions don't
238 have enough bits to specify both a CC register to be set and a CR register
239 to do the test on, so the same bit number is used for both. Needless to
240 say, this is rather inconvenient for GCC. */
241 rtx nested_cc_reg;
242
243 /* Extra CR registers used for &&, ||. */
244 rtx extra_int_cr;
245 rtx extra_fp_cr;
246
247 /* Previous CR used in nested if, to make sure we are dealing with the same
248 nested if as the previous statement. */
249 rtx last_nested_if_cr;
250 }
251 frv_ifcvt_t;
252
253 static /* GTY(()) */ frv_ifcvt_t frv_ifcvt;
254
255 /* Map register number to smallest register class. */
256 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
257
258 /* Cached value of frv_stack_info. */
259 static frv_stack_t *frv_stack_cache = (frv_stack_t *)0;
260
261 /* Forward references */
262
263 static void frv_option_override (void);
264 static bool frv_legitimate_address_p (machine_mode, rtx, bool);
265 static int frv_default_flags_for_cpu (void);
266 static FRV_INLINE bool frv_small_data_reloc_p (rtx, int);
267 static void frv_print_operand (FILE *, rtx, int);
268 static void frv_print_operand_address (FILE *, machine_mode, rtx);
269 static bool frv_print_operand_punct_valid_p (unsigned char code);
270 static void frv_print_operand_memory_reference_reg
271 (FILE *, rtx);
272 static void frv_print_operand_memory_reference (FILE *, rtx, int);
273 static int frv_print_operand_jump_hint (rtx_insn *);
274 static const char *comparison_string (enum rtx_code, rtx);
275 static rtx frv_function_value (const_tree, const_tree,
276 bool);
277 static rtx frv_libcall_value (machine_mode,
278 const_rtx);
279 static FRV_INLINE int frv_regno_ok_for_base_p (int, int);
280 static rtx single_set_pattern (rtx);
281 static int frv_function_contains_far_jump (void);
282 static rtx frv_alloc_temp_reg (frv_tmp_reg_t *,
283 enum reg_class,
284 machine_mode,
285 int, int);
286 static rtx frv_frame_offset_rtx (int);
287 static rtx frv_frame_mem (machine_mode, rtx, int);
288 static rtx frv_dwarf_store (rtx, int);
289 static void frv_frame_insn (rtx, rtx);
290 static void frv_frame_access (frv_frame_accessor_t*,
291 rtx, int);
292 static void frv_frame_access_multi (frv_frame_accessor_t*,
293 frv_stack_t *, int);
294 static void frv_frame_access_standard_regs (enum frv_stack_op,
295 frv_stack_t *);
296 static struct machine_function *frv_init_machine_status (void);
297 static rtx frv_int_to_acc (enum insn_code, int, rtx);
298 static machine_mode frv_matching_accg_mode (machine_mode);
299 static rtx frv_read_argument (tree, unsigned int);
300 static rtx frv_read_iacc_argument (machine_mode, tree, unsigned int);
301 static int frv_check_constant_argument (enum insn_code, int, rtx);
302 static rtx frv_legitimize_target (enum insn_code, rtx);
303 static rtx frv_legitimize_argument (enum insn_code, int, rtx);
304 static rtx frv_legitimize_tls_address (rtx, enum tls_model);
305 static rtx frv_legitimize_address (rtx, rtx, machine_mode);
306 static rtx frv_expand_set_builtin (enum insn_code, tree, rtx);
307 static rtx frv_expand_unop_builtin (enum insn_code, tree, rtx);
308 static rtx frv_expand_binop_builtin (enum insn_code, tree, rtx);
309 static rtx frv_expand_cut_builtin (enum insn_code, tree, rtx);
310 static rtx frv_expand_binopimm_builtin (enum insn_code, tree, rtx);
311 static rtx frv_expand_voidbinop_builtin (enum insn_code, tree);
312 static rtx frv_expand_int_void2arg (enum insn_code, tree);
313 static rtx frv_expand_prefetches (enum insn_code, tree);
314 static rtx frv_expand_voidtriop_builtin (enum insn_code, tree);
315 static rtx frv_expand_voidaccop_builtin (enum insn_code, tree);
316 static rtx frv_expand_mclracc_builtin (tree);
317 static rtx frv_expand_mrdacc_builtin (enum insn_code, tree);
318 static rtx frv_expand_mwtacc_builtin (enum insn_code, tree);
319 static rtx frv_expand_noargs_builtin (enum insn_code);
320 static void frv_split_iacc_move (rtx, rtx);
321 static rtx frv_emit_comparison (enum rtx_code, rtx, rtx);
322 static void frv_ifcvt_add_insn (rtx, rtx_insn *, int);
323 static rtx frv_ifcvt_rewrite_mem (rtx, machine_mode, rtx);
324 static rtx frv_ifcvt_load_value (rtx, rtx);
325 static unsigned int frv_insn_unit (rtx_insn *);
326 static bool frv_issues_to_branch_unit_p (rtx_insn *);
327 static int frv_cond_flags (rtx);
328 static bool frv_regstate_conflict_p (regstate_t, regstate_t);
329 static bool frv_registers_conflict_p (rtx);
330 static void frv_registers_update_1 (rtx, const_rtx, void *);
331 static void frv_registers_update (rtx);
332 static void frv_start_packet (void);
333 static void frv_start_packet_block (void);
334 static void frv_finish_packet (void (*) (void));
335 static bool frv_pack_insn_p (rtx_insn *);
336 static void frv_add_insn_to_packet (rtx_insn *);
337 static void frv_insert_nop_in_packet (rtx_insn *);
338 static bool frv_for_each_packet (void (*) (void));
339 static bool frv_sort_insn_group_1 (enum frv_insn_group,
340 unsigned int, unsigned int,
341 unsigned int, unsigned int,
342 state_t);
343 static int frv_compare_insns (const void *, const void *);
344 static void frv_sort_insn_group (enum frv_insn_group);
345 static void frv_reorder_packet (void);
346 static void frv_fill_unused_units (enum frv_insn_group);
347 static void frv_align_label (void);
348 static void frv_reorg_packet (void);
349 static void frv_register_nop (rtx);
350 static void frv_reorg (void);
351 static void frv_pack_insns (void);
352 static void frv_function_prologue (FILE *);
353 static void frv_function_epilogue (FILE *);
354 static bool frv_assemble_integer (rtx, unsigned, int);
355 static void frv_init_builtins (void);
356 static rtx frv_expand_builtin (tree, rtx, rtx, machine_mode, int);
357 static void frv_init_libfuncs (void);
358 static bool frv_in_small_data_p (const_tree);
359 static void frv_asm_output_mi_thunk
360 (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
361 static void frv_setup_incoming_varargs (cumulative_args_t,
362 const function_arg_info &,
363 int *, int);
364 static rtx frv_expand_builtin_saveregs (void);
365 static void frv_expand_builtin_va_start (tree, rtx);
366 static bool frv_rtx_costs (rtx, machine_mode, int, int,
367 int*, bool);
368 static int frv_register_move_cost (machine_mode,
369 reg_class_t, reg_class_t);
370 static int frv_memory_move_cost (machine_mode,
371 reg_class_t, bool);
372 static void frv_asm_out_constructor (rtx, int);
373 static void frv_asm_out_destructor (rtx, int);
374 static bool frv_function_symbol_referenced_p (rtx);
375 static bool frv_legitimate_constant_p (machine_mode, rtx);
376 static bool frv_cannot_force_const_mem (machine_mode, rtx);
377 static const char *unspec_got_name (int);
378 static void frv_output_const_unspec (FILE *,
379 const struct frv_unspec *);
380 static bool frv_function_ok_for_sibcall (tree, tree);
381 static rtx frv_struct_value_rtx (tree, int);
382 static bool frv_must_pass_in_stack (const function_arg_info &);
383 static int frv_arg_partial_bytes (cumulative_args_t,
384 const function_arg_info &);
385 static rtx frv_function_arg (cumulative_args_t, const function_arg_info &);
386 static rtx frv_function_incoming_arg (cumulative_args_t,
387 const function_arg_info &);
388 static void frv_function_arg_advance (cumulative_args_t,
389 const function_arg_info &);
390 static unsigned int frv_function_arg_boundary (machine_mode,
391 const_tree);
392 static void frv_output_dwarf_dtprel (FILE *, int, rtx)
393 ATTRIBUTE_UNUSED;
394 static reg_class_t frv_secondary_reload (bool, rtx, reg_class_t,
395 machine_mode,
396 secondary_reload_info *);
397 static bool frv_frame_pointer_required (void);
398 static bool frv_can_eliminate (const int, const int);
399 static void frv_conditional_register_usage (void);
400 static void frv_trampoline_init (rtx, tree, rtx);
401 static bool frv_class_likely_spilled_p (reg_class_t);
402 static unsigned int frv_hard_regno_nregs (unsigned int, machine_mode);
403 static bool frv_hard_regno_mode_ok (unsigned int, machine_mode);
404 static bool frv_modes_tieable_p (machine_mode, machine_mode);
405
406 /* Initialize the GCC target structure. */
407 #undef TARGET_PRINT_OPERAND
408 #define TARGET_PRINT_OPERAND frv_print_operand
409 #undef TARGET_PRINT_OPERAND_ADDRESS
410 #define TARGET_PRINT_OPERAND_ADDRESS frv_print_operand_address
411 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
412 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P frv_print_operand_punct_valid_p
413 #undef TARGET_ASM_FUNCTION_PROLOGUE
414 #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue
415 #undef TARGET_ASM_FUNCTION_EPILOGUE
416 #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue
417 #undef TARGET_ASM_INTEGER
418 #define TARGET_ASM_INTEGER frv_assemble_integer
419 #undef TARGET_OPTION_OVERRIDE
420 #define TARGET_OPTION_OVERRIDE frv_option_override
421 #undef TARGET_INIT_BUILTINS
422 #define TARGET_INIT_BUILTINS frv_init_builtins
423 #undef TARGET_EXPAND_BUILTIN
424 #define TARGET_EXPAND_BUILTIN frv_expand_builtin
425 #undef TARGET_INIT_LIBFUNCS
426 #define TARGET_INIT_LIBFUNCS frv_init_libfuncs
427 #undef TARGET_IN_SMALL_DATA_P
428 #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p
429 #undef TARGET_REGISTER_MOVE_COST
430 #define TARGET_REGISTER_MOVE_COST frv_register_move_cost
431 #undef TARGET_MEMORY_MOVE_COST
432 #define TARGET_MEMORY_MOVE_COST frv_memory_move_cost
433 #undef TARGET_RTX_COSTS
434 #define TARGET_RTX_COSTS frv_rtx_costs
435 #undef TARGET_ASM_CONSTRUCTOR
436 #define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor
437 #undef TARGET_ASM_DESTRUCTOR
438 #define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor
439
440 #undef TARGET_ASM_OUTPUT_MI_THUNK
441 #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk
442 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
443 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
444
445 #undef TARGET_SCHED_ISSUE_RATE
446 #define TARGET_SCHED_ISSUE_RATE frv_issue_rate
447
448 #undef TARGET_LEGITIMIZE_ADDRESS
449 #define TARGET_LEGITIMIZE_ADDRESS frv_legitimize_address
450
451 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
452 #define TARGET_FUNCTION_OK_FOR_SIBCALL frv_function_ok_for_sibcall
453 #undef TARGET_LEGITIMATE_CONSTANT_P
454 #define TARGET_LEGITIMATE_CONSTANT_P frv_legitimate_constant_p
455 #undef TARGET_CANNOT_FORCE_CONST_MEM
456 #define TARGET_CANNOT_FORCE_CONST_MEM frv_cannot_force_const_mem
457
458 #undef TARGET_HAVE_TLS
459 #define TARGET_HAVE_TLS HAVE_AS_TLS
460
461 #undef TARGET_STRUCT_VALUE_RTX
462 #define TARGET_STRUCT_VALUE_RTX frv_struct_value_rtx
463 #undef TARGET_MUST_PASS_IN_STACK
464 #define TARGET_MUST_PASS_IN_STACK frv_must_pass_in_stack
465 #undef TARGET_PASS_BY_REFERENCE
466 #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack
467 #undef TARGET_ARG_PARTIAL_BYTES
468 #define TARGET_ARG_PARTIAL_BYTES frv_arg_partial_bytes
469 #undef TARGET_FUNCTION_ARG
470 #define TARGET_FUNCTION_ARG frv_function_arg
471 #undef TARGET_FUNCTION_INCOMING_ARG
472 #define TARGET_FUNCTION_INCOMING_ARG frv_function_incoming_arg
473 #undef TARGET_FUNCTION_ARG_ADVANCE
474 #define TARGET_FUNCTION_ARG_ADVANCE frv_function_arg_advance
475 #undef TARGET_FUNCTION_ARG_BOUNDARY
476 #define TARGET_FUNCTION_ARG_BOUNDARY frv_function_arg_boundary
477
478 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
479 #define TARGET_EXPAND_BUILTIN_SAVEREGS frv_expand_builtin_saveregs
480 #undef TARGET_SETUP_INCOMING_VARARGS
481 #define TARGET_SETUP_INCOMING_VARARGS frv_setup_incoming_varargs
482 #undef TARGET_MACHINE_DEPENDENT_REORG
483 #define TARGET_MACHINE_DEPENDENT_REORG frv_reorg
484
485 #undef TARGET_EXPAND_BUILTIN_VA_START
486 #define TARGET_EXPAND_BUILTIN_VA_START frv_expand_builtin_va_start
487
488 #if HAVE_AS_TLS
489 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
490 #define TARGET_ASM_OUTPUT_DWARF_DTPREL frv_output_dwarf_dtprel
491 #endif
492
493 #undef TARGET_CLASS_LIKELY_SPILLED_P
494 #define TARGET_CLASS_LIKELY_SPILLED_P frv_class_likely_spilled_p
495
496 #undef TARGET_SECONDARY_RELOAD
497 #define TARGET_SECONDARY_RELOAD frv_secondary_reload
498
499 #undef TARGET_LRA_P
500 #define TARGET_LRA_P hook_bool_void_false
501
502 #undef TARGET_LEGITIMATE_ADDRESS_P
503 #define TARGET_LEGITIMATE_ADDRESS_P frv_legitimate_address_p
504
505 #undef TARGET_FRAME_POINTER_REQUIRED
506 #define TARGET_FRAME_POINTER_REQUIRED frv_frame_pointer_required
507
508 #undef TARGET_CAN_ELIMINATE
509 #define TARGET_CAN_ELIMINATE frv_can_eliminate
510
511 #undef TARGET_CONDITIONAL_REGISTER_USAGE
512 #define TARGET_CONDITIONAL_REGISTER_USAGE frv_conditional_register_usage
513
514 #undef TARGET_TRAMPOLINE_INIT
515 #define TARGET_TRAMPOLINE_INIT frv_trampoline_init
516
517 #undef TARGET_FUNCTION_VALUE
518 #define TARGET_FUNCTION_VALUE frv_function_value
519 #undef TARGET_LIBCALL_VALUE
520 #define TARGET_LIBCALL_VALUE frv_libcall_value
521
522 #undef TARGET_HARD_REGNO_NREGS
523 #define TARGET_HARD_REGNO_NREGS frv_hard_regno_nregs
524 #undef TARGET_HARD_REGNO_MODE_OK
525 #define TARGET_HARD_REGNO_MODE_OK frv_hard_regno_mode_ok
526 #undef TARGET_MODES_TIEABLE_P
527 #define TARGET_MODES_TIEABLE_P frv_modes_tieable_p
528 #undef TARGET_CONSTANT_ALIGNMENT
529 #define TARGET_CONSTANT_ALIGNMENT constant_alignment_word_strings
530
531 #undef TARGET_HAVE_SPECULATION_SAFE_VALUE
532 #define TARGET_HAVE_SPECULATION_SAFE_VALUE speculation_safe_value_not_needed
533
534 struct gcc_target targetm = TARGET_INITIALIZER;
535
536 #define FRV_SYMBOL_REF_TLS_P(RTX) \
537 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
538
539
540 /* Any function call that satisfies the machine-independent
541 requirements is eligible on FR-V. */
542
543 static bool
frv_function_ok_for_sibcall(tree decl ATTRIBUTE_UNUSED,tree exp ATTRIBUTE_UNUSED)544 frv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
545 tree exp ATTRIBUTE_UNUSED)
546 {
547 return true;
548 }
549
550 /* Return true if SYMBOL is a small data symbol and relocation RELOC
551 can be used to access it directly in a load or store. */
552
553 static FRV_INLINE bool
frv_small_data_reloc_p(rtx symbol,int reloc)554 frv_small_data_reloc_p (rtx symbol, int reloc)
555 {
556 return (GET_CODE (symbol) == SYMBOL_REF
557 && SYMBOL_REF_SMALL_P (symbol)
558 && (!TARGET_FDPIC || flag_pic == 1)
559 && (reloc == R_FRV_GOTOFF12 || reloc == R_FRV_GPREL12));
560 }
561
562 /* Return true if X is a valid relocation unspec. If it is, fill in UNSPEC
563 appropriately. */
564
565 bool
frv_const_unspec_p(rtx x,struct frv_unspec * unspec)566 frv_const_unspec_p (rtx x, struct frv_unspec *unspec)
567 {
568 if (GET_CODE (x) == CONST)
569 {
570 unspec->offset = 0;
571 x = XEXP (x, 0);
572 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
573 {
574 unspec->offset += INTVAL (XEXP (x, 1));
575 x = XEXP (x, 0);
576 }
577 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_GOT)
578 {
579 unspec->symbol = XVECEXP (x, 0, 0);
580 unspec->reloc = INTVAL (XVECEXP (x, 0, 1));
581
582 if (unspec->offset == 0)
583 return true;
584
585 if (frv_small_data_reloc_p (unspec->symbol, unspec->reloc)
586 && unspec->offset > 0
587 && unspec->offset < g_switch_value)
588 return true;
589 }
590 }
591 return false;
592 }
593
594 /* Decide whether we can force certain constants to memory. If we
595 decide we can't, the caller should be able to cope with it in
596 another way.
597
598 We never allow constants to be forced into memory for TARGET_FDPIC.
599 This is necessary for several reasons:
600
601 1. Since frv_legitimate_constant_p rejects constant pool addresses, the
602 target-independent code will try to force them into the constant
603 pool, thus leading to infinite recursion.
604
605 2. We can never introduce new constant pool references during reload.
606 Any such reference would require use of the pseudo FDPIC register.
607
608 3. We can't represent a constant added to a function pointer (which is
609 not the same as a pointer to a function+constant).
610
611 4. In many cases, it's more efficient to calculate the constant in-line. */
612
613 static bool
frv_cannot_force_const_mem(machine_mode mode ATTRIBUTE_UNUSED,rtx x ATTRIBUTE_UNUSED)614 frv_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED,
615 rtx x ATTRIBUTE_UNUSED)
616 {
617 return TARGET_FDPIC;
618 }
619
620 static int
frv_default_flags_for_cpu(void)621 frv_default_flags_for_cpu (void)
622 {
623 switch (frv_cpu_type)
624 {
625 case FRV_CPU_GENERIC:
626 return MASK_DEFAULT_FRV;
627
628 case FRV_CPU_FR550:
629 return MASK_DEFAULT_FR550;
630
631 case FRV_CPU_FR500:
632 case FRV_CPU_TOMCAT:
633 return MASK_DEFAULT_FR500;
634
635 case FRV_CPU_FR450:
636 return MASK_DEFAULT_FR450;
637
638 case FRV_CPU_FR405:
639 case FRV_CPU_FR400:
640 return MASK_DEFAULT_FR400;
641
642 case FRV_CPU_FR300:
643 case FRV_CPU_SIMPLE:
644 return MASK_DEFAULT_SIMPLE;
645
646 default:
647 gcc_unreachable ();
648 }
649 }
650
651 /* Implement TARGET_OPTION_OVERRIDE. */
652
653 static void
frv_option_override(void)654 frv_option_override (void)
655 {
656 int regno;
657 unsigned int i;
658
659 target_flags |= (frv_default_flags_for_cpu () & ~target_flags_explicit);
660
661 /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the
662 linker about linking pic and non-pic code. */
663 if (TARGET_LIBPIC)
664 {
665 if (!flag_pic) /* -fPIC */
666 flag_pic = 2;
667
668 if (!OPTION_SET_P (g_switch_value)) /* -G0 */
669 {
670 g_switch_value = 0;
671 }
672 }
673
674 /* A C expression whose value is a register class containing hard
675 register REGNO. In general there is more than one such class;
676 choose a class which is "minimal", meaning that no smaller class
677 also contains the register. */
678
679 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
680 {
681 enum reg_class rclass;
682
683 if (GPR_P (regno))
684 {
685 int gpr_reg = regno - GPR_FIRST;
686
687 if (gpr_reg == GR8_REG)
688 rclass = GR8_REGS;
689
690 else if (gpr_reg == GR9_REG)
691 rclass = GR9_REGS;
692
693 else if (gpr_reg == GR14_REG)
694 rclass = FDPIC_FPTR_REGS;
695
696 else if (gpr_reg == FDPIC_REGNO)
697 rclass = FDPIC_REGS;
698
699 else if ((gpr_reg & 3) == 0)
700 rclass = QUAD_REGS;
701
702 else if ((gpr_reg & 1) == 0)
703 rclass = EVEN_REGS;
704
705 else
706 rclass = GPR_REGS;
707 }
708
709 else if (FPR_P (regno))
710 {
711 int fpr_reg = regno - GPR_FIRST;
712 if ((fpr_reg & 3) == 0)
713 rclass = QUAD_FPR_REGS;
714
715 else if ((fpr_reg & 1) == 0)
716 rclass = FEVEN_REGS;
717
718 else
719 rclass = FPR_REGS;
720 }
721
722 else if (regno == LR_REGNO)
723 rclass = LR_REG;
724
725 else if (regno == LCR_REGNO)
726 rclass = LCR_REG;
727
728 else if (ICC_P (regno))
729 rclass = ICC_REGS;
730
731 else if (FCC_P (regno))
732 rclass = FCC_REGS;
733
734 else if (ICR_P (regno))
735 rclass = ICR_REGS;
736
737 else if (FCR_P (regno))
738 rclass = FCR_REGS;
739
740 else if (ACC_P (regno))
741 {
742 int r = regno - ACC_FIRST;
743 if ((r & 3) == 0)
744 rclass = QUAD_ACC_REGS;
745 else if ((r & 1) == 0)
746 rclass = EVEN_ACC_REGS;
747 else
748 rclass = ACC_REGS;
749 }
750
751 else if (ACCG_P (regno))
752 rclass = ACCG_REGS;
753
754 else
755 rclass = NO_REGS;
756
757 regno_reg_class[regno] = rclass;
758 }
759
760 /* Check for small data option */
761 if (!OPTION_SET_P (g_switch_value) && !TARGET_LIBPIC)
762 g_switch_value = SDATA_DEFAULT_SIZE;
763
764 /* There is no single unaligned SI op for PIC code. Sometimes we
765 need to use ".4byte" and sometimes we need to use ".picptr".
766 See frv_assemble_integer for details. */
767 if (flag_pic || TARGET_FDPIC)
768 targetm.asm_out.unaligned_op.si = 0;
769
770 if ((target_flags_explicit & MASK_LINKED_FP) == 0)
771 target_flags |= MASK_LINKED_FP;
772
773 if ((target_flags_explicit & MASK_OPTIMIZE_MEMBAR) == 0)
774 target_flags |= MASK_OPTIMIZE_MEMBAR;
775
776 for (i = 0; i < ARRAY_SIZE (frv_unit_names); i++)
777 frv_unit_codes[i] = get_cpu_unit_code (frv_unit_names[i]);
778
779 for (i = 0; i < ARRAY_SIZE (frv_type_to_unit); i++)
780 frv_type_to_unit[i] = ARRAY_SIZE (frv_unit_codes);
781
782 init_machine_status = frv_init_machine_status;
783 }
784
785
786 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
787
788 static void
frv_conditional_register_usage(void)789 frv_conditional_register_usage (void)
790 {
791 int i;
792
793 for (i = GPR_FIRST + NUM_GPRS; i <= GPR_LAST; i++)
794 fixed_regs[i] = call_used_regs[i] = 1;
795
796 for (i = FPR_FIRST + NUM_FPRS; i <= FPR_LAST; i++)
797 fixed_regs[i] = call_used_regs[i] = 1;
798
799 /* Reserve the registers used for conditional execution. At present, we need
800 1 ICC and 1 ICR register. */
801 fixed_regs[ICC_TEMP] = call_used_regs[ICC_TEMP] = 1;
802 fixed_regs[ICR_TEMP] = call_used_regs[ICR_TEMP] = 1;
803
804 if (TARGET_FIXED_CC)
805 {
806 fixed_regs[ICC_FIRST] = call_used_regs[ICC_FIRST] = 1;
807 fixed_regs[FCC_FIRST] = call_used_regs[FCC_FIRST] = 1;
808 fixed_regs[ICR_FIRST] = call_used_regs[ICR_FIRST] = 1;
809 fixed_regs[FCR_FIRST] = call_used_regs[FCR_FIRST] = 1;
810 }
811
812 if (TARGET_FDPIC)
813 fixed_regs[GPR_FIRST + 16] = fixed_regs[GPR_FIRST + 17] =
814 call_used_regs[GPR_FIRST + 16] = call_used_regs[GPR_FIRST + 17] = 0;
815
816 #if 0
817 /* If -fpic, SDA_BASE_REG is the PIC register. */
818 if (g_switch_value == 0 && !flag_pic)
819 fixed_regs[SDA_BASE_REG] = call_used_regs[SDA_BASE_REG] = 0;
820
821 if (!flag_pic)
822 fixed_regs[PIC_REGNO] = call_used_regs[PIC_REGNO] = 0;
823 #endif
824 }
825
826
827 /*
828 * Compute the stack frame layout
829 *
830 * Register setup:
831 * +---------------+-----------------------+-----------------------+
832 * |Register |type |caller-save/callee-save|
833 * +---------------+-----------------------+-----------------------+
834 * |GR0 |Zero register | - |
835 * |GR1 |Stack pointer(SP) | - |
836 * |GR2 |Frame pointer(FP) | - |
837 * |GR3 |Hidden parameter | caller save |
838 * |GR4-GR7 | - | caller save |
839 * |GR8-GR13 |Argument register | caller save |
840 * |GR14-GR15 | - | caller save |
841 * |GR16-GR31 | - | callee save |
842 * |GR32-GR47 | - | caller save |
843 * |GR48-GR63 | - | callee save |
844 * |FR0-FR15 | - | caller save |
845 * |FR16-FR31 | - | callee save |
846 * |FR32-FR47 | - | caller save |
847 * |FR48-FR63 | - | callee save |
848 * +---------------+-----------------------+-----------------------+
849 *
850 * Stack frame setup:
851 * Low
852 * SP-> |-----------------------------------|
853 * | Argument area |
854 * |-----------------------------------|
855 * | Register save area |
856 * |-----------------------------------|
857 * | Local variable save area |
858 * FP-> |-----------------------------------|
859 * | Old FP |
860 * |-----------------------------------|
861 * | Hidden parameter save area |
862 * |-----------------------------------|
863 * | Return address(LR) storage area |
864 * |-----------------------------------|
865 * | Padding for alignment |
866 * |-----------------------------------|
867 * | Register argument area |
868 * OLD SP-> |-----------------------------------|
869 * | Parameter area |
870 * |-----------------------------------|
871 * High
872 *
873 * Argument area/Parameter area:
874 *
875 * When a function is called, this area is used for argument transfer. When
876 * the argument is set up by the caller function, this area is referred to as
877 * the argument area. When the argument is referenced by the callee function,
878 * this area is referred to as the parameter area. The area is allocated when
879 * all arguments cannot be placed on the argument register at the time of
880 * argument transfer.
881 *
882 * Register save area:
883 *
884 * This is a register save area that must be guaranteed for the caller
885 * function. This area is not secured when the register save operation is not
886 * needed.
887 *
888 * Local variable save area:
889 *
890 * This is the area for local variables and temporary variables.
891 *
892 * Old FP:
893 *
894 * This area stores the FP value of the caller function.
895 *
896 * Hidden parameter save area:
897 *
898 * This area stores the start address of the return value storage
899 * area for a struct/union return function.
900 * When a struct/union is used as the return value, the caller
901 * function stores the return value storage area start address in
902 * register GR3 and passes it to the caller function.
903 * The callee function interprets the address stored in the GR3
904 * as the return value storage area start address.
905 * When register GR3 needs to be saved into memory, the callee
906 * function saves it in the hidden parameter save area. This
907 * area is not secured when the save operation is not needed.
908 *
909 * Return address(LR) storage area:
910 *
911 * This area saves the LR. The LR stores the address of a return to the caller
912 * function for the purpose of function calling.
913 *
914 * Argument register area:
915 *
916 * This area saves the argument register. This area is not secured when the
917 * save operation is not needed.
918 *
919 * Argument:
920 *
921 * Arguments, the count of which equals the count of argument registers (6
922 * words), are positioned in registers GR8 to GR13 and delivered to the callee
923 * function. When a struct/union return function is called, the return value
924 * area address is stored in register GR3. Arguments not placed in the
925 * argument registers will be stored in the stack argument area for transfer
926 * purposes. When an 8-byte type argument is to be delivered using registers,
927 * it is divided into two and placed in two registers for transfer. When
928 * argument registers must be saved to memory, the callee function secures an
929 * argument register save area in the stack. In this case, a continuous
930 * argument register save area must be established in the parameter area. The
931 * argument register save area must be allocated as needed to cover the size of
932 * the argument register to be saved. If the function has a variable count of
933 * arguments, it saves all argument registers in the argument register save
934 * area.
935 *
936 * Argument Extension Format:
937 *
938 * When an argument is to be stored in the stack, its type is converted to an
939 * extended type in accordance with the individual argument type. The argument
940 * is freed by the caller function after the return from the callee function is
941 * made.
942 *
943 * +-----------------------+---------------+------------------------+
944 * | Argument Type |Extended Type |Stack Storage Size(byte)|
945 * +-----------------------+---------------+------------------------+
946 * |char |int | 4 |
947 * |signed char |int | 4 |
948 * |unsigned char |int | 4 |
949 * |[signed] short int |int | 4 |
950 * |unsigned short int |int | 4 |
951 * |[signed] int |No extension | 4 |
952 * |unsigned int |No extension | 4 |
953 * |[signed] long int |No extension | 4 |
954 * |unsigned long int |No extension | 4 |
955 * |[signed] long long int |No extension | 8 |
956 * |unsigned long long int |No extension | 8 |
957 * |float |double | 8 |
958 * |double |No extension | 8 |
959 * |long double |No extension | 8 |
960 * |pointer |No extension | 4 |
961 * |struct/union |- | 4 (*1) |
962 * +-----------------------+---------------+------------------------+
963 *
964 * When a struct/union is to be delivered as an argument, the caller copies it
965 * to the local variable area and delivers the address of that area.
966 *
967 * Return Value:
968 *
969 * +-------------------------------+----------------------+
970 * |Return Value Type |Return Value Interface|
971 * +-------------------------------+----------------------+
972 * |void |None |
973 * |[signed|unsigned] char |GR8 |
974 * |[signed|unsigned] short int |GR8 |
975 * |[signed|unsigned] int |GR8 |
976 * |[signed|unsigned] long int |GR8 |
977 * |pointer |GR8 |
978 * |[signed|unsigned] long long int|GR8 & GR9 |
979 * |float |GR8 |
980 * |double |GR8 & GR9 |
981 * |long double |GR8 & GR9 |
982 * |struct/union |(*1) |
983 * +-------------------------------+----------------------+
984 *
985 * When a struct/union is used as the return value, the caller function stores
986 * the start address of the return value storage area into GR3 and then passes
987 * it to the callee function. The callee function interprets GR3 as the start
988 * address of the return value storage area. When this address needs to be
989 * saved in memory, the callee function secures the hidden parameter save area
990 * and saves the address in that area.
991 */
992
993 frv_stack_t *
frv_stack_info(void)994 frv_stack_info (void)
995 {
996 static frv_stack_t info, zero_info;
997 frv_stack_t *info_ptr = &info;
998 tree fndecl = current_function_decl;
999 int varargs_p = 0;
1000 tree cur_arg;
1001 tree next_arg;
1002 int range;
1003 int alignment;
1004 int offset;
1005
1006 /* If we've already calculated the values and reload is complete,
1007 just return now. */
1008 if (frv_stack_cache)
1009 return frv_stack_cache;
1010
1011 /* Zero all fields. */
1012 info = zero_info;
1013
1014 /* Set up the register range information. */
1015 info_ptr->regs[STACK_REGS_GPR].name = "gpr";
1016 info_ptr->regs[STACK_REGS_GPR].first = LAST_ARG_REGNUM + 1;
1017 info_ptr->regs[STACK_REGS_GPR].last = GPR_LAST;
1018 info_ptr->regs[STACK_REGS_GPR].dword_p = TRUE;
1019
1020 info_ptr->regs[STACK_REGS_FPR].name = "fpr";
1021 info_ptr->regs[STACK_REGS_FPR].first = FPR_FIRST;
1022 info_ptr->regs[STACK_REGS_FPR].last = FPR_LAST;
1023 info_ptr->regs[STACK_REGS_FPR].dword_p = TRUE;
1024
1025 info_ptr->regs[STACK_REGS_LR].name = "lr";
1026 info_ptr->regs[STACK_REGS_LR].first = LR_REGNO;
1027 info_ptr->regs[STACK_REGS_LR].last = LR_REGNO;
1028 info_ptr->regs[STACK_REGS_LR].special_p = 1;
1029
1030 info_ptr->regs[STACK_REGS_CC].name = "cc";
1031 info_ptr->regs[STACK_REGS_CC].first = CC_FIRST;
1032 info_ptr->regs[STACK_REGS_CC].last = CC_LAST;
1033 info_ptr->regs[STACK_REGS_CC].field_p = TRUE;
1034
1035 info_ptr->regs[STACK_REGS_LCR].name = "lcr";
1036 info_ptr->regs[STACK_REGS_LCR].first = LCR_REGNO;
1037 info_ptr->regs[STACK_REGS_LCR].last = LCR_REGNO;
1038
1039 info_ptr->regs[STACK_REGS_STDARG].name = "stdarg";
1040 info_ptr->regs[STACK_REGS_STDARG].first = FIRST_ARG_REGNUM;
1041 info_ptr->regs[STACK_REGS_STDARG].last = LAST_ARG_REGNUM;
1042 info_ptr->regs[STACK_REGS_STDARG].dword_p = 1;
1043 info_ptr->regs[STACK_REGS_STDARG].special_p = 1;
1044
1045 info_ptr->regs[STACK_REGS_STRUCT].name = "struct";
1046 info_ptr->regs[STACK_REGS_STRUCT].first = FRV_STRUCT_VALUE_REGNUM;
1047 info_ptr->regs[STACK_REGS_STRUCT].last = FRV_STRUCT_VALUE_REGNUM;
1048 info_ptr->regs[STACK_REGS_STRUCT].special_p = 1;
1049
1050 info_ptr->regs[STACK_REGS_FP].name = "fp";
1051 info_ptr->regs[STACK_REGS_FP].first = FRAME_POINTER_REGNUM;
1052 info_ptr->regs[STACK_REGS_FP].last = FRAME_POINTER_REGNUM;
1053 info_ptr->regs[STACK_REGS_FP].special_p = 1;
1054
1055 /* Determine if this is a stdarg function. If so, allocate space to store
1056 the 6 arguments. */
1057 if (cfun->stdarg)
1058 varargs_p = 1;
1059
1060 else
1061 {
1062 /* Find the last argument, and see if it is __builtin_va_alist. */
1063 for (cur_arg = DECL_ARGUMENTS (fndecl); cur_arg != (tree)0; cur_arg = next_arg)
1064 {
1065 next_arg = DECL_CHAIN (cur_arg);
1066 if (next_arg == (tree)0)
1067 {
1068 if (DECL_NAME (cur_arg)
1069 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)), "__builtin_va_alist"))
1070 varargs_p = 1;
1071
1072 break;
1073 }
1074 }
1075 }
1076
1077 /* Iterate over all of the register ranges. */
1078 for (range = 0; range < STACK_REGS_MAX; range++)
1079 {
1080 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1081 int first = reg_ptr->first;
1082 int last = reg_ptr->last;
1083 int size_1word = 0;
1084 int size_2words = 0;
1085 int regno;
1086
1087 /* Calculate which registers need to be saved & save area size. */
1088 switch (range)
1089 {
1090 default:
1091 for (regno = first; regno <= last; regno++)
1092 {
1093 if ((df_regs_ever_live_p (regno)
1094 && !call_used_or_fixed_reg_p (regno))
1095 || (crtl->calls_eh_return
1096 && (regno >= FIRST_EH_REGNUM && regno <= LAST_EH_REGNUM))
1097 || (!TARGET_FDPIC && flag_pic
1098 && crtl->uses_pic_offset_table && regno == PIC_REGNO))
1099 {
1100 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1101 size_1word += UNITS_PER_WORD;
1102 }
1103 }
1104 break;
1105
1106 /* Calculate whether we need to create a frame after everything else
1107 has been processed. */
1108 case STACK_REGS_FP:
1109 break;
1110
1111 case STACK_REGS_LR:
1112 if (df_regs_ever_live_p (LR_REGNO)
1113 || profile_flag
1114 /* This is set for __builtin_return_address, etc. */
1115 || cfun->machine->frame_needed
1116 || (TARGET_LINKED_FP && frame_pointer_needed)
1117 || (!TARGET_FDPIC && flag_pic
1118 && crtl->uses_pic_offset_table))
1119 {
1120 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1121 size_1word += UNITS_PER_WORD;
1122 }
1123 break;
1124
1125 case STACK_REGS_STDARG:
1126 if (varargs_p)
1127 {
1128 /* If this is a stdarg function with a non varardic
1129 argument split between registers and the stack,
1130 adjust the saved registers downward. */
1131 last -= (ADDR_ALIGN (crtl->args.pretend_args_size, UNITS_PER_WORD)
1132 / UNITS_PER_WORD);
1133
1134 for (regno = first; regno <= last; regno++)
1135 {
1136 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1137 size_1word += UNITS_PER_WORD;
1138 }
1139
1140 info_ptr->stdarg_size = size_1word;
1141 }
1142 break;
1143
1144 case STACK_REGS_STRUCT:
1145 if (cfun->returns_struct)
1146 {
1147 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1148 size_1word += UNITS_PER_WORD;
1149 }
1150 break;
1151 }
1152
1153
1154 if (size_1word)
1155 {
1156 /* If this is a field, it only takes one word. */
1157 if (reg_ptr->field_p)
1158 size_1word = UNITS_PER_WORD;
1159
1160 /* Determine which register pairs can be saved together. */
1161 else if (reg_ptr->dword_p && TARGET_DWORD)
1162 {
1163 for (regno = first; regno < last; regno += 2)
1164 {
1165 if (info_ptr->save_p[regno] && info_ptr->save_p[regno+1])
1166 {
1167 size_2words += 2 * UNITS_PER_WORD;
1168 size_1word -= 2 * UNITS_PER_WORD;
1169 info_ptr->save_p[regno] = REG_SAVE_2WORDS;
1170 info_ptr->save_p[regno+1] = REG_SAVE_NO_SAVE;
1171 }
1172 }
1173 }
1174
1175 reg_ptr->size_1word = size_1word;
1176 reg_ptr->size_2words = size_2words;
1177
1178 if (! reg_ptr->special_p)
1179 {
1180 info_ptr->regs_size_1word += size_1word;
1181 info_ptr->regs_size_2words += size_2words;
1182 }
1183 }
1184 }
1185
1186 /* Set up the sizes of each field in the frame body, making the sizes
1187 of each be divisible by the size of a dword if dword operations might
1188 be used, or the size of a word otherwise. */
1189 alignment = (TARGET_DWORD? 2 * UNITS_PER_WORD : UNITS_PER_WORD);
1190
1191 info_ptr->parameter_size = ADDR_ALIGN (crtl->outgoing_args_size, alignment);
1192 info_ptr->regs_size = ADDR_ALIGN (info_ptr->regs_size_2words
1193 + info_ptr->regs_size_1word,
1194 alignment);
1195 info_ptr->vars_size = ADDR_ALIGN (get_frame_size (), alignment);
1196
1197 info_ptr->pretend_size = crtl->args.pretend_args_size;
1198
1199 /* Work out the size of the frame, excluding the header. Both the frame
1200 body and register parameter area will be dword-aligned. */
1201 info_ptr->total_size
1202 = (ADDR_ALIGN (info_ptr->parameter_size
1203 + info_ptr->regs_size
1204 + info_ptr->vars_size,
1205 2 * UNITS_PER_WORD)
1206 + ADDR_ALIGN (info_ptr->pretend_size
1207 + info_ptr->stdarg_size,
1208 2 * UNITS_PER_WORD));
1209
1210 /* See if we need to create a frame at all, if so add header area. */
1211 if (info_ptr->total_size > 0
1212 || frame_pointer_needed
1213 || info_ptr->regs[STACK_REGS_LR].size_1word > 0
1214 || info_ptr->regs[STACK_REGS_STRUCT].size_1word > 0)
1215 {
1216 offset = info_ptr->parameter_size;
1217 info_ptr->header_size = 4 * UNITS_PER_WORD;
1218 info_ptr->total_size += 4 * UNITS_PER_WORD;
1219
1220 /* Calculate the offsets to save normal register pairs. */
1221 for (range = 0; range < STACK_REGS_MAX; range++)
1222 {
1223 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1224 if (! reg_ptr->special_p)
1225 {
1226 int first = reg_ptr->first;
1227 int last = reg_ptr->last;
1228 int regno;
1229
1230 for (regno = first; regno <= last; regno++)
1231 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS
1232 && regno != FRAME_POINTER_REGNUM
1233 && (regno < FIRST_ARG_REGNUM
1234 || regno > LAST_ARG_REGNUM))
1235 {
1236 info_ptr->reg_offset[regno] = offset;
1237 offset += 2 * UNITS_PER_WORD;
1238 }
1239 }
1240 }
1241
1242 /* Calculate the offsets to save normal single registers. */
1243 for (range = 0; range < STACK_REGS_MAX; range++)
1244 {
1245 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1246 if (! reg_ptr->special_p)
1247 {
1248 int first = reg_ptr->first;
1249 int last = reg_ptr->last;
1250 int regno;
1251
1252 for (regno = first; regno <= last; regno++)
1253 if (info_ptr->save_p[regno] == REG_SAVE_1WORD
1254 && regno != FRAME_POINTER_REGNUM
1255 && (regno < FIRST_ARG_REGNUM
1256 || regno > LAST_ARG_REGNUM))
1257 {
1258 info_ptr->reg_offset[regno] = offset;
1259 offset += UNITS_PER_WORD;
1260 }
1261 }
1262 }
1263
1264 /* Calculate the offset to save the local variables at. */
1265 offset = ADDR_ALIGN (offset, alignment);
1266 if (info_ptr->vars_size)
1267 {
1268 info_ptr->vars_offset = offset;
1269 offset += info_ptr->vars_size;
1270 }
1271
1272 /* Align header to a dword-boundary. */
1273 offset = ADDR_ALIGN (offset, 2 * UNITS_PER_WORD);
1274
1275 /* Calculate the offsets in the fixed frame. */
1276 info_ptr->save_p[FRAME_POINTER_REGNUM] = REG_SAVE_1WORD;
1277 info_ptr->reg_offset[FRAME_POINTER_REGNUM] = offset;
1278 info_ptr->regs[STACK_REGS_FP].size_1word = UNITS_PER_WORD;
1279
1280 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1281 info_ptr->reg_offset[LR_REGNO] = offset + 2*UNITS_PER_WORD;
1282 info_ptr->regs[STACK_REGS_LR].size_1word = UNITS_PER_WORD;
1283
1284 if (cfun->returns_struct)
1285 {
1286 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1287 info_ptr->reg_offset[FRV_STRUCT_VALUE_REGNUM] = offset + UNITS_PER_WORD;
1288 info_ptr->regs[STACK_REGS_STRUCT].size_1word = UNITS_PER_WORD;
1289 }
1290
1291 /* Calculate the offsets to store the arguments passed in registers
1292 for stdarg functions. The register pairs are first and the single
1293 register if any is last. The register save area starts on a
1294 dword-boundary. */
1295 if (info_ptr->stdarg_size)
1296 {
1297 int first = info_ptr->regs[STACK_REGS_STDARG].first;
1298 int last = info_ptr->regs[STACK_REGS_STDARG].last;
1299 int regno;
1300
1301 /* Skip the header. */
1302 offset += 4 * UNITS_PER_WORD;
1303 for (regno = first; regno <= last; regno++)
1304 {
1305 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS)
1306 {
1307 info_ptr->reg_offset[regno] = offset;
1308 offset += 2 * UNITS_PER_WORD;
1309 }
1310 else if (info_ptr->save_p[regno] == REG_SAVE_1WORD)
1311 {
1312 info_ptr->reg_offset[regno] = offset;
1313 offset += UNITS_PER_WORD;
1314 }
1315 }
1316 }
1317 }
1318
1319 if (reload_completed)
1320 frv_stack_cache = info_ptr;
1321
1322 return info_ptr;
1323 }
1324
1325
1326 /* Print the information about the frv stack offsets, etc. when debugging. */
1327
1328 void
frv_debug_stack(frv_stack_t * info)1329 frv_debug_stack (frv_stack_t *info)
1330 {
1331 int range;
1332
1333 if (!info)
1334 info = frv_stack_info ();
1335
1336 fprintf (stderr, "\nStack information for function %s:\n",
1337 ((current_function_decl && DECL_NAME (current_function_decl))
1338 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
1339 : "<unknown>"));
1340
1341 fprintf (stderr, "\ttotal_size\t= %6d\n", info->total_size);
1342 fprintf (stderr, "\tvars_size\t= %6d\n", info->vars_size);
1343 fprintf (stderr, "\tparam_size\t= %6d\n", info->parameter_size);
1344 fprintf (stderr, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n",
1345 info->regs_size, info->regs_size_1word, info->regs_size_2words);
1346
1347 fprintf (stderr, "\theader_size\t= %6d\n", info->header_size);
1348 fprintf (stderr, "\tpretend_size\t= %6d\n", info->pretend_size);
1349 fprintf (stderr, "\tvars_offset\t= %6d\n", info->vars_offset);
1350 fprintf (stderr, "\tregs_offset\t= %6d\n", info->regs_offset);
1351
1352 for (range = 0; range < STACK_REGS_MAX; range++)
1353 {
1354 frv_stack_regs_t *regs = &(info->regs[range]);
1355 if ((regs->size_1word + regs->size_2words) > 0)
1356 {
1357 int first = regs->first;
1358 int last = regs->last;
1359 int regno;
1360
1361 fprintf (stderr, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =",
1362 regs->name, regs->size_1word + regs->size_2words,
1363 regs->size_1word, regs->size_2words);
1364
1365 for (regno = first; regno <= last; regno++)
1366 {
1367 if (info->save_p[regno] == REG_SAVE_1WORD)
1368 fprintf (stderr, " %s (%d)", reg_names[regno],
1369 info->reg_offset[regno]);
1370
1371 else if (info->save_p[regno] == REG_SAVE_2WORDS)
1372 fprintf (stderr, " %s-%s (%d)", reg_names[regno],
1373 reg_names[regno+1], info->reg_offset[regno]);
1374 }
1375
1376 fputc ('\n', stderr);
1377 }
1378 }
1379
1380 fflush (stderr);
1381 }
1382
1383
1384
1385
1386 /* Used during final to control the packing of insns. The value is
1387 1 if the current instruction should be packed with the next one,
1388 0 if it shouldn't or -1 if packing is disabled altogether. */
1389
1390 static int frv_insn_packing_flag;
1391
1392 /* True if the current function contains a far jump. */
1393
1394 static int
frv_function_contains_far_jump(void)1395 frv_function_contains_far_jump (void)
1396 {
1397 rtx_insn *insn = get_insns ();
1398 while (insn != NULL
1399 && !(JUMP_P (insn)
1400 && get_attr_far_jump (insn) == FAR_JUMP_YES))
1401 insn = NEXT_INSN (insn);
1402 return (insn != NULL);
1403 }
1404
1405 /* For the FRV, this function makes sure that a function with far jumps
1406 will return correctly. It also does the VLIW packing. */
1407
1408 static void
frv_function_prologue(FILE * file)1409 frv_function_prologue (FILE *file)
1410 {
1411 /* If no frame was created, check whether the function uses a call
1412 instruction to implement a far jump. If so, save the link in gr3 and
1413 replace all returns to LR with returns to GR3. GR3 is used because it
1414 is call-clobbered, because is not available to the register allocator,
1415 and because all functions that take a hidden argument pointer will have
1416 a stack frame. */
1417 if (frv_stack_info ()->total_size == 0 && frv_function_contains_far_jump ())
1418 {
1419 rtx_insn *insn;
1420
1421 /* Just to check that the above comment is true. */
1422 gcc_assert (!df_regs_ever_live_p (GPR_FIRST + 3));
1423
1424 /* Generate the instruction that saves the link register. */
1425 fprintf (file, "\tmovsg lr,gr3\n");
1426
1427 /* Replace the LR with GR3 in *return_internal patterns. The insn
1428 will now return using jmpl @(gr3,0) rather than bralr. We cannot
1429 simply emit a different assembly directive because bralr and jmpl
1430 execute in different units. */
1431 for (insn = get_insns(); insn != NULL; insn = NEXT_INSN (insn))
1432 if (JUMP_P (insn))
1433 {
1434 rtx pattern = PATTERN (insn);
1435 if (GET_CODE (pattern) == PARALLEL
1436 && XVECLEN (pattern, 0) >= 2
1437 && GET_CODE (XVECEXP (pattern, 0, 0)) == RETURN
1438 && GET_CODE (XVECEXP (pattern, 0, 1)) == USE)
1439 {
1440 rtx address = XEXP (XVECEXP (pattern, 0, 1), 0);
1441 if (GET_CODE (address) == REG && REGNO (address) == LR_REGNO)
1442 SET_REGNO (address, GPR_FIRST + 3);
1443 }
1444 }
1445 }
1446
1447 frv_pack_insns ();
1448
1449 /* Allow the garbage collector to free the nops created by frv_reorg. */
1450 memset (frv_nops, 0, sizeof (frv_nops));
1451 }
1452
1453
1454 /* Return the next available temporary register in a given class. */
1455
1456 static rtx
frv_alloc_temp_reg(frv_tmp_reg_t * info,enum reg_class rclass,machine_mode mode,int mark_as_used,int no_abort)1457 frv_alloc_temp_reg (
1458 frv_tmp_reg_t *info, /* which registers are available */
1459 enum reg_class rclass, /* register class desired */
1460 machine_mode mode, /* mode to allocate register with */
1461 int mark_as_used, /* register not available after allocation */
1462 int no_abort) /* return NULL instead of aborting */
1463 {
1464 int regno = info->next_reg[ (int)rclass ];
1465 int orig_regno = regno;
1466 HARD_REG_SET *reg_in_class = ®_class_contents[ (int)rclass ];
1467 int i, nr;
1468
1469 for (;;)
1470 {
1471 if (TEST_HARD_REG_BIT (*reg_in_class, regno)
1472 && TEST_HARD_REG_BIT (info->regs, regno))
1473 break;
1474
1475 if (++regno >= FIRST_PSEUDO_REGISTER)
1476 regno = 0;
1477 if (regno == orig_regno)
1478 {
1479 gcc_assert (no_abort);
1480 return NULL_RTX;
1481 }
1482 }
1483
1484 nr = hard_regno_nregs (regno, mode);
1485 info->next_reg[ (int)rclass ] = regno + nr;
1486
1487 if (mark_as_used)
1488 for (i = 0; i < nr; i++)
1489 CLEAR_HARD_REG_BIT (info->regs, regno+i);
1490
1491 return gen_rtx_REG (mode, regno);
1492 }
1493
1494
1495 /* Return an rtx with the value OFFSET, which will either be a register or a
1496 signed 12-bit integer. It can be used as the second operand in an "add"
1497 instruction, or as the index in a load or store.
1498
1499 The function returns a constant rtx if OFFSET is small enough, otherwise
1500 it loads the constant into register OFFSET_REGNO and returns that. */
1501 static rtx
frv_frame_offset_rtx(int offset)1502 frv_frame_offset_rtx (int offset)
1503 {
1504 rtx offset_rtx = GEN_INT (offset);
1505 if (IN_RANGE (offset, -2048, 2047))
1506 return offset_rtx;
1507 else
1508 {
1509 rtx reg_rtx = gen_rtx_REG (SImode, OFFSET_REGNO);
1510 if (IN_RANGE (offset, -32768, 32767))
1511 emit_insn (gen_movsi (reg_rtx, offset_rtx));
1512 else
1513 {
1514 emit_insn (gen_movsi_high (reg_rtx, offset_rtx));
1515 emit_insn (gen_movsi_lo_sum (reg_rtx, offset_rtx));
1516 }
1517 return reg_rtx;
1518 }
1519 }
1520
1521 /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The
1522 prologue and epilogue uses such expressions to access the stack. */
1523 static rtx
frv_frame_mem(machine_mode mode,rtx base,int offset)1524 frv_frame_mem (machine_mode mode, rtx base, int offset)
1525 {
1526 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode,
1527 base,
1528 frv_frame_offset_rtx (offset)));
1529 }
1530
1531 /* Generate a frame-related expression:
1532
1533 (set REG (mem (plus (sp) (const_int OFFSET)))).
1534
1535 Such expressions are used in FRAME_RELATED_EXPR notes for more complex
1536 instructions. Marking the expressions as frame-related is superfluous if
1537 the note contains just a single set. But if the note contains a PARALLEL
1538 or SEQUENCE that has several sets, each set must be individually marked
1539 as frame-related. */
1540 static rtx
frv_dwarf_store(rtx reg,int offset)1541 frv_dwarf_store (rtx reg, int offset)
1542 {
1543 rtx set = gen_rtx_SET (gen_rtx_MEM (GET_MODE (reg),
1544 plus_constant (Pmode, stack_pointer_rtx,
1545 offset)),
1546 reg);
1547 RTX_FRAME_RELATED_P (set) = 1;
1548 return set;
1549 }
1550
1551 /* Emit a frame-related instruction whose pattern is PATTERN. The
1552 instruction is the last in a sequence that cumulatively performs the
1553 operation described by DWARF_PATTERN. The instruction is marked as
1554 frame-related and has a REG_FRAME_RELATED_EXPR note containing
1555 DWARF_PATTERN. */
1556 static void
frv_frame_insn(rtx pattern,rtx dwarf_pattern)1557 frv_frame_insn (rtx pattern, rtx dwarf_pattern)
1558 {
1559 rtx insn = emit_insn (pattern);
1560 RTX_FRAME_RELATED_P (insn) = 1;
1561 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
1562 dwarf_pattern,
1563 REG_NOTES (insn));
1564 }
1565
1566 /* Emit instructions that transfer REG to or from the memory location (sp +
1567 STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is
1568 FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this
1569 function to store registers and only the epilogue uses it to load them.
1570
1571 The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET).
1572 The generated instruction will use BASE as its base register. BASE may
1573 simply be the stack pointer, but if several accesses are being made to a
1574 region far away from the stack pointer, it may be more efficient to set
1575 up a temporary instead.
1576
1577 Store instructions will be frame-related and will be annotated with the
1578 overall effect of the store. Load instructions will be followed by a
1579 (use) to prevent later optimizations from zapping them.
1580
1581 The function takes care of the moves to and from SPRs, using TEMP_REGNO
1582 as a temporary in such cases. */
1583 static void
frv_frame_access(frv_frame_accessor_t * accessor,rtx reg,int stack_offset)1584 frv_frame_access (frv_frame_accessor_t *accessor, rtx reg, int stack_offset)
1585 {
1586 machine_mode mode = GET_MODE (reg);
1587 rtx mem = frv_frame_mem (mode,
1588 accessor->base,
1589 stack_offset - accessor->base_offset);
1590
1591 if (accessor->op == FRV_LOAD)
1592 {
1593 if (SPR_P (REGNO (reg)))
1594 {
1595 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1596 emit_insn (gen_rtx_SET (temp, mem));
1597 emit_insn (gen_rtx_SET (reg, temp));
1598 }
1599 else
1600 {
1601 /* We cannot use reg+reg addressing for DImode access. */
1602 if (mode == DImode
1603 && GET_CODE (XEXP (mem, 0)) == PLUS
1604 && GET_CODE (XEXP (XEXP (mem, 0), 0)) == REG
1605 && GET_CODE (XEXP (XEXP (mem, 0), 1)) == REG)
1606 {
1607 rtx temp = gen_rtx_REG (SImode, TEMP_REGNO);
1608
1609 emit_move_insn (temp,
1610 gen_rtx_PLUS (SImode, XEXP (XEXP (mem, 0), 0),
1611 XEXP (XEXP (mem, 0), 1)));
1612 mem = gen_rtx_MEM (DImode, temp);
1613 }
1614 emit_insn (gen_rtx_SET (reg, mem));
1615 }
1616 emit_use (reg);
1617 }
1618 else
1619 {
1620 if (SPR_P (REGNO (reg)))
1621 {
1622 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1623 emit_insn (gen_rtx_SET (temp, reg));
1624 frv_frame_insn (gen_rtx_SET (mem, temp),
1625 frv_dwarf_store (reg, stack_offset));
1626 }
1627 else if (mode == DImode)
1628 {
1629 /* For DImode saves, the dwarf2 version needs to be a SEQUENCE
1630 with a separate save for each register. */
1631 rtx reg1 = gen_rtx_REG (SImode, REGNO (reg));
1632 rtx reg2 = gen_rtx_REG (SImode, REGNO (reg) + 1);
1633 rtx set1 = frv_dwarf_store (reg1, stack_offset);
1634 rtx set2 = frv_dwarf_store (reg2, stack_offset + 4);
1635
1636 /* Also we cannot use reg+reg addressing. */
1637 if (GET_CODE (XEXP (mem, 0)) == PLUS
1638 && GET_CODE (XEXP (XEXP (mem, 0), 0)) == REG
1639 && GET_CODE (XEXP (XEXP (mem, 0), 1)) == REG)
1640 {
1641 rtx temp = gen_rtx_REG (SImode, TEMP_REGNO);
1642 emit_move_insn (temp,
1643 gen_rtx_PLUS (SImode, XEXP (XEXP (mem, 0), 0),
1644 XEXP (XEXP (mem, 0), 1)));
1645 mem = gen_rtx_MEM (DImode, temp);
1646 }
1647
1648 frv_frame_insn (gen_rtx_SET (mem, reg),
1649 gen_rtx_PARALLEL (VOIDmode,
1650 gen_rtvec (2, set1, set2)));
1651 }
1652 else
1653 frv_frame_insn (gen_rtx_SET (mem, reg),
1654 frv_dwarf_store (reg, stack_offset));
1655 }
1656 }
1657
1658 /* A function that uses frv_frame_access to transfer a group of registers to
1659 or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO
1660 is the stack information generated by frv_stack_info, and REG_SET is the
1661 number of the register set to transfer. */
1662 static void
frv_frame_access_multi(frv_frame_accessor_t * accessor,frv_stack_t * info,int reg_set)1663 frv_frame_access_multi (frv_frame_accessor_t *accessor,
1664 frv_stack_t *info,
1665 int reg_set)
1666 {
1667 frv_stack_regs_t *regs_info;
1668 int regno;
1669
1670 regs_info = &info->regs[reg_set];
1671 for (regno = regs_info->first; regno <= regs_info->last; regno++)
1672 if (info->save_p[regno])
1673 frv_frame_access (accessor,
1674 info->save_p[regno] == REG_SAVE_2WORDS
1675 ? gen_rtx_REG (DImode, regno)
1676 : gen_rtx_REG (SImode, regno),
1677 info->reg_offset[regno]);
1678 }
1679
1680 /* Save or restore callee-saved registers that are kept outside the frame
1681 header. The function saves the registers if OP is FRV_STORE and restores
1682 them if OP is FRV_LOAD. INFO is the stack information generated by
1683 frv_stack_info. */
1684 static void
frv_frame_access_standard_regs(enum frv_stack_op op,frv_stack_t * info)1685 frv_frame_access_standard_regs (enum frv_stack_op op, frv_stack_t *info)
1686 {
1687 frv_frame_accessor_t accessor;
1688
1689 accessor.op = op;
1690 accessor.base = stack_pointer_rtx;
1691 accessor.base_offset = 0;
1692 frv_frame_access_multi (&accessor, info, STACK_REGS_GPR);
1693 frv_frame_access_multi (&accessor, info, STACK_REGS_FPR);
1694 frv_frame_access_multi (&accessor, info, STACK_REGS_LCR);
1695 }
1696
1697
1698 /* Called after register allocation to add any instructions needed for the
1699 prologue. Using a prologue insn is favored compared to putting all of the
1700 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1701 it allows the scheduler to intermix instructions with the saves of
1702 the caller saved registers. In some cases, it might be necessary
1703 to emit a barrier instruction as the last insn to prevent such
1704 scheduling.
1705
1706 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
1707 so that the debug info generation code can handle them properly. */
1708 void
frv_expand_prologue(void)1709 frv_expand_prologue (void)
1710 {
1711 frv_stack_t *info = frv_stack_info ();
1712 rtx sp = stack_pointer_rtx;
1713 rtx fp = frame_pointer_rtx;
1714 frv_frame_accessor_t accessor;
1715
1716 if (TARGET_DEBUG_STACK)
1717 frv_debug_stack (info);
1718
1719 if (flag_stack_usage_info)
1720 current_function_static_stack_size = info->total_size;
1721
1722 if (info->total_size == 0)
1723 return;
1724
1725 /* We're interested in three areas of the frame here:
1726
1727 A: the register save area
1728 B: the old FP
1729 C: the header after B
1730
1731 If the frame pointer isn't used, we'll have to set up A, B and C
1732 using the stack pointer. If the frame pointer is used, we'll access
1733 them as follows:
1734
1735 A: set up using sp
1736 B: set up using sp or a temporary (see below)
1737 C: set up using fp
1738
1739 We set up B using the stack pointer if the frame is small enough.
1740 Otherwise, it's more efficient to copy the old stack pointer into a
1741 temporary and use that.
1742
1743 Note that it's important to make sure the prologue and epilogue use the
1744 same registers to access A and C, since doing otherwise will confuse
1745 the aliasing code. */
1746
1747 /* Set up ACCESSOR for accessing region B above. If the frame pointer
1748 isn't used, the same method will serve for C. */
1749 accessor.op = FRV_STORE;
1750 if (frame_pointer_needed && info->total_size > 2048)
1751 {
1752 accessor.base = gen_rtx_REG (Pmode, OLD_SP_REGNO);
1753 accessor.base_offset = info->total_size;
1754 emit_insn (gen_movsi (accessor.base, sp));
1755 }
1756 else
1757 {
1758 accessor.base = stack_pointer_rtx;
1759 accessor.base_offset = 0;
1760 }
1761
1762 /* Allocate the stack space. */
1763 {
1764 rtx asm_offset = frv_frame_offset_rtx (-info->total_size);
1765 rtx dwarf_offset = GEN_INT (-info->total_size);
1766
1767 frv_frame_insn (gen_stack_adjust (sp, sp, asm_offset),
1768 gen_rtx_SET (sp, gen_rtx_PLUS (Pmode, sp, dwarf_offset)));
1769 }
1770
1771 /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET)
1772 and point the new one to that location. */
1773 if (frame_pointer_needed)
1774 {
1775 int fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1776
1777 /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is
1778 based on ACCESSOR.BASE but DWARF_SRC is always based on the stack
1779 pointer. */
1780 rtx asm_src = plus_constant (Pmode, accessor.base,
1781 fp_offset - accessor.base_offset);
1782 rtx dwarf_src = plus_constant (Pmode, sp, fp_offset);
1783
1784 /* Store the old frame pointer at (sp + FP_OFFSET). */
1785 frv_frame_access (&accessor, fp, fp_offset);
1786
1787 /* Set up the new frame pointer. */
1788 frv_frame_insn (gen_rtx_SET (fp, asm_src),
1789 gen_rtx_SET (fp, dwarf_src));
1790
1791 /* Access region C from the frame pointer. */
1792 accessor.base = fp;
1793 accessor.base_offset = fp_offset;
1794 }
1795
1796 /* Set up region C. */
1797 frv_frame_access_multi (&accessor, info, STACK_REGS_STRUCT);
1798 frv_frame_access_multi (&accessor, info, STACK_REGS_LR);
1799 frv_frame_access_multi (&accessor, info, STACK_REGS_STDARG);
1800
1801 /* Set up region A. */
1802 frv_frame_access_standard_regs (FRV_STORE, info);
1803
1804 /* If this is a varargs/stdarg function, issue a blockage to prevent the
1805 scheduler from moving loads before the stores saving the registers. */
1806 if (info->stdarg_size > 0)
1807 emit_insn (gen_blockage ());
1808
1809 /* Set up pic register/small data register for this function. */
1810 if (!TARGET_FDPIC && flag_pic && crtl->uses_pic_offset_table)
1811 emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode, PIC_REGNO),
1812 gen_rtx_REG (Pmode, LR_REGNO),
1813 gen_rtx_REG (SImode, OFFSET_REGNO)));
1814 }
1815
1816
1817 /* Under frv, all of the work is done via frv_expand_epilogue, but
1818 this function provides a convenient place to do cleanup. */
1819
1820 static void
frv_function_epilogue(FILE *)1821 frv_function_epilogue (FILE *)
1822 {
1823 frv_stack_cache = (frv_stack_t *)0;
1824
1825 /* Zap last used registers for conditional execution. */
1826 memset (&frv_ifcvt.tmp_reg, 0, sizeof (frv_ifcvt.tmp_reg));
1827
1828 /* Release the bitmap of created insns. */
1829 BITMAP_FREE (frv_ifcvt.scratch_insns_bitmap);
1830 }
1831
1832
1833 /* Called after register allocation to add any instructions needed for the
1834 epilogue. Using an epilogue insn is favored compared to putting all of the
1835 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1836 it allows the scheduler to intermix instructions with the saves of
1837 the caller saved registers. In some cases, it might be necessary
1838 to emit a barrier instruction as the last insn to prevent such
1839 scheduling. */
1840
1841 void
frv_expand_epilogue(bool emit_return)1842 frv_expand_epilogue (bool emit_return)
1843 {
1844 frv_stack_t *info = frv_stack_info ();
1845 rtx fp = frame_pointer_rtx;
1846 rtx sp = stack_pointer_rtx;
1847 rtx return_addr;
1848 int fp_offset;
1849
1850 fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1851
1852 /* Restore the stack pointer to its original value if alloca or the like
1853 is used. */
1854 if (! crtl->sp_is_unchanging)
1855 emit_insn (gen_addsi3 (sp, fp, frv_frame_offset_rtx (-fp_offset)));
1856
1857 /* Restore the callee-saved registers that were used in this function. */
1858 frv_frame_access_standard_regs (FRV_LOAD, info);
1859
1860 /* Set RETURN_ADDR to the address we should return to. Set it to NULL if
1861 no return instruction should be emitted. */
1862 if (info->save_p[LR_REGNO])
1863 {
1864 int lr_offset;
1865 rtx mem;
1866
1867 /* Use the same method to access the link register's slot as we did in
1868 the prologue. In other words, use the frame pointer if available,
1869 otherwise use the stack pointer.
1870
1871 LR_OFFSET is the offset of the link register's slot from the start
1872 of the frame and MEM is a memory rtx for it. */
1873 lr_offset = info->reg_offset[LR_REGNO];
1874 if (frame_pointer_needed)
1875 mem = frv_frame_mem (Pmode, fp, lr_offset - fp_offset);
1876 else
1877 mem = frv_frame_mem (Pmode, sp, lr_offset);
1878
1879 /* Load the old link register into a GPR. */
1880 return_addr = gen_rtx_REG (Pmode, TEMP_REGNO);
1881 emit_insn (gen_rtx_SET (return_addr, mem));
1882 }
1883 else
1884 return_addr = gen_rtx_REG (Pmode, LR_REGNO);
1885
1886 /* Restore the old frame pointer. Emit a USE afterwards to make sure
1887 the load is preserved. */
1888 if (frame_pointer_needed)
1889 {
1890 emit_insn (gen_rtx_SET (fp, gen_rtx_MEM (Pmode, fp)));
1891 emit_use (fp);
1892 }
1893
1894 /* Deallocate the stack frame. */
1895 if (info->total_size != 0)
1896 {
1897 rtx offset = frv_frame_offset_rtx (info->total_size);
1898 emit_insn (gen_stack_adjust (sp, sp, offset));
1899 }
1900
1901 /* If this function uses eh_return, add the final stack adjustment now. */
1902 if (crtl->calls_eh_return)
1903 emit_insn (gen_stack_adjust (sp, sp, EH_RETURN_STACKADJ_RTX));
1904
1905 if (emit_return)
1906 emit_jump_insn (gen_epilogue_return (return_addr));
1907 else
1908 {
1909 rtx lr = return_addr;
1910
1911 if (REGNO (return_addr) != LR_REGNO)
1912 {
1913 lr = gen_rtx_REG (Pmode, LR_REGNO);
1914 emit_move_insn (lr, return_addr);
1915 }
1916
1917 emit_use (lr);
1918 }
1919 }
1920
1921
1922 /* Worker function for TARGET_ASM_OUTPUT_MI_THUNK. */
1923
1924 static void
frv_asm_output_mi_thunk(FILE * file,tree thunk_fndecl ATTRIBUTE_UNUSED,HOST_WIDE_INT delta,HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,tree function)1925 frv_asm_output_mi_thunk (FILE *file,
1926 tree thunk_fndecl ATTRIBUTE_UNUSED,
1927 HOST_WIDE_INT delta,
1928 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
1929 tree function)
1930 {
1931 const char *fnname = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (thunk_fndecl));
1932 const char *name_func = XSTR (XEXP (DECL_RTL (function), 0), 0);
1933 const char *name_arg0 = reg_names[FIRST_ARG_REGNUM];
1934 const char *name_jmp = reg_names[JUMP_REGNO];
1935 const char *parallel = (frv_issue_rate () > 1 ? ".p" : "");
1936
1937 assemble_start_function (thunk_fndecl, fnname);
1938
1939 /* Do the add using an addi if possible. */
1940 if (IN_RANGE (delta, -2048, 2047))
1941 fprintf (file, "\taddi %s,#%d,%s\n", name_arg0, (int) delta, name_arg0);
1942 else
1943 {
1944 const char *const name_add = reg_names[TEMP_REGNO];
1945 fprintf (file, "\tsethi%s #hi(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
1946 parallel, delta, name_add);
1947 fprintf (file, "\tsetlo #lo(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
1948 delta, name_add);
1949 fprintf (file, "\tadd %s,%s,%s\n", name_add, name_arg0, name_arg0);
1950 }
1951
1952 if (TARGET_FDPIC)
1953 {
1954 const char *name_pic = reg_names[FDPIC_REGNO];
1955 name_jmp = reg_names[FDPIC_FPTR_REGNO];
1956
1957 if (flag_pic != 1)
1958 {
1959 fprintf (file, "\tsethi%s #gotofffuncdeschi(", parallel);
1960 assemble_name (file, name_func);
1961 fprintf (file, "),%s\n", name_jmp);
1962
1963 fprintf (file, "\tsetlo #gotofffuncdesclo(");
1964 assemble_name (file, name_func);
1965 fprintf (file, "),%s\n", name_jmp);
1966
1967 fprintf (file, "\tldd @(%s,%s), %s\n", name_jmp, name_pic, name_jmp);
1968 }
1969 else
1970 {
1971 fprintf (file, "\tlddo @(%s,#gotofffuncdesc12(", name_pic);
1972 assemble_name (file, name_func);
1973 fprintf (file, "\t)), %s\n", name_jmp);
1974 }
1975 }
1976 else if (!flag_pic)
1977 {
1978 fprintf (file, "\tsethi%s #hi(", parallel);
1979 assemble_name (file, name_func);
1980 fprintf (file, "),%s\n", name_jmp);
1981
1982 fprintf (file, "\tsetlo #lo(");
1983 assemble_name (file, name_func);
1984 fprintf (file, "),%s\n", name_jmp);
1985 }
1986 else
1987 {
1988 /* Use JUMP_REGNO as a temporary PIC register. */
1989 const char *name_lr = reg_names[LR_REGNO];
1990 const char *name_gppic = name_jmp;
1991 const char *name_tmp = reg_names[TEMP_REGNO];
1992
1993 fprintf (file, "\tmovsg %s,%s\n", name_lr, name_tmp);
1994 fprintf (file, "\tcall 1f\n");
1995 fprintf (file, "1:\tmovsg %s,%s\n", name_lr, name_gppic);
1996 fprintf (file, "\tmovgs %s,%s\n", name_tmp, name_lr);
1997 fprintf (file, "\tsethi%s #gprelhi(1b),%s\n", parallel, name_tmp);
1998 fprintf (file, "\tsetlo #gprello(1b),%s\n", name_tmp);
1999 fprintf (file, "\tsub %s,%s,%s\n", name_gppic, name_tmp, name_gppic);
2000
2001 fprintf (file, "\tsethi%s #gprelhi(", parallel);
2002 assemble_name (file, name_func);
2003 fprintf (file, "),%s\n", name_tmp);
2004
2005 fprintf (file, "\tsetlo #gprello(");
2006 assemble_name (file, name_func);
2007 fprintf (file, "),%s\n", name_tmp);
2008
2009 fprintf (file, "\tadd %s,%s,%s\n", name_gppic, name_tmp, name_jmp);
2010 }
2011
2012 /* Jump to the function address. */
2013 fprintf (file, "\tjmpl @(%s,%s)\n", name_jmp, reg_names[GPR_FIRST+0]);
2014 assemble_end_function (thunk_fndecl, fnname);
2015 }
2016
2017
2018
2019 /* On frv, create a frame whenever we need to create stack. */
2020
2021 static bool
frv_frame_pointer_required(void)2022 frv_frame_pointer_required (void)
2023 {
2024 /* If we forgoing the usual linkage requirements, we only need
2025 a frame pointer if the stack pointer might change. */
2026 if (!TARGET_LINKED_FP)
2027 return !crtl->sp_is_unchanging;
2028
2029 if (! crtl->is_leaf)
2030 return true;
2031
2032 if (get_frame_size () != 0)
2033 return true;
2034
2035 if (cfun->stdarg)
2036 return true;
2037
2038 if (!crtl->sp_is_unchanging)
2039 return true;
2040
2041 if (!TARGET_FDPIC && flag_pic && crtl->uses_pic_offset_table)
2042 return true;
2043
2044 if (profile_flag)
2045 return true;
2046
2047 if (cfun->machine->frame_needed)
2048 return true;
2049
2050 return false;
2051 }
2052
2053
2054 /* Worker function for TARGET_CAN_ELIMINATE. */
2055
2056 bool
frv_can_eliminate(const int from,const int to)2057 frv_can_eliminate (const int from, const int to)
2058 {
2059 return (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM
2060 ? ! frame_pointer_needed
2061 : true);
2062 }
2063
2064 /* This function returns the initial difference between the specified
2065 pair of registers. */
2066
2067 /* See frv_stack_info for more details on the frv stack frame. */
2068
2069 int
frv_initial_elimination_offset(int from,int to)2070 frv_initial_elimination_offset (int from, int to)
2071 {
2072 frv_stack_t *info = frv_stack_info ();
2073 int ret = 0;
2074
2075 if (to == STACK_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2076 ret = info->total_size - info->pretend_size;
2077
2078 else if (to == STACK_POINTER_REGNUM && from == FRAME_POINTER_REGNUM)
2079 ret = info->reg_offset[FRAME_POINTER_REGNUM];
2080
2081 else if (to == FRAME_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2082 ret = (info->total_size
2083 - info->reg_offset[FRAME_POINTER_REGNUM]
2084 - info->pretend_size);
2085
2086 else
2087 gcc_unreachable ();
2088
2089 if (TARGET_DEBUG_STACK)
2090 fprintf (stderr, "Eliminate %s to %s by adding %d\n",
2091 reg_names [from], reg_names[to], ret);
2092
2093 return ret;
2094 }
2095
2096
2097 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
2098
2099 static void
frv_setup_incoming_varargs(cumulative_args_t cum_v,const function_arg_info & arg,int * pretend_size,int second_time)2100 frv_setup_incoming_varargs (cumulative_args_t cum_v,
2101 const function_arg_info &arg,
2102 int *pretend_size,
2103 int second_time)
2104 {
2105 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
2106
2107 if (TARGET_DEBUG_ARG)
2108 fprintf (stderr,
2109 "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n",
2110 *cum, GET_MODE_NAME (arg.mode), *pretend_size, second_time);
2111 }
2112
2113
2114 /* Worker function for TARGET_EXPAND_BUILTIN_SAVEREGS. */
2115
2116 static rtx
frv_expand_builtin_saveregs(void)2117 frv_expand_builtin_saveregs (void)
2118 {
2119 int offset = UNITS_PER_WORD * FRV_NUM_ARG_REGS;
2120
2121 if (TARGET_DEBUG_ARG)
2122 fprintf (stderr, "expand_builtin_saveregs: offset from ap = %d\n",
2123 offset);
2124
2125 return gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx, GEN_INT (- offset));
2126 }
2127
2128
2129 /* Expand __builtin_va_start to do the va_start macro. */
2130
2131 static void
frv_expand_builtin_va_start(tree valist,rtx nextarg)2132 frv_expand_builtin_va_start (tree valist, rtx nextarg)
2133 {
2134 tree t;
2135 int num = crtl->args.info - FIRST_ARG_REGNUM - FRV_NUM_ARG_REGS;
2136
2137 nextarg = gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx,
2138 GEN_INT (UNITS_PER_WORD * num));
2139
2140 if (TARGET_DEBUG_ARG)
2141 {
2142 fprintf (stderr, "va_start: args_info = %d, num = %d\n",
2143 crtl->args.info, num);
2144
2145 debug_rtx (nextarg);
2146 }
2147
2148 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist,
2149 fold_convert (TREE_TYPE (valist),
2150 make_tree (sizetype, nextarg)));
2151 TREE_SIDE_EFFECTS (t) = 1;
2152
2153 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2154 }
2155
2156
2157 /* Expand a block move operation, and return 1 if successful. Return 0
2158 if we should let the compiler generate normal code.
2159
2160 operands[0] is the destination
2161 operands[1] is the source
2162 operands[2] is the length
2163 operands[3] is the alignment */
2164
2165 /* Maximum number of loads to do before doing the stores */
2166 #ifndef MAX_MOVE_REG
2167 #define MAX_MOVE_REG 4
2168 #endif
2169
2170 /* Maximum number of total loads to do. */
2171 #ifndef TOTAL_MOVE_REG
2172 #define TOTAL_MOVE_REG 8
2173 #endif
2174
2175 int
frv_expand_block_move(rtx operands[])2176 frv_expand_block_move (rtx operands[])
2177 {
2178 rtx orig_dest = operands[0];
2179 rtx orig_src = operands[1];
2180 rtx bytes_rtx = operands[2];
2181 rtx align_rtx = operands[3];
2182 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2183 int align;
2184 int bytes;
2185 int offset;
2186 int num_reg;
2187 int i;
2188 rtx src_reg;
2189 rtx dest_reg;
2190 rtx src_addr;
2191 rtx dest_addr;
2192 rtx src_mem;
2193 rtx dest_mem;
2194 rtx tmp_reg;
2195 rtx stores[MAX_MOVE_REG];
2196 int move_bytes;
2197 machine_mode mode;
2198
2199 /* If this is not a fixed size move, just call memcpy. */
2200 if (! constp)
2201 return FALSE;
2202
2203 /* This should be a fixed size alignment. */
2204 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
2205
2206 align = INTVAL (align_rtx);
2207
2208 /* Anything to move? */
2209 bytes = INTVAL (bytes_rtx);
2210 if (bytes <= 0)
2211 return TRUE;
2212
2213 /* Don't support real large moves. */
2214 if (bytes > TOTAL_MOVE_REG*align)
2215 return FALSE;
2216
2217 /* Move the address into scratch registers. */
2218 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2219 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2220
2221 num_reg = offset = 0;
2222 for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes))
2223 {
2224 /* Calculate the correct offset for src/dest. */
2225 if (offset == 0)
2226 {
2227 src_addr = src_reg;
2228 dest_addr = dest_reg;
2229 }
2230 else
2231 {
2232 src_addr = plus_constant (Pmode, src_reg, offset);
2233 dest_addr = plus_constant (Pmode, dest_reg, offset);
2234 }
2235
2236 /* Generate the appropriate load and store, saving the stores
2237 for later. */
2238 if (bytes >= 4 && align >= 4)
2239 mode = SImode;
2240 else if (bytes >= 2 && align >= 2)
2241 mode = HImode;
2242 else
2243 mode = QImode;
2244
2245 move_bytes = GET_MODE_SIZE (mode);
2246 tmp_reg = gen_reg_rtx (mode);
2247 src_mem = change_address (orig_src, mode, src_addr);
2248 dest_mem = change_address (orig_dest, mode, dest_addr);
2249 emit_insn (gen_rtx_SET (tmp_reg, src_mem));
2250 stores[num_reg++] = gen_rtx_SET (dest_mem, tmp_reg);
2251
2252 if (num_reg >= MAX_MOVE_REG)
2253 {
2254 for (i = 0; i < num_reg; i++)
2255 emit_insn (stores[i]);
2256 num_reg = 0;
2257 }
2258 }
2259
2260 for (i = 0; i < num_reg; i++)
2261 emit_insn (stores[i]);
2262
2263 return TRUE;
2264 }
2265
2266
2267 /* Expand a block clear operation, and return 1 if successful. Return 0
2268 if we should let the compiler generate normal code.
2269
2270 operands[0] is the destination
2271 operands[1] is the length
2272 operands[3] is the alignment */
2273
2274 int
frv_expand_block_clear(rtx operands[])2275 frv_expand_block_clear (rtx operands[])
2276 {
2277 rtx orig_dest = operands[0];
2278 rtx bytes_rtx = operands[1];
2279 rtx align_rtx = operands[3];
2280 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2281 int align;
2282 int bytes;
2283 int offset;
2284 rtx dest_reg;
2285 rtx dest_addr;
2286 rtx dest_mem;
2287 int clear_bytes;
2288 machine_mode mode;
2289
2290 /* If this is not a fixed size move, just call memcpy. */
2291 if (! constp)
2292 return FALSE;
2293
2294 /* This should be a fixed size alignment. */
2295 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
2296
2297 align = INTVAL (align_rtx);
2298
2299 /* Anything to move? */
2300 bytes = INTVAL (bytes_rtx);
2301 if (bytes <= 0)
2302 return TRUE;
2303
2304 /* Don't support real large clears. */
2305 if (bytes > TOTAL_MOVE_REG*align)
2306 return FALSE;
2307
2308 /* Move the address into a scratch register. */
2309 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2310
2311 offset = 0;
2312 for ( ; bytes > 0; (bytes -= clear_bytes), (offset += clear_bytes))
2313 {
2314 /* Calculate the correct offset for src/dest. */
2315 dest_addr = ((offset == 0)
2316 ? dest_reg
2317 : plus_constant (Pmode, dest_reg, offset));
2318
2319 /* Generate the appropriate store of gr0. */
2320 if (bytes >= 4 && align >= 4)
2321 mode = SImode;
2322 else if (bytes >= 2 && align >= 2)
2323 mode = HImode;
2324 else
2325 mode = QImode;
2326
2327 clear_bytes = GET_MODE_SIZE (mode);
2328 dest_mem = change_address (orig_dest, mode, dest_addr);
2329 emit_insn (gen_rtx_SET (dest_mem, const0_rtx));
2330 }
2331
2332 return TRUE;
2333 }
2334
2335
2336 /* The following variable is used to output modifiers of assembler
2337 code of the current output insn. */
2338
2339 static rtx *frv_insn_operands;
2340
2341 /* The following function is used to add assembler insn code suffix .p
2342 if it is necessary. */
2343
2344 const char *
frv_asm_output_opcode(FILE * f,const char * ptr)2345 frv_asm_output_opcode (FILE *f, const char *ptr)
2346 {
2347 int c;
2348
2349 if (frv_insn_packing_flag <= 0)
2350 return ptr;
2351
2352 for (; *ptr && *ptr != ' ' && *ptr != '\t';)
2353 {
2354 c = *ptr++;
2355 if (c == '%' && ((*ptr >= 'a' && *ptr <= 'z')
2356 || (*ptr >= 'A' && *ptr <= 'Z')))
2357 {
2358 int letter = *ptr++;
2359
2360 c = atoi (ptr);
2361 frv_print_operand (f, frv_insn_operands [c], letter);
2362 while ((c = *ptr) >= '0' && c <= '9')
2363 ptr++;
2364 }
2365 else
2366 fputc (c, f);
2367 }
2368
2369 fprintf (f, ".p");
2370
2371 return ptr;
2372 }
2373
2374 /* Set up the packing bit for the current output insn. Note that this
2375 function is not called for asm insns. */
2376
2377 void
frv_final_prescan_insn(rtx_insn * insn,rtx * opvec,int noperands ATTRIBUTE_UNUSED)2378 frv_final_prescan_insn (rtx_insn *insn, rtx *opvec,
2379 int noperands ATTRIBUTE_UNUSED)
2380 {
2381 if (INSN_P (insn))
2382 {
2383 if (frv_insn_packing_flag >= 0)
2384 {
2385 frv_insn_operands = opvec;
2386 frv_insn_packing_flag = PACKING_FLAG_P (insn);
2387 }
2388 else if (recog_memoized (insn) >= 0
2389 && get_attr_acc_group (insn) == ACC_GROUP_ODD)
2390 /* Packing optimizations have been disabled, but INSN can only
2391 be issued in M1. Insert an mnop in M0. */
2392 fprintf (asm_out_file, "\tmnop.p\n");
2393 }
2394 }
2395
2396
2397
2398 /* A C expression whose value is RTL representing the address in a stack frame
2399 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
2400 an RTL expression for the address of the stack frame itself.
2401
2402 If you don't define this macro, the default is to return the value of
2403 FRAMEADDR--that is, the stack frame address is also the address of the stack
2404 word that points to the previous frame. */
2405
2406 /* The default is correct, but we need to make sure the frame gets created. */
2407 rtx
frv_dynamic_chain_address(rtx frame)2408 frv_dynamic_chain_address (rtx frame)
2409 {
2410 cfun->machine->frame_needed = 1;
2411 return frame;
2412 }
2413
2414
2415 /* A C expression whose value is RTL representing the value of the return
2416 address for the frame COUNT steps up from the current frame, after the
2417 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
2418 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
2419 defined.
2420
2421 The value of the expression must always be the correct address when COUNT is
2422 zero, but may be `NULL_RTX' if there is not way to determine the return
2423 address of other frames. */
2424
2425 rtx
frv_return_addr_rtx(int count,rtx frame)2426 frv_return_addr_rtx (int count, rtx frame)
2427 {
2428 if (count != 0)
2429 return const0_rtx;
2430 cfun->machine->frame_needed = 1;
2431 return gen_rtx_MEM (Pmode, plus_constant (Pmode, frame, 8));
2432 }
2433
2434 /* Given a memory reference MEMREF, interpret the referenced memory as
2435 an array of MODE values, and return a reference to the element
2436 specified by INDEX. Assume that any pre-modification implicit in
2437 MEMREF has already happened.
2438
2439 MEMREF must be a legitimate operand for modes larger than SImode.
2440 frv_legitimate_address_p forbids register+register addresses, which
2441 this function cannot handle. */
2442 rtx
frv_index_memory(rtx memref,machine_mode mode,int index)2443 frv_index_memory (rtx memref, machine_mode mode, int index)
2444 {
2445 rtx base = XEXP (memref, 0);
2446 if (GET_CODE (base) == PRE_MODIFY)
2447 base = XEXP (base, 0);
2448 return change_address (memref, mode,
2449 plus_constant (Pmode, base,
2450 index * GET_MODE_SIZE (mode)));
2451 }
2452
2453
2454 /* Print a memory address as an operand to reference that memory location. */
2455 static void
frv_print_operand_address(FILE * stream,machine_mode,rtx x)2456 frv_print_operand_address (FILE * stream, machine_mode /* mode */, rtx x)
2457 {
2458 if (GET_CODE (x) == MEM)
2459 x = XEXP (x, 0);
2460
2461 switch (GET_CODE (x))
2462 {
2463 case REG:
2464 fputs (reg_names [ REGNO (x)], stream);
2465 return;
2466
2467 case CONST_INT:
2468 fprintf (stream, "%ld", (long) INTVAL (x));
2469 return;
2470
2471 case SYMBOL_REF:
2472 assemble_name (stream, XSTR (x, 0));
2473 return;
2474
2475 case LABEL_REF:
2476 case CONST:
2477 output_addr_const (stream, x);
2478 return;
2479
2480 case PLUS:
2481 /* Poorly constructed asm statements can trigger this alternative.
2482 See gcc/testsuite/gcc.dg/asm-4.c for an example. */
2483 frv_print_operand_memory_reference (stream, x, 0);
2484 return;
2485
2486 default:
2487 break;
2488 }
2489
2490 fatal_insn ("bad insn to frv_print_operand_address:", x);
2491 }
2492
2493
2494 static void
frv_print_operand_memory_reference_reg(FILE * stream,rtx x)2495 frv_print_operand_memory_reference_reg (FILE * stream, rtx x)
2496 {
2497 int regno = true_regnum (x);
2498 if (GPR_P (regno))
2499 fputs (reg_names[regno], stream);
2500 else
2501 fatal_insn ("bad register to frv_print_operand_memory_reference_reg:", x);
2502 }
2503
2504 /* Print a memory reference suitable for the ld/st instructions. */
2505
2506 static void
frv_print_operand_memory_reference(FILE * stream,rtx x,int addr_offset)2507 frv_print_operand_memory_reference (FILE * stream, rtx x, int addr_offset)
2508 {
2509 struct frv_unspec unspec;
2510 rtx x0 = NULL_RTX;
2511 rtx x1 = NULL_RTX;
2512
2513 switch (GET_CODE (x))
2514 {
2515 case SUBREG:
2516 case REG:
2517 x0 = x;
2518 break;
2519
2520 case PRE_MODIFY: /* (pre_modify (reg) (plus (reg) (reg))) */
2521 x0 = XEXP (x, 0);
2522 x1 = XEXP (XEXP (x, 1), 1);
2523 break;
2524
2525 case CONST_INT:
2526 x1 = x;
2527 break;
2528
2529 case PLUS:
2530 x0 = XEXP (x, 0);
2531 x1 = XEXP (x, 1);
2532 if (GET_CODE (x0) == CONST_INT)
2533 {
2534 x0 = XEXP (x, 1);
2535 x1 = XEXP (x, 0);
2536 }
2537 break;
2538
2539 default:
2540 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2541 break;
2542
2543 }
2544
2545 if (addr_offset)
2546 {
2547 if (!x1)
2548 x1 = const0_rtx;
2549 else if (GET_CODE (x1) != CONST_INT)
2550 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2551 }
2552
2553 fputs ("@(", stream);
2554 if (!x0)
2555 fputs (reg_names[GPR_R0], stream);
2556 else if (GET_CODE (x0) == REG || GET_CODE (x0) == SUBREG)
2557 frv_print_operand_memory_reference_reg (stream, x0);
2558 else
2559 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2560
2561 fputs (",", stream);
2562 if (!x1)
2563 fputs (reg_names [GPR_R0], stream);
2564
2565 else
2566 {
2567 switch (GET_CODE (x1))
2568 {
2569 case SUBREG:
2570 case REG:
2571 frv_print_operand_memory_reference_reg (stream, x1);
2572 break;
2573
2574 case CONST_INT:
2575 fprintf (stream, "%ld", (long) (INTVAL (x1) + addr_offset));
2576 break;
2577
2578 case CONST:
2579 if (!frv_const_unspec_p (x1, &unspec))
2580 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x1);
2581 frv_output_const_unspec (stream, &unspec);
2582 break;
2583
2584 default:
2585 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2586 }
2587 }
2588
2589 fputs (")", stream);
2590 }
2591
2592
2593 /* Return 2 for likely branches and 0 for non-likely branches */
2594
2595 #define FRV_JUMP_LIKELY 2
2596 #define FRV_JUMP_NOT_LIKELY 0
2597
2598 static int
frv_print_operand_jump_hint(rtx_insn * insn)2599 frv_print_operand_jump_hint (rtx_insn *insn)
2600 {
2601 rtx note;
2602 rtx labelref;
2603 int ret;
2604 enum { UNKNOWN, BACKWARD, FORWARD } jump_type = UNKNOWN;
2605
2606 gcc_assert (JUMP_P (insn));
2607
2608 /* Assume any non-conditional jump is likely. */
2609 if (! any_condjump_p (insn))
2610 ret = FRV_JUMP_LIKELY;
2611
2612 else
2613 {
2614 labelref = condjump_label (insn);
2615 if (labelref)
2616 {
2617 rtx label = XEXP (labelref, 0);
2618 jump_type = (insn_current_address > INSN_ADDRESSES (INSN_UID (label))
2619 ? BACKWARD
2620 : FORWARD);
2621 }
2622
2623 note = find_reg_note (insn, REG_BR_PROB, 0);
2624 if (!note)
2625 ret = ((jump_type == BACKWARD) ? FRV_JUMP_LIKELY : FRV_JUMP_NOT_LIKELY);
2626
2627 else
2628 {
2629 ret = ((profile_probability::from_reg_br_prob_note (XINT (note, 0))
2630 >= profile_probability::even ())
2631 ? FRV_JUMP_LIKELY
2632 : FRV_JUMP_NOT_LIKELY);
2633 }
2634 }
2635
2636 #if 0
2637 if (TARGET_DEBUG)
2638 {
2639 char *direction;
2640
2641 switch (jump_type)
2642 {
2643 default:
2644 case UNKNOWN: direction = "unknown jump direction"; break;
2645 case BACKWARD: direction = "jump backward"; break;
2646 case FORWARD: direction = "jump forward"; break;
2647 }
2648
2649 fprintf (stderr,
2650 "%s: uid %ld, %s, probability = %d, max prob. = %d, hint = %d\n",
2651 IDENTIFIER_POINTER (DECL_NAME (current_function_decl)),
2652 (long)INSN_UID (insn), direction, prob,
2653 REG_BR_PROB_BASE, ret);
2654 }
2655 #endif
2656
2657 return ret;
2658 }
2659
2660
2661 /* Return the comparison operator to use for CODE given that the ICC
2662 register is OP0. */
2663
2664 static const char *
comparison_string(enum rtx_code code,rtx op0)2665 comparison_string (enum rtx_code code, rtx op0)
2666 {
2667 bool is_nz_p = GET_MODE (op0) == CC_NZmode;
2668 switch (code)
2669 {
2670 default: output_operand_lossage ("bad condition code"); return "";
2671 case EQ: return "eq";
2672 case NE: return "ne";
2673 case LT: return is_nz_p ? "n" : "lt";
2674 case LE: return "le";
2675 case GT: return "gt";
2676 case GE: return is_nz_p ? "p" : "ge";
2677 case LTU: return is_nz_p ? "no" : "c";
2678 case LEU: return is_nz_p ? "eq" : "ls";
2679 case GTU: return is_nz_p ? "ne" : "hi";
2680 case GEU: return is_nz_p ? "ra" : "nc";
2681 }
2682 }
2683
2684 /* Print an operand to an assembler instruction.
2685
2686 `%' followed by a letter and a digit says to output an operand in an
2687 alternate fashion. Four letters have standard, built-in meanings
2688 described below. The hook `TARGET_PRINT_OPERAND' can define
2689 additional letters with nonstandard meanings.
2690
2691 `%cDIGIT' can be used to substitute an operand that is a constant value
2692 without the syntax that normally indicates an immediate operand.
2693
2694 `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated
2695 before printing.
2696
2697 `%aDIGIT' can be used to substitute an operand as if it were a memory
2698 reference, with the actual operand treated as the address. This may be
2699 useful when outputting a "load address" instruction, because often the
2700 assembler syntax for such an instruction requires you to write the operand
2701 as if it were a memory reference.
2702
2703 `%lDIGIT' is used to substitute a `label_ref' into a jump instruction.
2704
2705 `%=' outputs a number which is unique to each instruction in the entire
2706 compilation. This is useful for making local labels to be referred to more
2707 than once in a single template that generates multiple assembler
2708 instructions.
2709
2710 `%' followed by a punctuation character specifies a substitution that
2711 does not use an operand. Only one case is standard: `%%' outputs a
2712 `%' into the assembler code. Other nonstandard cases can be defined
2713 in the `TARGET_PRINT_OPERAND' hook. You must also define which
2714 punctuation characters are valid with the
2715 `TARGET_PRINT_OPERAND_PUNCT_VALID_P' hook. */
2716
2717 static void
frv_print_operand(FILE * file,rtx x,int code)2718 frv_print_operand (FILE * file, rtx x, int code)
2719 {
2720 struct frv_unspec unspec;
2721 HOST_WIDE_INT value;
2722 int offset;
2723
2724 if (code != 0 && !ISALPHA (code))
2725 value = 0;
2726
2727 else if (GET_CODE (x) == CONST_INT)
2728 value = INTVAL (x);
2729
2730 else if (GET_CODE (x) == CONST_DOUBLE)
2731 {
2732 if (GET_MODE (x) == SFmode)
2733 {
2734 long l;
2735
2736 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), l);
2737 value = l;
2738 }
2739
2740 else if (GET_MODE (x) == VOIDmode)
2741 value = CONST_DOUBLE_LOW (x);
2742
2743 else
2744 fatal_insn ("bad insn in frv_print_operand, bad const_double", x);
2745 }
2746
2747 else
2748 value = 0;
2749
2750 switch (code)
2751 {
2752
2753 case '.':
2754 /* Output r0. */
2755 fputs (reg_names[GPR_R0], file);
2756 break;
2757
2758 case '#':
2759 fprintf (file, "%d", frv_print_operand_jump_hint (current_output_insn));
2760 break;
2761
2762 case '@':
2763 /* Output small data area base register (gr16). */
2764 fputs (reg_names[SDA_BASE_REG], file);
2765 break;
2766
2767 case '~':
2768 /* Output pic register (gr17). */
2769 fputs (reg_names[PIC_REGNO], file);
2770 break;
2771
2772 case '*':
2773 /* Output the temporary integer CCR register. */
2774 fputs (reg_names[ICR_TEMP], file);
2775 break;
2776
2777 case '&':
2778 /* Output the temporary integer CC register. */
2779 fputs (reg_names[ICC_TEMP], file);
2780 break;
2781
2782 /* case 'a': print an address. */
2783
2784 case 'C':
2785 /* Print appropriate test for integer branch false operation. */
2786 fputs (comparison_string (reverse_condition (GET_CODE (x)),
2787 XEXP (x, 0)), file);
2788 break;
2789
2790 case 'c':
2791 /* Print appropriate test for integer branch true operation. */
2792 fputs (comparison_string (GET_CODE (x), XEXP (x, 0)), file);
2793 break;
2794
2795 case 'e':
2796 /* Print 1 for a NE and 0 for an EQ to give the final argument
2797 for a conditional instruction. */
2798 if (GET_CODE (x) == NE)
2799 fputs ("1", file);
2800
2801 else if (GET_CODE (x) == EQ)
2802 fputs ("0", file);
2803
2804 else
2805 fatal_insn ("bad insn to frv_print_operand, 'e' modifier:", x);
2806 break;
2807
2808 case 'F':
2809 /* Print appropriate test for floating point branch false operation. */
2810 switch (GET_CODE (x))
2811 {
2812 default:
2813 fatal_insn ("bad insn to frv_print_operand, 'F' modifier:", x);
2814
2815 case EQ: fputs ("ne", file); break;
2816 case NE: fputs ("eq", file); break;
2817 case LT: fputs ("uge", file); break;
2818 case LE: fputs ("ug", file); break;
2819 case GT: fputs ("ule", file); break;
2820 case GE: fputs ("ul", file); break;
2821 }
2822 break;
2823
2824 case 'f':
2825 /* Print appropriate test for floating point branch true operation. */
2826 switch (GET_CODE (x))
2827 {
2828 default:
2829 fatal_insn ("bad insn to frv_print_operand, 'f' modifier:", x);
2830
2831 case EQ: fputs ("eq", file); break;
2832 case NE: fputs ("ne", file); break;
2833 case LT: fputs ("lt", file); break;
2834 case LE: fputs ("le", file); break;
2835 case GT: fputs ("gt", file); break;
2836 case GE: fputs ("ge", file); break;
2837 }
2838 break;
2839
2840 case 'g':
2841 /* Print appropriate GOT function. */
2842 if (GET_CODE (x) != CONST_INT)
2843 fatal_insn ("bad insn to frv_print_operand, 'g' modifier:", x);
2844 fputs (unspec_got_name (INTVAL (x)), file);
2845 break;
2846
2847 case 'I':
2848 /* Print 'i' if the operand is a constant, or is a memory reference that
2849 adds a constant. */
2850 if (GET_CODE (x) == MEM)
2851 x = ((GET_CODE (XEXP (x, 0)) == PLUS)
2852 ? XEXP (XEXP (x, 0), 1)
2853 : XEXP (x, 0));
2854 else if (GET_CODE (x) == PLUS)
2855 x = XEXP (x, 1);
2856
2857 switch (GET_CODE (x))
2858 {
2859 default:
2860 break;
2861
2862 case CONST_INT:
2863 case SYMBOL_REF:
2864 case CONST:
2865 fputs ("i", file);
2866 break;
2867 }
2868 break;
2869
2870 case 'i':
2871 /* For jump instructions, print 'i' if the operand is a constant or
2872 is an expression that adds a constant. */
2873 if (GET_CODE (x) == CONST_INT)
2874 fputs ("i", file);
2875
2876 else
2877 {
2878 if (GET_CODE (x) == CONST_INT
2879 || (GET_CODE (x) == PLUS
2880 && (GET_CODE (XEXP (x, 1)) == CONST_INT
2881 || GET_CODE (XEXP (x, 0)) == CONST_INT)))
2882 fputs ("i", file);
2883 }
2884 break;
2885
2886 case 'L':
2887 /* Print the lower register of a double word register pair */
2888 if (GET_CODE (x) == REG)
2889 fputs (reg_names[ REGNO (x)+1 ], file);
2890 else
2891 fatal_insn ("bad insn to frv_print_operand, 'L' modifier:", x);
2892 break;
2893
2894 /* case 'l': print a LABEL_REF. */
2895
2896 case 'M':
2897 case 'N':
2898 /* Print a memory reference for ld/st/jmp, %N prints a memory reference
2899 for the second word of double memory operations. */
2900 offset = (code == 'M') ? 0 : UNITS_PER_WORD;
2901 switch (GET_CODE (x))
2902 {
2903 default:
2904 fatal_insn ("bad insn to frv_print_operand, 'M/N' modifier:", x);
2905
2906 case MEM:
2907 frv_print_operand_memory_reference (file, XEXP (x, 0), offset);
2908 break;
2909
2910 case REG:
2911 case SUBREG:
2912 case CONST_INT:
2913 case PLUS:
2914 case SYMBOL_REF:
2915 frv_print_operand_memory_reference (file, x, offset);
2916 break;
2917 }
2918 break;
2919
2920 case 'O':
2921 /* Print the opcode of a command. */
2922 switch (GET_CODE (x))
2923 {
2924 default:
2925 fatal_insn ("bad insn to frv_print_operand, 'O' modifier:", x);
2926
2927 case PLUS: fputs ("add", file); break;
2928 case MINUS: fputs ("sub", file); break;
2929 case AND: fputs ("and", file); break;
2930 case IOR: fputs ("or", file); break;
2931 case XOR: fputs ("xor", file); break;
2932 case ASHIFT: fputs ("sll", file); break;
2933 case ASHIFTRT: fputs ("sra", file); break;
2934 case LSHIFTRT: fputs ("srl", file); break;
2935 }
2936 break;
2937
2938 /* case 'n': negate and print a constant int. */
2939
2940 case 'P':
2941 /* Print PIC label using operand as the number. */
2942 if (GET_CODE (x) != CONST_INT)
2943 fatal_insn ("bad insn to frv_print_operand, P modifier:", x);
2944
2945 fprintf (file, ".LCF%ld", (long)INTVAL (x));
2946 break;
2947
2948 case 'U':
2949 /* Print 'u' if the operand is a update load/store. */
2950 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
2951 fputs ("u", file);
2952 break;
2953
2954 case 'z':
2955 /* If value is 0, print gr0, otherwise it must be a register. */
2956 if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0)
2957 fputs (reg_names[GPR_R0], file);
2958
2959 else if (GET_CODE (x) == REG)
2960 fputs (reg_names [REGNO (x)], file);
2961
2962 else
2963 fatal_insn ("bad insn in frv_print_operand, z case", x);
2964 break;
2965
2966 case 'x':
2967 /* Print constant in hex. */
2968 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
2969 {
2970 fprintf (file, "%s0x%.4lx", IMMEDIATE_PREFIX, (long) value);
2971 break;
2972 }
2973
2974 /* Fall through. */
2975
2976 case '\0':
2977 if (GET_CODE (x) == REG)
2978 fputs (reg_names [REGNO (x)], file);
2979
2980 else if (GET_CODE (x) == CONST_INT
2981 || GET_CODE (x) == CONST_DOUBLE)
2982 fprintf (file, "%s%ld", IMMEDIATE_PREFIX, (long) value);
2983
2984 else if (frv_const_unspec_p (x, &unspec))
2985 frv_output_const_unspec (file, &unspec);
2986
2987 else if (GET_CODE (x) == MEM)
2988 frv_print_operand_address (file, GET_MODE (x), XEXP (x, 0));
2989
2990 else if (CONSTANT_ADDRESS_P (x))
2991 frv_print_operand_address (file, VOIDmode, x);
2992
2993 else
2994 fatal_insn ("bad insn in frv_print_operand, 0 case", x);
2995
2996 break;
2997
2998 default:
2999 fatal_insn ("frv_print_operand: unknown code", x);
3000 break;
3001 }
3002
3003 return;
3004 }
3005
3006 static bool
frv_print_operand_punct_valid_p(unsigned char code)3007 frv_print_operand_punct_valid_p (unsigned char code)
3008 {
3009 return (code == '.' || code == '#' || code == '@' || code == '~'
3010 || code == '*' || code == '&');
3011 }
3012
3013
3014 /* A C statement (sans semicolon) for initializing the variable CUM for the
3015 state at the beginning of the argument list. The variable has type
3016 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
3017 of the function which will receive the args, or 0 if the args are to a
3018 compiler support library function. The value of INDIRECT is nonzero when
3019 processing an indirect call, for example a call through a function pointer.
3020 The value of INDIRECT is zero for a call to an explicitly named function, a
3021 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
3022 arguments for the function being compiled.
3023
3024 When processing a call to a compiler support library function, LIBNAME
3025 identifies which one. It is a `symbol_ref' rtx which contains the name of
3026 the function, as a string. LIBNAME is 0 when an ordinary C function call is
3027 being processed. Thus, each time this macro is called, either LIBNAME or
3028 FNTYPE is nonzero, but never both of them at once. */
3029
3030 void
frv_init_cumulative_args(CUMULATIVE_ARGS * cum,tree fntype,rtx libname,tree fndecl,int incoming)3031 frv_init_cumulative_args (CUMULATIVE_ARGS *cum,
3032 tree fntype,
3033 rtx libname,
3034 tree fndecl,
3035 int incoming)
3036 {
3037 *cum = FIRST_ARG_REGNUM;
3038
3039 if (TARGET_DEBUG_ARG)
3040 {
3041 fprintf (stderr, "\ninit_cumulative_args:");
3042 if (!fndecl && fntype)
3043 fputs (" indirect", stderr);
3044
3045 if (incoming)
3046 fputs (" incoming", stderr);
3047
3048 if (fntype)
3049 {
3050 tree ret_type = TREE_TYPE (fntype);
3051 fprintf (stderr, " return=%s,",
3052 get_tree_code_name (TREE_CODE (ret_type)));
3053 }
3054
3055 if (libname && GET_CODE (libname) == SYMBOL_REF)
3056 fprintf (stderr, " libname=%s", XSTR (libname, 0));
3057
3058 if (cfun->returns_struct)
3059 fprintf (stderr, " return-struct");
3060
3061 putc ('\n', stderr);
3062 }
3063 }
3064
3065
3066 /* Return true if we should pass an argument on the stack rather than
3067 in registers. */
3068
3069 static bool
frv_must_pass_in_stack(const function_arg_info & arg)3070 frv_must_pass_in_stack (const function_arg_info &arg)
3071 {
3072 return arg.mode == BLKmode || arg.aggregate_type_p ();
3073 }
3074
3075 /* If defined, a C expression that gives the alignment boundary, in bits, of an
3076 argument with the specified mode and type. If it is not defined,
3077 `PARM_BOUNDARY' is used for all arguments. */
3078
3079 static unsigned int
frv_function_arg_boundary(machine_mode mode ATTRIBUTE_UNUSED,const_tree type ATTRIBUTE_UNUSED)3080 frv_function_arg_boundary (machine_mode mode ATTRIBUTE_UNUSED,
3081 const_tree type ATTRIBUTE_UNUSED)
3082 {
3083 return BITS_PER_WORD;
3084 }
3085
3086 static rtx
frv_function_arg_1(cumulative_args_t cum_v,const function_arg_info & arg,bool incoming ATTRIBUTE_UNUSED)3087 frv_function_arg_1 (cumulative_args_t cum_v, const function_arg_info &arg,
3088 bool incoming ATTRIBUTE_UNUSED)
3089 {
3090 const CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
3091
3092 machine_mode xmode = (arg.mode == BLKmode) ? SImode : arg.mode;
3093 int arg_num = *cum;
3094 rtx ret;
3095 const char *debstr;
3096
3097 /* Return a marker for use in the call instruction. */
3098 if (xmode == VOIDmode)
3099 {
3100 ret = const0_rtx;
3101 debstr = "<0>";
3102 }
3103
3104 else if (arg_num <= LAST_ARG_REGNUM)
3105 {
3106 ret = gen_rtx_REG (xmode, arg_num);
3107 debstr = reg_names[arg_num];
3108 }
3109
3110 else
3111 {
3112 ret = NULL_RTX;
3113 debstr = "memory";
3114 }
3115
3116 if (TARGET_DEBUG_ARG)
3117 fprintf (stderr,
3118 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n",
3119 arg_num, GET_MODE_NAME (arg.mode), arg.named,
3120 GET_MODE_SIZE (arg.mode), debstr);
3121
3122 return ret;
3123 }
3124
3125 static rtx
frv_function_arg(cumulative_args_t cum,const function_arg_info & arg)3126 frv_function_arg (cumulative_args_t cum, const function_arg_info &arg)
3127 {
3128 return frv_function_arg_1 (cum, arg, false);
3129 }
3130
3131 static rtx
frv_function_incoming_arg(cumulative_args_t cum,const function_arg_info & arg)3132 frv_function_incoming_arg (cumulative_args_t cum, const function_arg_info &arg)
3133 {
3134 return frv_function_arg_1 (cum, arg, true);
3135 }
3136
3137
3138 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
3139
3140 static void
frv_function_arg_advance(cumulative_args_t cum_v,const function_arg_info & arg)3141 frv_function_arg_advance (cumulative_args_t cum_v,
3142 const function_arg_info &arg)
3143 {
3144 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
3145
3146 machine_mode xmode = (arg.mode == BLKmode) ? SImode : arg.mode;
3147 int bytes = GET_MODE_SIZE (xmode);
3148 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3149 int arg_num = *cum;
3150
3151 *cum = arg_num + words;
3152
3153 if (TARGET_DEBUG_ARG)
3154 fprintf (stderr,
3155 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n",
3156 arg_num, GET_MODE_NAME (arg.mode), arg.named,
3157 words * UNITS_PER_WORD);
3158 }
3159
3160
3161 /* Implement TARGET_ARG_PARTIAL_BYTES. */
3162
3163 static int
frv_arg_partial_bytes(cumulative_args_t cum,const function_arg_info & arg)3164 frv_arg_partial_bytes (cumulative_args_t cum, const function_arg_info &arg)
3165 {
3166 machine_mode xmode = (arg.mode == BLKmode) ? SImode : arg.mode;
3167 int bytes = GET_MODE_SIZE (xmode);
3168 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3169 int arg_num = *get_cumulative_args (cum);
3170 int ret;
3171
3172 ret = ((arg_num <= LAST_ARG_REGNUM && arg_num + words > LAST_ARG_REGNUM+1)
3173 ? LAST_ARG_REGNUM - arg_num + 1
3174 : 0);
3175 ret *= UNITS_PER_WORD;
3176
3177 if (TARGET_DEBUG_ARG && ret)
3178 fprintf (stderr, "frv_arg_partial_bytes: %d\n", ret);
3179
3180 return ret;
3181 }
3182
3183
3184 /* Implements TARGET_FUNCTION_VALUE. */
3185
3186 static rtx
frv_function_value(const_tree valtype,const_tree fn_decl_or_type ATTRIBUTE_UNUSED,bool outgoing ATTRIBUTE_UNUSED)3187 frv_function_value (const_tree valtype,
3188 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
3189 bool outgoing ATTRIBUTE_UNUSED)
3190 {
3191 return gen_rtx_REG (TYPE_MODE (valtype), RETURN_VALUE_REGNUM);
3192 }
3193
3194
3195 /* Implements TARGET_LIBCALL_VALUE. */
3196
3197 static rtx
frv_libcall_value(machine_mode mode,const_rtx fun ATTRIBUTE_UNUSED)3198 frv_libcall_value (machine_mode mode,
3199 const_rtx fun ATTRIBUTE_UNUSED)
3200 {
3201 return gen_rtx_REG (mode, RETURN_VALUE_REGNUM);
3202 }
3203
3204
3205 /* Implements FUNCTION_VALUE_REGNO_P. */
3206
3207 bool
frv_function_value_regno_p(const unsigned int regno)3208 frv_function_value_regno_p (const unsigned int regno)
3209 {
3210 return (regno == RETURN_VALUE_REGNUM);
3211 }
3212
3213 /* Return true if a register is ok to use as a base or index register. */
3214
3215 static FRV_INLINE int
frv_regno_ok_for_base_p(int regno,int strict_p)3216 frv_regno_ok_for_base_p (int regno, int strict_p)
3217 {
3218 if (GPR_P (regno))
3219 return TRUE;
3220
3221 if (strict_p)
3222 return (reg_renumber[regno] >= 0 && GPR_P (reg_renumber[regno]));
3223
3224 if (regno == ARG_POINTER_REGNUM)
3225 return TRUE;
3226
3227 return (regno >= FIRST_PSEUDO_REGISTER);
3228 }
3229
3230
3231 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3232 RTX) is a legitimate memory address on the target machine for a memory
3233 operand of mode MODE.
3234
3235 It usually pays to define several simpler macros to serve as subroutines for
3236 this one. Otherwise it may be too complicated to understand.
3237
3238 This macro must exist in two variants: a strict variant and a non-strict
3239 one. The strict variant is used in the reload pass. It must be defined so
3240 that any pseudo-register that has not been allocated a hard register is
3241 considered a memory reference. In contexts where some kind of register is
3242 required, a pseudo-register with no hard register must be rejected.
3243
3244 The non-strict variant is used in other passes. It must be defined to
3245 accept all pseudo-registers in every context where some kind of register is
3246 required.
3247
3248 Compiler source files that want to use the strict variant of this macro
3249 define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT'
3250 conditional to define the strict variant in that case and the non-strict
3251 variant otherwise.
3252
3253 Normally, constant addresses which are the sum of a `symbol_ref' and an
3254 integer are stored inside a `const' RTX to mark them as constant.
3255 Therefore, there is no need to recognize such sums specifically as
3256 legitimate addresses. Normally you would simply recognize any `const' as
3257 legitimate.
3258
3259 Usually `TARGET_PRINT_OPERAND_ADDRESS' is not prepared to handle
3260 constant sums that are not marked with `const'. It assumes that a
3261 naked `plus' indicates indexing. If so, then you *must* reject such
3262 naked constant sums as illegitimate addresses, so that none of them
3263 will be given to `TARGET_PRINT_OPERAND_ADDRESS'. */
3264
3265 int
frv_legitimate_address_p_1(machine_mode mode,rtx x,int strict_p,int condexec_p,int allow_double_reg_p)3266 frv_legitimate_address_p_1 (machine_mode mode,
3267 rtx x,
3268 int strict_p,
3269 int condexec_p,
3270 int allow_double_reg_p)
3271 {
3272 rtx x0, x1;
3273 int ret = 0;
3274 HOST_WIDE_INT value;
3275 unsigned regno0;
3276
3277 if (FRV_SYMBOL_REF_TLS_P (x))
3278 return 0;
3279
3280 switch (GET_CODE (x))
3281 {
3282 default:
3283 break;
3284
3285 case SUBREG:
3286 x = SUBREG_REG (x);
3287 if (GET_CODE (x) != REG)
3288 break;
3289
3290 /* Fall through. */
3291
3292 case REG:
3293 ret = frv_regno_ok_for_base_p (REGNO (x), strict_p);
3294 break;
3295
3296 case PRE_MODIFY:
3297 x0 = XEXP (x, 0);
3298 x1 = XEXP (x, 1);
3299 if (GET_CODE (x0) != REG
3300 || ! frv_regno_ok_for_base_p (REGNO (x0), strict_p)
3301 || GET_CODE (x1) != PLUS
3302 || ! rtx_equal_p (x0, XEXP (x1, 0))
3303 || GET_CODE (XEXP (x1, 1)) != REG
3304 || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1, 1)), strict_p))
3305 break;
3306
3307 ret = 1;
3308 break;
3309
3310 case CONST_INT:
3311 /* 12-bit immediate */
3312 if (condexec_p)
3313 ret = FALSE;
3314 else
3315 {
3316 ret = IN_RANGE (INTVAL (x), -2048, 2047);
3317
3318 /* If we can't use load/store double operations, make sure we can
3319 address the second word. */
3320 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3321 ret = IN_RANGE (INTVAL (x) + GET_MODE_SIZE (mode) - 1,
3322 -2048, 2047);
3323 }
3324 break;
3325
3326 case PLUS:
3327 x0 = XEXP (x, 0);
3328 x1 = XEXP (x, 1);
3329
3330 if (GET_CODE (x0) == SUBREG)
3331 x0 = SUBREG_REG (x0);
3332
3333 if (GET_CODE (x0) != REG)
3334 break;
3335
3336 regno0 = REGNO (x0);
3337 if (!frv_regno_ok_for_base_p (regno0, strict_p))
3338 break;
3339
3340 switch (GET_CODE (x1))
3341 {
3342 default:
3343 break;
3344
3345 case SUBREG:
3346 x1 = SUBREG_REG (x1);
3347 if (GET_CODE (x1) != REG)
3348 break;
3349
3350 /* Fall through. */
3351
3352 case REG:
3353 /* Do not allow reg+reg addressing for modes > 1 word if we
3354 can't depend on having move double instructions. */
3355 if (!allow_double_reg_p && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3356 ret = FALSE;
3357 else
3358 ret = frv_regno_ok_for_base_p (REGNO (x1), strict_p);
3359 break;
3360
3361 case CONST_INT:
3362 /* 12-bit immediate */
3363 if (condexec_p)
3364 ret = FALSE;
3365 else
3366 {
3367 value = INTVAL (x1);
3368 ret = IN_RANGE (value, -2048, 2047);
3369
3370 /* If we can't use load/store double operations, make sure we can
3371 address the second word. */
3372 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3373 ret = IN_RANGE (value + GET_MODE_SIZE (mode) - 1, -2048, 2047);
3374 }
3375 break;
3376
3377 case CONST:
3378 if (!condexec_p && got12_operand (x1, VOIDmode))
3379 ret = TRUE;
3380 break;
3381
3382 }
3383 break;
3384 }
3385
3386 if (TARGET_DEBUG_ADDR)
3387 {
3388 fprintf (stderr, "\n========== legitimate_address_p, mode = %s, result = %d, addresses are %sstrict%s\n",
3389 GET_MODE_NAME (mode), ret, (strict_p) ? "" : "not ",
3390 (condexec_p) ? ", inside conditional code" : "");
3391 debug_rtx (x);
3392 }
3393
3394 return ret;
3395 }
3396
3397 bool
frv_legitimate_address_p(machine_mode mode,rtx x,bool strict_p)3398 frv_legitimate_address_p (machine_mode mode, rtx x, bool strict_p)
3399 {
3400 return frv_legitimate_address_p_1 (mode, x, strict_p, FALSE, FALSE);
3401 }
3402
3403 /* Given an ADDR, generate code to inline the PLT. */
3404 static rtx
gen_inlined_tls_plt(rtx addr)3405 gen_inlined_tls_plt (rtx addr)
3406 {
3407 rtx retval, dest;
3408 rtx picreg = get_hard_reg_initial_val (Pmode, FDPIC_REG);
3409
3410
3411 dest = gen_reg_rtx (DImode);
3412
3413 if (flag_pic == 1)
3414 {
3415 /*
3416 -fpic version:
3417
3418 lddi.p @(gr15, #gottlsdesc12(ADDR)), gr8
3419 calll #gettlsoff(ADDR)@(gr8, gr0)
3420 */
3421 emit_insn (gen_tls_lddi (dest, addr, picreg));
3422 }
3423 else
3424 {
3425 /*
3426 -fPIC version:
3427
3428 sethi.p #gottlsdeschi(ADDR), gr8
3429 setlo #gottlsdesclo(ADDR), gr8
3430 ldd #tlsdesc(ADDR)@(gr15, gr8), gr8
3431 calll #gettlsoff(ADDR)@(gr8, gr0)
3432 */
3433 rtx reguse = gen_reg_rtx (Pmode);
3434 emit_insn (gen_tlsoff_hilo (reguse, addr, GEN_INT (R_FRV_GOTTLSDESCHI)));
3435 emit_insn (gen_tls_tlsdesc_ldd (dest, picreg, reguse, addr));
3436 }
3437
3438 retval = gen_reg_rtx (Pmode);
3439 emit_insn (gen_tls_indirect_call (retval, addr, dest, picreg));
3440 return retval;
3441 }
3442
3443 /* Emit a TLSMOFF or TLSMOFF12 offset, depending on -mTLS. Returns
3444 the destination address. */
3445 static rtx
gen_tlsmoff(rtx addr,rtx reg)3446 gen_tlsmoff (rtx addr, rtx reg)
3447 {
3448 rtx dest = gen_reg_rtx (Pmode);
3449
3450 if (TARGET_BIG_TLS)
3451 {
3452 /* sethi.p #tlsmoffhi(x), grA
3453 setlo #tlsmofflo(x), grA
3454 */
3455 dest = gen_reg_rtx (Pmode);
3456 emit_insn (gen_tlsoff_hilo (dest, addr,
3457 GEN_INT (R_FRV_TLSMOFFHI)));
3458 dest = gen_rtx_PLUS (Pmode, dest, reg);
3459 }
3460 else
3461 {
3462 /* addi grB, #tlsmoff12(x), grC
3463 -or-
3464 ld/st @(grB, #tlsmoff12(x)), grC
3465 */
3466 dest = gen_reg_rtx (Pmode);
3467 emit_insn (gen_symGOTOFF2reg_i (dest, addr, reg,
3468 GEN_INT (R_FRV_TLSMOFF12)));
3469 }
3470 return dest;
3471 }
3472
3473 /* Generate code for a TLS address. */
3474 static rtx
frv_legitimize_tls_address(rtx addr,enum tls_model model)3475 frv_legitimize_tls_address (rtx addr, enum tls_model model)
3476 {
3477 rtx dest, tp = gen_rtx_REG (Pmode, 29);
3478 rtx picreg = get_hard_reg_initial_val (Pmode, 15);
3479
3480 switch (model)
3481 {
3482 case TLS_MODEL_INITIAL_EXEC:
3483 if (flag_pic == 1)
3484 {
3485 /* -fpic version.
3486 ldi @(gr15, #gottlsoff12(x)), gr5
3487 */
3488 dest = gen_reg_rtx (Pmode);
3489 emit_insn (gen_tls_load_gottlsoff12 (dest, addr, picreg));
3490 dest = gen_rtx_PLUS (Pmode, tp, dest);
3491 }
3492 else
3493 {
3494 /* -fPIC or anything else.
3495
3496 sethi.p #gottlsoffhi(x), gr14
3497 setlo #gottlsofflo(x), gr14
3498 ld #tlsoff(x)@(gr15, gr14), gr9
3499 */
3500 rtx tmp = gen_reg_rtx (Pmode);
3501 dest = gen_reg_rtx (Pmode);
3502 emit_insn (gen_tlsoff_hilo (tmp, addr,
3503 GEN_INT (R_FRV_GOTTLSOFF_HI)));
3504
3505 emit_insn (gen_tls_tlsoff_ld (dest, picreg, tmp, addr));
3506 dest = gen_rtx_PLUS (Pmode, tp, dest);
3507 }
3508 break;
3509 case TLS_MODEL_LOCAL_DYNAMIC:
3510 {
3511 rtx reg, retval;
3512
3513 if (TARGET_INLINE_PLT)
3514 retval = gen_inlined_tls_plt (GEN_INT (0));
3515 else
3516 {
3517 /* call #gettlsoff(0) */
3518 retval = gen_reg_rtx (Pmode);
3519 emit_insn (gen_call_gettlsoff (retval, GEN_INT (0), picreg));
3520 }
3521
3522 reg = gen_reg_rtx (Pmode);
3523 emit_insn (gen_rtx_SET (reg, gen_rtx_PLUS (Pmode, retval, tp)));
3524
3525 dest = gen_tlsmoff (addr, reg);
3526
3527 /*
3528 dest = gen_reg_rtx (Pmode);
3529 emit_insn (gen_tlsoff_hilo (dest, addr,
3530 GEN_INT (R_FRV_TLSMOFFHI)));
3531 dest = gen_rtx_PLUS (Pmode, dest, reg);
3532 */
3533 break;
3534 }
3535 case TLS_MODEL_LOCAL_EXEC:
3536 dest = gen_tlsmoff (addr, gen_rtx_REG (Pmode, 29));
3537 break;
3538 case TLS_MODEL_GLOBAL_DYNAMIC:
3539 {
3540 rtx retval;
3541
3542 if (TARGET_INLINE_PLT)
3543 retval = gen_inlined_tls_plt (addr);
3544 else
3545 {
3546 /* call #gettlsoff(x) */
3547 retval = gen_reg_rtx (Pmode);
3548 emit_insn (gen_call_gettlsoff (retval, addr, picreg));
3549 }
3550 dest = gen_rtx_PLUS (Pmode, retval, tp);
3551 break;
3552 }
3553 default:
3554 gcc_unreachable ();
3555 }
3556
3557 return dest;
3558 }
3559
3560 rtx
frv_legitimize_address(rtx x,rtx oldx ATTRIBUTE_UNUSED,machine_mode mode ATTRIBUTE_UNUSED)3561 frv_legitimize_address (rtx x,
3562 rtx oldx ATTRIBUTE_UNUSED,
3563 machine_mode mode ATTRIBUTE_UNUSED)
3564 {
3565 if (GET_CODE (x) == SYMBOL_REF)
3566 {
3567 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
3568 if (model != 0)
3569 return frv_legitimize_tls_address (x, model);
3570 }
3571
3572 return x;
3573 }
3574
3575 /* Test whether a local function descriptor is canonical, i.e.,
3576 whether we can use FUNCDESC_GOTOFF to compute the address of the
3577 function. */
3578
3579 static bool
frv_local_funcdesc_p(rtx fnx)3580 frv_local_funcdesc_p (rtx fnx)
3581 {
3582 tree fn;
3583 enum symbol_visibility vis;
3584 bool ret;
3585
3586 if (! SYMBOL_REF_LOCAL_P (fnx))
3587 return FALSE;
3588
3589 fn = SYMBOL_REF_DECL (fnx);
3590
3591 if (! fn)
3592 return FALSE;
3593
3594 vis = DECL_VISIBILITY (fn);
3595
3596 if (vis == VISIBILITY_PROTECTED)
3597 /* Private function descriptors for protected functions are not
3598 canonical. Temporarily change the visibility to global. */
3599 vis = VISIBILITY_DEFAULT;
3600 else if (flag_shlib)
3601 /* If we're already compiling for a shared library (that, unlike
3602 executables, can't assume that the existence of a definition
3603 implies local binding), we can skip the re-testing. */
3604 return TRUE;
3605
3606 ret = default_binds_local_p_1 (fn, flag_pic);
3607
3608 DECL_VISIBILITY (fn) = vis;
3609
3610 return ret;
3611 }
3612
3613 /* Load the _gp symbol into DEST. SRC is supposed to be the FDPIC
3614 register. */
3615
3616 rtx
frv_gen_GPsym2reg(rtx dest,rtx src)3617 frv_gen_GPsym2reg (rtx dest, rtx src)
3618 {
3619 tree gp = get_identifier ("_gp");
3620 rtx gp_sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (gp));
3621
3622 return gen_symGOT2reg (dest, gp_sym, src, GEN_INT (R_FRV_GOT12));
3623 }
3624
3625 static const char *
unspec_got_name(int i)3626 unspec_got_name (int i)
3627 {
3628 switch (i)
3629 {
3630 case R_FRV_GOT12: return "got12";
3631 case R_FRV_GOTHI: return "gothi";
3632 case R_FRV_GOTLO: return "gotlo";
3633 case R_FRV_FUNCDESC: return "funcdesc";
3634 case R_FRV_FUNCDESC_GOT12: return "gotfuncdesc12";
3635 case R_FRV_FUNCDESC_GOTHI: return "gotfuncdeschi";
3636 case R_FRV_FUNCDESC_GOTLO: return "gotfuncdesclo";
3637 case R_FRV_FUNCDESC_VALUE: return "funcdescvalue";
3638 case R_FRV_FUNCDESC_GOTOFF12: return "gotofffuncdesc12";
3639 case R_FRV_FUNCDESC_GOTOFFHI: return "gotofffuncdeschi";
3640 case R_FRV_FUNCDESC_GOTOFFLO: return "gotofffuncdesclo";
3641 case R_FRV_GOTOFF12: return "gotoff12";
3642 case R_FRV_GOTOFFHI: return "gotoffhi";
3643 case R_FRV_GOTOFFLO: return "gotofflo";
3644 case R_FRV_GPREL12: return "gprel12";
3645 case R_FRV_GPRELHI: return "gprelhi";
3646 case R_FRV_GPRELLO: return "gprello";
3647 case R_FRV_GOTTLSOFF_HI: return "gottlsoffhi";
3648 case R_FRV_GOTTLSOFF_LO: return "gottlsofflo";
3649 case R_FRV_TLSMOFFHI: return "tlsmoffhi";
3650 case R_FRV_TLSMOFFLO: return "tlsmofflo";
3651 case R_FRV_TLSMOFF12: return "tlsmoff12";
3652 case R_FRV_TLSDESCHI: return "tlsdeschi";
3653 case R_FRV_TLSDESCLO: return "tlsdesclo";
3654 case R_FRV_GOTTLSDESCHI: return "gottlsdeschi";
3655 case R_FRV_GOTTLSDESCLO: return "gottlsdesclo";
3656 default: gcc_unreachable ();
3657 }
3658 }
3659
3660 /* Write the assembler syntax for UNSPEC to STREAM. Note that any offset
3661 is added inside the relocation operator. */
3662
3663 static void
frv_output_const_unspec(FILE * stream,const struct frv_unspec * unspec)3664 frv_output_const_unspec (FILE *stream, const struct frv_unspec *unspec)
3665 {
3666 fprintf (stream, "#%s(", unspec_got_name (unspec->reloc));
3667 output_addr_const (stream, plus_constant (Pmode, unspec->symbol,
3668 unspec->offset));
3669 fputs (")", stream);
3670 }
3671
3672 /* Implement FIND_BASE_TERM. See whether ORIG_X represents #gprel12(foo)
3673 or #gotoff12(foo) for some small data symbol foo. If so, return foo,
3674 otherwise return ORIG_X. */
3675
3676 rtx
frv_find_base_term(rtx x)3677 frv_find_base_term (rtx x)
3678 {
3679 struct frv_unspec unspec;
3680
3681 if (frv_const_unspec_p (x, &unspec)
3682 && frv_small_data_reloc_p (unspec.symbol, unspec.reloc))
3683 return plus_constant (Pmode, unspec.symbol, unspec.offset);
3684
3685 return x;
3686 }
3687
3688 /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if
3689 the operand is used by a predicated instruction. */
3690
3691 int
frv_legitimate_memory_operand(rtx op,machine_mode mode,int condexec_p)3692 frv_legitimate_memory_operand (rtx op, machine_mode mode, int condexec_p)
3693 {
3694 return ((GET_MODE (op) == mode || mode == VOIDmode)
3695 && GET_CODE (op) == MEM
3696 && frv_legitimate_address_p_1 (mode, XEXP (op, 0),
3697 reload_completed, condexec_p, FALSE));
3698 }
3699
3700 void
frv_expand_fdpic_call(rtx * operands,bool ret_value,bool sibcall)3701 frv_expand_fdpic_call (rtx *operands, bool ret_value, bool sibcall)
3702 {
3703 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
3704 rtx picreg = get_hard_reg_initial_val (SImode, FDPIC_REG);
3705 rtx c, rvrtx=0;
3706 rtx addr;
3707
3708 if (ret_value)
3709 {
3710 rvrtx = operands[0];
3711 operands ++;
3712 }
3713
3714 addr = XEXP (operands[0], 0);
3715
3716 /* Inline PLTs if we're optimizing for speed. We'd like to inline
3717 any calls that would involve a PLT, but can't tell, since we
3718 don't know whether an extern function is going to be provided by
3719 a separate translation unit or imported from a separate module.
3720 When compiling for shared libraries, if the function has default
3721 visibility, we assume it's overridable, so we inline the PLT, but
3722 for executables, we don't really have a way to make a good
3723 decision: a function is as likely to be imported from a shared
3724 library as it is to be defined in the executable itself. We
3725 assume executables will get global functions defined locally,
3726 whereas shared libraries will have them potentially overridden,
3727 so we only inline PLTs when compiling for shared libraries.
3728
3729 In order to mark a function as local to a shared library, any
3730 non-default visibility attribute suffices. Unfortunately,
3731 there's no simple way to tag a function declaration as ``in a
3732 different module'', which we could then use to trigger PLT
3733 inlining on executables. There's -minline-plt, but it affects
3734 all external functions, so one would have to also mark function
3735 declarations available in the same module with non-default
3736 visibility, which is advantageous in itself. */
3737 if (GET_CODE (addr) == SYMBOL_REF
3738 && ((!SYMBOL_REF_LOCAL_P (addr) && TARGET_INLINE_PLT)
3739 || sibcall))
3740 {
3741 rtx x, dest;
3742 dest = gen_reg_rtx (SImode);
3743 if (flag_pic != 1)
3744 x = gen_symGOTOFF2reg_hilo (dest, addr, OUR_FDPIC_REG,
3745 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3746 else
3747 x = gen_symGOTOFF2reg (dest, addr, OUR_FDPIC_REG,
3748 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3749 emit_insn (x);
3750 crtl->uses_pic_offset_table = TRUE;
3751 addr = dest;
3752 }
3753 else if (GET_CODE (addr) == SYMBOL_REF)
3754 {
3755 /* These are always either local, or handled through a local
3756 PLT. */
3757 if (ret_value)
3758 c = gen_call_value_fdpicsi (rvrtx, addr, operands[1],
3759 operands[2], picreg, lr);
3760 else
3761 c = gen_call_fdpicsi (addr, operands[1], operands[2], picreg, lr);
3762 emit_call_insn (c);
3763 return;
3764 }
3765 else if (! ldd_address_operand (addr, Pmode))
3766 addr = force_reg (Pmode, addr);
3767
3768 picreg = gen_reg_rtx (DImode);
3769 emit_insn (gen_movdi_ldd (picreg, addr));
3770
3771 if (sibcall && ret_value)
3772 c = gen_sibcall_value_fdpicdi (rvrtx, picreg, const0_rtx);
3773 else if (sibcall)
3774 c = gen_sibcall_fdpicdi (picreg, const0_rtx);
3775 else if (ret_value)
3776 c = gen_call_value_fdpicdi (rvrtx, picreg, const0_rtx, lr);
3777 else
3778 c = gen_call_fdpicdi (picreg, const0_rtx, lr);
3779 emit_call_insn (c);
3780 }
3781
3782 /* Look for a SYMBOL_REF of a function in an rtx. We always want to
3783 process these separately from any offsets, such that we add any
3784 offsets to the function descriptor (the actual pointer), not to the
3785 function address. */
3786
3787 static bool
frv_function_symbol_referenced_p(rtx x)3788 frv_function_symbol_referenced_p (rtx x)
3789 {
3790 const char *format;
3791 int length;
3792 int j;
3793
3794 if (GET_CODE (x) == SYMBOL_REF)
3795 return SYMBOL_REF_FUNCTION_P (x);
3796
3797 length = GET_RTX_LENGTH (GET_CODE (x));
3798 format = GET_RTX_FORMAT (GET_CODE (x));
3799
3800 for (j = 0; j < length; ++j)
3801 {
3802 switch (format[j])
3803 {
3804 case 'e':
3805 if (frv_function_symbol_referenced_p (XEXP (x, j)))
3806 return TRUE;
3807 break;
3808
3809 case 'V':
3810 case 'E':
3811 if (XVEC (x, j) != 0)
3812 {
3813 int k;
3814 for (k = 0; k < XVECLEN (x, j); ++k)
3815 if (frv_function_symbol_referenced_p (XVECEXP (x, j, k)))
3816 return TRUE;
3817 }
3818 break;
3819
3820 default:
3821 /* Nothing to do. */
3822 break;
3823 }
3824 }
3825
3826 return FALSE;
3827 }
3828
3829 /* Return true if the memory operand is one that can be conditionally
3830 executed. */
3831
3832 int
condexec_memory_operand(rtx op,machine_mode mode)3833 condexec_memory_operand (rtx op, machine_mode mode)
3834 {
3835 machine_mode op_mode = GET_MODE (op);
3836 rtx addr;
3837
3838 if (mode != VOIDmode && op_mode != mode)
3839 return FALSE;
3840
3841 switch (op_mode)
3842 {
3843 default:
3844 return FALSE;
3845
3846 case E_QImode:
3847 case E_HImode:
3848 case E_SImode:
3849 case E_SFmode:
3850 break;
3851 }
3852
3853 if (GET_CODE (op) != MEM)
3854 return FALSE;
3855
3856 addr = XEXP (op, 0);
3857 return frv_legitimate_address_p_1 (mode, addr, reload_completed, TRUE, FALSE);
3858 }
3859
3860 /* Return true if the bare return instruction can be used outside of the
3861 epilog code. For frv, we only do it if there was no stack allocation. */
3862
3863 int
direct_return_p(void)3864 direct_return_p (void)
3865 {
3866 frv_stack_t *info;
3867
3868 if (!reload_completed)
3869 return FALSE;
3870
3871 info = frv_stack_info ();
3872 return (info->total_size == 0);
3873 }
3874
3875
3876 void
frv_emit_move(machine_mode mode,rtx dest,rtx src)3877 frv_emit_move (machine_mode mode, rtx dest, rtx src)
3878 {
3879 if (GET_CODE (src) == SYMBOL_REF)
3880 {
3881 enum tls_model model = SYMBOL_REF_TLS_MODEL (src);
3882 if (model != 0)
3883 src = frv_legitimize_tls_address (src, model);
3884 }
3885
3886 switch (mode)
3887 {
3888 case E_SImode:
3889 if (frv_emit_movsi (dest, src))
3890 return;
3891 break;
3892
3893 case E_QImode:
3894 case E_HImode:
3895 case E_DImode:
3896 case E_SFmode:
3897 case E_DFmode:
3898 if (!reload_in_progress
3899 && !reload_completed
3900 && !register_operand (dest, mode)
3901 && !reg_or_0_operand (src, mode))
3902 src = copy_to_mode_reg (mode, src);
3903 break;
3904
3905 default:
3906 gcc_unreachable ();
3907 }
3908
3909 emit_insn (gen_rtx_SET (dest, src));
3910 }
3911
3912 /* Emit code to handle a MOVSI, adding in the small data register or pic
3913 register if needed to load up addresses. Return TRUE if the appropriate
3914 instructions are emitted. */
3915
3916 int
frv_emit_movsi(rtx dest,rtx src)3917 frv_emit_movsi (rtx dest, rtx src)
3918 {
3919 int base_regno = -1;
3920 int unspec = 0;
3921 rtx sym = src;
3922 struct frv_unspec old_unspec;
3923
3924 if (!reload_in_progress
3925 && !reload_completed
3926 && !register_operand (dest, SImode)
3927 && (!reg_or_0_operand (src, SImode)
3928 /* Virtual registers will almost always be replaced by an
3929 add instruction, so expose this to CSE by copying to
3930 an intermediate register. */
3931 || (GET_CODE (src) == REG
3932 && IN_RANGE (REGNO (src),
3933 FIRST_VIRTUAL_REGISTER,
3934 LAST_VIRTUAL_POINTER_REGISTER))))
3935 {
3936 emit_insn (gen_rtx_SET (dest, copy_to_mode_reg (SImode, src)));
3937 return TRUE;
3938 }
3939
3940 /* Explicitly add in the PIC or small data register if needed. */
3941 switch (GET_CODE (src))
3942 {
3943 default:
3944 break;
3945
3946 case LABEL_REF:
3947 handle_label:
3948 if (TARGET_FDPIC)
3949 {
3950 /* Using GPREL12, we use a single GOT entry for all symbols
3951 in read-only sections, but trade sequences such as:
3952
3953 sethi #gothi(label), gr#
3954 setlo #gotlo(label), gr#
3955 ld @(gr15,gr#), gr#
3956
3957 for
3958
3959 ld @(gr15,#got12(_gp)), gr#
3960 sethi #gprelhi(label), gr##
3961 setlo #gprello(label), gr##
3962 add gr#, gr##, gr##
3963
3964 We may often be able to share gr# for multiple
3965 computations of GPREL addresses, and we may often fold
3966 the final add into the pair of registers of a load or
3967 store instruction, so it's often profitable. Even when
3968 optimizing for size, we're trading a GOT entry for an
3969 additional instruction, which trades GOT space
3970 (read-write) for code size (read-only, shareable), as
3971 long as the symbol is not used in more than two different
3972 locations.
3973
3974 With -fpie/-fpic, we'd be trading a single load for a
3975 sequence of 4 instructions, because the offset of the
3976 label can't be assumed to be addressable with 12 bits, so
3977 we don't do this. */
3978 if (TARGET_GPREL_RO)
3979 unspec = R_FRV_GPREL12;
3980 else
3981 unspec = R_FRV_GOT12;
3982 }
3983 else if (flag_pic)
3984 base_regno = PIC_REGNO;
3985
3986 break;
3987
3988 case CONST:
3989 if (frv_const_unspec_p (src, &old_unspec))
3990 break;
3991
3992 if (TARGET_FDPIC && frv_function_symbol_referenced_p (XEXP (src, 0)))
3993 {
3994 handle_whatever:
3995 src = force_reg (GET_MODE (XEXP (src, 0)), XEXP (src, 0));
3996 emit_move_insn (dest, src);
3997 return TRUE;
3998 }
3999 else
4000 {
4001 sym = XEXP (sym, 0);
4002 if (GET_CODE (sym) == PLUS
4003 && GET_CODE (XEXP (sym, 0)) == SYMBOL_REF
4004 && GET_CODE (XEXP (sym, 1)) == CONST_INT)
4005 sym = XEXP (sym, 0);
4006 if (GET_CODE (sym) == SYMBOL_REF)
4007 goto handle_sym;
4008 else if (GET_CODE (sym) == LABEL_REF)
4009 goto handle_label;
4010 else
4011 goto handle_whatever;
4012 }
4013 break;
4014
4015 case SYMBOL_REF:
4016 handle_sym:
4017 if (TARGET_FDPIC)
4018 {
4019 enum tls_model model = SYMBOL_REF_TLS_MODEL (sym);
4020
4021 if (model != 0)
4022 {
4023 src = frv_legitimize_tls_address (src, model);
4024 emit_move_insn (dest, src);
4025 return TRUE;
4026 }
4027
4028 if (SYMBOL_REF_FUNCTION_P (sym))
4029 {
4030 if (frv_local_funcdesc_p (sym))
4031 unspec = R_FRV_FUNCDESC_GOTOFF12;
4032 else
4033 unspec = R_FRV_FUNCDESC_GOT12;
4034 }
4035 else
4036 {
4037 if (CONSTANT_POOL_ADDRESS_P (sym))
4038 switch (GET_CODE (get_pool_constant (sym)))
4039 {
4040 case CONST:
4041 case SYMBOL_REF:
4042 case LABEL_REF:
4043 if (flag_pic)
4044 {
4045 unspec = R_FRV_GOTOFF12;
4046 break;
4047 }
4048 /* Fall through. */
4049 default:
4050 if (TARGET_GPREL_RO)
4051 unspec = R_FRV_GPREL12;
4052 else
4053 unspec = R_FRV_GOT12;
4054 break;
4055 }
4056 else if (SYMBOL_REF_LOCAL_P (sym)
4057 && !SYMBOL_REF_EXTERNAL_P (sym)
4058 && SYMBOL_REF_DECL (sym)
4059 && (!DECL_P (SYMBOL_REF_DECL (sym))
4060 || !DECL_COMMON (SYMBOL_REF_DECL (sym))))
4061 {
4062 tree decl = SYMBOL_REF_DECL (sym);
4063 tree init = TREE_CODE (decl) == VAR_DECL
4064 ? DECL_INITIAL (decl)
4065 : TREE_CODE (decl) == CONSTRUCTOR
4066 ? decl : 0;
4067 int reloc = 0;
4068 bool named_section, readonly;
4069
4070 if (init && init != error_mark_node)
4071 reloc = compute_reloc_for_constant (init);
4072
4073 named_section = TREE_CODE (decl) == VAR_DECL
4074 && lookup_attribute ("section", DECL_ATTRIBUTES (decl));
4075 readonly = decl_readonly_section (decl, reloc);
4076
4077 if (named_section)
4078 unspec = R_FRV_GOT12;
4079 else if (!readonly)
4080 unspec = R_FRV_GOTOFF12;
4081 else if (readonly && TARGET_GPREL_RO)
4082 unspec = R_FRV_GPREL12;
4083 else
4084 unspec = R_FRV_GOT12;
4085 }
4086 else
4087 unspec = R_FRV_GOT12;
4088 }
4089 }
4090
4091 else if (SYMBOL_REF_SMALL_P (sym))
4092 base_regno = SDA_BASE_REG;
4093
4094 else if (flag_pic)
4095 base_regno = PIC_REGNO;
4096
4097 break;
4098 }
4099
4100 if (base_regno >= 0)
4101 {
4102 if (GET_CODE (sym) == SYMBOL_REF && SYMBOL_REF_SMALL_P (sym))
4103 emit_insn (gen_symGOTOFF2reg (dest, src,
4104 gen_rtx_REG (Pmode, base_regno),
4105 GEN_INT (R_FRV_GPREL12)));
4106 else
4107 emit_insn (gen_symGOTOFF2reg_hilo (dest, src,
4108 gen_rtx_REG (Pmode, base_regno),
4109 GEN_INT (R_FRV_GPREL12)));
4110 if (base_regno == PIC_REGNO)
4111 crtl->uses_pic_offset_table = TRUE;
4112 return TRUE;
4113 }
4114
4115 if (unspec)
4116 {
4117 rtx x;
4118
4119 /* Since OUR_FDPIC_REG is a pseudo register, we can't safely introduce
4120 new uses of it once reload has begun. */
4121 gcc_assert (!reload_in_progress && !reload_completed);
4122
4123 switch (unspec)
4124 {
4125 case R_FRV_GOTOFF12:
4126 if (!frv_small_data_reloc_p (sym, unspec))
4127 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
4128 GEN_INT (unspec));
4129 else
4130 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4131 break;
4132 case R_FRV_GPREL12:
4133 if (!frv_small_data_reloc_p (sym, unspec))
4134 x = gen_symGPREL2reg_hilo (dest, src, OUR_FDPIC_REG,
4135 GEN_INT (unspec));
4136 else
4137 x = gen_symGPREL2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4138 break;
4139 case R_FRV_FUNCDESC_GOTOFF12:
4140 if (flag_pic != 1)
4141 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
4142 GEN_INT (unspec));
4143 else
4144 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4145 break;
4146 default:
4147 if (flag_pic != 1)
4148 x = gen_symGOT2reg_hilo (dest, src, OUR_FDPIC_REG,
4149 GEN_INT (unspec));
4150 else
4151 x = gen_symGOT2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4152 break;
4153 }
4154 emit_insn (x);
4155 crtl->uses_pic_offset_table = TRUE;
4156 return TRUE;
4157 }
4158
4159
4160 return FALSE;
4161 }
4162
4163
4164 /* Return a string to output a single word move. */
4165
4166 const char *
output_move_single(rtx operands[],rtx insn)4167 output_move_single (rtx operands[], rtx insn)
4168 {
4169 rtx dest = operands[0];
4170 rtx src = operands[1];
4171
4172 if (GET_CODE (dest) == REG)
4173 {
4174 int dest_regno = REGNO (dest);
4175 machine_mode mode = GET_MODE (dest);
4176
4177 if (GPR_P (dest_regno))
4178 {
4179 if (GET_CODE (src) == REG)
4180 {
4181 /* gpr <- some sort of register */
4182 int src_regno = REGNO (src);
4183
4184 if (GPR_P (src_regno))
4185 return "mov %1, %0";
4186
4187 else if (FPR_P (src_regno))
4188 return "movfg %1, %0";
4189
4190 else if (SPR_P (src_regno))
4191 return "movsg %1, %0";
4192 }
4193
4194 else if (GET_CODE (src) == MEM)
4195 {
4196 /* gpr <- memory */
4197 switch (mode)
4198 {
4199 default:
4200 break;
4201
4202 case E_QImode:
4203 return "ldsb%I1%U1 %M1,%0";
4204
4205 case E_HImode:
4206 return "ldsh%I1%U1 %M1,%0";
4207
4208 case E_SImode:
4209 case E_SFmode:
4210 return "ld%I1%U1 %M1, %0";
4211 }
4212 }
4213
4214 else if (GET_CODE (src) == CONST_INT
4215 || GET_CODE (src) == CONST_DOUBLE)
4216 {
4217 /* gpr <- integer/floating constant */
4218 HOST_WIDE_INT value;
4219
4220 if (GET_CODE (src) == CONST_INT)
4221 value = INTVAL (src);
4222
4223 else if (mode == SFmode)
4224 {
4225 long l;
4226
4227 REAL_VALUE_TO_TARGET_SINGLE
4228 (*CONST_DOUBLE_REAL_VALUE (src), l);
4229 value = l;
4230 }
4231
4232 else
4233 value = CONST_DOUBLE_LOW (src);
4234
4235 if (IN_RANGE (value, -32768, 32767))
4236 return "setlos %1, %0";
4237
4238 return "#";
4239 }
4240
4241 else if (GET_CODE (src) == SYMBOL_REF
4242 || GET_CODE (src) == LABEL_REF
4243 || GET_CODE (src) == CONST)
4244 {
4245 return "#";
4246 }
4247 }
4248
4249 else if (FPR_P (dest_regno))
4250 {
4251 if (GET_CODE (src) == REG)
4252 {
4253 /* fpr <- some sort of register */
4254 int src_regno = REGNO (src);
4255
4256 if (GPR_P (src_regno))
4257 return "movgf %1, %0";
4258
4259 else if (FPR_P (src_regno))
4260 {
4261 if (TARGET_HARD_FLOAT)
4262 return "fmovs %1, %0";
4263 else
4264 return "mor %1, %1, %0";
4265 }
4266 }
4267
4268 else if (GET_CODE (src) == MEM)
4269 {
4270 /* fpr <- memory */
4271 switch (mode)
4272 {
4273 default:
4274 break;
4275
4276 case E_QImode:
4277 return "ldbf%I1%U1 %M1,%0";
4278
4279 case E_HImode:
4280 return "ldhf%I1%U1 %M1,%0";
4281
4282 case E_SImode:
4283 case E_SFmode:
4284 return "ldf%I1%U1 %M1, %0";
4285 }
4286 }
4287
4288 else if (ZERO_P (src))
4289 return "movgf %., %0";
4290 }
4291
4292 else if (SPR_P (dest_regno))
4293 {
4294 if (GET_CODE (src) == REG)
4295 {
4296 /* spr <- some sort of register */
4297 int src_regno = REGNO (src);
4298
4299 if (GPR_P (src_regno))
4300 return "movgs %1, %0";
4301 }
4302 else if (ZERO_P (src))
4303 return "movgs %., %0";
4304 }
4305 }
4306
4307 else if (GET_CODE (dest) == MEM)
4308 {
4309 if (GET_CODE (src) == REG)
4310 {
4311 int src_regno = REGNO (src);
4312 machine_mode mode = GET_MODE (dest);
4313
4314 if (GPR_P (src_regno))
4315 {
4316 switch (mode)
4317 {
4318 default:
4319 break;
4320
4321 case E_QImode:
4322 return "stb%I0%U0 %1, %M0";
4323
4324 case E_HImode:
4325 return "sth%I0%U0 %1, %M0";
4326
4327 case E_SImode:
4328 case E_SFmode:
4329 return "st%I0%U0 %1, %M0";
4330 }
4331 }
4332
4333 else if (FPR_P (src_regno))
4334 {
4335 switch (mode)
4336 {
4337 default:
4338 break;
4339
4340 case E_QImode:
4341 return "stbf%I0%U0 %1, %M0";
4342
4343 case E_HImode:
4344 return "sthf%I0%U0 %1, %M0";
4345
4346 case E_SImode:
4347 case E_SFmode:
4348 return "stf%I0%U0 %1, %M0";
4349 }
4350 }
4351 }
4352
4353 else if (ZERO_P (src))
4354 {
4355 switch (GET_MODE (dest))
4356 {
4357 default:
4358 break;
4359
4360 case E_QImode:
4361 return "stb%I0%U0 %., %M0";
4362
4363 case E_HImode:
4364 return "sth%I0%U0 %., %M0";
4365
4366 case E_SImode:
4367 case E_SFmode:
4368 return "st%I0%U0 %., %M0";
4369 }
4370 }
4371 }
4372
4373 fatal_insn ("bad output_move_single operand", insn);
4374 return "";
4375 }
4376
4377
4378 /* Return a string to output a double word move. */
4379
4380 const char *
output_move_double(rtx operands[],rtx insn)4381 output_move_double (rtx operands[], rtx insn)
4382 {
4383 rtx dest = operands[0];
4384 rtx src = operands[1];
4385 machine_mode mode = GET_MODE (dest);
4386
4387 if (GET_CODE (dest) == REG)
4388 {
4389 int dest_regno = REGNO (dest);
4390
4391 if (GPR_P (dest_regno))
4392 {
4393 if (GET_CODE (src) == REG)
4394 {
4395 /* gpr <- some sort of register */
4396 int src_regno = REGNO (src);
4397
4398 if (GPR_P (src_regno))
4399 return "#";
4400
4401 else if (FPR_P (src_regno))
4402 {
4403 if (((dest_regno - GPR_FIRST) & 1) == 0
4404 && ((src_regno - FPR_FIRST) & 1) == 0)
4405 return "movfgd %1, %0";
4406
4407 return "#";
4408 }
4409 }
4410
4411 else if (GET_CODE (src) == MEM)
4412 {
4413 /* gpr <- memory */
4414 if (dbl_memory_one_insn_operand (src, mode))
4415 return "ldd%I1%U1 %M1, %0";
4416
4417 return "#";
4418 }
4419
4420 else if (GET_CODE (src) == CONST_INT
4421 || GET_CODE (src) == CONST_DOUBLE)
4422 return "#";
4423 }
4424
4425 else if (FPR_P (dest_regno))
4426 {
4427 if (GET_CODE (src) == REG)
4428 {
4429 /* fpr <- some sort of register */
4430 int src_regno = REGNO (src);
4431
4432 if (GPR_P (src_regno))
4433 {
4434 if (((dest_regno - FPR_FIRST) & 1) == 0
4435 && ((src_regno - GPR_FIRST) & 1) == 0)
4436 return "movgfd %1, %0";
4437
4438 return "#";
4439 }
4440
4441 else if (FPR_P (src_regno))
4442 {
4443 if (TARGET_DOUBLE
4444 && ((dest_regno - FPR_FIRST) & 1) == 0
4445 && ((src_regno - FPR_FIRST) & 1) == 0)
4446 return "fmovd %1, %0";
4447
4448 return "#";
4449 }
4450 }
4451
4452 else if (GET_CODE (src) == MEM)
4453 {
4454 /* fpr <- memory */
4455 if (dbl_memory_one_insn_operand (src, mode))
4456 return "lddf%I1%U1 %M1, %0";
4457
4458 return "#";
4459 }
4460
4461 else if (ZERO_P (src))
4462 return "#";
4463 }
4464 }
4465
4466 else if (GET_CODE (dest) == MEM)
4467 {
4468 if (GET_CODE (src) == REG)
4469 {
4470 int src_regno = REGNO (src);
4471
4472 if (GPR_P (src_regno))
4473 {
4474 if (((src_regno - GPR_FIRST) & 1) == 0
4475 && dbl_memory_one_insn_operand (dest, mode))
4476 return "std%I0%U0 %1, %M0";
4477
4478 return "#";
4479 }
4480
4481 if (FPR_P (src_regno))
4482 {
4483 if (((src_regno - FPR_FIRST) & 1) == 0
4484 && dbl_memory_one_insn_operand (dest, mode))
4485 return "stdf%I0%U0 %1, %M0";
4486
4487 return "#";
4488 }
4489 }
4490
4491 else if (ZERO_P (src))
4492 {
4493 if (dbl_memory_one_insn_operand (dest, mode))
4494 return "std%I0%U0 %., %M0";
4495
4496 return "#";
4497 }
4498 }
4499
4500 fatal_insn ("bad output_move_double operand", insn);
4501 return "";
4502 }
4503
4504
4505 /* Return a string to output a single word conditional move.
4506 Operand0 -- EQ/NE of ccr register and 0
4507 Operand1 -- CCR register
4508 Operand2 -- destination
4509 Operand3 -- source */
4510
4511 const char *
output_condmove_single(rtx operands[],rtx insn)4512 output_condmove_single (rtx operands[], rtx insn)
4513 {
4514 rtx dest = operands[2];
4515 rtx src = operands[3];
4516
4517 if (GET_CODE (dest) == REG)
4518 {
4519 int dest_regno = REGNO (dest);
4520 machine_mode mode = GET_MODE (dest);
4521
4522 if (GPR_P (dest_regno))
4523 {
4524 if (GET_CODE (src) == REG)
4525 {
4526 /* gpr <- some sort of register */
4527 int src_regno = REGNO (src);
4528
4529 if (GPR_P (src_regno))
4530 return "cmov %z3, %2, %1, %e0";
4531
4532 else if (FPR_P (src_regno))
4533 return "cmovfg %3, %2, %1, %e0";
4534 }
4535
4536 else if (GET_CODE (src) == MEM)
4537 {
4538 /* gpr <- memory */
4539 switch (mode)
4540 {
4541 default:
4542 break;
4543
4544 case E_QImode:
4545 return "cldsb%I3%U3 %M3, %2, %1, %e0";
4546
4547 case E_HImode:
4548 return "cldsh%I3%U3 %M3, %2, %1, %e0";
4549
4550 case E_SImode:
4551 case E_SFmode:
4552 return "cld%I3%U3 %M3, %2, %1, %e0";
4553 }
4554 }
4555
4556 else if (ZERO_P (src))
4557 return "cmov %., %2, %1, %e0";
4558 }
4559
4560 else if (FPR_P (dest_regno))
4561 {
4562 if (GET_CODE (src) == REG)
4563 {
4564 /* fpr <- some sort of register */
4565 int src_regno = REGNO (src);
4566
4567 if (GPR_P (src_regno))
4568 return "cmovgf %3, %2, %1, %e0";
4569
4570 else if (FPR_P (src_regno))
4571 {
4572 if (TARGET_HARD_FLOAT)
4573 return "cfmovs %3,%2,%1,%e0";
4574 else
4575 return "cmor %3, %3, %2, %1, %e0";
4576 }
4577 }
4578
4579 else if (GET_CODE (src) == MEM)
4580 {
4581 /* fpr <- memory */
4582 if (mode == SImode || mode == SFmode)
4583 return "cldf%I3%U3 %M3, %2, %1, %e0";
4584 }
4585
4586 else if (ZERO_P (src))
4587 return "cmovgf %., %2, %1, %e0";
4588 }
4589 }
4590
4591 else if (GET_CODE (dest) == MEM)
4592 {
4593 if (GET_CODE (src) == REG)
4594 {
4595 int src_regno = REGNO (src);
4596 machine_mode mode = GET_MODE (dest);
4597
4598 if (GPR_P (src_regno))
4599 {
4600 switch (mode)
4601 {
4602 default:
4603 break;
4604
4605 case E_QImode:
4606 return "cstb%I2%U2 %3, %M2, %1, %e0";
4607
4608 case E_HImode:
4609 return "csth%I2%U2 %3, %M2, %1, %e0";
4610
4611 case E_SImode:
4612 case E_SFmode:
4613 return "cst%I2%U2 %3, %M2, %1, %e0";
4614 }
4615 }
4616
4617 else if (FPR_P (src_regno) && (mode == SImode || mode == SFmode))
4618 return "cstf%I2%U2 %3, %M2, %1, %e0";
4619 }
4620
4621 else if (ZERO_P (src))
4622 {
4623 machine_mode mode = GET_MODE (dest);
4624 switch (mode)
4625 {
4626 default:
4627 break;
4628
4629 case E_QImode:
4630 return "cstb%I2%U2 %., %M2, %1, %e0";
4631
4632 case E_HImode:
4633 return "csth%I2%U2 %., %M2, %1, %e0";
4634
4635 case E_SImode:
4636 case E_SFmode:
4637 return "cst%I2%U2 %., %M2, %1, %e0";
4638 }
4639 }
4640 }
4641
4642 fatal_insn ("bad output_condmove_single operand", insn);
4643 return "";
4644 }
4645
4646
4647 /* Emit the appropriate code to do a comparison, returning the register the
4648 comparison was done it. */
4649
4650 static rtx
frv_emit_comparison(enum rtx_code test,rtx op0,rtx op1)4651 frv_emit_comparison (enum rtx_code test, rtx op0, rtx op1)
4652 {
4653 machine_mode cc_mode;
4654 rtx cc_reg;
4655
4656 /* Floating point doesn't have comparison against a constant. */
4657 if (GET_MODE (op0) == CC_FPmode && GET_CODE (op1) != REG)
4658 op1 = force_reg (GET_MODE (op0), op1);
4659
4660 /* Possibly disable using anything but a fixed register in order to work
4661 around cse moving comparisons past function calls. */
4662 cc_mode = SELECT_CC_MODE (test, op0, op1);
4663 cc_reg = ((TARGET_ALLOC_CC)
4664 ? gen_reg_rtx (cc_mode)
4665 : gen_rtx_REG (cc_mode,
4666 (cc_mode == CC_FPmode) ? FCC_FIRST : ICC_FIRST));
4667
4668 emit_insn (gen_rtx_SET (cc_reg, gen_rtx_COMPARE (cc_mode, op0, op1)));
4669
4670 return cc_reg;
4671 }
4672
4673
4674 /* Emit code for a conditional branch.
4675 XXX: I originally wanted to add a clobber of a CCR register to use in
4676 conditional execution, but that confuses the rest of the compiler. */
4677
4678 int
frv_emit_cond_branch(rtx operands[])4679 frv_emit_cond_branch (rtx operands[])
4680 {
4681 rtx test_rtx;
4682 rtx label_ref;
4683 rtx if_else;
4684 enum rtx_code test = GET_CODE (operands[0]);
4685 rtx cc_reg = frv_emit_comparison (test, operands[1], operands[2]);
4686 machine_mode cc_mode = GET_MODE (cc_reg);
4687
4688 /* Branches generate:
4689 (set (pc)
4690 (if_then_else (<test>, <cc_reg>, (const_int 0))
4691 (label_ref <branch_label>)
4692 (pc))) */
4693 label_ref = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
4694 test_rtx = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
4695 if_else = gen_rtx_IF_THEN_ELSE (cc_mode, test_rtx, label_ref, pc_rtx);
4696 emit_jump_insn (gen_rtx_SET (pc_rtx, if_else));
4697 return TRUE;
4698 }
4699
4700
4701 /* Emit code to set a gpr to 1/0 based on a comparison. */
4702
4703 int
frv_emit_scc(rtx operands[])4704 frv_emit_scc (rtx operands[])
4705 {
4706 rtx set;
4707 rtx test_rtx;
4708 rtx clobber;
4709 rtx cr_reg;
4710 enum rtx_code test = GET_CODE (operands[1]);
4711 rtx cc_reg = frv_emit_comparison (test, operands[2], operands[3]);
4712
4713 /* SCC instructions generate:
4714 (parallel [(set <target> (<test>, <cc_reg>, (const_int 0))
4715 (clobber (<ccr_reg>))]) */
4716 test_rtx = gen_rtx_fmt_ee (test, SImode, cc_reg, const0_rtx);
4717 set = gen_rtx_SET (operands[0], test_rtx);
4718
4719 cr_reg = ((TARGET_ALLOC_CC)
4720 ? gen_reg_rtx (CC_CCRmode)
4721 : gen_rtx_REG (CC_CCRmode,
4722 ((GET_MODE (cc_reg) == CC_FPmode)
4723 ? FCR_FIRST
4724 : ICR_FIRST)));
4725
4726 clobber = gen_rtx_CLOBBER (VOIDmode, cr_reg);
4727 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
4728 return TRUE;
4729 }
4730
4731
4732 /* Split a SCC instruction into component parts, returning a SEQUENCE to hold
4733 the separate insns. */
4734
4735 rtx
frv_split_scc(rtx dest,rtx test,rtx cc_reg,rtx cr_reg,HOST_WIDE_INT value)4736 frv_split_scc (rtx dest, rtx test, rtx cc_reg, rtx cr_reg, HOST_WIDE_INT value)
4737 {
4738 rtx ret;
4739
4740 start_sequence ();
4741
4742 /* Set the appropriate CCR bit. */
4743 emit_insn (gen_rtx_SET (cr_reg,
4744 gen_rtx_fmt_ee (GET_CODE (test),
4745 GET_MODE (cr_reg),
4746 cc_reg,
4747 const0_rtx)));
4748
4749 /* Move the value into the destination. */
4750 emit_move_insn (dest, GEN_INT (value));
4751
4752 /* Move 0 into the destination if the test failed */
4753 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4754 gen_rtx_EQ (GET_MODE (cr_reg),
4755 cr_reg,
4756 const0_rtx),
4757 gen_rtx_SET (dest, const0_rtx)));
4758
4759 /* Finish up, return sequence. */
4760 ret = get_insns ();
4761 end_sequence ();
4762 return ret;
4763 }
4764
4765
4766 /* Emit the code for a conditional move, return TRUE if we could do the
4767 move. */
4768
4769 int
frv_emit_cond_move(rtx dest,rtx test_rtx,rtx src1,rtx src2)4770 frv_emit_cond_move (rtx dest, rtx test_rtx, rtx src1, rtx src2)
4771 {
4772 rtx set;
4773 rtx clobber_cc;
4774 rtx test2;
4775 rtx cr_reg;
4776 rtx if_rtx;
4777 enum rtx_code test = GET_CODE (test_rtx);
4778 rtx cc_reg = frv_emit_comparison (test,
4779 XEXP (test_rtx, 0), XEXP (test_rtx, 1));
4780 machine_mode cc_mode = GET_MODE (cc_reg);
4781
4782 /* Conditional move instructions generate:
4783 (parallel [(set <target>
4784 (if_then_else (<test> <cc_reg> (const_int 0))
4785 <src1>
4786 <src2>))
4787 (clobber (<ccr_reg>))]) */
4788
4789 /* Handle various cases of conditional move involving two constants. */
4790 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
4791 {
4792 HOST_WIDE_INT value1 = INTVAL (src1);
4793 HOST_WIDE_INT value2 = INTVAL (src2);
4794
4795 /* Having 0 as one of the constants can be done by loading the other
4796 constant, and optionally moving in gr0. */
4797 if (value1 == 0 || value2 == 0)
4798 ;
4799
4800 /* If the first value is within an addi range and also the difference
4801 between the two fits in an addi's range, load up the difference, then
4802 conditionally move in 0, and then unconditionally add the first
4803 value. */
4804 else if (IN_RANGE (value1, -2048, 2047)
4805 && IN_RANGE (value2 - value1, -2048, 2047))
4806 ;
4807
4808 /* If neither condition holds, just force the constant into a
4809 register. */
4810 else
4811 {
4812 src1 = force_reg (GET_MODE (dest), src1);
4813 src2 = force_reg (GET_MODE (dest), src2);
4814 }
4815 }
4816
4817 /* If one value is a register, insure the other value is either 0 or a
4818 register. */
4819 else
4820 {
4821 if (GET_CODE (src1) == CONST_INT && INTVAL (src1) != 0)
4822 src1 = force_reg (GET_MODE (dest), src1);
4823
4824 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
4825 src2 = force_reg (GET_MODE (dest), src2);
4826 }
4827
4828 test2 = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
4829 if_rtx = gen_rtx_IF_THEN_ELSE (GET_MODE (dest), test2, src1, src2);
4830
4831 set = gen_rtx_SET (dest, if_rtx);
4832
4833 cr_reg = ((TARGET_ALLOC_CC)
4834 ? gen_reg_rtx (CC_CCRmode)
4835 : gen_rtx_REG (CC_CCRmode,
4836 (cc_mode == CC_FPmode) ? FCR_FIRST : ICR_FIRST));
4837
4838 clobber_cc = gen_rtx_CLOBBER (VOIDmode, cr_reg);
4839 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber_cc)));
4840 return TRUE;
4841 }
4842
4843
4844 /* Split a conditional move into constituent parts, returning a SEQUENCE
4845 containing all of the insns. */
4846
4847 rtx
frv_split_cond_move(rtx operands[])4848 frv_split_cond_move (rtx operands[])
4849 {
4850 rtx dest = operands[0];
4851 rtx test = operands[1];
4852 rtx cc_reg = operands[2];
4853 rtx src1 = operands[3];
4854 rtx src2 = operands[4];
4855 rtx cr_reg = operands[5];
4856 rtx ret;
4857 machine_mode cr_mode = GET_MODE (cr_reg);
4858
4859 start_sequence ();
4860
4861 /* Set the appropriate CCR bit. */
4862 emit_insn (gen_rtx_SET (cr_reg,
4863 gen_rtx_fmt_ee (GET_CODE (test),
4864 GET_MODE (cr_reg),
4865 cc_reg,
4866 const0_rtx)));
4867
4868 /* Handle various cases of conditional move involving two constants. */
4869 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
4870 {
4871 HOST_WIDE_INT value1 = INTVAL (src1);
4872 HOST_WIDE_INT value2 = INTVAL (src2);
4873
4874 /* Having 0 as one of the constants can be done by loading the other
4875 constant, and optionally moving in gr0. */
4876 if (value1 == 0)
4877 {
4878 emit_move_insn (dest, src2);
4879 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4880 gen_rtx_NE (cr_mode, cr_reg,
4881 const0_rtx),
4882 gen_rtx_SET (dest, src1)));
4883 }
4884
4885 else if (value2 == 0)
4886 {
4887 emit_move_insn (dest, src1);
4888 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4889 gen_rtx_EQ (cr_mode, cr_reg,
4890 const0_rtx),
4891 gen_rtx_SET (dest, src2)));
4892 }
4893
4894 /* If the first value is within an addi range and also the difference
4895 between the two fits in an addi's range, load up the difference, then
4896 conditionally move in 0, and then unconditionally add the first
4897 value. */
4898 else if (IN_RANGE (value1, -2048, 2047)
4899 && IN_RANGE (value2 - value1, -2048, 2047))
4900 {
4901 rtx dest_si = ((GET_MODE (dest) == SImode)
4902 ? dest
4903 : gen_rtx_SUBREG (SImode, dest, 0));
4904
4905 emit_move_insn (dest_si, GEN_INT (value2 - value1));
4906 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4907 gen_rtx_NE (cr_mode, cr_reg,
4908 const0_rtx),
4909 gen_rtx_SET (dest_si, const0_rtx)));
4910 emit_insn (gen_addsi3 (dest_si, dest_si, src1));
4911 }
4912
4913 else
4914 gcc_unreachable ();
4915 }
4916 else
4917 {
4918 /* Emit the conditional move for the test being true if needed. */
4919 if (! rtx_equal_p (dest, src1))
4920 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4921 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
4922 gen_rtx_SET (dest, src1)));
4923
4924 /* Emit the conditional move for the test being false if needed. */
4925 if (! rtx_equal_p (dest, src2))
4926 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4927 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
4928 gen_rtx_SET (dest, src2)));
4929 }
4930
4931 /* Finish up, return sequence. */
4932 ret = get_insns ();
4933 end_sequence ();
4934 return ret;
4935 }
4936
4937
4938 /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a
4939 memory location that is not known to be dword-aligned. */
4940 void
frv_split_double_load(rtx dest,rtx source)4941 frv_split_double_load (rtx dest, rtx source)
4942 {
4943 int regno = REGNO (dest);
4944 rtx dest1 = gen_highpart (SImode, dest);
4945 rtx dest2 = gen_lowpart (SImode, dest);
4946 rtx address = XEXP (source, 0);
4947
4948 /* If the address is pre-modified, load the lower-numbered register
4949 first, then load the other register using an integer offset from
4950 the modified base register. This order should always be safe,
4951 since the pre-modification cannot affect the same registers as the
4952 load does.
4953
4954 The situation for other loads is more complicated. Loading one
4955 of the registers could affect the value of ADDRESS, so we must
4956 be careful which order we do them in. */
4957 if (GET_CODE (address) == PRE_MODIFY
4958 || ! refers_to_regno_p (regno, address))
4959 {
4960 /* It is safe to load the lower-numbered register first. */
4961 emit_move_insn (dest1, change_address (source, SImode, NULL));
4962 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
4963 }
4964 else
4965 {
4966 /* ADDRESS is not pre-modified and the address depends on the
4967 lower-numbered register. Load the higher-numbered register
4968 first. */
4969 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
4970 emit_move_insn (dest1, change_address (source, SImode, NULL));
4971 }
4972 }
4973
4974 /* Split (set DEST SOURCE), where DEST refers to a dword memory location
4975 and SOURCE is either a double register or the constant zero. */
4976 void
frv_split_double_store(rtx dest,rtx source)4977 frv_split_double_store (rtx dest, rtx source)
4978 {
4979 rtx dest1 = change_address (dest, SImode, NULL);
4980 rtx dest2 = frv_index_memory (dest, SImode, 1);
4981 if (ZERO_P (source))
4982 {
4983 emit_move_insn (dest1, CONST0_RTX (SImode));
4984 emit_move_insn (dest2, CONST0_RTX (SImode));
4985 }
4986 else
4987 {
4988 emit_move_insn (dest1, gen_highpart (SImode, source));
4989 emit_move_insn (dest2, gen_lowpart (SImode, source));
4990 }
4991 }
4992
4993
4994 /* Split a min/max operation returning a SEQUENCE containing all of the
4995 insns. */
4996
4997 rtx
frv_split_minmax(rtx operands[])4998 frv_split_minmax (rtx operands[])
4999 {
5000 rtx dest = operands[0];
5001 rtx minmax = operands[1];
5002 rtx src1 = operands[2];
5003 rtx src2 = operands[3];
5004 rtx cc_reg = operands[4];
5005 rtx cr_reg = operands[5];
5006 rtx ret;
5007 enum rtx_code test_code;
5008 machine_mode cr_mode = GET_MODE (cr_reg);
5009
5010 start_sequence ();
5011
5012 /* Figure out which test to use. */
5013 switch (GET_CODE (minmax))
5014 {
5015 default:
5016 gcc_unreachable ();
5017
5018 case SMIN: test_code = LT; break;
5019 case SMAX: test_code = GT; break;
5020 case UMIN: test_code = LTU; break;
5021 case UMAX: test_code = GTU; break;
5022 }
5023
5024 /* Issue the compare instruction. */
5025 emit_insn (gen_rtx_SET (cc_reg, gen_rtx_COMPARE (GET_MODE (cc_reg),
5026 src1, src2)));
5027
5028 /* Set the appropriate CCR bit. */
5029 emit_insn (gen_rtx_SET (cr_reg, gen_rtx_fmt_ee (test_code,
5030 GET_MODE (cr_reg),
5031 cc_reg,
5032 const0_rtx)));
5033
5034 /* If are taking the min/max of a nonzero constant, load that first, and
5035 then do a conditional move of the other value. */
5036 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
5037 {
5038 gcc_assert (!rtx_equal_p (dest, src1));
5039
5040 emit_move_insn (dest, src2);
5041 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5042 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5043 gen_rtx_SET (dest, src1)));
5044 }
5045
5046 /* Otherwise, do each half of the move. */
5047 else
5048 {
5049 /* Emit the conditional move for the test being true if needed. */
5050 if (! rtx_equal_p (dest, src1))
5051 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5052 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5053 gen_rtx_SET (dest, src1)));
5054
5055 /* Emit the conditional move for the test being false if needed. */
5056 if (! rtx_equal_p (dest, src2))
5057 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5058 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
5059 gen_rtx_SET (dest, src2)));
5060 }
5061
5062 /* Finish up, return sequence. */
5063 ret = get_insns ();
5064 end_sequence ();
5065 return ret;
5066 }
5067
5068
5069 /* Split an integer abs operation returning a SEQUENCE containing all of the
5070 insns. */
5071
5072 rtx
frv_split_abs(rtx operands[])5073 frv_split_abs (rtx operands[])
5074 {
5075 rtx dest = operands[0];
5076 rtx src = operands[1];
5077 rtx cc_reg = operands[2];
5078 rtx cr_reg = operands[3];
5079 rtx ret;
5080
5081 start_sequence ();
5082
5083 /* Issue the compare < 0 instruction. */
5084 emit_insn (gen_rtx_SET (cc_reg, gen_rtx_COMPARE (CCmode, src, const0_rtx)));
5085
5086 /* Set the appropriate CCR bit. */
5087 emit_insn (gen_rtx_SET (cr_reg, gen_rtx_fmt_ee (LT, CC_CCRmode,
5088 cc_reg, const0_rtx)));
5089
5090 /* Emit the conditional negate if the value is negative. */
5091 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5092 gen_rtx_NE (CC_CCRmode, cr_reg, const0_rtx),
5093 gen_negsi2 (dest, src)));
5094
5095 /* Emit the conditional move for the test being false if needed. */
5096 if (! rtx_equal_p (dest, src))
5097 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5098 gen_rtx_EQ (CC_CCRmode, cr_reg, const0_rtx),
5099 gen_rtx_SET (dest, src)));
5100
5101 /* Finish up, return sequence. */
5102 ret = get_insns ();
5103 end_sequence ();
5104 return ret;
5105 }
5106
5107
5108 /* Initialize machine-specific if-conversion data.
5109 On the FR-V, we don't have any extra fields per se, but it is useful hook to
5110 initialize the static storage. */
5111 void
frv_ifcvt_machdep_init(void * ce_info ATTRIBUTE_UNUSED)5112 frv_ifcvt_machdep_init (void *ce_info ATTRIBUTE_UNUSED)
5113 {
5114 frv_ifcvt.added_insns_list = NULL_RTX;
5115 frv_ifcvt.cur_scratch_regs = 0;
5116 frv_ifcvt.num_nested_cond_exec = 0;
5117 frv_ifcvt.cr_reg = NULL_RTX;
5118 frv_ifcvt.nested_cc_reg = NULL_RTX;
5119 frv_ifcvt.extra_int_cr = NULL_RTX;
5120 frv_ifcvt.extra_fp_cr = NULL_RTX;
5121 frv_ifcvt.last_nested_if_cr = NULL_RTX;
5122 }
5123
5124
5125 /* Internal function to add a potential insn to the list of insns to be inserted
5126 if the conditional execution conversion is successful. */
5127
5128 static void
frv_ifcvt_add_insn(rtx pattern,rtx_insn * insn,int before_p)5129 frv_ifcvt_add_insn (rtx pattern, rtx_insn *insn, int before_p)
5130 {
5131 rtx link = alloc_EXPR_LIST (VOIDmode, pattern, insn);
5132
5133 link->jump = before_p; /* Mark to add this before or after insn. */
5134 frv_ifcvt.added_insns_list = alloc_EXPR_LIST (VOIDmode, link,
5135 frv_ifcvt.added_insns_list);
5136
5137 if (TARGET_DEBUG_COND_EXEC)
5138 {
5139 fprintf (stderr,
5140 "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n",
5141 (before_p) ? "before" : "after",
5142 (int)INSN_UID (insn));
5143
5144 debug_rtx (pattern);
5145 }
5146 }
5147
5148
5149 /* A C expression to modify the code described by the conditional if
5150 information CE_INFO, possibly updating the tests in TRUE_EXPR, and
5151 FALSE_EXPR for converting if-then and if-then-else code to conditional
5152 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
5153 tests cannot be converted. */
5154
5155 void
frv_ifcvt_modify_tests(ce_if_block * ce_info,rtx * p_true,rtx * p_false)5156 frv_ifcvt_modify_tests (ce_if_block *ce_info, rtx *p_true, rtx *p_false)
5157 {
5158 basic_block test_bb = ce_info->test_bb; /* test basic block */
5159 basic_block then_bb = ce_info->then_bb; /* THEN */
5160 basic_block else_bb = ce_info->else_bb; /* ELSE or NULL */
5161 basic_block join_bb = ce_info->join_bb; /* join block or NULL */
5162 rtx true_expr = *p_true;
5163 rtx cr;
5164 rtx cc;
5165 rtx nested_cc;
5166 machine_mode mode = GET_MODE (true_expr);
5167 int j;
5168 basic_block *bb;
5169 int num_bb;
5170 frv_tmp_reg_t *tmp_reg = &frv_ifcvt.tmp_reg;
5171 rtx check_insn;
5172 rtx sub_cond_exec_reg;
5173 enum rtx_code code;
5174 enum rtx_code code_true;
5175 enum rtx_code code_false;
5176 enum reg_class cc_class;
5177 enum reg_class cr_class;
5178 int cc_first;
5179 int cc_last;
5180 reg_set_iterator rsi;
5181
5182 /* Make sure we are only dealing with hard registers. Also honor the
5183 -mno-cond-exec switch, and -mno-nested-cond-exec switches if
5184 applicable. */
5185 if (!reload_completed || !TARGET_COND_EXEC
5186 || (!TARGET_NESTED_CE && ce_info->pass > 1))
5187 goto fail;
5188
5189 /* Figure out which registers we can allocate for our own purposes. Only
5190 consider registers that are not preserved across function calls and are
5191 not fixed. However, allow the ICC/ICR temporary registers to be allocated
5192 if we did not need to use them in reloading other registers. */
5193 memset (&tmp_reg->regs, 0, sizeof (tmp_reg->regs));
5194 tmp_reg->regs = regs_invalidated_by_call & ~fixed_reg_set;
5195 SET_HARD_REG_BIT (tmp_reg->regs, ICC_TEMP);
5196 SET_HARD_REG_BIT (tmp_reg->regs, ICR_TEMP);
5197
5198 /* If this is a nested IF, we need to discover whether the CC registers that
5199 are set/used inside of the block are used anywhere else. If not, we can
5200 change them to be the CC register that is paired with the CR register that
5201 controls the outermost IF block. */
5202 if (ce_info->pass > 1)
5203 {
5204 CLEAR_HARD_REG_SET (frv_ifcvt.nested_cc_ok_rewrite);
5205 for (j = CC_FIRST; j <= CC_LAST; j++)
5206 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5207 {
5208 if (REGNO_REG_SET_P (df_get_live_in (then_bb), j))
5209 continue;
5210
5211 if (else_bb
5212 && REGNO_REG_SET_P (df_get_live_in (else_bb), j))
5213 continue;
5214
5215 if (join_bb
5216 && REGNO_REG_SET_P (df_get_live_in (join_bb), j))
5217 continue;
5218
5219 SET_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j);
5220 }
5221 }
5222
5223 for (j = 0; j < frv_ifcvt.cur_scratch_regs; j++)
5224 frv_ifcvt.scratch_regs[j] = NULL_RTX;
5225
5226 frv_ifcvt.added_insns_list = NULL_RTX;
5227 frv_ifcvt.cur_scratch_regs = 0;
5228
5229 bb = (basic_block *) alloca ((2 + ce_info->num_multiple_test_blocks)
5230 * sizeof (basic_block));
5231
5232 if (join_bb)
5233 {
5234 unsigned int regno;
5235
5236 /* Remove anything live at the beginning of the join block from being
5237 available for allocation. */
5238 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (join_bb), 0, regno, rsi)
5239 {
5240 if (regno < FIRST_PSEUDO_REGISTER)
5241 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
5242 }
5243 }
5244
5245 /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */
5246 num_bb = 0;
5247 if (ce_info->num_multiple_test_blocks)
5248 {
5249 basic_block multiple_test_bb = ce_info->last_test_bb;
5250
5251 while (multiple_test_bb != test_bb)
5252 {
5253 bb[num_bb++] = multiple_test_bb;
5254 multiple_test_bb = EDGE_PRED (multiple_test_bb, 0)->src;
5255 }
5256 }
5257
5258 /* Add in the THEN and ELSE blocks to be scanned. */
5259 bb[num_bb++] = then_bb;
5260 if (else_bb)
5261 bb[num_bb++] = else_bb;
5262
5263 sub_cond_exec_reg = NULL_RTX;
5264 frv_ifcvt.num_nested_cond_exec = 0;
5265
5266 /* Scan all of the blocks for registers that must not be allocated. */
5267 for (j = 0; j < num_bb; j++)
5268 {
5269 rtx_insn *last_insn = BB_END (bb[j]);
5270 rtx_insn *insn = BB_HEAD (bb[j]);
5271 unsigned int regno;
5272
5273 if (dump_file)
5274 fprintf (dump_file, "Scanning %s block %d, start %d, end %d\n",
5275 (bb[j] == else_bb) ? "else" : ((bb[j] == then_bb) ? "then" : "test"),
5276 (int) bb[j]->index,
5277 (int) INSN_UID (BB_HEAD (bb[j])),
5278 (int) INSN_UID (BB_END (bb[j])));
5279
5280 /* Anything live at the beginning of the block is obviously unavailable
5281 for allocation. */
5282 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (bb[j]), 0, regno, rsi)
5283 {
5284 if (regno < FIRST_PSEUDO_REGISTER)
5285 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
5286 }
5287
5288 /* Loop through the insns in the block. */
5289 for (;;)
5290 {
5291 /* Mark any new registers that are created as being unavailable for
5292 allocation. Also see if the CC register used in nested IFs can be
5293 reallocated. */
5294 if (INSN_P (insn))
5295 {
5296 rtx pattern;
5297 rtx set;
5298 int skip_nested_if = FALSE;
5299 HARD_REG_SET mentioned_regs;
5300
5301 CLEAR_HARD_REG_SET (mentioned_regs);
5302 find_all_hard_regs (PATTERN (insn), &mentioned_regs);
5303 tmp_reg->regs &= ~mentioned_regs;
5304
5305 pattern = PATTERN (insn);
5306 if (GET_CODE (pattern) == COND_EXEC)
5307 {
5308 rtx reg = XEXP (COND_EXEC_TEST (pattern), 0);
5309
5310 if (reg != sub_cond_exec_reg)
5311 {
5312 sub_cond_exec_reg = reg;
5313 frv_ifcvt.num_nested_cond_exec++;
5314 }
5315 }
5316
5317 set = single_set_pattern (pattern);
5318 if (set)
5319 {
5320 rtx dest = SET_DEST (set);
5321 rtx src = SET_SRC (set);
5322
5323 if (GET_CODE (dest) == REG)
5324 {
5325 int regno = REGNO (dest);
5326 enum rtx_code src_code = GET_CODE (src);
5327
5328 if (CC_P (regno) && src_code == COMPARE)
5329 skip_nested_if = TRUE;
5330
5331 else if (CR_P (regno)
5332 && (src_code == IF_THEN_ELSE
5333 || COMPARISON_P (src)))
5334 skip_nested_if = TRUE;
5335 }
5336 }
5337
5338 if (! skip_nested_if)
5339 frv_ifcvt.nested_cc_ok_rewrite &= ~mentioned_regs;
5340 }
5341
5342 if (insn == last_insn)
5343 break;
5344
5345 insn = NEXT_INSN (insn);
5346 }
5347 }
5348
5349 /* If this is a nested if, rewrite the CC registers that are available to
5350 include the ones that can be rewritten, to increase the chance of being
5351 able to allocate a paired CC/CR register combination. */
5352 if (ce_info->pass > 1)
5353 {
5354 for (j = CC_FIRST; j <= CC_LAST; j++)
5355 if (TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j))
5356 SET_HARD_REG_BIT (tmp_reg->regs, j);
5357 else
5358 CLEAR_HARD_REG_BIT (tmp_reg->regs, j);
5359 }
5360
5361 if (dump_file)
5362 {
5363 int num_gprs = 0;
5364 fprintf (dump_file, "Available GPRs: ");
5365
5366 for (j = GPR_FIRST; j <= GPR_LAST; j++)
5367 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5368 {
5369 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5370 if (++num_gprs > GPR_TEMP_NUM+2)
5371 break;
5372 }
5373
5374 fprintf (dump_file, "%s\nAvailable CRs: ",
5375 (num_gprs > GPR_TEMP_NUM+2) ? " ..." : "");
5376
5377 for (j = CR_FIRST; j <= CR_LAST; j++)
5378 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5379 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5380
5381 fputs ("\n", dump_file);
5382
5383 if (ce_info->pass > 1)
5384 {
5385 fprintf (dump_file, "Modifiable CCs: ");
5386 for (j = CC_FIRST; j <= CC_LAST; j++)
5387 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5388 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5389
5390 fprintf (dump_file, "\n%d nested COND_EXEC statements\n",
5391 frv_ifcvt.num_nested_cond_exec);
5392 }
5393 }
5394
5395 /* Allocate the appropriate temporary condition code register. Try to
5396 allocate the ICR/FCR register that corresponds to the ICC/FCC register so
5397 that conditional cmp's can be done. */
5398 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
5399 {
5400 cr_class = ICR_REGS;
5401 cc_class = ICC_REGS;
5402 cc_first = ICC_FIRST;
5403 cc_last = ICC_LAST;
5404 }
5405 else if (mode == CC_FPmode)
5406 {
5407 cr_class = FCR_REGS;
5408 cc_class = FCC_REGS;
5409 cc_first = FCC_FIRST;
5410 cc_last = FCC_LAST;
5411 }
5412 else
5413 {
5414 cc_first = cc_last = 0;
5415 cr_class = cc_class = NO_REGS;
5416 }
5417
5418 cc = XEXP (true_expr, 0);
5419 nested_cc = cr = NULL_RTX;
5420 if (cc_class != NO_REGS)
5421 {
5422 /* For nested IFs and &&/||, see if we can find a CC and CR register pair
5423 so we can execute a csubcc/caddcc/cfcmps instruction. */
5424 int cc_regno;
5425
5426 for (cc_regno = cc_first; cc_regno <= cc_last; cc_regno++)
5427 {
5428 int cr_regno = cc_regno - CC_FIRST + CR_FIRST;
5429
5430 if (TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cc_regno)
5431 && TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cr_regno))
5432 {
5433 frv_ifcvt.tmp_reg.next_reg[ (int)cr_class ] = cr_regno;
5434 cr = frv_alloc_temp_reg (tmp_reg, cr_class, CC_CCRmode, TRUE,
5435 TRUE);
5436
5437 frv_ifcvt.tmp_reg.next_reg[ (int)cc_class ] = cc_regno;
5438 nested_cc = frv_alloc_temp_reg (tmp_reg, cc_class, CCmode,
5439 TRUE, TRUE);
5440 break;
5441 }
5442 }
5443 }
5444
5445 if (! cr)
5446 {
5447 if (dump_file)
5448 fprintf (dump_file, "Could not allocate a CR temporary register\n");
5449
5450 goto fail;
5451 }
5452
5453 if (dump_file)
5454 fprintf (dump_file,
5455 "Will use %s for conditional execution, %s for nested comparisons\n",
5456 reg_names[ REGNO (cr)],
5457 (nested_cc) ? reg_names[ REGNO (nested_cc) ] : "<none>");
5458
5459 /* Set the CCR bit. Note for integer tests, we reverse the condition so that
5460 in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR
5461 bit being true. We don't do this for floating point, because of NaNs. */
5462 code = GET_CODE (true_expr);
5463 if (GET_MODE (cc) != CC_FPmode)
5464 {
5465 code = reverse_condition (code);
5466 code_true = EQ;
5467 code_false = NE;
5468 }
5469 else
5470 {
5471 code_true = NE;
5472 code_false = EQ;
5473 }
5474
5475 check_insn = gen_rtx_SET (cr, gen_rtx_fmt_ee (code, CC_CCRmode,
5476 cc, const0_rtx));
5477
5478 /* Record the check insn to be inserted later. */
5479 frv_ifcvt_add_insn (check_insn, BB_END (test_bb), TRUE);
5480
5481 /* Update the tests. */
5482 frv_ifcvt.cr_reg = cr;
5483 frv_ifcvt.nested_cc_reg = nested_cc;
5484 *p_true = gen_rtx_fmt_ee (code_true, CC_CCRmode, cr, const0_rtx);
5485 *p_false = gen_rtx_fmt_ee (code_false, CC_CCRmode, cr, const0_rtx);
5486 return;
5487
5488 /* Fail, don't do this conditional execution. */
5489 fail:
5490 *p_true = NULL_RTX;
5491 *p_false = NULL_RTX;
5492 if (dump_file)
5493 fprintf (dump_file, "Disabling this conditional execution.\n");
5494
5495 return;
5496 }
5497
5498
5499 /* A C expression to modify the code described by the conditional if
5500 information CE_INFO, for the basic block BB, possibly updating the tests in
5501 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
5502 if-then-else code to conditional instructions. Set either TRUE_EXPR or
5503 FALSE_EXPR to a null pointer if the tests cannot be converted. */
5504
5505 /* p_true and p_false are given expressions of the form:
5506
5507 (and (eq:CC_CCR (reg:CC_CCR)
5508 (const_int 0))
5509 (eq:CC (reg:CC)
5510 (const_int 0))) */
5511
5512 void
frv_ifcvt_modify_multiple_tests(ce_if_block * ce_info,basic_block bb,rtx * p_true,rtx * p_false)5513 frv_ifcvt_modify_multiple_tests (ce_if_block *ce_info,
5514 basic_block bb,
5515 rtx *p_true,
5516 rtx *p_false)
5517 {
5518 rtx old_true = XEXP (*p_true, 0);
5519 rtx old_false = XEXP (*p_false, 0);
5520 rtx true_expr = XEXP (*p_true, 1);
5521 rtx false_expr = XEXP (*p_false, 1);
5522 rtx test_expr;
5523 rtx old_test;
5524 rtx cr = XEXP (old_true, 0);
5525 rtx check_insn;
5526 rtx new_cr = NULL_RTX;
5527 rtx *p_new_cr = (rtx *)0;
5528 rtx if_else;
5529 rtx compare;
5530 rtx cc;
5531 enum reg_class cr_class;
5532 machine_mode mode = GET_MODE (true_expr);
5533 rtx (*logical_func)(rtx, rtx, rtx);
5534
5535 if (TARGET_DEBUG_COND_EXEC)
5536 {
5537 fprintf (stderr,
5538 "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n",
5539 ce_info->and_and_p ? "&&" : "||");
5540
5541 debug_rtx (*p_true);
5542
5543 fputs ("\nfalse insn:\n", stderr);
5544 debug_rtx (*p_false);
5545 }
5546
5547 if (!TARGET_MULTI_CE)
5548 goto fail;
5549
5550 if (GET_CODE (cr) != REG)
5551 goto fail;
5552
5553 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
5554 {
5555 cr_class = ICR_REGS;
5556 p_new_cr = &frv_ifcvt.extra_int_cr;
5557 }
5558 else if (mode == CC_FPmode)
5559 {
5560 cr_class = FCR_REGS;
5561 p_new_cr = &frv_ifcvt.extra_fp_cr;
5562 }
5563 else
5564 goto fail;
5565
5566 /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or
5567 more &&/|| tests. */
5568 new_cr = *p_new_cr;
5569 if (! new_cr)
5570 {
5571 new_cr = *p_new_cr = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, cr_class,
5572 CC_CCRmode, TRUE, TRUE);
5573 if (! new_cr)
5574 goto fail;
5575 }
5576
5577 if (ce_info->and_and_p)
5578 {
5579 old_test = old_false;
5580 test_expr = true_expr;
5581 logical_func = (GET_CODE (old_true) == EQ) ? gen_andcr : gen_andncr;
5582 *p_true = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
5583 *p_false = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
5584 }
5585 else
5586 {
5587 old_test = old_false;
5588 test_expr = false_expr;
5589 logical_func = (GET_CODE (old_false) == EQ) ? gen_orcr : gen_orncr;
5590 *p_true = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
5591 *p_false = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
5592 }
5593
5594 /* First add the andcr/andncr/orcr/orncr, which will be added after the
5595 conditional check instruction, due to frv_ifcvt_add_insn being a LIFO
5596 stack. */
5597 frv_ifcvt_add_insn ((*logical_func) (cr, cr, new_cr), BB_END (bb), TRUE);
5598
5599 /* Now add the conditional check insn. */
5600 cc = XEXP (test_expr, 0);
5601 compare = gen_rtx_fmt_ee (GET_CODE (test_expr), CC_CCRmode, cc, const0_rtx);
5602 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, old_test, compare, const0_rtx);
5603
5604 check_insn = gen_rtx_SET (new_cr, if_else);
5605
5606 /* Add the new check insn to the list of check insns that need to be
5607 inserted. */
5608 frv_ifcvt_add_insn (check_insn, BB_END (bb), TRUE);
5609
5610 if (TARGET_DEBUG_COND_EXEC)
5611 {
5612 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n",
5613 stderr);
5614
5615 debug_rtx (*p_true);
5616
5617 fputs ("\nfalse insn:\n", stderr);
5618 debug_rtx (*p_false);
5619 }
5620
5621 return;
5622
5623 fail:
5624 *p_true = *p_false = NULL_RTX;
5625
5626 /* If we allocated a CR register, release it. */
5627 if (new_cr)
5628 {
5629 CLEAR_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, REGNO (new_cr));
5630 *p_new_cr = NULL_RTX;
5631 }
5632
5633 if (TARGET_DEBUG_COND_EXEC)
5634 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr);
5635
5636 return;
5637 }
5638
5639
5640 /* Return a register which will be loaded with a value if an IF block is
5641 converted to conditional execution. This is used to rewrite instructions
5642 that use constants to ones that just use registers. */
5643
5644 static rtx
frv_ifcvt_load_value(rtx value,rtx insn ATTRIBUTE_UNUSED)5645 frv_ifcvt_load_value (rtx value, rtx insn ATTRIBUTE_UNUSED)
5646 {
5647 int num_alloc = frv_ifcvt.cur_scratch_regs;
5648 int i;
5649 rtx reg;
5650
5651 /* We know gr0 == 0, so replace any errant uses. */
5652 if (value == const0_rtx)
5653 return gen_rtx_REG (SImode, GPR_FIRST);
5654
5655 /* First search all registers currently loaded to see if we have an
5656 applicable constant. */
5657 if (CONSTANT_P (value)
5658 || (GET_CODE (value) == REG && REGNO (value) == LR_REGNO))
5659 {
5660 for (i = 0; i < num_alloc; i++)
5661 {
5662 if (rtx_equal_p (SET_SRC (frv_ifcvt.scratch_regs[i]), value))
5663 return SET_DEST (frv_ifcvt.scratch_regs[i]);
5664 }
5665 }
5666
5667 /* Have we exhausted the number of registers available? */
5668 if (num_alloc >= GPR_TEMP_NUM)
5669 {
5670 if (dump_file)
5671 fprintf (dump_file, "Too many temporary registers allocated\n");
5672
5673 return NULL_RTX;
5674 }
5675
5676 /* Allocate the new register. */
5677 reg = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, GPR_REGS, SImode, TRUE, TRUE);
5678 if (! reg)
5679 {
5680 if (dump_file)
5681 fputs ("Could not find a scratch register\n", dump_file);
5682
5683 return NULL_RTX;
5684 }
5685
5686 frv_ifcvt.cur_scratch_regs++;
5687 frv_ifcvt.scratch_regs[num_alloc] = gen_rtx_SET (reg, value);
5688
5689 if (dump_file)
5690 {
5691 if (GET_CODE (value) == CONST_INT)
5692 fprintf (dump_file, "Register %s will hold %ld\n",
5693 reg_names[ REGNO (reg)], (long)INTVAL (value));
5694
5695 else if (GET_CODE (value) == REG && REGNO (value) == LR_REGNO)
5696 fprintf (dump_file, "Register %s will hold LR\n",
5697 reg_names[ REGNO (reg)]);
5698
5699 else
5700 fprintf (dump_file, "Register %s will hold a saved value\n",
5701 reg_names[ REGNO (reg)]);
5702 }
5703
5704 return reg;
5705 }
5706
5707
5708 /* Update a MEM used in conditional code that might contain an offset to put
5709 the offset into a scratch register, so that the conditional load/store
5710 operations can be used. This function returns the original pointer if the
5711 MEM is valid to use in conditional code, NULL if we can't load up the offset
5712 into a temporary register, or the new MEM if we were successful. */
5713
5714 static rtx
frv_ifcvt_rewrite_mem(rtx mem,machine_mode mode,rtx insn)5715 frv_ifcvt_rewrite_mem (rtx mem, machine_mode mode, rtx insn)
5716 {
5717 rtx addr = XEXP (mem, 0);
5718
5719 if (!frv_legitimate_address_p_1 (mode, addr, reload_completed, TRUE, FALSE))
5720 {
5721 if (GET_CODE (addr) == PLUS)
5722 {
5723 rtx addr_op0 = XEXP (addr, 0);
5724 rtx addr_op1 = XEXP (addr, 1);
5725
5726 if (GET_CODE (addr_op0) == REG && CONSTANT_P (addr_op1))
5727 {
5728 rtx reg = frv_ifcvt_load_value (addr_op1, insn);
5729 if (!reg)
5730 return NULL_RTX;
5731
5732 addr = gen_rtx_PLUS (Pmode, addr_op0, reg);
5733 }
5734
5735 else
5736 return NULL_RTX;
5737 }
5738
5739 else if (CONSTANT_P (addr))
5740 addr = frv_ifcvt_load_value (addr, insn);
5741
5742 else
5743 return NULL_RTX;
5744
5745 if (addr == NULL_RTX)
5746 return NULL_RTX;
5747
5748 else if (XEXP (mem, 0) != addr)
5749 return change_address (mem, mode, addr);
5750 }
5751
5752 return mem;
5753 }
5754
5755
5756 /* Given a PATTERN, return a SET expression if this PATTERN has only a single
5757 SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */
5758
5759 static rtx
single_set_pattern(rtx pattern)5760 single_set_pattern (rtx pattern)
5761 {
5762 rtx set;
5763 int i;
5764
5765 if (GET_CODE (pattern) == COND_EXEC)
5766 pattern = COND_EXEC_CODE (pattern);
5767
5768 if (GET_CODE (pattern) == SET)
5769 return pattern;
5770
5771 else if (GET_CODE (pattern) == PARALLEL)
5772 {
5773 for (i = 0, set = 0; i < XVECLEN (pattern, 0); i++)
5774 {
5775 rtx sub = XVECEXP (pattern, 0, i);
5776
5777 switch (GET_CODE (sub))
5778 {
5779 case USE:
5780 case CLOBBER:
5781 break;
5782
5783 case SET:
5784 if (set)
5785 return 0;
5786 else
5787 set = sub;
5788 break;
5789
5790 default:
5791 return 0;
5792 }
5793 }
5794 return set;
5795 }
5796
5797 return 0;
5798 }
5799
5800
5801 /* A C expression to modify the code described by the conditional if
5802 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null
5803 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
5804 insn cannot be converted to be executed conditionally. */
5805
5806 rtx
frv_ifcvt_modify_insn(ce_if_block * ce_info,rtx pattern,rtx_insn * insn)5807 frv_ifcvt_modify_insn (ce_if_block *ce_info,
5808 rtx pattern,
5809 rtx_insn *insn)
5810 {
5811 rtx orig_ce_pattern = pattern;
5812 rtx set;
5813 rtx op0;
5814 rtx op1;
5815 rtx test;
5816
5817 gcc_assert (GET_CODE (pattern) == COND_EXEC);
5818
5819 test = COND_EXEC_TEST (pattern);
5820 if (GET_CODE (test) == AND)
5821 {
5822 rtx cr = frv_ifcvt.cr_reg;
5823 rtx test_reg;
5824
5825 op0 = XEXP (test, 0);
5826 if (! rtx_equal_p (cr, XEXP (op0, 0)))
5827 goto fail;
5828
5829 op1 = XEXP (test, 1);
5830 test_reg = XEXP (op1, 0);
5831 if (GET_CODE (test_reg) != REG)
5832 goto fail;
5833
5834 /* Is this the first nested if block in this sequence? If so, generate
5835 an andcr or andncr. */
5836 if (! frv_ifcvt.last_nested_if_cr)
5837 {
5838 rtx and_op;
5839
5840 frv_ifcvt.last_nested_if_cr = test_reg;
5841 if (GET_CODE (op0) == NE)
5842 and_op = gen_andcr (test_reg, cr, test_reg);
5843 else
5844 and_op = gen_andncr (test_reg, cr, test_reg);
5845
5846 frv_ifcvt_add_insn (and_op, insn, TRUE);
5847 }
5848
5849 /* If this isn't the first statement in the nested if sequence, see if we
5850 are dealing with the same register. */
5851 else if (! rtx_equal_p (test_reg, frv_ifcvt.last_nested_if_cr))
5852 goto fail;
5853
5854 COND_EXEC_TEST (pattern) = test = op1;
5855 }
5856
5857 /* If this isn't a nested if, reset state variables. */
5858 else
5859 {
5860 frv_ifcvt.last_nested_if_cr = NULL_RTX;
5861 }
5862
5863 set = single_set_pattern (pattern);
5864 if (set)
5865 {
5866 rtx dest = SET_DEST (set);
5867 rtx src = SET_SRC (set);
5868 machine_mode mode = GET_MODE (dest);
5869
5870 /* Check for normal binary operators. */
5871 if (mode == SImode && ARITHMETIC_P (src))
5872 {
5873 op0 = XEXP (src, 0);
5874 op1 = XEXP (src, 1);
5875
5876 if (integer_register_operand (op0, SImode) && CONSTANT_P (op1))
5877 {
5878 op1 = frv_ifcvt_load_value (op1, insn);
5879 if (op1)
5880 COND_EXEC_CODE (pattern)
5881 = gen_rtx_SET (dest, gen_rtx_fmt_ee (GET_CODE (src),
5882 GET_MODE (src),
5883 op0, op1));
5884 else
5885 goto fail;
5886 }
5887 }
5888
5889 /* For multiply by a constant, we need to handle the sign extending
5890 correctly. Add a USE of the value after the multiply to prevent flow
5891 from cratering because only one register out of the two were used. */
5892 else if (mode == DImode && GET_CODE (src) == MULT)
5893 {
5894 op0 = XEXP (src, 0);
5895 op1 = XEXP (src, 1);
5896 if (GET_CODE (op0) == SIGN_EXTEND && GET_CODE (op1) == CONST_INT)
5897 {
5898 op1 = frv_ifcvt_load_value (op1, insn);
5899 if (op1)
5900 {
5901 op1 = gen_rtx_SIGN_EXTEND (DImode, op1);
5902 COND_EXEC_CODE (pattern)
5903 = gen_rtx_SET (dest, gen_rtx_MULT (DImode, op0, op1));
5904 }
5905 else
5906 goto fail;
5907 }
5908
5909 frv_ifcvt_add_insn (gen_use (dest), insn, FALSE);
5910 }
5911
5912 /* If we are just loading a constant created for a nested conditional
5913 execution statement, just load the constant without any conditional
5914 execution, since we know that the constant will not interfere with any
5915 other registers. */
5916 else if (frv_ifcvt.scratch_insns_bitmap
5917 && bitmap_bit_p (frv_ifcvt.scratch_insns_bitmap,
5918 INSN_UID (insn))
5919 && REG_P (SET_DEST (set))
5920 /* We must not unconditionally set a scratch reg chosen
5921 for a nested if-converted block if its incoming
5922 value from the TEST block (or the result of the THEN
5923 branch) could/should propagate to the JOIN block.
5924 It suffices to test whether the register is live at
5925 the JOIN point: if it's live there, we can infer
5926 that we set it in the former JOIN block of the
5927 nested if-converted block (otherwise it wouldn't
5928 have been available as a scratch register), and it
5929 is either propagated through or set in the other
5930 conditional block. It's probably not worth trying
5931 to catch the latter case, and it could actually
5932 limit scheduling of the combined block quite
5933 severely. */
5934 && ce_info->join_bb
5935 && ! (REGNO_REG_SET_P (df_get_live_in (ce_info->join_bb),
5936 REGNO (SET_DEST (set))))
5937 /* Similarly, we must not unconditionally set a reg
5938 used as scratch in the THEN branch if the same reg
5939 is live in the ELSE branch. */
5940 && (! ce_info->else_bb
5941 || BLOCK_FOR_INSN (insn) == ce_info->else_bb
5942 || ! (REGNO_REG_SET_P (df_get_live_in (ce_info->else_bb),
5943 REGNO (SET_DEST (set))))))
5944 pattern = set;
5945
5946 else if (mode == QImode || mode == HImode || mode == SImode
5947 || mode == SFmode)
5948 {
5949 int changed_p = FALSE;
5950
5951 /* Check for just loading up a constant */
5952 if (CONSTANT_P (src) && integer_register_operand (dest, mode))
5953 {
5954 src = frv_ifcvt_load_value (src, insn);
5955 if (!src)
5956 goto fail;
5957
5958 changed_p = TRUE;
5959 }
5960
5961 /* See if we need to fix up stores */
5962 if (GET_CODE (dest) == MEM)
5963 {
5964 rtx new_mem = frv_ifcvt_rewrite_mem (dest, mode, insn);
5965
5966 if (!new_mem)
5967 goto fail;
5968
5969 else if (new_mem != dest)
5970 {
5971 changed_p = TRUE;
5972 dest = new_mem;
5973 }
5974 }
5975
5976 /* See if we need to fix up loads */
5977 if (GET_CODE (src) == MEM)
5978 {
5979 rtx new_mem = frv_ifcvt_rewrite_mem (src, mode, insn);
5980
5981 if (!new_mem)
5982 goto fail;
5983
5984 else if (new_mem != src)
5985 {
5986 changed_p = TRUE;
5987 src = new_mem;
5988 }
5989 }
5990
5991 /* If either src or destination changed, redo SET. */
5992 if (changed_p)
5993 COND_EXEC_CODE (pattern) = gen_rtx_SET (dest, src);
5994 }
5995
5996 /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with
5997 rewriting the CC register to be the same as the paired CC/CR register
5998 for nested ifs. */
5999 else if (mode == CC_CCRmode && COMPARISON_P (src))
6000 {
6001 int regno = REGNO (XEXP (src, 0));
6002 rtx if_else;
6003
6004 if (ce_info->pass > 1
6005 && regno != (int)REGNO (frv_ifcvt.nested_cc_reg)
6006 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, regno))
6007 {
6008 src = gen_rtx_fmt_ee (GET_CODE (src),
6009 CC_CCRmode,
6010 frv_ifcvt.nested_cc_reg,
6011 XEXP (src, 1));
6012 }
6013
6014 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, test, src, const0_rtx);
6015 pattern = gen_rtx_SET (dest, if_else);
6016 }
6017
6018 /* Remap a nested compare instruction to use the paired CC/CR reg. */
6019 else if (ce_info->pass > 1
6020 && GET_CODE (dest) == REG
6021 && CC_P (REGNO (dest))
6022 && REGNO (dest) != REGNO (frv_ifcvt.nested_cc_reg)
6023 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite,
6024 REGNO (dest))
6025 && GET_CODE (src) == COMPARE)
6026 {
6027 PUT_MODE (frv_ifcvt.nested_cc_reg, GET_MODE (dest));
6028 COND_EXEC_CODE (pattern)
6029 = gen_rtx_SET (frv_ifcvt.nested_cc_reg, copy_rtx (src));
6030 }
6031 }
6032
6033 if (TARGET_DEBUG_COND_EXEC)
6034 {
6035 rtx orig_pattern = PATTERN (insn);
6036
6037 PATTERN (insn) = pattern;
6038 fprintf (stderr,
6039 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n",
6040 ce_info->pass);
6041
6042 debug_rtx (insn);
6043 PATTERN (insn) = orig_pattern;
6044 }
6045
6046 return pattern;
6047
6048 fail:
6049 if (TARGET_DEBUG_COND_EXEC)
6050 {
6051 rtx orig_pattern = PATTERN (insn);
6052
6053 PATTERN (insn) = orig_ce_pattern;
6054 fprintf (stderr,
6055 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n",
6056 ce_info->pass);
6057
6058 debug_rtx (insn);
6059 PATTERN (insn) = orig_pattern;
6060 }
6061
6062 return NULL_RTX;
6063 }
6064
6065
6066 /* A C expression to perform any final machine dependent modifications in
6067 converting code to conditional execution in the code described by the
6068 conditional if information CE_INFO. */
6069
6070 void
frv_ifcvt_modify_final(ce_if_block * ce_info ATTRIBUTE_UNUSED)6071 frv_ifcvt_modify_final (ce_if_block *ce_info ATTRIBUTE_UNUSED)
6072 {
6073 rtx_insn *existing_insn;
6074 rtx check_insn;
6075 rtx p = frv_ifcvt.added_insns_list;
6076 int i;
6077
6078 /* Loop inserting the check insns. The last check insn is the first test,
6079 and is the appropriate place to insert constants. */
6080 gcc_assert (p);
6081
6082 do
6083 {
6084 rtx check_and_insert_insns = XEXP (p, 0);
6085 rtx old_p = p;
6086
6087 check_insn = XEXP (check_and_insert_insns, 0);
6088 existing_insn = as_a <rtx_insn *> (XEXP (check_and_insert_insns, 1));
6089 p = XEXP (p, 1);
6090
6091 /* The jump bit is used to say that the new insn is to be inserted BEFORE
6092 the existing insn, otherwise it is to be inserted AFTER. */
6093 if (check_and_insert_insns->jump)
6094 {
6095 emit_insn_before (check_insn, existing_insn);
6096 check_and_insert_insns->jump = 0;
6097 }
6098 else
6099 emit_insn_after (check_insn, existing_insn);
6100
6101 free_EXPR_LIST_node (check_and_insert_insns);
6102 free_EXPR_LIST_node (old_p);
6103 }
6104 while (p != NULL_RTX);
6105
6106 /* Load up any constants needed into temp gprs */
6107 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
6108 {
6109 rtx_insn *insn = emit_insn_before (frv_ifcvt.scratch_regs[i], existing_insn);
6110 if (! frv_ifcvt.scratch_insns_bitmap)
6111 frv_ifcvt.scratch_insns_bitmap = BITMAP_ALLOC (NULL);
6112 bitmap_set_bit (frv_ifcvt.scratch_insns_bitmap, INSN_UID (insn));
6113 frv_ifcvt.scratch_regs[i] = NULL_RTX;
6114 }
6115
6116 frv_ifcvt.added_insns_list = NULL_RTX;
6117 frv_ifcvt.cur_scratch_regs = 0;
6118 }
6119
6120
6121 /* A C expression to cancel any machine dependent modifications in converting
6122 code to conditional execution in the code described by the conditional if
6123 information CE_INFO. */
6124
6125 void
frv_ifcvt_modify_cancel(ce_if_block * ce_info ATTRIBUTE_UNUSED)6126 frv_ifcvt_modify_cancel (ce_if_block *ce_info ATTRIBUTE_UNUSED)
6127 {
6128 int i;
6129 rtx p = frv_ifcvt.added_insns_list;
6130
6131 /* Loop freeing up the EXPR_LIST's allocated. */
6132 while (p != NULL_RTX)
6133 {
6134 rtx check_and_jump = XEXP (p, 0);
6135 rtx old_p = p;
6136
6137 p = XEXP (p, 1);
6138 free_EXPR_LIST_node (check_and_jump);
6139 free_EXPR_LIST_node (old_p);
6140 }
6141
6142 /* Release any temporary gprs allocated. */
6143 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
6144 frv_ifcvt.scratch_regs[i] = NULL_RTX;
6145
6146 frv_ifcvt.added_insns_list = NULL_RTX;
6147 frv_ifcvt.cur_scratch_regs = 0;
6148 return;
6149 }
6150
6151 /* A C expression for the size in bytes of the trampoline, as an integer.
6152 The template is:
6153
6154 setlo #0, <jmp_reg>
6155 setlo #0, <static_chain>
6156 sethi #0, <jmp_reg>
6157 sethi #0, <static_chain>
6158 jmpl @(gr0,<jmp_reg>) */
6159
6160 int
frv_trampoline_size(void)6161 frv_trampoline_size (void)
6162 {
6163 if (TARGET_FDPIC)
6164 /* Allocate room for the function descriptor and the lddi
6165 instruction. */
6166 return 8 + 6 * 4;
6167 return 5 /* instructions */ * 4 /* instruction size. */;
6168 }
6169
6170
6171 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
6172 RTX for the address of the trampoline; FNADDR is an RTX for the address of
6173 the nested function; STATIC_CHAIN is an RTX for the static chain value that
6174 should be passed to the function when it is called.
6175
6176 The template is:
6177
6178 setlo #0, <jmp_reg>
6179 setlo #0, <static_chain>
6180 sethi #0, <jmp_reg>
6181 sethi #0, <static_chain>
6182 jmpl @(gr0,<jmp_reg>) */
6183
6184 static void
frv_trampoline_init(rtx m_tramp,tree fndecl,rtx static_chain)6185 frv_trampoline_init (rtx m_tramp, tree fndecl, rtx static_chain)
6186 {
6187 rtx addr = XEXP (m_tramp, 0);
6188 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
6189 rtx sc_reg = force_reg (Pmode, static_chain);
6190
6191 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
6192 LCT_NORMAL, VOIDmode,
6193 addr, Pmode,
6194 GEN_INT (frv_trampoline_size ()), SImode,
6195 fnaddr, Pmode,
6196 sc_reg, Pmode);
6197 }
6198
6199
6200 /* Many machines have some registers that cannot be copied directly to or from
6201 memory or even from other types of registers. An example is the `MQ'
6202 register, which on most machines, can only be copied to or from general
6203 registers, but not memory. Some machines allow copying all registers to and
6204 from memory, but require a scratch register for stores to some memory
6205 locations (e.g., those with symbolic address on the RT, and those with
6206 certain symbolic address on the SPARC when compiling PIC). In some cases,
6207 both an intermediate and a scratch register are required.
6208
6209 You should define these macros to indicate to the reload phase that it may
6210 need to allocate at least one register for a reload in addition to the
6211 register to contain the data. Specifically, if copying X to a register
6212 RCLASS in MODE requires an intermediate register, you should define
6213 `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
6214 whose registers can be used as intermediate registers or scratch registers.
6215
6216 If copying a register RCLASS in MODE to X requires an intermediate or scratch
6217 register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
6218 largest register class required. If the requirements for input and output
6219 reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
6220 instead of defining both macros identically.
6221
6222 The values returned by these macros are often `GENERAL_REGS'. Return
6223 `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
6224 to or from a register of RCLASS in MODE without requiring a scratch register.
6225 Do not define this macro if it would always return `NO_REGS'.
6226
6227 If a scratch register is required (either with or without an intermediate
6228 register), you should define patterns for `reload_inM' or `reload_outM', as
6229 required.. These patterns, which will normally be implemented with a
6230 `define_expand', should be similar to the `movM' patterns, except that
6231 operand 2 is the scratch register.
6232
6233 Define constraints for the reload register and scratch register that contain
6234 a single register class. If the original reload register (whose class is
6235 RCLASS) can meet the constraint given in the pattern, the value returned by
6236 these macros is used for the class of the scratch register. Otherwise, two
6237 additional reload registers are required. Their classes are obtained from
6238 the constraints in the insn pattern.
6239
6240 X might be a pseudo-register or a `subreg' of a pseudo-register, which could
6241 either be in a hard register or in memory. Use `true_regnum' to find out;
6242 it will return -1 if the pseudo is in memory and the hard register number if
6243 it is in a register.
6244
6245 These macros should not be used in the case where a particular class of
6246 registers can only be copied to memory and not to another class of
6247 registers. In that case, secondary reload registers are not needed and
6248 would not be helpful. Instead, a stack location must be used to perform the
6249 copy and the `movM' pattern should use memory as an intermediate storage.
6250 This case often occurs between floating-point and general registers. */
6251
6252 enum reg_class
frv_secondary_reload_class(enum reg_class rclass,machine_mode mode ATTRIBUTE_UNUSED,rtx x)6253 frv_secondary_reload_class (enum reg_class rclass,
6254 machine_mode mode ATTRIBUTE_UNUSED,
6255 rtx x)
6256 {
6257 enum reg_class ret;
6258
6259 switch (rclass)
6260 {
6261 default:
6262 ret = NO_REGS;
6263 break;
6264
6265 /* Accumulators/Accumulator guard registers need to go through floating
6266 point registers. */
6267 case QUAD_REGS:
6268 case GPR_REGS:
6269 ret = NO_REGS;
6270 if (x && GET_CODE (x) == REG)
6271 {
6272 int regno = REGNO (x);
6273
6274 if (ACC_P (regno) || ACCG_P (regno))
6275 ret = FPR_REGS;
6276 }
6277 break;
6278
6279 /* Nonzero constants should be loaded into an FPR through a GPR. */
6280 case QUAD_FPR_REGS:
6281 if (x && CONSTANT_P (x) && !ZERO_P (x))
6282 ret = GPR_REGS;
6283 else
6284 ret = NO_REGS;
6285 break;
6286
6287 /* All of these types need gpr registers. */
6288 case ICC_REGS:
6289 case FCC_REGS:
6290 case CC_REGS:
6291 case ICR_REGS:
6292 case FCR_REGS:
6293 case CR_REGS:
6294 case LCR_REG:
6295 case LR_REG:
6296 ret = GPR_REGS;
6297 break;
6298
6299 /* The accumulators need fpr registers. */
6300 case QUAD_ACC_REGS:
6301 case ACCG_REGS:
6302 ret = FPR_REGS;
6303 break;
6304 }
6305
6306 return ret;
6307 }
6308
6309 /* This hook exists to catch the case where secondary_reload_class() is
6310 called from init_reg_autoinc() in regclass.c - before the reload optabs
6311 have been initialised. */
6312
6313 static reg_class_t
frv_secondary_reload(bool in_p,rtx x,reg_class_t reload_class_i,machine_mode reload_mode,secondary_reload_info * sri)6314 frv_secondary_reload (bool in_p, rtx x, reg_class_t reload_class_i,
6315 machine_mode reload_mode,
6316 secondary_reload_info * sri)
6317 {
6318 enum reg_class rclass = NO_REGS;
6319 enum reg_class reload_class = (enum reg_class) reload_class_i;
6320
6321 if (sri->prev_sri && sri->prev_sri->t_icode != CODE_FOR_nothing)
6322 {
6323 sri->icode = sri->prev_sri->t_icode;
6324 return NO_REGS;
6325 }
6326
6327 rclass = frv_secondary_reload_class (reload_class, reload_mode, x);
6328
6329 if (rclass != NO_REGS)
6330 {
6331 enum insn_code icode
6332 = direct_optab_handler (in_p ? reload_in_optab : reload_out_optab,
6333 reload_mode);
6334 if (icode == 0)
6335 {
6336 /* This happens when then the reload_[in|out]_optabs have
6337 not been initialised. */
6338 sri->t_icode = CODE_FOR_nothing;
6339 return rclass;
6340 }
6341 }
6342
6343 /* Fall back to the default secondary reload handler. */
6344 return default_secondary_reload (in_p, x, reload_class, reload_mode, sri);
6345
6346 }
6347
6348 /* Worker function for TARGET_CLASS_LIKELY_SPILLED_P. */
6349
6350 static bool
frv_class_likely_spilled_p(reg_class_t rclass)6351 frv_class_likely_spilled_p (reg_class_t rclass)
6352 {
6353 switch (rclass)
6354 {
6355 default:
6356 break;
6357
6358 case GR8_REGS:
6359 case GR9_REGS:
6360 case GR89_REGS:
6361 case FDPIC_FPTR_REGS:
6362 case FDPIC_REGS:
6363 case ICC_REGS:
6364 case FCC_REGS:
6365 case CC_REGS:
6366 case ICR_REGS:
6367 case FCR_REGS:
6368 case CR_REGS:
6369 case LCR_REG:
6370 case LR_REG:
6371 case SPR_REGS:
6372 case QUAD_ACC_REGS:
6373 case ACCG_REGS:
6374 return true;
6375 }
6376
6377 return false;
6378 }
6379
6380
6381 /* An expression for the alignment of a structure field FIELD if the
6382 alignment computed in the usual way is COMPUTED. GCC uses this
6383 value instead of the value in `BIGGEST_ALIGNMENT' or
6384 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
6385
6386 /* The definition type of the bit field data is either char, short, long or
6387 long long. The maximum bit size is the number of bits of its own type.
6388
6389 The bit field data is assigned to a storage unit that has an adequate size
6390 for bit field data retention and is located at the smallest address.
6391
6392 Consecutive bit field data are packed at consecutive bits having the same
6393 storage unit, with regard to the type, beginning with the MSB and continuing
6394 toward the LSB.
6395
6396 If a field to be assigned lies over a bit field type boundary, its
6397 assignment is completed by aligning it with a boundary suitable for the
6398 type.
6399
6400 When a bit field having a bit length of 0 is declared, it is forcibly
6401 assigned to the next storage unit.
6402
6403 e.g)
6404 struct {
6405 int a:2;
6406 int b:6;
6407 char c:4;
6408 int d:10;
6409 int :0;
6410 int f:2;
6411 } x;
6412
6413 +0 +1 +2 +3
6414 &x 00000000 00000000 00000000 00000000
6415 MLM----L
6416 a b
6417 &x+4 00000000 00000000 00000000 00000000
6418 M--L
6419 c
6420 &x+8 00000000 00000000 00000000 00000000
6421 M----------L
6422 d
6423 &x+12 00000000 00000000 00000000 00000000
6424 ML
6425 f
6426 */
6427
6428 int
frv_adjust_field_align(tree field,int computed)6429 frv_adjust_field_align (tree field, int computed)
6430 {
6431 /* Make sure that the bitfield is not wider than the type. */
6432 if (field
6433 && DECL_BIT_FIELD (field)
6434 && !DECL_ARTIFICIAL (field))
6435 {
6436 tree parent = DECL_CONTEXT (field);
6437 tree prev = NULL_TREE;
6438 tree cur;
6439
6440 for (cur = TYPE_FIELDS (parent); cur && cur != field; cur = DECL_CHAIN (cur))
6441 {
6442 if (TREE_CODE (cur) != FIELD_DECL)
6443 continue;
6444
6445 prev = cur;
6446 }
6447
6448 gcc_assert (cur);
6449
6450 /* If this isn't a :0 field and if the previous element is a bitfield
6451 also, see if the type is different, if so, we will need to align the
6452 bit-field to the next boundary. */
6453 if (prev
6454 && ! DECL_PACKED (field)
6455 && ! integer_zerop (DECL_SIZE (field))
6456 && DECL_BIT_FIELD_TYPE (field) != DECL_BIT_FIELD_TYPE (prev))
6457 {
6458 int prev_align = TYPE_ALIGN (TREE_TYPE (prev));
6459 int cur_align = TYPE_ALIGN (TREE_TYPE (field));
6460 computed = (prev_align > cur_align) ? prev_align : cur_align;
6461 }
6462 }
6463
6464 return computed;
6465 }
6466
6467
6468 /* Implement TARGET_HARD_REGNO_MODE_OK. */
6469
6470 static bool
frv_hard_regno_mode_ok(unsigned int regno,machine_mode mode)6471 frv_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
6472 {
6473 int base;
6474 int mask;
6475
6476 switch (mode)
6477 {
6478 case E_CCmode:
6479 case E_CC_UNSmode:
6480 case E_CC_NZmode:
6481 return ICC_P (regno) || GPR_P (regno);
6482
6483 case E_CC_CCRmode:
6484 return CR_P (regno) || GPR_P (regno);
6485
6486 case E_CC_FPmode:
6487 return FCC_P (regno) || GPR_P (regno);
6488
6489 default:
6490 break;
6491 }
6492
6493 /* Set BASE to the first register in REGNO's class. Set MASK to the
6494 bits that must be clear in (REGNO - BASE) for the register to be
6495 well-aligned. */
6496 if (INTEGRAL_MODE_P (mode) || FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode))
6497 {
6498 if (ACCG_P (regno))
6499 {
6500 /* ACCGs store one byte. Two-byte quantities must start in
6501 even-numbered registers, four-byte ones in registers whose
6502 numbers are divisible by four, and so on. */
6503 base = ACCG_FIRST;
6504 mask = GET_MODE_SIZE (mode) - 1;
6505 }
6506 else
6507 {
6508 /* The other registers store one word. */
6509 if (GPR_P (regno) || regno == AP_FIRST)
6510 base = GPR_FIRST;
6511
6512 else if (FPR_P (regno))
6513 base = FPR_FIRST;
6514
6515 else if (ACC_P (regno))
6516 base = ACC_FIRST;
6517
6518 else if (SPR_P (regno))
6519 return mode == SImode;
6520
6521 /* Fill in the table. */
6522 else
6523 return false;
6524
6525 /* Anything smaller than an SI is OK in any word-sized register. */
6526 if (GET_MODE_SIZE (mode) < 4)
6527 return true;
6528
6529 mask = (GET_MODE_SIZE (mode) / 4) - 1;
6530 }
6531 return (((regno - base) & mask) == 0);
6532 }
6533
6534 return false;
6535 }
6536
6537 /* Implement TARGET_MODES_TIEABLE_P. */
6538
6539 static bool
frv_modes_tieable_p(machine_mode mode1,machine_mode mode2)6540 frv_modes_tieable_p (machine_mode mode1, machine_mode mode2)
6541 {
6542 return mode1 == mode2;
6543 }
6544
6545
6546 /* Implement TARGET_HARD_REGNO_NREGS.
6547
6548 On the FRV, make the CC_FP mode take 3 words in the integer registers, so
6549 that we can build the appropriate instructions to properly reload the
6550 values. Also, make the byte-sized accumulator guards use one guard
6551 for each byte. */
6552
6553 static unsigned int
frv_hard_regno_nregs(unsigned int regno,machine_mode mode)6554 frv_hard_regno_nregs (unsigned int regno, machine_mode mode)
6555 {
6556 if (ACCG_P (regno))
6557 return GET_MODE_SIZE (mode);
6558 else
6559 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6560 }
6561
6562
6563 /* Implement CLASS_MAX_NREGS. */
6564
6565 int
frv_class_max_nregs(enum reg_class rclass,machine_mode mode)6566 frv_class_max_nregs (enum reg_class rclass, machine_mode mode)
6567 {
6568 if (rclass == ACCG_REGS)
6569 /* An N-byte value requires N accumulator guards. */
6570 return GET_MODE_SIZE (mode);
6571 else
6572 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6573 }
6574
6575
6576 /* A C expression that is nonzero if X is a legitimate constant for an
6577 immediate operand on the target machine. You can assume that X satisfies
6578 `CONSTANT_P', so you need not check this. In fact, `1' is a suitable
6579 definition for this macro on machines where anything `CONSTANT_P' is valid. */
6580
6581 static bool
frv_legitimate_constant_p(machine_mode mode,rtx x)6582 frv_legitimate_constant_p (machine_mode mode, rtx x)
6583 {
6584 /* frv_cannot_force_const_mem always returns true for FDPIC. This
6585 means that the move expanders will be expected to deal with most
6586 kinds of constant, regardless of what we return here.
6587
6588 However, among its other duties, frv_legitimate_constant_p decides whether
6589 a constant can be entered into reg_equiv_constant[]. If we return true,
6590 reload can create new instances of the constant whenever it likes.
6591
6592 The idea is therefore to accept as many constants as possible (to give
6593 reload more freedom) while rejecting constants that can only be created
6594 at certain times. In particular, anything with a symbolic component will
6595 require use of the pseudo FDPIC register, which is only available before
6596 reload. */
6597 if (TARGET_FDPIC)
6598 return LEGITIMATE_PIC_OPERAND_P (x);
6599
6600 /* All of the integer constants are ok. */
6601 if (GET_CODE (x) != CONST_DOUBLE)
6602 return TRUE;
6603
6604 /* double integer constants are ok. */
6605 if (GET_MODE (x) == VOIDmode || mode == DImode)
6606 return TRUE;
6607
6608 /* 0 is always ok. */
6609 if (x == CONST0_RTX (mode))
6610 return TRUE;
6611
6612 /* If floating point is just emulated, allow any constant, since it will be
6613 constructed in the GPRs. */
6614 if (!TARGET_HAS_FPRS)
6615 return TRUE;
6616
6617 if (mode == DFmode && !TARGET_DOUBLE)
6618 return TRUE;
6619
6620 /* Otherwise store the constant away and do a load. */
6621 return FALSE;
6622 }
6623
6624 /* Implement SELECT_CC_MODE. Choose CC_FP for floating-point comparisons,
6625 CC_NZ for comparisons against zero in which a single Z or N flag test
6626 is enough, CC_UNS for other unsigned comparisons, and CC for other
6627 signed comparisons. */
6628
6629 machine_mode
frv_select_cc_mode(enum rtx_code code,rtx x,rtx y)6630 frv_select_cc_mode (enum rtx_code code, rtx x, rtx y)
6631 {
6632 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
6633 return CC_FPmode;
6634
6635 switch (code)
6636 {
6637 case EQ:
6638 case NE:
6639 case LT:
6640 case GE:
6641 return y == const0_rtx ? CC_NZmode : CCmode;
6642
6643 case GTU:
6644 case GEU:
6645 case LTU:
6646 case LEU:
6647 return y == const0_rtx ? CC_NZmode : CC_UNSmode;
6648
6649 default:
6650 return CCmode;
6651 }
6652 }
6653
6654
6655 /* Worker function for TARGET_REGISTER_MOVE_COST. */
6656
6657 #define HIGH_COST 40
6658 #define MEDIUM_COST 3
6659 #define LOW_COST 1
6660
6661 static int
frv_register_move_cost(machine_mode mode ATTRIBUTE_UNUSED,reg_class_t from,reg_class_t to)6662 frv_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED,
6663 reg_class_t from, reg_class_t to)
6664 {
6665 switch (from)
6666 {
6667 default:
6668 break;
6669
6670 case QUAD_REGS:
6671 case GPR_REGS:
6672 case GR8_REGS:
6673 case GR9_REGS:
6674 case GR89_REGS:
6675 case FDPIC_REGS:
6676 case FDPIC_FPTR_REGS:
6677 case FDPIC_CALL_REGS:
6678 switch (to)
6679 {
6680 default:
6681 break;
6682
6683 case QUAD_REGS:
6684 case GPR_REGS:
6685 case GR8_REGS:
6686 case GR9_REGS:
6687 case GR89_REGS:
6688 case FDPIC_REGS:
6689 case FDPIC_FPTR_REGS:
6690 case FDPIC_CALL_REGS:
6691 return LOW_COST;
6692
6693 case FPR_REGS:
6694 return LOW_COST;
6695
6696 case LCR_REG:
6697 case LR_REG:
6698 case SPR_REGS:
6699 return LOW_COST;
6700 }
6701 break;
6702
6703 case QUAD_FPR_REGS:
6704 switch (to)
6705 {
6706 default:
6707 break;
6708
6709 case QUAD_REGS:
6710 case GPR_REGS:
6711 case GR8_REGS:
6712 case GR9_REGS:
6713 case GR89_REGS:
6714 case FDPIC_REGS:
6715 case FDPIC_FPTR_REGS:
6716 case FDPIC_CALL_REGS:
6717
6718 case QUAD_ACC_REGS:
6719 case ACCG_REGS:
6720 return MEDIUM_COST;
6721
6722 case QUAD_FPR_REGS:
6723 return LOW_COST;
6724 }
6725 break;
6726
6727 case LCR_REG:
6728 case LR_REG:
6729 case SPR_REGS:
6730 switch (to)
6731 {
6732 default:
6733 break;
6734
6735 case QUAD_REGS:
6736 case GPR_REGS:
6737 case GR8_REGS:
6738 case GR9_REGS:
6739 case GR89_REGS:
6740 case FDPIC_REGS:
6741 case FDPIC_FPTR_REGS:
6742 case FDPIC_CALL_REGS:
6743 return MEDIUM_COST;
6744 }
6745 break;
6746
6747 case QUAD_ACC_REGS:
6748 case ACCG_REGS:
6749 switch (to)
6750 {
6751 default:
6752 break;
6753
6754 case QUAD_FPR_REGS:
6755 return MEDIUM_COST;
6756 }
6757 break;
6758 }
6759
6760 return HIGH_COST;
6761 }
6762
6763 /* Worker function for TARGET_MEMORY_MOVE_COST. */
6764
6765 static int
frv_memory_move_cost(machine_mode mode ATTRIBUTE_UNUSED,reg_class_t rclass ATTRIBUTE_UNUSED,bool in ATTRIBUTE_UNUSED)6766 frv_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED,
6767 reg_class_t rclass ATTRIBUTE_UNUSED,
6768 bool in ATTRIBUTE_UNUSED)
6769 {
6770 return 4;
6771 }
6772
6773
6774 /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to
6775 use ".picptr" to generate safe relocations for PIC code. We also
6776 need a fixup entry for aligned (non-debugging) code. */
6777
6778 static bool
frv_assemble_integer(rtx value,unsigned int size,int aligned_p)6779 frv_assemble_integer (rtx value, unsigned int size, int aligned_p)
6780 {
6781 if ((flag_pic || TARGET_FDPIC) && size == UNITS_PER_WORD)
6782 {
6783 if (GET_CODE (value) == CONST
6784 || GET_CODE (value) == SYMBOL_REF
6785 || GET_CODE (value) == LABEL_REF)
6786 {
6787 if (TARGET_FDPIC && GET_CODE (value) == SYMBOL_REF
6788 && SYMBOL_REF_FUNCTION_P (value))
6789 {
6790 fputs ("\t.picptr\tfuncdesc(", asm_out_file);
6791 output_addr_const (asm_out_file, value);
6792 fputs (")\n", asm_out_file);
6793 return true;
6794 }
6795 else if (TARGET_FDPIC && GET_CODE (value) == CONST
6796 && frv_function_symbol_referenced_p (value))
6797 return false;
6798 if (aligned_p && !TARGET_FDPIC)
6799 {
6800 static int label_num = 0;
6801 char buf[256];
6802 const char *p;
6803
6804 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", label_num++);
6805 p = (* targetm.strip_name_encoding) (buf);
6806
6807 fprintf (asm_out_file, "%s:\n", p);
6808 fprintf (asm_out_file, "%s\n", FIXUP_SECTION_ASM_OP);
6809 fprintf (asm_out_file, "\t.picptr\t%s\n", p);
6810 fprintf (asm_out_file, "\t.previous\n");
6811 }
6812 assemble_integer_with_op ("\t.picptr\t", value);
6813 return true;
6814 }
6815 if (!aligned_p)
6816 {
6817 /* We've set the unaligned SI op to NULL, so we always have to
6818 handle the unaligned case here. */
6819 assemble_integer_with_op ("\t.4byte\t", value);
6820 return true;
6821 }
6822 }
6823 return default_assemble_integer (value, size, aligned_p);
6824 }
6825
6826 /* Function to set up the backend function structure. */
6827
6828 static struct machine_function *
frv_init_machine_status(void)6829 frv_init_machine_status (void)
6830 {
6831 return ggc_cleared_alloc<machine_function> ();
6832 }
6833
6834 /* Implement TARGET_SCHED_ISSUE_RATE. */
6835
6836 int
frv_issue_rate(void)6837 frv_issue_rate (void)
6838 {
6839 if (!TARGET_PACK)
6840 return 1;
6841
6842 switch (frv_cpu_type)
6843 {
6844 default:
6845 case FRV_CPU_FR300:
6846 case FRV_CPU_SIMPLE:
6847 return 1;
6848
6849 case FRV_CPU_FR400:
6850 case FRV_CPU_FR405:
6851 case FRV_CPU_FR450:
6852 return 2;
6853
6854 case FRV_CPU_GENERIC:
6855 case FRV_CPU_FR500:
6856 case FRV_CPU_TOMCAT:
6857 return 4;
6858
6859 case FRV_CPU_FR550:
6860 return 8;
6861 }
6862 }
6863
6864 /* Return the value of INSN's acc_group attribute. */
6865
6866 int
frv_acc_group(rtx insn)6867 frv_acc_group (rtx insn)
6868 {
6869 /* This distinction only applies to the FR550 packing constraints. */
6870 if (frv_cpu_type == FRV_CPU_FR550)
6871 {
6872 subrtx_iterator::array_type array;
6873 FOR_EACH_SUBRTX (iter, array, PATTERN (insn), NONCONST)
6874 if (REG_P (*iter))
6875 {
6876 unsigned int regno = REGNO (*iter);
6877 /* If REGNO refers to an accumulator, return ACC_GROUP_ODD if
6878 the bit 2 of the register number is set and ACC_GROUP_EVEN if
6879 it is clear. */
6880 if (ACC_P (regno))
6881 return (regno - ACC_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
6882 if (ACCG_P (regno))
6883 return (regno - ACCG_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
6884 }
6885 }
6886 return ACC_GROUP_NONE;
6887 }
6888
6889 /* Return the index of the DFA unit in FRV_UNIT_NAMES[] that instruction
6890 INSN will try to claim first. Since this value depends only on the
6891 type attribute, we can cache the results in FRV_TYPE_TO_UNIT[]. */
6892
6893 static unsigned int
frv_insn_unit(rtx_insn * insn)6894 frv_insn_unit (rtx_insn *insn)
6895 {
6896 enum attr_type type;
6897
6898 type = get_attr_type (insn);
6899 if (frv_type_to_unit[type] == ARRAY_SIZE (frv_unit_codes))
6900 {
6901 /* We haven't seen this type of instruction before. */
6902 state_t state;
6903 unsigned int unit;
6904
6905 /* Issue the instruction on its own to see which unit it prefers. */
6906 state = alloca (state_size ());
6907 state_reset (state);
6908 state_transition (state, insn);
6909
6910 /* Find out which unit was taken. */
6911 for (unit = 0; unit < ARRAY_SIZE (frv_unit_codes); unit++)
6912 if (cpu_unit_reservation_p (state, frv_unit_codes[unit]))
6913 break;
6914
6915 gcc_assert (unit != ARRAY_SIZE (frv_unit_codes));
6916
6917 frv_type_to_unit[type] = unit;
6918 }
6919 return frv_type_to_unit[type];
6920 }
6921
6922 /* Return true if INSN issues to a branch unit. */
6923
6924 static bool
frv_issues_to_branch_unit_p(rtx_insn * insn)6925 frv_issues_to_branch_unit_p (rtx_insn *insn)
6926 {
6927 return frv_unit_groups[frv_insn_unit (insn)] == GROUP_B;
6928 }
6929
6930 /* The instructions in the packet, partitioned into groups. */
6931 struct frv_packet_group {
6932 /* How many instructions in the packet belong to this group. */
6933 unsigned int num_insns;
6934
6935 /* A list of the instructions that belong to this group, in the order
6936 they appear in the rtl stream. */
6937 rtx_insn *insns[ARRAY_SIZE (frv_unit_codes)];
6938
6939 /* The contents of INSNS after they have been sorted into the correct
6940 assembly-language order. Element X issues to unit X. The list may
6941 contain extra nops. */
6942 rtx_insn *sorted[ARRAY_SIZE (frv_unit_codes)];
6943
6944 /* The member of frv_nops[] to use in sorted[]. */
6945 rtx_insn *nop;
6946 };
6947
6948 /* The current state of the packing pass, implemented by frv_pack_insns. */
6949 static struct {
6950 /* The state of the pipeline DFA. */
6951 state_t dfa_state;
6952
6953 /* Which hardware registers are set within the current packet,
6954 and the conditions under which they are set. */
6955 regstate_t regstate[FIRST_PSEUDO_REGISTER];
6956
6957 /* The memory locations that have been modified so far in this
6958 packet. MEM is the memref and COND is the regstate_t condition
6959 under which it is set. */
6960 struct {
6961 rtx mem;
6962 regstate_t cond;
6963 } mems[2];
6964
6965 /* The number of valid entries in MEMS. The value is larger than
6966 ARRAY_SIZE (mems) if there were too many mems to record. */
6967 unsigned int num_mems;
6968
6969 /* The maximum number of instructions that can be packed together. */
6970 unsigned int issue_rate;
6971
6972 /* The instructions in the packet, partitioned into groups. */
6973 struct frv_packet_group groups[NUM_GROUPS];
6974
6975 /* The instructions that make up the current packet. */
6976 rtx_insn *insns[ARRAY_SIZE (frv_unit_codes)];
6977 unsigned int num_insns;
6978 } frv_packet;
6979
6980 /* Return the regstate_t flags for the given COND_EXEC condition.
6981 Abort if the condition isn't in the right form. */
6982
6983 static int
frv_cond_flags(rtx cond)6984 frv_cond_flags (rtx cond)
6985 {
6986 gcc_assert ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
6987 && GET_CODE (XEXP (cond, 0)) == REG
6988 && CR_P (REGNO (XEXP (cond, 0)))
6989 && XEXP (cond, 1) == const0_rtx);
6990 return ((REGNO (XEXP (cond, 0)) - CR_FIRST)
6991 | (GET_CODE (cond) == NE
6992 ? REGSTATE_IF_TRUE
6993 : REGSTATE_IF_FALSE));
6994 }
6995
6996
6997 /* Return true if something accessed under condition COND2 can
6998 conflict with something written under condition COND1. */
6999
7000 static bool
frv_regstate_conflict_p(regstate_t cond1,regstate_t cond2)7001 frv_regstate_conflict_p (regstate_t cond1, regstate_t cond2)
7002 {
7003 /* If either reference was unconditional, we have a conflict. */
7004 if ((cond1 & REGSTATE_IF_EITHER) == 0
7005 || (cond2 & REGSTATE_IF_EITHER) == 0)
7006 return true;
7007
7008 /* The references might conflict if they were controlled by
7009 different CRs. */
7010 if ((cond1 & REGSTATE_CC_MASK) != (cond2 & REGSTATE_CC_MASK))
7011 return true;
7012
7013 /* They definitely conflict if they are controlled by the
7014 same condition. */
7015 if ((cond1 & cond2 & REGSTATE_IF_EITHER) != 0)
7016 return true;
7017
7018 return false;
7019 }
7020
7021
7022 /* Return true if an instruction with pattern PAT depends on an
7023 instruction in the current packet. COND describes the condition
7024 under which PAT might be set or used. */
7025
7026 static bool
frv_registers_conflict_p_1(rtx pat,regstate_t cond)7027 frv_registers_conflict_p_1 (rtx pat, regstate_t cond)
7028 {
7029 subrtx_var_iterator::array_type array;
7030 FOR_EACH_SUBRTX_VAR (iter, array, pat, NONCONST)
7031 {
7032 rtx x = *iter;
7033 if (GET_CODE (x) == REG)
7034 {
7035 unsigned int regno;
7036 FOR_EACH_REGNO (regno, x)
7037 if ((frv_packet.regstate[regno] & REGSTATE_MODIFIED) != 0)
7038 if (frv_regstate_conflict_p (frv_packet.regstate[regno], cond))
7039 return true;
7040 }
7041 else if (GET_CODE (x) == MEM)
7042 {
7043 /* If we ran out of memory slots, assume a conflict. */
7044 if (frv_packet.num_mems > ARRAY_SIZE (frv_packet.mems))
7045 return 1;
7046
7047 /* Check for output or true dependencies with earlier MEMs. */
7048 for (unsigned int i = 0; i < frv_packet.num_mems; i++)
7049 if (frv_regstate_conflict_p (frv_packet.mems[i].cond, cond))
7050 {
7051 if (true_dependence (frv_packet.mems[i].mem, VOIDmode, x))
7052 return true;
7053
7054 if (output_dependence (frv_packet.mems[i].mem, x))
7055 return true;
7056 }
7057 }
7058
7059 /* The return values of calls aren't significant: they describe
7060 the effect of the call as a whole, not of the insn itself. */
7061 else if (GET_CODE (x) == SET && GET_CODE (SET_SRC (x)) == CALL)
7062 iter.substitute (SET_SRC (x));
7063 }
7064 return false;
7065 }
7066
7067
7068 /* Return true if something in X might depend on an instruction
7069 in the current packet. */
7070
7071 static bool
frv_registers_conflict_p(rtx x)7072 frv_registers_conflict_p (rtx x)
7073 {
7074 regstate_t flags;
7075
7076 flags = 0;
7077 if (GET_CODE (x) == COND_EXEC)
7078 {
7079 if (frv_registers_conflict_p_1 (XEXP (x, 0), flags))
7080 return true;
7081
7082 flags |= frv_cond_flags (XEXP (x, 0));
7083 x = XEXP (x, 1);
7084 }
7085 return frv_registers_conflict_p_1 (x, flags);
7086 }
7087
7088
7089 /* A note_stores callback. DATA points to the regstate_t condition
7090 under which X is modified. Update FRV_PACKET accordingly. */
7091
7092 static void
frv_registers_update_1(rtx x,const_rtx pat ATTRIBUTE_UNUSED,void * data)7093 frv_registers_update_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7094 {
7095 unsigned int regno;
7096
7097 if (GET_CODE (x) == REG)
7098 FOR_EACH_REGNO (regno, x)
7099 frv_packet.regstate[regno] |= *(regstate_t *) data;
7100
7101 if (GET_CODE (x) == MEM)
7102 {
7103 if (frv_packet.num_mems < ARRAY_SIZE (frv_packet.mems))
7104 {
7105 frv_packet.mems[frv_packet.num_mems].mem = x;
7106 frv_packet.mems[frv_packet.num_mems].cond = *(regstate_t *) data;
7107 }
7108 frv_packet.num_mems++;
7109 }
7110 }
7111
7112
7113 /* Update the register state information for an instruction whose
7114 body is X. */
7115
7116 static void
frv_registers_update(rtx x)7117 frv_registers_update (rtx x)
7118 {
7119 regstate_t flags;
7120
7121 flags = REGSTATE_MODIFIED;
7122 if (GET_CODE (x) == COND_EXEC)
7123 {
7124 flags |= frv_cond_flags (XEXP (x, 0));
7125 x = XEXP (x, 1);
7126 }
7127 note_pattern_stores (x, frv_registers_update_1, &flags);
7128 }
7129
7130
7131 /* Initialize frv_packet for the start of a new packet. */
7132
7133 static void
frv_start_packet(void)7134 frv_start_packet (void)
7135 {
7136 enum frv_insn_group group;
7137
7138 memset (frv_packet.regstate, 0, sizeof (frv_packet.regstate));
7139 frv_packet.num_mems = 0;
7140 frv_packet.num_insns = 0;
7141 for (group = GROUP_I; group < NUM_GROUPS;
7142 group = (enum frv_insn_group) (group + 1))
7143 frv_packet.groups[group].num_insns = 0;
7144 }
7145
7146
7147 /* Likewise for the start of a new basic block. */
7148
7149 static void
frv_start_packet_block(void)7150 frv_start_packet_block (void)
7151 {
7152 state_reset (frv_packet.dfa_state);
7153 frv_start_packet ();
7154 }
7155
7156
7157 /* Finish the current packet, if any, and start a new one. Call
7158 HANDLE_PACKET with FRV_PACKET describing the completed packet. */
7159
7160 static void
frv_finish_packet(void (* handle_packet)(void))7161 frv_finish_packet (void (*handle_packet) (void))
7162 {
7163 if (frv_packet.num_insns > 0)
7164 {
7165 handle_packet ();
7166 state_transition (frv_packet.dfa_state, 0);
7167 frv_start_packet ();
7168 }
7169 }
7170
7171
7172 /* Return true if INSN can be added to the current packet. Update
7173 the DFA state on success. */
7174
7175 static bool
frv_pack_insn_p(rtx_insn * insn)7176 frv_pack_insn_p (rtx_insn *insn)
7177 {
7178 /* See if the packet is already as long as it can be. */
7179 if (frv_packet.num_insns == frv_packet.issue_rate)
7180 return false;
7181
7182 /* If the scheduler thought that an instruction should start a packet,
7183 it's usually a good idea to believe it. It knows much more about
7184 the latencies than we do.
7185
7186 There are some exceptions though:
7187
7188 - Conditional instructions are scheduled on the assumption that
7189 they will be executed. This is usually a good thing, since it
7190 tends to avoid unnecessary stalls in the conditional code.
7191 But we want to pack conditional instructions as tightly as
7192 possible, in order to optimize the case where they aren't
7193 executed.
7194
7195 - The scheduler will always put branches on their own, even
7196 if there's no real dependency.
7197
7198 - There's no point putting a call in its own packet unless
7199 we have to. */
7200 if (frv_packet.num_insns > 0
7201 && NONJUMP_INSN_P (insn)
7202 && GET_MODE (insn) == TImode
7203 && GET_CODE (PATTERN (insn)) != COND_EXEC)
7204 return false;
7205
7206 /* Check for register conflicts. Don't do this for setlo since any
7207 conflict will be with the partnering sethi, with which it can
7208 be packed. */
7209 if (get_attr_type (insn) != TYPE_SETLO)
7210 if (frv_registers_conflict_p (PATTERN (insn)))
7211 return false;
7212
7213 return state_transition (frv_packet.dfa_state, insn) < 0;
7214 }
7215
7216
7217 /* Add instruction INSN to the current packet. */
7218
7219 static void
frv_add_insn_to_packet(rtx_insn * insn)7220 frv_add_insn_to_packet (rtx_insn *insn)
7221 {
7222 struct frv_packet_group *packet_group;
7223
7224 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
7225 packet_group->insns[packet_group->num_insns++] = insn;
7226 frv_packet.insns[frv_packet.num_insns++] = insn;
7227
7228 frv_registers_update (PATTERN (insn));
7229 }
7230
7231
7232 /* Insert INSN (a member of frv_nops[]) into the current packet. If the
7233 packet ends in a branch or call, insert the nop before it, otherwise
7234 add to the end. */
7235
7236 static void
frv_insert_nop_in_packet(rtx_insn * insn)7237 frv_insert_nop_in_packet (rtx_insn *insn)
7238 {
7239 struct frv_packet_group *packet_group;
7240 rtx_insn *last;
7241
7242 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
7243 last = frv_packet.insns[frv_packet.num_insns - 1];
7244 if (! NONJUMP_INSN_P (last))
7245 {
7246 insn = emit_insn_before (PATTERN (insn), last);
7247 frv_packet.insns[frv_packet.num_insns - 1] = insn;
7248 frv_packet.insns[frv_packet.num_insns++] = last;
7249 }
7250 else
7251 {
7252 insn = emit_insn_after (PATTERN (insn), last);
7253 frv_packet.insns[frv_packet.num_insns++] = insn;
7254 }
7255 packet_group->insns[packet_group->num_insns++] = insn;
7256 }
7257
7258
7259 /* If packing is enabled, divide the instructions into packets and
7260 return true. Call HANDLE_PACKET for each complete packet. */
7261
7262 static bool
frv_for_each_packet(void (* handle_packet)(void))7263 frv_for_each_packet (void (*handle_packet) (void))
7264 {
7265 rtx_insn *insn, *next_insn;
7266
7267 frv_packet.issue_rate = frv_issue_rate ();
7268
7269 /* Early exit if we don't want to pack insns. */
7270 if (!optimize
7271 || !flag_schedule_insns_after_reload
7272 || !TARGET_VLIW_BRANCH
7273 || frv_packet.issue_rate == 1)
7274 return false;
7275
7276 /* Set up the initial packing state. */
7277 dfa_start ();
7278 frv_packet.dfa_state = alloca (state_size ());
7279
7280 frv_start_packet_block ();
7281 for (insn = get_insns (); insn != 0; insn = next_insn)
7282 {
7283 enum rtx_code code;
7284 bool eh_insn_p;
7285
7286 code = GET_CODE (insn);
7287 next_insn = NEXT_INSN (insn);
7288
7289 if (code == CODE_LABEL)
7290 {
7291 frv_finish_packet (handle_packet);
7292 frv_start_packet_block ();
7293 }
7294
7295 if (INSN_P (insn))
7296 switch (GET_CODE (PATTERN (insn)))
7297 {
7298 case USE:
7299 case CLOBBER:
7300 break;
7301
7302 default:
7303 /* Calls mustn't be packed on a TOMCAT. */
7304 if (CALL_P (insn) && frv_cpu_type == FRV_CPU_TOMCAT)
7305 frv_finish_packet (handle_packet);
7306
7307 /* Since the last instruction in a packet determines the EH
7308 region, any exception-throwing instruction must come at
7309 the end of reordered packet. Insns that issue to a
7310 branch unit are bound to come last; for others it's
7311 too hard to predict. */
7312 eh_insn_p = (find_reg_note (insn, REG_EH_REGION, NULL) != NULL);
7313 if (eh_insn_p && !frv_issues_to_branch_unit_p (insn))
7314 frv_finish_packet (handle_packet);
7315
7316 /* Finish the current packet if we can't add INSN to it.
7317 Simulate cycles until INSN is ready to issue. */
7318 if (!frv_pack_insn_p (insn))
7319 {
7320 frv_finish_packet (handle_packet);
7321 while (!frv_pack_insn_p (insn))
7322 state_transition (frv_packet.dfa_state, 0);
7323 }
7324
7325 /* Add the instruction to the packet. */
7326 frv_add_insn_to_packet (insn);
7327
7328 /* Calls and jumps end a packet, as do insns that throw
7329 an exception. */
7330 if (code == CALL_INSN || code == JUMP_INSN || eh_insn_p)
7331 frv_finish_packet (handle_packet);
7332 break;
7333 }
7334 }
7335 frv_finish_packet (handle_packet);
7336 dfa_finish ();
7337 return true;
7338 }
7339
7340 /* Subroutine of frv_sort_insn_group. We are trying to sort
7341 frv_packet.groups[GROUP].sorted[0...NUM_INSNS-1] into assembly
7342 language order. We have already picked a new position for
7343 frv_packet.groups[GROUP].sorted[X] if bit X of ISSUED is set.
7344 These instructions will occupy elements [0, LOWER_SLOT) and
7345 [UPPER_SLOT, NUM_INSNS) of the final (sorted) array. STATE is
7346 the DFA state after issuing these instructions.
7347
7348 Try filling elements [LOWER_SLOT, UPPER_SLOT) with every permutation
7349 of the unused instructions. Return true if one such permutation gives
7350 a valid ordering, leaving the successful permutation in sorted[].
7351 Do not modify sorted[] until a valid permutation is found. */
7352
7353 static bool
frv_sort_insn_group_1(enum frv_insn_group group,unsigned int lower_slot,unsigned int upper_slot,unsigned int issued,unsigned int num_insns,state_t state)7354 frv_sort_insn_group_1 (enum frv_insn_group group,
7355 unsigned int lower_slot, unsigned int upper_slot,
7356 unsigned int issued, unsigned int num_insns,
7357 state_t state)
7358 {
7359 struct frv_packet_group *packet_group;
7360 unsigned int i;
7361 state_t test_state;
7362 size_t dfa_size;
7363 rtx_insn *insn;
7364
7365 /* Early success if we've filled all the slots. */
7366 if (lower_slot == upper_slot)
7367 return true;
7368
7369 packet_group = &frv_packet.groups[group];
7370 dfa_size = state_size ();
7371 test_state = alloca (dfa_size);
7372
7373 /* Try issuing each unused instruction. */
7374 for (i = num_insns - 1; i + 1 != 0; i--)
7375 if (~issued & (1 << i))
7376 {
7377 insn = packet_group->sorted[i];
7378 memcpy (test_state, state, dfa_size);
7379 if (state_transition (test_state, insn) < 0
7380 && cpu_unit_reservation_p (test_state,
7381 NTH_UNIT (group, upper_slot - 1))
7382 && frv_sort_insn_group_1 (group, lower_slot, upper_slot - 1,
7383 issued | (1 << i), num_insns,
7384 test_state))
7385 {
7386 packet_group->sorted[upper_slot - 1] = insn;
7387 return true;
7388 }
7389 }
7390
7391 return false;
7392 }
7393
7394 /* Compare two instructions by their frv_insn_unit. */
7395
7396 static int
frv_compare_insns(const void * first,const void * second)7397 frv_compare_insns (const void *first, const void *second)
7398 {
7399 rtx_insn * const *insn1 = (rtx_insn * const *) first;
7400 rtx_insn * const *insn2 = (rtx_insn * const *) second;
7401 return frv_insn_unit (*insn1) - frv_insn_unit (*insn2);
7402 }
7403
7404 /* Copy frv_packet.groups[GROUP].insns[] to frv_packet.groups[GROUP].sorted[]
7405 and sort it into assembly language order. See frv.md for a description of
7406 the algorithm. */
7407
7408 static void
frv_sort_insn_group(enum frv_insn_group group)7409 frv_sort_insn_group (enum frv_insn_group group)
7410 {
7411 struct frv_packet_group *packet_group;
7412 unsigned int first, i, nop, max_unit, num_slots;
7413 state_t state, test_state;
7414 size_t dfa_size;
7415
7416 packet_group = &frv_packet.groups[group];
7417
7418 /* Assume no nop is needed. */
7419 packet_group->nop = 0;
7420
7421 if (packet_group->num_insns == 0)
7422 return;
7423
7424 /* Copy insns[] to sorted[]. */
7425 memcpy (packet_group->sorted, packet_group->insns,
7426 sizeof (rtx) * packet_group->num_insns);
7427
7428 /* Sort sorted[] by the unit that each insn tries to take first. */
7429 if (packet_group->num_insns > 1)
7430 qsort (packet_group->sorted, packet_group->num_insns,
7431 sizeof (rtx), frv_compare_insns);
7432
7433 /* That's always enough for branch and control insns. */
7434 if (group == GROUP_B || group == GROUP_C)
7435 return;
7436
7437 dfa_size = state_size ();
7438 state = alloca (dfa_size);
7439 test_state = alloca (dfa_size);
7440
7441 /* Find the highest FIRST such that sorted[0...FIRST-1] can issue
7442 consecutively and such that the DFA takes unit X when sorted[X]
7443 is added. Set STATE to the new DFA state. */
7444 state_reset (test_state);
7445 for (first = 0; first < packet_group->num_insns; first++)
7446 {
7447 memcpy (state, test_state, dfa_size);
7448 if (state_transition (test_state, packet_group->sorted[first]) >= 0
7449 || !cpu_unit_reservation_p (test_state, NTH_UNIT (group, first)))
7450 break;
7451 }
7452
7453 /* If all the instructions issued in ascending order, we're done. */
7454 if (first == packet_group->num_insns)
7455 return;
7456
7457 /* Add nops to the end of sorted[] and try each permutation until
7458 we find one that works. */
7459 for (nop = 0; nop < frv_num_nops; nop++)
7460 {
7461 max_unit = frv_insn_unit (frv_nops[nop]);
7462 if (frv_unit_groups[max_unit] == group)
7463 {
7464 packet_group->nop = frv_nops[nop];
7465 num_slots = UNIT_NUMBER (max_unit) + 1;
7466 for (i = packet_group->num_insns; i < num_slots; i++)
7467 packet_group->sorted[i] = frv_nops[nop];
7468 if (frv_sort_insn_group_1 (group, first, num_slots,
7469 (1 << first) - 1, num_slots, state))
7470 return;
7471 }
7472 }
7473 gcc_unreachable ();
7474 }
7475
7476 /* Sort the current packet into assembly-language order. Set packing
7477 flags as appropriate. */
7478
7479 static void
frv_reorder_packet(void)7480 frv_reorder_packet (void)
7481 {
7482 unsigned int cursor[NUM_GROUPS];
7483 rtx_insn *insns[ARRAY_SIZE (frv_unit_groups)];
7484 unsigned int unit, to, from;
7485 enum frv_insn_group group;
7486 struct frv_packet_group *packet_group;
7487
7488 /* First sort each group individually. */
7489 for (group = GROUP_I; group < NUM_GROUPS;
7490 group = (enum frv_insn_group) (group + 1))
7491 {
7492 cursor[group] = 0;
7493 frv_sort_insn_group (group);
7494 }
7495
7496 /* Go through the unit template and try add an instruction from
7497 that unit's group. */
7498 to = 0;
7499 for (unit = 0; unit < ARRAY_SIZE (frv_unit_groups); unit++)
7500 {
7501 group = frv_unit_groups[unit];
7502 packet_group = &frv_packet.groups[group];
7503 if (cursor[group] < packet_group->num_insns)
7504 {
7505 /* frv_reorg should have added nops for us. */
7506 gcc_assert (packet_group->sorted[cursor[group]]
7507 != packet_group->nop);
7508 insns[to++] = packet_group->sorted[cursor[group]++];
7509 }
7510 }
7511
7512 gcc_assert (to == frv_packet.num_insns);
7513
7514 /* Clear the last instruction's packing flag, thus marking the end of
7515 a packet. Reorder the other instructions relative to it. */
7516 CLEAR_PACKING_FLAG (insns[to - 1]);
7517 for (from = 0; from < to - 1; from++)
7518 {
7519 remove_insn (insns[from]);
7520 add_insn_before (insns[from], insns[to - 1], NULL);
7521 SET_PACKING_FLAG (insns[from]);
7522 }
7523 }
7524
7525
7526 /* Divide instructions into packets. Reorder the contents of each
7527 packet so that they are in the correct assembly-language order.
7528
7529 Since this pass can change the raw meaning of the rtl stream, it must
7530 only be called at the last minute, just before the instructions are
7531 written out. */
7532
7533 static void
frv_pack_insns(void)7534 frv_pack_insns (void)
7535 {
7536 if (frv_for_each_packet (frv_reorder_packet))
7537 frv_insn_packing_flag = 0;
7538 else
7539 frv_insn_packing_flag = -1;
7540 }
7541
7542 /* See whether we need to add nops to group GROUP in order to
7543 make a valid packet. */
7544
7545 static void
frv_fill_unused_units(enum frv_insn_group group)7546 frv_fill_unused_units (enum frv_insn_group group)
7547 {
7548 unsigned int non_nops, nops, i;
7549 struct frv_packet_group *packet_group;
7550
7551 packet_group = &frv_packet.groups[group];
7552
7553 /* Sort the instructions into assembly-language order.
7554 Use nops to fill slots that are otherwise unused. */
7555 frv_sort_insn_group (group);
7556
7557 /* See how many nops are needed before the final useful instruction. */
7558 i = nops = 0;
7559 for (non_nops = 0; non_nops < packet_group->num_insns; non_nops++)
7560 while (packet_group->sorted[i++] == packet_group->nop)
7561 nops++;
7562
7563 /* Insert that many nops into the instruction stream. */
7564 while (nops-- > 0)
7565 frv_insert_nop_in_packet (packet_group->nop);
7566 }
7567
7568 /* Return true if accesses IO1 and IO2 refer to the same doubleword. */
7569
7570 static bool
frv_same_doubleword_p(const struct frv_io * io1,const struct frv_io * io2)7571 frv_same_doubleword_p (const struct frv_io *io1, const struct frv_io *io2)
7572 {
7573 if (io1->const_address != 0 && io2->const_address != 0)
7574 return io1->const_address == io2->const_address;
7575
7576 if (io1->var_address != 0 && io2->var_address != 0)
7577 return rtx_equal_p (io1->var_address, io2->var_address);
7578
7579 return false;
7580 }
7581
7582 /* Return true if operations IO1 and IO2 are guaranteed to complete
7583 in order. */
7584
7585 static bool
frv_io_fixed_order_p(const struct frv_io * io1,const struct frv_io * io2)7586 frv_io_fixed_order_p (const struct frv_io *io1, const struct frv_io *io2)
7587 {
7588 /* The order of writes is always preserved. */
7589 if (io1->type == FRV_IO_WRITE && io2->type == FRV_IO_WRITE)
7590 return true;
7591
7592 /* The order of reads isn't preserved. */
7593 if (io1->type != FRV_IO_WRITE && io2->type != FRV_IO_WRITE)
7594 return false;
7595
7596 /* One operation is a write and the other is (or could be) a read.
7597 The order is only guaranteed if the accesses are to the same
7598 doubleword. */
7599 return frv_same_doubleword_p (io1, io2);
7600 }
7601
7602 /* Generalize I/O operation X so that it covers both X and Y. */
7603
7604 static void
frv_io_union(struct frv_io * x,const struct frv_io * y)7605 frv_io_union (struct frv_io *x, const struct frv_io *y)
7606 {
7607 if (x->type != y->type)
7608 x->type = FRV_IO_UNKNOWN;
7609 if (!frv_same_doubleword_p (x, y))
7610 {
7611 x->const_address = 0;
7612 x->var_address = 0;
7613 }
7614 }
7615
7616 /* Fill IO with information about the load or store associated with
7617 membar instruction INSN. */
7618
7619 static void
frv_extract_membar(struct frv_io * io,rtx_insn * insn)7620 frv_extract_membar (struct frv_io *io, rtx_insn *insn)
7621 {
7622 extract_insn (insn);
7623 io->type = (enum frv_io_type) INTVAL (recog_data.operand[2]);
7624 io->const_address = INTVAL (recog_data.operand[1]);
7625 io->var_address = XEXP (recog_data.operand[0], 0);
7626 }
7627
7628 /* A note_stores callback for which DATA points to an rtx. Nullify *DATA
7629 if X is a register and *DATA depends on X. */
7630
7631 static void
frv_io_check_address(rtx x,const_rtx pat ATTRIBUTE_UNUSED,void * data)7632 frv_io_check_address (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7633 {
7634 rtx *other = (rtx *) data;
7635
7636 if (REG_P (x) && *other != 0 && reg_overlap_mentioned_p (x, *other))
7637 *other = 0;
7638 }
7639
7640 /* A note_stores callback for which DATA points to a HARD_REG_SET.
7641 Remove every modified register from the set. */
7642
7643 static void
frv_io_handle_set(rtx x,const_rtx pat ATTRIBUTE_UNUSED,void * data)7644 frv_io_handle_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7645 {
7646 HARD_REG_SET *set = (HARD_REG_SET *) data;
7647 unsigned int regno;
7648
7649 if (REG_P (x))
7650 FOR_EACH_REGNO (regno, x)
7651 CLEAR_HARD_REG_BIT (*set, regno);
7652 }
7653
7654 /* A note_uses callback that adds all registers in *X to hard register
7655 set *DATA. */
7656
7657 static void
frv_io_handle_use(rtx * x,void * data)7658 frv_io_handle_use (rtx *x, void *data)
7659 {
7660 find_all_hard_regs (*x, (HARD_REG_SET *) data);
7661 }
7662
7663 /* Go through block BB looking for membars to remove. There are two
7664 cases where intra-block analysis is enough:
7665
7666 - a membar is redundant if it occurs between two consecutive I/O
7667 operations and if those operations are guaranteed to complete
7668 in order.
7669
7670 - a membar for a __builtin_read is redundant if the result is
7671 used before the next I/O operation is issued.
7672
7673 If the last membar in the block could not be removed, and there
7674 are guaranteed to be no I/O operations between that membar and
7675 the end of the block, store the membar in *LAST_MEMBAR, otherwise
7676 store null.
7677
7678 Describe the block's first I/O operation in *NEXT_IO. Describe
7679 an unknown operation if the block doesn't do any I/O. */
7680
7681 static void
frv_optimize_membar_local(basic_block bb,struct frv_io * next_io,rtx_insn ** last_membar)7682 frv_optimize_membar_local (basic_block bb, struct frv_io *next_io,
7683 rtx_insn **last_membar)
7684 {
7685 HARD_REG_SET used_regs;
7686 rtx set;
7687 rtx_insn *insn, *next_membar;
7688 bool next_is_end_p;
7689
7690 /* NEXT_IO is the next I/O operation to be performed after the current
7691 instruction. It starts off as being an unknown operation. */
7692 memset (next_io, 0, sizeof (*next_io));
7693
7694 /* NEXT_IS_END_P is true if NEXT_IO describes the end of the block. */
7695 next_is_end_p = true;
7696
7697 /* If the current instruction is a __builtin_read or __builtin_write,
7698 NEXT_MEMBAR is the membar instruction associated with it. NEXT_MEMBAR
7699 is null if the membar has already been deleted.
7700
7701 Note that the initialization here should only be needed to
7702 suppress warnings. */
7703 next_membar = 0;
7704
7705 /* USED_REGS is the set of registers that are used before the
7706 next I/O instruction. */
7707 CLEAR_HARD_REG_SET (used_regs);
7708
7709 for (insn = BB_END (bb); insn != BB_HEAD (bb); insn = PREV_INSN (insn))
7710 if (CALL_P (insn))
7711 {
7712 /* We can't predict what a call will do to volatile memory. */
7713 memset (next_io, 0, sizeof (struct frv_io));
7714 next_is_end_p = false;
7715 CLEAR_HARD_REG_SET (used_regs);
7716 }
7717 else if (INSN_P (insn))
7718 switch (recog_memoized (insn))
7719 {
7720 case CODE_FOR_optional_membar_qi:
7721 case CODE_FOR_optional_membar_hi:
7722 case CODE_FOR_optional_membar_si:
7723 case CODE_FOR_optional_membar_di:
7724 next_membar = insn;
7725 if (next_is_end_p)
7726 {
7727 /* Local information isn't enough to decide whether this
7728 membar is needed. Stash it away for later. */
7729 *last_membar = insn;
7730 frv_extract_membar (next_io, insn);
7731 next_is_end_p = false;
7732 }
7733 else
7734 {
7735 /* Check whether the I/O operation before INSN could be
7736 reordered with one described by NEXT_IO. If it can't,
7737 INSN will not be needed. */
7738 struct frv_io prev_io;
7739
7740 frv_extract_membar (&prev_io, insn);
7741 if (frv_io_fixed_order_p (&prev_io, next_io))
7742 {
7743 if (dump_file)
7744 fprintf (dump_file,
7745 ";; [Local] Removing membar %d since order"
7746 " of accesses is guaranteed\n",
7747 INSN_UID (next_membar));
7748
7749 insn = NEXT_INSN (insn);
7750 delete_insn (next_membar);
7751 next_membar = 0;
7752 }
7753 *next_io = prev_io;
7754 }
7755 break;
7756
7757 default:
7758 /* Invalidate NEXT_IO's address if it depends on something that
7759 is clobbered by INSN. */
7760 if (next_io->var_address)
7761 note_stores (insn, frv_io_check_address, &next_io->var_address);
7762
7763 /* If the next membar is associated with a __builtin_read,
7764 see if INSN reads from that address. If it does, and if
7765 the destination register is used before the next I/O access,
7766 there is no need for the membar. */
7767 set = PATTERN (insn);
7768 if (next_io->type == FRV_IO_READ
7769 && next_io->var_address != 0
7770 && next_membar != 0
7771 && GET_CODE (set) == SET
7772 && GET_CODE (SET_DEST (set)) == REG
7773 && TEST_HARD_REG_BIT (used_regs, REGNO (SET_DEST (set))))
7774 {
7775 rtx src;
7776
7777 src = SET_SRC (set);
7778 if (GET_CODE (src) == ZERO_EXTEND)
7779 src = XEXP (src, 0);
7780
7781 if (GET_CODE (src) == MEM
7782 && rtx_equal_p (XEXP (src, 0), next_io->var_address))
7783 {
7784 if (dump_file)
7785 fprintf (dump_file,
7786 ";; [Local] Removing membar %d since the target"
7787 " of %d is used before the I/O operation\n",
7788 INSN_UID (next_membar), INSN_UID (insn));
7789
7790 if (next_membar == *last_membar)
7791 *last_membar = 0;
7792
7793 delete_insn (next_membar);
7794 next_membar = 0;
7795 }
7796 }
7797
7798 /* If INSN has volatile references, forget about any registers
7799 that are used after it. Otherwise forget about uses that
7800 are (or might be) defined by INSN. */
7801 if (volatile_refs_p (PATTERN (insn)))
7802 CLEAR_HARD_REG_SET (used_regs);
7803 else
7804 note_stores (insn, frv_io_handle_set, &used_regs);
7805
7806 note_uses (&PATTERN (insn), frv_io_handle_use, &used_regs);
7807 break;
7808 }
7809 }
7810
7811 /* See if MEMBAR, the last membar instruction in BB, can be removed.
7812 FIRST_IO[X] describes the first operation performed by basic block X. */
7813
7814 static void
frv_optimize_membar_global(basic_block bb,struct frv_io * first_io,rtx_insn * membar)7815 frv_optimize_membar_global (basic_block bb, struct frv_io *first_io,
7816 rtx_insn *membar)
7817 {
7818 struct frv_io this_io, next_io;
7819 edge succ;
7820 edge_iterator ei;
7821
7822 /* We need to keep the membar if there is an edge to the exit block. */
7823 FOR_EACH_EDGE (succ, ei, bb->succs)
7824 /* for (succ = bb->succ; succ != 0; succ = succ->succ_next) */
7825 if (succ->dest == EXIT_BLOCK_PTR_FOR_FN (cfun))
7826 return;
7827
7828 /* Work out the union of all successor blocks. */
7829 ei = ei_start (bb->succs);
7830 ei_cond (ei, &succ);
7831 /* next_io = first_io[bb->succ->dest->index]; */
7832 next_io = first_io[succ->dest->index];
7833 ei = ei_start (bb->succs);
7834 if (ei_cond (ei, &succ))
7835 {
7836 for (ei_next (&ei); ei_cond (ei, &succ); ei_next (&ei))
7837 /*for (succ = bb->succ->succ_next; succ != 0; succ = succ->succ_next)*/
7838 frv_io_union (&next_io, &first_io[succ->dest->index]);
7839 }
7840 else
7841 gcc_unreachable ();
7842
7843 frv_extract_membar (&this_io, membar);
7844 if (frv_io_fixed_order_p (&this_io, &next_io))
7845 {
7846 if (dump_file)
7847 fprintf (dump_file,
7848 ";; [Global] Removing membar %d since order of accesses"
7849 " is guaranteed\n", INSN_UID (membar));
7850
7851 delete_insn (membar);
7852 }
7853 }
7854
7855 /* Remove redundant membars from the current function. */
7856
7857 static void
frv_optimize_membar(void)7858 frv_optimize_membar (void)
7859 {
7860 basic_block bb;
7861 struct frv_io *first_io;
7862 rtx_insn **last_membar;
7863
7864 compute_bb_for_insn ();
7865 first_io = XCNEWVEC (struct frv_io, last_basic_block_for_fn (cfun));
7866 last_membar = XCNEWVEC (rtx_insn *, last_basic_block_for_fn (cfun));
7867
7868 FOR_EACH_BB_FN (bb, cfun)
7869 frv_optimize_membar_local (bb, &first_io[bb->index],
7870 &last_membar[bb->index]);
7871
7872 FOR_EACH_BB_FN (bb, cfun)
7873 if (last_membar[bb->index] != 0)
7874 frv_optimize_membar_global (bb, first_io, last_membar[bb->index]);
7875
7876 free (first_io);
7877 free (last_membar);
7878 }
7879
7880 /* Used by frv_reorg to keep track of the current packet's address. */
7881 static unsigned int frv_packet_address;
7882
7883 /* If the current packet falls through to a label, try to pad the packet
7884 with nops in order to fit the label's alignment requirements. */
7885
7886 static void
frv_align_label(void)7887 frv_align_label (void)
7888 {
7889 unsigned int alignment, target, nop;
7890 rtx_insn *x, *last, *barrier, *label;
7891
7892 /* Walk forward to the start of the next packet. Set ALIGNMENT to the
7893 maximum alignment of that packet, LABEL to the last label between
7894 the packets, and BARRIER to the last barrier. */
7895 last = frv_packet.insns[frv_packet.num_insns - 1];
7896 label = barrier = 0;
7897 alignment = 4;
7898 for (x = NEXT_INSN (last); x != 0 && !INSN_P (x); x = NEXT_INSN (x))
7899 {
7900 if (LABEL_P (x))
7901 {
7902 unsigned int subalign = 1 << label_to_alignment (x).levels[0].log;
7903 alignment = MAX (alignment, subalign);
7904 label = x;
7905 }
7906 if (BARRIER_P (x))
7907 barrier = x;
7908 }
7909
7910 /* If -malign-labels, and the packet falls through to an unaligned
7911 label, try introducing a nop to align that label to 8 bytes. */
7912 if (TARGET_ALIGN_LABELS
7913 && label != 0
7914 && barrier == 0
7915 && frv_packet.num_insns < frv_packet.issue_rate)
7916 alignment = MAX (alignment, 8);
7917
7918 /* Advance the address to the end of the current packet. */
7919 frv_packet_address += frv_packet.num_insns * 4;
7920
7921 /* Work out the target address, after alignment. */
7922 target = (frv_packet_address + alignment - 1) & -alignment;
7923
7924 /* If the packet falls through to the label, try to find an efficient
7925 padding sequence. */
7926 if (barrier == 0)
7927 {
7928 /* First try adding nops to the current packet. */
7929 for (nop = 0; nop < frv_num_nops; nop++)
7930 while (frv_packet_address < target && frv_pack_insn_p (frv_nops[nop]))
7931 {
7932 frv_insert_nop_in_packet (frv_nops[nop]);
7933 frv_packet_address += 4;
7934 }
7935
7936 /* If we still haven't reached the target, add some new packets that
7937 contain only nops. If there are two types of nop, insert an
7938 alternating sequence of frv_nops[0] and frv_nops[1], which will
7939 lead to packets like:
7940
7941 nop.p
7942 mnop.p/fnop.p
7943 nop.p
7944 mnop/fnop
7945
7946 etc. Just emit frv_nops[0] if that's the only nop we have. */
7947 last = frv_packet.insns[frv_packet.num_insns - 1];
7948 nop = 0;
7949 while (frv_packet_address < target)
7950 {
7951 last = emit_insn_after (PATTERN (frv_nops[nop]), last);
7952 frv_packet_address += 4;
7953 if (frv_num_nops > 1)
7954 nop ^= 1;
7955 }
7956 }
7957
7958 frv_packet_address = target;
7959 }
7960
7961 /* Subroutine of frv_reorg, called after each packet has been constructed
7962 in frv_packet. */
7963
7964 static void
frv_reorg_packet(void)7965 frv_reorg_packet (void)
7966 {
7967 frv_fill_unused_units (GROUP_I);
7968 frv_fill_unused_units (GROUP_FM);
7969 frv_align_label ();
7970 }
7971
7972 /* Add an instruction with pattern NOP to frv_nops[]. */
7973
7974 static void
frv_register_nop(rtx nop)7975 frv_register_nop (rtx nop)
7976 {
7977 rtx_insn *nop_insn = make_insn_raw (nop);
7978 SET_NEXT_INSN (nop_insn) = 0;
7979 SET_PREV_INSN (nop_insn) = 0;
7980 frv_nops[frv_num_nops++] = nop_insn;
7981 }
7982
7983 /* Implement TARGET_MACHINE_DEPENDENT_REORG. Divide the instructions
7984 into packets and check whether we need to insert nops in order to
7985 fulfill the processor's issue requirements. Also, if the user has
7986 requested a certain alignment for a label, try to meet that alignment
7987 by inserting nops in the previous packet. */
7988
7989 static void
frv_reorg(void)7990 frv_reorg (void)
7991 {
7992 if (optimize > 0 && TARGET_OPTIMIZE_MEMBAR && cfun->machine->has_membar_p)
7993 frv_optimize_membar ();
7994
7995 frv_num_nops = 0;
7996 frv_register_nop (gen_nop ());
7997 if (TARGET_MEDIA)
7998 frv_register_nop (gen_mnop ());
7999 if (TARGET_HARD_FLOAT)
8000 frv_register_nop (gen_fnop ());
8001
8002 /* Estimate the length of each branch. Although this may change after
8003 we've inserted nops, it will only do so in big functions. */
8004 shorten_branches (get_insns ());
8005
8006 frv_packet_address = 0;
8007 frv_for_each_packet (frv_reorg_packet);
8008 }
8009
8010 #define def_builtin(name, type, code) \
8011 add_builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL)
8012
8013 struct builtin_description
8014 {
8015 enum insn_code icode;
8016 const char *name;
8017 enum frv_builtins code;
8018 enum rtx_code comparison;
8019 unsigned int flag;
8020 };
8021
8022 /* Media intrinsics that take a single, constant argument. */
8023
8024 static struct builtin_description bdesc_set[] =
8025 {
8026 { CODE_FOR_mhdsets, "__MHDSETS", FRV_BUILTIN_MHDSETS, UNKNOWN, 0 }
8027 };
8028
8029 /* Media intrinsics that take just one argument. */
8030
8031 static struct builtin_description bdesc_1arg[] =
8032 {
8033 { CODE_FOR_mnot, "__MNOT", FRV_BUILTIN_MNOT, UNKNOWN, 0 },
8034 { CODE_FOR_munpackh, "__MUNPACKH", FRV_BUILTIN_MUNPACKH, UNKNOWN, 0 },
8035 { CODE_FOR_mbtoh, "__MBTOH", FRV_BUILTIN_MBTOH, UNKNOWN, 0 },
8036 { CODE_FOR_mhtob, "__MHTOB", FRV_BUILTIN_MHTOB, UNKNOWN, 0},
8037 { CODE_FOR_mabshs, "__MABSHS", FRV_BUILTIN_MABSHS, UNKNOWN, 0 },
8038 { CODE_FOR_scutss, "__SCUTSS", FRV_BUILTIN_SCUTSS, UNKNOWN, 0 }
8039 };
8040
8041 /* Media intrinsics that take two arguments. */
8042
8043 static struct builtin_description bdesc_2arg[] =
8044 {
8045 { CODE_FOR_mand, "__MAND", FRV_BUILTIN_MAND, UNKNOWN, 0},
8046 { CODE_FOR_mor, "__MOR", FRV_BUILTIN_MOR, UNKNOWN, 0},
8047 { CODE_FOR_mxor, "__MXOR", FRV_BUILTIN_MXOR, UNKNOWN, 0},
8048 { CODE_FOR_maveh, "__MAVEH", FRV_BUILTIN_MAVEH, UNKNOWN, 0},
8049 { CODE_FOR_msaths, "__MSATHS", FRV_BUILTIN_MSATHS, UNKNOWN, 0},
8050 { CODE_FOR_msathu, "__MSATHU", FRV_BUILTIN_MSATHU, UNKNOWN, 0},
8051 { CODE_FOR_maddhss, "__MADDHSS", FRV_BUILTIN_MADDHSS, UNKNOWN, 0},
8052 { CODE_FOR_maddhus, "__MADDHUS", FRV_BUILTIN_MADDHUS, UNKNOWN, 0},
8053 { CODE_FOR_msubhss, "__MSUBHSS", FRV_BUILTIN_MSUBHSS, UNKNOWN, 0},
8054 { CODE_FOR_msubhus, "__MSUBHUS", FRV_BUILTIN_MSUBHUS, UNKNOWN, 0},
8055 { CODE_FOR_mqaddhss, "__MQADDHSS", FRV_BUILTIN_MQADDHSS, UNKNOWN, 0},
8056 { CODE_FOR_mqaddhus, "__MQADDHUS", FRV_BUILTIN_MQADDHUS, UNKNOWN, 0},
8057 { CODE_FOR_mqsubhss, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS, UNKNOWN, 0},
8058 { CODE_FOR_mqsubhus, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS, UNKNOWN, 0},
8059 { CODE_FOR_mpackh, "__MPACKH", FRV_BUILTIN_MPACKH, UNKNOWN, 0},
8060 { CODE_FOR_mcop1, "__Mcop1", FRV_BUILTIN_MCOP1, UNKNOWN, 0},
8061 { CODE_FOR_mcop2, "__Mcop2", FRV_BUILTIN_MCOP2, UNKNOWN, 0},
8062 { CODE_FOR_mwcut, "__MWCUT", FRV_BUILTIN_MWCUT, UNKNOWN, 0},
8063 { CODE_FOR_mqsaths, "__MQSATHS", FRV_BUILTIN_MQSATHS, UNKNOWN, 0},
8064 { CODE_FOR_mqlclrhs, "__MQLCLRHS", FRV_BUILTIN_MQLCLRHS, UNKNOWN, 0},
8065 { CODE_FOR_mqlmths, "__MQLMTHS", FRV_BUILTIN_MQLMTHS, UNKNOWN, 0},
8066 { CODE_FOR_smul, "__SMUL", FRV_BUILTIN_SMUL, UNKNOWN, 0},
8067 { CODE_FOR_umul, "__UMUL", FRV_BUILTIN_UMUL, UNKNOWN, 0},
8068 { CODE_FOR_addss, "__ADDSS", FRV_BUILTIN_ADDSS, UNKNOWN, 0},
8069 { CODE_FOR_subss, "__SUBSS", FRV_BUILTIN_SUBSS, UNKNOWN, 0},
8070 { CODE_FOR_slass, "__SLASS", FRV_BUILTIN_SLASS, UNKNOWN, 0},
8071 { CODE_FOR_scan, "__SCAN", FRV_BUILTIN_SCAN, UNKNOWN, 0}
8072 };
8073
8074 /* Integer intrinsics that take two arguments and have no return value. */
8075
8076 static struct builtin_description bdesc_int_void2arg[] =
8077 {
8078 { CODE_FOR_smass, "__SMASS", FRV_BUILTIN_SMASS, UNKNOWN, 0},
8079 { CODE_FOR_smsss, "__SMSSS", FRV_BUILTIN_SMSSS, UNKNOWN, 0},
8080 { CODE_FOR_smu, "__SMU", FRV_BUILTIN_SMU, UNKNOWN, 0}
8081 };
8082
8083 static struct builtin_description bdesc_prefetches[] =
8084 {
8085 { CODE_FOR_frv_prefetch0, "__data_prefetch0", FRV_BUILTIN_PREFETCH0, UNKNOWN,
8086 0},
8087 { CODE_FOR_frv_prefetch, "__data_prefetch", FRV_BUILTIN_PREFETCH, UNKNOWN, 0}
8088 };
8089
8090 /* Media intrinsics that take two arguments, the first being an ACC number. */
8091
8092 static struct builtin_description bdesc_cut[] =
8093 {
8094 { CODE_FOR_mcut, "__MCUT", FRV_BUILTIN_MCUT, UNKNOWN, 0},
8095 { CODE_FOR_mcutss, "__MCUTSS", FRV_BUILTIN_MCUTSS, UNKNOWN, 0},
8096 { CODE_FOR_mdcutssi, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI, UNKNOWN, 0}
8097 };
8098
8099 /* Two-argument media intrinsics with an immediate second argument. */
8100
8101 static struct builtin_description bdesc_2argimm[] =
8102 {
8103 { CODE_FOR_mrotli, "__MROTLI", FRV_BUILTIN_MROTLI, UNKNOWN, 0},
8104 { CODE_FOR_mrotri, "__MROTRI", FRV_BUILTIN_MROTRI, UNKNOWN, 0},
8105 { CODE_FOR_msllhi, "__MSLLHI", FRV_BUILTIN_MSLLHI, UNKNOWN, 0},
8106 { CODE_FOR_msrlhi, "__MSRLHI", FRV_BUILTIN_MSRLHI, UNKNOWN, 0},
8107 { CODE_FOR_msrahi, "__MSRAHI", FRV_BUILTIN_MSRAHI, UNKNOWN, 0},
8108 { CODE_FOR_mexpdhw, "__MEXPDHW", FRV_BUILTIN_MEXPDHW, UNKNOWN, 0},
8109 { CODE_FOR_mexpdhd, "__MEXPDHD", FRV_BUILTIN_MEXPDHD, UNKNOWN, 0},
8110 { CODE_FOR_mdrotli, "__MDROTLI", FRV_BUILTIN_MDROTLI, UNKNOWN, 0},
8111 { CODE_FOR_mcplhi, "__MCPLHI", FRV_BUILTIN_MCPLHI, UNKNOWN, 0},
8112 { CODE_FOR_mcpli, "__MCPLI", FRV_BUILTIN_MCPLI, UNKNOWN, 0},
8113 { CODE_FOR_mhsetlos, "__MHSETLOS", FRV_BUILTIN_MHSETLOS, UNKNOWN, 0},
8114 { CODE_FOR_mhsetloh, "__MHSETLOH", FRV_BUILTIN_MHSETLOH, UNKNOWN, 0},
8115 { CODE_FOR_mhsethis, "__MHSETHIS", FRV_BUILTIN_MHSETHIS, UNKNOWN, 0},
8116 { CODE_FOR_mhsethih, "__MHSETHIH", FRV_BUILTIN_MHSETHIH, UNKNOWN, 0},
8117 { CODE_FOR_mhdseth, "__MHDSETH", FRV_BUILTIN_MHDSETH, UNKNOWN, 0},
8118 { CODE_FOR_mqsllhi, "__MQSLLHI", FRV_BUILTIN_MQSLLHI, UNKNOWN, 0},
8119 { CODE_FOR_mqsrahi, "__MQSRAHI", FRV_BUILTIN_MQSRAHI, UNKNOWN, 0}
8120 };
8121
8122 /* Media intrinsics that take two arguments and return void, the first argument
8123 being a pointer to 4 words in memory. */
8124
8125 static struct builtin_description bdesc_void2arg[] =
8126 {
8127 { CODE_FOR_mdunpackh, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH, UNKNOWN, 0},
8128 { CODE_FOR_mbtohe, "__MBTOHE", FRV_BUILTIN_MBTOHE, UNKNOWN, 0},
8129 };
8130
8131 /* Media intrinsics that take three arguments, the first being a const_int that
8132 denotes an accumulator, and that return void. */
8133
8134 static struct builtin_description bdesc_void3arg[] =
8135 {
8136 { CODE_FOR_mcpxrs, "__MCPXRS", FRV_BUILTIN_MCPXRS, UNKNOWN, 0},
8137 { CODE_FOR_mcpxru, "__MCPXRU", FRV_BUILTIN_MCPXRU, UNKNOWN, 0},
8138 { CODE_FOR_mcpxis, "__MCPXIS", FRV_BUILTIN_MCPXIS, UNKNOWN, 0},
8139 { CODE_FOR_mcpxiu, "__MCPXIU", FRV_BUILTIN_MCPXIU, UNKNOWN, 0},
8140 { CODE_FOR_mmulhs, "__MMULHS", FRV_BUILTIN_MMULHS, UNKNOWN, 0},
8141 { CODE_FOR_mmulhu, "__MMULHU", FRV_BUILTIN_MMULHU, UNKNOWN, 0},
8142 { CODE_FOR_mmulxhs, "__MMULXHS", FRV_BUILTIN_MMULXHS, UNKNOWN, 0},
8143 { CODE_FOR_mmulxhu, "__MMULXHU", FRV_BUILTIN_MMULXHU, UNKNOWN, 0},
8144 { CODE_FOR_mmachs, "__MMACHS", FRV_BUILTIN_MMACHS, UNKNOWN, 0},
8145 { CODE_FOR_mmachu, "__MMACHU", FRV_BUILTIN_MMACHU, UNKNOWN, 0},
8146 { CODE_FOR_mmrdhs, "__MMRDHS", FRV_BUILTIN_MMRDHS, UNKNOWN, 0},
8147 { CODE_FOR_mmrdhu, "__MMRDHU", FRV_BUILTIN_MMRDHU, UNKNOWN, 0},
8148 { CODE_FOR_mqcpxrs, "__MQCPXRS", FRV_BUILTIN_MQCPXRS, UNKNOWN, 0},
8149 { CODE_FOR_mqcpxru, "__MQCPXRU", FRV_BUILTIN_MQCPXRU, UNKNOWN, 0},
8150 { CODE_FOR_mqcpxis, "__MQCPXIS", FRV_BUILTIN_MQCPXIS, UNKNOWN, 0},
8151 { CODE_FOR_mqcpxiu, "__MQCPXIU", FRV_BUILTIN_MQCPXIU, UNKNOWN, 0},
8152 { CODE_FOR_mqmulhs, "__MQMULHS", FRV_BUILTIN_MQMULHS, UNKNOWN, 0},
8153 { CODE_FOR_mqmulhu, "__MQMULHU", FRV_BUILTIN_MQMULHU, UNKNOWN, 0},
8154 { CODE_FOR_mqmulxhs, "__MQMULXHS", FRV_BUILTIN_MQMULXHS, UNKNOWN, 0},
8155 { CODE_FOR_mqmulxhu, "__MQMULXHU", FRV_BUILTIN_MQMULXHU, UNKNOWN, 0},
8156 { CODE_FOR_mqmachs, "__MQMACHS", FRV_BUILTIN_MQMACHS, UNKNOWN, 0},
8157 { CODE_FOR_mqmachu, "__MQMACHU", FRV_BUILTIN_MQMACHU, UNKNOWN, 0},
8158 { CODE_FOR_mqxmachs, "__MQXMACHS", FRV_BUILTIN_MQXMACHS, UNKNOWN, 0},
8159 { CODE_FOR_mqxmacxhs, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS, UNKNOWN, 0},
8160 { CODE_FOR_mqmacxhs, "__MQMACXHS", FRV_BUILTIN_MQMACXHS, UNKNOWN, 0}
8161 };
8162
8163 /* Media intrinsics that take two accumulator numbers as argument and
8164 return void. */
8165
8166 static struct builtin_description bdesc_voidacc[] =
8167 {
8168 { CODE_FOR_maddaccs, "__MADDACCS", FRV_BUILTIN_MADDACCS, UNKNOWN, 0},
8169 { CODE_FOR_msubaccs, "__MSUBACCS", FRV_BUILTIN_MSUBACCS, UNKNOWN, 0},
8170 { CODE_FOR_masaccs, "__MASACCS", FRV_BUILTIN_MASACCS, UNKNOWN, 0},
8171 { CODE_FOR_mdaddaccs, "__MDADDACCS", FRV_BUILTIN_MDADDACCS, UNKNOWN, 0},
8172 { CODE_FOR_mdsubaccs, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS, UNKNOWN, 0},
8173 { CODE_FOR_mdasaccs, "__MDASACCS", FRV_BUILTIN_MDASACCS, UNKNOWN, 0}
8174 };
8175
8176 /* Intrinsics that load a value and then issue a MEMBAR. The load is
8177 a normal move and the ICODE is for the membar. */
8178
8179 static struct builtin_description bdesc_loads[] =
8180 {
8181 { CODE_FOR_optional_membar_qi, "__builtin_read8",
8182 FRV_BUILTIN_READ8, UNKNOWN, 0},
8183 { CODE_FOR_optional_membar_hi, "__builtin_read16",
8184 FRV_BUILTIN_READ16, UNKNOWN, 0},
8185 { CODE_FOR_optional_membar_si, "__builtin_read32",
8186 FRV_BUILTIN_READ32, UNKNOWN, 0},
8187 { CODE_FOR_optional_membar_di, "__builtin_read64",
8188 FRV_BUILTIN_READ64, UNKNOWN, 0}
8189 };
8190
8191 /* Likewise stores. */
8192
8193 static struct builtin_description bdesc_stores[] =
8194 {
8195 { CODE_FOR_optional_membar_qi, "__builtin_write8",
8196 FRV_BUILTIN_WRITE8, UNKNOWN, 0},
8197 { CODE_FOR_optional_membar_hi, "__builtin_write16",
8198 FRV_BUILTIN_WRITE16, UNKNOWN, 0},
8199 { CODE_FOR_optional_membar_si, "__builtin_write32",
8200 FRV_BUILTIN_WRITE32, UNKNOWN, 0},
8201 { CODE_FOR_optional_membar_di, "__builtin_write64",
8202 FRV_BUILTIN_WRITE64, UNKNOWN, 0},
8203 };
8204
8205 /* Initialize media builtins. */
8206
8207 static void
frv_init_builtins(void)8208 frv_init_builtins (void)
8209 {
8210 tree accumulator = integer_type_node;
8211 tree integer = integer_type_node;
8212 tree voidt = void_type_node;
8213 tree uhalf = short_unsigned_type_node;
8214 tree sword1 = long_integer_type_node;
8215 tree uword1 = long_unsigned_type_node;
8216 tree sword2 = long_long_integer_type_node;
8217 tree uword2 = long_long_unsigned_type_node;
8218 tree uword4 = build_pointer_type (uword1);
8219 tree vptr = build_pointer_type (build_type_variant (void_type_node, 0, 1));
8220 tree ubyte = unsigned_char_type_node;
8221 tree iacc = integer_type_node;
8222
8223 #define UNARY(RET, T1) \
8224 build_function_type_list (RET, T1, NULL_TREE)
8225
8226 #define BINARY(RET, T1, T2) \
8227 build_function_type_list (RET, T1, T2, NULL_TREE)
8228
8229 #define TRINARY(RET, T1, T2, T3) \
8230 build_function_type_list (RET, T1, T2, T3, NULL_TREE)
8231
8232 #define QUAD(RET, T1, T2, T3, T4) \
8233 build_function_type_list (RET, T1, T2, T3, T4, NULL_TREE)
8234
8235 tree void_ftype_void = build_function_type_list (voidt, NULL_TREE);
8236
8237 tree void_ftype_acc = UNARY (voidt, accumulator);
8238 tree void_ftype_uw4_uw1 = BINARY (voidt, uword4, uword1);
8239 tree void_ftype_uw4_uw2 = BINARY (voidt, uword4, uword2);
8240 tree void_ftype_acc_uw1 = BINARY (voidt, accumulator, uword1);
8241 tree void_ftype_acc_acc = BINARY (voidt, accumulator, accumulator);
8242 tree void_ftype_acc_uw1_uw1 = TRINARY (voidt, accumulator, uword1, uword1);
8243 tree void_ftype_acc_sw1_sw1 = TRINARY (voidt, accumulator, sword1, sword1);
8244 tree void_ftype_acc_uw2_uw2 = TRINARY (voidt, accumulator, uword2, uword2);
8245 tree void_ftype_acc_sw2_sw2 = TRINARY (voidt, accumulator, sword2, sword2);
8246
8247 tree uw1_ftype_uw1 = UNARY (uword1, uword1);
8248 tree uw1_ftype_sw1 = UNARY (uword1, sword1);
8249 tree uw1_ftype_uw2 = UNARY (uword1, uword2);
8250 tree uw1_ftype_acc = UNARY (uword1, accumulator);
8251 tree uw1_ftype_uh_uh = BINARY (uword1, uhalf, uhalf);
8252 tree uw1_ftype_uw1_uw1 = BINARY (uword1, uword1, uword1);
8253 tree uw1_ftype_uw1_int = BINARY (uword1, uword1, integer);
8254 tree uw1_ftype_acc_uw1 = BINARY (uword1, accumulator, uword1);
8255 tree uw1_ftype_acc_sw1 = BINARY (uword1, accumulator, sword1);
8256 tree uw1_ftype_uw2_uw1 = BINARY (uword1, uword2, uword1);
8257 tree uw1_ftype_uw2_int = BINARY (uword1, uword2, integer);
8258
8259 tree sw1_ftype_int = UNARY (sword1, integer);
8260 tree sw1_ftype_sw1_sw1 = BINARY (sword1, sword1, sword1);
8261 tree sw1_ftype_sw1_int = BINARY (sword1, sword1, integer);
8262
8263 tree uw2_ftype_uw1 = UNARY (uword2, uword1);
8264 tree uw2_ftype_uw1_int = BINARY (uword2, uword1, integer);
8265 tree uw2_ftype_uw2_uw2 = BINARY (uword2, uword2, uword2);
8266 tree uw2_ftype_uw2_int = BINARY (uword2, uword2, integer);
8267 tree uw2_ftype_acc_int = BINARY (uword2, accumulator, integer);
8268 tree uw2_ftype_uh_uh_uh_uh = QUAD (uword2, uhalf, uhalf, uhalf, uhalf);
8269
8270 tree sw2_ftype_sw2_sw2 = BINARY (sword2, sword2, sword2);
8271 tree sw2_ftype_sw2_int = BINARY (sword2, sword2, integer);
8272 tree uw2_ftype_uw1_uw1 = BINARY (uword2, uword1, uword1);
8273 tree sw2_ftype_sw1_sw1 = BINARY (sword2, sword1, sword1);
8274 tree void_ftype_sw1_sw1 = BINARY (voidt, sword1, sword1);
8275 tree void_ftype_iacc_sw2 = BINARY (voidt, iacc, sword2);
8276 tree void_ftype_iacc_sw1 = BINARY (voidt, iacc, sword1);
8277 tree sw1_ftype_sw1 = UNARY (sword1, sword1);
8278 tree sw2_ftype_iacc = UNARY (sword2, iacc);
8279 tree sw1_ftype_iacc = UNARY (sword1, iacc);
8280 tree void_ftype_ptr = UNARY (voidt, const_ptr_type_node);
8281 tree uw1_ftype_vptr = UNARY (uword1, vptr);
8282 tree uw2_ftype_vptr = UNARY (uword2, vptr);
8283 tree void_ftype_vptr_ub = BINARY (voidt, vptr, ubyte);
8284 tree void_ftype_vptr_uh = BINARY (voidt, vptr, uhalf);
8285 tree void_ftype_vptr_uw1 = BINARY (voidt, vptr, uword1);
8286 tree void_ftype_vptr_uw2 = BINARY (voidt, vptr, uword2);
8287
8288 def_builtin ("__MAND", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAND);
8289 def_builtin ("__MOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MOR);
8290 def_builtin ("__MXOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MXOR);
8291 def_builtin ("__MNOT", uw1_ftype_uw1, FRV_BUILTIN_MNOT);
8292 def_builtin ("__MROTLI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTLI);
8293 def_builtin ("__MROTRI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTRI);
8294 def_builtin ("__MWCUT", uw1_ftype_uw2_uw1, FRV_BUILTIN_MWCUT);
8295 def_builtin ("__MAVEH", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAVEH);
8296 def_builtin ("__MSLLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSLLHI);
8297 def_builtin ("__MSRLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSRLHI);
8298 def_builtin ("__MSRAHI", sw1_ftype_sw1_int, FRV_BUILTIN_MSRAHI);
8299 def_builtin ("__MSATHS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSATHS);
8300 def_builtin ("__MSATHU", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSATHU);
8301 def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MADDHSS);
8302 def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MADDHUS);
8303 def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSUBHSS);
8304 def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSUBHUS);
8305 def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULHS);
8306 def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULHU);
8307 def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULXHS);
8308 def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULXHU);
8309 def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMACHS);
8310 def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMACHU);
8311 def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMRDHS);
8312 def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMRDHU);
8313 def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQADDHSS);
8314 def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQADDHUS);
8315 def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSUBHSS);
8316 def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQSUBHUS);
8317 def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULHS);
8318 def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULHU);
8319 def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULXHS);
8320 def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULXHU);
8321 def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACHS);
8322 def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMACHU);
8323 def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXRS);
8324 def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXRU);
8325 def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXIS);
8326 def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXIU);
8327 def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXRS);
8328 def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXRU);
8329 def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXIS);
8330 def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXIU);
8331 def_builtin ("__MCUT", uw1_ftype_acc_uw1, FRV_BUILTIN_MCUT);
8332 def_builtin ("__MCUTSS", uw1_ftype_acc_sw1, FRV_BUILTIN_MCUTSS);
8333 def_builtin ("__MEXPDHW", uw1_ftype_uw1_int, FRV_BUILTIN_MEXPDHW);
8334 def_builtin ("__MEXPDHD", uw2_ftype_uw1_int, FRV_BUILTIN_MEXPDHD);
8335 def_builtin ("__MPACKH", uw1_ftype_uh_uh, FRV_BUILTIN_MPACKH);
8336 def_builtin ("__MUNPACKH", uw2_ftype_uw1, FRV_BUILTIN_MUNPACKH);
8337 def_builtin ("__MDPACKH", uw2_ftype_uh_uh_uh_uh, FRV_BUILTIN_MDPACKH);
8338 def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2, FRV_BUILTIN_MDUNPACKH);
8339 def_builtin ("__MBTOH", uw2_ftype_uw1, FRV_BUILTIN_MBTOH);
8340 def_builtin ("__MHTOB", uw1_ftype_uw2, FRV_BUILTIN_MHTOB);
8341 def_builtin ("__MBTOHE", void_ftype_uw4_uw1, FRV_BUILTIN_MBTOHE);
8342 def_builtin ("__MCLRACC", void_ftype_acc, FRV_BUILTIN_MCLRACC);
8343 def_builtin ("__MCLRACCA", void_ftype_void, FRV_BUILTIN_MCLRACCA);
8344 def_builtin ("__MRDACC", uw1_ftype_acc, FRV_BUILTIN_MRDACC);
8345 def_builtin ("__MRDACCG", uw1_ftype_acc, FRV_BUILTIN_MRDACCG);
8346 def_builtin ("__MWTACC", void_ftype_acc_uw1, FRV_BUILTIN_MWTACC);
8347 def_builtin ("__MWTACCG", void_ftype_acc_uw1, FRV_BUILTIN_MWTACCG);
8348 def_builtin ("__Mcop1", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP1);
8349 def_builtin ("__Mcop2", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP2);
8350 def_builtin ("__MTRAP", void_ftype_void, FRV_BUILTIN_MTRAP);
8351 def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACHS);
8352 def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACXHS);
8353 def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACXHS);
8354 def_builtin ("__MADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MADDACCS);
8355 def_builtin ("__MSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MSUBACCS);
8356 def_builtin ("__MASACCS", void_ftype_acc_acc, FRV_BUILTIN_MASACCS);
8357 def_builtin ("__MDADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MDADDACCS);
8358 def_builtin ("__MDSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MDSUBACCS);
8359 def_builtin ("__MDASACCS", void_ftype_acc_acc, FRV_BUILTIN_MDASACCS);
8360 def_builtin ("__MABSHS", uw1_ftype_sw1, FRV_BUILTIN_MABSHS);
8361 def_builtin ("__MDROTLI", uw2_ftype_uw2_int, FRV_BUILTIN_MDROTLI);
8362 def_builtin ("__MCPLHI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLHI);
8363 def_builtin ("__MCPLI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLI);
8364 def_builtin ("__MDCUTSSI", uw2_ftype_acc_int, FRV_BUILTIN_MDCUTSSI);
8365 def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSATHS);
8366 def_builtin ("__MHSETLOS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETLOS);
8367 def_builtin ("__MHSETHIS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETHIS);
8368 def_builtin ("__MHDSETS", sw1_ftype_int, FRV_BUILTIN_MHDSETS);
8369 def_builtin ("__MHSETLOH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETLOH);
8370 def_builtin ("__MHSETHIH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETHIH);
8371 def_builtin ("__MHDSETH", uw1_ftype_uw1_int, FRV_BUILTIN_MHDSETH);
8372 def_builtin ("__MQLCLRHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLCLRHS);
8373 def_builtin ("__MQLMTHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLMTHS);
8374 def_builtin ("__MQSLLHI", uw2_ftype_uw2_int, FRV_BUILTIN_MQSLLHI);
8375 def_builtin ("__MQSRAHI", sw2_ftype_sw2_int, FRV_BUILTIN_MQSRAHI);
8376 def_builtin ("__SMUL", sw2_ftype_sw1_sw1, FRV_BUILTIN_SMUL);
8377 def_builtin ("__UMUL", uw2_ftype_uw1_uw1, FRV_BUILTIN_UMUL);
8378 def_builtin ("__SMASS", void_ftype_sw1_sw1, FRV_BUILTIN_SMASS);
8379 def_builtin ("__SMSSS", void_ftype_sw1_sw1, FRV_BUILTIN_SMSSS);
8380 def_builtin ("__SMU", void_ftype_sw1_sw1, FRV_BUILTIN_SMU);
8381 def_builtin ("__ADDSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_ADDSS);
8382 def_builtin ("__SUBSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SUBSS);
8383 def_builtin ("__SLASS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SLASS);
8384 def_builtin ("__SCAN", sw1_ftype_sw1_sw1, FRV_BUILTIN_SCAN);
8385 def_builtin ("__SCUTSS", sw1_ftype_sw1, FRV_BUILTIN_SCUTSS);
8386 def_builtin ("__IACCreadll", sw2_ftype_iacc, FRV_BUILTIN_IACCreadll);
8387 def_builtin ("__IACCreadl", sw1_ftype_iacc, FRV_BUILTIN_IACCreadl);
8388 def_builtin ("__IACCsetll", void_ftype_iacc_sw2, FRV_BUILTIN_IACCsetll);
8389 def_builtin ("__IACCsetl", void_ftype_iacc_sw1, FRV_BUILTIN_IACCsetl);
8390 def_builtin ("__data_prefetch0", void_ftype_ptr, FRV_BUILTIN_PREFETCH0);
8391 def_builtin ("__data_prefetch", void_ftype_ptr, FRV_BUILTIN_PREFETCH);
8392 def_builtin ("__builtin_read8", uw1_ftype_vptr, FRV_BUILTIN_READ8);
8393 def_builtin ("__builtin_read16", uw1_ftype_vptr, FRV_BUILTIN_READ16);
8394 def_builtin ("__builtin_read32", uw1_ftype_vptr, FRV_BUILTIN_READ32);
8395 def_builtin ("__builtin_read64", uw2_ftype_vptr, FRV_BUILTIN_READ64);
8396
8397 def_builtin ("__builtin_write8", void_ftype_vptr_ub, FRV_BUILTIN_WRITE8);
8398 def_builtin ("__builtin_write16", void_ftype_vptr_uh, FRV_BUILTIN_WRITE16);
8399 def_builtin ("__builtin_write32", void_ftype_vptr_uw1, FRV_BUILTIN_WRITE32);
8400 def_builtin ("__builtin_write64", void_ftype_vptr_uw2, FRV_BUILTIN_WRITE64);
8401
8402 #undef UNARY
8403 #undef BINARY
8404 #undef TRINARY
8405 #undef QUAD
8406 }
8407
8408 /* Set the names for various arithmetic operations according to the
8409 FRV ABI. */
8410 static void
frv_init_libfuncs(void)8411 frv_init_libfuncs (void)
8412 {
8413 set_optab_libfunc (smod_optab, SImode, "__modi");
8414 set_optab_libfunc (umod_optab, SImode, "__umodi");
8415
8416 set_optab_libfunc (add_optab, DImode, "__addll");
8417 set_optab_libfunc (sub_optab, DImode, "__subll");
8418 set_optab_libfunc (smul_optab, DImode, "__mulll");
8419 set_optab_libfunc (sdiv_optab, DImode, "__divll");
8420 set_optab_libfunc (smod_optab, DImode, "__modll");
8421 set_optab_libfunc (umod_optab, DImode, "__umodll");
8422 set_optab_libfunc (and_optab, DImode, "__andll");
8423 set_optab_libfunc (ior_optab, DImode, "__orll");
8424 set_optab_libfunc (xor_optab, DImode, "__xorll");
8425 set_optab_libfunc (one_cmpl_optab, DImode, "__notll");
8426
8427 set_optab_libfunc (add_optab, SFmode, "__addf");
8428 set_optab_libfunc (sub_optab, SFmode, "__subf");
8429 set_optab_libfunc (smul_optab, SFmode, "__mulf");
8430 set_optab_libfunc (sdiv_optab, SFmode, "__divf");
8431
8432 set_optab_libfunc (add_optab, DFmode, "__addd");
8433 set_optab_libfunc (sub_optab, DFmode, "__subd");
8434 set_optab_libfunc (smul_optab, DFmode, "__muld");
8435 set_optab_libfunc (sdiv_optab, DFmode, "__divd");
8436
8437 set_conv_libfunc (sext_optab, DFmode, SFmode, "__ftod");
8438 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__dtof");
8439
8440 set_conv_libfunc (sfix_optab, SImode, SFmode, "__ftoi");
8441 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
8442 set_conv_libfunc (sfix_optab, SImode, DFmode, "__dtoi");
8443 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
8444
8445 set_conv_libfunc (ufix_optab, SImode, SFmode, "__ftoui");
8446 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
8447 set_conv_libfunc (ufix_optab, SImode, DFmode, "__dtoui");
8448 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
8449
8450 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__itof");
8451 set_conv_libfunc (sfloat_optab, SFmode, DImode, "__lltof");
8452 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__itod");
8453 set_conv_libfunc (sfloat_optab, DFmode, DImode, "__lltod");
8454 }
8455
8456 /* Convert an integer constant to an accumulator register. ICODE is the
8457 code of the target instruction, OPNUM is the number of the
8458 accumulator operand and OPVAL is the constant integer. Try both
8459 ACC and ACCG registers; only report an error if neither fit the
8460 instruction. */
8461
8462 static rtx
frv_int_to_acc(enum insn_code icode,int opnum,rtx opval)8463 frv_int_to_acc (enum insn_code icode, int opnum, rtx opval)
8464 {
8465 rtx reg;
8466 int i;
8467
8468 /* ACCs and ACCGs are implicit global registers if media intrinsics
8469 are being used. We set up this lazily to avoid creating lots of
8470 unnecessary call_insn rtl in non-media code. */
8471 for (i = 0; i <= ACC_MASK; i++)
8472 if ((i & ACC_MASK) == i)
8473 global_regs[i + ACC_FIRST] = global_regs[i + ACCG_FIRST] = 1;
8474
8475 if (GET_CODE (opval) != CONST_INT)
8476 {
8477 error ("accumulator is not a constant integer");
8478 return NULL_RTX;
8479 }
8480 if ((INTVAL (opval) & ~ACC_MASK) != 0)
8481 {
8482 error ("accumulator number is out of bounds");
8483 return NULL_RTX;
8484 }
8485
8486 reg = gen_rtx_REG (insn_data[icode].operand[opnum].mode,
8487 ACC_FIRST + INTVAL (opval));
8488 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
8489 SET_REGNO (reg, ACCG_FIRST + INTVAL (opval));
8490
8491 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
8492 {
8493 error ("inappropriate accumulator for %qs", insn_data[icode].name);
8494 return NULL_RTX;
8495 }
8496 return reg;
8497 }
8498
8499 /* If an ACC rtx has mode MODE, return the mode that the matching ACCG
8500 should have. */
8501
8502 static machine_mode
frv_matching_accg_mode(machine_mode mode)8503 frv_matching_accg_mode (machine_mode mode)
8504 {
8505 switch (mode)
8506 {
8507 case E_V4SImode:
8508 return V4QImode;
8509
8510 case E_DImode:
8511 return HImode;
8512
8513 case E_SImode:
8514 return QImode;
8515
8516 default:
8517 gcc_unreachable ();
8518 }
8519 }
8520
8521 /* Given that a __builtin_read or __builtin_write function is accessing
8522 address ADDRESS, return the value that should be used as operand 1
8523 of the membar. */
8524
8525 static rtx
frv_io_address_cookie(rtx address)8526 frv_io_address_cookie (rtx address)
8527 {
8528 return (GET_CODE (address) == CONST_INT
8529 ? GEN_INT (INTVAL (address) / 8 * 8)
8530 : const0_rtx);
8531 }
8532
8533 /* Return the accumulator guard that should be paired with accumulator
8534 register ACC. The mode of the returned register is in the same
8535 class as ACC, but is four times smaller. */
8536
8537 rtx
frv_matching_accg_for_acc(rtx acc)8538 frv_matching_accg_for_acc (rtx acc)
8539 {
8540 return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc)),
8541 REGNO (acc) - ACC_FIRST + ACCG_FIRST);
8542 }
8543
8544 /* Read the requested argument from the call EXP given by INDEX.
8545 Return the value as an rtx. */
8546
8547 static rtx
frv_read_argument(tree exp,unsigned int index)8548 frv_read_argument (tree exp, unsigned int index)
8549 {
8550 return expand_normal (CALL_EXPR_ARG (exp, index));
8551 }
8552
8553 /* Like frv_read_argument, but interpret the argument as the number
8554 of an IACC register and return a (reg:MODE ...) rtx for it. */
8555
8556 static rtx
frv_read_iacc_argument(machine_mode mode,tree call,unsigned int index)8557 frv_read_iacc_argument (machine_mode mode, tree call,
8558 unsigned int index)
8559 {
8560 int i, regno;
8561 rtx op;
8562
8563 op = frv_read_argument (call, index);
8564 if (GET_CODE (op) != CONST_INT
8565 || INTVAL (op) < 0
8566 || INTVAL (op) > IACC_LAST - IACC_FIRST
8567 || ((INTVAL (op) * 4) & (GET_MODE_SIZE (mode) - 1)) != 0)
8568 {
8569 error ("invalid IACC argument");
8570 op = const0_rtx;
8571 }
8572
8573 /* IACCs are implicit global registers. We set up this lazily to
8574 avoid creating lots of unnecessary call_insn rtl when IACCs aren't
8575 being used. */
8576 regno = INTVAL (op) + IACC_FIRST;
8577 for (i = 0; i < hard_regno_nregs (regno, mode); i++)
8578 global_regs[regno + i] = 1;
8579
8580 return gen_rtx_REG (mode, regno);
8581 }
8582
8583 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
8584 The instruction should require a constant operand of some sort. The
8585 function prints an error if OPVAL is not valid. */
8586
8587 static int
frv_check_constant_argument(enum insn_code icode,int opnum,rtx opval)8588 frv_check_constant_argument (enum insn_code icode, int opnum, rtx opval)
8589 {
8590 if (GET_CODE (opval) != CONST_INT)
8591 {
8592 error ("%qs expects a constant argument", insn_data[icode].name);
8593 return FALSE;
8594 }
8595 if (! (*insn_data[icode].operand[opnum].predicate) (opval, VOIDmode))
8596 {
8597 error ("constant argument out of range for %qs", insn_data[icode].name);
8598 return FALSE;
8599 }
8600 return TRUE;
8601 }
8602
8603 /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET
8604 if it's not null, has the right mode, and satisfies operand 0's
8605 predicate. */
8606
8607 static rtx
frv_legitimize_target(enum insn_code icode,rtx target)8608 frv_legitimize_target (enum insn_code icode, rtx target)
8609 {
8610 machine_mode mode = insn_data[icode].operand[0].mode;
8611
8612 if (! target
8613 || GET_MODE (target) != mode
8614 || ! (*insn_data[icode].operand[0].predicate) (target, mode))
8615 return gen_reg_rtx (mode);
8616 else
8617 return target;
8618 }
8619
8620 /* Given that ARG is being passed as operand OPNUM to instruction ICODE,
8621 check whether ARG satisfies the operand's constraints. If it doesn't,
8622 copy ARG to a temporary register and return that. Otherwise return ARG
8623 itself. */
8624
8625 static rtx
frv_legitimize_argument(enum insn_code icode,int opnum,rtx arg)8626 frv_legitimize_argument (enum insn_code icode, int opnum, rtx arg)
8627 {
8628 machine_mode mode = insn_data[icode].operand[opnum].mode;
8629
8630 if ((*insn_data[icode].operand[opnum].predicate) (arg, mode))
8631 return arg;
8632 else
8633 return copy_to_mode_reg (mode, arg);
8634 }
8635
8636 /* Return a volatile memory reference of mode MODE whose address is ARG. */
8637
8638 static rtx
frv_volatile_memref(machine_mode mode,rtx arg)8639 frv_volatile_memref (machine_mode mode, rtx arg)
8640 {
8641 rtx mem;
8642
8643 mem = gen_rtx_MEM (mode, memory_address (mode, arg));
8644 MEM_VOLATILE_P (mem) = 1;
8645 return mem;
8646 }
8647
8648 /* Expand builtins that take a single, constant argument. At the moment,
8649 only MHDSETS falls into this category. */
8650
8651 static rtx
frv_expand_set_builtin(enum insn_code icode,tree call,rtx target)8652 frv_expand_set_builtin (enum insn_code icode, tree call, rtx target)
8653 {
8654 rtx pat;
8655 rtx op0 = frv_read_argument (call, 0);
8656
8657 if (! frv_check_constant_argument (icode, 1, op0))
8658 return NULL_RTX;
8659
8660 target = frv_legitimize_target (icode, target);
8661 pat = GEN_FCN (icode) (target, op0);
8662 if (! pat)
8663 return NULL_RTX;
8664
8665 emit_insn (pat);
8666 return target;
8667 }
8668
8669 /* Expand builtins that take one operand. */
8670
8671 static rtx
frv_expand_unop_builtin(enum insn_code icode,tree call,rtx target)8672 frv_expand_unop_builtin (enum insn_code icode, tree call, rtx target)
8673 {
8674 rtx pat;
8675 rtx op0 = frv_read_argument (call, 0);
8676
8677 target = frv_legitimize_target (icode, target);
8678 op0 = frv_legitimize_argument (icode, 1, op0);
8679 pat = GEN_FCN (icode) (target, op0);
8680 if (! pat)
8681 return NULL_RTX;
8682
8683 emit_insn (pat);
8684 return target;
8685 }
8686
8687 /* Expand builtins that take two operands. */
8688
8689 static rtx
frv_expand_binop_builtin(enum insn_code icode,tree call,rtx target)8690 frv_expand_binop_builtin (enum insn_code icode, tree call, rtx target)
8691 {
8692 rtx pat;
8693 rtx op0 = frv_read_argument (call, 0);
8694 rtx op1 = frv_read_argument (call, 1);
8695
8696 target = frv_legitimize_target (icode, target);
8697 op0 = frv_legitimize_argument (icode, 1, op0);
8698 op1 = frv_legitimize_argument (icode, 2, op1);
8699 pat = GEN_FCN (icode) (target, op0, op1);
8700 if (! pat)
8701 return NULL_RTX;
8702
8703 emit_insn (pat);
8704 return target;
8705 }
8706
8707 /* Expand cut-style builtins, which take two operands and an implicit ACCG
8708 one. */
8709
8710 static rtx
frv_expand_cut_builtin(enum insn_code icode,tree call,rtx target)8711 frv_expand_cut_builtin (enum insn_code icode, tree call, rtx target)
8712 {
8713 rtx pat;
8714 rtx op0 = frv_read_argument (call, 0);
8715 rtx op1 = frv_read_argument (call, 1);
8716 rtx op2;
8717
8718 target = frv_legitimize_target (icode, target);
8719 op0 = frv_int_to_acc (icode, 1, op0);
8720 if (! op0)
8721 return NULL_RTX;
8722
8723 if (icode == CODE_FOR_mdcutssi || GET_CODE (op1) == CONST_INT)
8724 {
8725 if (! frv_check_constant_argument (icode, 2, op1))
8726 return NULL_RTX;
8727 }
8728 else
8729 op1 = frv_legitimize_argument (icode, 2, op1);
8730
8731 op2 = frv_matching_accg_for_acc (op0);
8732 pat = GEN_FCN (icode) (target, op0, op1, op2);
8733 if (! pat)
8734 return NULL_RTX;
8735
8736 emit_insn (pat);
8737 return target;
8738 }
8739
8740 /* Expand builtins that take two operands and the second is immediate. */
8741
8742 static rtx
frv_expand_binopimm_builtin(enum insn_code icode,tree call,rtx target)8743 frv_expand_binopimm_builtin (enum insn_code icode, tree call, rtx target)
8744 {
8745 rtx pat;
8746 rtx op0 = frv_read_argument (call, 0);
8747 rtx op1 = frv_read_argument (call, 1);
8748
8749 if (! frv_check_constant_argument (icode, 2, op1))
8750 return NULL_RTX;
8751
8752 target = frv_legitimize_target (icode, target);
8753 op0 = frv_legitimize_argument (icode, 1, op0);
8754 pat = GEN_FCN (icode) (target, op0, op1);
8755 if (! pat)
8756 return NULL_RTX;
8757
8758 emit_insn (pat);
8759 return target;
8760 }
8761
8762 /* Expand builtins that take two operands, the first operand being a pointer to
8763 ints and return void. */
8764
8765 static rtx
frv_expand_voidbinop_builtin(enum insn_code icode,tree call)8766 frv_expand_voidbinop_builtin (enum insn_code icode, tree call)
8767 {
8768 rtx pat;
8769 rtx op0 = frv_read_argument (call, 0);
8770 rtx op1 = frv_read_argument (call, 1);
8771 machine_mode mode0 = insn_data[icode].operand[0].mode;
8772 rtx addr;
8773
8774 if (GET_CODE (op0) != MEM)
8775 {
8776 rtx reg = op0;
8777
8778 if (! offsettable_address_p (0, mode0, op0))
8779 {
8780 reg = gen_reg_rtx (Pmode);
8781 emit_insn (gen_rtx_SET (reg, op0));
8782 }
8783
8784 op0 = gen_rtx_MEM (SImode, reg);
8785 }
8786
8787 addr = XEXP (op0, 0);
8788 if (! offsettable_address_p (0, mode0, addr))
8789 addr = copy_to_mode_reg (Pmode, op0);
8790
8791 op0 = change_address (op0, V4SImode, addr);
8792 op1 = frv_legitimize_argument (icode, 1, op1);
8793 pat = GEN_FCN (icode) (op0, op1);
8794 if (! pat)
8795 return 0;
8796
8797 emit_insn (pat);
8798 return 0;
8799 }
8800
8801 /* Expand builtins that take two long operands and return void. */
8802
8803 static rtx
frv_expand_int_void2arg(enum insn_code icode,tree call)8804 frv_expand_int_void2arg (enum insn_code icode, tree call)
8805 {
8806 rtx pat;
8807 rtx op0 = frv_read_argument (call, 0);
8808 rtx op1 = frv_read_argument (call, 1);
8809
8810 op0 = frv_legitimize_argument (icode, 1, op0);
8811 op1 = frv_legitimize_argument (icode, 1, op1);
8812 pat = GEN_FCN (icode) (op0, op1);
8813 if (! pat)
8814 return NULL_RTX;
8815
8816 emit_insn (pat);
8817 return NULL_RTX;
8818 }
8819
8820 /* Expand prefetch builtins. These take a single address as argument. */
8821
8822 static rtx
frv_expand_prefetches(enum insn_code icode,tree call)8823 frv_expand_prefetches (enum insn_code icode, tree call)
8824 {
8825 rtx pat;
8826 rtx op0 = frv_read_argument (call, 0);
8827
8828 pat = GEN_FCN (icode) (force_reg (Pmode, op0));
8829 if (! pat)
8830 return 0;
8831
8832 emit_insn (pat);
8833 return 0;
8834 }
8835
8836 /* Expand builtins that take three operands and return void. The first
8837 argument must be a constant that describes a pair or quad accumulators. A
8838 fourth argument is created that is the accumulator guard register that
8839 corresponds to the accumulator. */
8840
8841 static rtx
frv_expand_voidtriop_builtin(enum insn_code icode,tree call)8842 frv_expand_voidtriop_builtin (enum insn_code icode, tree call)
8843 {
8844 rtx pat;
8845 rtx op0 = frv_read_argument (call, 0);
8846 rtx op1 = frv_read_argument (call, 1);
8847 rtx op2 = frv_read_argument (call, 2);
8848 rtx op3;
8849
8850 op0 = frv_int_to_acc (icode, 0, op0);
8851 if (! op0)
8852 return NULL_RTX;
8853
8854 op1 = frv_legitimize_argument (icode, 1, op1);
8855 op2 = frv_legitimize_argument (icode, 2, op2);
8856 op3 = frv_matching_accg_for_acc (op0);
8857 pat = GEN_FCN (icode) (op0, op1, op2, op3);
8858 if (! pat)
8859 return NULL_RTX;
8860
8861 emit_insn (pat);
8862 return NULL_RTX;
8863 }
8864
8865 /* Expand builtins that perform accumulator-to-accumulator operations.
8866 These builtins take two accumulator numbers as argument and return
8867 void. */
8868
8869 static rtx
frv_expand_voidaccop_builtin(enum insn_code icode,tree call)8870 frv_expand_voidaccop_builtin (enum insn_code icode, tree call)
8871 {
8872 rtx pat;
8873 rtx op0 = frv_read_argument (call, 0);
8874 rtx op1 = frv_read_argument (call, 1);
8875 rtx op2;
8876 rtx op3;
8877
8878 op0 = frv_int_to_acc (icode, 0, op0);
8879 if (! op0)
8880 return NULL_RTX;
8881
8882 op1 = frv_int_to_acc (icode, 1, op1);
8883 if (! op1)
8884 return NULL_RTX;
8885
8886 op2 = frv_matching_accg_for_acc (op0);
8887 op3 = frv_matching_accg_for_acc (op1);
8888 pat = GEN_FCN (icode) (op0, op1, op2, op3);
8889 if (! pat)
8890 return NULL_RTX;
8891
8892 emit_insn (pat);
8893 return NULL_RTX;
8894 }
8895
8896 /* Expand a __builtin_read* function. ICODE is the instruction code for the
8897 membar and TARGET_MODE is the mode that the loaded value should have. */
8898
8899 static rtx
frv_expand_load_builtin(enum insn_code icode,machine_mode target_mode,tree call,rtx target)8900 frv_expand_load_builtin (enum insn_code icode, machine_mode target_mode,
8901 tree call, rtx target)
8902 {
8903 rtx op0 = frv_read_argument (call, 0);
8904 rtx cookie = frv_io_address_cookie (op0);
8905
8906 if (target == 0 || !REG_P (target))
8907 target = gen_reg_rtx (target_mode);
8908 op0 = frv_volatile_memref (insn_data[icode].operand[0].mode, op0);
8909 convert_move (target, op0, 1);
8910 emit_insn (GEN_FCN (icode) (copy_rtx (op0), cookie, GEN_INT (FRV_IO_READ)));
8911 cfun->machine->has_membar_p = 1;
8912 return target;
8913 }
8914
8915 /* Likewise __builtin_write* functions. */
8916
8917 static rtx
frv_expand_store_builtin(enum insn_code icode,tree call)8918 frv_expand_store_builtin (enum insn_code icode, tree call)
8919 {
8920 rtx op0 = frv_read_argument (call, 0);
8921 rtx op1 = frv_read_argument (call, 1);
8922 rtx cookie = frv_io_address_cookie (op0);
8923
8924 op0 = frv_volatile_memref (insn_data[icode].operand[0].mode, op0);
8925 convert_move (op0, force_reg (insn_data[icode].operand[0].mode, op1), 1);
8926 emit_insn (GEN_FCN (icode) (copy_rtx (op0), cookie, GEN_INT (FRV_IO_WRITE)));
8927 cfun->machine->has_membar_p = 1;
8928 return NULL_RTX;
8929 }
8930
8931 /* Expand the MDPACKH builtin. It takes four unsigned short arguments and
8932 each argument forms one word of the two double-word input registers.
8933 CALL is the tree for the call and TARGET, if nonnull, suggests a good place
8934 to put the return value. */
8935
8936 static rtx
frv_expand_mdpackh_builtin(tree call,rtx target)8937 frv_expand_mdpackh_builtin (tree call, rtx target)
8938 {
8939 enum insn_code icode = CODE_FOR_mdpackh;
8940 rtx pat, op0, op1;
8941 rtx arg1 = frv_read_argument (call, 0);
8942 rtx arg2 = frv_read_argument (call, 1);
8943 rtx arg3 = frv_read_argument (call, 2);
8944 rtx arg4 = frv_read_argument (call, 3);
8945
8946 target = frv_legitimize_target (icode, target);
8947 op0 = gen_reg_rtx (DImode);
8948 op1 = gen_reg_rtx (DImode);
8949
8950 /* The high half of each word is not explicitly initialized, so indicate
8951 that the input operands are not live before this point. */
8952 emit_clobber (op0);
8953 emit_clobber (op1);
8954
8955 /* Move each argument into the low half of its associated input word. */
8956 emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 2), arg1);
8957 emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 6), arg2);
8958 emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 2), arg3);
8959 emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 6), arg4);
8960
8961 pat = GEN_FCN (icode) (target, op0, op1);
8962 if (! pat)
8963 return NULL_RTX;
8964
8965 emit_insn (pat);
8966 return target;
8967 }
8968
8969 /* Expand the MCLRACC builtin. This builtin takes a single accumulator
8970 number as argument. */
8971
8972 static rtx
frv_expand_mclracc_builtin(tree call)8973 frv_expand_mclracc_builtin (tree call)
8974 {
8975 enum insn_code icode = CODE_FOR_mclracc;
8976 rtx pat;
8977 rtx op0 = frv_read_argument (call, 0);
8978
8979 op0 = frv_int_to_acc (icode, 0, op0);
8980 if (! op0)
8981 return NULL_RTX;
8982
8983 pat = GEN_FCN (icode) (op0);
8984 if (pat)
8985 emit_insn (pat);
8986
8987 return NULL_RTX;
8988 }
8989
8990 /* Expand builtins that take no arguments. */
8991
8992 static rtx
frv_expand_noargs_builtin(enum insn_code icode)8993 frv_expand_noargs_builtin (enum insn_code icode)
8994 {
8995 rtx pat = GEN_FCN (icode) (const0_rtx);
8996 if (pat)
8997 emit_insn (pat);
8998
8999 return NULL_RTX;
9000 }
9001
9002 /* Expand MRDACC and MRDACCG. These builtins take a single accumulator
9003 number or accumulator guard number as argument and return an SI integer. */
9004
9005 static rtx
frv_expand_mrdacc_builtin(enum insn_code icode,tree call)9006 frv_expand_mrdacc_builtin (enum insn_code icode, tree call)
9007 {
9008 rtx pat;
9009 rtx target = gen_reg_rtx (SImode);
9010 rtx op0 = frv_read_argument (call, 0);
9011
9012 op0 = frv_int_to_acc (icode, 1, op0);
9013 if (! op0)
9014 return NULL_RTX;
9015
9016 pat = GEN_FCN (icode) (target, op0);
9017 if (! pat)
9018 return NULL_RTX;
9019
9020 emit_insn (pat);
9021 return target;
9022 }
9023
9024 /* Expand MWTACC and MWTACCG. These builtins take an accumulator or
9025 accumulator guard as their first argument and an SImode value as their
9026 second. */
9027
9028 static rtx
frv_expand_mwtacc_builtin(enum insn_code icode,tree call)9029 frv_expand_mwtacc_builtin (enum insn_code icode, tree call)
9030 {
9031 rtx pat;
9032 rtx op0 = frv_read_argument (call, 0);
9033 rtx op1 = frv_read_argument (call, 1);
9034
9035 op0 = frv_int_to_acc (icode, 0, op0);
9036 if (! op0)
9037 return NULL_RTX;
9038
9039 op1 = frv_legitimize_argument (icode, 1, op1);
9040 pat = GEN_FCN (icode) (op0, op1);
9041 if (pat)
9042 emit_insn (pat);
9043
9044 return NULL_RTX;
9045 }
9046
9047 /* Emit a move from SRC to DEST in SImode chunks. This can be used
9048 to move DImode values into and out of IACC0. */
9049
9050 static void
frv_split_iacc_move(rtx dest,rtx src)9051 frv_split_iacc_move (rtx dest, rtx src)
9052 {
9053 machine_mode inner;
9054 int i;
9055
9056 inner = GET_MODE (dest);
9057 for (i = 0; i < GET_MODE_SIZE (inner); i += GET_MODE_SIZE (SImode))
9058 emit_move_insn (simplify_gen_subreg (SImode, dest, inner, i),
9059 simplify_gen_subreg (SImode, src, inner, i));
9060 }
9061
9062 /* Expand builtins. */
9063
9064 static rtx
frv_expand_builtin(tree exp,rtx target,rtx subtarget ATTRIBUTE_UNUSED,machine_mode mode ATTRIBUTE_UNUSED,int ignore ATTRIBUTE_UNUSED)9065 frv_expand_builtin (tree exp,
9066 rtx target,
9067 rtx subtarget ATTRIBUTE_UNUSED,
9068 machine_mode mode ATTRIBUTE_UNUSED,
9069 int ignore ATTRIBUTE_UNUSED)
9070 {
9071 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
9072 unsigned fcode = DECL_MD_FUNCTION_CODE (fndecl);
9073 unsigned i;
9074 struct builtin_description *d;
9075
9076 if (fcode < FRV_BUILTIN_FIRST_NONMEDIA && !TARGET_MEDIA)
9077 {
9078 error ("media functions are not available unless %<-mmedia%> is used");
9079 return NULL_RTX;
9080 }
9081
9082 switch (fcode)
9083 {
9084 case FRV_BUILTIN_MCOP1:
9085 case FRV_BUILTIN_MCOP2:
9086 case FRV_BUILTIN_MDUNPACKH:
9087 case FRV_BUILTIN_MBTOHE:
9088 if (! TARGET_MEDIA_REV1)
9089 {
9090 error ("this media function is only available on the fr500");
9091 return NULL_RTX;
9092 }
9093 break;
9094
9095 case FRV_BUILTIN_MQXMACHS:
9096 case FRV_BUILTIN_MQXMACXHS:
9097 case FRV_BUILTIN_MQMACXHS:
9098 case FRV_BUILTIN_MADDACCS:
9099 case FRV_BUILTIN_MSUBACCS:
9100 case FRV_BUILTIN_MASACCS:
9101 case FRV_BUILTIN_MDADDACCS:
9102 case FRV_BUILTIN_MDSUBACCS:
9103 case FRV_BUILTIN_MDASACCS:
9104 case FRV_BUILTIN_MABSHS:
9105 case FRV_BUILTIN_MDROTLI:
9106 case FRV_BUILTIN_MCPLHI:
9107 case FRV_BUILTIN_MCPLI:
9108 case FRV_BUILTIN_MDCUTSSI:
9109 case FRV_BUILTIN_MQSATHS:
9110 case FRV_BUILTIN_MHSETLOS:
9111 case FRV_BUILTIN_MHSETLOH:
9112 case FRV_BUILTIN_MHSETHIS:
9113 case FRV_BUILTIN_MHSETHIH:
9114 case FRV_BUILTIN_MHDSETS:
9115 case FRV_BUILTIN_MHDSETH:
9116 if (! TARGET_MEDIA_REV2)
9117 {
9118 error ("this media function is only available on the fr400"
9119 " and fr550");
9120 return NULL_RTX;
9121 }
9122 break;
9123
9124 case FRV_BUILTIN_SMASS:
9125 case FRV_BUILTIN_SMSSS:
9126 case FRV_BUILTIN_SMU:
9127 case FRV_BUILTIN_ADDSS:
9128 case FRV_BUILTIN_SUBSS:
9129 case FRV_BUILTIN_SLASS:
9130 case FRV_BUILTIN_SCUTSS:
9131 case FRV_BUILTIN_IACCreadll:
9132 case FRV_BUILTIN_IACCreadl:
9133 case FRV_BUILTIN_IACCsetll:
9134 case FRV_BUILTIN_IACCsetl:
9135 if (!TARGET_FR405_BUILTINS)
9136 {
9137 error ("this built-in function is only available"
9138 " on the fr405 and fr450");
9139 return NULL_RTX;
9140 }
9141 break;
9142
9143 case FRV_BUILTIN_PREFETCH:
9144 if (!TARGET_FR500_FR550_BUILTINS)
9145 {
9146 error ("this built-in function is only available on the fr500"
9147 " and fr550");
9148 return NULL_RTX;
9149 }
9150 break;
9151
9152 case FRV_BUILTIN_MQLCLRHS:
9153 case FRV_BUILTIN_MQLMTHS:
9154 case FRV_BUILTIN_MQSLLHI:
9155 case FRV_BUILTIN_MQSRAHI:
9156 if (!TARGET_MEDIA_FR450)
9157 {
9158 error ("this built-in function is only available on the fr450");
9159 return NULL_RTX;
9160 }
9161 break;
9162
9163 default:
9164 break;
9165 }
9166
9167 /* Expand unique builtins. */
9168
9169 switch (fcode)
9170 {
9171 case FRV_BUILTIN_MTRAP:
9172 return frv_expand_noargs_builtin (CODE_FOR_mtrap);
9173
9174 case FRV_BUILTIN_MCLRACC:
9175 return frv_expand_mclracc_builtin (exp);
9176
9177 case FRV_BUILTIN_MCLRACCA:
9178 if (TARGET_ACC_8)
9179 return frv_expand_noargs_builtin (CODE_FOR_mclracca8);
9180 else
9181 return frv_expand_noargs_builtin (CODE_FOR_mclracca4);
9182
9183 case FRV_BUILTIN_MRDACC:
9184 return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc, exp);
9185
9186 case FRV_BUILTIN_MRDACCG:
9187 return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg, exp);
9188
9189 case FRV_BUILTIN_MWTACC:
9190 return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc, exp);
9191
9192 case FRV_BUILTIN_MWTACCG:
9193 return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg, exp);
9194
9195 case FRV_BUILTIN_MDPACKH:
9196 return frv_expand_mdpackh_builtin (exp, target);
9197
9198 case FRV_BUILTIN_IACCreadll:
9199 {
9200 rtx src = frv_read_iacc_argument (DImode, exp, 0);
9201 if (target == 0 || !REG_P (target))
9202 target = gen_reg_rtx (DImode);
9203 frv_split_iacc_move (target, src);
9204 return target;
9205 }
9206
9207 case FRV_BUILTIN_IACCreadl:
9208 return frv_read_iacc_argument (SImode, exp, 0);
9209
9210 case FRV_BUILTIN_IACCsetll:
9211 {
9212 rtx dest = frv_read_iacc_argument (DImode, exp, 0);
9213 rtx src = frv_read_argument (exp, 1);
9214 frv_split_iacc_move (dest, force_reg (DImode, src));
9215 return 0;
9216 }
9217
9218 case FRV_BUILTIN_IACCsetl:
9219 {
9220 rtx dest = frv_read_iacc_argument (SImode, exp, 0);
9221 rtx src = frv_read_argument (exp, 1);
9222 emit_move_insn (dest, force_reg (SImode, src));
9223 return 0;
9224 }
9225
9226 default:
9227 break;
9228 }
9229
9230 /* Expand groups of builtins. */
9231
9232 for (i = 0, d = bdesc_set; i < ARRAY_SIZE (bdesc_set); i++, d++)
9233 if (d->code == fcode)
9234 return frv_expand_set_builtin (d->icode, exp, target);
9235
9236 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
9237 if (d->code == fcode)
9238 return frv_expand_unop_builtin (d->icode, exp, target);
9239
9240 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
9241 if (d->code == fcode)
9242 return frv_expand_binop_builtin (d->icode, exp, target);
9243
9244 for (i = 0, d = bdesc_cut; i < ARRAY_SIZE (bdesc_cut); i++, d++)
9245 if (d->code == fcode)
9246 return frv_expand_cut_builtin (d->icode, exp, target);
9247
9248 for (i = 0, d = bdesc_2argimm; i < ARRAY_SIZE (bdesc_2argimm); i++, d++)
9249 if (d->code == fcode)
9250 return frv_expand_binopimm_builtin (d->icode, exp, target);
9251
9252 for (i = 0, d = bdesc_void2arg; i < ARRAY_SIZE (bdesc_void2arg); i++, d++)
9253 if (d->code == fcode)
9254 return frv_expand_voidbinop_builtin (d->icode, exp);
9255
9256 for (i = 0, d = bdesc_void3arg; i < ARRAY_SIZE (bdesc_void3arg); i++, d++)
9257 if (d->code == fcode)
9258 return frv_expand_voidtriop_builtin (d->icode, exp);
9259
9260 for (i = 0, d = bdesc_voidacc; i < ARRAY_SIZE (bdesc_voidacc); i++, d++)
9261 if (d->code == fcode)
9262 return frv_expand_voidaccop_builtin (d->icode, exp);
9263
9264 for (i = 0, d = bdesc_int_void2arg;
9265 i < ARRAY_SIZE (bdesc_int_void2arg); i++, d++)
9266 if (d->code == fcode)
9267 return frv_expand_int_void2arg (d->icode, exp);
9268
9269 for (i = 0, d = bdesc_prefetches;
9270 i < ARRAY_SIZE (bdesc_prefetches); i++, d++)
9271 if (d->code == fcode)
9272 return frv_expand_prefetches (d->icode, exp);
9273
9274 for (i = 0, d = bdesc_loads; i < ARRAY_SIZE (bdesc_loads); i++, d++)
9275 if (d->code == fcode)
9276 return frv_expand_load_builtin (d->icode, TYPE_MODE (TREE_TYPE (exp)),
9277 exp, target);
9278
9279 for (i = 0, d = bdesc_stores; i < ARRAY_SIZE (bdesc_stores); i++, d++)
9280 if (d->code == fcode)
9281 return frv_expand_store_builtin (d->icode, exp);
9282
9283 return 0;
9284 }
9285
9286 static bool
frv_in_small_data_p(const_tree decl)9287 frv_in_small_data_p (const_tree decl)
9288 {
9289 HOST_WIDE_INT size;
9290 const char *section_name;
9291
9292 /* Don't apply the -G flag to internal compiler structures. We
9293 should leave such structures in the main data section, partly
9294 for efficiency and partly because the size of some of them
9295 (such as C++ typeinfos) is not known until later. */
9296 if (TREE_CODE (decl) != VAR_DECL || DECL_ARTIFICIAL (decl))
9297 return false;
9298
9299 /* If we already know which section the decl should be in, see if
9300 it's a small data section. */
9301 section_name = DECL_SECTION_NAME (decl);
9302 if (section_name)
9303 {
9304 if (startswith (section_name, ".sdata"))
9305 return true;
9306 if (startswith (section_name, ".sbss"))
9307 return true;
9308 return false;
9309 }
9310
9311 size = int_size_in_bytes (TREE_TYPE (decl));
9312 if (size > 0 && size <= g_switch_value)
9313 return true;
9314
9315 return false;
9316 }
9317
9318 static bool
frv_rtx_costs(rtx x,machine_mode mode,int outer_code,int opno ATTRIBUTE_UNUSED,int * total,bool speed ATTRIBUTE_UNUSED)9319 frv_rtx_costs (rtx x,
9320 machine_mode mode,
9321 int outer_code,
9322 int opno ATTRIBUTE_UNUSED,
9323 int *total,
9324 bool speed ATTRIBUTE_UNUSED)
9325 {
9326 int code = GET_CODE (x);
9327
9328 if (outer_code == MEM)
9329 {
9330 /* Don't differentiate between memory addresses. All the ones
9331 we accept have equal cost. */
9332 *total = COSTS_N_INSNS (0);
9333 return true;
9334 }
9335
9336 switch (code)
9337 {
9338 case CONST_INT:
9339 /* Make 12-bit integers really cheap. */
9340 if (IN_RANGE (INTVAL (x), -2048, 2047))
9341 {
9342 *total = 0;
9343 return true;
9344 }
9345 /* Fall through. */
9346
9347 case CONST:
9348 case LABEL_REF:
9349 case SYMBOL_REF:
9350 case CONST_DOUBLE:
9351 *total = COSTS_N_INSNS (2);
9352 return true;
9353
9354 case PLUS:
9355 case MINUS:
9356 case AND:
9357 case IOR:
9358 case XOR:
9359 case ASHIFT:
9360 case ASHIFTRT:
9361 case LSHIFTRT:
9362 case NOT:
9363 case NEG:
9364 case COMPARE:
9365 if (mode == SImode)
9366 *total = COSTS_N_INSNS (1);
9367 else if (mode == DImode)
9368 *total = COSTS_N_INSNS (2);
9369 else
9370 *total = COSTS_N_INSNS (3);
9371 return true;
9372
9373 case MULT:
9374 if (mode == SImode)
9375 *total = COSTS_N_INSNS (2);
9376 else
9377 *total = COSTS_N_INSNS (6); /* guess */
9378 return true;
9379
9380 case DIV:
9381 case UDIV:
9382 case MOD:
9383 case UMOD:
9384 *total = COSTS_N_INSNS (18);
9385 return true;
9386
9387 case MEM:
9388 *total = COSTS_N_INSNS (3);
9389 return true;
9390
9391 default:
9392 return false;
9393 }
9394 }
9395
9396 static void
frv_asm_out_constructor(rtx symbol,int priority ATTRIBUTE_UNUSED)9397 frv_asm_out_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9398 {
9399 switch_to_section (ctors_section);
9400 assemble_align (POINTER_SIZE);
9401 if (TARGET_FDPIC)
9402 {
9403 int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1);
9404
9405 gcc_assert (ok);
9406 return;
9407 }
9408 assemble_integer_with_op ("\t.picptr\t", symbol);
9409 }
9410
9411 static void
frv_asm_out_destructor(rtx symbol,int priority ATTRIBUTE_UNUSED)9412 frv_asm_out_destructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9413 {
9414 switch_to_section (dtors_section);
9415 assemble_align (POINTER_SIZE);
9416 if (TARGET_FDPIC)
9417 {
9418 int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1);
9419
9420 gcc_assert (ok);
9421 return;
9422 }
9423 assemble_integer_with_op ("\t.picptr\t", symbol);
9424 }
9425
9426 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9427
9428 static rtx
frv_struct_value_rtx(tree fntype ATTRIBUTE_UNUSED,int incoming ATTRIBUTE_UNUSED)9429 frv_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
9430 int incoming ATTRIBUTE_UNUSED)
9431 {
9432 return gen_rtx_REG (Pmode, FRV_STRUCT_VALUE_REGNUM);
9433 }
9434
9435 #define TLS_BIAS (2048 - 16)
9436
9437 /* This is called from dwarf2out.cc via TARGET_ASM_OUTPUT_DWARF_DTPREL.
9438 We need to emit DTP-relative relocations. */
9439
9440 static void
frv_output_dwarf_dtprel(FILE * file,int size,rtx x)9441 frv_output_dwarf_dtprel (FILE *file, int size, rtx x)
9442 {
9443 gcc_assert (size == 4);
9444 fputs ("\t.picptr\ttlsmoff(", file);
9445 /* We want the unbiased TLS offset, so add the bias to the
9446 expression, such that the implicit biasing cancels out. */
9447 output_addr_const (file, plus_constant (Pmode, x, TLS_BIAS));
9448 fputs (")", file);
9449 }
9450
9451 #include "gt-frv.h"
9452