1 /*-
2 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
3 * Copyright (C) 1995, 1996 TooLs GmbH.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by TooLs GmbH.
17 * 4. The name of TooLs GmbH may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 *
31 * $NetBSD: trap.c,v 1.58 2002/03/04 04:07:35 dbj Exp $
32 */
33
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
36
37 #include <sys/param.h>
38 #include <sys/kdb.h>
39 #include <sys/proc.h>
40 #include <sys/ktr.h>
41 #include <sys/lock.h>
42 #include <sys/mutex.h>
43 #include <sys/pioctl.h>
44 #include <sys/ptrace.h>
45 #include <sys/reboot.h>
46 #include <sys/syscall.h>
47 #include <sys/sysent.h>
48 #include <sys/systm.h>
49 #include <sys/kernel.h>
50 #include <sys/uio.h>
51 #include <sys/signalvar.h>
52 #include <sys/vmmeter.h>
53
54 #include <security/audit/audit.h>
55
56 #include <vm/vm.h>
57 #include <vm/pmap.h>
58 #include <vm/vm_extern.h>
59 #include <vm/vm_param.h>
60 #include <vm/vm_kern.h>
61 #include <vm/vm_map.h>
62 #include <vm/vm_page.h>
63
64 #include <machine/_inttypes.h>
65 #include <machine/altivec.h>
66 #include <machine/cpu.h>
67 #include <machine/db_machdep.h>
68 #include <machine/fpu.h>
69 #include <machine/frame.h>
70 #include <machine/pcb.h>
71 #include <machine/pmap.h>
72 #include <machine/psl.h>
73 #include <machine/trap.h>
74 #include <machine/spr.h>
75 #include <machine/sr.h>
76
77 /* Below matches setjmp.S */
78 #define FAULTBUF_LR 21
79 #define FAULTBUF_R1 1
80 #define FAULTBUF_R2 2
81 #define FAULTBUF_CR 22
82 #define FAULTBUF_R14 3
83
84 static void trap_fatal(struct trapframe *frame);
85 static void printtrap(u_int vector, struct trapframe *frame, int isfatal,
86 int user);
87 static int trap_pfault(struct trapframe *frame, int user);
88 static int fix_unaligned(struct thread *td, struct trapframe *frame);
89 static int handle_onfault(struct trapframe *frame);
90 static void syscall(struct trapframe *frame);
91
92 #ifdef __powerpc64__
93 void handle_kernel_slb_spill(int, register_t, register_t);
94 static int handle_user_slb_spill(pmap_t pm, vm_offset_t addr);
95 extern int n_slbs;
96 #endif
97
98 struct powerpc_exception {
99 u_int vector;
100 char *name;
101 };
102
103 #ifdef KDTRACE_HOOKS
104 #include <sys/dtrace_bsd.h>
105
106 int (*dtrace_invop_jump_addr)(struct trapframe *);
107 #endif
108
109 static struct powerpc_exception powerpc_exceptions[] = {
110 { EXC_CRIT, "critical input" },
111 { EXC_RST, "system reset" },
112 { EXC_MCHK, "machine check" },
113 { EXC_DSI, "data storage interrupt" },
114 { EXC_DSE, "data segment exception" },
115 { EXC_ISI, "instruction storage interrupt" },
116 { EXC_ISE, "instruction segment exception" },
117 { EXC_EXI, "external interrupt" },
118 { EXC_ALI, "alignment" },
119 { EXC_PGM, "program" },
120 { EXC_FPU, "floating-point unavailable" },
121 { EXC_APU, "auxiliary proc unavailable" },
122 { EXC_DECR, "decrementer" },
123 { EXC_FIT, "fixed-interval timer" },
124 { EXC_WDOG, "watchdog timer" },
125 { EXC_SC, "system call" },
126 { EXC_TRC, "trace" },
127 { EXC_FPA, "floating-point assist" },
128 { EXC_DEBUG, "debug" },
129 { EXC_PERF, "performance monitoring" },
130 { EXC_VEC, "altivec unavailable" },
131 { EXC_VSX, "vsx unavailable" },
132 { EXC_ITMISS, "instruction tlb miss" },
133 { EXC_DLMISS, "data load tlb miss" },
134 { EXC_DSMISS, "data store tlb miss" },
135 { EXC_BPT, "instruction breakpoint" },
136 { EXC_SMI, "system management" },
137 { EXC_VECAST_G4, "altivec assist" },
138 { EXC_THRM, "thermal management" },
139 { EXC_RUNMODETRC, "run mode/trace" },
140 { EXC_LAST, NULL }
141 };
142
143 static const char *
trapname(u_int vector)144 trapname(u_int vector)
145 {
146 struct powerpc_exception *pe;
147
148 for (pe = powerpc_exceptions; pe->vector != EXC_LAST; pe++) {
149 if (pe->vector == vector)
150 return (pe->name);
151 }
152
153 return ("unknown");
154 }
155
156 void
trap(struct trapframe * frame)157 trap(struct trapframe *frame)
158 {
159 struct thread *td;
160 struct proc *p;
161 #ifdef KDTRACE_HOOKS
162 uint32_t inst;
163 #endif
164 int sig, type, user;
165 u_int ucode;
166 ksiginfo_t ksi;
167
168 PCPU_INC(cnt.v_trap);
169
170 td = curthread;
171 p = td->td_proc;
172
173 type = ucode = frame->exc;
174 sig = 0;
175 user = frame->srr1 & PSL_PR;
176
177 CTR3(KTR_TRAP, "trap: %s type=%s (%s)", td->td_name,
178 trapname(type), user ? "user" : "kernel");
179
180 #ifdef KDTRACE_HOOKS
181 /*
182 * A trap can occur while DTrace executes a probe. Before
183 * executing the probe, DTrace blocks re-scheduling and sets
184 * a flag in its per-cpu flags to indicate that it doesn't
185 * want to fault. On returning from the probe, the no-fault
186 * flag is cleared and finally re-scheduling is enabled.
187 *
188 * If the DTrace kernel module has registered a trap handler,
189 * call it and if it returns non-zero, assume that it has
190 * handled the trap and modified the trap frame so that this
191 * function can return normally.
192 */
193 if (dtrace_trap_func != NULL && (*dtrace_trap_func)(frame, type) != 0)
194 return;
195 #endif
196
197 if (user) {
198 td->td_pticks = 0;
199 td->td_frame = frame;
200 if (td->td_cowgen != p->p_cowgen)
201 thread_cow_update(td);
202
203 /* User Mode Traps */
204 switch (type) {
205 case EXC_RUNMODETRC:
206 case EXC_TRC:
207 frame->srr1 &= ~PSL_SE;
208 sig = SIGTRAP;
209 ucode = TRAP_TRACE;
210 break;
211
212 #ifdef __powerpc64__
213 case EXC_ISE:
214 case EXC_DSE:
215 if (handle_user_slb_spill(&p->p_vmspace->vm_pmap,
216 (type == EXC_ISE) ? frame->srr0 : frame->dar) != 0){
217 sig = SIGSEGV;
218 ucode = SEGV_MAPERR;
219 }
220 break;
221 #endif
222 case EXC_DSI:
223 case EXC_ISI:
224 sig = trap_pfault(frame, 1);
225 if (sig == SIGSEGV)
226 ucode = SEGV_MAPERR;
227 break;
228
229 case EXC_SC:
230 syscall(frame);
231 break;
232
233 case EXC_FPU:
234 KASSERT((td->td_pcb->pcb_flags & PCB_FPU) != PCB_FPU,
235 ("FPU already enabled for thread"));
236 enable_fpu(td);
237 break;
238
239 case EXC_VEC:
240 KASSERT((td->td_pcb->pcb_flags & PCB_VEC) != PCB_VEC,
241 ("Altivec already enabled for thread"));
242 enable_vec(td);
243 break;
244
245 case EXC_VSX:
246 KASSERT((td->td_pcb->pcb_flags & PCB_VSX) != PCB_VSX,
247 ("VSX already enabled for thread"));
248 if (!(td->td_pcb->pcb_flags & PCB_VEC))
249 enable_vec(td);
250 if (!(td->td_pcb->pcb_flags & PCB_FPU))
251 save_fpu(td);
252 td->td_pcb->pcb_flags |= PCB_VSX;
253 enable_fpu(td);
254 break;
255
256 case EXC_VECAST_E:
257 case EXC_VECAST_G4:
258 case EXC_VECAST_G5:
259 /*
260 * We get a VPU assist exception for IEEE mode
261 * vector operations on denormalized floats.
262 * Emulating this is a giant pain, so for now,
263 * just switch off IEEE mode and treat them as
264 * zero.
265 */
266
267 save_vec(td);
268 td->td_pcb->pcb_vec.vscr |= ALTIVEC_VSCR_NJ;
269 enable_vec(td);
270 break;
271
272 case EXC_ALI:
273 if (fix_unaligned(td, frame) != 0) {
274 sig = SIGBUS;
275 ucode = BUS_ADRALN;
276 }
277 else
278 frame->srr0 += 4;
279 break;
280
281 case EXC_DEBUG: /* Single stepping */
282 mtspr(SPR_DBSR, mfspr(SPR_DBSR));
283 frame->srr1 &= ~PSL_DE;
284 frame->cpu.booke.dbcr0 &= ~(DBCR0_IDM || DBCR0_IC);
285 sig = SIGTRAP;
286 ucode = TRAP_TRACE;
287 break;
288
289 case EXC_PGM:
290 /* Identify the trap reason */
291 #ifdef AIM
292 if (frame->srr1 & EXC_PGM_TRAP) {
293 #else
294 if (frame->cpu.booke.esr & ESR_PTR) {
295 #endif
296 #ifdef KDTRACE_HOOKS
297 inst = fuword32((const void *)frame->srr0);
298 if (inst == 0x0FFFDDDD &&
299 dtrace_pid_probe_ptr != NULL) {
300 struct reg regs;
301 fill_regs(td, ®s);
302 (*dtrace_pid_probe_ptr)(®s);
303 break;
304 }
305 #endif
306 sig = SIGTRAP;
307 ucode = TRAP_BRKPT;
308 } else {
309 sig = ppc_instr_emulate(frame, td->td_pcb);
310 if (sig == SIGILL) {
311 if (frame->srr1 & EXC_PGM_PRIV)
312 ucode = ILL_PRVOPC;
313 else if (frame->srr1 & EXC_PGM_ILLEGAL)
314 ucode = ILL_ILLOPC;
315 } else if (sig == SIGFPE)
316 ucode = FPE_FLTINV; /* Punt for now, invalid operation. */
317 }
318 break;
319
320 case EXC_MCHK:
321 /*
322 * Note that this may not be recoverable for the user
323 * process, depending on the type of machine check,
324 * but it at least prevents the kernel from dying.
325 */
326 sig = SIGBUS;
327 ucode = BUS_OBJERR;
328 break;
329
330 default:
331 trap_fatal(frame);
332 }
333 } else {
334 /* Kernel Mode Traps */
335
336 KASSERT(cold || td->td_ucred != NULL,
337 ("kernel trap doesn't have ucred"));
338 switch (type) {
339 #ifdef KDTRACE_HOOKS
340 case EXC_PGM:
341 if (frame->srr1 & EXC_PGM_TRAP) {
342 if (*(uint32_t *)frame->srr0 == EXC_DTRACE) {
343 if (dtrace_invop_jump_addr != NULL) {
344 dtrace_invop_jump_addr(frame);
345 return;
346 }
347 }
348 }
349 break;
350 #endif
351 #ifdef __powerpc64__
352 case EXC_DSE:
353 if ((frame->dar & SEGMENT_MASK) == USER_ADDR) {
354 __asm __volatile ("slbmte %0, %1" ::
355 "r"(td->td_pcb->pcb_cpu.aim.usr_vsid),
356 "r"(USER_SLB_SLBE));
357 return;
358 }
359 break;
360 #endif
361 case EXC_DSI:
362 if (trap_pfault(frame, 0) == 0)
363 return;
364 break;
365 case EXC_MCHK:
366 if (handle_onfault(frame))
367 return;
368 break;
369 default:
370 break;
371 }
372 trap_fatal(frame);
373 }
374
375 if (sig != 0) {
376 if (p->p_sysent->sv_transtrap != NULL)
377 sig = (p->p_sysent->sv_transtrap)(sig, type);
378 ksiginfo_init_trap(&ksi);
379 ksi.ksi_signo = sig;
380 ksi.ksi_code = (int) ucode; /* XXX, not POSIX */
381 /* ksi.ksi_addr = ? */
382 ksi.ksi_trapno = type;
383 trapsignal(td, &ksi);
384 }
385
386 userret(td, frame);
387 }
388
389 static void
390 trap_fatal(struct trapframe *frame)
391 {
392
393 printtrap(frame->exc, frame, 1, (frame->srr1 & PSL_PR));
394 #ifdef KDB
395 if ((debugger_on_panic || kdb_active) &&
396 kdb_trap(frame->exc, 0, frame))
397 return;
398 #endif
399 panic("%s trap", trapname(frame->exc));
400 }
401
402 static void
403 printtrap(u_int vector, struct trapframe *frame, int isfatal, int user)
404 {
405 uint16_t ver;
406 #ifdef BOOKE
407 vm_paddr_t pa;
408 #endif
409
410 printf("\n");
411 printf("%s %s trap:\n", isfatal ? "fatal" : "handled",
412 user ? "user" : "kernel");
413 printf("\n");
414 printf(" exception = 0x%x (%s)\n", vector, trapname(vector));
415 switch (vector) {
416 case EXC_DSE:
417 case EXC_DSI:
418 case EXC_DTMISS:
419 printf(" virtual address = 0x%" PRIxPTR "\n", frame->dar);
420 #ifdef AIM
421 printf(" dsisr = 0x%lx\n",
422 (u_long)frame->cpu.aim.dsisr);
423 #endif
424 break;
425 case EXC_ISE:
426 case EXC_ISI:
427 case EXC_ITMISS:
428 printf(" virtual address = 0x%" PRIxPTR "\n", frame->srr0);
429 break;
430 case EXC_MCHK:
431 ver = mfpvr() >> 16;
432 #if defined(AIM)
433 if (MPC745X_P(ver))
434 printf(" msssr0 = 0x%lx\n",
435 (u_long)mfspr(SPR_MSSSR0));
436 #elif defined(BOOKE)
437 pa = mfspr(SPR_MCARU);
438 pa = (pa << 32) | mfspr(SPR_MCAR);
439 printf(" mcsr = 0x%lx\n", (u_long)mfspr(SPR_MCSR));
440 printf(" mcar = 0x%jx\n", (uintmax_t)pa);
441 #endif
442 break;
443 }
444 #ifdef BOOKE
445 printf(" esr = 0x%" PRIxPTR "\n",
446 frame->cpu.booke.esr);
447 #endif
448 printf(" srr0 = 0x%" PRIxPTR "\n", frame->srr0);
449 printf(" srr1 = 0x%lx\n", (u_long)frame->srr1);
450 printf(" lr = 0x%" PRIxPTR "\n", frame->lr);
451 printf(" curthread = %p\n", curthread);
452 if (curthread != NULL)
453 printf(" pid = %d, comm = %s\n",
454 curthread->td_proc->p_pid, curthread->td_name);
455 printf("\n");
456 }
457
458 /*
459 * Handles a fatal fault when we have onfault state to recover. Returns
460 * non-zero if there was onfault recovery state available.
461 */
462 static int
463 handle_onfault(struct trapframe *frame)
464 {
465 struct thread *td;
466 jmp_buf *fb;
467
468 td = curthread;
469 fb = td->td_pcb->pcb_onfault;
470 if (fb != NULL) {
471 frame->srr0 = (*fb)->_jb[FAULTBUF_LR];
472 frame->fixreg[1] = (*fb)->_jb[FAULTBUF_R1];
473 frame->fixreg[2] = (*fb)->_jb[FAULTBUF_R2];
474 frame->fixreg[3] = 1;
475 frame->cr = (*fb)->_jb[FAULTBUF_CR];
476 bcopy(&(*fb)->_jb[FAULTBUF_R14], &frame->fixreg[14],
477 18 * sizeof(register_t));
478 td->td_pcb->pcb_onfault = NULL; /* Returns twice, not thrice */
479 return (1);
480 }
481 return (0);
482 }
483
484 int
485 cpu_fetch_syscall_args(struct thread *td, struct syscall_args *sa)
486 {
487 struct proc *p;
488 struct trapframe *frame;
489 caddr_t params;
490 size_t argsz;
491 int error, n, i;
492
493 p = td->td_proc;
494 frame = td->td_frame;
495
496 sa->code = frame->fixreg[0];
497 params = (caddr_t)(frame->fixreg + FIRSTARG);
498 n = NARGREG;
499
500 if (sa->code == SYS_syscall) {
501 /*
502 * code is first argument,
503 * followed by actual args.
504 */
505 sa->code = *(register_t *) params;
506 params += sizeof(register_t);
507 n -= 1;
508 } else if (sa->code == SYS___syscall) {
509 /*
510 * Like syscall, but code is a quad,
511 * so as to maintain quad alignment
512 * for the rest of the args.
513 */
514 if (SV_PROC_FLAG(p, SV_ILP32)) {
515 params += sizeof(register_t);
516 sa->code = *(register_t *) params;
517 params += sizeof(register_t);
518 n -= 2;
519 } else {
520 sa->code = *(register_t *) params;
521 params += sizeof(register_t);
522 n -= 1;
523 }
524 }
525
526 if (p->p_sysent->sv_mask)
527 sa->code &= p->p_sysent->sv_mask;
528 if (sa->code >= p->p_sysent->sv_size)
529 sa->callp = &p->p_sysent->sv_table[0];
530 else
531 sa->callp = &p->p_sysent->sv_table[sa->code];
532
533 sa->narg = sa->callp->sy_narg;
534
535 if (SV_PROC_FLAG(p, SV_ILP32)) {
536 argsz = sizeof(uint32_t);
537
538 for (i = 0; i < n; i++)
539 sa->args[i] = ((u_register_t *)(params))[i] &
540 0xffffffff;
541 } else {
542 argsz = sizeof(uint64_t);
543
544 for (i = 0; i < n; i++)
545 sa->args[i] = ((u_register_t *)(params))[i];
546 }
547
548 if (sa->narg > n)
549 error = copyin(MOREARGS(frame->fixreg[1]), sa->args + n,
550 (sa->narg - n) * argsz);
551 else
552 error = 0;
553
554 #ifdef __powerpc64__
555 if (SV_PROC_FLAG(p, SV_ILP32) && sa->narg > n) {
556 /* Expand the size of arguments copied from the stack */
557
558 for (i = sa->narg; i >= n; i--)
559 sa->args[i] = ((uint32_t *)(&sa->args[n]))[i-n];
560 }
561 #endif
562
563 if (error == 0) {
564 td->td_retval[0] = 0;
565 td->td_retval[1] = frame->fixreg[FIRSTARG + 1];
566 }
567 return (error);
568 }
569
570 #include "../../kern/subr_syscall.c"
571
572 void
573 syscall(struct trapframe *frame)
574 {
575 struct thread *td;
576 struct syscall_args sa;
577 int error;
578
579 td = curthread;
580 td->td_frame = frame;
581
582 #ifdef __powerpc64__
583 /*
584 * Speculatively restore last user SLB segment, which we know is
585 * invalid already, since we are likely to do copyin()/copyout().
586 */
587 __asm __volatile ("slbmte %0, %1; isync" ::
588 "r"(td->td_pcb->pcb_cpu.aim.usr_vsid), "r"(USER_SLB_SLBE));
589 #endif
590
591 error = syscallenter(td, &sa);
592 syscallret(td, error, &sa);
593 }
594
595 #ifdef __powerpc64__
596 /* Handle kernel SLB faults -- runs in real mode, all seat belts off */
597 void
598 handle_kernel_slb_spill(int type, register_t dar, register_t srr0)
599 {
600 struct slb *slbcache;
601 uint64_t slbe, slbv;
602 uint64_t esid, addr;
603 int i;
604
605 addr = (type == EXC_ISE) ? srr0 : dar;
606 slbcache = PCPU_GET(slb);
607 esid = (uintptr_t)addr >> ADDR_SR_SHFT;
608 slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID;
609
610 /* See if the hardware flushed this somehow (can happen in LPARs) */
611 for (i = 0; i < n_slbs; i++)
612 if (slbcache[i].slbe == (slbe | (uint64_t)i))
613 return;
614
615 /* Not in the map, needs to actually be added */
616 slbv = kernel_va_to_slbv(addr);
617 if (slbcache[USER_SLB_SLOT].slbe == 0) {
618 for (i = 0; i < n_slbs; i++) {
619 if (i == USER_SLB_SLOT)
620 continue;
621 if (!(slbcache[i].slbe & SLBE_VALID))
622 goto fillkernslb;
623 }
624
625 if (i == n_slbs)
626 slbcache[USER_SLB_SLOT].slbe = 1;
627 }
628
629 /* Sacrifice a random SLB entry that is not the user entry */
630 i = mftb() % n_slbs;
631 if (i == USER_SLB_SLOT)
632 i = (i+1) % n_slbs;
633
634 fillkernslb:
635 /* Write new entry */
636 slbcache[i].slbv = slbv;
637 slbcache[i].slbe = slbe | (uint64_t)i;
638
639 /* Trap handler will restore from cache on exit */
640 }
641
642 static int
643 handle_user_slb_spill(pmap_t pm, vm_offset_t addr)
644 {
645 struct slb *user_entry;
646 uint64_t esid;
647 int i;
648
649 esid = (uintptr_t)addr >> ADDR_SR_SHFT;
650
651 PMAP_LOCK(pm);
652 user_entry = user_va_to_slb_entry(pm, addr);
653
654 if (user_entry == NULL) {
655 /* allocate_vsid auto-spills it */
656 (void)allocate_user_vsid(pm, esid, 0);
657 } else {
658 /*
659 * Check that another CPU has not already mapped this.
660 * XXX: Per-thread SLB caches would be better.
661 */
662 for (i = 0; i < pm->pm_slb_len; i++)
663 if (pm->pm_slb[i] == user_entry)
664 break;
665
666 if (i == pm->pm_slb_len)
667 slb_insert_user(pm, user_entry);
668 }
669 PMAP_UNLOCK(pm);
670
671 return (0);
672 }
673 #endif
674
675 static int
676 trap_pfault(struct trapframe *frame, int user)
677 {
678 vm_offset_t eva, va;
679 struct thread *td;
680 struct proc *p;
681 vm_map_t map;
682 vm_prot_t ftype;
683 int rv;
684 #ifdef AIM
685 register_t user_sr;
686 #endif
687
688 td = curthread;
689 p = td->td_proc;
690 if (frame->exc == EXC_ISI) {
691 eva = frame->srr0;
692 ftype = VM_PROT_EXECUTE;
693 if (frame->srr1 & SRR1_ISI_PFAULT)
694 ftype |= VM_PROT_READ;
695 } else {
696 eva = frame->dar;
697 #ifdef BOOKE
698 if (frame->cpu.booke.esr & ESR_ST)
699 #else
700 if (frame->cpu.aim.dsisr & DSISR_STORE)
701 #endif
702 ftype = VM_PROT_WRITE;
703 else
704 ftype = VM_PROT_READ;
705 }
706
707 if (user) {
708 KASSERT(p->p_vmspace != NULL, ("trap_pfault: vmspace NULL"));
709 map = &p->p_vmspace->vm_map;
710 } else {
711 #ifdef BOOKE
712 if (eva < VM_MAXUSER_ADDRESS) {
713 #else
714 if ((eva >> ADDR_SR_SHFT) == (USER_ADDR >> ADDR_SR_SHFT)) {
715 #endif
716 map = &p->p_vmspace->vm_map;
717
718 #ifdef AIM
719 user_sr = td->td_pcb->pcb_cpu.aim.usr_segm;
720 eva &= ADDR_PIDX | ADDR_POFF;
721 eva |= user_sr << ADDR_SR_SHFT;
722 #endif
723 } else {
724 map = kernel_map;
725 }
726 }
727 va = trunc_page(eva);
728
729 /* Fault in the page. */
730 rv = vm_fault(map, va, ftype, VM_FAULT_NORMAL);
731 /*
732 * XXXDTRACE: add dtrace_doubletrap_func here?
733 */
734
735 if (rv == KERN_SUCCESS)
736 return (0);
737
738 if (!user && handle_onfault(frame))
739 return (0);
740
741 return (SIGSEGV);
742 }
743
744 /*
745 * For now, this only deals with the particular unaligned access case
746 * that gcc tends to generate. Eventually it should handle all of the
747 * possibilities that can happen on a 32-bit PowerPC in big-endian mode.
748 */
749
750 static int
751 fix_unaligned(struct thread *td, struct trapframe *frame)
752 {
753 struct thread *fputhread;
754 int indicator, reg;
755 double *fpr;
756
757 indicator = EXC_ALI_OPCODE_INDICATOR(frame->cpu.aim.dsisr);
758
759 switch (indicator) {
760 case EXC_ALI_LFD:
761 case EXC_ALI_STFD:
762 reg = EXC_ALI_RST(frame->cpu.aim.dsisr);
763 fpr = &td->td_pcb->pcb_fpu.fpr[reg].fpr;
764 fputhread = PCPU_GET(fputhread);
765
766 /* Juggle the FPU to ensure that we've initialized
767 * the FPRs, and that their current state is in
768 * the PCB.
769 */
770 if (fputhread != td) {
771 if (fputhread)
772 save_fpu(fputhread);
773 enable_fpu(td);
774 }
775 save_fpu(td);
776
777 if (indicator == EXC_ALI_LFD) {
778 if (copyin((void *)frame->dar, fpr,
779 sizeof(double)) != 0)
780 return (-1);
781 enable_fpu(td);
782 } else {
783 if (copyout(fpr, (void *)frame->dar,
784 sizeof(double)) != 0)
785 return (-1);
786 }
787 return (0);
788 break;
789 }
790
791 return (-1);
792 }
793
794 #ifdef KDB
795 int db_trap_glue(struct trapframe *); /* Called from trap_subr.S */
796
797 int
798 db_trap_glue(struct trapframe *frame)
799 {
800 if (!(frame->srr1 & PSL_PR)
801 && (frame->exc == EXC_TRC || frame->exc == EXC_RUNMODETRC
802 #ifdef AIM
803 || (frame->exc == EXC_PGM
804 && (frame->srr1 & EXC_PGM_TRAP))
805 #else
806 || (frame->exc == EXC_DEBUG)
807 #endif
808 || frame->exc == EXC_BPT
809 || frame->exc == EXC_DSI)) {
810 int type = frame->exc;
811
812 /* Ignore DTrace traps. */
813 if (*(uint32_t *)frame->srr0 == EXC_DTRACE)
814 return (0);
815 #ifdef AIM
816 if (type == EXC_PGM && (frame->srr1 & EXC_PGM_TRAP)) {
817 #else
818 if (frame->cpu.booke.esr & ESR_PTR) {
819 #endif
820 type = T_BREAKPOINT;
821 }
822 return (kdb_trap(type, 0, frame));
823 }
824
825 return (0);
826 }
827 #endif
828