1 /******************************************************************************
2
3 Copyright (c) 2013-2015, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 ******************************************************************************/
33 /*$FreeBSD$*/
34
35 #include "i40e_type.h"
36 #include "i40e_adminq.h"
37 #include "i40e_prototype.h"
38 #include "i40e_virtchnl.h"
39
40
41 /**
42 * i40e_set_mac_type - Sets MAC type
43 * @hw: pointer to the HW structure
44 *
45 * This function sets the mac type of the adapter based on the
46 * vendor ID and device ID stored in the hw structure.
47 **/
i40e_set_mac_type(struct i40e_hw * hw)48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
49 {
50 enum i40e_status_code status = I40E_SUCCESS;
51
52 DEBUGFUNC("i40e_set_mac_type\n");
53
54 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
55 switch (hw->device_id) {
56 case I40E_DEV_ID_SFP_XL710:
57 case I40E_DEV_ID_QEMU:
58 case I40E_DEV_ID_KX_A:
59 case I40E_DEV_ID_KX_B:
60 case I40E_DEV_ID_KX_C:
61 case I40E_DEV_ID_QSFP_A:
62 case I40E_DEV_ID_QSFP_B:
63 case I40E_DEV_ID_QSFP_C:
64 case I40E_DEV_ID_10G_BASE_T:
65 case I40E_DEV_ID_10G_BASE_T4:
66 case I40E_DEV_ID_20G_KR2:
67 case I40E_DEV_ID_20G_KR2_A:
68 hw->mac.type = I40E_MAC_XL710;
69 break;
70 #ifdef X722_SUPPORT
71 case I40E_DEV_ID_SFP_X722:
72 case I40E_DEV_ID_1G_BASE_T_X722:
73 case I40E_DEV_ID_10G_BASE_T_X722:
74 hw->mac.type = I40E_MAC_X722;
75 break;
76 #endif
77 #ifdef X722_SUPPORT
78 case I40E_DEV_ID_X722_VF:
79 case I40E_DEV_ID_X722_VF_HV:
80 hw->mac.type = I40E_MAC_X722_VF;
81 break;
82 #endif
83 case I40E_DEV_ID_VF:
84 case I40E_DEV_ID_VF_HV:
85 hw->mac.type = I40E_MAC_VF;
86 break;
87 default:
88 hw->mac.type = I40E_MAC_GENERIC;
89 break;
90 }
91 } else {
92 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
93 }
94
95 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
96 hw->mac.type, status);
97 return status;
98 }
99
100 /**
101 * i40e_aq_str - convert AQ err code to a string
102 * @hw: pointer to the HW structure
103 * @aq_err: the AQ error code to convert
104 **/
i40e_aq_str(struct i40e_hw * hw,enum i40e_admin_queue_err aq_err)105 char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
106 {
107 switch (aq_err) {
108 case I40E_AQ_RC_OK:
109 return "OK";
110 case I40E_AQ_RC_EPERM:
111 return "I40E_AQ_RC_EPERM";
112 case I40E_AQ_RC_ENOENT:
113 return "I40E_AQ_RC_ENOENT";
114 case I40E_AQ_RC_ESRCH:
115 return "I40E_AQ_RC_ESRCH";
116 case I40E_AQ_RC_EINTR:
117 return "I40E_AQ_RC_EINTR";
118 case I40E_AQ_RC_EIO:
119 return "I40E_AQ_RC_EIO";
120 case I40E_AQ_RC_ENXIO:
121 return "I40E_AQ_RC_ENXIO";
122 case I40E_AQ_RC_E2BIG:
123 return "I40E_AQ_RC_E2BIG";
124 case I40E_AQ_RC_EAGAIN:
125 return "I40E_AQ_RC_EAGAIN";
126 case I40E_AQ_RC_ENOMEM:
127 return "I40E_AQ_RC_ENOMEM";
128 case I40E_AQ_RC_EACCES:
129 return "I40E_AQ_RC_EACCES";
130 case I40E_AQ_RC_EFAULT:
131 return "I40E_AQ_RC_EFAULT";
132 case I40E_AQ_RC_EBUSY:
133 return "I40E_AQ_RC_EBUSY";
134 case I40E_AQ_RC_EEXIST:
135 return "I40E_AQ_RC_EEXIST";
136 case I40E_AQ_RC_EINVAL:
137 return "I40E_AQ_RC_EINVAL";
138 case I40E_AQ_RC_ENOTTY:
139 return "I40E_AQ_RC_ENOTTY";
140 case I40E_AQ_RC_ENOSPC:
141 return "I40E_AQ_RC_ENOSPC";
142 case I40E_AQ_RC_ENOSYS:
143 return "I40E_AQ_RC_ENOSYS";
144 case I40E_AQ_RC_ERANGE:
145 return "I40E_AQ_RC_ERANGE";
146 case I40E_AQ_RC_EFLUSHED:
147 return "I40E_AQ_RC_EFLUSHED";
148 case I40E_AQ_RC_BAD_ADDR:
149 return "I40E_AQ_RC_BAD_ADDR";
150 case I40E_AQ_RC_EMODE:
151 return "I40E_AQ_RC_EMODE";
152 case I40E_AQ_RC_EFBIG:
153 return "I40E_AQ_RC_EFBIG";
154 }
155
156 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
157 return hw->err_str;
158 }
159
160 /**
161 * i40e_stat_str - convert status err code to a string
162 * @hw: pointer to the HW structure
163 * @stat_err: the status error code to convert
164 **/
i40e_stat_str(struct i40e_hw * hw,enum i40e_status_code stat_err)165 char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
166 {
167 switch (stat_err) {
168 case I40E_SUCCESS:
169 return "OK";
170 case I40E_ERR_NVM:
171 return "I40E_ERR_NVM";
172 case I40E_ERR_NVM_CHECKSUM:
173 return "I40E_ERR_NVM_CHECKSUM";
174 case I40E_ERR_PHY:
175 return "I40E_ERR_PHY";
176 case I40E_ERR_CONFIG:
177 return "I40E_ERR_CONFIG";
178 case I40E_ERR_PARAM:
179 return "I40E_ERR_PARAM";
180 case I40E_ERR_MAC_TYPE:
181 return "I40E_ERR_MAC_TYPE";
182 case I40E_ERR_UNKNOWN_PHY:
183 return "I40E_ERR_UNKNOWN_PHY";
184 case I40E_ERR_LINK_SETUP:
185 return "I40E_ERR_LINK_SETUP";
186 case I40E_ERR_ADAPTER_STOPPED:
187 return "I40E_ERR_ADAPTER_STOPPED";
188 case I40E_ERR_INVALID_MAC_ADDR:
189 return "I40E_ERR_INVALID_MAC_ADDR";
190 case I40E_ERR_DEVICE_NOT_SUPPORTED:
191 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
192 case I40E_ERR_MASTER_REQUESTS_PENDING:
193 return "I40E_ERR_MASTER_REQUESTS_PENDING";
194 case I40E_ERR_INVALID_LINK_SETTINGS:
195 return "I40E_ERR_INVALID_LINK_SETTINGS";
196 case I40E_ERR_AUTONEG_NOT_COMPLETE:
197 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
198 case I40E_ERR_RESET_FAILED:
199 return "I40E_ERR_RESET_FAILED";
200 case I40E_ERR_SWFW_SYNC:
201 return "I40E_ERR_SWFW_SYNC";
202 case I40E_ERR_NO_AVAILABLE_VSI:
203 return "I40E_ERR_NO_AVAILABLE_VSI";
204 case I40E_ERR_NO_MEMORY:
205 return "I40E_ERR_NO_MEMORY";
206 case I40E_ERR_BAD_PTR:
207 return "I40E_ERR_BAD_PTR";
208 case I40E_ERR_RING_FULL:
209 return "I40E_ERR_RING_FULL";
210 case I40E_ERR_INVALID_PD_ID:
211 return "I40E_ERR_INVALID_PD_ID";
212 case I40E_ERR_INVALID_QP_ID:
213 return "I40E_ERR_INVALID_QP_ID";
214 case I40E_ERR_INVALID_CQ_ID:
215 return "I40E_ERR_INVALID_CQ_ID";
216 case I40E_ERR_INVALID_CEQ_ID:
217 return "I40E_ERR_INVALID_CEQ_ID";
218 case I40E_ERR_INVALID_AEQ_ID:
219 return "I40E_ERR_INVALID_AEQ_ID";
220 case I40E_ERR_INVALID_SIZE:
221 return "I40E_ERR_INVALID_SIZE";
222 case I40E_ERR_INVALID_ARP_INDEX:
223 return "I40E_ERR_INVALID_ARP_INDEX";
224 case I40E_ERR_INVALID_FPM_FUNC_ID:
225 return "I40E_ERR_INVALID_FPM_FUNC_ID";
226 case I40E_ERR_QP_INVALID_MSG_SIZE:
227 return "I40E_ERR_QP_INVALID_MSG_SIZE";
228 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
229 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
230 case I40E_ERR_INVALID_FRAG_COUNT:
231 return "I40E_ERR_INVALID_FRAG_COUNT";
232 case I40E_ERR_QUEUE_EMPTY:
233 return "I40E_ERR_QUEUE_EMPTY";
234 case I40E_ERR_INVALID_ALIGNMENT:
235 return "I40E_ERR_INVALID_ALIGNMENT";
236 case I40E_ERR_FLUSHED_QUEUE:
237 return "I40E_ERR_FLUSHED_QUEUE";
238 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
239 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
240 case I40E_ERR_INVALID_IMM_DATA_SIZE:
241 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
242 case I40E_ERR_TIMEOUT:
243 return "I40E_ERR_TIMEOUT";
244 case I40E_ERR_OPCODE_MISMATCH:
245 return "I40E_ERR_OPCODE_MISMATCH";
246 case I40E_ERR_CQP_COMPL_ERROR:
247 return "I40E_ERR_CQP_COMPL_ERROR";
248 case I40E_ERR_INVALID_VF_ID:
249 return "I40E_ERR_INVALID_VF_ID";
250 case I40E_ERR_INVALID_HMCFN_ID:
251 return "I40E_ERR_INVALID_HMCFN_ID";
252 case I40E_ERR_BACKING_PAGE_ERROR:
253 return "I40E_ERR_BACKING_PAGE_ERROR";
254 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
255 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
256 case I40E_ERR_INVALID_PBLE_INDEX:
257 return "I40E_ERR_INVALID_PBLE_INDEX";
258 case I40E_ERR_INVALID_SD_INDEX:
259 return "I40E_ERR_INVALID_SD_INDEX";
260 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
261 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
262 case I40E_ERR_INVALID_SD_TYPE:
263 return "I40E_ERR_INVALID_SD_TYPE";
264 case I40E_ERR_MEMCPY_FAILED:
265 return "I40E_ERR_MEMCPY_FAILED";
266 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
267 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
268 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
269 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
270 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
271 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
272 case I40E_ERR_SRQ_ENABLED:
273 return "I40E_ERR_SRQ_ENABLED";
274 case I40E_ERR_ADMIN_QUEUE_ERROR:
275 return "I40E_ERR_ADMIN_QUEUE_ERROR";
276 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
277 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
278 case I40E_ERR_BUF_TOO_SHORT:
279 return "I40E_ERR_BUF_TOO_SHORT";
280 case I40E_ERR_ADMIN_QUEUE_FULL:
281 return "I40E_ERR_ADMIN_QUEUE_FULL";
282 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
283 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
284 case I40E_ERR_BAD_IWARP_CQE:
285 return "I40E_ERR_BAD_IWARP_CQE";
286 case I40E_ERR_NVM_BLANK_MODE:
287 return "I40E_ERR_NVM_BLANK_MODE";
288 case I40E_ERR_NOT_IMPLEMENTED:
289 return "I40E_ERR_NOT_IMPLEMENTED";
290 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
291 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
292 case I40E_ERR_DIAG_TEST_FAILED:
293 return "I40E_ERR_DIAG_TEST_FAILED";
294 case I40E_ERR_NOT_READY:
295 return "I40E_ERR_NOT_READY";
296 case I40E_NOT_SUPPORTED:
297 return "I40E_NOT_SUPPORTED";
298 case I40E_ERR_FIRMWARE_API_VERSION:
299 return "I40E_ERR_FIRMWARE_API_VERSION";
300 }
301
302 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
303 return hw->err_str;
304 }
305
306 /**
307 * i40e_debug_aq
308 * @hw: debug mask related to admin queue
309 * @mask: debug mask
310 * @desc: pointer to admin queue descriptor
311 * @buffer: pointer to command buffer
312 * @buf_len: max length of buffer
313 *
314 * Dumps debug log about adminq command with descriptor contents.
315 **/
i40e_debug_aq(struct i40e_hw * hw,enum i40e_debug_mask mask,void * desc,void * buffer,u16 buf_len)316 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
317 void *buffer, u16 buf_len)
318 {
319 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
320 u16 len = LE16_TO_CPU(aq_desc->datalen);
321 u8 *buf = (u8 *)buffer;
322 u16 i = 0;
323
324 if ((!(mask & hw->debug_mask)) || (desc == NULL))
325 return;
326
327 i40e_debug(hw, mask,
328 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
329 LE16_TO_CPU(aq_desc->opcode),
330 LE16_TO_CPU(aq_desc->flags),
331 LE16_TO_CPU(aq_desc->datalen),
332 LE16_TO_CPU(aq_desc->retval));
333 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
334 LE32_TO_CPU(aq_desc->cookie_high),
335 LE32_TO_CPU(aq_desc->cookie_low));
336 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
337 LE32_TO_CPU(aq_desc->params.internal.param0),
338 LE32_TO_CPU(aq_desc->params.internal.param1));
339 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
340 LE32_TO_CPU(aq_desc->params.external.addr_high),
341 LE32_TO_CPU(aq_desc->params.external.addr_low));
342
343 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
344 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
345 if (buf_len < len)
346 len = buf_len;
347 /* write the full 16-byte chunks */
348 for (i = 0; i < (len - 16); i += 16)
349 i40e_debug(hw, mask,
350 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
351 i, buf[i], buf[i+1], buf[i+2], buf[i+3],
352 buf[i+4], buf[i+5], buf[i+6], buf[i+7],
353 buf[i+8], buf[i+9], buf[i+10], buf[i+11],
354 buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
355 /* write whatever's left over without overrunning the buffer */
356 if (i < len) {
357 char d_buf[80];
358 int j = 0;
359
360 memset(d_buf, 0, sizeof(d_buf));
361 j += sprintf(d_buf, "\t0x%04X ", i);
362 while (i < len)
363 j += sprintf(&d_buf[j], " %02X", buf[i++]);
364 i40e_debug(hw, mask, "%s\n", d_buf);
365 }
366 }
367 }
368
369 /**
370 * i40e_check_asq_alive
371 * @hw: pointer to the hw struct
372 *
373 * Returns TRUE if Queue is enabled else FALSE.
374 **/
i40e_check_asq_alive(struct i40e_hw * hw)375 bool i40e_check_asq_alive(struct i40e_hw *hw)
376 {
377 if (hw->aq.asq.len)
378 if (!i40e_is_vf(hw))
379 return !!(rd32(hw, hw->aq.asq.len) &
380 I40E_PF_ATQLEN_ATQENABLE_MASK);
381 if (i40e_is_vf(hw))
382 return !!(rd32(hw, hw->aq.asq.len) &
383 I40E_VF_ATQLEN1_ATQENABLE_MASK);
384 return FALSE;
385 }
386
387 /**
388 * i40e_aq_queue_shutdown
389 * @hw: pointer to the hw struct
390 * @unloading: is the driver unloading itself
391 *
392 * Tell the Firmware that we're shutting down the AdminQ and whether
393 * or not the driver is unloading as well.
394 **/
i40e_aq_queue_shutdown(struct i40e_hw * hw,bool unloading)395 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
396 bool unloading)
397 {
398 struct i40e_aq_desc desc;
399 struct i40e_aqc_queue_shutdown *cmd =
400 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
401 enum i40e_status_code status;
402
403 i40e_fill_default_direct_cmd_desc(&desc,
404 i40e_aqc_opc_queue_shutdown);
405
406 if (unloading)
407 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
408 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
409
410 return status;
411 }
412 #ifdef X722_SUPPORT
413
414 /**
415 * i40e_aq_get_set_rss_lut
416 * @hw: pointer to the hardware structure
417 * @vsi_id: vsi fw index
418 * @pf_lut: for PF table set TRUE, for VSI table set FALSE
419 * @lut: pointer to the lut buffer provided by the caller
420 * @lut_size: size of the lut buffer
421 * @set: set TRUE to set the table, FALSE to get the table
422 *
423 * Internal function to get or set RSS look up table
424 **/
i40e_aq_get_set_rss_lut(struct i40e_hw * hw,u16 vsi_id,bool pf_lut,u8 * lut,u16 lut_size,bool set)425 static enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
426 u16 vsi_id, bool pf_lut,
427 u8 *lut, u16 lut_size,
428 bool set)
429 {
430 enum i40e_status_code status;
431 struct i40e_aq_desc desc;
432 struct i40e_aqc_get_set_rss_lut *cmd_resp =
433 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
434
435 if (set)
436 i40e_fill_default_direct_cmd_desc(&desc,
437 i40e_aqc_opc_set_rss_lut);
438 else
439 i40e_fill_default_direct_cmd_desc(&desc,
440 i40e_aqc_opc_get_rss_lut);
441
442 /* Indirect command */
443 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
444 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
445
446 cmd_resp->vsi_id =
447 CPU_TO_LE16((u16)((vsi_id <<
448 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
449 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
450 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
451
452 if (pf_lut)
453 cmd_resp->flags |= CPU_TO_LE16((u16)
454 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
455 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
456 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
457 else
458 cmd_resp->flags |= CPU_TO_LE16((u16)
459 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
460 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
461 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
462
463 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_WORD((u64)lut));
464 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)lut));
465
466 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
467
468 return status;
469 }
470
471 /**
472 * i40e_aq_get_rss_lut
473 * @hw: pointer to the hardware structure
474 * @vsi_id: vsi fw index
475 * @pf_lut: for PF table set TRUE, for VSI table set FALSE
476 * @lut: pointer to the lut buffer provided by the caller
477 * @lut_size: size of the lut buffer
478 *
479 * get the RSS lookup table, PF or VSI type
480 **/
i40e_aq_get_rss_lut(struct i40e_hw * hw,u16 vsi_id,bool pf_lut,u8 * lut,u16 lut_size)481 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
482 bool pf_lut, u8 *lut, u16 lut_size)
483 {
484 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
485 FALSE);
486 }
487
488 /**
489 * i40e_aq_set_rss_lut
490 * @hw: pointer to the hardware structure
491 * @vsi_id: vsi fw index
492 * @pf_lut: for PF table set TRUE, for VSI table set FALSE
493 * @lut: pointer to the lut buffer provided by the caller
494 * @lut_size: size of the lut buffer
495 *
496 * set the RSS lookup table, PF or VSI type
497 **/
i40e_aq_set_rss_lut(struct i40e_hw * hw,u16 vsi_id,bool pf_lut,u8 * lut,u16 lut_size)498 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
499 bool pf_lut, u8 *lut, u16 lut_size)
500 {
501 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, TRUE);
502 }
503
504 /**
505 * i40e_aq_get_set_rss_key
506 * @hw: pointer to the hw struct
507 * @vsi_id: vsi fw index
508 * @key: pointer to key info struct
509 * @set: set TRUE to set the key, FALSE to get the key
510 *
511 * get the RSS key per VSI
512 **/
i40e_aq_get_set_rss_key(struct i40e_hw * hw,u16 vsi_id,struct i40e_aqc_get_set_rss_key_data * key,bool set)513 static enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
514 u16 vsi_id,
515 struct i40e_aqc_get_set_rss_key_data *key,
516 bool set)
517 {
518 enum i40e_status_code status;
519 struct i40e_aq_desc desc;
520 struct i40e_aqc_get_set_rss_key *cmd_resp =
521 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
522 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
523
524 if (set)
525 i40e_fill_default_direct_cmd_desc(&desc,
526 i40e_aqc_opc_set_rss_key);
527 else
528 i40e_fill_default_direct_cmd_desc(&desc,
529 i40e_aqc_opc_get_rss_key);
530
531 /* Indirect command */
532 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
533 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
534
535 cmd_resp->vsi_id =
536 CPU_TO_LE16((u16)((vsi_id <<
537 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
538 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
539 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
540 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_WORD((u64)key));
541 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)key));
542
543 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
544
545 return status;
546 }
547
548 /**
549 * i40e_aq_get_rss_key
550 * @hw: pointer to the hw struct
551 * @vsi_id: vsi fw index
552 * @key: pointer to key info struct
553 *
554 **/
i40e_aq_get_rss_key(struct i40e_hw * hw,u16 vsi_id,struct i40e_aqc_get_set_rss_key_data * key)555 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
556 u16 vsi_id,
557 struct i40e_aqc_get_set_rss_key_data *key)
558 {
559 return i40e_aq_get_set_rss_key(hw, vsi_id, key, FALSE);
560 }
561
562 /**
563 * i40e_aq_set_rss_key
564 * @hw: pointer to the hw struct
565 * @vsi_id: vsi fw index
566 * @key: pointer to key info struct
567 *
568 * set the RSS key per VSI
569 **/
i40e_aq_set_rss_key(struct i40e_hw * hw,u16 vsi_id,struct i40e_aqc_get_set_rss_key_data * key)570 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
571 u16 vsi_id,
572 struct i40e_aqc_get_set_rss_key_data *key)
573 {
574 return i40e_aq_get_set_rss_key(hw, vsi_id, key, TRUE);
575 }
576 #endif /* X722_SUPPORT */
577
578 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
579 * hardware to a bit-field that can be used by SW to more easily determine the
580 * packet type.
581 *
582 * Macros are used to shorten the table lines and make this table human
583 * readable.
584 *
585 * We store the PTYPE in the top byte of the bit field - this is just so that
586 * we can check that the table doesn't have a row missing, as the index into
587 * the table should be the PTYPE.
588 *
589 * Typical work flow:
590 *
591 * IF NOT i40e_ptype_lookup[ptype].known
592 * THEN
593 * Packet is unknown
594 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
595 * Use the rest of the fields to look at the tunnels, inner protocols, etc
596 * ELSE
597 * Use the enum i40e_rx_l2_ptype to decode the packet type
598 * ENDIF
599 */
600
601 /* macro to make the table lines short */
602 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
603 { PTYPE, \
604 1, \
605 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
606 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
607 I40E_RX_PTYPE_##OUTER_FRAG, \
608 I40E_RX_PTYPE_TUNNEL_##T, \
609 I40E_RX_PTYPE_TUNNEL_END_##TE, \
610 I40E_RX_PTYPE_##TEF, \
611 I40E_RX_PTYPE_INNER_PROT_##I, \
612 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
613
614 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
615 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
616
617 /* shorter macros makes the table fit but are terse */
618 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
619 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
620 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
621
622 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
623 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
624 /* L2 Packet types */
625 I40E_PTT_UNUSED_ENTRY(0),
626 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
627 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
628 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
629 I40E_PTT_UNUSED_ENTRY(4),
630 I40E_PTT_UNUSED_ENTRY(5),
631 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
632 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
633 I40E_PTT_UNUSED_ENTRY(8),
634 I40E_PTT_UNUSED_ENTRY(9),
635 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
636 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
637 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
638 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
639 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
640 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
641 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
642 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
643 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
644 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
645 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
646 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
647
648 /* Non Tunneled IPv4 */
649 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
650 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
651 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
652 I40E_PTT_UNUSED_ENTRY(25),
653 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
654 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
655 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
656
657 /* IPv4 --> IPv4 */
658 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
659 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
660 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
661 I40E_PTT_UNUSED_ENTRY(32),
662 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
663 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
664 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
665
666 /* IPv4 --> IPv6 */
667 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
668 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
669 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
670 I40E_PTT_UNUSED_ENTRY(39),
671 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
672 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
673 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
674
675 /* IPv4 --> GRE/NAT */
676 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
677
678 /* IPv4 --> GRE/NAT --> IPv4 */
679 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
680 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
681 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
682 I40E_PTT_UNUSED_ENTRY(47),
683 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
684 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
685 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
686
687 /* IPv4 --> GRE/NAT --> IPv6 */
688 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
689 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
690 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
691 I40E_PTT_UNUSED_ENTRY(54),
692 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
693 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
694 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
695
696 /* IPv4 --> GRE/NAT --> MAC */
697 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
698
699 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
700 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
701 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
702 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
703 I40E_PTT_UNUSED_ENTRY(62),
704 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
705 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
706 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
707
708 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
709 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
710 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
711 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
712 I40E_PTT_UNUSED_ENTRY(69),
713 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
714 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
715 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
716
717 /* IPv4 --> GRE/NAT --> MAC/VLAN */
718 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
719
720 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
721 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
722 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
723 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
724 I40E_PTT_UNUSED_ENTRY(77),
725 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
726 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
727 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
728
729 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
730 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
731 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
732 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
733 I40E_PTT_UNUSED_ENTRY(84),
734 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
735 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
736 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
737
738 /* Non Tunneled IPv6 */
739 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
740 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
741 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
742 I40E_PTT_UNUSED_ENTRY(91),
743 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
744 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
745 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
746
747 /* IPv6 --> IPv4 */
748 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
749 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
750 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
751 I40E_PTT_UNUSED_ENTRY(98),
752 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
753 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
754 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
755
756 /* IPv6 --> IPv6 */
757 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
758 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
759 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
760 I40E_PTT_UNUSED_ENTRY(105),
761 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
762 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
763 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
764
765 /* IPv6 --> GRE/NAT */
766 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
767
768 /* IPv6 --> GRE/NAT -> IPv4 */
769 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
770 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
771 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
772 I40E_PTT_UNUSED_ENTRY(113),
773 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
774 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
775 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
776
777 /* IPv6 --> GRE/NAT -> IPv6 */
778 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
779 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
780 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
781 I40E_PTT_UNUSED_ENTRY(120),
782 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
783 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
784 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
785
786 /* IPv6 --> GRE/NAT -> MAC */
787 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
788
789 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
790 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
791 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
792 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
793 I40E_PTT_UNUSED_ENTRY(128),
794 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
795 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
796 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
797
798 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
799 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
800 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
801 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
802 I40E_PTT_UNUSED_ENTRY(135),
803 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
804 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
805 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
806
807 /* IPv6 --> GRE/NAT -> MAC/VLAN */
808 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
809
810 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
811 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
812 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
813 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
814 I40E_PTT_UNUSED_ENTRY(143),
815 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
816 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
817 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
818
819 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
820 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
821 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
822 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
823 I40E_PTT_UNUSED_ENTRY(150),
824 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
825 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
826 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
827
828 /* unused entries */
829 I40E_PTT_UNUSED_ENTRY(154),
830 I40E_PTT_UNUSED_ENTRY(155),
831 I40E_PTT_UNUSED_ENTRY(156),
832 I40E_PTT_UNUSED_ENTRY(157),
833 I40E_PTT_UNUSED_ENTRY(158),
834 I40E_PTT_UNUSED_ENTRY(159),
835
836 I40E_PTT_UNUSED_ENTRY(160),
837 I40E_PTT_UNUSED_ENTRY(161),
838 I40E_PTT_UNUSED_ENTRY(162),
839 I40E_PTT_UNUSED_ENTRY(163),
840 I40E_PTT_UNUSED_ENTRY(164),
841 I40E_PTT_UNUSED_ENTRY(165),
842 I40E_PTT_UNUSED_ENTRY(166),
843 I40E_PTT_UNUSED_ENTRY(167),
844 I40E_PTT_UNUSED_ENTRY(168),
845 I40E_PTT_UNUSED_ENTRY(169),
846
847 I40E_PTT_UNUSED_ENTRY(170),
848 I40E_PTT_UNUSED_ENTRY(171),
849 I40E_PTT_UNUSED_ENTRY(172),
850 I40E_PTT_UNUSED_ENTRY(173),
851 I40E_PTT_UNUSED_ENTRY(174),
852 I40E_PTT_UNUSED_ENTRY(175),
853 I40E_PTT_UNUSED_ENTRY(176),
854 I40E_PTT_UNUSED_ENTRY(177),
855 I40E_PTT_UNUSED_ENTRY(178),
856 I40E_PTT_UNUSED_ENTRY(179),
857
858 I40E_PTT_UNUSED_ENTRY(180),
859 I40E_PTT_UNUSED_ENTRY(181),
860 I40E_PTT_UNUSED_ENTRY(182),
861 I40E_PTT_UNUSED_ENTRY(183),
862 I40E_PTT_UNUSED_ENTRY(184),
863 I40E_PTT_UNUSED_ENTRY(185),
864 I40E_PTT_UNUSED_ENTRY(186),
865 I40E_PTT_UNUSED_ENTRY(187),
866 I40E_PTT_UNUSED_ENTRY(188),
867 I40E_PTT_UNUSED_ENTRY(189),
868
869 I40E_PTT_UNUSED_ENTRY(190),
870 I40E_PTT_UNUSED_ENTRY(191),
871 I40E_PTT_UNUSED_ENTRY(192),
872 I40E_PTT_UNUSED_ENTRY(193),
873 I40E_PTT_UNUSED_ENTRY(194),
874 I40E_PTT_UNUSED_ENTRY(195),
875 I40E_PTT_UNUSED_ENTRY(196),
876 I40E_PTT_UNUSED_ENTRY(197),
877 I40E_PTT_UNUSED_ENTRY(198),
878 I40E_PTT_UNUSED_ENTRY(199),
879
880 I40E_PTT_UNUSED_ENTRY(200),
881 I40E_PTT_UNUSED_ENTRY(201),
882 I40E_PTT_UNUSED_ENTRY(202),
883 I40E_PTT_UNUSED_ENTRY(203),
884 I40E_PTT_UNUSED_ENTRY(204),
885 I40E_PTT_UNUSED_ENTRY(205),
886 I40E_PTT_UNUSED_ENTRY(206),
887 I40E_PTT_UNUSED_ENTRY(207),
888 I40E_PTT_UNUSED_ENTRY(208),
889 I40E_PTT_UNUSED_ENTRY(209),
890
891 I40E_PTT_UNUSED_ENTRY(210),
892 I40E_PTT_UNUSED_ENTRY(211),
893 I40E_PTT_UNUSED_ENTRY(212),
894 I40E_PTT_UNUSED_ENTRY(213),
895 I40E_PTT_UNUSED_ENTRY(214),
896 I40E_PTT_UNUSED_ENTRY(215),
897 I40E_PTT_UNUSED_ENTRY(216),
898 I40E_PTT_UNUSED_ENTRY(217),
899 I40E_PTT_UNUSED_ENTRY(218),
900 I40E_PTT_UNUSED_ENTRY(219),
901
902 I40E_PTT_UNUSED_ENTRY(220),
903 I40E_PTT_UNUSED_ENTRY(221),
904 I40E_PTT_UNUSED_ENTRY(222),
905 I40E_PTT_UNUSED_ENTRY(223),
906 I40E_PTT_UNUSED_ENTRY(224),
907 I40E_PTT_UNUSED_ENTRY(225),
908 I40E_PTT_UNUSED_ENTRY(226),
909 I40E_PTT_UNUSED_ENTRY(227),
910 I40E_PTT_UNUSED_ENTRY(228),
911 I40E_PTT_UNUSED_ENTRY(229),
912
913 I40E_PTT_UNUSED_ENTRY(230),
914 I40E_PTT_UNUSED_ENTRY(231),
915 I40E_PTT_UNUSED_ENTRY(232),
916 I40E_PTT_UNUSED_ENTRY(233),
917 I40E_PTT_UNUSED_ENTRY(234),
918 I40E_PTT_UNUSED_ENTRY(235),
919 I40E_PTT_UNUSED_ENTRY(236),
920 I40E_PTT_UNUSED_ENTRY(237),
921 I40E_PTT_UNUSED_ENTRY(238),
922 I40E_PTT_UNUSED_ENTRY(239),
923
924 I40E_PTT_UNUSED_ENTRY(240),
925 I40E_PTT_UNUSED_ENTRY(241),
926 I40E_PTT_UNUSED_ENTRY(242),
927 I40E_PTT_UNUSED_ENTRY(243),
928 I40E_PTT_UNUSED_ENTRY(244),
929 I40E_PTT_UNUSED_ENTRY(245),
930 I40E_PTT_UNUSED_ENTRY(246),
931 I40E_PTT_UNUSED_ENTRY(247),
932 I40E_PTT_UNUSED_ENTRY(248),
933 I40E_PTT_UNUSED_ENTRY(249),
934
935 I40E_PTT_UNUSED_ENTRY(250),
936 I40E_PTT_UNUSED_ENTRY(251),
937 I40E_PTT_UNUSED_ENTRY(252),
938 I40E_PTT_UNUSED_ENTRY(253),
939 I40E_PTT_UNUSED_ENTRY(254),
940 I40E_PTT_UNUSED_ENTRY(255)
941 };
942
943
944 /**
945 * i40e_validate_mac_addr - Validate unicast MAC address
946 * @mac_addr: pointer to MAC address
947 *
948 * Tests a MAC address to ensure it is a valid Individual Address
949 **/
i40e_validate_mac_addr(u8 * mac_addr)950 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
951 {
952 enum i40e_status_code status = I40E_SUCCESS;
953
954 DEBUGFUNC("i40e_validate_mac_addr");
955
956 /* Broadcast addresses ARE multicast addresses
957 * Make sure it is not a multicast address
958 * Reject the zero address
959 */
960 if (I40E_IS_MULTICAST(mac_addr) ||
961 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
962 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
963 status = I40E_ERR_INVALID_MAC_ADDR;
964
965 return status;
966 }
967
968 /**
969 * i40e_init_shared_code - Initialize the shared code
970 * @hw: pointer to hardware structure
971 *
972 * This assigns the MAC type and PHY code and inits the NVM.
973 * Does not touch the hardware. This function must be called prior to any
974 * other function in the shared code. The i40e_hw structure should be
975 * memset to 0 prior to calling this function. The following fields in
976 * hw structure should be filled in prior to calling this function:
977 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
978 * subsystem_vendor_id, and revision_id
979 **/
i40e_init_shared_code(struct i40e_hw * hw)980 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
981 {
982 enum i40e_status_code status = I40E_SUCCESS;
983 u32 port, ari, func_rid;
984
985 DEBUGFUNC("i40e_init_shared_code");
986
987 i40e_set_mac_type(hw);
988
989 switch (hw->mac.type) {
990 case I40E_MAC_XL710:
991 #ifdef X722_SUPPORT
992 case I40E_MAC_X722:
993 #endif
994 break;
995 default:
996 return I40E_ERR_DEVICE_NOT_SUPPORTED;
997 }
998
999 hw->phy.get_link_info = TRUE;
1000
1001 /* Determine port number and PF number*/
1002 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1003 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1004 hw->port = (u8)port;
1005 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1006 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1007 func_rid = rd32(hw, I40E_PF_FUNC_RID);
1008 if (ari)
1009 hw->pf_id = (u8)(func_rid & 0xff);
1010 else
1011 hw->pf_id = (u8)(func_rid & 0x7);
1012
1013 status = i40e_init_nvm(hw);
1014 return status;
1015 }
1016
1017 /**
1018 * i40e_aq_mac_address_read - Retrieve the MAC addresses
1019 * @hw: pointer to the hw struct
1020 * @flags: a return indicator of what addresses were added to the addr store
1021 * @addrs: the requestor's mac addr store
1022 * @cmd_details: pointer to command details structure or NULL
1023 **/
i40e_aq_mac_address_read(struct i40e_hw * hw,u16 * flags,struct i40e_aqc_mac_address_read_data * addrs,struct i40e_asq_cmd_details * cmd_details)1024 static enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1025 u16 *flags,
1026 struct i40e_aqc_mac_address_read_data *addrs,
1027 struct i40e_asq_cmd_details *cmd_details)
1028 {
1029 struct i40e_aq_desc desc;
1030 struct i40e_aqc_mac_address_read *cmd_data =
1031 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1032 enum i40e_status_code status;
1033
1034 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1035 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1036
1037 status = i40e_asq_send_command(hw, &desc, addrs,
1038 sizeof(*addrs), cmd_details);
1039 *flags = LE16_TO_CPU(cmd_data->command_flags);
1040
1041 return status;
1042 }
1043
1044 /**
1045 * i40e_aq_mac_address_write - Change the MAC addresses
1046 * @hw: pointer to the hw struct
1047 * @flags: indicates which MAC to be written
1048 * @mac_addr: address to write
1049 * @cmd_details: pointer to command details structure or NULL
1050 **/
i40e_aq_mac_address_write(struct i40e_hw * hw,u16 flags,u8 * mac_addr,struct i40e_asq_cmd_details * cmd_details)1051 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1052 u16 flags, u8 *mac_addr,
1053 struct i40e_asq_cmd_details *cmd_details)
1054 {
1055 struct i40e_aq_desc desc;
1056 struct i40e_aqc_mac_address_write *cmd_data =
1057 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1058 enum i40e_status_code status;
1059
1060 i40e_fill_default_direct_cmd_desc(&desc,
1061 i40e_aqc_opc_mac_address_write);
1062 cmd_data->command_flags = CPU_TO_LE16(flags);
1063 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1064 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1065 ((u32)mac_addr[3] << 16) |
1066 ((u32)mac_addr[4] << 8) |
1067 mac_addr[5]);
1068
1069 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1070
1071 return status;
1072 }
1073
1074 /**
1075 * i40e_get_mac_addr - get MAC address
1076 * @hw: pointer to the HW structure
1077 * @mac_addr: pointer to MAC address
1078 *
1079 * Reads the adapter's MAC address from register
1080 **/
i40e_get_mac_addr(struct i40e_hw * hw,u8 * mac_addr)1081 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1082 {
1083 struct i40e_aqc_mac_address_read_data addrs;
1084 enum i40e_status_code status;
1085 u16 flags = 0;
1086
1087 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1088
1089 if (flags & I40E_AQC_LAN_ADDR_VALID)
1090 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
1091
1092 return status;
1093 }
1094
1095 /**
1096 * i40e_get_port_mac_addr - get Port MAC address
1097 * @hw: pointer to the HW structure
1098 * @mac_addr: pointer to Port MAC address
1099 *
1100 * Reads the adapter's Port MAC address
1101 **/
i40e_get_port_mac_addr(struct i40e_hw * hw,u8 * mac_addr)1102 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1103 {
1104 struct i40e_aqc_mac_address_read_data addrs;
1105 enum i40e_status_code status;
1106 u16 flags = 0;
1107
1108 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1109 if (status)
1110 return status;
1111
1112 if (flags & I40E_AQC_PORT_ADDR_VALID)
1113 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
1114 else
1115 status = I40E_ERR_INVALID_MAC_ADDR;
1116
1117 return status;
1118 }
1119
1120 /**
1121 * i40e_pre_tx_queue_cfg - pre tx queue configure
1122 * @hw: pointer to the HW structure
1123 * @queue: target pf queue index
1124 * @enable: state change request
1125 *
1126 * Handles hw requirement to indicate intention to enable
1127 * or disable target queue.
1128 **/
i40e_pre_tx_queue_cfg(struct i40e_hw * hw,u32 queue,bool enable)1129 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1130 {
1131 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1132 u32 reg_block = 0;
1133 u32 reg_val;
1134
1135 if (abs_queue_idx >= 128) {
1136 reg_block = abs_queue_idx / 128;
1137 abs_queue_idx %= 128;
1138 }
1139
1140 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1141 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1142 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1143
1144 if (enable)
1145 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1146 else
1147 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1148
1149 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1150 }
1151
1152 /**
1153 * i40e_read_pba_string - Reads part number string from EEPROM
1154 * @hw: pointer to hardware structure
1155 * @pba_num: stores the part number string from the EEPROM
1156 * @pba_num_size: part number string buffer length
1157 *
1158 * Reads the part number string from the EEPROM.
1159 **/
i40e_read_pba_string(struct i40e_hw * hw,u8 * pba_num,u32 pba_num_size)1160 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1161 u32 pba_num_size)
1162 {
1163 enum i40e_status_code status = I40E_SUCCESS;
1164 u16 pba_word = 0;
1165 u16 pba_size = 0;
1166 u16 pba_ptr = 0;
1167 u16 i = 0;
1168
1169 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1170 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1171 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1172 return status;
1173 }
1174
1175 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1176 if (status != I40E_SUCCESS) {
1177 DEBUGOUT("Failed to read PBA Block pointer.\n");
1178 return status;
1179 }
1180
1181 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1182 if (status != I40E_SUCCESS) {
1183 DEBUGOUT("Failed to read PBA Block size.\n");
1184 return status;
1185 }
1186
1187 /* Subtract one to get PBA word count (PBA Size word is included in
1188 * total size)
1189 */
1190 pba_size--;
1191 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1192 DEBUGOUT("Buffer to small for PBA data.\n");
1193 return I40E_ERR_PARAM;
1194 }
1195
1196 for (i = 0; i < pba_size; i++) {
1197 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1198 if (status != I40E_SUCCESS) {
1199 DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1200 return status;
1201 }
1202
1203 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1204 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1205 }
1206 pba_num[(pba_size * 2)] = '\0';
1207
1208 return status;
1209 }
1210
1211 /**
1212 * i40e_get_media_type - Gets media type
1213 * @hw: pointer to the hardware structure
1214 **/
i40e_get_media_type(struct i40e_hw * hw)1215 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1216 {
1217 enum i40e_media_type media;
1218
1219 switch (hw->phy.link_info.phy_type) {
1220 case I40E_PHY_TYPE_10GBASE_SR:
1221 case I40E_PHY_TYPE_10GBASE_LR:
1222 case I40E_PHY_TYPE_1000BASE_SX:
1223 case I40E_PHY_TYPE_1000BASE_LX:
1224 case I40E_PHY_TYPE_40GBASE_SR4:
1225 case I40E_PHY_TYPE_40GBASE_LR4:
1226 media = I40E_MEDIA_TYPE_FIBER;
1227 break;
1228 case I40E_PHY_TYPE_100BASE_TX:
1229 case I40E_PHY_TYPE_1000BASE_T:
1230 case I40E_PHY_TYPE_10GBASE_T:
1231 media = I40E_MEDIA_TYPE_BASET;
1232 break;
1233 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1234 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1235 case I40E_PHY_TYPE_10GBASE_CR1:
1236 case I40E_PHY_TYPE_40GBASE_CR4:
1237 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1238 case I40E_PHY_TYPE_40GBASE_AOC:
1239 case I40E_PHY_TYPE_10GBASE_AOC:
1240 media = I40E_MEDIA_TYPE_DA;
1241 break;
1242 case I40E_PHY_TYPE_1000BASE_KX:
1243 case I40E_PHY_TYPE_10GBASE_KX4:
1244 case I40E_PHY_TYPE_10GBASE_KR:
1245 case I40E_PHY_TYPE_40GBASE_KR4:
1246 case I40E_PHY_TYPE_20GBASE_KR2:
1247 media = I40E_MEDIA_TYPE_BACKPLANE;
1248 break;
1249 case I40E_PHY_TYPE_SGMII:
1250 case I40E_PHY_TYPE_XAUI:
1251 case I40E_PHY_TYPE_XFI:
1252 case I40E_PHY_TYPE_XLAUI:
1253 case I40E_PHY_TYPE_XLPPI:
1254 default:
1255 media = I40E_MEDIA_TYPE_UNKNOWN;
1256 break;
1257 }
1258
1259 return media;
1260 }
1261
1262 #define I40E_PF_RESET_WAIT_COUNT 200
1263 /**
1264 * i40e_pf_reset - Reset the PF
1265 * @hw: pointer to the hardware structure
1266 *
1267 * Assuming someone else has triggered a global reset,
1268 * assure the global reset is complete and then reset the PF
1269 **/
i40e_pf_reset(struct i40e_hw * hw)1270 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1271 {
1272 u32 cnt = 0;
1273 u32 cnt1 = 0;
1274 u32 reg = 0;
1275 u32 grst_del;
1276
1277 /* Poll for Global Reset steady state in case of recent GRST.
1278 * The grst delay value is in 100ms units, and we'll wait a
1279 * couple counts longer to be sure we don't just miss the end.
1280 */
1281 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1282 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1283 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1284 for (cnt = 0; cnt < grst_del + 10; cnt++) {
1285 reg = rd32(hw, I40E_GLGEN_RSTAT);
1286 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1287 break;
1288 i40e_msec_delay(100);
1289 }
1290 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1291 DEBUGOUT("Global reset polling failed to complete.\n");
1292 return I40E_ERR_RESET_FAILED;
1293 }
1294
1295 /* Now Wait for the FW to be ready */
1296 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1297 reg = rd32(hw, I40E_GLNVM_ULD);
1298 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1299 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1300 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1301 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1302 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1303 break;
1304 }
1305 i40e_msec_delay(10);
1306 }
1307 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1308 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1309 DEBUGOUT("wait for FW Reset complete timedout\n");
1310 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1311 return I40E_ERR_RESET_FAILED;
1312 }
1313
1314 /* If there was a Global Reset in progress when we got here,
1315 * we don't need to do the PF Reset
1316 */
1317 if (!cnt) {
1318 reg = rd32(hw, I40E_PFGEN_CTRL);
1319 wr32(hw, I40E_PFGEN_CTRL,
1320 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1321 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1322 reg = rd32(hw, I40E_PFGEN_CTRL);
1323 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1324 break;
1325 i40e_msec_delay(1);
1326 }
1327 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1328 DEBUGOUT("PF reset polling failed to complete.\n");
1329 return I40E_ERR_RESET_FAILED;
1330 }
1331 }
1332
1333 i40e_clear_pxe_mode(hw);
1334
1335
1336 return I40E_SUCCESS;
1337 }
1338
1339 /**
1340 * i40e_clear_hw - clear out any left over hw state
1341 * @hw: pointer to the hw struct
1342 *
1343 * Clear queues and interrupts, typically called at init time,
1344 * but after the capabilities have been found so we know how many
1345 * queues and msix vectors have been allocated.
1346 **/
i40e_clear_hw(struct i40e_hw * hw)1347 void i40e_clear_hw(struct i40e_hw *hw)
1348 {
1349 u32 num_queues, base_queue;
1350 u32 num_pf_int;
1351 u32 num_vf_int;
1352 u32 num_vfs;
1353 u32 i, j;
1354 u32 val;
1355 u32 eol = 0x7ff;
1356
1357 /* get number of interrupts, queues, and vfs */
1358 val = rd32(hw, I40E_GLPCI_CNF2);
1359 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1360 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1361 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1362 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1363
1364 val = rd32(hw, I40E_PFLAN_QALLOC);
1365 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1366 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1367 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1368 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1369 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1370 num_queues = (j - base_queue) + 1;
1371 else
1372 num_queues = 0;
1373
1374 val = rd32(hw, I40E_PF_VT_PFALLOC);
1375 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1376 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1377 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1378 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1379 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1380 num_vfs = (j - i) + 1;
1381 else
1382 num_vfs = 0;
1383
1384 /* stop all the interrupts */
1385 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1386 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1387 for (i = 0; i < num_pf_int - 2; i++)
1388 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1389
1390 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1391 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1392 wr32(hw, I40E_PFINT_LNKLST0, val);
1393 for (i = 0; i < num_pf_int - 2; i++)
1394 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1395 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1396 for (i = 0; i < num_vfs; i++)
1397 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1398 for (i = 0; i < num_vf_int - 2; i++)
1399 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1400
1401 /* warn the HW of the coming Tx disables */
1402 for (i = 0; i < num_queues; i++) {
1403 u32 abs_queue_idx = base_queue + i;
1404 u32 reg_block = 0;
1405
1406 if (abs_queue_idx >= 128) {
1407 reg_block = abs_queue_idx / 128;
1408 abs_queue_idx %= 128;
1409 }
1410
1411 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1412 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1413 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1414 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1415
1416 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1417 }
1418 i40e_usec_delay(400);
1419
1420 /* stop all the queues */
1421 for (i = 0; i < num_queues; i++) {
1422 wr32(hw, I40E_QINT_TQCTL(i), 0);
1423 wr32(hw, I40E_QTX_ENA(i), 0);
1424 wr32(hw, I40E_QINT_RQCTL(i), 0);
1425 wr32(hw, I40E_QRX_ENA(i), 0);
1426 }
1427
1428 /* short wait for all queue disables to settle */
1429 i40e_usec_delay(50);
1430 }
1431
1432 /**
1433 * i40e_clear_pxe_mode - clear pxe operations mode
1434 * @hw: pointer to the hw struct
1435 *
1436 * Make sure all PXE mode settings are cleared, including things
1437 * like descriptor fetch/write-back mode.
1438 **/
i40e_clear_pxe_mode(struct i40e_hw * hw)1439 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1440 {
1441 if (i40e_check_asq_alive(hw))
1442 i40e_aq_clear_pxe_mode(hw, NULL);
1443 }
1444
1445 /**
1446 * i40e_led_is_mine - helper to find matching led
1447 * @hw: pointer to the hw struct
1448 * @idx: index into GPIO registers
1449 *
1450 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1451 */
i40e_led_is_mine(struct i40e_hw * hw,int idx)1452 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1453 {
1454 u32 gpio_val = 0;
1455 u32 port;
1456
1457 if (!hw->func_caps.led[idx])
1458 return 0;
1459
1460 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1461 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1462 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1463
1464 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1465 * if it is not our port then ignore
1466 */
1467 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1468 (port != hw->port))
1469 return 0;
1470
1471 return gpio_val;
1472 }
1473
1474 #define I40E_COMBINED_ACTIVITY 0xA
1475 #define I40E_FILTER_ACTIVITY 0xE
1476 #define I40E_LINK_ACTIVITY 0xC
1477 #define I40E_MAC_ACTIVITY 0xD
1478 #define I40E_LED0 22
1479
1480 /**
1481 * i40e_led_get - return current on/off mode
1482 * @hw: pointer to the hw struct
1483 *
1484 * The value returned is the 'mode' field as defined in the
1485 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1486 * values are variations of possible behaviors relating to
1487 * blink, link, and wire.
1488 **/
i40e_led_get(struct i40e_hw * hw)1489 u32 i40e_led_get(struct i40e_hw *hw)
1490 {
1491 u32 current_mode = 0;
1492 u32 mode = 0;
1493 int i;
1494
1495 /* as per the documentation GPIO 22-29 are the LED
1496 * GPIO pins named LED0..LED7
1497 */
1498 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1499 u32 gpio_val = i40e_led_is_mine(hw, i);
1500
1501 if (!gpio_val)
1502 continue;
1503
1504 /* ignore gpio LED src mode entries related to the activity
1505 * LEDs
1506 */
1507 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1508 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1509 switch (current_mode) {
1510 case I40E_COMBINED_ACTIVITY:
1511 case I40E_FILTER_ACTIVITY:
1512 case I40E_MAC_ACTIVITY:
1513 continue;
1514 default:
1515 break;
1516 }
1517
1518 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1519 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1520 break;
1521 }
1522
1523 return mode;
1524 }
1525
1526 /**
1527 * i40e_led_set - set new on/off mode
1528 * @hw: pointer to the hw struct
1529 * @mode: 0=off, 0xf=on (else see manual for mode details)
1530 * @blink: TRUE if the LED should blink when on, FALSE if steady
1531 *
1532 * if this function is used to turn on the blink it should
1533 * be used to disable the blink when restoring the original state.
1534 **/
i40e_led_set(struct i40e_hw * hw,u32 mode,bool blink)1535 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1536 {
1537 u32 current_mode = 0;
1538 int i;
1539
1540 if (mode & 0xfffffff0)
1541 DEBUGOUT1("invalid mode passed in %X\n", mode);
1542
1543 /* as per the documentation GPIO 22-29 are the LED
1544 * GPIO pins named LED0..LED7
1545 */
1546 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1547 u32 gpio_val = i40e_led_is_mine(hw, i);
1548
1549 if (!gpio_val)
1550 continue;
1551
1552 /* ignore gpio LED src mode entries related to the activity
1553 * LEDs
1554 */
1555 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1556 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1557 switch (current_mode) {
1558 case I40E_COMBINED_ACTIVITY:
1559 case I40E_FILTER_ACTIVITY:
1560 case I40E_MAC_ACTIVITY:
1561 continue;
1562 default:
1563 break;
1564 }
1565
1566 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1567 /* this & is a bit of paranoia, but serves as a range check */
1568 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1569 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1570
1571 if (mode == I40E_LINK_ACTIVITY)
1572 blink = FALSE;
1573
1574 if (blink)
1575 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1576 else
1577 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1578
1579 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1580 break;
1581 }
1582 }
1583
1584 /* Admin command wrappers */
1585
1586 /**
1587 * i40e_aq_get_phy_capabilities
1588 * @hw: pointer to the hw struct
1589 * @abilities: structure for PHY capabilities to be filled
1590 * @qualified_modules: report Qualified Modules
1591 * @report_init: report init capabilities (active are default)
1592 * @cmd_details: pointer to command details structure or NULL
1593 *
1594 * Returns the various PHY abilities supported on the Port.
1595 **/
i40e_aq_get_phy_capabilities(struct i40e_hw * hw,bool qualified_modules,bool report_init,struct i40e_aq_get_phy_abilities_resp * abilities,struct i40e_asq_cmd_details * cmd_details)1596 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1597 bool qualified_modules, bool report_init,
1598 struct i40e_aq_get_phy_abilities_resp *abilities,
1599 struct i40e_asq_cmd_details *cmd_details)
1600 {
1601 struct i40e_aq_desc desc;
1602 enum i40e_status_code status;
1603 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1604
1605 if (!abilities)
1606 return I40E_ERR_PARAM;
1607
1608 i40e_fill_default_direct_cmd_desc(&desc,
1609 i40e_aqc_opc_get_phy_abilities);
1610
1611 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1612 if (abilities_size > I40E_AQ_LARGE_BUF)
1613 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1614
1615 if (qualified_modules)
1616 desc.params.external.param0 |=
1617 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1618
1619 if (report_init)
1620 desc.params.external.param0 |=
1621 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1622
1623 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1624 cmd_details);
1625
1626 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1627 status = I40E_ERR_UNKNOWN_PHY;
1628
1629 return status;
1630 }
1631
1632 /**
1633 * i40e_aq_set_phy_config
1634 * @hw: pointer to the hw struct
1635 * @config: structure with PHY configuration to be set
1636 * @cmd_details: pointer to command details structure or NULL
1637 *
1638 * Set the various PHY configuration parameters
1639 * supported on the Port.One or more of the Set PHY config parameters may be
1640 * ignored in an MFP mode as the PF may not have the privilege to set some
1641 * of the PHY Config parameters. This status will be indicated by the
1642 * command response.
1643 **/
i40e_aq_set_phy_config(struct i40e_hw * hw,struct i40e_aq_set_phy_config * config,struct i40e_asq_cmd_details * cmd_details)1644 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1645 struct i40e_aq_set_phy_config *config,
1646 struct i40e_asq_cmd_details *cmd_details)
1647 {
1648 struct i40e_aq_desc desc;
1649 struct i40e_aq_set_phy_config *cmd =
1650 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1651 enum i40e_status_code status;
1652
1653 if (!config)
1654 return I40E_ERR_PARAM;
1655
1656 i40e_fill_default_direct_cmd_desc(&desc,
1657 i40e_aqc_opc_set_phy_config);
1658
1659 *cmd = *config;
1660
1661 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1662
1663 return status;
1664 }
1665
1666 /**
1667 * i40e_set_fc
1668 * @hw: pointer to the hw struct
1669 *
1670 * Set the requested flow control mode using set_phy_config.
1671 **/
i40e_set_fc(struct i40e_hw * hw,u8 * aq_failures,bool atomic_restart)1672 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1673 bool atomic_restart)
1674 {
1675 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1676 struct i40e_aq_get_phy_abilities_resp abilities;
1677 struct i40e_aq_set_phy_config config;
1678 enum i40e_status_code status;
1679 u8 pause_mask = 0x0;
1680
1681 *aq_failures = 0x0;
1682
1683 switch (fc_mode) {
1684 case I40E_FC_FULL:
1685 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1686 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1687 break;
1688 case I40E_FC_RX_PAUSE:
1689 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1690 break;
1691 case I40E_FC_TX_PAUSE:
1692 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1693 break;
1694 default:
1695 break;
1696 }
1697
1698 /* Get the current phy config */
1699 status = i40e_aq_get_phy_capabilities(hw, FALSE, false, &abilities,
1700 NULL);
1701 if (status) {
1702 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1703 return status;
1704 }
1705
1706 memset(&config, 0, sizeof(config));
1707 /* clear the old pause settings */
1708 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1709 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1710 /* set the new abilities */
1711 config.abilities |= pause_mask;
1712 /* If the abilities have changed, then set the new config */
1713 if (config.abilities != abilities.abilities) {
1714 /* Auto restart link so settings take effect */
1715 if (atomic_restart)
1716 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1717 /* Copy over all the old settings */
1718 config.phy_type = abilities.phy_type;
1719 config.link_speed = abilities.link_speed;
1720 config.eee_capability = abilities.eee_capability;
1721 config.eeer = abilities.eeer_val;
1722 config.low_power_ctrl = abilities.d3_lpan;
1723 status = i40e_aq_set_phy_config(hw, &config, NULL);
1724
1725 if (status)
1726 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1727 }
1728 /* Update the link info */
1729 status = i40e_update_link_info(hw);
1730 if (status) {
1731 /* Wait a little bit (on 40G cards it sometimes takes a really
1732 * long time for link to come back from the atomic reset)
1733 * and try once more
1734 */
1735 i40e_msec_delay(1000);
1736 status = i40e_update_link_info(hw);
1737 }
1738 if (status)
1739 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1740
1741 return status;
1742 }
1743
1744 /**
1745 * i40e_aq_set_mac_config
1746 * @hw: pointer to the hw struct
1747 * @max_frame_size: Maximum Frame Size to be supported by the port
1748 * @crc_en: Tell HW to append a CRC to outgoing frames
1749 * @pacing: Pacing configurations
1750 * @cmd_details: pointer to command details structure or NULL
1751 *
1752 * Configure MAC settings for frame size, jumbo frame support and the
1753 * addition of a CRC by the hardware.
1754 **/
i40e_aq_set_mac_config(struct i40e_hw * hw,u16 max_frame_size,bool crc_en,u16 pacing,struct i40e_asq_cmd_details * cmd_details)1755 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1756 u16 max_frame_size,
1757 bool crc_en, u16 pacing,
1758 struct i40e_asq_cmd_details *cmd_details)
1759 {
1760 struct i40e_aq_desc desc;
1761 struct i40e_aq_set_mac_config *cmd =
1762 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1763 enum i40e_status_code status;
1764
1765 if (max_frame_size == 0)
1766 return I40E_ERR_PARAM;
1767
1768 i40e_fill_default_direct_cmd_desc(&desc,
1769 i40e_aqc_opc_set_mac_config);
1770
1771 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1772 cmd->params = ((u8)pacing & 0x0F) << 3;
1773 if (crc_en)
1774 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1775
1776 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1777
1778 return status;
1779 }
1780
1781 /**
1782 * i40e_aq_clear_pxe_mode
1783 * @hw: pointer to the hw struct
1784 * @cmd_details: pointer to command details structure or NULL
1785 *
1786 * Tell the firmware that the driver is taking over from PXE
1787 **/
i40e_aq_clear_pxe_mode(struct i40e_hw * hw,struct i40e_asq_cmd_details * cmd_details)1788 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1789 struct i40e_asq_cmd_details *cmd_details)
1790 {
1791 enum i40e_status_code status;
1792 struct i40e_aq_desc desc;
1793 struct i40e_aqc_clear_pxe *cmd =
1794 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1795
1796 i40e_fill_default_direct_cmd_desc(&desc,
1797 i40e_aqc_opc_clear_pxe_mode);
1798
1799 cmd->rx_cnt = 0x2;
1800
1801 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1802
1803 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1804
1805 return status;
1806 }
1807
1808 /**
1809 * i40e_aq_set_link_restart_an
1810 * @hw: pointer to the hw struct
1811 * @enable_link: if TRUE: enable link, if FALSE: disable link
1812 * @cmd_details: pointer to command details structure or NULL
1813 *
1814 * Sets up the link and restarts the Auto-Negotiation over the link.
1815 **/
i40e_aq_set_link_restart_an(struct i40e_hw * hw,bool enable_link,struct i40e_asq_cmd_details * cmd_details)1816 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1817 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1818 {
1819 struct i40e_aq_desc desc;
1820 struct i40e_aqc_set_link_restart_an *cmd =
1821 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1822 enum i40e_status_code status;
1823
1824 i40e_fill_default_direct_cmd_desc(&desc,
1825 i40e_aqc_opc_set_link_restart_an);
1826
1827 cmd->command = I40E_AQ_PHY_RESTART_AN;
1828 if (enable_link)
1829 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1830 else
1831 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1832
1833 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1834
1835 return status;
1836 }
1837
1838 /**
1839 * i40e_aq_get_link_info
1840 * @hw: pointer to the hw struct
1841 * @enable_lse: enable/disable LinkStatusEvent reporting
1842 * @link: pointer to link status structure - optional
1843 * @cmd_details: pointer to command details structure or NULL
1844 *
1845 * Returns the link status of the adapter.
1846 **/
i40e_aq_get_link_info(struct i40e_hw * hw,bool enable_lse,struct i40e_link_status * link,struct i40e_asq_cmd_details * cmd_details)1847 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1848 bool enable_lse, struct i40e_link_status *link,
1849 struct i40e_asq_cmd_details *cmd_details)
1850 {
1851 struct i40e_aq_desc desc;
1852 struct i40e_aqc_get_link_status *resp =
1853 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1854 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1855 enum i40e_status_code status;
1856 bool tx_pause, rx_pause;
1857 u16 command_flags;
1858
1859 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1860
1861 if (enable_lse)
1862 command_flags = I40E_AQ_LSE_ENABLE;
1863 else
1864 command_flags = I40E_AQ_LSE_DISABLE;
1865 resp->command_flags = CPU_TO_LE16(command_flags);
1866
1867 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1868
1869 if (status != I40E_SUCCESS)
1870 goto aq_get_link_info_exit;
1871
1872 /* save off old link status information */
1873 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1874 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1875
1876 /* update link status */
1877 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1878 hw->phy.media_type = i40e_get_media_type(hw);
1879 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1880 hw_link_info->link_info = resp->link_info;
1881 hw_link_info->an_info = resp->an_info;
1882 hw_link_info->ext_info = resp->ext_info;
1883 hw_link_info->loopback = resp->loopback;
1884 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1885 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1886
1887 /* update fc info */
1888 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1889 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1890 if (tx_pause & rx_pause)
1891 hw->fc.current_mode = I40E_FC_FULL;
1892 else if (tx_pause)
1893 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1894 else if (rx_pause)
1895 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1896 else
1897 hw->fc.current_mode = I40E_FC_NONE;
1898
1899 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1900 hw_link_info->crc_enable = TRUE;
1901 else
1902 hw_link_info->crc_enable = FALSE;
1903
1904 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))
1905 hw_link_info->lse_enable = TRUE;
1906 else
1907 hw_link_info->lse_enable = FALSE;
1908
1909 if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1910 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1911 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1912
1913 /* save link status information */
1914 if (link)
1915 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1916 I40E_NONDMA_TO_NONDMA);
1917
1918 /* flag cleared so helper functions don't call AQ again */
1919 hw->phy.get_link_info = FALSE;
1920
1921 aq_get_link_info_exit:
1922 return status;
1923 }
1924
1925 /**
1926 * i40e_aq_set_phy_int_mask
1927 * @hw: pointer to the hw struct
1928 * @mask: interrupt mask to be set
1929 * @cmd_details: pointer to command details structure or NULL
1930 *
1931 * Set link interrupt mask.
1932 **/
i40e_aq_set_phy_int_mask(struct i40e_hw * hw,u16 mask,struct i40e_asq_cmd_details * cmd_details)1933 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1934 u16 mask,
1935 struct i40e_asq_cmd_details *cmd_details)
1936 {
1937 struct i40e_aq_desc desc;
1938 struct i40e_aqc_set_phy_int_mask *cmd =
1939 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1940 enum i40e_status_code status;
1941
1942 i40e_fill_default_direct_cmd_desc(&desc,
1943 i40e_aqc_opc_set_phy_int_mask);
1944
1945 cmd->event_mask = CPU_TO_LE16(mask);
1946
1947 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1948
1949 return status;
1950 }
1951
1952 /**
1953 * i40e_aq_get_local_advt_reg
1954 * @hw: pointer to the hw struct
1955 * @advt_reg: local AN advertisement register value
1956 * @cmd_details: pointer to command details structure or NULL
1957 *
1958 * Get the Local AN advertisement register value.
1959 **/
i40e_aq_get_local_advt_reg(struct i40e_hw * hw,u64 * advt_reg,struct i40e_asq_cmd_details * cmd_details)1960 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
1961 u64 *advt_reg,
1962 struct i40e_asq_cmd_details *cmd_details)
1963 {
1964 struct i40e_aq_desc desc;
1965 struct i40e_aqc_an_advt_reg *resp =
1966 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1967 enum i40e_status_code status;
1968
1969 i40e_fill_default_direct_cmd_desc(&desc,
1970 i40e_aqc_opc_get_local_advt_reg);
1971
1972 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1973
1974 if (status != I40E_SUCCESS)
1975 goto aq_get_local_advt_reg_exit;
1976
1977 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1978 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1979
1980 aq_get_local_advt_reg_exit:
1981 return status;
1982 }
1983
1984 /**
1985 * i40e_aq_set_local_advt_reg
1986 * @hw: pointer to the hw struct
1987 * @advt_reg: local AN advertisement register value
1988 * @cmd_details: pointer to command details structure or NULL
1989 *
1990 * Get the Local AN advertisement register value.
1991 **/
i40e_aq_set_local_advt_reg(struct i40e_hw * hw,u64 advt_reg,struct i40e_asq_cmd_details * cmd_details)1992 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
1993 u64 advt_reg,
1994 struct i40e_asq_cmd_details *cmd_details)
1995 {
1996 struct i40e_aq_desc desc;
1997 struct i40e_aqc_an_advt_reg *cmd =
1998 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1999 enum i40e_status_code status;
2000
2001 i40e_fill_default_direct_cmd_desc(&desc,
2002 i40e_aqc_opc_get_local_advt_reg);
2003
2004 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2005 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2006
2007 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2008
2009 return status;
2010 }
2011
2012 /**
2013 * i40e_aq_get_partner_advt
2014 * @hw: pointer to the hw struct
2015 * @advt_reg: AN partner advertisement register value
2016 * @cmd_details: pointer to command details structure or NULL
2017 *
2018 * Get the link partner AN advertisement register value.
2019 **/
i40e_aq_get_partner_advt(struct i40e_hw * hw,u64 * advt_reg,struct i40e_asq_cmd_details * cmd_details)2020 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2021 u64 *advt_reg,
2022 struct i40e_asq_cmd_details *cmd_details)
2023 {
2024 struct i40e_aq_desc desc;
2025 struct i40e_aqc_an_advt_reg *resp =
2026 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2027 enum i40e_status_code status;
2028
2029 i40e_fill_default_direct_cmd_desc(&desc,
2030 i40e_aqc_opc_get_partner_advt);
2031
2032 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2033
2034 if (status != I40E_SUCCESS)
2035 goto aq_get_partner_advt_exit;
2036
2037 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2038 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2039
2040 aq_get_partner_advt_exit:
2041 return status;
2042 }
2043
2044 /**
2045 * i40e_aq_set_lb_modes
2046 * @hw: pointer to the hw struct
2047 * @lb_modes: loopback mode to be set
2048 * @cmd_details: pointer to command details structure or NULL
2049 *
2050 * Sets loopback modes.
2051 **/
i40e_aq_set_lb_modes(struct i40e_hw * hw,u16 lb_modes,struct i40e_asq_cmd_details * cmd_details)2052 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2053 u16 lb_modes,
2054 struct i40e_asq_cmd_details *cmd_details)
2055 {
2056 struct i40e_aq_desc desc;
2057 struct i40e_aqc_set_lb_mode *cmd =
2058 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2059 enum i40e_status_code status;
2060
2061 i40e_fill_default_direct_cmd_desc(&desc,
2062 i40e_aqc_opc_set_lb_modes);
2063
2064 cmd->lb_mode = CPU_TO_LE16(lb_modes);
2065
2066 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2067
2068 return status;
2069 }
2070
2071 /**
2072 * i40e_aq_set_phy_debug
2073 * @hw: pointer to the hw struct
2074 * @cmd_flags: debug command flags
2075 * @cmd_details: pointer to command details structure or NULL
2076 *
2077 * Reset the external PHY.
2078 **/
i40e_aq_set_phy_debug(struct i40e_hw * hw,u8 cmd_flags,struct i40e_asq_cmd_details * cmd_details)2079 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2080 struct i40e_asq_cmd_details *cmd_details)
2081 {
2082 struct i40e_aq_desc desc;
2083 struct i40e_aqc_set_phy_debug *cmd =
2084 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2085 enum i40e_status_code status;
2086
2087 i40e_fill_default_direct_cmd_desc(&desc,
2088 i40e_aqc_opc_set_phy_debug);
2089
2090 cmd->command_flags = cmd_flags;
2091
2092 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2093
2094 return status;
2095 }
2096
2097 /**
2098 * i40e_aq_add_vsi
2099 * @hw: pointer to the hw struct
2100 * @vsi_ctx: pointer to a vsi context struct
2101 * @cmd_details: pointer to command details structure or NULL
2102 *
2103 * Add a VSI context to the hardware.
2104 **/
i40e_aq_add_vsi(struct i40e_hw * hw,struct i40e_vsi_context * vsi_ctx,struct i40e_asq_cmd_details * cmd_details)2105 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2106 struct i40e_vsi_context *vsi_ctx,
2107 struct i40e_asq_cmd_details *cmd_details)
2108 {
2109 struct i40e_aq_desc desc;
2110 struct i40e_aqc_add_get_update_vsi *cmd =
2111 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2112 struct i40e_aqc_add_get_update_vsi_completion *resp =
2113 (struct i40e_aqc_add_get_update_vsi_completion *)
2114 &desc.params.raw;
2115 enum i40e_status_code status;
2116
2117 i40e_fill_default_direct_cmd_desc(&desc,
2118 i40e_aqc_opc_add_vsi);
2119
2120 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2121 cmd->connection_type = vsi_ctx->connection_type;
2122 cmd->vf_id = vsi_ctx->vf_num;
2123 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2124
2125 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2126
2127 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2128 sizeof(vsi_ctx->info), cmd_details);
2129
2130 if (status != I40E_SUCCESS)
2131 goto aq_add_vsi_exit;
2132
2133 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2134 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2135 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2136 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2137
2138 aq_add_vsi_exit:
2139 return status;
2140 }
2141
2142 /**
2143 * i40e_aq_set_default_vsi
2144 * @hw: pointer to the hw struct
2145 * @seid: vsi number
2146 * @cmd_details: pointer to command details structure or NULL
2147 **/
i40e_aq_set_default_vsi(struct i40e_hw * hw,u16 seid,struct i40e_asq_cmd_details * cmd_details)2148 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2149 u16 seid,
2150 struct i40e_asq_cmd_details *cmd_details)
2151 {
2152 struct i40e_aq_desc desc;
2153 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2154 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2155 &desc.params.raw;
2156 enum i40e_status_code status;
2157
2158 i40e_fill_default_direct_cmd_desc(&desc,
2159 i40e_aqc_opc_set_vsi_promiscuous_modes);
2160
2161 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2162 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2163 cmd->seid = CPU_TO_LE16(seid);
2164
2165 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2166
2167 return status;
2168 }
2169
2170 /**
2171 * i40e_aq_set_vsi_unicast_promiscuous
2172 * @hw: pointer to the hw struct
2173 * @seid: vsi number
2174 * @set: set unicast promiscuous enable/disable
2175 * @cmd_details: pointer to command details structure or NULL
2176 **/
i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw * hw,u16 seid,bool set,struct i40e_asq_cmd_details * cmd_details)2177 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2178 u16 seid, bool set,
2179 struct i40e_asq_cmd_details *cmd_details)
2180 {
2181 struct i40e_aq_desc desc;
2182 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2183 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2184 enum i40e_status_code status;
2185 u16 flags = 0;
2186
2187 i40e_fill_default_direct_cmd_desc(&desc,
2188 i40e_aqc_opc_set_vsi_promiscuous_modes);
2189
2190 if (set)
2191 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2192
2193 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2194
2195 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2196
2197 cmd->seid = CPU_TO_LE16(seid);
2198 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2199
2200 return status;
2201 }
2202
2203 /**
2204 * i40e_aq_set_vsi_multicast_promiscuous
2205 * @hw: pointer to the hw struct
2206 * @seid: vsi number
2207 * @set: set multicast promiscuous enable/disable
2208 * @cmd_details: pointer to command details structure or NULL
2209 **/
i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw * hw,u16 seid,bool set,struct i40e_asq_cmd_details * cmd_details)2210 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2211 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2212 {
2213 struct i40e_aq_desc desc;
2214 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2215 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2216 enum i40e_status_code status;
2217 u16 flags = 0;
2218
2219 i40e_fill_default_direct_cmd_desc(&desc,
2220 i40e_aqc_opc_set_vsi_promiscuous_modes);
2221
2222 if (set)
2223 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2224
2225 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2226
2227 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2228
2229 cmd->seid = CPU_TO_LE16(seid);
2230 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2231
2232 return status;
2233 }
2234
2235 /**
2236 * i40e_aq_set_vsi_mc_promisc_on_vlan
2237 * @hw: pointer to the hw struct
2238 * @seid: vsi number
2239 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2240 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2241 * @cmd_details: pointer to command details structure or NULL
2242 **/
i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw * hw,u16 seid,bool enable,u16 vid,struct i40e_asq_cmd_details * cmd_details)2243 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2244 u16 seid, bool enable, u16 vid,
2245 struct i40e_asq_cmd_details *cmd_details)
2246 {
2247 struct i40e_aq_desc desc;
2248 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2249 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2250 enum i40e_status_code status;
2251 u16 flags = 0;
2252
2253 i40e_fill_default_direct_cmd_desc(&desc,
2254 i40e_aqc_opc_set_vsi_promiscuous_modes);
2255
2256 if (enable)
2257 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2258
2259 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2260 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2261 cmd->seid = CPU_TO_LE16(seid);
2262 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2263
2264 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2265
2266 return status;
2267 }
2268
2269 /**
2270 * i40e_aq_set_vsi_uc_promisc_on_vlan
2271 * @hw: pointer to the hw struct
2272 * @seid: vsi number
2273 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2274 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2275 * @cmd_details: pointer to command details structure or NULL
2276 **/
i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw * hw,u16 seid,bool enable,u16 vid,struct i40e_asq_cmd_details * cmd_details)2277 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2278 u16 seid, bool enable, u16 vid,
2279 struct i40e_asq_cmd_details *cmd_details)
2280 {
2281 struct i40e_aq_desc desc;
2282 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2283 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2284 enum i40e_status_code status;
2285 u16 flags = 0;
2286
2287 i40e_fill_default_direct_cmd_desc(&desc,
2288 i40e_aqc_opc_set_vsi_promiscuous_modes);
2289
2290 if (enable)
2291 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2292
2293 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2294 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2295 cmd->seid = CPU_TO_LE16(seid);
2296 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2297
2298 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2299
2300 return status;
2301 }
2302
2303 /**
2304 * i40e_aq_set_vsi_broadcast
2305 * @hw: pointer to the hw struct
2306 * @seid: vsi number
2307 * @set_filter: TRUE to set filter, FALSE to clear filter
2308 * @cmd_details: pointer to command details structure or NULL
2309 *
2310 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2311 **/
i40e_aq_set_vsi_broadcast(struct i40e_hw * hw,u16 seid,bool set_filter,struct i40e_asq_cmd_details * cmd_details)2312 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2313 u16 seid, bool set_filter,
2314 struct i40e_asq_cmd_details *cmd_details)
2315 {
2316 struct i40e_aq_desc desc;
2317 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2318 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2319 enum i40e_status_code status;
2320
2321 i40e_fill_default_direct_cmd_desc(&desc,
2322 i40e_aqc_opc_set_vsi_promiscuous_modes);
2323
2324 if (set_filter)
2325 cmd->promiscuous_flags
2326 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2327 else
2328 cmd->promiscuous_flags
2329 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2330
2331 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2332 cmd->seid = CPU_TO_LE16(seid);
2333 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2334
2335 return status;
2336 }
2337
2338 /**
2339 * i40e_get_vsi_params - get VSI configuration info
2340 * @hw: pointer to the hw struct
2341 * @vsi_ctx: pointer to a vsi context struct
2342 * @cmd_details: pointer to command details structure or NULL
2343 **/
i40e_aq_get_vsi_params(struct i40e_hw * hw,struct i40e_vsi_context * vsi_ctx,struct i40e_asq_cmd_details * cmd_details)2344 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2345 struct i40e_vsi_context *vsi_ctx,
2346 struct i40e_asq_cmd_details *cmd_details)
2347 {
2348 struct i40e_aq_desc desc;
2349 struct i40e_aqc_add_get_update_vsi *cmd =
2350 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2351 struct i40e_aqc_add_get_update_vsi_completion *resp =
2352 (struct i40e_aqc_add_get_update_vsi_completion *)
2353 &desc.params.raw;
2354 enum i40e_status_code status;
2355
2356 i40e_fill_default_direct_cmd_desc(&desc,
2357 i40e_aqc_opc_get_vsi_parameters);
2358
2359 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2360
2361 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2362
2363 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2364 sizeof(vsi_ctx->info), NULL);
2365
2366 if (status != I40E_SUCCESS)
2367 goto aq_get_vsi_params_exit;
2368
2369 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2370 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2371 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2372 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2373
2374 aq_get_vsi_params_exit:
2375 return status;
2376 }
2377
2378 /**
2379 * i40e_aq_update_vsi_params
2380 * @hw: pointer to the hw struct
2381 * @vsi_ctx: pointer to a vsi context struct
2382 * @cmd_details: pointer to command details structure or NULL
2383 *
2384 * Update a VSI context.
2385 **/
i40e_aq_update_vsi_params(struct i40e_hw * hw,struct i40e_vsi_context * vsi_ctx,struct i40e_asq_cmd_details * cmd_details)2386 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2387 struct i40e_vsi_context *vsi_ctx,
2388 struct i40e_asq_cmd_details *cmd_details)
2389 {
2390 struct i40e_aq_desc desc;
2391 struct i40e_aqc_add_get_update_vsi *cmd =
2392 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2393 enum i40e_status_code status;
2394
2395 i40e_fill_default_direct_cmd_desc(&desc,
2396 i40e_aqc_opc_update_vsi_parameters);
2397 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2398
2399 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2400
2401 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2402 sizeof(vsi_ctx->info), cmd_details);
2403
2404 return status;
2405 }
2406
2407 /**
2408 * i40e_aq_get_switch_config
2409 * @hw: pointer to the hardware structure
2410 * @buf: pointer to the result buffer
2411 * @buf_size: length of input buffer
2412 * @start_seid: seid to start for the report, 0 == beginning
2413 * @cmd_details: pointer to command details structure or NULL
2414 *
2415 * Fill the buf with switch configuration returned from AdminQ command
2416 **/
i40e_aq_get_switch_config(struct i40e_hw * hw,struct i40e_aqc_get_switch_config_resp * buf,u16 buf_size,u16 * start_seid,struct i40e_asq_cmd_details * cmd_details)2417 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2418 struct i40e_aqc_get_switch_config_resp *buf,
2419 u16 buf_size, u16 *start_seid,
2420 struct i40e_asq_cmd_details *cmd_details)
2421 {
2422 struct i40e_aq_desc desc;
2423 struct i40e_aqc_switch_seid *scfg =
2424 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2425 enum i40e_status_code status;
2426
2427 i40e_fill_default_direct_cmd_desc(&desc,
2428 i40e_aqc_opc_get_switch_config);
2429 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2430 if (buf_size > I40E_AQ_LARGE_BUF)
2431 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2432 scfg->seid = CPU_TO_LE16(*start_seid);
2433
2434 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2435 *start_seid = LE16_TO_CPU(scfg->seid);
2436
2437 return status;
2438 }
2439
2440 /**
2441 * i40e_aq_get_firmware_version
2442 * @hw: pointer to the hw struct
2443 * @fw_major_version: firmware major version
2444 * @fw_minor_version: firmware minor version
2445 * @fw_build: firmware build number
2446 * @api_major_version: major queue version
2447 * @api_minor_version: minor queue version
2448 * @cmd_details: pointer to command details structure or NULL
2449 *
2450 * Get the firmware version from the admin queue commands
2451 **/
i40e_aq_get_firmware_version(struct i40e_hw * hw,u16 * fw_major_version,u16 * fw_minor_version,u32 * fw_build,u16 * api_major_version,u16 * api_minor_version,struct i40e_asq_cmd_details * cmd_details)2452 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2453 u16 *fw_major_version, u16 *fw_minor_version,
2454 u32 *fw_build,
2455 u16 *api_major_version, u16 *api_minor_version,
2456 struct i40e_asq_cmd_details *cmd_details)
2457 {
2458 struct i40e_aq_desc desc;
2459 struct i40e_aqc_get_version *resp =
2460 (struct i40e_aqc_get_version *)&desc.params.raw;
2461 enum i40e_status_code status;
2462
2463 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2464
2465 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2466
2467 if (status == I40E_SUCCESS) {
2468 if (fw_major_version != NULL)
2469 *fw_major_version = LE16_TO_CPU(resp->fw_major);
2470 if (fw_minor_version != NULL)
2471 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2472 if (fw_build != NULL)
2473 *fw_build = LE32_TO_CPU(resp->fw_build);
2474 if (api_major_version != NULL)
2475 *api_major_version = LE16_TO_CPU(resp->api_major);
2476 if (api_minor_version != NULL)
2477 *api_minor_version = LE16_TO_CPU(resp->api_minor);
2478
2479 /* A workaround to fix the API version in SW */
2480 if (api_major_version && api_minor_version &&
2481 fw_major_version && fw_minor_version &&
2482 ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2483 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2484 (*fw_major_version > 4)))
2485 *api_minor_version = 2;
2486 }
2487
2488 return status;
2489 }
2490
2491 /**
2492 * i40e_aq_send_driver_version
2493 * @hw: pointer to the hw struct
2494 * @dv: driver's major, minor version
2495 * @cmd_details: pointer to command details structure or NULL
2496 *
2497 * Send the driver version to the firmware
2498 **/
i40e_aq_send_driver_version(struct i40e_hw * hw,struct i40e_driver_version * dv,struct i40e_asq_cmd_details * cmd_details)2499 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2500 struct i40e_driver_version *dv,
2501 struct i40e_asq_cmd_details *cmd_details)
2502 {
2503 struct i40e_aq_desc desc;
2504 struct i40e_aqc_driver_version *cmd =
2505 (struct i40e_aqc_driver_version *)&desc.params.raw;
2506 enum i40e_status_code status;
2507 u16 len;
2508
2509 if (dv == NULL)
2510 return I40E_ERR_PARAM;
2511
2512 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2513
2514 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2515 cmd->driver_major_ver = dv->major_version;
2516 cmd->driver_minor_ver = dv->minor_version;
2517 cmd->driver_build_ver = dv->build_version;
2518 cmd->driver_subbuild_ver = dv->subbuild_version;
2519
2520 len = 0;
2521 while (len < sizeof(dv->driver_string) &&
2522 (dv->driver_string[len] < 0x80) &&
2523 dv->driver_string[len])
2524 len++;
2525 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2526 len, cmd_details);
2527
2528 return status;
2529 }
2530
2531 /**
2532 * i40e_get_link_status - get status of the HW network link
2533 * @hw: pointer to the hw struct
2534 * @link_up: pointer to bool (TRUE/FALSE = linkup/linkdown)
2535 *
2536 * Variable link_up TRUE if link is up, FALSE if link is down.
2537 * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2538 *
2539 * Side effect: LinkStatusEvent reporting becomes enabled
2540 **/
i40e_get_link_status(struct i40e_hw * hw,bool * link_up)2541 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2542 {
2543 enum i40e_status_code status = I40E_SUCCESS;
2544
2545 if (hw->phy.get_link_info) {
2546 status = i40e_update_link_info(hw);
2547
2548 if (status != I40E_SUCCESS)
2549 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2550 status);
2551 }
2552
2553 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2554
2555 return status;
2556 }
2557
2558 /**
2559 * i40e_updatelink_status - update status of the HW network link
2560 * @hw: pointer to the hw struct
2561 **/
i40e_update_link_info(struct i40e_hw * hw)2562 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2563 {
2564 struct i40e_aq_get_phy_abilities_resp abilities;
2565 enum i40e_status_code status = I40E_SUCCESS;
2566
2567 status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL);
2568 if (status)
2569 return status;
2570
2571 status = i40e_aq_get_phy_capabilities(hw, FALSE, false, &abilities,
2572 NULL);
2573 if (status)
2574 return status;
2575
2576 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2577 sizeof(hw->phy.link_info.module_type));
2578
2579 return status;
2580 }
2581
2582
2583 /**
2584 * i40e_get_link_speed
2585 * @hw: pointer to the hw struct
2586 *
2587 * Returns the link speed of the adapter.
2588 **/
i40e_get_link_speed(struct i40e_hw * hw)2589 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2590 {
2591 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2592 enum i40e_status_code status = I40E_SUCCESS;
2593
2594 if (hw->phy.get_link_info) {
2595 status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL);
2596
2597 if (status != I40E_SUCCESS)
2598 goto i40e_link_speed_exit;
2599 }
2600
2601 speed = hw->phy.link_info.link_speed;
2602
2603 i40e_link_speed_exit:
2604 return speed;
2605 }
2606
2607 /**
2608 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2609 * @hw: pointer to the hw struct
2610 * @uplink_seid: the MAC or other gizmo SEID
2611 * @downlink_seid: the VSI SEID
2612 * @enabled_tc: bitmap of TCs to be enabled
2613 * @default_port: TRUE for default port VSI, FALSE for control port
2614 * @enable_l2_filtering: TRUE to add L2 filter table rules to regular forwarding rules for cloud support
2615 * @veb_seid: pointer to where to put the resulting VEB SEID
2616 * @cmd_details: pointer to command details structure or NULL
2617 *
2618 * This asks the FW to add a VEB between the uplink and downlink
2619 * elements. If the uplink SEID is 0, this will be a floating VEB.
2620 **/
i40e_aq_add_veb(struct i40e_hw * hw,u16 uplink_seid,u16 downlink_seid,u8 enabled_tc,bool default_port,bool enable_l2_filtering,u16 * veb_seid,struct i40e_asq_cmd_details * cmd_details)2621 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2622 u16 downlink_seid, u8 enabled_tc,
2623 bool default_port, bool enable_l2_filtering,
2624 u16 *veb_seid,
2625 struct i40e_asq_cmd_details *cmd_details)
2626 {
2627 struct i40e_aq_desc desc;
2628 struct i40e_aqc_add_veb *cmd =
2629 (struct i40e_aqc_add_veb *)&desc.params.raw;
2630 struct i40e_aqc_add_veb_completion *resp =
2631 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2632 enum i40e_status_code status;
2633 u16 veb_flags = 0;
2634
2635 /* SEIDs need to either both be set or both be 0 for floating VEB */
2636 if (!!uplink_seid != !!downlink_seid)
2637 return I40E_ERR_PARAM;
2638
2639 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2640
2641 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2642 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2643 cmd->enable_tcs = enabled_tc;
2644 if (!uplink_seid)
2645 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2646 if (default_port)
2647 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2648 else
2649 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2650
2651 if (enable_l2_filtering)
2652 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
2653
2654 cmd->veb_flags = CPU_TO_LE16(veb_flags);
2655
2656 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2657
2658 if (!status && veb_seid)
2659 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2660
2661 return status;
2662 }
2663
2664 /**
2665 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2666 * @hw: pointer to the hw struct
2667 * @veb_seid: the SEID of the VEB to query
2668 * @switch_id: the uplink switch id
2669 * @floating: set to TRUE if the VEB is floating
2670 * @statistic_index: index of the stats counter block for this VEB
2671 * @vebs_used: number of VEB's used by function
2672 * @vebs_free: total VEB's not reserved by any function
2673 * @cmd_details: pointer to command details structure or NULL
2674 *
2675 * This retrieves the parameters for a particular VEB, specified by
2676 * uplink_seid, and returns them to the caller.
2677 **/
i40e_aq_get_veb_parameters(struct i40e_hw * hw,u16 veb_seid,u16 * switch_id,bool * floating,u16 * statistic_index,u16 * vebs_used,u16 * vebs_free,struct i40e_asq_cmd_details * cmd_details)2678 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2679 u16 veb_seid, u16 *switch_id,
2680 bool *floating, u16 *statistic_index,
2681 u16 *vebs_used, u16 *vebs_free,
2682 struct i40e_asq_cmd_details *cmd_details)
2683 {
2684 struct i40e_aq_desc desc;
2685 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2686 (struct i40e_aqc_get_veb_parameters_completion *)
2687 &desc.params.raw;
2688 enum i40e_status_code status;
2689
2690 if (veb_seid == 0)
2691 return I40E_ERR_PARAM;
2692
2693 i40e_fill_default_direct_cmd_desc(&desc,
2694 i40e_aqc_opc_get_veb_parameters);
2695 cmd_resp->seid = CPU_TO_LE16(veb_seid);
2696
2697 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2698 if (status)
2699 goto get_veb_exit;
2700
2701 if (switch_id)
2702 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2703 if (statistic_index)
2704 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2705 if (vebs_used)
2706 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2707 if (vebs_free)
2708 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2709 if (floating) {
2710 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2711
2712 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2713 *floating = TRUE;
2714 else
2715 *floating = FALSE;
2716 }
2717
2718 get_veb_exit:
2719 return status;
2720 }
2721
2722 /**
2723 * i40e_aq_add_macvlan
2724 * @hw: pointer to the hw struct
2725 * @seid: VSI for the mac address
2726 * @mv_list: list of macvlans to be added
2727 * @count: length of the list
2728 * @cmd_details: pointer to command details structure or NULL
2729 *
2730 * Add MAC/VLAN addresses to the HW filtering
2731 **/
i40e_aq_add_macvlan(struct i40e_hw * hw,u16 seid,struct i40e_aqc_add_macvlan_element_data * mv_list,u16 count,struct i40e_asq_cmd_details * cmd_details)2732 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2733 struct i40e_aqc_add_macvlan_element_data *mv_list,
2734 u16 count, struct i40e_asq_cmd_details *cmd_details)
2735 {
2736 struct i40e_aq_desc desc;
2737 struct i40e_aqc_macvlan *cmd =
2738 (struct i40e_aqc_macvlan *)&desc.params.raw;
2739 enum i40e_status_code status;
2740 u16 buf_size;
2741
2742 if (count == 0 || !mv_list || !hw)
2743 return I40E_ERR_PARAM;
2744
2745 buf_size = count * sizeof(*mv_list);
2746
2747 /* prep the rest of the request */
2748 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2749 cmd->num_addresses = CPU_TO_LE16(count);
2750 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2751 cmd->seid[1] = 0;
2752 cmd->seid[2] = 0;
2753
2754 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2755 if (buf_size > I40E_AQ_LARGE_BUF)
2756 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2757
2758 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2759 cmd_details);
2760
2761 return status;
2762 }
2763
2764 /**
2765 * i40e_aq_remove_macvlan
2766 * @hw: pointer to the hw struct
2767 * @seid: VSI for the mac address
2768 * @mv_list: list of macvlans to be removed
2769 * @count: length of the list
2770 * @cmd_details: pointer to command details structure or NULL
2771 *
2772 * Remove MAC/VLAN addresses from the HW filtering
2773 **/
i40e_aq_remove_macvlan(struct i40e_hw * hw,u16 seid,struct i40e_aqc_remove_macvlan_element_data * mv_list,u16 count,struct i40e_asq_cmd_details * cmd_details)2774 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2775 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2776 u16 count, struct i40e_asq_cmd_details *cmd_details)
2777 {
2778 struct i40e_aq_desc desc;
2779 struct i40e_aqc_macvlan *cmd =
2780 (struct i40e_aqc_macvlan *)&desc.params.raw;
2781 enum i40e_status_code status;
2782 u16 buf_size;
2783
2784 if (count == 0 || !mv_list || !hw)
2785 return I40E_ERR_PARAM;
2786
2787 buf_size = count * sizeof(*mv_list);
2788
2789 /* prep the rest of the request */
2790 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2791 cmd->num_addresses = CPU_TO_LE16(count);
2792 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2793 cmd->seid[1] = 0;
2794 cmd->seid[2] = 0;
2795
2796 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2797 if (buf_size > I40E_AQ_LARGE_BUF)
2798 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2799
2800 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2801 cmd_details);
2802
2803 return status;
2804 }
2805
2806 /**
2807 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
2808 * @hw: pointer to the hw struct
2809 * @seid: VSI for the vlan filters
2810 * @v_list: list of vlan filters to be added
2811 * @count: length of the list
2812 * @cmd_details: pointer to command details structure or NULL
2813 **/
i40e_aq_add_vlan(struct i40e_hw * hw,u16 seid,struct i40e_aqc_add_remove_vlan_element_data * v_list,u8 count,struct i40e_asq_cmd_details * cmd_details)2814 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
2815 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2816 u8 count, struct i40e_asq_cmd_details *cmd_details)
2817 {
2818 struct i40e_aq_desc desc;
2819 struct i40e_aqc_macvlan *cmd =
2820 (struct i40e_aqc_macvlan *)&desc.params.raw;
2821 enum i40e_status_code status;
2822 u16 buf_size;
2823
2824 if (count == 0 || !v_list || !hw)
2825 return I40E_ERR_PARAM;
2826
2827 buf_size = count * sizeof(*v_list);
2828
2829 /* prep the rest of the request */
2830 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
2831 cmd->num_addresses = CPU_TO_LE16(count);
2832 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2833 cmd->seid[1] = 0;
2834 cmd->seid[2] = 0;
2835
2836 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2837 if (buf_size > I40E_AQ_LARGE_BUF)
2838 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2839
2840 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2841 cmd_details);
2842
2843 return status;
2844 }
2845
2846 /**
2847 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
2848 * @hw: pointer to the hw struct
2849 * @seid: VSI for the vlan filters
2850 * @v_list: list of macvlans to be removed
2851 * @count: length of the list
2852 * @cmd_details: pointer to command details structure or NULL
2853 **/
i40e_aq_remove_vlan(struct i40e_hw * hw,u16 seid,struct i40e_aqc_add_remove_vlan_element_data * v_list,u8 count,struct i40e_asq_cmd_details * cmd_details)2854 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
2855 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2856 u8 count, struct i40e_asq_cmd_details *cmd_details)
2857 {
2858 struct i40e_aq_desc desc;
2859 struct i40e_aqc_macvlan *cmd =
2860 (struct i40e_aqc_macvlan *)&desc.params.raw;
2861 enum i40e_status_code status;
2862 u16 buf_size;
2863
2864 if (count == 0 || !v_list || !hw)
2865 return I40E_ERR_PARAM;
2866
2867 buf_size = count * sizeof(*v_list);
2868
2869 /* prep the rest of the request */
2870 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
2871 cmd->num_addresses = CPU_TO_LE16(count);
2872 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2873 cmd->seid[1] = 0;
2874 cmd->seid[2] = 0;
2875
2876 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2877 if (buf_size > I40E_AQ_LARGE_BUF)
2878 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2879
2880 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2881 cmd_details);
2882
2883 return status;
2884 }
2885
2886 /**
2887 * i40e_aq_send_msg_to_vf
2888 * @hw: pointer to the hardware structure
2889 * @vfid: vf id to send msg
2890 * @v_opcode: opcodes for VF-PF communication
2891 * @v_retval: return error code
2892 * @msg: pointer to the msg buffer
2893 * @msglen: msg length
2894 * @cmd_details: pointer to command details
2895 *
2896 * send msg to vf
2897 **/
i40e_aq_send_msg_to_vf(struct i40e_hw * hw,u16 vfid,u32 v_opcode,u32 v_retval,u8 * msg,u16 msglen,struct i40e_asq_cmd_details * cmd_details)2898 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2899 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2900 struct i40e_asq_cmd_details *cmd_details)
2901 {
2902 struct i40e_aq_desc desc;
2903 struct i40e_aqc_pf_vf_message *cmd =
2904 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2905 enum i40e_status_code status;
2906
2907 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2908 cmd->id = CPU_TO_LE32(vfid);
2909 desc.cookie_high = CPU_TO_LE32(v_opcode);
2910 desc.cookie_low = CPU_TO_LE32(v_retval);
2911 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
2912 if (msglen) {
2913 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
2914 I40E_AQ_FLAG_RD));
2915 if (msglen > I40E_AQ_LARGE_BUF)
2916 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2917 desc.datalen = CPU_TO_LE16(msglen);
2918 }
2919 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2920
2921 return status;
2922 }
2923
2924 /**
2925 * i40e_aq_debug_read_register
2926 * @hw: pointer to the hw struct
2927 * @reg_addr: register address
2928 * @reg_val: register value
2929 * @cmd_details: pointer to command details structure or NULL
2930 *
2931 * Read the register using the admin queue commands
2932 **/
i40e_aq_debug_read_register(struct i40e_hw * hw,u32 reg_addr,u64 * reg_val,struct i40e_asq_cmd_details * cmd_details)2933 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
2934 u32 reg_addr, u64 *reg_val,
2935 struct i40e_asq_cmd_details *cmd_details)
2936 {
2937 struct i40e_aq_desc desc;
2938 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2939 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2940 enum i40e_status_code status;
2941
2942 if (reg_val == NULL)
2943 return I40E_ERR_PARAM;
2944
2945 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
2946
2947 cmd_resp->address = CPU_TO_LE32(reg_addr);
2948
2949 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2950
2951 if (status == I40E_SUCCESS) {
2952 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
2953 (u64)LE32_TO_CPU(cmd_resp->value_low);
2954 }
2955
2956 return status;
2957 }
2958
2959 /**
2960 * i40e_aq_debug_write_register
2961 * @hw: pointer to the hw struct
2962 * @reg_addr: register address
2963 * @reg_val: register value
2964 * @cmd_details: pointer to command details structure or NULL
2965 *
2966 * Write to a register using the admin queue commands
2967 **/
i40e_aq_debug_write_register(struct i40e_hw * hw,u32 reg_addr,u64 reg_val,struct i40e_asq_cmd_details * cmd_details)2968 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
2969 u32 reg_addr, u64 reg_val,
2970 struct i40e_asq_cmd_details *cmd_details)
2971 {
2972 struct i40e_aq_desc desc;
2973 struct i40e_aqc_debug_reg_read_write *cmd =
2974 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2975 enum i40e_status_code status;
2976
2977 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2978
2979 cmd->address = CPU_TO_LE32(reg_addr);
2980 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
2981 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
2982
2983 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2984
2985 return status;
2986 }
2987
2988 /**
2989 * i40e_aq_get_hmc_resource_profile
2990 * @hw: pointer to the hw struct
2991 * @profile: type of profile the HMC is to be set as
2992 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2993 * @cmd_details: pointer to command details structure or NULL
2994 *
2995 * query the HMC profile of the device.
2996 **/
i40e_aq_get_hmc_resource_profile(struct i40e_hw * hw,enum i40e_aq_hmc_profile * profile,u8 * pe_vf_enabled_count,struct i40e_asq_cmd_details * cmd_details)2997 enum i40e_status_code i40e_aq_get_hmc_resource_profile(struct i40e_hw *hw,
2998 enum i40e_aq_hmc_profile *profile,
2999 u8 *pe_vf_enabled_count,
3000 struct i40e_asq_cmd_details *cmd_details)
3001 {
3002 struct i40e_aq_desc desc;
3003 struct i40e_aq_get_set_hmc_resource_profile *resp =
3004 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
3005 enum i40e_status_code status;
3006
3007 i40e_fill_default_direct_cmd_desc(&desc,
3008 i40e_aqc_opc_query_hmc_resource_profile);
3009 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3010
3011 *profile = (enum i40e_aq_hmc_profile)(resp->pm_profile &
3012 I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK);
3013 *pe_vf_enabled_count = resp->pe_vf_enabled &
3014 I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK;
3015
3016 return status;
3017 }
3018
3019 /**
3020 * i40e_aq_set_hmc_resource_profile
3021 * @hw: pointer to the hw struct
3022 * @profile: type of profile the HMC is to be set as
3023 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
3024 * @cmd_details: pointer to command details structure or NULL
3025 *
3026 * set the HMC profile of the device.
3027 **/
i40e_aq_set_hmc_resource_profile(struct i40e_hw * hw,enum i40e_aq_hmc_profile profile,u8 pe_vf_enabled_count,struct i40e_asq_cmd_details * cmd_details)3028 enum i40e_status_code i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
3029 enum i40e_aq_hmc_profile profile,
3030 u8 pe_vf_enabled_count,
3031 struct i40e_asq_cmd_details *cmd_details)
3032 {
3033 struct i40e_aq_desc desc;
3034 struct i40e_aq_get_set_hmc_resource_profile *cmd =
3035 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
3036 enum i40e_status_code status;
3037
3038 i40e_fill_default_direct_cmd_desc(&desc,
3039 i40e_aqc_opc_set_hmc_resource_profile);
3040
3041 cmd->pm_profile = (u8)profile;
3042 cmd->pe_vf_enabled = pe_vf_enabled_count;
3043
3044 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3045
3046 return status;
3047 }
3048
3049 /**
3050 * i40e_aq_request_resource
3051 * @hw: pointer to the hw struct
3052 * @resource: resource id
3053 * @access: access type
3054 * @sdp_number: resource number
3055 * @timeout: the maximum time in ms that the driver may hold the resource
3056 * @cmd_details: pointer to command details structure or NULL
3057 *
3058 * requests common resource using the admin queue commands
3059 **/
i40e_aq_request_resource(struct i40e_hw * hw,enum i40e_aq_resources_ids resource,enum i40e_aq_resource_access_type access,u8 sdp_number,u64 * timeout,struct i40e_asq_cmd_details * cmd_details)3060 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3061 enum i40e_aq_resources_ids resource,
3062 enum i40e_aq_resource_access_type access,
3063 u8 sdp_number, u64 *timeout,
3064 struct i40e_asq_cmd_details *cmd_details)
3065 {
3066 struct i40e_aq_desc desc;
3067 struct i40e_aqc_request_resource *cmd_resp =
3068 (struct i40e_aqc_request_resource *)&desc.params.raw;
3069 enum i40e_status_code status;
3070
3071 DEBUGFUNC("i40e_aq_request_resource");
3072
3073 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3074
3075 cmd_resp->resource_id = CPU_TO_LE16(resource);
3076 cmd_resp->access_type = CPU_TO_LE16(access);
3077 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3078
3079 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3080 /* The completion specifies the maximum time in ms that the driver
3081 * may hold the resource in the Timeout field.
3082 * If the resource is held by someone else, the command completes with
3083 * busy return value and the timeout field indicates the maximum time
3084 * the current owner of the resource has to free it.
3085 */
3086 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3087 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3088
3089 return status;
3090 }
3091
3092 /**
3093 * i40e_aq_release_resource
3094 * @hw: pointer to the hw struct
3095 * @resource: resource id
3096 * @sdp_number: resource number
3097 * @cmd_details: pointer to command details structure or NULL
3098 *
3099 * release common resource using the admin queue commands
3100 **/
i40e_aq_release_resource(struct i40e_hw * hw,enum i40e_aq_resources_ids resource,u8 sdp_number,struct i40e_asq_cmd_details * cmd_details)3101 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3102 enum i40e_aq_resources_ids resource,
3103 u8 sdp_number,
3104 struct i40e_asq_cmd_details *cmd_details)
3105 {
3106 struct i40e_aq_desc desc;
3107 struct i40e_aqc_request_resource *cmd =
3108 (struct i40e_aqc_request_resource *)&desc.params.raw;
3109 enum i40e_status_code status;
3110
3111 DEBUGFUNC("i40e_aq_release_resource");
3112
3113 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3114
3115 cmd->resource_id = CPU_TO_LE16(resource);
3116 cmd->resource_number = CPU_TO_LE32(sdp_number);
3117
3118 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3119
3120 return status;
3121 }
3122
3123 /**
3124 * i40e_aq_read_nvm
3125 * @hw: pointer to the hw struct
3126 * @module_pointer: module pointer location in words from the NVM beginning
3127 * @offset: byte offset from the module beginning
3128 * @length: length of the section to be read (in bytes from the offset)
3129 * @data: command buffer (size [bytes] = length)
3130 * @last_command: tells if this is the last command in a series
3131 * @cmd_details: pointer to command details structure or NULL
3132 *
3133 * Read the NVM using the admin queue commands
3134 **/
i40e_aq_read_nvm(struct i40e_hw * hw,u8 module_pointer,u32 offset,u16 length,void * data,bool last_command,struct i40e_asq_cmd_details * cmd_details)3135 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3136 u32 offset, u16 length, void *data,
3137 bool last_command,
3138 struct i40e_asq_cmd_details *cmd_details)
3139 {
3140 struct i40e_aq_desc desc;
3141 struct i40e_aqc_nvm_update *cmd =
3142 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3143 enum i40e_status_code status;
3144
3145 DEBUGFUNC("i40e_aq_read_nvm");
3146
3147 /* In offset the highest byte must be zeroed. */
3148 if (offset & 0xFF000000) {
3149 status = I40E_ERR_PARAM;
3150 goto i40e_aq_read_nvm_exit;
3151 }
3152
3153 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3154
3155 /* If this is the last command in a series, set the proper flag. */
3156 if (last_command)
3157 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3158 cmd->module_pointer = module_pointer;
3159 cmd->offset = CPU_TO_LE32(offset);
3160 cmd->length = CPU_TO_LE16(length);
3161
3162 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3163 if (length > I40E_AQ_LARGE_BUF)
3164 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3165
3166 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3167
3168 i40e_aq_read_nvm_exit:
3169 return status;
3170 }
3171
3172 /**
3173 * i40e_aq_read_nvm_config - read an nvm config block
3174 * @hw: pointer to the hw struct
3175 * @cmd_flags: NVM access admin command bits
3176 * @field_id: field or feature id
3177 * @data: buffer for result
3178 * @buf_size: buffer size
3179 * @element_count: pointer to count of elements read by FW
3180 * @cmd_details: pointer to command details structure or NULL
3181 **/
i40e_aq_read_nvm_config(struct i40e_hw * hw,u8 cmd_flags,u32 field_id,void * data,u16 buf_size,u16 * element_count,struct i40e_asq_cmd_details * cmd_details)3182 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3183 u8 cmd_flags, u32 field_id, void *data,
3184 u16 buf_size, u16 *element_count,
3185 struct i40e_asq_cmd_details *cmd_details)
3186 {
3187 struct i40e_aq_desc desc;
3188 struct i40e_aqc_nvm_config_read *cmd =
3189 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3190 enum i40e_status_code status;
3191
3192 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3193 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3194 if (buf_size > I40E_AQ_LARGE_BUF)
3195 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3196
3197 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3198 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3199 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3200 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3201 else
3202 cmd->element_id_msw = 0;
3203
3204 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3205
3206 if (!status && element_count)
3207 *element_count = LE16_TO_CPU(cmd->element_count);
3208
3209 return status;
3210 }
3211
3212 /**
3213 * i40e_aq_write_nvm_config - write an nvm config block
3214 * @hw: pointer to the hw struct
3215 * @cmd_flags: NVM access admin command bits
3216 * @data: buffer for result
3217 * @buf_size: buffer size
3218 * @element_count: count of elements to be written
3219 * @cmd_details: pointer to command details structure or NULL
3220 **/
i40e_aq_write_nvm_config(struct i40e_hw * hw,u8 cmd_flags,void * data,u16 buf_size,u16 element_count,struct i40e_asq_cmd_details * cmd_details)3221 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3222 u8 cmd_flags, void *data, u16 buf_size,
3223 u16 element_count,
3224 struct i40e_asq_cmd_details *cmd_details)
3225 {
3226 struct i40e_aq_desc desc;
3227 struct i40e_aqc_nvm_config_write *cmd =
3228 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3229 enum i40e_status_code status;
3230
3231 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3232 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3233 if (buf_size > I40E_AQ_LARGE_BUF)
3234 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3235
3236 cmd->element_count = CPU_TO_LE16(element_count);
3237 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3238 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3239
3240 return status;
3241 }
3242
3243 /**
3244 * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3245 * @hw: pointer to the hw struct
3246 * @cmd_details: pointer to command details structure or NULL
3247 **/
i40e_aq_oem_post_update(struct i40e_hw * hw,void * buff,u16 buff_size,struct i40e_asq_cmd_details * cmd_details)3248 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3249 void *buff, u16 buff_size,
3250 struct i40e_asq_cmd_details *cmd_details)
3251 {
3252 struct i40e_aq_desc desc;
3253 enum i40e_status_code status;
3254
3255
3256 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3257 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3258 if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3259 status = I40E_ERR_NOT_IMPLEMENTED;
3260
3261 return status;
3262 }
3263
3264 /**
3265 * i40e_aq_erase_nvm
3266 * @hw: pointer to the hw struct
3267 * @module_pointer: module pointer location in words from the NVM beginning
3268 * @offset: offset in the module (expressed in 4 KB from module's beginning)
3269 * @length: length of the section to be erased (expressed in 4 KB)
3270 * @last_command: tells if this is the last command in a series
3271 * @cmd_details: pointer to command details structure or NULL
3272 *
3273 * Erase the NVM sector using the admin queue commands
3274 **/
i40e_aq_erase_nvm(struct i40e_hw * hw,u8 module_pointer,u32 offset,u16 length,bool last_command,struct i40e_asq_cmd_details * cmd_details)3275 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3276 u32 offset, u16 length, bool last_command,
3277 struct i40e_asq_cmd_details *cmd_details)
3278 {
3279 struct i40e_aq_desc desc;
3280 struct i40e_aqc_nvm_update *cmd =
3281 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3282 enum i40e_status_code status;
3283
3284 DEBUGFUNC("i40e_aq_erase_nvm");
3285
3286 /* In offset the highest byte must be zeroed. */
3287 if (offset & 0xFF000000) {
3288 status = I40E_ERR_PARAM;
3289 goto i40e_aq_erase_nvm_exit;
3290 }
3291
3292 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3293
3294 /* If this is the last command in a series, set the proper flag. */
3295 if (last_command)
3296 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3297 cmd->module_pointer = module_pointer;
3298 cmd->offset = CPU_TO_LE32(offset);
3299 cmd->length = CPU_TO_LE16(length);
3300
3301 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3302
3303 i40e_aq_erase_nvm_exit:
3304 return status;
3305 }
3306
3307 #define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
3308 #define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
3309 #define I40E_DEV_FUNC_CAP_NPAR 0x03
3310 #define I40E_DEV_FUNC_CAP_OS2BMC 0x04
3311 #define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
3312 #define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
3313 #define I40E_DEV_FUNC_CAP_VF 0x13
3314 #define I40E_DEV_FUNC_CAP_VMDQ 0x14
3315 #define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
3316 #define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
3317 #define I40E_DEV_FUNC_CAP_VSI 0x17
3318 #define I40E_DEV_FUNC_CAP_DCB 0x18
3319 #define I40E_DEV_FUNC_CAP_FCOE 0x21
3320 #define I40E_DEV_FUNC_CAP_ISCSI 0x22
3321 #define I40E_DEV_FUNC_CAP_RSS 0x40
3322 #define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
3323 #define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
3324 #define I40E_DEV_FUNC_CAP_MSIX 0x43
3325 #define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
3326 #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
3327 #define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
3328 #define I40E_DEV_FUNC_CAP_FLEX10 0xF1
3329 #define I40E_DEV_FUNC_CAP_CEM 0xF2
3330 #define I40E_DEV_FUNC_CAP_IWARP 0x51
3331 #define I40E_DEV_FUNC_CAP_LED 0x61
3332 #define I40E_DEV_FUNC_CAP_SDP 0x62
3333 #define I40E_DEV_FUNC_CAP_MDIO 0x63
3334 #define I40E_DEV_FUNC_CAP_WR_CSR_PROT 0x64
3335
3336 /**
3337 * i40e_parse_discover_capabilities
3338 * @hw: pointer to the hw struct
3339 * @buff: pointer to a buffer containing device/function capability records
3340 * @cap_count: number of capability records in the list
3341 * @list_type_opc: type of capabilities list to parse
3342 *
3343 * Parse the device/function capabilities list.
3344 **/
i40e_parse_discover_capabilities(struct i40e_hw * hw,void * buff,u32 cap_count,enum i40e_admin_queue_opc list_type_opc)3345 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3346 u32 cap_count,
3347 enum i40e_admin_queue_opc list_type_opc)
3348 {
3349 struct i40e_aqc_list_capabilities_element_resp *cap;
3350 u32 valid_functions, num_functions;
3351 u32 number, logical_id, phys_id;
3352 struct i40e_hw_capabilities *p;
3353 u8 major_rev;
3354 u32 i = 0;
3355 u16 id;
3356
3357 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3358
3359 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3360 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3361 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3362 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3363 else
3364 return;
3365
3366 for (i = 0; i < cap_count; i++, cap++) {
3367 id = LE16_TO_CPU(cap->id);
3368 number = LE32_TO_CPU(cap->number);
3369 logical_id = LE32_TO_CPU(cap->logical_id);
3370 phys_id = LE32_TO_CPU(cap->phys_id);
3371 major_rev = cap->major_rev;
3372
3373 switch (id) {
3374 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
3375 p->switch_mode = number;
3376 break;
3377 case I40E_DEV_FUNC_CAP_MGMT_MODE:
3378 p->management_mode = number;
3379 break;
3380 case I40E_DEV_FUNC_CAP_NPAR:
3381 p->npar_enable = number;
3382 break;
3383 case I40E_DEV_FUNC_CAP_OS2BMC:
3384 p->os2bmc = number;
3385 break;
3386 case I40E_DEV_FUNC_CAP_VALID_FUNC:
3387 p->valid_functions = number;
3388 break;
3389 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
3390 if (number == 1)
3391 p->sr_iov_1_1 = TRUE;
3392 break;
3393 case I40E_DEV_FUNC_CAP_VF:
3394 p->num_vfs = number;
3395 p->vf_base_id = logical_id;
3396 break;
3397 case I40E_DEV_FUNC_CAP_VMDQ:
3398 if (number == 1)
3399 p->vmdq = TRUE;
3400 break;
3401 case I40E_DEV_FUNC_CAP_802_1_QBG:
3402 if (number == 1)
3403 p->evb_802_1_qbg = TRUE;
3404 break;
3405 case I40E_DEV_FUNC_CAP_802_1_QBH:
3406 if (number == 1)
3407 p->evb_802_1_qbh = TRUE;
3408 break;
3409 case I40E_DEV_FUNC_CAP_VSI:
3410 p->num_vsis = number;
3411 break;
3412 case I40E_DEV_FUNC_CAP_DCB:
3413 if (number == 1) {
3414 p->dcb = TRUE;
3415 p->enabled_tcmap = logical_id;
3416 p->maxtc = phys_id;
3417 }
3418 break;
3419 case I40E_DEV_FUNC_CAP_FCOE:
3420 if (number == 1)
3421 p->fcoe = TRUE;
3422 break;
3423 case I40E_DEV_FUNC_CAP_ISCSI:
3424 if (number == 1)
3425 p->iscsi = TRUE;
3426 break;
3427 case I40E_DEV_FUNC_CAP_RSS:
3428 p->rss = TRUE;
3429 p->rss_table_size = number;
3430 p->rss_table_entry_width = logical_id;
3431 break;
3432 case I40E_DEV_FUNC_CAP_RX_QUEUES:
3433 p->num_rx_qp = number;
3434 p->base_queue = phys_id;
3435 break;
3436 case I40E_DEV_FUNC_CAP_TX_QUEUES:
3437 p->num_tx_qp = number;
3438 p->base_queue = phys_id;
3439 break;
3440 case I40E_DEV_FUNC_CAP_MSIX:
3441 p->num_msix_vectors = number;
3442 break;
3443 case I40E_DEV_FUNC_CAP_MSIX_VF:
3444 p->num_msix_vectors_vf = number;
3445 break;
3446 case I40E_DEV_FUNC_CAP_FLEX10:
3447 if (major_rev == 1) {
3448 if (number == 1) {
3449 p->flex10_enable = TRUE;
3450 p->flex10_capable = TRUE;
3451 }
3452 } else {
3453 /* Capability revision >= 2 */
3454 if (number & 1)
3455 p->flex10_enable = TRUE;
3456 if (number & 2)
3457 p->flex10_capable = TRUE;
3458 }
3459 p->flex10_mode = logical_id;
3460 p->flex10_status = phys_id;
3461 break;
3462 case I40E_DEV_FUNC_CAP_CEM:
3463 if (number == 1)
3464 p->mgmt_cem = TRUE;
3465 break;
3466 case I40E_DEV_FUNC_CAP_IWARP:
3467 if (number == 1)
3468 p->iwarp = TRUE;
3469 break;
3470 case I40E_DEV_FUNC_CAP_LED:
3471 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3472 p->led[phys_id] = TRUE;
3473 break;
3474 case I40E_DEV_FUNC_CAP_SDP:
3475 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3476 p->sdp[phys_id] = TRUE;
3477 break;
3478 case I40E_DEV_FUNC_CAP_MDIO:
3479 if (number == 1) {
3480 p->mdio_port_num = phys_id;
3481 p->mdio_port_mode = logical_id;
3482 }
3483 break;
3484 case I40E_DEV_FUNC_CAP_IEEE_1588:
3485 if (number == 1)
3486 p->ieee_1588 = TRUE;
3487 break;
3488 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
3489 p->fd = TRUE;
3490 p->fd_filters_guaranteed = number;
3491 p->fd_filters_best_effort = logical_id;
3492 break;
3493 case I40E_DEV_FUNC_CAP_WR_CSR_PROT:
3494 p->wr_csr_prot = (u64)number;
3495 p->wr_csr_prot |= (u64)logical_id << 32;
3496 break;
3497 default:
3498 break;
3499 }
3500 }
3501
3502 if (p->fcoe)
3503 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3504
3505 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3506 p->fcoe = FALSE;
3507
3508 /* count the enabled ports (aka the "not disabled" ports) */
3509 hw->num_ports = 0;
3510 for (i = 0; i < 4; i++) {
3511 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3512 u64 port_cfg = 0;
3513
3514 /* use AQ read to get the physical register offset instead
3515 * of the port relative offset
3516 */
3517 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3518 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3519 hw->num_ports++;
3520 }
3521
3522 valid_functions = p->valid_functions;
3523 num_functions = 0;
3524 while (valid_functions) {
3525 if (valid_functions & 1)
3526 num_functions++;
3527 valid_functions >>= 1;
3528 }
3529
3530 /* partition id is 1-based, and functions are evenly spread
3531 * across the ports as partitions
3532 */
3533 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3534 hw->num_partitions = num_functions / hw->num_ports;
3535
3536 /* additional HW specific goodies that might
3537 * someday be HW version specific
3538 */
3539 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3540 }
3541
3542 /**
3543 * i40e_aq_discover_capabilities
3544 * @hw: pointer to the hw struct
3545 * @buff: a virtual buffer to hold the capabilities
3546 * @buff_size: Size of the virtual buffer
3547 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3548 * @list_type_opc: capabilities type to discover - pass in the command opcode
3549 * @cmd_details: pointer to command details structure or NULL
3550 *
3551 * Get the device capabilities descriptions from the firmware
3552 **/
i40e_aq_discover_capabilities(struct i40e_hw * hw,void * buff,u16 buff_size,u16 * data_size,enum i40e_admin_queue_opc list_type_opc,struct i40e_asq_cmd_details * cmd_details)3553 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3554 void *buff, u16 buff_size, u16 *data_size,
3555 enum i40e_admin_queue_opc list_type_opc,
3556 struct i40e_asq_cmd_details *cmd_details)
3557 {
3558 struct i40e_aqc_list_capabilites *cmd;
3559 struct i40e_aq_desc desc;
3560 enum i40e_status_code status = I40E_SUCCESS;
3561
3562 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3563
3564 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3565 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3566 status = I40E_ERR_PARAM;
3567 goto exit;
3568 }
3569
3570 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3571
3572 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3573 if (buff_size > I40E_AQ_LARGE_BUF)
3574 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3575
3576 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3577 *data_size = LE16_TO_CPU(desc.datalen);
3578
3579 if (status)
3580 goto exit;
3581
3582 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
3583 list_type_opc);
3584
3585 exit:
3586 return status;
3587 }
3588
3589 /**
3590 * i40e_aq_update_nvm
3591 * @hw: pointer to the hw struct
3592 * @module_pointer: module pointer location in words from the NVM beginning
3593 * @offset: byte offset from the module beginning
3594 * @length: length of the section to be written (in bytes from the offset)
3595 * @data: command buffer (size [bytes] = length)
3596 * @last_command: tells if this is the last command in a series
3597 * @cmd_details: pointer to command details structure or NULL
3598 *
3599 * Update the NVM using the admin queue commands
3600 **/
i40e_aq_update_nvm(struct i40e_hw * hw,u8 module_pointer,u32 offset,u16 length,void * data,bool last_command,struct i40e_asq_cmd_details * cmd_details)3601 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3602 u32 offset, u16 length, void *data,
3603 bool last_command,
3604 struct i40e_asq_cmd_details *cmd_details)
3605 {
3606 struct i40e_aq_desc desc;
3607 struct i40e_aqc_nvm_update *cmd =
3608 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3609 enum i40e_status_code status;
3610
3611 DEBUGFUNC("i40e_aq_update_nvm");
3612
3613 /* In offset the highest byte must be zeroed. */
3614 if (offset & 0xFF000000) {
3615 status = I40E_ERR_PARAM;
3616 goto i40e_aq_update_nvm_exit;
3617 }
3618
3619 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3620
3621 /* If this is the last command in a series, set the proper flag. */
3622 if (last_command)
3623 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3624 cmd->module_pointer = module_pointer;
3625 cmd->offset = CPU_TO_LE32(offset);
3626 cmd->length = CPU_TO_LE16(length);
3627
3628 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3629 if (length > I40E_AQ_LARGE_BUF)
3630 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3631
3632 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3633
3634 i40e_aq_update_nvm_exit:
3635 return status;
3636 }
3637
3638 /**
3639 * i40e_aq_get_lldp_mib
3640 * @hw: pointer to the hw struct
3641 * @bridge_type: type of bridge requested
3642 * @mib_type: Local, Remote or both Local and Remote MIBs
3643 * @buff: pointer to a user supplied buffer to store the MIB block
3644 * @buff_size: size of the buffer (in bytes)
3645 * @local_len : length of the returned Local LLDP MIB
3646 * @remote_len: length of the returned Remote LLDP MIB
3647 * @cmd_details: pointer to command details structure or NULL
3648 *
3649 * Requests the complete LLDP MIB (entire packet).
3650 **/
i40e_aq_get_lldp_mib(struct i40e_hw * hw,u8 bridge_type,u8 mib_type,void * buff,u16 buff_size,u16 * local_len,u16 * remote_len,struct i40e_asq_cmd_details * cmd_details)3651 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3652 u8 mib_type, void *buff, u16 buff_size,
3653 u16 *local_len, u16 *remote_len,
3654 struct i40e_asq_cmd_details *cmd_details)
3655 {
3656 struct i40e_aq_desc desc;
3657 struct i40e_aqc_lldp_get_mib *cmd =
3658 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3659 struct i40e_aqc_lldp_get_mib *resp =
3660 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3661 enum i40e_status_code status;
3662
3663 if (buff_size == 0 || !buff)
3664 return I40E_ERR_PARAM;
3665
3666 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3667 /* Indirect Command */
3668 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3669
3670 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3671 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3672 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3673
3674 desc.datalen = CPU_TO_LE16(buff_size);
3675
3676 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3677 if (buff_size > I40E_AQ_LARGE_BUF)
3678 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3679
3680 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3681 if (!status) {
3682 if (local_len != NULL)
3683 *local_len = LE16_TO_CPU(resp->local_len);
3684 if (remote_len != NULL)
3685 *remote_len = LE16_TO_CPU(resp->remote_len);
3686 }
3687
3688 return status;
3689 }
3690
3691 /**
3692 * i40e_aq_set_lldp_mib - Set the LLDP MIB
3693 * @hw: pointer to the hw struct
3694 * @mib_type: Local, Remote or both Local and Remote MIBs
3695 * @buff: pointer to a user supplied buffer to store the MIB block
3696 * @buff_size: size of the buffer (in bytes)
3697 * @cmd_details: pointer to command details structure or NULL
3698 *
3699 * Set the LLDP MIB.
3700 **/
i40e_aq_set_lldp_mib(struct i40e_hw * hw,u8 mib_type,void * buff,u16 buff_size,struct i40e_asq_cmd_details * cmd_details)3701 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
3702 u8 mib_type, void *buff, u16 buff_size,
3703 struct i40e_asq_cmd_details *cmd_details)
3704 {
3705 struct i40e_aq_desc desc;
3706 struct i40e_aqc_lldp_set_local_mib *cmd =
3707 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
3708 enum i40e_status_code status;
3709
3710 if (buff_size == 0 || !buff)
3711 return I40E_ERR_PARAM;
3712
3713 i40e_fill_default_direct_cmd_desc(&desc,
3714 i40e_aqc_opc_lldp_set_local_mib);
3715 /* Indirect Command */
3716 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3717 if (buff_size > I40E_AQ_LARGE_BUF)
3718 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3719 desc.datalen = CPU_TO_LE16(buff_size);
3720
3721 cmd->type = mib_type;
3722 cmd->length = CPU_TO_LE16(buff_size);
3723 cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
3724 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
3725
3726 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3727 return status;
3728 }
3729
3730 /**
3731 * i40e_aq_cfg_lldp_mib_change_event
3732 * @hw: pointer to the hw struct
3733 * @enable_update: Enable or Disable event posting
3734 * @cmd_details: pointer to command details structure or NULL
3735 *
3736 * Enable or Disable posting of an event on ARQ when LLDP MIB
3737 * associated with the interface changes
3738 **/
i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw * hw,bool enable_update,struct i40e_asq_cmd_details * cmd_details)3739 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3740 bool enable_update,
3741 struct i40e_asq_cmd_details *cmd_details)
3742 {
3743 struct i40e_aq_desc desc;
3744 struct i40e_aqc_lldp_update_mib *cmd =
3745 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3746 enum i40e_status_code status;
3747
3748 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3749
3750 if (!enable_update)
3751 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3752
3753 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3754
3755 return status;
3756 }
3757
3758 /**
3759 * i40e_aq_add_lldp_tlv
3760 * @hw: pointer to the hw struct
3761 * @bridge_type: type of bridge
3762 * @buff: buffer with TLV to add
3763 * @buff_size: length of the buffer
3764 * @tlv_len: length of the TLV to be added
3765 * @mib_len: length of the LLDP MIB returned in response
3766 * @cmd_details: pointer to command details structure or NULL
3767 *
3768 * Add the specified TLV to LLDP Local MIB for the given bridge type,
3769 * it is responsibility of the caller to make sure that the TLV is not
3770 * already present in the LLDPDU.
3771 * In return firmware will write the complete LLDP MIB with the newly
3772 * added TLV in the response buffer.
3773 **/
i40e_aq_add_lldp_tlv(struct i40e_hw * hw,u8 bridge_type,void * buff,u16 buff_size,u16 tlv_len,u16 * mib_len,struct i40e_asq_cmd_details * cmd_details)3774 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
3775 void *buff, u16 buff_size, u16 tlv_len,
3776 u16 *mib_len,
3777 struct i40e_asq_cmd_details *cmd_details)
3778 {
3779 struct i40e_aq_desc desc;
3780 struct i40e_aqc_lldp_add_tlv *cmd =
3781 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3782 enum i40e_status_code status;
3783
3784 if (buff_size == 0 || !buff || tlv_len == 0)
3785 return I40E_ERR_PARAM;
3786
3787 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
3788
3789 /* Indirect Command */
3790 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3791 if (buff_size > I40E_AQ_LARGE_BUF)
3792 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3793 desc.datalen = CPU_TO_LE16(buff_size);
3794
3795 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3796 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3797 cmd->len = CPU_TO_LE16(tlv_len);
3798
3799 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3800 if (!status) {
3801 if (mib_len != NULL)
3802 *mib_len = LE16_TO_CPU(desc.datalen);
3803 }
3804
3805 return status;
3806 }
3807
3808 /**
3809 * i40e_aq_update_lldp_tlv
3810 * @hw: pointer to the hw struct
3811 * @bridge_type: type of bridge
3812 * @buff: buffer with TLV to update
3813 * @buff_size: size of the buffer holding original and updated TLVs
3814 * @old_len: Length of the Original TLV
3815 * @new_len: Length of the Updated TLV
3816 * @offset: offset of the updated TLV in the buff
3817 * @mib_len: length of the returned LLDP MIB
3818 * @cmd_details: pointer to command details structure or NULL
3819 *
3820 * Update the specified TLV to the LLDP Local MIB for the given bridge type.
3821 * Firmware will place the complete LLDP MIB in response buffer with the
3822 * updated TLV.
3823 **/
i40e_aq_update_lldp_tlv(struct i40e_hw * hw,u8 bridge_type,void * buff,u16 buff_size,u16 old_len,u16 new_len,u16 offset,u16 * mib_len,struct i40e_asq_cmd_details * cmd_details)3824 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
3825 u8 bridge_type, void *buff, u16 buff_size,
3826 u16 old_len, u16 new_len, u16 offset,
3827 u16 *mib_len,
3828 struct i40e_asq_cmd_details *cmd_details)
3829 {
3830 struct i40e_aq_desc desc;
3831 struct i40e_aqc_lldp_update_tlv *cmd =
3832 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
3833 enum i40e_status_code status;
3834
3835 if (buff_size == 0 || !buff || offset == 0 ||
3836 old_len == 0 || new_len == 0)
3837 return I40E_ERR_PARAM;
3838
3839 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
3840
3841 /* Indirect Command */
3842 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3843 if (buff_size > I40E_AQ_LARGE_BUF)
3844 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3845 desc.datalen = CPU_TO_LE16(buff_size);
3846
3847 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3848 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3849 cmd->old_len = CPU_TO_LE16(old_len);
3850 cmd->new_offset = CPU_TO_LE16(offset);
3851 cmd->new_len = CPU_TO_LE16(new_len);
3852
3853 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3854 if (!status) {
3855 if (mib_len != NULL)
3856 *mib_len = LE16_TO_CPU(desc.datalen);
3857 }
3858
3859 return status;
3860 }
3861
3862 /**
3863 * i40e_aq_delete_lldp_tlv
3864 * @hw: pointer to the hw struct
3865 * @bridge_type: type of bridge
3866 * @buff: pointer to a user supplied buffer that has the TLV
3867 * @buff_size: length of the buffer
3868 * @tlv_len: length of the TLV to be deleted
3869 * @mib_len: length of the returned LLDP MIB
3870 * @cmd_details: pointer to command details structure or NULL
3871 *
3872 * Delete the specified TLV from LLDP Local MIB for the given bridge type.
3873 * The firmware places the entire LLDP MIB in the response buffer.
3874 **/
i40e_aq_delete_lldp_tlv(struct i40e_hw * hw,u8 bridge_type,void * buff,u16 buff_size,u16 tlv_len,u16 * mib_len,struct i40e_asq_cmd_details * cmd_details)3875 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
3876 u8 bridge_type, void *buff, u16 buff_size,
3877 u16 tlv_len, u16 *mib_len,
3878 struct i40e_asq_cmd_details *cmd_details)
3879 {
3880 struct i40e_aq_desc desc;
3881 struct i40e_aqc_lldp_add_tlv *cmd =
3882 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3883 enum i40e_status_code status;
3884
3885 if (buff_size == 0 || !buff)
3886 return I40E_ERR_PARAM;
3887
3888 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
3889
3890 /* Indirect Command */
3891 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3892 if (buff_size > I40E_AQ_LARGE_BUF)
3893 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3894 desc.datalen = CPU_TO_LE16(buff_size);
3895 cmd->len = CPU_TO_LE16(tlv_len);
3896 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3897 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3898
3899 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3900 if (!status) {
3901 if (mib_len != NULL)
3902 *mib_len = LE16_TO_CPU(desc.datalen);
3903 }
3904
3905 return status;
3906 }
3907
3908 /**
3909 * i40e_aq_stop_lldp
3910 * @hw: pointer to the hw struct
3911 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3912 * @cmd_details: pointer to command details structure or NULL
3913 *
3914 * Stop or Shutdown the embedded LLDP Agent
3915 **/
i40e_aq_stop_lldp(struct i40e_hw * hw,bool shutdown_agent,struct i40e_asq_cmd_details * cmd_details)3916 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3917 struct i40e_asq_cmd_details *cmd_details)
3918 {
3919 struct i40e_aq_desc desc;
3920 struct i40e_aqc_lldp_stop *cmd =
3921 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3922 enum i40e_status_code status;
3923
3924 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3925
3926 if (shutdown_agent)
3927 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3928
3929 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3930
3931 return status;
3932 }
3933
3934 /**
3935 * i40e_aq_start_lldp
3936 * @hw: pointer to the hw struct
3937 * @cmd_details: pointer to command details structure or NULL
3938 *
3939 * Start the embedded LLDP Agent on all ports.
3940 **/
i40e_aq_start_lldp(struct i40e_hw * hw,struct i40e_asq_cmd_details * cmd_details)3941 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
3942 struct i40e_asq_cmd_details *cmd_details)
3943 {
3944 struct i40e_aq_desc desc;
3945 struct i40e_aqc_lldp_start *cmd =
3946 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3947 enum i40e_status_code status;
3948
3949 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3950
3951 cmd->command = I40E_AQ_LLDP_AGENT_START;
3952
3953 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3954
3955 return status;
3956 }
3957
3958 /**
3959 * i40e_aq_get_cee_dcb_config
3960 * @hw: pointer to the hw struct
3961 * @buff: response buffer that stores CEE operational configuration
3962 * @buff_size: size of the buffer passed
3963 * @cmd_details: pointer to command details structure or NULL
3964 *
3965 * Get CEE DCBX mode operational configuration from firmware
3966 **/
i40e_aq_get_cee_dcb_config(struct i40e_hw * hw,void * buff,u16 buff_size,struct i40e_asq_cmd_details * cmd_details)3967 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3968 void *buff, u16 buff_size,
3969 struct i40e_asq_cmd_details *cmd_details)
3970 {
3971 struct i40e_aq_desc desc;
3972 enum i40e_status_code status;
3973
3974 if (buff_size == 0 || !buff)
3975 return I40E_ERR_PARAM;
3976
3977 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3978
3979 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3980 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3981 cmd_details);
3982
3983 return status;
3984 }
3985
3986 /**
3987 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
3988 * @hw: pointer to the hw struct
3989 * @start_agent: True if DCBx Agent needs to be Started
3990 * False if DCBx Agent needs to be Stopped
3991 * @cmd_details: pointer to command details structure or NULL
3992 *
3993 * Start/Stop the embedded dcbx Agent
3994 **/
i40e_aq_start_stop_dcbx(struct i40e_hw * hw,bool start_agent,struct i40e_asq_cmd_details * cmd_details)3995 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
3996 bool start_agent,
3997 struct i40e_asq_cmd_details *cmd_details)
3998 {
3999 struct i40e_aq_desc desc;
4000 struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4001 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4002 &desc.params.raw;
4003 enum i40e_status_code status;
4004
4005 i40e_fill_default_direct_cmd_desc(&desc,
4006 i40e_aqc_opc_lldp_stop_start_spec_agent);
4007
4008 if (start_agent)
4009 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4010
4011 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4012
4013 return status;
4014 }
4015
4016 /**
4017 * i40e_aq_add_udp_tunnel
4018 * @hw: pointer to the hw struct
4019 * @udp_port: the UDP port to add
4020 * @header_len: length of the tunneling header length in DWords
4021 * @protocol_index: protocol index type
4022 * @filter_index: pointer to filter index
4023 * @cmd_details: pointer to command details structure or NULL
4024 **/
i40e_aq_add_udp_tunnel(struct i40e_hw * hw,u16 udp_port,u8 protocol_index,u8 * filter_index,struct i40e_asq_cmd_details * cmd_details)4025 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4026 u16 udp_port, u8 protocol_index,
4027 u8 *filter_index,
4028 struct i40e_asq_cmd_details *cmd_details)
4029 {
4030 struct i40e_aq_desc desc;
4031 struct i40e_aqc_add_udp_tunnel *cmd =
4032 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4033 struct i40e_aqc_del_udp_tunnel_completion *resp =
4034 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4035 enum i40e_status_code status;
4036
4037 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4038
4039 cmd->udp_port = CPU_TO_LE16(udp_port);
4040 cmd->protocol_type = protocol_index;
4041
4042 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4043
4044 if (!status && filter_index)
4045 *filter_index = resp->index;
4046
4047 return status;
4048 }
4049
4050 /**
4051 * i40e_aq_del_udp_tunnel
4052 * @hw: pointer to the hw struct
4053 * @index: filter index
4054 * @cmd_details: pointer to command details structure or NULL
4055 **/
i40e_aq_del_udp_tunnel(struct i40e_hw * hw,u8 index,struct i40e_asq_cmd_details * cmd_details)4056 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4057 struct i40e_asq_cmd_details *cmd_details)
4058 {
4059 struct i40e_aq_desc desc;
4060 struct i40e_aqc_remove_udp_tunnel *cmd =
4061 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4062 enum i40e_status_code status;
4063
4064 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4065
4066 cmd->index = index;
4067
4068 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4069
4070 return status;
4071 }
4072
4073 /**
4074 * i40e_aq_get_switch_resource_alloc (0x0204)
4075 * @hw: pointer to the hw struct
4076 * @num_entries: pointer to u8 to store the number of resource entries returned
4077 * @buf: pointer to a user supplied buffer. This buffer must be large enough
4078 * to store the resource information for all resource types. Each
4079 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
4080 * @count: size, in bytes, of the buffer provided
4081 * @cmd_details: pointer to command details structure or NULL
4082 *
4083 * Query the resources allocated to a function.
4084 **/
i40e_aq_get_switch_resource_alloc(struct i40e_hw * hw,u8 * num_entries,struct i40e_aqc_switch_resource_alloc_element_resp * buf,u16 count,struct i40e_asq_cmd_details * cmd_details)4085 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4086 u8 *num_entries,
4087 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4088 u16 count,
4089 struct i40e_asq_cmd_details *cmd_details)
4090 {
4091 struct i40e_aq_desc desc;
4092 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4093 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4094 enum i40e_status_code status;
4095 u16 length = count * sizeof(*buf);
4096
4097 i40e_fill_default_direct_cmd_desc(&desc,
4098 i40e_aqc_opc_get_switch_resource_alloc);
4099
4100 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4101 if (length > I40E_AQ_LARGE_BUF)
4102 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4103
4104 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4105
4106 if (!status && num_entries)
4107 *num_entries = cmd_resp->num_entries;
4108
4109 return status;
4110 }
4111
4112 /**
4113 * i40e_aq_delete_element - Delete switch element
4114 * @hw: pointer to the hw struct
4115 * @seid: the SEID to delete from the switch
4116 * @cmd_details: pointer to command details structure or NULL
4117 *
4118 * This deletes a switch element from the switch.
4119 **/
i40e_aq_delete_element(struct i40e_hw * hw,u16 seid,struct i40e_asq_cmd_details * cmd_details)4120 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4121 struct i40e_asq_cmd_details *cmd_details)
4122 {
4123 struct i40e_aq_desc desc;
4124 struct i40e_aqc_switch_seid *cmd =
4125 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4126 enum i40e_status_code status;
4127
4128 if (seid == 0)
4129 return I40E_ERR_PARAM;
4130
4131 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4132
4133 cmd->seid = CPU_TO_LE16(seid);
4134
4135 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4136
4137 return status;
4138 }
4139
4140 /**
4141 * i40_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4142 * @hw: pointer to the hw struct
4143 * @flags: component flags
4144 * @mac_seid: uplink seid (MAC SEID)
4145 * @vsi_seid: connected vsi seid
4146 * @ret_seid: seid of create pv component
4147 *
4148 * This instantiates an i40e port virtualizer with specified flags.
4149 * Depending on specified flags the port virtualizer can act as a
4150 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4151 */
i40e_aq_add_pvirt(struct i40e_hw * hw,u16 flags,u16 mac_seid,u16 vsi_seid,u16 * ret_seid)4152 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4153 u16 mac_seid, u16 vsi_seid,
4154 u16 *ret_seid)
4155 {
4156 struct i40e_aq_desc desc;
4157 struct i40e_aqc_add_update_pv *cmd =
4158 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4159 struct i40e_aqc_add_update_pv_completion *resp =
4160 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4161 enum i40e_status_code status;
4162
4163 if (vsi_seid == 0)
4164 return I40E_ERR_PARAM;
4165
4166 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4167 cmd->command_flags = CPU_TO_LE16(flags);
4168 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4169 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4170
4171 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4172 if (!status && ret_seid)
4173 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4174
4175 return status;
4176 }
4177
4178 /**
4179 * i40e_aq_add_tag - Add an S/E-tag
4180 * @hw: pointer to the hw struct
4181 * @direct_to_queue: should s-tag direct flow to a specific queue
4182 * @vsi_seid: VSI SEID to use this tag
4183 * @tag: value of the tag
4184 * @queue_num: queue number, only valid is direct_to_queue is TRUE
4185 * @tags_used: return value, number of tags in use by this PF
4186 * @tags_free: return value, number of unallocated tags
4187 * @cmd_details: pointer to command details structure or NULL
4188 *
4189 * This associates an S- or E-tag to a VSI in the switch complex. It returns
4190 * the number of tags allocated by the PF, and the number of unallocated
4191 * tags available.
4192 **/
i40e_aq_add_tag(struct i40e_hw * hw,bool direct_to_queue,u16 vsi_seid,u16 tag,u16 queue_num,u16 * tags_used,u16 * tags_free,struct i40e_asq_cmd_details * cmd_details)4193 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4194 u16 vsi_seid, u16 tag, u16 queue_num,
4195 u16 *tags_used, u16 *tags_free,
4196 struct i40e_asq_cmd_details *cmd_details)
4197 {
4198 struct i40e_aq_desc desc;
4199 struct i40e_aqc_add_tag *cmd =
4200 (struct i40e_aqc_add_tag *)&desc.params.raw;
4201 struct i40e_aqc_add_remove_tag_completion *resp =
4202 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4203 enum i40e_status_code status;
4204
4205 if (vsi_seid == 0)
4206 return I40E_ERR_PARAM;
4207
4208 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4209
4210 cmd->seid = CPU_TO_LE16(vsi_seid);
4211 cmd->tag = CPU_TO_LE16(tag);
4212 if (direct_to_queue) {
4213 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4214 cmd->queue_number = CPU_TO_LE16(queue_num);
4215 }
4216
4217 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4218
4219 if (!status) {
4220 if (tags_used != NULL)
4221 *tags_used = LE16_TO_CPU(resp->tags_used);
4222 if (tags_free != NULL)
4223 *tags_free = LE16_TO_CPU(resp->tags_free);
4224 }
4225
4226 return status;
4227 }
4228
4229 /**
4230 * i40e_aq_remove_tag - Remove an S- or E-tag
4231 * @hw: pointer to the hw struct
4232 * @vsi_seid: VSI SEID this tag is associated with
4233 * @tag: value of the S-tag to delete
4234 * @tags_used: return value, number of tags in use by this PF
4235 * @tags_free: return value, number of unallocated tags
4236 * @cmd_details: pointer to command details structure or NULL
4237 *
4238 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
4239 * the number of tags allocated by the PF, and the number of unallocated
4240 * tags available.
4241 **/
i40e_aq_remove_tag(struct i40e_hw * hw,u16 vsi_seid,u16 tag,u16 * tags_used,u16 * tags_free,struct i40e_asq_cmd_details * cmd_details)4242 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4243 u16 tag, u16 *tags_used, u16 *tags_free,
4244 struct i40e_asq_cmd_details *cmd_details)
4245 {
4246 struct i40e_aq_desc desc;
4247 struct i40e_aqc_remove_tag *cmd =
4248 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4249 struct i40e_aqc_add_remove_tag_completion *resp =
4250 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4251 enum i40e_status_code status;
4252
4253 if (vsi_seid == 0)
4254 return I40E_ERR_PARAM;
4255
4256 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4257
4258 cmd->seid = CPU_TO_LE16(vsi_seid);
4259 cmd->tag = CPU_TO_LE16(tag);
4260
4261 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4262
4263 if (!status) {
4264 if (tags_used != NULL)
4265 *tags_used = LE16_TO_CPU(resp->tags_used);
4266 if (tags_free != NULL)
4267 *tags_free = LE16_TO_CPU(resp->tags_free);
4268 }
4269
4270 return status;
4271 }
4272
4273 /**
4274 * i40e_aq_add_mcast_etag - Add a multicast E-tag
4275 * @hw: pointer to the hw struct
4276 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4277 * @etag: value of E-tag to add
4278 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4279 * @buf: address of indirect buffer
4280 * @tags_used: return value, number of E-tags in use by this port
4281 * @tags_free: return value, number of unallocated M-tags
4282 * @cmd_details: pointer to command details structure or NULL
4283 *
4284 * This associates a multicast E-tag to a port virtualizer. It will return
4285 * the number of tags allocated by the PF, and the number of unallocated
4286 * tags available.
4287 *
4288 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4289 * num_tags_in_buf long.
4290 **/
i40e_aq_add_mcast_etag(struct i40e_hw * hw,u16 pv_seid,u16 etag,u8 num_tags_in_buf,void * buf,u16 * tags_used,u16 * tags_free,struct i40e_asq_cmd_details * cmd_details)4291 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4292 u16 etag, u8 num_tags_in_buf, void *buf,
4293 u16 *tags_used, u16 *tags_free,
4294 struct i40e_asq_cmd_details *cmd_details)
4295 {
4296 struct i40e_aq_desc desc;
4297 struct i40e_aqc_add_remove_mcast_etag *cmd =
4298 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4299 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4300 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4301 enum i40e_status_code status;
4302 u16 length = sizeof(u16) * num_tags_in_buf;
4303
4304 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4305 return I40E_ERR_PARAM;
4306
4307 i40e_fill_default_direct_cmd_desc(&desc,
4308 i40e_aqc_opc_add_multicast_etag);
4309
4310 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4311 cmd->etag = CPU_TO_LE16(etag);
4312 cmd->num_unicast_etags = num_tags_in_buf;
4313
4314 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4315 if (length > I40E_AQ_LARGE_BUF)
4316 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4317
4318 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4319
4320 if (!status) {
4321 if (tags_used != NULL)
4322 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4323 if (tags_free != NULL)
4324 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4325 }
4326
4327 return status;
4328 }
4329
4330 /**
4331 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4332 * @hw: pointer to the hw struct
4333 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4334 * @etag: value of the E-tag to remove
4335 * @tags_used: return value, number of tags in use by this port
4336 * @tags_free: return value, number of unallocated tags
4337 * @cmd_details: pointer to command details structure or NULL
4338 *
4339 * This deletes an E-tag from the port virtualizer. It will return
4340 * the number of tags allocated by the port, and the number of unallocated
4341 * tags available.
4342 **/
i40e_aq_remove_mcast_etag(struct i40e_hw * hw,u16 pv_seid,u16 etag,u16 * tags_used,u16 * tags_free,struct i40e_asq_cmd_details * cmd_details)4343 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4344 u16 etag, u16 *tags_used, u16 *tags_free,
4345 struct i40e_asq_cmd_details *cmd_details)
4346 {
4347 struct i40e_aq_desc desc;
4348 struct i40e_aqc_add_remove_mcast_etag *cmd =
4349 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4350 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4351 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4352 enum i40e_status_code status;
4353
4354
4355 if (pv_seid == 0)
4356 return I40E_ERR_PARAM;
4357
4358 i40e_fill_default_direct_cmd_desc(&desc,
4359 i40e_aqc_opc_remove_multicast_etag);
4360
4361 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4362 cmd->etag = CPU_TO_LE16(etag);
4363
4364 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4365
4366 if (!status) {
4367 if (tags_used != NULL)
4368 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4369 if (tags_free != NULL)
4370 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4371 }
4372
4373 return status;
4374 }
4375
4376 /**
4377 * i40e_aq_update_tag - Update an S/E-tag
4378 * @hw: pointer to the hw struct
4379 * @vsi_seid: VSI SEID using this S-tag
4380 * @old_tag: old tag value
4381 * @new_tag: new tag value
4382 * @tags_used: return value, number of tags in use by this PF
4383 * @tags_free: return value, number of unallocated tags
4384 * @cmd_details: pointer to command details structure or NULL
4385 *
4386 * This updates the value of the tag currently attached to this VSI
4387 * in the switch complex. It will return the number of tags allocated
4388 * by the PF, and the number of unallocated tags available.
4389 **/
i40e_aq_update_tag(struct i40e_hw * hw,u16 vsi_seid,u16 old_tag,u16 new_tag,u16 * tags_used,u16 * tags_free,struct i40e_asq_cmd_details * cmd_details)4390 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4391 u16 old_tag, u16 new_tag, u16 *tags_used,
4392 u16 *tags_free,
4393 struct i40e_asq_cmd_details *cmd_details)
4394 {
4395 struct i40e_aq_desc desc;
4396 struct i40e_aqc_update_tag *cmd =
4397 (struct i40e_aqc_update_tag *)&desc.params.raw;
4398 struct i40e_aqc_update_tag_completion *resp =
4399 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4400 enum i40e_status_code status;
4401
4402 if (vsi_seid == 0)
4403 return I40E_ERR_PARAM;
4404
4405 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4406
4407 cmd->seid = CPU_TO_LE16(vsi_seid);
4408 cmd->old_tag = CPU_TO_LE16(old_tag);
4409 cmd->new_tag = CPU_TO_LE16(new_tag);
4410
4411 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4412
4413 if (!status) {
4414 if (tags_used != NULL)
4415 *tags_used = LE16_TO_CPU(resp->tags_used);
4416 if (tags_free != NULL)
4417 *tags_free = LE16_TO_CPU(resp->tags_free);
4418 }
4419
4420 return status;
4421 }
4422
4423 /**
4424 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4425 * @hw: pointer to the hw struct
4426 * @tcmap: TC map for request/release any ignore PFC condition
4427 * @request: request or release ignore PFC condition
4428 * @tcmap_ret: return TCs for which PFC is currently ignored
4429 * @cmd_details: pointer to command details structure or NULL
4430 *
4431 * This sends out request/release to ignore PFC condition for a TC.
4432 * It will return the TCs for which PFC is currently ignored.
4433 **/
i40e_aq_dcb_ignore_pfc(struct i40e_hw * hw,u8 tcmap,bool request,u8 * tcmap_ret,struct i40e_asq_cmd_details * cmd_details)4434 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4435 bool request, u8 *tcmap_ret,
4436 struct i40e_asq_cmd_details *cmd_details)
4437 {
4438 struct i40e_aq_desc desc;
4439 struct i40e_aqc_pfc_ignore *cmd_resp =
4440 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4441 enum i40e_status_code status;
4442
4443 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4444
4445 if (request)
4446 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4447
4448 cmd_resp->tc_bitmap = tcmap;
4449
4450 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4451
4452 if (!status) {
4453 if (tcmap_ret != NULL)
4454 *tcmap_ret = cmd_resp->tc_bitmap;
4455 }
4456
4457 return status;
4458 }
4459
4460 /**
4461 * i40e_aq_dcb_updated - DCB Updated Command
4462 * @hw: pointer to the hw struct
4463 * @cmd_details: pointer to command details structure or NULL
4464 *
4465 * When LLDP is handled in PF this command is used by the PF
4466 * to notify EMP that a DCB setting is modified.
4467 * When LLDP is handled in EMP this command is used by the PF
4468 * to notify EMP whenever one of the following parameters get
4469 * modified:
4470 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4471 * - PCIRTT in PRTDCB_GENC.PCIRTT
4472 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4473 * EMP will return when the shared RPB settings have been
4474 * recomputed and modified. The retval field in the descriptor
4475 * will be set to 0 when RPB is modified.
4476 **/
i40e_aq_dcb_updated(struct i40e_hw * hw,struct i40e_asq_cmd_details * cmd_details)4477 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4478 struct i40e_asq_cmd_details *cmd_details)
4479 {
4480 struct i40e_aq_desc desc;
4481 enum i40e_status_code status;
4482
4483 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4484
4485 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4486
4487 return status;
4488 }
4489
4490 /**
4491 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4492 * @hw: pointer to the hw struct
4493 * @seid: defines the SEID of the switch for which the stats are requested
4494 * @vlan_id: the VLAN ID for which the statistics are requested
4495 * @stat_index: index of the statistics counters block assigned to this VLAN
4496 * @cmd_details: pointer to command details structure or NULL
4497 *
4498 * XL710 supports 128 smonVlanStats counters.This command is used to
4499 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4500 * switch.
4501 **/
i40e_aq_add_statistics(struct i40e_hw * hw,u16 seid,u16 vlan_id,u16 * stat_index,struct i40e_asq_cmd_details * cmd_details)4502 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4503 u16 vlan_id, u16 *stat_index,
4504 struct i40e_asq_cmd_details *cmd_details)
4505 {
4506 struct i40e_aq_desc desc;
4507 struct i40e_aqc_add_remove_statistics *cmd_resp =
4508 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4509 enum i40e_status_code status;
4510
4511 if ((seid == 0) || (stat_index == NULL))
4512 return I40E_ERR_PARAM;
4513
4514 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4515
4516 cmd_resp->seid = CPU_TO_LE16(seid);
4517 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4518
4519 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4520
4521 if (!status && stat_index)
4522 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4523
4524 return status;
4525 }
4526
4527 /**
4528 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4529 * @hw: pointer to the hw struct
4530 * @seid: defines the SEID of the switch for which the stats are requested
4531 * @vlan_id: the VLAN ID for which the statistics are requested
4532 * @stat_index: index of the statistics counters block assigned to this VLAN
4533 * @cmd_details: pointer to command details structure or NULL
4534 *
4535 * XL710 supports 128 smonVlanStats counters.This command is used to
4536 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4537 * switch.
4538 **/
i40e_aq_remove_statistics(struct i40e_hw * hw,u16 seid,u16 vlan_id,u16 stat_index,struct i40e_asq_cmd_details * cmd_details)4539 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4540 u16 vlan_id, u16 stat_index,
4541 struct i40e_asq_cmd_details *cmd_details)
4542 {
4543 struct i40e_aq_desc desc;
4544 struct i40e_aqc_add_remove_statistics *cmd =
4545 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4546 enum i40e_status_code status;
4547
4548 if (seid == 0)
4549 return I40E_ERR_PARAM;
4550
4551 i40e_fill_default_direct_cmd_desc(&desc,
4552 i40e_aqc_opc_remove_statistics);
4553
4554 cmd->seid = CPU_TO_LE16(seid);
4555 cmd->vlan = CPU_TO_LE16(vlan_id);
4556 cmd->stat_index = CPU_TO_LE16(stat_index);
4557
4558 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4559
4560 return status;
4561 }
4562
4563 /**
4564 * i40e_aq_set_port_parameters - set physical port parameters.
4565 * @hw: pointer to the hw struct
4566 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
4567 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
4568 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
4569 * @double_vlan: if set double VLAN is enabled
4570 * @cmd_details: pointer to command details structure or NULL
4571 **/
i40e_aq_set_port_parameters(struct i40e_hw * hw,u16 bad_frame_vsi,bool save_bad_pac,bool pad_short_pac,bool double_vlan,struct i40e_asq_cmd_details * cmd_details)4572 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
4573 u16 bad_frame_vsi, bool save_bad_pac,
4574 bool pad_short_pac, bool double_vlan,
4575 struct i40e_asq_cmd_details *cmd_details)
4576 {
4577 struct i40e_aqc_set_port_parameters *cmd;
4578 enum i40e_status_code status;
4579 struct i40e_aq_desc desc;
4580 u16 command_flags = 0;
4581
4582 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
4583
4584 i40e_fill_default_direct_cmd_desc(&desc,
4585 i40e_aqc_opc_set_port_parameters);
4586
4587 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
4588 if (save_bad_pac)
4589 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
4590 if (pad_short_pac)
4591 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
4592 if (double_vlan)
4593 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
4594 cmd->command_flags = CPU_TO_LE16(command_flags);
4595
4596 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4597
4598 return status;
4599 }
4600
4601 /**
4602 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
4603 * @hw: pointer to the hw struct
4604 * @seid: seid for the physical port/switching component/vsi
4605 * @buff: Indirect buffer to hold data parameters and response
4606 * @buff_size: Indirect buffer size
4607 * @opcode: Tx scheduler AQ command opcode
4608 * @cmd_details: pointer to command details structure or NULL
4609 *
4610 * Generic command handler for Tx scheduler AQ commands
4611 **/
i40e_aq_tx_sched_cmd(struct i40e_hw * hw,u16 seid,void * buff,u16 buff_size,enum i40e_admin_queue_opc opcode,struct i40e_asq_cmd_details * cmd_details)4612 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
4613 void *buff, u16 buff_size,
4614 enum i40e_admin_queue_opc opcode,
4615 struct i40e_asq_cmd_details *cmd_details)
4616 {
4617 struct i40e_aq_desc desc;
4618 struct i40e_aqc_tx_sched_ind *cmd =
4619 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4620 enum i40e_status_code status;
4621 bool cmd_param_flag = FALSE;
4622
4623 switch (opcode) {
4624 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
4625 case i40e_aqc_opc_configure_vsi_tc_bw:
4626 case i40e_aqc_opc_enable_switching_comp_ets:
4627 case i40e_aqc_opc_modify_switching_comp_ets:
4628 case i40e_aqc_opc_disable_switching_comp_ets:
4629 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
4630 case i40e_aqc_opc_configure_switching_comp_bw_config:
4631 cmd_param_flag = TRUE;
4632 break;
4633 case i40e_aqc_opc_query_vsi_bw_config:
4634 case i40e_aqc_opc_query_vsi_ets_sla_config:
4635 case i40e_aqc_opc_query_switching_comp_ets_config:
4636 case i40e_aqc_opc_query_port_ets_config:
4637 case i40e_aqc_opc_query_switching_comp_bw_config:
4638 cmd_param_flag = FALSE;
4639 break;
4640 default:
4641 return I40E_ERR_PARAM;
4642 }
4643
4644 i40e_fill_default_direct_cmd_desc(&desc, opcode);
4645
4646 /* Indirect command */
4647 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4648 if (cmd_param_flag)
4649 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4650 if (buff_size > I40E_AQ_LARGE_BUF)
4651 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4652
4653 desc.datalen = CPU_TO_LE16(buff_size);
4654
4655 cmd->vsi_seid = CPU_TO_LE16(seid);
4656
4657 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4658
4659 return status;
4660 }
4661
4662 /**
4663 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
4664 * @hw: pointer to the hw struct
4665 * @seid: VSI seid
4666 * @credit: BW limit credits (0 = disabled)
4667 * @max_credit: Max BW limit credits
4668 * @cmd_details: pointer to command details structure or NULL
4669 **/
i40e_aq_config_vsi_bw_limit(struct i40e_hw * hw,u16 seid,u16 credit,u8 max_credit,struct i40e_asq_cmd_details * cmd_details)4670 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
4671 u16 seid, u16 credit, u8 max_credit,
4672 struct i40e_asq_cmd_details *cmd_details)
4673 {
4674 struct i40e_aq_desc desc;
4675 struct i40e_aqc_configure_vsi_bw_limit *cmd =
4676 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
4677 enum i40e_status_code status;
4678
4679 i40e_fill_default_direct_cmd_desc(&desc,
4680 i40e_aqc_opc_configure_vsi_bw_limit);
4681
4682 cmd->vsi_seid = CPU_TO_LE16(seid);
4683 cmd->credit = CPU_TO_LE16(credit);
4684 cmd->max_credit = max_credit;
4685
4686 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4687
4688 return status;
4689 }
4690
4691 /**
4692 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
4693 * @hw: pointer to the hw struct
4694 * @seid: switching component seid
4695 * @credit: BW limit credits (0 = disabled)
4696 * @max_bw: Max BW limit credits
4697 * @cmd_details: pointer to command details structure or NULL
4698 **/
i40e_aq_config_switch_comp_bw_limit(struct i40e_hw * hw,u16 seid,u16 credit,u8 max_bw,struct i40e_asq_cmd_details * cmd_details)4699 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
4700 u16 seid, u16 credit, u8 max_bw,
4701 struct i40e_asq_cmd_details *cmd_details)
4702 {
4703 struct i40e_aq_desc desc;
4704 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
4705 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
4706 enum i40e_status_code status;
4707
4708 i40e_fill_default_direct_cmd_desc(&desc,
4709 i40e_aqc_opc_configure_switching_comp_bw_limit);
4710
4711 cmd->seid = CPU_TO_LE16(seid);
4712 cmd->credit = CPU_TO_LE16(credit);
4713 cmd->max_bw = max_bw;
4714
4715 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4716
4717 return status;
4718 }
4719
4720 /**
4721 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
4722 * @hw: pointer to the hw struct
4723 * @seid: VSI seid
4724 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
4725 * @cmd_details: pointer to command details structure or NULL
4726 **/
i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw * hw,u16 seid,struct i40e_aqc_configure_vsi_ets_sla_bw_data * bw_data,struct i40e_asq_cmd_details * cmd_details)4727 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
4728 u16 seid,
4729 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
4730 struct i40e_asq_cmd_details *cmd_details)
4731 {
4732 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4733 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
4734 cmd_details);
4735 }
4736
4737 /**
4738 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
4739 * @hw: pointer to the hw struct
4740 * @seid: VSI seid
4741 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
4742 * @cmd_details: pointer to command details structure or NULL
4743 **/
i40e_aq_config_vsi_tc_bw(struct i40e_hw * hw,u16 seid,struct i40e_aqc_configure_vsi_tc_bw_data * bw_data,struct i40e_asq_cmd_details * cmd_details)4744 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
4745 u16 seid,
4746 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
4747 struct i40e_asq_cmd_details *cmd_details)
4748 {
4749 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4750 i40e_aqc_opc_configure_vsi_tc_bw,
4751 cmd_details);
4752 }
4753
4754 /**
4755 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
4756 * @hw: pointer to the hw struct
4757 * @seid: seid of the switching component
4758 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
4759 * @cmd_details: pointer to command details structure or NULL
4760 **/
i40e_aq_config_switch_comp_ets_bw_limit(struct i40e_hw * hw,u16 seid,struct i40e_aqc_configure_switching_comp_ets_bw_limit_data * bw_data,struct i40e_asq_cmd_details * cmd_details)4761 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
4762 struct i40e_hw *hw, u16 seid,
4763 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
4764 struct i40e_asq_cmd_details *cmd_details)
4765 {
4766 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4767 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
4768 cmd_details);
4769 }
4770
4771 /**
4772 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
4773 * @hw: pointer to the hw struct
4774 * @seid: seid of the VSI
4775 * @bw_data: Buffer to hold VSI BW configuration
4776 * @cmd_details: pointer to command details structure or NULL
4777 **/
i40e_aq_query_vsi_bw_config(struct i40e_hw * hw,u16 seid,struct i40e_aqc_query_vsi_bw_config_resp * bw_data,struct i40e_asq_cmd_details * cmd_details)4778 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
4779 u16 seid,
4780 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
4781 struct i40e_asq_cmd_details *cmd_details)
4782 {
4783 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4784 i40e_aqc_opc_query_vsi_bw_config,
4785 cmd_details);
4786 }
4787
4788 /**
4789 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
4790 * @hw: pointer to the hw struct
4791 * @seid: seid of the VSI
4792 * @bw_data: Buffer to hold VSI BW configuration per TC
4793 * @cmd_details: pointer to command details structure or NULL
4794 **/
i40e_aq_query_vsi_ets_sla_config(struct i40e_hw * hw,u16 seid,struct i40e_aqc_query_vsi_ets_sla_config_resp * bw_data,struct i40e_asq_cmd_details * cmd_details)4795 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
4796 u16 seid,
4797 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
4798 struct i40e_asq_cmd_details *cmd_details)
4799 {
4800 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4801 i40e_aqc_opc_query_vsi_ets_sla_config,
4802 cmd_details);
4803 }
4804
4805 /**
4806 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
4807 * @hw: pointer to the hw struct
4808 * @seid: seid of the switching component
4809 * @bw_data: Buffer to hold switching component's per TC BW config
4810 * @cmd_details: pointer to command details structure or NULL
4811 **/
i40e_aq_query_switch_comp_ets_config(struct i40e_hw * hw,u16 seid,struct i40e_aqc_query_switching_comp_ets_config_resp * bw_data,struct i40e_asq_cmd_details * cmd_details)4812 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
4813 u16 seid,
4814 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
4815 struct i40e_asq_cmd_details *cmd_details)
4816 {
4817 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4818 i40e_aqc_opc_query_switching_comp_ets_config,
4819 cmd_details);
4820 }
4821
4822 /**
4823 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
4824 * @hw: pointer to the hw struct
4825 * @seid: seid of the VSI or switching component connected to Physical Port
4826 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
4827 * @cmd_details: pointer to command details structure or NULL
4828 **/
i40e_aq_query_port_ets_config(struct i40e_hw * hw,u16 seid,struct i40e_aqc_query_port_ets_config_resp * bw_data,struct i40e_asq_cmd_details * cmd_details)4829 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
4830 u16 seid,
4831 struct i40e_aqc_query_port_ets_config_resp *bw_data,
4832 struct i40e_asq_cmd_details *cmd_details)
4833 {
4834 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4835 i40e_aqc_opc_query_port_ets_config,
4836 cmd_details);
4837 }
4838
4839 /**
4840 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
4841 * @hw: pointer to the hw struct
4842 * @seid: seid of the switching component
4843 * @bw_data: Buffer to hold switching component's BW configuration
4844 * @cmd_details: pointer to command details structure or NULL
4845 **/
i40e_aq_query_switch_comp_bw_config(struct i40e_hw * hw,u16 seid,struct i40e_aqc_query_switching_comp_bw_config_resp * bw_data,struct i40e_asq_cmd_details * cmd_details)4846 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
4847 u16 seid,
4848 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
4849 struct i40e_asq_cmd_details *cmd_details)
4850 {
4851 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4852 i40e_aqc_opc_query_switching_comp_bw_config,
4853 cmd_details);
4854 }
4855
4856 /**
4857 * i40e_validate_filter_settings
4858 * @hw: pointer to the hardware structure
4859 * @settings: Filter control settings
4860 *
4861 * Check and validate the filter control settings passed.
4862 * The function checks for the valid filter/context sizes being
4863 * passed for FCoE and PE.
4864 *
4865 * Returns I40E_SUCCESS if the values passed are valid and within
4866 * range else returns an error.
4867 **/
i40e_validate_filter_settings(struct i40e_hw * hw,struct i40e_filter_control_settings * settings)4868 static enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
4869 struct i40e_filter_control_settings *settings)
4870 {
4871 u32 fcoe_cntx_size, fcoe_filt_size;
4872 u32 pe_cntx_size, pe_filt_size;
4873 u32 fcoe_fmax;
4874
4875 u32 val;
4876
4877 /* Validate FCoE settings passed */
4878 switch (settings->fcoe_filt_num) {
4879 case I40E_HASH_FILTER_SIZE_1K:
4880 case I40E_HASH_FILTER_SIZE_2K:
4881 case I40E_HASH_FILTER_SIZE_4K:
4882 case I40E_HASH_FILTER_SIZE_8K:
4883 case I40E_HASH_FILTER_SIZE_16K:
4884 case I40E_HASH_FILTER_SIZE_32K:
4885 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4886 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
4887 break;
4888 default:
4889 return I40E_ERR_PARAM;
4890 }
4891
4892 switch (settings->fcoe_cntx_num) {
4893 case I40E_DMA_CNTX_SIZE_512:
4894 case I40E_DMA_CNTX_SIZE_1K:
4895 case I40E_DMA_CNTX_SIZE_2K:
4896 case I40E_DMA_CNTX_SIZE_4K:
4897 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4898 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
4899 break;
4900 default:
4901 return I40E_ERR_PARAM;
4902 }
4903
4904 /* Validate PE settings passed */
4905 switch (settings->pe_filt_num) {
4906 case I40E_HASH_FILTER_SIZE_1K:
4907 case I40E_HASH_FILTER_SIZE_2K:
4908 case I40E_HASH_FILTER_SIZE_4K:
4909 case I40E_HASH_FILTER_SIZE_8K:
4910 case I40E_HASH_FILTER_SIZE_16K:
4911 case I40E_HASH_FILTER_SIZE_32K:
4912 case I40E_HASH_FILTER_SIZE_64K:
4913 case I40E_HASH_FILTER_SIZE_128K:
4914 case I40E_HASH_FILTER_SIZE_256K:
4915 case I40E_HASH_FILTER_SIZE_512K:
4916 case I40E_HASH_FILTER_SIZE_1M:
4917 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4918 pe_filt_size <<= (u32)settings->pe_filt_num;
4919 break;
4920 default:
4921 return I40E_ERR_PARAM;
4922 }
4923
4924 switch (settings->pe_cntx_num) {
4925 case I40E_DMA_CNTX_SIZE_512:
4926 case I40E_DMA_CNTX_SIZE_1K:
4927 case I40E_DMA_CNTX_SIZE_2K:
4928 case I40E_DMA_CNTX_SIZE_4K:
4929 case I40E_DMA_CNTX_SIZE_8K:
4930 case I40E_DMA_CNTX_SIZE_16K:
4931 case I40E_DMA_CNTX_SIZE_32K:
4932 case I40E_DMA_CNTX_SIZE_64K:
4933 case I40E_DMA_CNTX_SIZE_128K:
4934 case I40E_DMA_CNTX_SIZE_256K:
4935 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4936 pe_cntx_size <<= (u32)settings->pe_cntx_num;
4937 break;
4938 default:
4939 return I40E_ERR_PARAM;
4940 }
4941
4942 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
4943 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
4944 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
4945 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
4946 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
4947 return I40E_ERR_INVALID_SIZE;
4948
4949 return I40E_SUCCESS;
4950 }
4951
4952 /**
4953 * i40e_set_filter_control
4954 * @hw: pointer to the hardware structure
4955 * @settings: Filter control settings
4956 *
4957 * Set the Queue Filters for PE/FCoE and enable filters required
4958 * for a single PF. It is expected that these settings are programmed
4959 * at the driver initialization time.
4960 **/
i40e_set_filter_control(struct i40e_hw * hw,struct i40e_filter_control_settings * settings)4961 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
4962 struct i40e_filter_control_settings *settings)
4963 {
4964 enum i40e_status_code ret = I40E_SUCCESS;
4965 u32 hash_lut_size = 0;
4966 u32 val;
4967
4968 if (!settings)
4969 return I40E_ERR_PARAM;
4970
4971 /* Validate the input settings */
4972 ret = i40e_validate_filter_settings(hw, settings);
4973 if (ret)
4974 return ret;
4975
4976 /* Read the PF Queue Filter control register */
4977 val = rd32(hw, I40E_PFQF_CTL_0);
4978
4979 /* Program required PE hash buckets for the PF */
4980 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
4981 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
4982 I40E_PFQF_CTL_0_PEHSIZE_MASK;
4983 /* Program required PE contexts for the PF */
4984 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
4985 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
4986 I40E_PFQF_CTL_0_PEDSIZE_MASK;
4987
4988 /* Program required FCoE hash buckets for the PF */
4989 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4990 val |= ((u32)settings->fcoe_filt_num <<
4991 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
4992 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4993 /* Program required FCoE DDP contexts for the PF */
4994 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4995 val |= ((u32)settings->fcoe_cntx_num <<
4996 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
4997 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4998
4999 /* Program Hash LUT size for the PF */
5000 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5001 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5002 hash_lut_size = 1;
5003 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5004 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5005
5006 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5007 if (settings->enable_fdir)
5008 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5009 if (settings->enable_ethtype)
5010 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5011 if (settings->enable_macvlan)
5012 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5013
5014 wr32(hw, I40E_PFQF_CTL_0, val);
5015
5016 return I40E_SUCCESS;
5017 }
5018
5019 /**
5020 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5021 * @hw: pointer to the hw struct
5022 * @mac_addr: MAC address to use in the filter
5023 * @ethtype: Ethertype to use in the filter
5024 * @flags: Flags that needs to be applied to the filter
5025 * @vsi_seid: seid of the control VSI
5026 * @queue: VSI queue number to send the packet to
5027 * @is_add: Add control packet filter if True else remove
5028 * @stats: Structure to hold information on control filter counts
5029 * @cmd_details: pointer to command details structure or NULL
5030 *
5031 * This command will Add or Remove control packet filter for a control VSI.
5032 * In return it will update the total number of perfect filter count in
5033 * the stats member.
5034 **/
i40e_aq_add_rem_control_packet_filter(struct i40e_hw * hw,u8 * mac_addr,u16 ethtype,u16 flags,u16 vsi_seid,u16 queue,bool is_add,struct i40e_control_filter_stats * stats,struct i40e_asq_cmd_details * cmd_details)5035 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5036 u8 *mac_addr, u16 ethtype, u16 flags,
5037 u16 vsi_seid, u16 queue, bool is_add,
5038 struct i40e_control_filter_stats *stats,
5039 struct i40e_asq_cmd_details *cmd_details)
5040 {
5041 struct i40e_aq_desc desc;
5042 struct i40e_aqc_add_remove_control_packet_filter *cmd =
5043 (struct i40e_aqc_add_remove_control_packet_filter *)
5044 &desc.params.raw;
5045 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5046 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5047 &desc.params.raw;
5048 enum i40e_status_code status;
5049
5050 if (vsi_seid == 0)
5051 return I40E_ERR_PARAM;
5052
5053 if (is_add) {
5054 i40e_fill_default_direct_cmd_desc(&desc,
5055 i40e_aqc_opc_add_control_packet_filter);
5056 cmd->queue = CPU_TO_LE16(queue);
5057 } else {
5058 i40e_fill_default_direct_cmd_desc(&desc,
5059 i40e_aqc_opc_remove_control_packet_filter);
5060 }
5061
5062 if (mac_addr)
5063 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
5064 I40E_NONDMA_TO_NONDMA);
5065
5066 cmd->etype = CPU_TO_LE16(ethtype);
5067 cmd->flags = CPU_TO_LE16(flags);
5068 cmd->seid = CPU_TO_LE16(vsi_seid);
5069
5070 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5071
5072 if (!status && stats) {
5073 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5074 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5075 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5076 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5077 }
5078
5079 return status;
5080 }
5081
5082 /**
5083 * i40e_aq_add_cloud_filters
5084 * @hw: pointer to the hardware structure
5085 * @seid: VSI seid to add cloud filters from
5086 * @filters: Buffer which contains the filters to be added
5087 * @filter_count: number of filters contained in the buffer
5088 *
5089 * Set the cloud filters for a given VSI. The contents of the
5090 * i40e_aqc_add_remove_cloud_filters_element_data are filled
5091 * in by the caller of the function.
5092 *
5093 **/
i40e_aq_add_cloud_filters(struct i40e_hw * hw,u16 seid,struct i40e_aqc_add_remove_cloud_filters_element_data * filters,u8 filter_count)5094 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5095 u16 seid,
5096 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5097 u8 filter_count)
5098 {
5099 struct i40e_aq_desc desc;
5100 struct i40e_aqc_add_remove_cloud_filters *cmd =
5101 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5102 u16 buff_len;
5103 enum i40e_status_code status;
5104
5105 i40e_fill_default_direct_cmd_desc(&desc,
5106 i40e_aqc_opc_add_cloud_filters);
5107
5108 buff_len = filter_count * sizeof(*filters);
5109 desc.datalen = CPU_TO_LE16(buff_len);
5110 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5111 cmd->num_filters = filter_count;
5112 cmd->seid = CPU_TO_LE16(seid);
5113
5114 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5115
5116 return status;
5117 }
5118
5119 /**
5120 * i40e_aq_remove_cloud_filters
5121 * @hw: pointer to the hardware structure
5122 * @seid: VSI seid to remove cloud filters from
5123 * @filters: Buffer which contains the filters to be removed
5124 * @filter_count: number of filters contained in the buffer
5125 *
5126 * Remove the cloud filters for a given VSI. The contents of the
5127 * i40e_aqc_add_remove_cloud_filters_element_data are filled
5128 * in by the caller of the function.
5129 *
5130 **/
i40e_aq_remove_cloud_filters(struct i40e_hw * hw,u16 seid,struct i40e_aqc_add_remove_cloud_filters_element_data * filters,u8 filter_count)5131 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5132 u16 seid,
5133 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5134 u8 filter_count)
5135 {
5136 struct i40e_aq_desc desc;
5137 struct i40e_aqc_add_remove_cloud_filters *cmd =
5138 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5139 enum i40e_status_code status;
5140 u16 buff_len;
5141
5142 i40e_fill_default_direct_cmd_desc(&desc,
5143 i40e_aqc_opc_remove_cloud_filters);
5144
5145 buff_len = filter_count * sizeof(*filters);
5146 desc.datalen = CPU_TO_LE16(buff_len);
5147 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5148 cmd->num_filters = filter_count;
5149 cmd->seid = CPU_TO_LE16(seid);
5150
5151 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5152
5153 return status;
5154 }
5155
5156 /**
5157 * i40e_aq_alternate_write
5158 * @hw: pointer to the hardware structure
5159 * @reg_addr0: address of first dword to be read
5160 * @reg_val0: value to be written under 'reg_addr0'
5161 * @reg_addr1: address of second dword to be read
5162 * @reg_val1: value to be written under 'reg_addr1'
5163 *
5164 * Write one or two dwords to alternate structure. Fields are indicated
5165 * by 'reg_addr0' and 'reg_addr1' register numbers.
5166 *
5167 **/
i40e_aq_alternate_write(struct i40e_hw * hw,u32 reg_addr0,u32 reg_val0,u32 reg_addr1,u32 reg_val1)5168 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5169 u32 reg_addr0, u32 reg_val0,
5170 u32 reg_addr1, u32 reg_val1)
5171 {
5172 struct i40e_aq_desc desc;
5173 struct i40e_aqc_alternate_write *cmd_resp =
5174 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5175 enum i40e_status_code status;
5176
5177 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5178 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5179 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5180 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5181 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5182
5183 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5184
5185 return status;
5186 }
5187
5188 /**
5189 * i40e_aq_alternate_write_indirect
5190 * @hw: pointer to the hardware structure
5191 * @addr: address of a first register to be modified
5192 * @dw_count: number of alternate structure fields to write
5193 * @buffer: pointer to the command buffer
5194 *
5195 * Write 'dw_count' dwords from 'buffer' to alternate structure
5196 * starting at 'addr'.
5197 *
5198 **/
i40e_aq_alternate_write_indirect(struct i40e_hw * hw,u32 addr,u32 dw_count,void * buffer)5199 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5200 u32 addr, u32 dw_count, void *buffer)
5201 {
5202 struct i40e_aq_desc desc;
5203 struct i40e_aqc_alternate_ind_write *cmd_resp =
5204 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5205 enum i40e_status_code status;
5206
5207 if (buffer == NULL)
5208 return I40E_ERR_PARAM;
5209
5210 /* Indirect command */
5211 i40e_fill_default_direct_cmd_desc(&desc,
5212 i40e_aqc_opc_alternate_write_indirect);
5213
5214 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5215 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5216 if (dw_count > (I40E_AQ_LARGE_BUF/4))
5217 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5218
5219 cmd_resp->address = CPU_TO_LE32(addr);
5220 cmd_resp->length = CPU_TO_LE32(dw_count);
5221 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_WORD((u64)buffer));
5222 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));
5223
5224 status = i40e_asq_send_command(hw, &desc, buffer,
5225 I40E_LO_DWORD(4*dw_count), NULL);
5226
5227 return status;
5228 }
5229
5230 /**
5231 * i40e_aq_alternate_read
5232 * @hw: pointer to the hardware structure
5233 * @reg_addr0: address of first dword to be read
5234 * @reg_val0: pointer for data read from 'reg_addr0'
5235 * @reg_addr1: address of second dword to be read
5236 * @reg_val1: pointer for data read from 'reg_addr1'
5237 *
5238 * Read one or two dwords from alternate structure. Fields are indicated
5239 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5240 * is not passed then only register at 'reg_addr0' is read.
5241 *
5242 **/
i40e_aq_alternate_read(struct i40e_hw * hw,u32 reg_addr0,u32 * reg_val0,u32 reg_addr1,u32 * reg_val1)5243 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5244 u32 reg_addr0, u32 *reg_val0,
5245 u32 reg_addr1, u32 *reg_val1)
5246 {
5247 struct i40e_aq_desc desc;
5248 struct i40e_aqc_alternate_write *cmd_resp =
5249 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5250 enum i40e_status_code status;
5251
5252 if (reg_val0 == NULL)
5253 return I40E_ERR_PARAM;
5254
5255 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5256 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5257 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5258
5259 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5260
5261 if (status == I40E_SUCCESS) {
5262 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5263
5264 if (reg_val1 != NULL)
5265 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5266 }
5267
5268 return status;
5269 }
5270
5271 /**
5272 * i40e_aq_alternate_read_indirect
5273 * @hw: pointer to the hardware structure
5274 * @addr: address of the alternate structure field
5275 * @dw_count: number of alternate structure fields to read
5276 * @buffer: pointer to the command buffer
5277 *
5278 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5279 * place them in 'buffer'. The buffer should be allocated by caller.
5280 *
5281 **/
i40e_aq_alternate_read_indirect(struct i40e_hw * hw,u32 addr,u32 dw_count,void * buffer)5282 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5283 u32 addr, u32 dw_count, void *buffer)
5284 {
5285 struct i40e_aq_desc desc;
5286 struct i40e_aqc_alternate_ind_write *cmd_resp =
5287 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5288 enum i40e_status_code status;
5289
5290 if (buffer == NULL)
5291 return I40E_ERR_PARAM;
5292
5293 /* Indirect command */
5294 i40e_fill_default_direct_cmd_desc(&desc,
5295 i40e_aqc_opc_alternate_read_indirect);
5296
5297 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5298 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5299 if (dw_count > (I40E_AQ_LARGE_BUF/4))
5300 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5301
5302 cmd_resp->address = CPU_TO_LE32(addr);
5303 cmd_resp->length = CPU_TO_LE32(dw_count);
5304 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_DWORD((u64)buffer));
5305 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));
5306
5307 status = i40e_asq_send_command(hw, &desc, buffer,
5308 I40E_LO_DWORD(4*dw_count), NULL);
5309
5310 return status;
5311 }
5312
5313 /**
5314 * i40e_aq_alternate_clear
5315 * @hw: pointer to the HW structure.
5316 *
5317 * Clear the alternate structures of the port from which the function
5318 * is called.
5319 *
5320 **/
i40e_aq_alternate_clear(struct i40e_hw * hw)5321 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
5322 {
5323 struct i40e_aq_desc desc;
5324 enum i40e_status_code status;
5325
5326 i40e_fill_default_direct_cmd_desc(&desc,
5327 i40e_aqc_opc_alternate_clear_port);
5328
5329 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5330
5331 return status;
5332 }
5333
5334 /**
5335 * i40e_aq_alternate_write_done
5336 * @hw: pointer to the HW structure.
5337 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
5338 * @reset_needed: indicates the SW should trigger GLOBAL reset
5339 *
5340 * Indicates to the FW that alternate structures have been changed.
5341 *
5342 **/
i40e_aq_alternate_write_done(struct i40e_hw * hw,u8 bios_mode,bool * reset_needed)5343 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
5344 u8 bios_mode, bool *reset_needed)
5345 {
5346 struct i40e_aq_desc desc;
5347 struct i40e_aqc_alternate_write_done *cmd =
5348 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5349 enum i40e_status_code status;
5350
5351 if (reset_needed == NULL)
5352 return I40E_ERR_PARAM;
5353
5354 i40e_fill_default_direct_cmd_desc(&desc,
5355 i40e_aqc_opc_alternate_write_done);
5356
5357 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
5358
5359 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5360 if (!status && reset_needed)
5361 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
5362 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
5363
5364 return status;
5365 }
5366
5367 /**
5368 * i40e_aq_set_oem_mode
5369 * @hw: pointer to the HW structure.
5370 * @oem_mode: the OEM mode to be used
5371 *
5372 * Sets the device to a specific operating mode. Currently the only supported
5373 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
5374 *
5375 **/
i40e_aq_set_oem_mode(struct i40e_hw * hw,u8 oem_mode)5376 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
5377 u8 oem_mode)
5378 {
5379 struct i40e_aq_desc desc;
5380 struct i40e_aqc_alternate_write_done *cmd =
5381 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5382 enum i40e_status_code status;
5383
5384 i40e_fill_default_direct_cmd_desc(&desc,
5385 i40e_aqc_opc_alternate_set_mode);
5386
5387 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
5388
5389 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5390
5391 return status;
5392 }
5393
5394 /**
5395 * i40e_aq_resume_port_tx
5396 * @hw: pointer to the hardware structure
5397 * @cmd_details: pointer to command details structure or NULL
5398 *
5399 * Resume port's Tx traffic
5400 **/
i40e_aq_resume_port_tx(struct i40e_hw * hw,struct i40e_asq_cmd_details * cmd_details)5401 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
5402 struct i40e_asq_cmd_details *cmd_details)
5403 {
5404 struct i40e_aq_desc desc;
5405 enum i40e_status_code status;
5406
5407 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
5408
5409 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5410
5411 return status;
5412 }
5413
5414 /**
5415 * i40e_set_pci_config_data - store PCI bus info
5416 * @hw: pointer to hardware structure
5417 * @link_status: the link status word from PCI config space
5418 *
5419 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
5420 **/
i40e_set_pci_config_data(struct i40e_hw * hw,u16 link_status)5421 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
5422 {
5423 hw->bus.type = i40e_bus_type_pci_express;
5424
5425 switch (link_status & I40E_PCI_LINK_WIDTH) {
5426 case I40E_PCI_LINK_WIDTH_1:
5427 hw->bus.width = i40e_bus_width_pcie_x1;
5428 break;
5429 case I40E_PCI_LINK_WIDTH_2:
5430 hw->bus.width = i40e_bus_width_pcie_x2;
5431 break;
5432 case I40E_PCI_LINK_WIDTH_4:
5433 hw->bus.width = i40e_bus_width_pcie_x4;
5434 break;
5435 case I40E_PCI_LINK_WIDTH_8:
5436 hw->bus.width = i40e_bus_width_pcie_x8;
5437 break;
5438 default:
5439 hw->bus.width = i40e_bus_width_unknown;
5440 break;
5441 }
5442
5443 switch (link_status & I40E_PCI_LINK_SPEED) {
5444 case I40E_PCI_LINK_SPEED_2500:
5445 hw->bus.speed = i40e_bus_speed_2500;
5446 break;
5447 case I40E_PCI_LINK_SPEED_5000:
5448 hw->bus.speed = i40e_bus_speed_5000;
5449 break;
5450 case I40E_PCI_LINK_SPEED_8000:
5451 hw->bus.speed = i40e_bus_speed_8000;
5452 break;
5453 default:
5454 hw->bus.speed = i40e_bus_speed_unknown;
5455 break;
5456 }
5457 }
5458
5459 /**
5460 * i40e_aq_debug_dump
5461 * @hw: pointer to the hardware structure
5462 * @cluster_id: specific cluster to dump
5463 * @table_id: table id within cluster
5464 * @start_index: index of line in the block to read
5465 * @buff_size: dump buffer size
5466 * @buff: dump buffer
5467 * @ret_buff_size: actual buffer size returned
5468 * @ret_next_table: next block to read
5469 * @ret_next_index: next index to read
5470 *
5471 * Dump internal FW/HW data for debug purposes.
5472 *
5473 **/
i40e_aq_debug_dump(struct i40e_hw * hw,u8 cluster_id,u8 table_id,u32 start_index,u16 buff_size,void * buff,u16 * ret_buff_size,u8 * ret_next_table,u32 * ret_next_index,struct i40e_asq_cmd_details * cmd_details)5474 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
5475 u8 table_id, u32 start_index, u16 buff_size,
5476 void *buff, u16 *ret_buff_size,
5477 u8 *ret_next_table, u32 *ret_next_index,
5478 struct i40e_asq_cmd_details *cmd_details)
5479 {
5480 struct i40e_aq_desc desc;
5481 struct i40e_aqc_debug_dump_internals *cmd =
5482 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5483 struct i40e_aqc_debug_dump_internals *resp =
5484 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5485 enum i40e_status_code status;
5486
5487 if (buff_size == 0 || !buff)
5488 return I40E_ERR_PARAM;
5489
5490 i40e_fill_default_direct_cmd_desc(&desc,
5491 i40e_aqc_opc_debug_dump_internals);
5492 /* Indirect Command */
5493 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5494 if (buff_size > I40E_AQ_LARGE_BUF)
5495 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5496
5497 cmd->cluster_id = cluster_id;
5498 cmd->table_id = table_id;
5499 cmd->idx = CPU_TO_LE32(start_index);
5500
5501 desc.datalen = CPU_TO_LE16(buff_size);
5502
5503 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5504 if (!status) {
5505 if (ret_buff_size != NULL)
5506 *ret_buff_size = LE16_TO_CPU(desc.datalen);
5507 if (ret_next_table != NULL)
5508 *ret_next_table = resp->table_id;
5509 if (ret_next_index != NULL)
5510 *ret_next_index = LE32_TO_CPU(resp->idx);
5511 }
5512
5513 return status;
5514 }
5515
5516 /**
5517 * i40e_read_bw_from_alt_ram
5518 * @hw: pointer to the hardware structure
5519 * @max_bw: pointer for max_bw read
5520 * @min_bw: pointer for min_bw read
5521 * @min_valid: pointer for bool that is TRUE if min_bw is a valid value
5522 * @max_valid: pointer for bool that is TRUE if max_bw is a valid value
5523 *
5524 * Read bw from the alternate ram for the given pf
5525 **/
i40e_read_bw_from_alt_ram(struct i40e_hw * hw,u32 * max_bw,u32 * min_bw,bool * min_valid,bool * max_valid)5526 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
5527 u32 *max_bw, u32 *min_bw,
5528 bool *min_valid, bool *max_valid)
5529 {
5530 enum i40e_status_code status;
5531 u32 max_bw_addr, min_bw_addr;
5532
5533 /* Calculate the address of the min/max bw registers */
5534 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5535 I40E_ALT_STRUCT_MAX_BW_OFFSET +
5536 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5537 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5538 I40E_ALT_STRUCT_MIN_BW_OFFSET +
5539 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5540
5541 /* Read the bandwidths from alt ram */
5542 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
5543 min_bw_addr, min_bw);
5544
5545 if (*min_bw & I40E_ALT_BW_VALID_MASK)
5546 *min_valid = TRUE;
5547 else
5548 *min_valid = FALSE;
5549
5550 if (*max_bw & I40E_ALT_BW_VALID_MASK)
5551 *max_valid = TRUE;
5552 else
5553 *max_valid = FALSE;
5554
5555 return status;
5556 }
5557
5558 /**
5559 * i40e_aq_configure_partition_bw
5560 * @hw: pointer to the hardware structure
5561 * @bw_data: Buffer holding valid pfs and bw limits
5562 * @cmd_details: pointer to command details
5563 *
5564 * Configure partitions guaranteed/max bw
5565 **/
i40e_aq_configure_partition_bw(struct i40e_hw * hw,struct i40e_aqc_configure_partition_bw_data * bw_data,struct i40e_asq_cmd_details * cmd_details)5566 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
5567 struct i40e_aqc_configure_partition_bw_data *bw_data,
5568 struct i40e_asq_cmd_details *cmd_details)
5569 {
5570 enum i40e_status_code status;
5571 struct i40e_aq_desc desc;
5572 u16 bwd_size = sizeof(*bw_data);
5573
5574 i40e_fill_default_direct_cmd_desc(&desc,
5575 i40e_aqc_opc_configure_partition_bw);
5576
5577 /* Indirect command */
5578 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5579 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5580
5581 if (bwd_size > I40E_AQ_LARGE_BUF)
5582 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5583
5584 desc.datalen = CPU_TO_LE16(bwd_size);
5585
5586 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
5587
5588 return status;
5589 }
5590
5591 /**
5592 * i40e_aq_send_msg_to_pf
5593 * @hw: pointer to the hardware structure
5594 * @v_opcode: opcodes for VF-PF communication
5595 * @v_retval: return error code
5596 * @msg: pointer to the msg buffer
5597 * @msglen: msg length
5598 * @cmd_details: pointer to command details
5599 *
5600 * Send message to PF driver using admin queue. By default, this message
5601 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
5602 * completion before returning.
5603 **/
i40e_aq_send_msg_to_pf(struct i40e_hw * hw,enum i40e_virtchnl_ops v_opcode,enum i40e_status_code v_retval,u8 * msg,u16 msglen,struct i40e_asq_cmd_details * cmd_details)5604 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
5605 enum i40e_virtchnl_ops v_opcode,
5606 enum i40e_status_code v_retval,
5607 u8 *msg, u16 msglen,
5608 struct i40e_asq_cmd_details *cmd_details)
5609 {
5610 struct i40e_aq_desc desc;
5611 struct i40e_asq_cmd_details details;
5612 enum i40e_status_code status;
5613
5614 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
5615 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
5616 desc.cookie_high = CPU_TO_LE32(v_opcode);
5617 desc.cookie_low = CPU_TO_LE32(v_retval);
5618 if (msglen) {
5619 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
5620 | I40E_AQ_FLAG_RD));
5621 if (msglen > I40E_AQ_LARGE_BUF)
5622 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5623 desc.datalen = CPU_TO_LE16(msglen);
5624 }
5625 if (!cmd_details) {
5626 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
5627 details.async = TRUE;
5628 cmd_details = &details;
5629 }
5630 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
5631 msglen, cmd_details);
5632 return status;
5633 }
5634
5635 /**
5636 * i40e_vf_parse_hw_config
5637 * @hw: pointer to the hardware structure
5638 * @msg: pointer to the virtual channel VF resource structure
5639 *
5640 * Given a VF resource message from the PF, populate the hw struct
5641 * with appropriate information.
5642 **/
i40e_vf_parse_hw_config(struct i40e_hw * hw,struct i40e_virtchnl_vf_resource * msg)5643 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
5644 struct i40e_virtchnl_vf_resource *msg)
5645 {
5646 struct i40e_virtchnl_vsi_resource *vsi_res;
5647 int i;
5648
5649 vsi_res = &msg->vsi_res[0];
5650
5651 hw->dev_caps.num_vsis = msg->num_vsis;
5652 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
5653 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
5654 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
5655 hw->dev_caps.dcb = msg->vf_offload_flags &
5656 I40E_VIRTCHNL_VF_OFFLOAD_L2;
5657 hw->dev_caps.fcoe = (msg->vf_offload_flags &
5658 I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
5659 hw->dev_caps.iwarp = (msg->vf_offload_flags &
5660 I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
5661 for (i = 0; i < msg->num_vsis; i++) {
5662 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
5663 i40e_memcpy(hw->mac.perm_addr,
5664 vsi_res->default_mac_addr,
5665 I40E_ETH_LENGTH_OF_ADDRESS,
5666 I40E_NONDMA_TO_NONDMA);
5667 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
5668 I40E_ETH_LENGTH_OF_ADDRESS,
5669 I40E_NONDMA_TO_NONDMA);
5670 }
5671 vsi_res++;
5672 }
5673 }
5674
5675 /**
5676 * i40e_vf_reset
5677 * @hw: pointer to the hardware structure
5678 *
5679 * Send a VF_RESET message to the PF. Does not wait for response from PF
5680 * as none will be forthcoming. Immediately after calling this function,
5681 * the admin queue should be shut down and (optionally) reinitialized.
5682 **/
i40e_vf_reset(struct i40e_hw * hw)5683 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
5684 {
5685 return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
5686 I40E_SUCCESS, NULL, 0, NULL);
5687 }
5688