1 /*-
2 * Copyright (c) 2003 Hidetoshi Shimokawa
3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the acknowledgement as bellow:
16 *
17 * This product includes software developed by K. Kobayashi and H. Shimokawa
18 *
19 * 4. The name of the author may not be used to endorse or promote products
20 * derived from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
33 *
34 * $FreeBSD: stable/10/sys/dev/firewire/fwohci.c 310081 2016-12-14 17:17:07Z avg $
35 *
36 */
37
38 #define ATRQ_CH 0
39 #define ATRS_CH 1
40 #define ARRQ_CH 2
41 #define ARRS_CH 3
42 #define ITX_CH 4
43 #define IRX_CH 0x24
44
45 #include <sys/param.h>
46 #include <sys/systm.h>
47 #include <sys/mbuf.h>
48 #include <sys/malloc.h>
49 #include <sys/sockio.h>
50 #include <sys/sysctl.h>
51 #include <sys/bus.h>
52 #include <sys/kernel.h>
53 #include <sys/conf.h>
54 #include <sys/endian.h>
55 #include <sys/kdb.h>
56
57 #include <machine/bus.h>
58 #include <machine/md_var.h>
59
60 #if defined(__DragonFly__) || __FreeBSD_version < 500000
61 #include <machine/clock.h> /* for DELAY() */
62 #endif
63
64 #ifdef __DragonFly__
65 #include "firewire.h"
66 #include "firewirereg.h"
67 #include "fwdma.h"
68 #include "fwohcireg.h"
69 #include "fwohcivar.h"
70 #include "firewire_phy.h"
71 #else
72 #include <dev/firewire/firewire.h>
73 #include <dev/firewire/firewirereg.h>
74 #include <dev/firewire/fwdma.h>
75 #include <dev/firewire/fwohcireg.h>
76 #include <dev/firewire/fwohcivar.h>
77 #include <dev/firewire/firewire_phy.h>
78 #endif
79
80 #undef OHCI_DEBUG
81
82 static int nocyclemaster = 0;
83 int firewire_phydma_enable = 1;
84 SYSCTL_DECL(_hw_firewire);
85 SYSCTL_INT(_hw_firewire, OID_AUTO, nocyclemaster, CTLFLAG_RW, &nocyclemaster, 0,
86 "Do not send cycle start packets");
87 SYSCTL_INT(_hw_firewire, OID_AUTO, phydma_enable, CTLFLAG_RW,
88 &firewire_phydma_enable, 1, "Allow physical request DMA from firewire");
89 TUNABLE_INT("hw.firewire.phydma_enable", &firewire_phydma_enable);
90
91 static char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL",
92 "STOR","LOAD","NOP ","STOP",};
93
94 static char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3",
95 "UNDEF","REG","SYS","DEV"};
96 static char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"};
97 char fwohcicode[32][0x20]={
98 "No stat","Undef","long","miss Ack err",
99 "FIFO underrun","FIFO overrun","desc err", "data read err",
100 "data write err","bus reset","timeout","tcode err",
101 "Undef","Undef","unknown event","flushed",
102 "Undef","ack complete","ack pend","Undef",
103 "ack busy_X","ack busy_A","ack busy_B","Undef",
104 "Undef","Undef","Undef","ack tardy",
105 "Undef","ack data_err","ack type_err",""};
106
107 #define MAX_SPEED 3
108 extern char *linkspeed[];
109 uint32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31};
110
111 static struct tcode_info tinfo[] = {
112 /* hdr_len block flag valid_response */
113 /* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL, FWTCODE_WRES},
114 /* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY, FWTCODE_WRES},
115 /* 2 WRES */ {12, FWTI_RES, 0xff},
116 /* 3 XXX */ { 0, 0, 0xff},
117 /* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL, FWTCODE_RRESQ},
118 /* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL, FWTCODE_RRESB},
119 /* 6 RRESQ */ {16, FWTI_RES, 0xff},
120 /* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY, 0xff},
121 /* 8 CYCS */ { 0, 0, 0xff},
122 /* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY, FWTCODE_LRES},
123 /* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR, 0xff},
124 /* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY, 0xff},
125 /* c XXX */ { 0, 0, 0xff},
126 /* d XXX */ { 0, 0, 0xff},
127 /* e PHY */ {12, FWTI_REQ, 0xff},
128 /* f XXX */ { 0, 0, 0xff}
129 };
130
131 #define OHCI_WRITE_SIGMASK 0xffff0000
132 #define OHCI_READ_SIGMASK 0xffff0000
133
134 #define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x))
135 #define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r))
136
137 static void fwohci_ibr (struct firewire_comm *);
138 static void fwohci_db_init (struct fwohci_softc *, struct fwohci_dbch *);
139 static void fwohci_db_free (struct fwohci_dbch *);
140 static void fwohci_arcv (struct fwohci_softc *, struct fwohci_dbch *, int);
141 static void fwohci_txd (struct fwohci_softc *, struct fwohci_dbch *);
142 static void fwohci_start_atq (struct firewire_comm *);
143 static void fwohci_start_ats (struct firewire_comm *);
144 static void fwohci_start (struct fwohci_softc *, struct fwohci_dbch *);
145 static uint32_t fwphy_wrdata ( struct fwohci_softc *, uint32_t, uint32_t);
146 static uint32_t fwphy_rddata ( struct fwohci_softc *, uint32_t);
147 static int fwohci_rx_enable (struct fwohci_softc *, struct fwohci_dbch *);
148 static int fwohci_tx_enable (struct fwohci_softc *, struct fwohci_dbch *);
149 static int fwohci_irx_enable (struct firewire_comm *, int);
150 static int fwohci_irx_disable (struct firewire_comm *, int);
151 #if BYTE_ORDER == BIG_ENDIAN
152 static void fwohci_irx_post (struct firewire_comm *, uint32_t *);
153 #endif
154 static int fwohci_itxbuf_enable (struct firewire_comm *, int);
155 static int fwohci_itx_disable (struct firewire_comm *, int);
156 static void fwohci_timeout (void *);
157 static void fwohci_set_intr (struct firewire_comm *, int);
158
159 static int fwohci_add_rx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *);
160 static int fwohci_add_tx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int);
161 static void dump_db (struct fwohci_softc *, uint32_t);
162 static void print_db (struct fwohcidb_tr *, struct fwohcidb *, uint32_t , uint32_t);
163 static void dump_dma (struct fwohci_softc *, uint32_t);
164 static uint32_t fwohci_cyctimer (struct firewire_comm *);
165 static void fwohci_rbuf_update (struct fwohci_softc *, int);
166 static void fwohci_tbuf_update (struct fwohci_softc *, int);
167 void fwohci_txbufdb (struct fwohci_softc *, int , struct fw_bulkxfer *);
168 static void fwohci_task_busreset(void *, int);
169 static void fwohci_task_sid(void *, int);
170 static void fwohci_task_dma(void *, int);
171
172 /*
173 * memory allocated for DMA programs
174 */
175 #define DMA_PROG_ALLOC (8 * PAGE_SIZE)
176
177 #define NDB FWMAXQUEUE
178
179 #define OHCI_VERSION 0x00
180 #define OHCI_ATRETRY 0x08
181 #define OHCI_CROMHDR 0x18
182 #define OHCI_BUS_OPT 0x20
183 #define OHCI_BUSIRMC (1U << 31)
184 #define OHCI_BUSCMC (1 << 30)
185 #define OHCI_BUSISC (1 << 29)
186 #define OHCI_BUSBMC (1 << 28)
187 #define OHCI_BUSPMC (1 << 27)
188 #define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\
189 OHCI_BUSBMC | OHCI_BUSPMC
190
191 #define OHCI_EUID_HI 0x24
192 #define OHCI_EUID_LO 0x28
193
194 #define OHCI_CROMPTR 0x34
195 #define OHCI_HCCCTL 0x50
196 #define OHCI_HCCCTLCLR 0x54
197 #define OHCI_AREQHI 0x100
198 #define OHCI_AREQHICLR 0x104
199 #define OHCI_AREQLO 0x108
200 #define OHCI_AREQLOCLR 0x10c
201 #define OHCI_PREQHI 0x110
202 #define OHCI_PREQHICLR 0x114
203 #define OHCI_PREQLO 0x118
204 #define OHCI_PREQLOCLR 0x11c
205 #define OHCI_PREQUPPER 0x120
206 #define OHCI_PREQUPPER_MAX 0xffff0000
207
208 #define OHCI_SID_BUF 0x64
209 #define OHCI_SID_CNT 0x68
210 #define OHCI_SID_ERR (1U << 31)
211 #define OHCI_SID_CNT_MASK 0xffc
212
213 #define OHCI_IT_STAT 0x90
214 #define OHCI_IT_STATCLR 0x94
215 #define OHCI_IT_MASK 0x98
216 #define OHCI_IT_MASKCLR 0x9c
217
218 #define OHCI_IR_STAT 0xa0
219 #define OHCI_IR_STATCLR 0xa4
220 #define OHCI_IR_MASK 0xa8
221 #define OHCI_IR_MASKCLR 0xac
222
223 #define OHCI_LNKCTL 0xe0
224 #define OHCI_LNKCTLCLR 0xe4
225
226 #define OHCI_PHYACCESS 0xec
227 #define OHCI_CYCLETIMER 0xf0
228
229 #define OHCI_DMACTL(off) (off)
230 #define OHCI_DMACTLCLR(off) (off + 4)
231 #define OHCI_DMACMD(off) (off + 0xc)
232 #define OHCI_DMAMATCH(off) (off + 0x10)
233
234 #define OHCI_ATQOFF 0x180
235 #define OHCI_ATQCTL OHCI_ATQOFF
236 #define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4)
237 #define OHCI_ATQCMD (OHCI_ATQOFF + 0xc)
238 #define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10)
239
240 #define OHCI_ATSOFF 0x1a0
241 #define OHCI_ATSCTL OHCI_ATSOFF
242 #define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4)
243 #define OHCI_ATSCMD (OHCI_ATSOFF + 0xc)
244 #define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10)
245
246 #define OHCI_ARQOFF 0x1c0
247 #define OHCI_ARQCTL OHCI_ARQOFF
248 #define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4)
249 #define OHCI_ARQCMD (OHCI_ARQOFF + 0xc)
250 #define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10)
251
252 #define OHCI_ARSOFF 0x1e0
253 #define OHCI_ARSCTL OHCI_ARSOFF
254 #define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4)
255 #define OHCI_ARSCMD (OHCI_ARSOFF + 0xc)
256 #define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10)
257
258 #define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH))
259 #define OHCI_ITCTL(CH) (OHCI_ITOFF(CH))
260 #define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4)
261 #define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc)
262
263 #define OHCI_IROFF(CH) (0x400 + 0x20 * (CH))
264 #define OHCI_IRCTL(CH) (OHCI_IROFF(CH))
265 #define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4)
266 #define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc)
267 #define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10)
268
269 d_ioctl_t fwohci_ioctl;
270
271 /*
272 * Communication with PHY device
273 */
274 /* XXX need lock for phy access */
275 static uint32_t
fwphy_wrdata(struct fwohci_softc * sc,uint32_t addr,uint32_t data)276 fwphy_wrdata( struct fwohci_softc *sc, uint32_t addr, uint32_t data)
277 {
278 uint32_t fun;
279
280 addr &= 0xf;
281 data &= 0xff;
282
283 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA));
284 OWRITE(sc, OHCI_PHYACCESS, fun);
285 DELAY(100);
286
287 return(fwphy_rddata( sc, addr));
288 }
289
290 static uint32_t
fwohci_set_bus_manager(struct firewire_comm * fc,u_int node)291 fwohci_set_bus_manager(struct firewire_comm *fc, u_int node)
292 {
293 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
294 int i;
295 uint32_t bm;
296
297 #define OHCI_CSR_DATA 0x0c
298 #define OHCI_CSR_COMP 0x10
299 #define OHCI_CSR_CONT 0x14
300 #define OHCI_BUS_MANAGER_ID 0
301
302 OWRITE(sc, OHCI_CSR_DATA, node);
303 OWRITE(sc, OHCI_CSR_COMP, 0x3f);
304 OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID);
305 for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++)
306 DELAY(10);
307 bm = OREAD(sc, OHCI_CSR_DATA);
308 if((bm & 0x3f) == 0x3f)
309 bm = node;
310 if (firewire_debug)
311 device_printf(sc->fc.dev, "%s: %d->%d (loop=%d)\n",
312 __func__, bm, node, i);
313
314 return(bm);
315 }
316
317 static uint32_t
fwphy_rddata(struct fwohci_softc * sc,u_int addr)318 fwphy_rddata(struct fwohci_softc *sc, u_int addr)
319 {
320 uint32_t fun, stat;
321 u_int i, retry = 0;
322
323 addr &= 0xf;
324 #define MAX_RETRY 100
325 again:
326 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL);
327 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR);
328 OWRITE(sc, OHCI_PHYACCESS, fun);
329 for ( i = 0 ; i < MAX_RETRY ; i ++ ){
330 fun = OREAD(sc, OHCI_PHYACCESS);
331 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0)
332 break;
333 DELAY(100);
334 }
335 if(i >= MAX_RETRY) {
336 if (firewire_debug)
337 device_printf(sc->fc.dev, "%s: failed(1).\n", __func__);
338 if (++retry < MAX_RETRY) {
339 DELAY(100);
340 goto again;
341 }
342 }
343 /* Make sure that SCLK is started */
344 stat = OREAD(sc, FWOHCI_INTSTAT);
345 if ((stat & OHCI_INT_REG_FAIL) != 0 ||
346 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) {
347 if (firewire_debug)
348 device_printf(sc->fc.dev, "%s: failed(2).\n", __func__);
349 if (++retry < MAX_RETRY) {
350 DELAY(100);
351 goto again;
352 }
353 }
354 if (firewire_debug > 1 || retry >= MAX_RETRY)
355 device_printf(sc->fc.dev,
356 "%s:: 0x%x loop=%d, retry=%d\n",
357 __func__, addr, i, retry);
358 #undef MAX_RETRY
359 return((fun >> PHYDEV_RDDATA )& 0xff);
360 }
361 /* Device specific ioctl. */
362 int
fwohci_ioctl(struct cdev * dev,u_long cmd,caddr_t data,int flag,fw_proc * td)363 fwohci_ioctl (struct cdev *dev, u_long cmd, caddr_t data, int flag, fw_proc *td)
364 {
365 struct firewire_softc *sc;
366 struct fwohci_softc *fc;
367 int unit = DEV2UNIT(dev);
368 int err = 0;
369 struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data;
370 uint32_t *dmach = (uint32_t *) data;
371
372 sc = devclass_get_softc(firewire_devclass, unit);
373 if(sc == NULL){
374 return(EINVAL);
375 }
376 fc = (struct fwohci_softc *)sc->fc;
377
378 if (!data)
379 return(EINVAL);
380
381 switch (cmd) {
382 case FWOHCI_WRREG:
383 #define OHCI_MAX_REG 0x800
384 if(reg->addr <= OHCI_MAX_REG){
385 OWRITE(fc, reg->addr, reg->data);
386 reg->data = OREAD(fc, reg->addr);
387 }else{
388 err = EINVAL;
389 }
390 break;
391 case FWOHCI_RDREG:
392 if(reg->addr <= OHCI_MAX_REG){
393 reg->data = OREAD(fc, reg->addr);
394 }else{
395 err = EINVAL;
396 }
397 break;
398 /* Read DMA descriptors for debug */
399 case DUMPDMA:
400 if(*dmach <= OHCI_MAX_DMA_CH ){
401 dump_dma(fc, *dmach);
402 dump_db(fc, *dmach);
403 }else{
404 err = EINVAL;
405 }
406 break;
407 /* Read/Write Phy registers */
408 #define OHCI_MAX_PHY_REG 0xf
409 case FWOHCI_RDPHYREG:
410 if (reg->addr <= OHCI_MAX_PHY_REG)
411 reg->data = fwphy_rddata(fc, reg->addr);
412 else
413 err = EINVAL;
414 break;
415 case FWOHCI_WRPHYREG:
416 if (reg->addr <= OHCI_MAX_PHY_REG)
417 reg->data = fwphy_wrdata(fc, reg->addr, reg->data);
418 else
419 err = EINVAL;
420 break;
421 default:
422 err = EINVAL;
423 break;
424 }
425 return err;
426 }
427
428 static int
fwohci_probe_phy(struct fwohci_softc * sc,device_t dev)429 fwohci_probe_phy(struct fwohci_softc *sc, device_t dev)
430 {
431 uint32_t reg, reg2;
432 int e1394a = 1;
433 /*
434 * probe PHY parameters
435 * 0. to prove PHY version, whether compliance of 1394a.
436 * 1. to probe maximum speed supported by the PHY and
437 * number of port supported by core-logic.
438 * It is not actually available port on your PC .
439 */
440 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS);
441 DELAY(500);
442
443 reg = fwphy_rddata(sc, FW_PHY_SPD_REG);
444
445 if((reg >> 5) != 7 ){
446 sc->fc.mode &= ~FWPHYASYST;
447 sc->fc.nport = reg & FW_PHY_NP;
448 sc->fc.speed = reg & FW_PHY_SPD >> 6;
449 if (sc->fc.speed > MAX_SPEED) {
450 device_printf(dev, "invalid speed %d (fixed to %d).\n",
451 sc->fc.speed, MAX_SPEED);
452 sc->fc.speed = MAX_SPEED;
453 }
454 device_printf(dev,
455 "Phy 1394 only %s, %d ports.\n",
456 linkspeed[sc->fc.speed], sc->fc.nport);
457 }else{
458 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG);
459 sc->fc.mode |= FWPHYASYST;
460 sc->fc.nport = reg & FW_PHY_NP;
461 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5;
462 if (sc->fc.speed > MAX_SPEED) {
463 device_printf(dev, "invalid speed %d (fixed to %d).\n",
464 sc->fc.speed, MAX_SPEED);
465 sc->fc.speed = MAX_SPEED;
466 }
467 device_printf(dev,
468 "Phy 1394a available %s, %d ports.\n",
469 linkspeed[sc->fc.speed], sc->fc.nport);
470
471 /* check programPhyEnable */
472 reg2 = fwphy_rddata(sc, 5);
473 #if 0
474 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) {
475 #else /* XXX force to enable 1394a */
476 if (e1394a) {
477 #endif
478 if (firewire_debug)
479 device_printf(dev,
480 "Enable 1394a Enhancements\n");
481 /* enable EAA EMC */
482 reg2 |= 0x03;
483 /* set aPhyEnhanceEnable */
484 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN);
485 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY);
486 } else {
487 /* for safe */
488 reg2 &= ~0x83;
489 }
490 reg2 = fwphy_wrdata(sc, 5, reg2);
491 }
492
493 reg = fwphy_rddata(sc, FW_PHY_SPD_REG);
494 if((reg >> 5) == 7 ){
495 reg = fwphy_rddata(sc, 4);
496 reg |= 1 << 6;
497 fwphy_wrdata(sc, 4, reg);
498 reg = fwphy_rddata(sc, 4);
499 }
500 return 0;
501 }
502
503
504 void
505 fwohci_reset(struct fwohci_softc *sc, device_t dev)
506 {
507 int i, max_rec, speed;
508 uint32_t reg, reg2;
509 struct fwohcidb_tr *db_tr;
510
511 /* Disable interrupts */
512 OWRITE(sc, FWOHCI_INTMASKCLR, ~0);
513
514 /* Now stopping all DMA channels */
515 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN);
516 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN);
517 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
518 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
519
520 OWRITE(sc, OHCI_IR_MASKCLR, ~0);
521 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
522 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN);
523 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN);
524 }
525
526 /* FLUSH FIFO and reset Transmitter/Reciever */
527 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET);
528 if (firewire_debug)
529 device_printf(dev, "resetting OHCI...");
530 i = 0;
531 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) {
532 if (i++ > 100) break;
533 DELAY(1000);
534 }
535 if (firewire_debug)
536 printf("done (loop=%d)\n", i);
537
538 /* Probe phy */
539 fwohci_probe_phy(sc, dev);
540
541 /* Probe link */
542 reg = OREAD(sc, OHCI_BUS_OPT);
543 reg2 = reg | OHCI_BUSFNC;
544 max_rec = (reg & 0x0000f000) >> 12;
545 speed = (reg & 0x00000007);
546 device_printf(dev, "Link %s, max_rec %d bytes.\n",
547 linkspeed[speed], MAXREC(max_rec));
548 /* XXX fix max_rec */
549 sc->fc.maxrec = sc->fc.speed + 8;
550 if (max_rec != sc->fc.maxrec) {
551 reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12);
552 device_printf(dev, "max_rec %d -> %d\n",
553 MAXREC(max_rec), MAXREC(sc->fc.maxrec));
554 }
555 if (firewire_debug)
556 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2);
557 OWRITE(sc, OHCI_BUS_OPT, reg2);
558
559 /* Initialize registers */
560 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]);
561 OWRITE(sc, OHCI_CROMPTR, sc->crom_dma.bus_addr);
562 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND);
563 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR);
564 OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr);
565 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID);
566
567 /* Enable link */
568 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN);
569
570 /* Force to start async RX DMA */
571 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING;
572 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING;
573 fwohci_rx_enable(sc, &sc->arrq);
574 fwohci_rx_enable(sc, &sc->arrs);
575
576 /* Initialize async TX */
577 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD);
578 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD);
579
580 /* AT Retries */
581 OWRITE(sc, FWOHCI_RETRY,
582 /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */
583 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ;
584
585 sc->atrq.top = STAILQ_FIRST(&sc->atrq.db_trq);
586 sc->atrs.top = STAILQ_FIRST(&sc->atrs.db_trq);
587 sc->atrq.bottom = sc->atrq.top;
588 sc->atrs.bottom = sc->atrs.top;
589
590 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ;
591 i ++, db_tr = STAILQ_NEXT(db_tr, link)){
592 db_tr->xfer = NULL;
593 }
594 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ;
595 i ++, db_tr = STAILQ_NEXT(db_tr, link)){
596 db_tr->xfer = NULL;
597 }
598
599
600 /* Enable interrupts */
601 sc->intmask = (OHCI_INT_ERR | OHCI_INT_PHY_SID
602 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS
603 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS
604 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR);
605 sc->intmask |= OHCI_INT_DMA_IR | OHCI_INT_DMA_IT;
606 sc->intmask |= OHCI_INT_CYC_LOST | OHCI_INT_PHY_INT;
607 OWRITE(sc, FWOHCI_INTMASK, sc->intmask);
608 fwohci_set_intr(&sc->fc, 1);
609
610 }
611
612 int
613 fwohci_init(struct fwohci_softc *sc, device_t dev)
614 {
615 int i, mver;
616 uint32_t reg;
617 uint8_t ui[8];
618
619 /* OHCI version */
620 reg = OREAD(sc, OHCI_VERSION);
621 mver = (reg >> 16) & 0xff;
622 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n",
623 mver, reg & 0xff, (reg>>24) & 1);
624 if (mver < 1 || mver > 9) {
625 device_printf(dev, "invalid OHCI version\n");
626 return (ENXIO);
627 }
628
629 /* Available Isochronous DMA channel probe */
630 OWRITE(sc, OHCI_IT_MASK, 0xffffffff);
631 OWRITE(sc, OHCI_IR_MASK, 0xffffffff);
632 reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK);
633 OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff);
634 OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff);
635 for (i = 0; i < 0x20; i++)
636 if ((reg & (1 << i)) == 0)
637 break;
638 sc->fc.nisodma = i;
639 device_printf(dev, "No. of Isochronous channels is %d.\n", i);
640 if (i == 0)
641 return (ENXIO);
642
643 sc->fc.arq = &sc->arrq.xferq;
644 sc->fc.ars = &sc->arrs.xferq;
645 sc->fc.atq = &sc->atrq.xferq;
646 sc->fc.ats = &sc->atrs.xferq;
647
648 sc->arrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE);
649 sc->arrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE);
650 sc->atrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE);
651 sc->atrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE);
652
653 sc->arrq.xferq.start = NULL;
654 sc->arrs.xferq.start = NULL;
655 sc->atrq.xferq.start = fwohci_start_atq;
656 sc->atrs.xferq.start = fwohci_start_ats;
657
658 sc->arrq.xferq.buf = NULL;
659 sc->arrs.xferq.buf = NULL;
660 sc->atrq.xferq.buf = NULL;
661 sc->atrs.xferq.buf = NULL;
662
663 sc->arrq.xferq.dmach = -1;
664 sc->arrs.xferq.dmach = -1;
665 sc->atrq.xferq.dmach = -1;
666 sc->atrs.xferq.dmach = -1;
667
668 sc->arrq.ndesc = 1;
669 sc->arrs.ndesc = 1;
670 sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */
671 sc->atrs.ndesc = 2;
672
673 sc->arrq.ndb = NDB;
674 sc->arrs.ndb = NDB / 2;
675 sc->atrq.ndb = NDB;
676 sc->atrs.ndb = NDB / 2;
677
678 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
679 sc->fc.it[i] = &sc->it[i].xferq;
680 sc->fc.ir[i] = &sc->ir[i].xferq;
681 sc->it[i].xferq.dmach = i;
682 sc->ir[i].xferq.dmach = i;
683 sc->it[i].ndb = 0;
684 sc->ir[i].ndb = 0;
685 }
686
687 sc->fc.tcode = tinfo;
688 sc->fc.dev = dev;
689
690 sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE,
691 &sc->crom_dma, BUS_DMA_WAITOK | BUS_DMA_COHERENT);
692 if(sc->fc.config_rom == NULL){
693 device_printf(dev, "config_rom alloc failed.");
694 return ENOMEM;
695 }
696
697 #if 0
698 bzero(&sc->fc.config_rom[0], CROMSIZE);
699 sc->fc.config_rom[1] = 0x31333934;
700 sc->fc.config_rom[2] = 0xf000a002;
701 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI);
702 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO);
703 sc->fc.config_rom[5] = 0;
704 sc->fc.config_rom[0] = (4 << 24) | (5 << 16);
705
706 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4);
707 #endif
708
709
710 /* SID recieve buffer must align 2^11 */
711 #define OHCI_SIDSIZE (1 << 11)
712 sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE,
713 &sc->sid_dma, BUS_DMA_WAITOK | BUS_DMA_COHERENT);
714 if (sc->sid_buf == NULL) {
715 device_printf(dev, "sid_buf alloc failed.");
716 return ENOMEM;
717 }
718
719 fwdma_malloc(&sc->fc, sizeof(uint32_t), sizeof(uint32_t),
720 &sc->dummy_dma, BUS_DMA_WAITOK);
721
722 if (sc->dummy_dma.v_addr == NULL) {
723 device_printf(dev, "dummy_dma alloc failed.");
724 return ENOMEM;
725 }
726
727 fwohci_db_init(sc, &sc->arrq);
728 if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0)
729 return ENOMEM;
730
731 fwohci_db_init(sc, &sc->arrs);
732 if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0)
733 return ENOMEM;
734
735 fwohci_db_init(sc, &sc->atrq);
736 if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0)
737 return ENOMEM;
738
739 fwohci_db_init(sc, &sc->atrs);
740 if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0)
741 return ENOMEM;
742
743 sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H);
744 sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L);
745 for( i = 0 ; i < 8 ; i ++)
746 ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i);
747 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
748 ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]);
749
750 sc->fc.ioctl = fwohci_ioctl;
751 sc->fc.cyctimer = fwohci_cyctimer;
752 sc->fc.set_bmr = fwohci_set_bus_manager;
753 sc->fc.ibr = fwohci_ibr;
754 sc->fc.irx_enable = fwohci_irx_enable;
755 sc->fc.irx_disable = fwohci_irx_disable;
756
757 sc->fc.itx_enable = fwohci_itxbuf_enable;
758 sc->fc.itx_disable = fwohci_itx_disable;
759 #if BYTE_ORDER == BIG_ENDIAN
760 sc->fc.irx_post = fwohci_irx_post;
761 #else
762 sc->fc.irx_post = NULL;
763 #endif
764 sc->fc.itx_post = NULL;
765 sc->fc.timeout = fwohci_timeout;
766 sc->fc.poll = fwohci_poll;
767 sc->fc.set_intr = fwohci_set_intr;
768
769 sc->intmask = sc->irstat = sc->itstat = 0;
770
771 /* Init task queue */
772 sc->fc.taskqueue = taskqueue_create_fast("fw_taskq", M_WAITOK,
773 taskqueue_thread_enqueue, &sc->fc.taskqueue);
774 taskqueue_start_threads(&sc->fc.taskqueue, 1, PI_NET, "fw%d_taskq",
775 device_get_unit(dev));
776 TASK_INIT(&sc->fwohci_task_busreset, 2, fwohci_task_busreset, sc);
777 TASK_INIT(&sc->fwohci_task_sid, 1, fwohci_task_sid, sc);
778 TASK_INIT(&sc->fwohci_task_dma, 0, fwohci_task_dma, sc);
779
780 fw_init(&sc->fc);
781 fwohci_reset(sc, dev);
782
783 return 0;
784 }
785
786 void
787 fwohci_timeout(void *arg)
788 {
789 struct fwohci_softc *sc;
790
791 sc = (struct fwohci_softc *)arg;
792 }
793
794 uint32_t
795 fwohci_cyctimer(struct firewire_comm *fc)
796 {
797 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
798 return(OREAD(sc, OHCI_CYCLETIMER));
799 }
800
801 int
802 fwohci_detach(struct fwohci_softc *sc, device_t dev)
803 {
804 int i;
805
806 if (sc->sid_buf != NULL)
807 fwdma_free(&sc->fc, &sc->sid_dma);
808 if (sc->fc.config_rom != NULL)
809 fwdma_free(&sc->fc, &sc->crom_dma);
810
811 fwohci_db_free(&sc->arrq);
812 fwohci_db_free(&sc->arrs);
813
814 fwohci_db_free(&sc->atrq);
815 fwohci_db_free(&sc->atrs);
816
817 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
818 fwohci_db_free(&sc->it[i]);
819 fwohci_db_free(&sc->ir[i]);
820 }
821 if (sc->fc.taskqueue != NULL) {
822 taskqueue_drain(sc->fc.taskqueue, &sc->fwohci_task_busreset);
823 taskqueue_drain(sc->fc.taskqueue, &sc->fwohci_task_sid);
824 taskqueue_drain(sc->fc.taskqueue, &sc->fwohci_task_dma);
825 taskqueue_drain(sc->fc.taskqueue, &sc->fc.task_timeout);
826 taskqueue_free(sc->fc.taskqueue);
827 sc->fc.taskqueue = NULL;
828 }
829
830 return 0;
831 }
832
833 #define LAST_DB(dbtr, db) do { \
834 struct fwohcidb_tr *_dbtr = (dbtr); \
835 int _cnt = _dbtr->dbcnt; \
836 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \
837 } while (0)
838
839 static void
840 fwohci_execute_db(void *arg, bus_dma_segment_t *segs, int nseg, int error)
841 {
842 struct fwohcidb_tr *db_tr;
843 struct fwohcidb *db;
844 bus_dma_segment_t *s;
845 int i;
846
847 db_tr = (struct fwohcidb_tr *)arg;
848 db = &db_tr->db[db_tr->dbcnt];
849 if (error) {
850 if (firewire_debug || error != EFBIG)
851 printf("fwohci_execute_db: error=%d\n", error);
852 return;
853 }
854 for (i = 0; i < nseg; i++) {
855 s = &segs[i];
856 FWOHCI_DMA_WRITE(db->db.desc.addr, s->ds_addr);
857 FWOHCI_DMA_WRITE(db->db.desc.cmd, s->ds_len);
858 FWOHCI_DMA_WRITE(db->db.desc.res, 0);
859 db++;
860 db_tr->dbcnt++;
861 }
862 }
863
864 static void
865 fwohci_execute_db2(void *arg, bus_dma_segment_t *segs, int nseg,
866 bus_size_t size, int error)
867 {
868 fwohci_execute_db(arg, segs, nseg, error);
869 }
870
871 static void
872 fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
873 {
874 int i;
875 int tcode, hdr_len, pl_off;
876 int fsegment = -1;
877 uint32_t off;
878 struct fw_xfer *xfer;
879 struct fw_pkt *fp;
880 struct fwohci_txpkthdr *ohcifp;
881 struct fwohcidb_tr *db_tr;
882 struct fwohcidb *db;
883 uint32_t *ld;
884 struct tcode_info *info;
885 static int maxdesc=0;
886
887 FW_GLOCK_ASSERT(&sc->fc);
888
889 if(&sc->atrq == dbch){
890 off = OHCI_ATQOFF;
891 }else if(&sc->atrs == dbch){
892 off = OHCI_ATSOFF;
893 }else{
894 return;
895 }
896
897 if (dbch->flags & FWOHCI_DBCH_FULL)
898 return;
899
900 db_tr = dbch->top;
901 txloop:
902 xfer = STAILQ_FIRST(&dbch->xferq.q);
903 if(xfer == NULL){
904 goto kick;
905 }
906 #if 0
907 if(dbch->xferq.queued == 0 ){
908 device_printf(sc->fc.dev, "TX queue empty\n");
909 }
910 #endif
911 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link);
912 db_tr->xfer = xfer;
913 xfer->flag = FWXF_START;
914
915 fp = &xfer->send.hdr;
916 tcode = fp->mode.common.tcode;
917
918 ohcifp = (struct fwohci_txpkthdr *) db_tr->db[1].db.immed;
919 info = &tinfo[tcode];
920 hdr_len = pl_off = info->hdr_len;
921
922 ld = &ohcifp->mode.ld[0];
923 ld[0] = ld[1] = ld[2] = ld[3] = 0;
924 for( i = 0 ; i < pl_off ; i+= 4)
925 ld[i/4] = fp->mode.ld[i/4];
926
927 ohcifp->mode.common.spd = xfer->send.spd & 0x7;
928 if (tcode == FWTCODE_STREAM ){
929 hdr_len = 8;
930 ohcifp->mode.stream.len = fp->mode.stream.len;
931 } else if (tcode == FWTCODE_PHY) {
932 hdr_len = 12;
933 ld[1] = fp->mode.ld[1];
934 ld[2] = fp->mode.ld[2];
935 ohcifp->mode.common.spd = 0;
936 ohcifp->mode.common.tcode = FWOHCITCODE_PHY;
937 } else {
938 ohcifp->mode.asycomm.dst = fp->mode.hdr.dst;
939 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS;
940 ohcifp->mode.asycomm.tlrt |= FWRETRY_X;
941 }
942 db = &db_tr->db[0];
943 FWOHCI_DMA_WRITE(db->db.desc.cmd,
944 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len);
945 FWOHCI_DMA_WRITE(db->db.desc.addr, 0);
946 FWOHCI_DMA_WRITE(db->db.desc.res, 0);
947 /* Specify bound timer of asy. responce */
948 if(&sc->atrs == dbch){
949 FWOHCI_DMA_WRITE(db->db.desc.res,
950 (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13));
951 }
952 #if BYTE_ORDER == BIG_ENDIAN
953 if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ)
954 hdr_len = 12;
955 for (i = 0; i < hdr_len/4; i ++)
956 FWOHCI_DMA_WRITE(ld[i], ld[i]);
957 #endif
958
959 again:
960 db_tr->dbcnt = 2;
961 db = &db_tr->db[db_tr->dbcnt];
962 if (xfer->send.pay_len > 0) {
963 int err;
964 /* handle payload */
965 if (xfer->mbuf == NULL) {
966 err = bus_dmamap_load(dbch->dmat, db_tr->dma_map,
967 &xfer->send.payload[0], xfer->send.pay_len,
968 fwohci_execute_db, db_tr,
969 /*flags*/0);
970 } else {
971 /* XXX we can handle only 6 (=8-2) mbuf chains */
972 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map,
973 xfer->mbuf,
974 fwohci_execute_db2, db_tr,
975 /* flags */0);
976 if (err == EFBIG) {
977 struct mbuf *m0;
978
979 if (firewire_debug)
980 device_printf(sc->fc.dev, "EFBIG.\n");
981 m0 = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
982 if (m0 != NULL) {
983 m_copydata(xfer->mbuf, 0,
984 xfer->mbuf->m_pkthdr.len,
985 mtod(m0, caddr_t));
986 m0->m_len = m0->m_pkthdr.len =
987 xfer->mbuf->m_pkthdr.len;
988 m_freem(xfer->mbuf);
989 xfer->mbuf = m0;
990 goto again;
991 }
992 device_printf(sc->fc.dev, "m_getcl failed.\n");
993 }
994 }
995 if (err)
996 printf("dmamap_load: err=%d\n", err);
997 bus_dmamap_sync(dbch->dmat, db_tr->dma_map,
998 BUS_DMASYNC_PREWRITE);
999 #if 0 /* OHCI_OUTPUT_MODE == 0 */
1000 for (i = 2; i < db_tr->dbcnt; i++)
1001 FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd,
1002 OHCI_OUTPUT_MORE);
1003 #endif
1004 }
1005 if (maxdesc < db_tr->dbcnt) {
1006 maxdesc = db_tr->dbcnt;
1007 if (firewire_debug)
1008 device_printf(sc->fc.dev, "%s: maxdesc %d\n", __func__, maxdesc);
1009 }
1010 /* last db */
1011 LAST_DB(db_tr, db);
1012 FWOHCI_DMA_SET(db->db.desc.cmd,
1013 OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS);
1014 FWOHCI_DMA_WRITE(db->db.desc.depend,
1015 STAILQ_NEXT(db_tr, link)->bus_addr);
1016
1017 if(fsegment == -1 )
1018 fsegment = db_tr->dbcnt;
1019 if (dbch->pdb_tr != NULL) {
1020 LAST_DB(dbch->pdb_tr, db);
1021 FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt);
1022 }
1023 dbch->xferq.queued ++;
1024 dbch->pdb_tr = db_tr;
1025 db_tr = STAILQ_NEXT(db_tr, link);
1026 if(db_tr != dbch->bottom){
1027 goto txloop;
1028 } else {
1029 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n");
1030 dbch->flags |= FWOHCI_DBCH_FULL;
1031 }
1032 kick:
1033 /* kick asy q */
1034 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD);
1035 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
1036
1037 if(dbch->xferq.flag & FWXFERQ_RUNNING) {
1038 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE);
1039 } else {
1040 if (firewire_debug)
1041 device_printf(sc->fc.dev, "start AT DMA status=%x\n",
1042 OREAD(sc, OHCI_DMACTL(off)));
1043 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment);
1044 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN);
1045 dbch->xferq.flag |= FWXFERQ_RUNNING;
1046 }
1047
1048 dbch->top = db_tr;
1049 return;
1050 }
1051
1052 static void
1053 fwohci_start_atq(struct firewire_comm *fc)
1054 {
1055 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1056 FW_GLOCK(&sc->fc);
1057 fwohci_start( sc, &(sc->atrq));
1058 FW_GUNLOCK(&sc->fc);
1059 return;
1060 }
1061
1062 static void
1063 fwohci_start_ats(struct firewire_comm *fc)
1064 {
1065 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1066 FW_GLOCK(&sc->fc);
1067 fwohci_start( sc, &(sc->atrs));
1068 FW_GUNLOCK(&sc->fc);
1069 return;
1070 }
1071
1072 void
1073 fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1074 {
1075 int s, ch, err = 0;
1076 struct fwohcidb_tr *tr;
1077 struct fwohcidb *db;
1078 struct fw_xfer *xfer;
1079 uint32_t off;
1080 u_int stat, status;
1081 int packets;
1082 struct firewire_comm *fc = (struct firewire_comm *)sc;
1083
1084 if(&sc->atrq == dbch){
1085 off = OHCI_ATQOFF;
1086 ch = ATRQ_CH;
1087 }else if(&sc->atrs == dbch){
1088 off = OHCI_ATSOFF;
1089 ch = ATRS_CH;
1090 }else{
1091 return;
1092 }
1093 s = splfw();
1094 tr = dbch->bottom;
1095 packets = 0;
1096 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD);
1097 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE);
1098 while(dbch->xferq.queued > 0){
1099 LAST_DB(tr, db);
1100 status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT;
1101 if(!(status & OHCI_CNTL_DMA_ACTIVE)){
1102 if (fc->status != FWBUSINIT)
1103 /* maybe out of order?? */
1104 goto out;
1105 }
1106 bus_dmamap_sync(dbch->dmat, tr->dma_map,
1107 BUS_DMASYNC_POSTWRITE);
1108 bus_dmamap_unload(dbch->dmat, tr->dma_map);
1109 #if 1
1110 if (firewire_debug > 1)
1111 dump_db(sc, ch);
1112 #endif
1113 if(status & OHCI_CNTL_DMA_DEAD) {
1114 /* Stop DMA */
1115 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN);
1116 device_printf(sc->fc.dev, "force reset AT FIFO\n");
1117 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN);
1118 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN);
1119 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN);
1120 }
1121 stat = status & FWOHCIEV_MASK;
1122 switch(stat){
1123 case FWOHCIEV_ACKPEND:
1124 case FWOHCIEV_ACKCOMPL:
1125 err = 0;
1126 break;
1127 case FWOHCIEV_ACKBSA:
1128 case FWOHCIEV_ACKBSB:
1129 case FWOHCIEV_ACKBSX:
1130 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]);
1131 err = EBUSY;
1132 break;
1133 case FWOHCIEV_FLUSHED:
1134 case FWOHCIEV_ACKTARD:
1135 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]);
1136 err = EAGAIN;
1137 break;
1138 case FWOHCIEV_MISSACK:
1139 case FWOHCIEV_UNDRRUN:
1140 case FWOHCIEV_OVRRUN:
1141 case FWOHCIEV_DESCERR:
1142 case FWOHCIEV_DTRDERR:
1143 case FWOHCIEV_TIMEOUT:
1144 case FWOHCIEV_TCODERR:
1145 case FWOHCIEV_UNKNOWN:
1146 case FWOHCIEV_ACKDERR:
1147 case FWOHCIEV_ACKTERR:
1148 default:
1149 device_printf(sc->fc.dev, "txd err=%2x %s\n",
1150 stat, fwohcicode[stat]);
1151 err = EINVAL;
1152 break;
1153 }
1154 if (tr->xfer != NULL) {
1155 xfer = tr->xfer;
1156 if (xfer->flag & FWXF_RCVD) {
1157 #if 0
1158 if (firewire_debug)
1159 printf("already rcvd\n");
1160 #endif
1161 fw_xfer_done(xfer);
1162 } else {
1163 microtime(&xfer->tv);
1164 xfer->flag = FWXF_SENT;
1165 if (err == EBUSY) {
1166 xfer->flag = FWXF_BUSY;
1167 xfer->resp = err;
1168 xfer->recv.pay_len = 0;
1169 fw_xfer_done(xfer);
1170 } else if (stat != FWOHCIEV_ACKPEND) {
1171 if (stat != FWOHCIEV_ACKCOMPL)
1172 xfer->flag = FWXF_SENTERR;
1173 xfer->resp = err;
1174 xfer->recv.pay_len = 0;
1175 fw_xfer_done(xfer);
1176 }
1177 }
1178 /*
1179 * The watchdog timer takes care of split
1180 * transcation timeout for ACKPEND case.
1181 */
1182 } else {
1183 printf("this shouldn't happen\n");
1184 }
1185 FW_GLOCK(fc);
1186 dbch->xferq.queued --;
1187 FW_GUNLOCK(fc);
1188 tr->xfer = NULL;
1189
1190 packets ++;
1191 tr = STAILQ_NEXT(tr, link);
1192 dbch->bottom = tr;
1193 if (dbch->bottom == dbch->top) {
1194 /* we reaches the end of context program */
1195 if (firewire_debug && dbch->xferq.queued > 0)
1196 printf("queued > 0\n");
1197 break;
1198 }
1199 }
1200 out:
1201 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) {
1202 printf("make free slot\n");
1203 dbch->flags &= ~FWOHCI_DBCH_FULL;
1204 FW_GLOCK(fc);
1205 fwohci_start(sc, dbch);
1206 FW_GUNLOCK(fc);
1207 }
1208 splx(s);
1209 }
1210
1211 static void
1212 fwohci_db_free(struct fwohci_dbch *dbch)
1213 {
1214 struct fwohcidb_tr *db_tr;
1215 int idb;
1216
1217 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0)
1218 return;
1219
1220 for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb;
1221 db_tr = STAILQ_NEXT(db_tr, link), idb++){
1222 if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 &&
1223 db_tr->buf != NULL) {
1224 fwdma_free_size(dbch->dmat, db_tr->dma_map,
1225 db_tr->buf, dbch->xferq.psize);
1226 db_tr->buf = NULL;
1227 } else if (db_tr->dma_map != NULL)
1228 bus_dmamap_destroy(dbch->dmat, db_tr->dma_map);
1229 }
1230 dbch->ndb = 0;
1231 db_tr = STAILQ_FIRST(&dbch->db_trq);
1232 fwdma_free_multiseg(dbch->am);
1233 free(db_tr, M_FW);
1234 STAILQ_INIT(&dbch->db_trq);
1235 dbch->flags &= ~FWOHCI_DBCH_INIT;
1236 }
1237
1238 static void
1239 fwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1240 {
1241 int idb;
1242 struct fwohcidb_tr *db_tr;
1243
1244 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0)
1245 goto out;
1246
1247 /* create dma_tag for buffers */
1248 #define MAX_REQCOUNT 0xffff
1249 if (bus_dma_tag_create(/*parent*/ sc->fc.dmat,
1250 /*alignment*/ 1, /*boundary*/ 0,
1251 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT,
1252 /*highaddr*/ BUS_SPACE_MAXADDR,
1253 /*filter*/NULL, /*filterarg*/NULL,
1254 /*maxsize*/ dbch->xferq.psize,
1255 /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1,
1256 /*maxsegsz*/ MAX_REQCOUNT,
1257 /*flags*/ 0,
1258 #if defined(__FreeBSD__) && __FreeBSD_version >= 501102
1259 /*lockfunc*/busdma_lock_mutex,
1260 /*lockarg*/FW_GMTX(&sc->fc),
1261 #endif
1262 &dbch->dmat))
1263 return;
1264
1265 /* allocate DB entries and attach one to each DMA channels */
1266 /* DB entry must start at 16 bytes bounary. */
1267 STAILQ_INIT(&dbch->db_trq);
1268 db_tr = (struct fwohcidb_tr *)
1269 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb,
1270 M_FW, M_WAITOK | M_ZERO);
1271 if(db_tr == NULL){
1272 printf("fwohci_db_init: malloc(1) failed\n");
1273 return;
1274 }
1275
1276 #define DB_SIZE(x) (sizeof(struct fwohcidb) * (x)->ndesc)
1277 dbch->am = fwdma_malloc_multiseg(&sc->fc, DB_SIZE(dbch),
1278 DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK);
1279 if (dbch->am == NULL) {
1280 printf("fwohci_db_init: fwdma_malloc_multiseg failed\n");
1281 free(db_tr, M_FW);
1282 return;
1283 }
1284 /* Attach DB to DMA ch. */
1285 for(idb = 0 ; idb < dbch->ndb ; idb++){
1286 db_tr->dbcnt = 0;
1287 db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb);
1288 db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb);
1289 /* create dmamap for buffers */
1290 /* XXX do we need 4bytes alignment tag? */
1291 /* XXX don't alloc dma_map for AR */
1292 if (bus_dmamap_create(dbch->dmat, 0, &db_tr->dma_map) != 0) {
1293 printf("bus_dmamap_create failed\n");
1294 dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */
1295 fwohci_db_free(dbch);
1296 return;
1297 }
1298 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link);
1299 if (dbch->xferq.flag & FWXFERQ_EXTBUF) {
1300 if (idb % dbch->xferq.bnpacket == 0)
1301 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket
1302 ].start = (caddr_t)db_tr;
1303 if ((idb + 1) % dbch->xferq.bnpacket == 0)
1304 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket
1305 ].end = (caddr_t)db_tr;
1306 }
1307 db_tr++;
1308 }
1309 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next
1310 = STAILQ_FIRST(&dbch->db_trq);
1311 out:
1312 dbch->xferq.queued = 0;
1313 dbch->pdb_tr = NULL;
1314 dbch->top = STAILQ_FIRST(&dbch->db_trq);
1315 dbch->bottom = dbch->top;
1316 dbch->flags = FWOHCI_DBCH_INIT;
1317 }
1318
1319 static int
1320 fwohci_itx_disable(struct firewire_comm *fc, int dmach)
1321 {
1322 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1323
1324 OWRITE(sc, OHCI_ITCTLCLR(dmach),
1325 OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S);
1326 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach);
1327 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach);
1328 /* XXX we cannot free buffers until the DMA really stops */
1329 pause("fwitxd", hz);
1330 fwohci_db_free(&sc->it[dmach]);
1331 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING;
1332 return 0;
1333 }
1334
1335 static int
1336 fwohci_irx_disable(struct firewire_comm *fc, int dmach)
1337 {
1338 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1339
1340 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1341 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach);
1342 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach);
1343 /* XXX we cannot free buffers until the DMA really stops */
1344 pause("fwirxd", hz);
1345 fwohci_db_free(&sc->ir[dmach]);
1346 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING;
1347 return 0;
1348 }
1349
1350 #if BYTE_ORDER == BIG_ENDIAN
1351 static void
1352 fwohci_irx_post (struct firewire_comm *fc , uint32_t *qld)
1353 {
1354 qld[0] = FWOHCI_DMA_READ(qld[0]);
1355 return;
1356 }
1357 #endif
1358
1359 static int
1360 fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1361 {
1362 int err = 0;
1363 int idb, z, i, dmach = 0, ldesc;
1364 uint32_t off = 0;
1365 struct fwohcidb_tr *db_tr;
1366 struct fwohcidb *db;
1367
1368 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){
1369 err = EINVAL;
1370 return err;
1371 }
1372 z = dbch->ndesc;
1373 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){
1374 if( &sc->it[dmach] == dbch){
1375 off = OHCI_ITOFF(dmach);
1376 break;
1377 }
1378 }
1379 if(off == 0){
1380 err = EINVAL;
1381 return err;
1382 }
1383 if(dbch->xferq.flag & FWXFERQ_RUNNING)
1384 return err;
1385 dbch->xferq.flag |= FWXFERQ_RUNNING;
1386 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){
1387 dbch->bottom = STAILQ_NEXT(dbch->bottom, link);
1388 }
1389 db_tr = dbch->top;
1390 for (idb = 0; idb < dbch->ndb; idb ++) {
1391 fwohci_add_tx_buf(dbch, db_tr, idb);
1392 if(STAILQ_NEXT(db_tr, link) == NULL){
1393 break;
1394 }
1395 db = db_tr->db;
1396 ldesc = db_tr->dbcnt - 1;
1397 FWOHCI_DMA_WRITE(db[0].db.desc.depend,
1398 STAILQ_NEXT(db_tr, link)->bus_addr | z);
1399 db[ldesc].db.desc.depend = db[0].db.desc.depend;
1400 if(dbch->xferq.flag & FWXFERQ_EXTBUF){
1401 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){
1402 FWOHCI_DMA_SET(
1403 db[ldesc].db.desc.cmd,
1404 OHCI_INTERRUPT_ALWAYS);
1405 /* OHCI 1.1 and above */
1406 FWOHCI_DMA_SET(
1407 db[0].db.desc.cmd,
1408 OHCI_INTERRUPT_ALWAYS);
1409 }
1410 }
1411 db_tr = STAILQ_NEXT(db_tr, link);
1412 }
1413 FWOHCI_DMA_CLEAR(
1414 dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf);
1415 return err;
1416 }
1417
1418 static int
1419 fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1420 {
1421 int err = 0;
1422 int idb, z, i, dmach = 0, ldesc;
1423 uint32_t off = 0;
1424 struct fwohcidb_tr *db_tr;
1425 struct fwohcidb *db;
1426
1427 z = dbch->ndesc;
1428 if(&sc->arrq == dbch){
1429 off = OHCI_ARQOFF;
1430 }else if(&sc->arrs == dbch){
1431 off = OHCI_ARSOFF;
1432 }else{
1433 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){
1434 if( &sc->ir[dmach] == dbch){
1435 off = OHCI_IROFF(dmach);
1436 break;
1437 }
1438 }
1439 }
1440 if(off == 0){
1441 err = EINVAL;
1442 return err;
1443 }
1444 if(dbch->xferq.flag & FWXFERQ_STREAM){
1445 if(dbch->xferq.flag & FWXFERQ_RUNNING)
1446 return err;
1447 }else{
1448 if(dbch->xferq.flag & FWXFERQ_RUNNING){
1449 err = EBUSY;
1450 return err;
1451 }
1452 }
1453 dbch->xferq.flag |= FWXFERQ_RUNNING;
1454 dbch->top = STAILQ_FIRST(&dbch->db_trq);
1455 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){
1456 dbch->bottom = STAILQ_NEXT(dbch->bottom, link);
1457 }
1458 db_tr = dbch->top;
1459 for (idb = 0; idb < dbch->ndb; idb ++) {
1460 fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma);
1461 if (STAILQ_NEXT(db_tr, link) == NULL)
1462 break;
1463 db = db_tr->db;
1464 ldesc = db_tr->dbcnt - 1;
1465 FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend,
1466 STAILQ_NEXT(db_tr, link)->bus_addr | z);
1467 if(dbch->xferq.flag & FWXFERQ_EXTBUF){
1468 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){
1469 FWOHCI_DMA_SET(
1470 db[ldesc].db.desc.cmd,
1471 OHCI_INTERRUPT_ALWAYS);
1472 FWOHCI_DMA_CLEAR(
1473 db[ldesc].db.desc.depend,
1474 0xf);
1475 }
1476 }
1477 db_tr = STAILQ_NEXT(db_tr, link);
1478 }
1479 FWOHCI_DMA_CLEAR(
1480 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf);
1481 dbch->buf_offset = 0;
1482 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD);
1483 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
1484 if(dbch->xferq.flag & FWXFERQ_STREAM){
1485 return err;
1486 }else{
1487 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z);
1488 }
1489 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN);
1490 return err;
1491 }
1492
1493 static int
1494 fwohci_next_cycle(struct firewire_comm *fc, int cycle_now)
1495 {
1496 int sec, cycle, cycle_match;
1497
1498 cycle = cycle_now & 0x1fff;
1499 sec = cycle_now >> 13;
1500 #define CYCLE_MOD 0x10
1501 #if 1
1502 #define CYCLE_DELAY 8 /* min delay to start DMA */
1503 #else
1504 #define CYCLE_DELAY 7000 /* min delay to start DMA */
1505 #endif
1506 cycle = cycle + CYCLE_DELAY;
1507 if (cycle >= 8000) {
1508 sec ++;
1509 cycle -= 8000;
1510 }
1511 cycle = roundup2(cycle, CYCLE_MOD);
1512 if (cycle >= 8000) {
1513 sec ++;
1514 if (cycle == 8000)
1515 cycle = 0;
1516 else
1517 cycle = CYCLE_MOD;
1518 }
1519 cycle_match = ((sec << 13) | cycle) & 0x7ffff;
1520
1521 return(cycle_match);
1522 }
1523
1524 static int
1525 fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach)
1526 {
1527 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1528 int err = 0;
1529 unsigned short tag, ich;
1530 struct fwohci_dbch *dbch;
1531 int cycle_match, cycle_now, s, ldesc;
1532 uint32_t stat;
1533 struct fw_bulkxfer *first, *chunk, *prev;
1534 struct fw_xferq *it;
1535
1536 dbch = &sc->it[dmach];
1537 it = &dbch->xferq;
1538
1539 tag = (it->flag >> 6) & 3;
1540 ich = it->flag & 0x3f;
1541 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) {
1542 dbch->ndb = it->bnpacket * it->bnchunk;
1543 dbch->ndesc = 3;
1544 fwohci_db_init(sc, dbch);
1545 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0)
1546 return ENOMEM;
1547
1548 err = fwohci_tx_enable(sc, dbch);
1549 }
1550 if(err)
1551 return err;
1552
1553 ldesc = dbch->ndesc - 1;
1554 s = splfw();
1555 FW_GLOCK(fc);
1556 prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link);
1557 while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) {
1558 struct fwohcidb *db;
1559
1560 fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket,
1561 BUS_DMASYNC_PREWRITE);
1562 fwohci_txbufdb(sc, dmach, chunk);
1563 if (prev != NULL) {
1564 db = ((struct fwohcidb_tr *)(prev->end))->db;
1565 #if 0 /* XXX necessary? */
1566 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd,
1567 OHCI_BRANCH_ALWAYS);
1568 #endif
1569 #if 0 /* if bulkxfer->npacket changes */
1570 db[ldesc].db.desc.depend = db[0].db.desc.depend =
1571 ((struct fwohcidb_tr *)
1572 (chunk->start))->bus_addr | dbch->ndesc;
1573 #else
1574 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc);
1575 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc);
1576 #endif
1577 }
1578 STAILQ_REMOVE_HEAD(&it->stvalid, link);
1579 STAILQ_INSERT_TAIL(&it->stdma, chunk, link);
1580 prev = chunk;
1581 }
1582 FW_GUNLOCK(fc);
1583 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
1584 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD);
1585 splx(s);
1586 stat = OREAD(sc, OHCI_ITCTL(dmach));
1587 if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S))
1588 printf("stat 0x%x\n", stat);
1589
1590 if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S))
1591 return 0;
1592
1593 #if 0
1594 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1595 #endif
1596 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach);
1597 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach);
1598 OWRITE(sc, OHCI_IT_MASK, 1 << dmach);
1599 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT);
1600
1601 first = STAILQ_FIRST(&it->stdma);
1602 OWRITE(sc, OHCI_ITCMD(dmach),
1603 ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc);
1604 if (firewire_debug > 1) {
1605 printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat);
1606 #if 1
1607 dump_dma(sc, ITX_CH + dmach);
1608 #endif
1609 }
1610 if ((stat & OHCI_CNTL_DMA_RUN) == 0) {
1611 #if 1
1612 /* Don't start until all chunks are buffered */
1613 if (STAILQ_FIRST(&it->stfree) != NULL)
1614 goto out;
1615 #endif
1616 #if 1
1617 /* Clear cycle match counter bits */
1618 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000);
1619
1620 /* 2bit second + 13bit cycle */
1621 cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff;
1622 cycle_match = fwohci_next_cycle(fc, cycle_now);
1623
1624 OWRITE(sc, OHCI_ITCTL(dmach),
1625 OHCI_CNTL_CYCMATCH_S | (cycle_match << 16)
1626 | OHCI_CNTL_DMA_RUN);
1627 #else
1628 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN);
1629 #endif
1630 if (firewire_debug > 1) {
1631 printf("cycle_match: 0x%04x->0x%04x\n",
1632 cycle_now, cycle_match);
1633 dump_dma(sc, ITX_CH + dmach);
1634 dump_db(sc, ITX_CH + dmach);
1635 }
1636 } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) {
1637 device_printf(sc->fc.dev,
1638 "IT DMA underrun (0x%08x)\n", stat);
1639 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE);
1640 }
1641 out:
1642 return err;
1643 }
1644
1645 static int
1646 fwohci_irx_enable(struct firewire_comm *fc, int dmach)
1647 {
1648 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1649 int err = 0, s, ldesc;
1650 unsigned short tag, ich;
1651 uint32_t stat;
1652 struct fwohci_dbch *dbch;
1653 struct fwohcidb_tr *db_tr;
1654 struct fw_bulkxfer *first, *prev, *chunk;
1655 struct fw_xferq *ir;
1656
1657 dbch = &sc->ir[dmach];
1658 ir = &dbch->xferq;
1659
1660 if ((ir->flag & FWXFERQ_RUNNING) == 0) {
1661 tag = (ir->flag >> 6) & 3;
1662 ich = ir->flag & 0x3f;
1663 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich);
1664
1665 ir->queued = 0;
1666 dbch->ndb = ir->bnpacket * ir->bnchunk;
1667 dbch->ndesc = 2;
1668 fwohci_db_init(sc, dbch);
1669 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0)
1670 return ENOMEM;
1671 err = fwohci_rx_enable(sc, dbch);
1672 }
1673 if(err)
1674 return err;
1675
1676 first = STAILQ_FIRST(&ir->stfree);
1677 if (first == NULL) {
1678 device_printf(fc->dev, "IR DMA no free chunk\n");
1679 return 0;
1680 }
1681
1682 ldesc = dbch->ndesc - 1;
1683 s = splfw();
1684 if ((ir->flag & FWXFERQ_HANDLER) == 0)
1685 FW_GLOCK(fc);
1686 prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link);
1687 while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) {
1688 struct fwohcidb *db;
1689
1690 #if 1 /* XXX for if_fwe */
1691 if (chunk->mbuf != NULL) {
1692 db_tr = (struct fwohcidb_tr *)(chunk->start);
1693 db_tr->dbcnt = 1;
1694 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map,
1695 chunk->mbuf, fwohci_execute_db2, db_tr,
1696 /* flags */0);
1697 FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd,
1698 OHCI_UPDATE | OHCI_INPUT_LAST |
1699 OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS);
1700 }
1701 #endif
1702 db = ((struct fwohcidb_tr *)(chunk->end))->db;
1703 FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0);
1704 FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf);
1705 if (prev != NULL) {
1706 db = ((struct fwohcidb_tr *)(prev->end))->db;
1707 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc);
1708 }
1709 STAILQ_REMOVE_HEAD(&ir->stfree, link);
1710 STAILQ_INSERT_TAIL(&ir->stdma, chunk, link);
1711 prev = chunk;
1712 }
1713 if ((ir->flag & FWXFERQ_HANDLER) == 0)
1714 FW_GUNLOCK(fc);
1715 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
1716 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD);
1717 splx(s);
1718 stat = OREAD(sc, OHCI_IRCTL(dmach));
1719 if (stat & OHCI_CNTL_DMA_ACTIVE)
1720 return 0;
1721 if (stat & OHCI_CNTL_DMA_RUN) {
1722 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1723 device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat);
1724 }
1725
1726 if (firewire_debug)
1727 printf("start IR DMA 0x%x\n", stat);
1728 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach);
1729 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach);
1730 OWRITE(sc, OHCI_IR_MASK, 1 << dmach);
1731 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000);
1732 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR);
1733 OWRITE(sc, OHCI_IRCMD(dmach),
1734 ((struct fwohcidb_tr *)(first->start))->bus_addr
1735 | dbch->ndesc);
1736 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN);
1737 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR);
1738 #if 0
1739 dump_db(sc, IRX_CH + dmach);
1740 #endif
1741 return err;
1742 }
1743
1744 int
1745 fwohci_stop(struct fwohci_softc *sc, device_t dev)
1746 {
1747 u_int i;
1748
1749 fwohci_set_intr(&sc->fc, 0);
1750
1751 /* Now stopping all DMA channel */
1752 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN);
1753 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN);
1754 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
1755 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
1756
1757 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
1758 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN);
1759 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN);
1760 }
1761
1762 #if 0 /* Let dcons(4) be accessed */
1763 /* Stop interrupt */
1764 OWRITE(sc, FWOHCI_INTMASKCLR,
1765 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID
1766 | OHCI_INT_PHY_INT
1767 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS
1768 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS
1769 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS
1770 | OHCI_INT_PHY_BUS_R);
1771
1772 /* FLUSH FIFO and reset Transmitter/Reciever */
1773 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET);
1774 #endif
1775
1776 /* XXX Link down? Bus reset? */
1777 return 0;
1778 }
1779
1780 int
1781 fwohci_resume(struct fwohci_softc *sc, device_t dev)
1782 {
1783 int i;
1784 struct fw_xferq *ir;
1785 struct fw_bulkxfer *chunk;
1786
1787 fwohci_reset(sc, dev);
1788 /* XXX resume isochronous receive automatically. (how about TX?) */
1789 for(i = 0; i < sc->fc.nisodma; i ++) {
1790 ir = &sc->ir[i].xferq;
1791 if((ir->flag & FWXFERQ_RUNNING) != 0) {
1792 device_printf(sc->fc.dev,
1793 "resume iso receive ch: %d\n", i);
1794 ir->flag &= ~FWXFERQ_RUNNING;
1795 /* requeue stdma to stfree */
1796 while((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) {
1797 STAILQ_REMOVE_HEAD(&ir->stdma, link);
1798 STAILQ_INSERT_TAIL(&ir->stfree, chunk, link);
1799 }
1800 sc->fc.irx_enable(&sc->fc, i);
1801 }
1802 }
1803
1804 bus_generic_resume(dev);
1805 sc->fc.ibr(&sc->fc);
1806 return 0;
1807 }
1808
1809 #ifdef OHCI_DEBUG
1810 static void
1811 fwohci_dump_intr(struct fwohci_softc *sc, uint32_t stat)
1812 {
1813 if(stat & OREAD(sc, FWOHCI_INTMASK))
1814 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n",
1815 stat & OHCI_INT_EN ? "DMA_EN ":"",
1816 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"",
1817 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"",
1818 stat & OHCI_INT_ERR ? "INT_ERR ":"",
1819 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"",
1820 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"",
1821 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"",
1822 stat & OHCI_INT_CYC_START ? "CYC_START ":"",
1823 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"",
1824 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"",
1825 stat & OHCI_INT_PHY_SID ? "SID ":"",
1826 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"",
1827 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"",
1828 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"",
1829 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"",
1830 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"",
1831 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"",
1832 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"",
1833 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"",
1834 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"",
1835 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"",
1836 stat, OREAD(sc, FWOHCI_INTMASK)
1837 );
1838 }
1839 #endif
1840 static void
1841 fwohci_intr_core(struct fwohci_softc *sc, uint32_t stat, int count)
1842 {
1843 struct firewire_comm *fc = (struct firewire_comm *)sc;
1844 uintmax_t prequpper;
1845 uint32_t node_id, plen;
1846
1847 FW_GLOCK_ASSERT(fc);
1848 if ((stat & OHCI_INT_PHY_BUS_R) && (fc->status != FWBUSRESET)) {
1849 fc->status = FWBUSRESET;
1850 /* Disable bus reset interrupt until sid recv. */
1851 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R);
1852
1853 device_printf(fc->dev, "%s: BUS reset\n", __func__);
1854 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST);
1855 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC);
1856
1857 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
1858 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING;
1859 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
1860 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING;
1861
1862 if (!kdb_active)
1863 taskqueue_enqueue(sc->fc.taskqueue, &sc->fwohci_task_busreset);
1864 }
1865 if (stat & OHCI_INT_PHY_SID) {
1866 /* Enable bus reset interrupt */
1867 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R);
1868 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R);
1869
1870 /* Allow async. request to us */
1871 OWRITE(sc, OHCI_AREQHI, 1 << 31);
1872 if (firewire_phydma_enable) {
1873 /* allow from all nodes */
1874 OWRITE(sc, OHCI_PREQHI, 0x7fffffff);
1875 OWRITE(sc, OHCI_PREQLO, 0xffffffff);
1876 prequpper = ((uintmax_t)Maxmem << PAGE_SHIFT) >> 16;
1877 if (prequpper > OHCI_PREQUPPER_MAX) {
1878 device_printf(fc->dev,
1879 "Physical memory size of 0x%jx exceeds "
1880 "fire wire address space. Limiting dma "
1881 "to memory below 0x%jx\n",
1882 (uintmax_t)Maxmem << PAGE_SHIFT,
1883 (uintmax_t)OHCI_PREQUPPER_MAX << 16);
1884 prequpper = OHCI_PREQUPPER_MAX;
1885 }
1886 OWRITE(sc, OHCI_PREQUPPER, prequpper & 0xffffffff);
1887 if (OREAD(sc, OHCI_PREQUPPER) !=
1888 (prequpper & 0xffffffff)) {
1889 device_printf(fc->dev,
1890 "PhysicalUpperBound register is not "
1891 "implemented. Physical memory access "
1892 "is limited to the first 4GB\n");
1893 device_printf(fc->dev,
1894 "PhysicalUpperBound = 0x%08x\n",
1895 OREAD(sc, OHCI_PREQUPPER));
1896 }
1897 }
1898 /* Set ATRetries register */
1899 OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff);
1900
1901 /*
1902 * Checking whether the node is root or not. If root, turn on
1903 * cycle master.
1904 */
1905 node_id = OREAD(sc, FWOHCI_NODEID);
1906 plen = OREAD(sc, OHCI_SID_CNT);
1907
1908 fc->nodeid = node_id & 0x3f;
1909 device_printf(fc->dev, "%s: node_id=0x%08x, SelfID Count=%d, ",
1910 __func__, fc->nodeid, (plen >> 16) & 0xff);
1911 if (!(node_id & OHCI_NODE_VALID)) {
1912 device_printf(fc->dev, "%s: Bus reset failure\n",
1913 __func__);
1914 goto sidout;
1915 }
1916
1917 /* cycle timer */
1918 sc->cycle_lost = 0;
1919 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_CYC_LOST);
1920 if ((node_id & OHCI_NODE_ROOT) && !nocyclemaster) {
1921 printf("CYCLEMASTER mode\n");
1922 OWRITE(sc, OHCI_LNKCTL,
1923 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER);
1924 } else {
1925 printf("non CYCLEMASTER mode\n");
1926 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR);
1927 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER);
1928 }
1929
1930 fc->status = FWBUSINIT;
1931
1932 if (!kdb_active)
1933 taskqueue_enqueue(sc->fc.taskqueue, &sc->fwohci_task_sid);
1934 }
1935 sidout:
1936 if ((stat & ~(OHCI_INT_PHY_BUS_R | OHCI_INT_PHY_SID)) && (!kdb_active))
1937 taskqueue_enqueue(sc->fc.taskqueue, &sc->fwohci_task_dma);
1938 }
1939
1940 static void
1941 fwohci_intr_dma(struct fwohci_softc *sc, uint32_t stat, int count)
1942 {
1943 uint32_t irstat, itstat;
1944 u_int i;
1945 struct firewire_comm *fc = (struct firewire_comm *)sc;
1946
1947 if (stat & OHCI_INT_DMA_IR) {
1948 irstat = atomic_readandclear_int(&sc->irstat);
1949 for(i = 0; i < fc->nisodma ; i++){
1950 struct fwohci_dbch *dbch;
1951
1952 if((irstat & (1 << i)) != 0){
1953 dbch = &sc->ir[i];
1954 if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) {
1955 device_printf(sc->fc.dev,
1956 "dma(%d) not active\n", i);
1957 continue;
1958 }
1959 fwohci_rbuf_update(sc, i);
1960 }
1961 }
1962 }
1963 if (stat & OHCI_INT_DMA_IT) {
1964 itstat = atomic_readandclear_int(&sc->itstat);
1965 for(i = 0; i < fc->nisodma ; i++){
1966 if((itstat & (1 << i)) != 0){
1967 fwohci_tbuf_update(sc, i);
1968 }
1969 }
1970 }
1971 if (stat & OHCI_INT_DMA_PRRS) {
1972 #if 0
1973 dump_dma(sc, ARRS_CH);
1974 dump_db(sc, ARRS_CH);
1975 #endif
1976 fwohci_arcv(sc, &sc->arrs, count);
1977 }
1978 if (stat & OHCI_INT_DMA_PRRQ) {
1979 #if 0
1980 dump_dma(sc, ARRQ_CH);
1981 dump_db(sc, ARRQ_CH);
1982 #endif
1983 fwohci_arcv(sc, &sc->arrq, count);
1984 }
1985 if (stat & OHCI_INT_CYC_LOST) {
1986 if (sc->cycle_lost >= 0)
1987 sc->cycle_lost ++;
1988 if (sc->cycle_lost > 10) {
1989 sc->cycle_lost = -1;
1990 #if 0
1991 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCTIMER);
1992 #endif
1993 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST);
1994 device_printf(fc->dev, "too many cycles lost, "
1995 "no cycle master present?\n");
1996 }
1997 }
1998 if (stat & OHCI_INT_DMA_ATRQ) {
1999 fwohci_txd(sc, &(sc->atrq));
2000 }
2001 if (stat & OHCI_INT_DMA_ATRS) {
2002 fwohci_txd(sc, &(sc->atrs));
2003 }
2004 if (stat & OHCI_INT_PW_ERR) {
2005 device_printf(fc->dev, "posted write error\n");
2006 }
2007 if (stat & OHCI_INT_ERR) {
2008 device_printf(fc->dev, "unrecoverable error\n");
2009 }
2010 if (stat & OHCI_INT_PHY_INT) {
2011 device_printf(fc->dev, "phy int\n");
2012 }
2013
2014 return;
2015 }
2016
2017 static void
2018 fwohci_task_busreset(void *arg, int pending)
2019 {
2020 struct fwohci_softc *sc = (struct fwohci_softc *)arg;
2021
2022 FW_GLOCK(&sc->fc);
2023 fw_busreset(&sc->fc, FWBUSRESET);
2024 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0]));
2025 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2]));
2026 FW_GUNLOCK(&sc->fc);
2027 }
2028
2029 static void
2030 fwohci_task_sid(void *arg, int pending)
2031 {
2032 struct fwohci_softc *sc = (struct fwohci_softc *)arg;
2033 struct firewire_comm *fc = &sc->fc;
2034 uint32_t *buf;
2035 int i, plen;
2036
2037
2038 /*
2039 * We really should have locking
2040 * here. Not sure why it's not
2041 */
2042 plen = OREAD(sc, OHCI_SID_CNT);
2043
2044 if (plen & OHCI_SID_ERR) {
2045 device_printf(fc->dev, "SID Error\n");
2046 return;
2047 }
2048 plen &= OHCI_SID_CNT_MASK;
2049 if (plen < 4 || plen > OHCI_SIDSIZE) {
2050 device_printf(fc->dev, "invalid SID len = %d\n", plen);
2051 return;
2052 }
2053 plen -= 4; /* chop control info */
2054 buf = (uint32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT);
2055 if (buf == NULL) {
2056 device_printf(fc->dev, "malloc failed\n");
2057 return;
2058 }
2059 for (i = 0; i < plen / 4; i ++)
2060 buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]);
2061
2062 /* pending all pre-bus_reset packets */
2063 fwohci_txd(sc, &sc->atrq);
2064 fwohci_txd(sc, &sc->atrs);
2065 fwohci_arcv(sc, &sc->arrs, -1);
2066 fwohci_arcv(sc, &sc->arrq, -1);
2067 fw_drain_txq(fc);
2068 fw_sidrcv(fc, buf, plen);
2069 free(buf, M_FW);
2070 }
2071
2072 static void
2073 fwohci_task_dma(void *arg, int pending)
2074 {
2075 struct fwohci_softc *sc = (struct fwohci_softc *)arg;
2076 uint32_t stat;
2077
2078 again:
2079 stat = atomic_readandclear_int(&sc->intstat);
2080 if (stat)
2081 fwohci_intr_dma(sc, stat, -1);
2082 else
2083 return;
2084 goto again;
2085 }
2086
2087 static int
2088 fwohci_check_stat(struct fwohci_softc *sc)
2089 {
2090 uint32_t stat, irstat, itstat;
2091
2092 FW_GLOCK_ASSERT(&sc->fc);
2093 stat = OREAD(sc, FWOHCI_INTSTAT);
2094 if (stat == 0xffffffff) {
2095 if (!bus_child_present(sc->fc.dev))
2096 return (FILTER_HANDLED);
2097 device_printf(sc->fc.dev, "device physically ejected?\n");
2098 return (FILTER_STRAY);
2099 }
2100 if (stat)
2101 OWRITE(sc, FWOHCI_INTSTATCLR, stat & ~OHCI_INT_PHY_BUS_R);
2102
2103 stat &= sc->intmask;
2104 if (stat == 0)
2105 return (FILTER_STRAY);
2106
2107 atomic_set_int(&sc->intstat, stat);
2108 if (stat & OHCI_INT_DMA_IR) {
2109 irstat = OREAD(sc, OHCI_IR_STAT);
2110 OWRITE(sc, OHCI_IR_STATCLR, irstat);
2111 atomic_set_int(&sc->irstat, irstat);
2112 }
2113 if (stat & OHCI_INT_DMA_IT) {
2114 itstat = OREAD(sc, OHCI_IT_STAT);
2115 OWRITE(sc, OHCI_IT_STATCLR, itstat);
2116 atomic_set_int(&sc->itstat, itstat);
2117 }
2118
2119 fwohci_intr_core(sc, stat, -1);
2120 return (FILTER_HANDLED);
2121 }
2122
2123 void
2124 fwohci_intr(void *arg)
2125 {
2126 struct fwohci_softc *sc = (struct fwohci_softc *)arg;
2127
2128 FW_GLOCK(&sc->fc);
2129 fwohci_check_stat(sc);
2130 FW_GUNLOCK(&sc->fc);
2131 }
2132
2133 void
2134 fwohci_poll(struct firewire_comm *fc, int quick, int count)
2135 {
2136 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
2137
2138 FW_GLOCK(fc);
2139 fwohci_check_stat(sc);
2140 FW_GUNLOCK(fc);
2141 }
2142
2143 static void
2144 fwohci_set_intr(struct firewire_comm *fc, int enable)
2145 {
2146 struct fwohci_softc *sc;
2147
2148 sc = (struct fwohci_softc *)fc;
2149 if (firewire_debug)
2150 device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable);
2151 if (enable) {
2152 sc->intmask |= OHCI_INT_EN;
2153 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN);
2154 } else {
2155 sc->intmask &= ~OHCI_INT_EN;
2156 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN);
2157 }
2158 }
2159
2160 static void
2161 fwohci_tbuf_update(struct fwohci_softc *sc, int dmach)
2162 {
2163 struct firewire_comm *fc = &sc->fc;
2164 struct fwohcidb *db;
2165 struct fw_bulkxfer *chunk;
2166 struct fw_xferq *it;
2167 uint32_t stat, count;
2168 int s, w=0, ldesc;
2169
2170 it = fc->it[dmach];
2171 ldesc = sc->it[dmach].ndesc - 1;
2172 s = splfw(); /* unnecessary ? */
2173 FW_GLOCK(fc);
2174 fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD);
2175 if (firewire_debug)
2176 dump_db(sc, ITX_CH + dmach);
2177 while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) {
2178 db = ((struct fwohcidb_tr *)(chunk->end))->db;
2179 stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res)
2180 >> OHCI_STATUS_SHIFT;
2181 db = ((struct fwohcidb_tr *)(chunk->start))->db;
2182 /* timestamp */
2183 count = FWOHCI_DMA_READ(db[ldesc].db.desc.res)
2184 & OHCI_COUNT_MASK;
2185 if (stat == 0)
2186 break;
2187 STAILQ_REMOVE_HEAD(&it->stdma, link);
2188 switch (stat & FWOHCIEV_MASK){
2189 case FWOHCIEV_ACKCOMPL:
2190 #if 0
2191 device_printf(fc->dev, "0x%08x\n", count);
2192 #endif
2193 break;
2194 default:
2195 device_printf(fc->dev,
2196 "Isochronous transmit err %02x(%s)\n",
2197 stat, fwohcicode[stat & 0x1f]);
2198 }
2199 STAILQ_INSERT_TAIL(&it->stfree, chunk, link);
2200 w++;
2201 }
2202 FW_GUNLOCK(fc);
2203 splx(s);
2204 if (w)
2205 wakeup(it);
2206 }
2207
2208 static void
2209 fwohci_rbuf_update(struct fwohci_softc *sc, int dmach)
2210 {
2211 struct firewire_comm *fc = &sc->fc;
2212 struct fwohcidb_tr *db_tr;
2213 struct fw_bulkxfer *chunk;
2214 struct fw_xferq *ir;
2215 uint32_t stat;
2216 int w = 0, ldesc;
2217
2218 ir = fc->ir[dmach];
2219 ldesc = sc->ir[dmach].ndesc - 1;
2220
2221 #if 0
2222 dump_db(sc, dmach);
2223 #endif
2224 if ((ir->flag & FWXFERQ_HANDLER) == 0)
2225 FW_GLOCK(fc);
2226 fwdma_sync_multiseg_all(sc->ir[dmach].am, BUS_DMASYNC_POSTREAD);
2227 while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) {
2228 db_tr = (struct fwohcidb_tr *)chunk->end;
2229 stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res)
2230 >> OHCI_STATUS_SHIFT;
2231 if (stat == 0)
2232 break;
2233
2234 if (chunk->mbuf != NULL) {
2235 bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map,
2236 BUS_DMASYNC_POSTREAD);
2237 bus_dmamap_unload(sc->ir[dmach].dmat, db_tr->dma_map);
2238 } else if (ir->buf != NULL) {
2239 fwdma_sync_multiseg(ir->buf, chunk->poffset,
2240 ir->bnpacket, BUS_DMASYNC_POSTREAD);
2241 } else {
2242 /* XXX */
2243 printf("fwohci_rbuf_update: this shouldn't happend\n");
2244 }
2245
2246 STAILQ_REMOVE_HEAD(&ir->stdma, link);
2247 STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link);
2248 switch (stat & FWOHCIEV_MASK) {
2249 case FWOHCIEV_ACKCOMPL:
2250 chunk->resp = 0;
2251 break;
2252 default:
2253 chunk->resp = EINVAL;
2254 device_printf(fc->dev,
2255 "Isochronous receive err %02x(%s)\n",
2256 stat, fwohcicode[stat & 0x1f]);
2257 }
2258 w++;
2259 }
2260 if ((ir->flag & FWXFERQ_HANDLER) == 0)
2261 FW_GUNLOCK(fc);
2262 if (w == 0)
2263 return;
2264
2265 if (ir->flag & FWXFERQ_HANDLER)
2266 ir->hand(ir);
2267 else
2268 wakeup(ir);
2269 }
2270
2271 void
2272 dump_dma(struct fwohci_softc *sc, uint32_t ch)
2273 {
2274 uint32_t off, cntl, stat, cmd, match;
2275
2276 if(ch == 0){
2277 off = OHCI_ATQOFF;
2278 }else if(ch == 1){
2279 off = OHCI_ATSOFF;
2280 }else if(ch == 2){
2281 off = OHCI_ARQOFF;
2282 }else if(ch == 3){
2283 off = OHCI_ARSOFF;
2284 }else if(ch < IRX_CH){
2285 off = OHCI_ITCTL(ch - ITX_CH);
2286 }else{
2287 off = OHCI_IRCTL(ch - IRX_CH);
2288 }
2289 cntl = stat = OREAD(sc, off);
2290 cmd = OREAD(sc, off + 0xc);
2291 match = OREAD(sc, off + 0x10);
2292
2293 device_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n",
2294 ch,
2295 cntl,
2296 cmd,
2297 match);
2298 stat &= 0xffff ;
2299 if (stat) {
2300 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n",
2301 ch,
2302 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "",
2303 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "",
2304 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "",
2305 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "",
2306 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "",
2307 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "",
2308 fwohcicode[stat & 0x1f],
2309 stat & 0x1f
2310 );
2311 }else{
2312 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch);
2313 }
2314 }
2315
2316 void
2317 dump_db(struct fwohci_softc *sc, uint32_t ch)
2318 {
2319 struct fwohci_dbch *dbch;
2320 struct fwohcidb_tr *cp = NULL, *pp, *np = NULL;
2321 struct fwohcidb *curr = NULL, *prev, *next = NULL;
2322 int idb, jdb;
2323 uint32_t cmd, off;
2324 if(ch == 0){
2325 off = OHCI_ATQOFF;
2326 dbch = &sc->atrq;
2327 }else if(ch == 1){
2328 off = OHCI_ATSOFF;
2329 dbch = &sc->atrs;
2330 }else if(ch == 2){
2331 off = OHCI_ARQOFF;
2332 dbch = &sc->arrq;
2333 }else if(ch == 3){
2334 off = OHCI_ARSOFF;
2335 dbch = &sc->arrs;
2336 }else if(ch < IRX_CH){
2337 off = OHCI_ITCTL(ch - ITX_CH);
2338 dbch = &sc->it[ch - ITX_CH];
2339 }else {
2340 off = OHCI_IRCTL(ch - IRX_CH);
2341 dbch = &sc->ir[ch - IRX_CH];
2342 }
2343 cmd = OREAD(sc, off + 0xc);
2344
2345 if( dbch->ndb == 0 ){
2346 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch);
2347 return;
2348 }
2349 pp = dbch->top;
2350 prev = pp->db;
2351 for(idb = 0 ; idb < dbch->ndb ; idb ++ ){
2352 cp = STAILQ_NEXT(pp, link);
2353 if(cp == NULL){
2354 curr = NULL;
2355 goto outdb;
2356 }
2357 np = STAILQ_NEXT(cp, link);
2358 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){
2359 if ((cmd & 0xfffffff0) == cp->bus_addr) {
2360 curr = cp->db;
2361 if(np != NULL){
2362 next = np->db;
2363 }else{
2364 next = NULL;
2365 }
2366 goto outdb;
2367 }
2368 }
2369 pp = STAILQ_NEXT(pp, link);
2370 if(pp == NULL){
2371 curr = NULL;
2372 goto outdb;
2373 }
2374 prev = pp->db;
2375 }
2376 outdb:
2377 if( curr != NULL){
2378 #if 0
2379 printf("Prev DB %d\n", ch);
2380 print_db(pp, prev, ch, dbch->ndesc);
2381 #endif
2382 printf("Current DB %d\n", ch);
2383 print_db(cp, curr, ch, dbch->ndesc);
2384 #if 0
2385 printf("Next DB %d\n", ch);
2386 print_db(np, next, ch, dbch->ndesc);
2387 #endif
2388 }else{
2389 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd);
2390 }
2391 return;
2392 }
2393
2394 void
2395 print_db(struct fwohcidb_tr *db_tr, struct fwohcidb *db,
2396 uint32_t ch, uint32_t max)
2397 {
2398 fwohcireg_t stat;
2399 int i, key;
2400 uint32_t cmd, res;
2401
2402 if(db == NULL){
2403 printf("No Descriptor is found\n");
2404 return;
2405 }
2406
2407 printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n",
2408 ch,
2409 "Current",
2410 "OP ",
2411 "KEY",
2412 "INT",
2413 "BR ",
2414 "len",
2415 "Addr",
2416 "Depend",
2417 "Stat",
2418 "Cnt");
2419 for( i = 0 ; i <= max ; i ++){
2420 cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd);
2421 res = FWOHCI_DMA_READ(db[i].db.desc.res);
2422 key = cmd & OHCI_KEY_MASK;
2423 stat = res >> OHCI_STATUS_SHIFT;
2424 #if defined(__DragonFly__) || __FreeBSD_version < 500000
2425 printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x",
2426 db_tr->bus_addr,
2427 #else
2428 printf("%08jx %s %s %s %s %5d %08x %08x %04x:%04x",
2429 (uintmax_t)db_tr->bus_addr,
2430 #endif
2431 dbcode[(cmd >> 28) & 0xf],
2432 dbkey[(cmd >> 24) & 0x7],
2433 dbcond[(cmd >> 20) & 0x3],
2434 dbcond[(cmd >> 18) & 0x3],
2435 cmd & OHCI_COUNT_MASK,
2436 FWOHCI_DMA_READ(db[i].db.desc.addr),
2437 FWOHCI_DMA_READ(db[i].db.desc.depend),
2438 stat,
2439 res & OHCI_COUNT_MASK);
2440 if(stat & 0xff00){
2441 printf(" %s%s%s%s%s%s %s(%x)\n",
2442 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "",
2443 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "",
2444 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "",
2445 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "",
2446 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "",
2447 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "",
2448 fwohcicode[stat & 0x1f],
2449 stat & 0x1f
2450 );
2451 }else{
2452 printf(" Nostat\n");
2453 }
2454 if(key == OHCI_KEY_ST2 ){
2455 printf("0x%08x 0x%08x 0x%08x 0x%08x\n",
2456 FWOHCI_DMA_READ(db[i+1].db.immed[0]),
2457 FWOHCI_DMA_READ(db[i+1].db.immed[1]),
2458 FWOHCI_DMA_READ(db[i+1].db.immed[2]),
2459 FWOHCI_DMA_READ(db[i+1].db.immed[3]));
2460 }
2461 if(key == OHCI_KEY_DEVICE){
2462 return;
2463 }
2464 if((cmd & OHCI_BRANCH_MASK)
2465 == OHCI_BRANCH_ALWAYS){
2466 return;
2467 }
2468 if((cmd & OHCI_CMD_MASK)
2469 == OHCI_OUTPUT_LAST){
2470 return;
2471 }
2472 if((cmd & OHCI_CMD_MASK)
2473 == OHCI_INPUT_LAST){
2474 return;
2475 }
2476 if(key == OHCI_KEY_ST2 ){
2477 i++;
2478 }
2479 }
2480 return;
2481 }
2482
2483 void
2484 fwohci_ibr(struct firewire_comm *fc)
2485 {
2486 struct fwohci_softc *sc;
2487 uint32_t fun;
2488
2489 device_printf(fc->dev, "Initiate bus reset\n");
2490 sc = (struct fwohci_softc *)fc;
2491
2492 FW_GLOCK(fc);
2493 /*
2494 * Make sure our cached values from the config rom are
2495 * initialised.
2496 */
2497 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0]));
2498 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2]));
2499
2500 /*
2501 * Set root hold-off bit so that non cyclemaster capable node
2502 * shouldn't became the root node.
2503 */
2504 #if 1
2505 fun = fwphy_rddata(sc, FW_PHY_IBR_REG);
2506 fun |= FW_PHY_IBR | FW_PHY_RHB;
2507 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun);
2508 #else /* Short bus reset */
2509 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG);
2510 fun |= FW_PHY_ISBR | FW_PHY_RHB;
2511 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun);
2512 #endif
2513 FW_GUNLOCK(fc);
2514 }
2515
2516 void
2517 fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer)
2518 {
2519 struct fwohcidb_tr *db_tr, *fdb_tr;
2520 struct fwohci_dbch *dbch;
2521 struct fwohcidb *db;
2522 struct fw_pkt *fp;
2523 struct fwohci_txpkthdr *ohcifp;
2524 unsigned short chtag;
2525 int idb;
2526
2527 FW_GLOCK_ASSERT(&sc->fc);
2528
2529 dbch = &sc->it[dmach];
2530 chtag = sc->it[dmach].xferq.flag & 0xff;
2531
2532 db_tr = (struct fwohcidb_tr *)(bulkxfer->start);
2533 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end);
2534 /*
2535 device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr);
2536 */
2537 for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) {
2538 db = db_tr->db;
2539 fp = (struct fw_pkt *)db_tr->buf;
2540 ohcifp = (struct fwohci_txpkthdr *) db[1].db.immed;
2541 ohcifp->mode.ld[0] = fp->mode.ld[0];
2542 ohcifp->mode.common.spd = 0 & 0x7;
2543 ohcifp->mode.stream.len = fp->mode.stream.len;
2544 ohcifp->mode.stream.chtag = chtag;
2545 ohcifp->mode.stream.tcode = 0xa;
2546 #if BYTE_ORDER == BIG_ENDIAN
2547 FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]);
2548 FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]);
2549 #endif
2550
2551 FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK);
2552 FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len);
2553 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0);
2554 #if 0 /* if bulkxfer->npackets changes */
2555 db[2].db.desc.cmd = OHCI_OUTPUT_LAST
2556 | OHCI_UPDATE
2557 | OHCI_BRANCH_ALWAYS;
2558 db[0].db.desc.depend =
2559 = db[dbch->ndesc - 1].db.desc.depend
2560 = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc;
2561 #else
2562 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc);
2563 FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc);
2564 #endif
2565 bulkxfer->end = (caddr_t)db_tr;
2566 db_tr = STAILQ_NEXT(db_tr, link);
2567 }
2568 db = ((struct fwohcidb_tr *)bulkxfer->end)->db;
2569 FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf);
2570 FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf);
2571 #if 0 /* if bulkxfer->npackets changes */
2572 db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS;
2573 /* OHCI 1.1 and above */
2574 db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS;
2575 #endif
2576 /*
2577 db_tr = (struct fwohcidb_tr *)bulkxfer->start;
2578 fdb_tr = (struct fwohcidb_tr *)bulkxfer->end;
2579 device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr);
2580 */
2581 return;
2582 }
2583
2584 static int
2585 fwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr,
2586 int poffset)
2587 {
2588 struct fwohcidb *db = db_tr->db;
2589 struct fw_xferq *it;
2590 int err = 0;
2591
2592 it = &dbch->xferq;
2593 if(it->buf == 0){
2594 err = EINVAL;
2595 return err;
2596 }
2597 db_tr->buf = fwdma_v_addr(it->buf, poffset);
2598 db_tr->dbcnt = 3;
2599
2600 FWOHCI_DMA_WRITE(db[0].db.desc.cmd,
2601 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8);
2602 FWOHCI_DMA_WRITE(db[0].db.desc.addr, 0);
2603 bzero((void *)&db[1].db.immed[0], sizeof(db[1].db.immed));
2604 FWOHCI_DMA_WRITE(db[2].db.desc.addr,
2605 fwdma_bus_addr(it->buf, poffset) + sizeof(uint32_t));
2606
2607 FWOHCI_DMA_WRITE(db[2].db.desc.cmd,
2608 OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS);
2609 #if 1
2610 FWOHCI_DMA_WRITE(db[0].db.desc.res, 0);
2611 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0);
2612 #endif
2613 return 0;
2614 }
2615
2616 int
2617 fwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr,
2618 int poffset, struct fwdma_alloc *dummy_dma)
2619 {
2620 struct fwohcidb *db = db_tr->db;
2621 struct fw_xferq *ir;
2622 int i, ldesc;
2623 bus_addr_t dbuf[2];
2624 int dsiz[2];
2625
2626 ir = &dbch->xferq;
2627 if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) {
2628 if (db_tr->buf == NULL) {
2629 db_tr->buf = fwdma_malloc_size(dbch->dmat,
2630 &db_tr->dma_map, ir->psize, &dbuf[0],
2631 BUS_DMA_NOWAIT);
2632 if (db_tr->buf == NULL)
2633 return(ENOMEM);
2634 }
2635 db_tr->dbcnt = 1;
2636 dsiz[0] = ir->psize;
2637 bus_dmamap_sync(dbch->dmat, db_tr->dma_map,
2638 BUS_DMASYNC_PREREAD);
2639 } else {
2640 db_tr->dbcnt = 0;
2641 if (dummy_dma != NULL) {
2642 dsiz[db_tr->dbcnt] = sizeof(uint32_t);
2643 dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr;
2644 }
2645 dsiz[db_tr->dbcnt] = ir->psize;
2646 if (ir->buf != NULL) {
2647 db_tr->buf = fwdma_v_addr(ir->buf, poffset);
2648 dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset);
2649 }
2650 db_tr->dbcnt++;
2651 }
2652 for(i = 0 ; i < db_tr->dbcnt ; i++){
2653 FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]);
2654 FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]);
2655 if (ir->flag & FWXFERQ_STREAM) {
2656 FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE);
2657 }
2658 FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]);
2659 }
2660 ldesc = db_tr->dbcnt - 1;
2661 if (ir->flag & FWXFERQ_STREAM) {
2662 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST);
2663 }
2664 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS);
2665 return 0;
2666 }
2667
2668
2669 static int
2670 fwohci_arcv_swap(struct fw_pkt *fp, int len)
2671 {
2672 struct fw_pkt *fp0;
2673 uint32_t ld0;
2674 int slen, hlen;
2675 #if BYTE_ORDER == BIG_ENDIAN
2676 int i;
2677 #endif
2678
2679 ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]);
2680 #if 0
2681 printf("ld0: x%08x\n", ld0);
2682 #endif
2683 fp0 = (struct fw_pkt *)&ld0;
2684 /* determine length to swap */
2685 switch (fp0->mode.common.tcode) {
2686 case FWTCODE_RREQQ:
2687 case FWTCODE_WRES:
2688 case FWTCODE_WREQQ:
2689 case FWTCODE_RRESQ:
2690 case FWOHCITCODE_PHY:
2691 slen = 12;
2692 break;
2693 case FWTCODE_RREQB:
2694 case FWTCODE_WREQB:
2695 case FWTCODE_LREQ:
2696 case FWTCODE_RRESB:
2697 case FWTCODE_LRES:
2698 slen = 16;
2699 break;
2700 default:
2701 printf("Unknown tcode %d\n", fp0->mode.common.tcode);
2702 return(0);
2703 }
2704 hlen = tinfo[fp0->mode.common.tcode].hdr_len;
2705 if (hlen > len) {
2706 if (firewire_debug)
2707 printf("splitted header\n");
2708 return(-hlen);
2709 }
2710 #if BYTE_ORDER == BIG_ENDIAN
2711 for(i = 0; i < slen/4; i ++)
2712 fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]);
2713 #endif
2714 return(hlen);
2715 }
2716
2717 static int
2718 fwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp)
2719 {
2720 struct tcode_info *info;
2721 int r;
2722
2723 info = &tinfo[fp->mode.common.tcode];
2724 r = info->hdr_len + sizeof(uint32_t);
2725 if ((info->flag & FWTI_BLOCK_ASY) != 0)
2726 r += roundup2(fp->mode.wreqb.len, sizeof(uint32_t));
2727
2728 if (r == sizeof(uint32_t)) {
2729 /* XXX */
2730 device_printf(sc->fc.dev, "Unknown tcode %d\n",
2731 fp->mode.common.tcode);
2732 return (-1);
2733 }
2734
2735 if (r > dbch->xferq.psize) {
2736 device_printf(sc->fc.dev, "Invalid packet length %d\n", r);
2737 return (-1);
2738 /* panic ? */
2739 }
2740
2741 return r;
2742 }
2743
2744 static void
2745 fwohci_arcv_free_buf(struct fwohci_softc *sc, struct fwohci_dbch *dbch,
2746 struct fwohcidb_tr *db_tr, uint32_t off, int wake)
2747 {
2748 struct fwohcidb *db = &db_tr->db[0];
2749
2750 FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf);
2751 FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize);
2752 FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1);
2753 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
2754 dbch->bottom = db_tr;
2755
2756 if (wake)
2757 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE);
2758 }
2759
2760 static void
2761 fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count)
2762 {
2763 struct fwohcidb_tr *db_tr;
2764 struct iovec vec[2];
2765 struct fw_pkt pktbuf;
2766 int nvec;
2767 struct fw_pkt *fp;
2768 uint8_t *ld;
2769 uint32_t stat, off, status, event;
2770 u_int spd;
2771 int len, plen, hlen, pcnt, offset;
2772 int s;
2773 caddr_t buf;
2774 int resCount;
2775
2776 if(&sc->arrq == dbch){
2777 off = OHCI_ARQOFF;
2778 }else if(&sc->arrs == dbch){
2779 off = OHCI_ARSOFF;
2780 }else{
2781 return;
2782 }
2783
2784 s = splfw();
2785 db_tr = dbch->top;
2786 pcnt = 0;
2787 /* XXX we cannot handle a packet which lies in more than two buf */
2788 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD);
2789 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE);
2790 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT;
2791 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK;
2792 while (status & OHCI_CNTL_DMA_ACTIVE) {
2793 #if 0
2794
2795 if (off == OHCI_ARQOFF)
2796 printf("buf 0x%08x, status 0x%04x, resCount 0x%04x\n",
2797 db_tr->bus_addr, status, resCount);
2798 #endif
2799 len = dbch->xferq.psize - resCount;
2800 ld = (uint8_t *)db_tr->buf;
2801 if (dbch->pdb_tr == NULL) {
2802 len -= dbch->buf_offset;
2803 ld += dbch->buf_offset;
2804 }
2805 if (len > 0)
2806 bus_dmamap_sync(dbch->dmat, db_tr->dma_map,
2807 BUS_DMASYNC_POSTREAD);
2808 while (len > 0 ) {
2809 if (count >= 0 && count-- == 0)
2810 goto out;
2811 if(dbch->pdb_tr != NULL){
2812 /* we have a fragment in previous buffer */
2813 int rlen;
2814
2815 offset = dbch->buf_offset;
2816 if (offset < 0)
2817 offset = - offset;
2818 buf = dbch->pdb_tr->buf + offset;
2819 rlen = dbch->xferq.psize - offset;
2820 if (firewire_debug)
2821 printf("rlen=%d, offset=%d\n",
2822 rlen, dbch->buf_offset);
2823 if (dbch->buf_offset < 0) {
2824 /* splitted in header, pull up */
2825 char *p;
2826
2827 p = (char *)&pktbuf;
2828 bcopy(buf, p, rlen);
2829 p += rlen;
2830 /* this must be too long but harmless */
2831 rlen = sizeof(pktbuf) - rlen;
2832 if (rlen < 0)
2833 printf("why rlen < 0\n");
2834 bcopy(db_tr->buf, p, rlen);
2835 ld += rlen;
2836 len -= rlen;
2837 hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf));
2838 if (hlen <= 0) {
2839 printf("hlen should be positive.");
2840 goto err;
2841 }
2842 offset = sizeof(pktbuf);
2843 vec[0].iov_base = (char *)&pktbuf;
2844 vec[0].iov_len = offset;
2845 } else {
2846 /* splitted in payload */
2847 offset = rlen;
2848 vec[0].iov_base = buf;
2849 vec[0].iov_len = rlen;
2850 }
2851 fp=(struct fw_pkt *)vec[0].iov_base;
2852 nvec = 1;
2853 } else {
2854 /* no fragment in previous buffer */
2855 fp=(struct fw_pkt *)ld;
2856 hlen = fwohci_arcv_swap(fp, len);
2857 if (hlen == 0)
2858 goto err;
2859 if (hlen < 0) {
2860 dbch->pdb_tr = db_tr;
2861 dbch->buf_offset = - dbch->buf_offset;
2862 /* sanity check */
2863 if (resCount != 0) {
2864 printf("resCount=%d hlen=%d\n",
2865 resCount, hlen);
2866 goto err;
2867 }
2868 goto out;
2869 }
2870 offset = 0;
2871 nvec = 0;
2872 }
2873 plen = fwohci_get_plen(sc, dbch, fp) - offset;
2874 if (plen < 0) {
2875 /* minimum header size + trailer
2876 = sizeof(fw_pkt) so this shouldn't happens */
2877 printf("plen(%d) is negative! offset=%d\n",
2878 plen, offset);
2879 goto err;
2880 }
2881 if (plen > 0) {
2882 len -= plen;
2883 if (len < 0) {
2884 dbch->pdb_tr = db_tr;
2885 if (firewire_debug)
2886 printf("splitted payload\n");
2887 /* sanity check */
2888 if (resCount != 0) {
2889 printf("resCount=%d plen=%d"
2890 " len=%d\n",
2891 resCount, plen, len);
2892 goto err;
2893 }
2894 goto out;
2895 }
2896 vec[nvec].iov_base = ld;
2897 vec[nvec].iov_len = plen;
2898 nvec ++;
2899 ld += plen;
2900 }
2901 dbch->buf_offset = ld - (uint8_t *)db_tr->buf;
2902 if (nvec == 0)
2903 printf("nvec == 0\n");
2904
2905 /* DMA result-code will be written at the tail of packet */
2906 stat = FWOHCI_DMA_READ(*(uint32_t *)(ld - sizeof(struct fwohci_trailer)));
2907 #if 0
2908 printf("plen: %d, stat %x\n",
2909 plen ,stat);
2910 #endif
2911 spd = (stat >> 21) & 0x3;
2912 event = (stat >> 16) & 0x1f;
2913 switch (event) {
2914 case FWOHCIEV_ACKPEND:
2915 #if 0
2916 printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode);
2917 #endif
2918 /* fall through */
2919 case FWOHCIEV_ACKCOMPL:
2920 {
2921 struct fw_rcv_buf rb;
2922
2923 if ((vec[nvec-1].iov_len -=
2924 sizeof(struct fwohci_trailer)) == 0)
2925 nvec--;
2926 rb.fc = &sc->fc;
2927 rb.vec = vec;
2928 rb.nvec = nvec;
2929 rb.spd = spd;
2930 fw_rcv(&rb);
2931 break;
2932 }
2933 case FWOHCIEV_BUSRST:
2934 if ((sc->fc.status != FWBUSRESET) &&
2935 (sc->fc.status != FWBUSINIT))
2936 printf("got BUSRST packet!?\n");
2937 break;
2938 default:
2939 device_printf(sc->fc.dev,
2940 "Async DMA Receive error err=%02x %s"
2941 " plen=%d offset=%d len=%d status=0x%08x"
2942 " tcode=0x%x, stat=0x%08x\n",
2943 event, fwohcicode[event], plen,
2944 dbch->buf_offset, len,
2945 OREAD(sc, OHCI_DMACTL(off)),
2946 fp->mode.common.tcode, stat);
2947 #if 1 /* XXX */
2948 goto err;
2949 #endif
2950 break;
2951 }
2952 pcnt ++;
2953 if (dbch->pdb_tr != NULL) {
2954 fwohci_arcv_free_buf(sc, dbch, dbch->pdb_tr,
2955 off, 1);
2956 dbch->pdb_tr = NULL;
2957 }
2958
2959 }
2960 out:
2961 if (resCount == 0) {
2962 /* done on this buffer */
2963 if (dbch->pdb_tr == NULL) {
2964 fwohci_arcv_free_buf(sc, dbch, db_tr, off, 1);
2965 dbch->buf_offset = 0;
2966 } else
2967 if (dbch->pdb_tr != db_tr)
2968 printf("pdb_tr != db_tr\n");
2969 db_tr = STAILQ_NEXT(db_tr, link);
2970 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res)
2971 >> OHCI_STATUS_SHIFT;
2972 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res)
2973 & OHCI_COUNT_MASK;
2974 /* XXX check buffer overrun */
2975 dbch->top = db_tr;
2976 } else {
2977 dbch->buf_offset = dbch->xferq.psize - resCount;
2978 break;
2979 }
2980 /* XXX make sure DMA is not dead */
2981 }
2982 #if 0
2983 if (pcnt < 1)
2984 printf("fwohci_arcv: no packets\n");
2985 #endif
2986 splx(s);
2987 return;
2988
2989 err:
2990 device_printf(sc->fc.dev, "AR DMA status=%x, ",
2991 OREAD(sc, OHCI_DMACTL(off)));
2992 dbch->pdb_tr = NULL;
2993 /* skip until resCount != 0 */
2994 printf(" skip buffer");
2995 while (resCount == 0) {
2996 printf(" #");
2997 fwohci_arcv_free_buf(sc, dbch, db_tr, off, 0);
2998 db_tr = STAILQ_NEXT(db_tr, link);
2999 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res)
3000 & OHCI_COUNT_MASK;
3001 }
3002 printf(" done\n");
3003 dbch->top = db_tr;
3004 dbch->buf_offset = dbch->xferq.psize - resCount;
3005 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE);
3006 splx(s);
3007 }
3008