1 /*
2 * Copyright (c) 2004-2005 HighPoint Technologies, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: src/sys/dev/hptmv/entry.c,v 1.26 2012/06/01 04:34:49 eadler Exp $
27 */
28
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/kernel.h>
32 #include <sys/bus.h>
33 #include <sys/malloc.h>
34 #include <sys/resource.h>
35 #include <sys/time.h>
36 #include <sys/callout.h>
37 #include <sys/signalvar.h>
38 #include <sys/eventhandler.h>
39 #include <sys/proc.h>
40 #include <sys/kthread.h>
41
42 #include <sys/lock.h>
43 #include <sys/module.h>
44
45 #include <bus/pci/pcireg.h>
46 #include <bus/pci/pcivar.h>
47 #include <bus/cam/cam.h>
48 #include <bus/cam/cam_ccb.h>
49 #include <bus/cam/cam_xpt.h>
50 #include <bus/cam/cam_xpt_periph.h>
51
52 #ifndef __KERNEL__
53 #define __KERNEL__
54 #endif
55
56 #include <dev/raid/hptmv/global.h>
57 #include <dev/raid/hptmv/hptintf.h>
58 #include <dev/raid/hptmv/osbsd.h>
59 #include <dev/raid/hptmv/access601.h>
60
61
62 #ifdef DEBUG
63 #ifdef DEBUG_LEVEL
64 int hpt_dbg_level = DEBUG_LEVEL;
65 #else
66 int hpt_dbg_level = 0;
67 #endif
68 #endif
69
70 #define MV_ERROR kprintf
71
72 /*
73 * CAM SIM entry points
74 */
75 static int hpt_probe (device_t dev);
76 static void launch_worker_thread(void);
77 static int hpt_attach(device_t dev);
78 static int hpt_detach(device_t dev);
79 static int hpt_shutdown(device_t dev);
80 static void hpt_poll(struct cam_sim *sim);
81 static void hpt_intr(void *arg);
82 static void hpt_async(void *callback_arg, u_int32_t code, struct cam_path *path, void *arg);
83 static void hpt_action(struct cam_sim *sim, union ccb *ccb);
84
85 static struct thread *hptdaemonproc;
86
87 static device_method_t driver_methods[] = {
88 /* Device interface */
89 DEVMETHOD(device_probe, hpt_probe),
90 DEVMETHOD(device_attach, hpt_attach),
91 DEVMETHOD(device_detach, hpt_detach),
92
93 DEVMETHOD(device_shutdown, hpt_shutdown),
94 DEVMETHOD_END
95 };
96
97 static driver_t hpt_pci_driver = {
98 __str(PROC_DIR_NAME),
99 driver_methods,
100 sizeof(IAL_ADAPTER_T)
101 };
102
103 static devclass_t hpt_devclass;
104
105 #define __DRIVER_MODULE(p1, p2, p3, p4, p5, p6) DRIVER_MODULE(p1, p2, p3, p4, p5, p6)
106 __DRIVER_MODULE(PROC_DIR_NAME, pci, hpt_pci_driver, hpt_devclass, NULL, NULL);
107 MODULE_DEPEND(PROC_DIR_NAME, cam, 1, 1, 1);
108
109 #define ccb_ccb_ptr spriv_ptr0
110 #define ccb_adapter ccb_h.spriv_ptr1
111
112 static void SetInquiryData(PINQUIRYDATA inquiryData, PVDevice pVDev);
113 static void HPTLIBAPI OsSendCommand (_VBUS_ARG union ccb * ccb);
114 static void HPTLIBAPI fOsCommandDone(_VBUS_ARG PCommand pCmd);
115 static void ccb_done(union ccb *ccb);
116 static void hpt_queue_ccb(union ccb **ccb_Q, union ccb *ccb);
117 static void hpt_free_ccb(union ccb **ccb_Q, union ccb *ccb);
118 static void hptmv_free_edma_queues(IAL_ADAPTER_T *pAdapter);
119 static void hptmv_free_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum);
120 static void handleEdmaError(_VBUS_ARG PCommand pCmd);
121 static int hptmv_init_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum);
122 static int fResetActiveCommands(PVBus _vbus_p);
123 static void fRegisterVdevice(IAL_ADAPTER_T *pAdapter);
124 static int hptmv_allocate_edma_queues(IAL_ADAPTER_T *pAdapter);
125 static void hptmv_handle_event_disconnect(void *data);
126 static void hptmv_handle_event_connect(void *data);
127 static int start_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum);
128 static void init_vdev_params(IAL_ADAPTER_T *pAdapter, MV_U8 channel);
129 static int hptmv_parse_identify_results(MV_SATA_CHANNEL *pMvSataChannel);
130 static int HPTLIBAPI fOsBuildSgl(_VBUS_ARG PCommand pCmd, FPSCAT_GATH pSg,
131 int logical);
132 static MV_BOOLEAN CommandCompletionCB(MV_SATA_ADAPTER *pMvSataAdapter,
133 MV_U8 channelNum, MV_COMPLETION_TYPE comp_type, MV_VOID_PTR commandId,
134 MV_U16 responseFlags, MV_U32 timeStamp,
135 MV_STORAGE_DEVICE_REGISTERS *registerStruct);
136 static MV_BOOLEAN hptmv_event_notify(MV_SATA_ADAPTER *pMvSataAdapter,
137 MV_EVENT_TYPE eventType, MV_U32 param1, MV_U32 param2);
138
139 #define ccb_ccb_ptr spriv_ptr0
140 #define ccb_adapter ccb_h.spriv_ptr1
141
142 IAL_ADAPTER_T *gIal_Adapter = NULL;
143 IAL_ADAPTER_T *pCurAdapter = NULL;
144 static MV_SATA_CHANNEL gMvSataChannels[MAX_VBUS][MV_SATA_CHANNELS_NUM];
145
146 typedef struct st_HPT_DPC {
147 IAL_ADAPTER_T *pAdapter;
148 void (*dpc)(IAL_ADAPTER_T *, void *, UCHAR);
149 void *arg;
150 UCHAR flags;
151 } ST_HPT_DPC;
152
153 #define MAX_DPC 16
154 UCHAR DPC_Request_Nums = 0;
155 static ST_HPT_DPC DpcQueue[MAX_DPC];
156 static int DpcQueue_First=0;
157 static int DpcQueue_Last = 0;
158
159 char DRIVER_VERSION[] = "v1.16";
160
161 static struct lock driver_lock;
lock_driver(void)162 void lock_driver(void)
163 {
164 lockmgr(&driver_lock, LK_EXCLUSIVE);
165 }
unlock_driver(void)166 void unlock_driver(void)
167 {
168 lockmgr(&driver_lock, LK_RELEASE);
169 }
170
171 /*******************************************************************************
172 * Name: hptmv_free_channel
173 *
174 * Description: free allocated queues for the given channel
175 *
176 * Parameters: pMvSataAdapter - pointer to the RR18xx controler this
177 * channel connected to.
178 * channelNum - channel number.
179 *
180 ******************************************************************************/
181 static void
hptmv_free_channel(IAL_ADAPTER_T * pAdapter,MV_U8 channelNum)182 hptmv_free_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum)
183 {
184 HPT_ASSERT(channelNum < MV_SATA_CHANNELS_NUM);
185 pAdapter->mvSataAdapter.sataChannel[channelNum] = NULL;
186 }
187
failDevice(PVDevice pVDev)188 static void failDevice(PVDevice pVDev)
189 {
190 PVBus _vbus_p = pVDev->pVBus;
191 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)_vbus_p->OsExt;
192
193 pVDev->u.disk.df_on_line = 0;
194 pVDev->vf_online = 0;
195 if (pVDev->pfnDeviceFailed)
196 CallWhenIdle(_VBUS_P (DPC_PROC)pVDev->pfnDeviceFailed, pVDev);
197
198 fNotifyGUI(ET_DEVICE_REMOVED, pVDev);
199
200 #ifndef FOR_DEMO
201 if (pAdapter->ver_601==2 && !pAdapter->beeping) {
202 pAdapter->beeping = 1;
203 BeepOn(pAdapter->mvSataAdapter.adapterIoBaseAddress);
204 set_fail_led(&pAdapter->mvSataAdapter, pVDev->u.disk.mv->channelNumber, 1);
205 }
206 #endif
207 }
208
209 int MvSataResetChannel(MV_SATA_ADAPTER *pMvSataAdapter, MV_U8 channel);
210
211 static void
handleEdmaError(_VBUS_ARG PCommand pCmd)212 handleEdmaError(_VBUS_ARG PCommand pCmd)
213 {
214 PDevice pDevice = &pCmd->pVDevice->u.disk;
215 MV_SATA_ADAPTER * pSataAdapter = pDevice->mv->mvSataAdapter;
216
217 if (!pDevice->df_on_line) {
218 KdPrint(("Device is offline"));
219 pCmd->Result = RETURN_BAD_DEVICE;
220 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
221 return;
222 }
223
224 if (pCmd->RetryCount++>5) {
225 hpt_printk(("too many retries on channel(%d)\n", pDevice->mv->channelNumber));
226 failed:
227 failDevice(pCmd->pVDevice);
228 pCmd->Result = RETURN_IDE_ERROR;
229 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
230 return;
231 }
232
233 /* reset the channel and retry the command */
234 if (MvSataResetChannel(pSataAdapter, pDevice->mv->channelNumber))
235 goto failed;
236
237 fNotifyGUI(ET_DEVICE_ERROR, Map2pVDevice(pDevice));
238
239 hpt_printk(("Retry on channel(%d)\n", pDevice->mv->channelNumber));
240 fDeviceSendCommand(_VBUS_P pCmd);
241 }
242
243 /****************************************************************
244 * Name: hptmv_init_channel
245 *
246 * Description: allocate request and response queues for the EDMA of the
247 * given channel and sets other fields.
248 *
249 * Parameters:
250 * pAdapter - pointer to the emulated adapter data structure
251 * channelNum - channel number.
252 * Return: 0 on success, otherwise on failure
253 ****************************************************************/
254 static int
hptmv_init_channel(IAL_ADAPTER_T * pAdapter,MV_U8 channelNum)255 hptmv_init_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum)
256 {
257 MV_SATA_CHANNEL *pMvSataChannel;
258 dma_addr_t req_dma_addr;
259 dma_addr_t rsp_dma_addr;
260
261 if (channelNum >= MV_SATA_CHANNELS_NUM)
262 {
263 MV_ERROR("RR18xx[%d]: Bad channelNum=%d",
264 pAdapter->mvSataAdapter.adapterId, channelNum);
265 return -1;
266 }
267
268 pMvSataChannel = &gMvSataChannels[pAdapter->mvSataAdapter.adapterId][channelNum];
269 pAdapter->mvSataAdapter.sataChannel[channelNum] = pMvSataChannel;
270 pMvSataChannel->channelNumber = channelNum;
271 pMvSataChannel->lba48Address = MV_FALSE;
272 pMvSataChannel->maxReadTransfer = MV_FALSE;
273
274 pMvSataChannel->requestQueue = (struct mvDmaRequestQueueEntry *)
275 (pAdapter->requestsArrayBaseAlignedAddr + (channelNum * MV_EDMA_REQUEST_QUEUE_SIZE));
276 req_dma_addr = pAdapter->requestsArrayBaseDmaAlignedAddr + (channelNum * MV_EDMA_REQUEST_QUEUE_SIZE);
277
278
279 KdPrint(("requestQueue addr is 0x%llX", (HPT_U64)(ULONG_PTR)req_dma_addr));
280
281 /* check the 1K alignment of the request queue*/
282 if (req_dma_addr & 0x3ff)
283 {
284 MV_ERROR("RR18xx[%d]: request queue allocated isn't 1 K aligned,"
285 " dma_addr=%llx channel=%d\n", pAdapter->mvSataAdapter.adapterId,
286 (HPT_U64)(ULONG_PTR)req_dma_addr, channelNum);
287 return -1;
288 }
289 pMvSataChannel->requestQueuePciLowAddress = req_dma_addr;
290 pMvSataChannel->requestQueuePciHiAddress = 0;
291 KdPrint(("RR18xx[%d,%d]: request queue allocated: 0x%p",
292 pAdapter->mvSataAdapter.adapterId, channelNum,
293 pMvSataChannel->requestQueue));
294 pMvSataChannel->responseQueue = (struct mvDmaResponseQueueEntry *)
295 (pAdapter->responsesArrayBaseAlignedAddr + (channelNum * MV_EDMA_RESPONSE_QUEUE_SIZE));
296 rsp_dma_addr = pAdapter->responsesArrayBaseDmaAlignedAddr + (channelNum * MV_EDMA_RESPONSE_QUEUE_SIZE);
297
298 /* check the 256 alignment of the response queue*/
299 if (rsp_dma_addr & 0xff)
300 {
301 MV_ERROR("RR18xx[%d,%d]: response queue allocated isn't 256 byte "
302 "aligned, dma_addr=%llx\n",
303 pAdapter->mvSataAdapter.adapterId, channelNum, (HPT_U64)(ULONG_PTR)rsp_dma_addr);
304 return -1;
305 }
306 pMvSataChannel->responseQueuePciLowAddress = rsp_dma_addr;
307 pMvSataChannel->responseQueuePciHiAddress = 0;
308 KdPrint(("RR18xx[%d,%d]: response queue allocated: 0x%p",
309 pAdapter->mvSataAdapter.adapterId, channelNum,
310 pMvSataChannel->responseQueue));
311
312 pAdapter->mvChannel[channelNum].online = MV_TRUE;
313 return 0;
314 }
315
316 /******************************************************************************
317 * Name: hptmv_parse_identify_results
318 *
319 * Description: this functions parses the identify command results, checks
320 * that the connected deives can be accesed by RR18xx EDMA,
321 * and updates the channel stucture accordingly.
322 *
323 * Parameters: pMvSataChannel, pointer to the channel data structure.
324 *
325 * Returns: =0 ->success, < 0 ->failure.
326 *
327 ******************************************************************************/
328 static int
hptmv_parse_identify_results(MV_SATA_CHANNEL * pMvSataChannel)329 hptmv_parse_identify_results(MV_SATA_CHANNEL *pMvSataChannel)
330 {
331 MV_U16 *iden = pMvSataChannel->identifyDevice;
332
333 /*LBA addressing*/
334 if (! (iden[IDEN_CAPACITY_1_OFFSET] & 0x200))
335 {
336 KdPrint(("IAL Error in IDENTIFY info: LBA not supported\n"));
337 return -1;
338 }
339 else
340 {
341 KdPrint(("%25s - %s\n", "Capabilities", "LBA supported"));
342 }
343 /*DMA support*/
344 if (! (iden[IDEN_CAPACITY_1_OFFSET] & 0x100))
345 {
346 KdPrint(("IAL Error in IDENTIFY info: DMA not supported\n"));
347 return -1;
348 }
349 else
350 {
351 KdPrint(("%25s - %s\n", "Capabilities", "DMA supported"));
352 }
353 /* PIO */
354 if ((iden[IDEN_VALID] & 2) == 0)
355 {
356 KdPrint(("IAL Error in IDENTIFY info: not able to find PIO mode\n"));
357 return -1;
358 }
359 KdPrint(("%25s - 0x%02x\n", "PIO modes supported",
360 iden[IDEN_PIO_MODE_SPPORTED] & 0xff));
361
362 /*UDMA*/
363 if ((iden[IDEN_VALID] & 4) == 0)
364 {
365 KdPrint(("IAL Error in IDENTIFY info: not able to find UDMA mode\n"));
366 return -1;
367 }
368
369 /* 48 bit address */
370 if ((iden[IDEN_SUPPORTED_COMMANDS2] & 0x400))
371 {
372 KdPrint(("%25s - %s\n", "LBA48 addressing", "supported"));
373 pMvSataChannel->lba48Address = MV_TRUE;
374 }
375 else
376 {
377 KdPrint(("%25s - %s\n", "LBA48 addressing", "Not supported"));
378 pMvSataChannel->lba48Address = MV_FALSE;
379 }
380 return 0;
381 }
382
383 static void
init_vdev_params(IAL_ADAPTER_T * pAdapter,MV_U8 channel)384 init_vdev_params(IAL_ADAPTER_T *pAdapter, MV_U8 channel)
385 {
386 PVDevice pVDev = &pAdapter->VDevices[channel];
387 MV_SATA_CHANNEL *pMvSataChannel = pAdapter->mvSataAdapter.sataChannel[channel];
388 MV_U16_PTR IdentifyData = pMvSataChannel->identifyDevice;
389
390 pMvSataChannel->outstandingCommands = 0;
391
392 pVDev->u.disk.mv = pMvSataChannel;
393 pVDev->u.disk.df_on_line = 1;
394 pVDev->u.disk.pVBus = &pAdapter->VBus;
395 pVDev->pVBus = &pAdapter->VBus;
396
397 #ifdef SUPPORT_48BIT_LBA
398 if (pMvSataChannel->lba48Address == MV_TRUE)
399 pVDev->u.disk.dDeRealCapacity = ((IdentifyData[101]<<16) | IdentifyData[100]) - 1;
400 else
401 #endif
402 if(IdentifyData[53] & 1) {
403 pVDev->u.disk.dDeRealCapacity =
404 (((IdentifyData[58]<<16 | IdentifyData[57]) < (IdentifyData[61]<<16 | IdentifyData[60])) ?
405 (IdentifyData[61]<<16 | IdentifyData[60]) :
406 (IdentifyData[58]<<16 | IdentifyData[57])) - 1;
407 } else
408 pVDev->u.disk.dDeRealCapacity =
409 (IdentifyData[61]<<16 | IdentifyData[60]) - 1;
410
411 pVDev->u.disk.bDeUsable_Mode = pVDev->u.disk.bDeModeSetting =
412 pAdapter->mvChannel[channel].maxPioModeSupported - MV_ATA_TRANSFER_PIO_0;
413
414 if (pAdapter->mvChannel[channel].maxUltraDmaModeSupported!=0xFF) {
415 pVDev->u.disk.bDeUsable_Mode = pVDev->u.disk.bDeModeSetting =
416 pAdapter->mvChannel[channel].maxUltraDmaModeSupported - MV_ATA_TRANSFER_UDMA_0 + 8;
417 }
418 }
419
device_change(IAL_ADAPTER_T * pAdapter,MV_U8 channelIndex,int plugged)420 static void device_change(IAL_ADAPTER_T *pAdapter , MV_U8 channelIndex, int plugged)
421 {
422 PVDevice pVDev;
423 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter;
424 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channelIndex];
425
426 if (!pMvSataChannel) return;
427
428 if (plugged)
429 {
430 pVDev = &(pAdapter->VDevices[channelIndex]);
431 init_vdev_params(pAdapter, channelIndex);
432
433 pVDev->VDeviceType = pVDev->u.disk.df_atapi? VD_ATAPI :
434 pVDev->u.disk.df_removable_drive? VD_REMOVABLE : VD_SINGLE_DISK;
435
436 pVDev->VDeviceCapacity = pVDev->u.disk.dDeRealCapacity-SAVE_FOR_RAID_INFO;
437 pVDev->pfnSendCommand = pfnSendCommand[pVDev->VDeviceType];
438 pVDev->pfnDeviceFailed = pfnDeviceFailed[pVDev->VDeviceType];
439 pVDev->vf_online = 1;
440
441 #ifdef SUPPORT_ARRAY
442 if(pVDev->pParent)
443 {
444 int iMember;
445 for(iMember = 0; iMember < pVDev->pParent->u.array.bArnMember; iMember++)
446 if((PVDevice)pVDev->pParent->u.array.pMember[iMember] == pVDev)
447 pVDev->pParent->u.array.pMember[iMember] = NULL;
448 pVDev->pParent = NULL;
449 }
450 #endif
451 fNotifyGUI(ET_DEVICE_PLUGGED,pVDev);
452 fCheckBootable(pVDev);
453 RegisterVDevice(pVDev);
454
455 #ifndef FOR_DEMO
456 if (pAdapter->beeping) {
457 pAdapter->beeping = 0;
458 BeepOff(pAdapter->mvSataAdapter.adapterIoBaseAddress);
459 }
460 #endif
461
462 }
463 else
464 {
465 pVDev = &(pAdapter->VDevices[channelIndex]);
466 failDevice(pVDev);
467 }
468 }
469
470 static int
start_channel(IAL_ADAPTER_T * pAdapter,MV_U8 channelNum)471 start_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum)
472 {
473 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter;
474 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channelNum];
475 MV_CHANNEL *pChannelInfo = &(pAdapter->mvChannel[channelNum]);
476 MV_U32 udmaMode,pioMode;
477
478 KdPrint(("RR18xx [%d]: start channel (%d)", pMvSataAdapter->adapterId,
479 channelNum));
480
481
482 /* Software reset channel */
483 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE)
484 {
485 MV_ERROR("RR18xx [%d,%d]: failed to perform Software reset\n",
486 pMvSataAdapter->adapterId, channelNum);
487 return -1;
488 }
489
490 /* Hardware reset channel */
491 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE)
492 {
493 /* If failed, try again - this is when trying to hardreset a channel */
494 /* when drive is just spinning up */
495 StallExec(5000000); /* wait 5 sec before trying again */
496 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE)
497 {
498 MV_ERROR("RR18xx [%d,%d]: failed to perform Hard reset\n",
499 pMvSataAdapter->adapterId, channelNum);
500 return -1;
501 }
502 }
503
504 /* identify device*/
505 if (mvStorageDevATAIdentifyDevice(pMvSataAdapter, channelNum) == MV_FALSE)
506 {
507 MV_ERROR("RR18xx [%d,%d]: failed to perform ATA Identify command\n"
508 , pMvSataAdapter->adapterId, channelNum);
509 return -1;
510 }
511 if (hptmv_parse_identify_results(pMvSataChannel))
512 {
513 MV_ERROR("RR18xx [%d,%d]: Error in parsing ATA Identify message\n"
514 , pMvSataAdapter->adapterId, channelNum);
515 return -1;
516 }
517
518 /* mvStorageDevATASetFeatures */
519 /* Disable 8 bit PIO in case CFA enabled */
520 if (pMvSataChannel->identifyDevice[86] & 4)
521 {
522 KdPrint(("RR18xx [%d]: Disable 8 bit PIO (CFA enabled) \n",
523 pMvSataAdapter->adapterId));
524 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
525 MV_ATA_SET_FEATURES_DISABLE_8_BIT_PIO, 0,
526 0, 0, 0) == MV_FALSE)
527 {
528 MV_ERROR("RR18xx [%d]: channel %d: mvStorageDevATASetFeatures"
529 " failed\n", pMvSataAdapter->adapterId, channelNum);
530 return -1;
531 }
532 }
533 /* Write cache */
534 #ifdef ENABLE_WRITE_CACHE
535 if (pMvSataChannel->identifyDevice[82] & 0x20)
536 {
537 if (!(pMvSataChannel->identifyDevice[85] & 0x20)) /* if not enabled by default */
538 {
539 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
540 MV_ATA_SET_FEATURES_ENABLE_WCACHE, 0,
541 0, 0, 0) == MV_FALSE)
542 {
543 MV_ERROR("RR18xx [%d]: channel %d: mvStorageDevATASetFeatures failed\n",
544 pMvSataAdapter->adapterId, channelNum);
545 return -1;
546 }
547 }
548 KdPrint(("RR18xx [%d]: channel %d, write cache enabled\n",
549 pMvSataAdapter->adapterId, channelNum));
550 }
551 else
552 {
553 KdPrint(("RR18xx [%d]: channel %d, write cache not supported\n",
554 pMvSataAdapter->adapterId, channelNum));
555 }
556 #else /* disable write cache */
557 {
558 if (pMvSataChannel->identifyDevice[85] & 0x20)
559 {
560 KdPrint(("RR18xx [%d]: channel =%d, disable write cache\n",
561 pMvSataAdapter->adapterId, channelNum));
562 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
563 MV_ATA_SET_FEATURES_DISABLE_WCACHE, 0,
564 0, 0, 0) == MV_FALSE)
565 {
566 MV_ERROR("RR18xx [%d]: channel %d: mvStorageDevATASetFeatures failed\n",
567 pMvSataAdapter->adapterId, channelNum);
568 return -1;
569 }
570 }
571 KdPrint(("RR18xx [%d]: channel=%d, write cache disabled\n",
572 pMvSataAdapter->adapterId, channelNum));
573 }
574 #endif
575
576 /* Set transfer mode */
577 KdPrint(("RR18xx [%d] Set transfer mode XFER_PIO_SLOW\n",
578 pMvSataAdapter->adapterId));
579 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
580 MV_ATA_SET_FEATURES_TRANSFER,
581 MV_ATA_TRANSFER_PIO_SLOW, 0, 0, 0) ==
582 MV_FALSE)
583 {
584 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n",
585 pMvSataAdapter->adapterId, channelNum);
586 return -1;
587 }
588
589 if (pMvSataChannel->identifyDevice[IDEN_PIO_MODE_SPPORTED] & 1)
590 {
591 pioMode = MV_ATA_TRANSFER_PIO_4;
592 }
593 else if (pMvSataChannel->identifyDevice[IDEN_PIO_MODE_SPPORTED] & 2)
594 {
595 pioMode = MV_ATA_TRANSFER_PIO_3;
596 }
597 else
598 {
599 MV_ERROR("IAL Error in IDENTIFY info: PIO modes 3 and 4 not supported\n");
600 pioMode = MV_ATA_TRANSFER_PIO_SLOW;
601 }
602
603 KdPrint(("RR18xx [%d] Set transfer mode XFER_PIO_4\n",
604 pMvSataAdapter->adapterId));
605 pAdapter->mvChannel[channelNum].maxPioModeSupported = pioMode;
606 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
607 MV_ATA_SET_FEATURES_TRANSFER,
608 pioMode, 0, 0, 0) == MV_FALSE)
609 {
610 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n",
611 pMvSataAdapter->adapterId, channelNum);
612 return -1;
613 }
614
615 udmaMode = MV_ATA_TRANSFER_UDMA_0;
616 if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x40)
617 {
618 udmaMode = MV_ATA_TRANSFER_UDMA_6;
619 }
620 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x20)
621 {
622 udmaMode = MV_ATA_TRANSFER_UDMA_5;
623 }
624 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x10)
625 {
626 udmaMode = MV_ATA_TRANSFER_UDMA_4;
627 }
628 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 8)
629 {
630 udmaMode = MV_ATA_TRANSFER_UDMA_3;
631 }
632 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 4)
633 {
634 udmaMode = MV_ATA_TRANSFER_UDMA_2;
635 }
636
637 KdPrint(("RR18xx [%d] Set transfer mode XFER_UDMA_%d\n",
638 pMvSataAdapter->adapterId, udmaMode & 0xf));
639 pChannelInfo->maxUltraDmaModeSupported = udmaMode;
640
641 /*if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
642 MV_ATA_SET_FEATURES_TRANSFER, udmaMode,
643 0, 0, 0) == MV_FALSE)
644 {
645 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n",
646 pMvSataAdapter->adapterId, channelNum);
647 return -1;
648 }*/
649 if (pChannelInfo->maxUltraDmaModeSupported == 0xFF)
650 return TRUE;
651 else
652 do
653 {
654 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
655 MV_ATA_SET_FEATURES_TRANSFER,
656 pChannelInfo->maxUltraDmaModeSupported,
657 0, 0, 0) == MV_FALSE)
658 {
659 if (pChannelInfo->maxUltraDmaModeSupported > MV_ATA_TRANSFER_UDMA_0)
660 {
661 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE)
662 {
663 MV_REG_WRITE_BYTE(pMvSataAdapter->adapterIoBaseAddress,
664 pMvSataChannel->eDmaRegsOffset +
665 0x11c, /* command reg */
666 MV_ATA_COMMAND_IDLE_IMMEDIATE);
667 mvMicroSecondsDelay(10000);
668 mvSataChannelHardReset(pMvSataAdapter, channelNum);
669 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE)
670 return FALSE;
671 }
672 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE)
673 return FALSE;
674 pChannelInfo->maxUltraDmaModeSupported--;
675 continue;
676 }
677 else return FALSE;
678 }
679 break;
680 }while (1);
681
682 /* Read look ahead */
683 #ifdef ENABLE_READ_AHEAD
684 if (pMvSataChannel->identifyDevice[82] & 0x40)
685 {
686 if (!(pMvSataChannel->identifyDevice[85] & 0x40)) /* if not enabled by default */
687 {
688 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
689 MV_ATA_SET_FEATURES_ENABLE_RLA, 0, 0,
690 0, 0) == MV_FALSE)
691 {
692 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n",
693 pMvSataAdapter->adapterId, channelNum);
694 return -1;
695 }
696 }
697 KdPrint(("RR18xx [%d]: channel=%d, read look ahead enabled\n",
698 pMvSataAdapter->adapterId, channelNum));
699 }
700 else
701 {
702 KdPrint(("RR18xx [%d]: channel %d, Read Look Ahead not supported\n",
703 pMvSataAdapter->adapterId, channelNum));
704 }
705 #else
706 {
707 if (pMvSataChannel->identifyDevice[86] & 0x20)
708 {
709 KdPrint(("RR18xx [%d]:channel %d, disable read look ahead\n",
710 pMvSataAdapter->adapterId, channelNum));
711 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
712 MV_ATA_SET_FEATURES_DISABLE_RLA, 0, 0,
713 0, 0) == MV_FALSE)
714 {
715 MV_ERROR("RR18xx [%d]:channel %d: ATA Set Features failed\n",
716 pMvSataAdapter->adapterId, channelNum);
717 return -1;
718 }
719 }
720 KdPrint(("RR18xx [%d]:channel %d, read look ahead disabled\n",
721 pMvSataAdapter->adapterId, channelNum));
722 }
723 #endif
724
725
726 {
727 KdPrint(("RR18xx [%d]: channel %d config EDMA, Non Queued Mode\n",
728 pMvSataAdapter->adapterId,
729 channelNum));
730 if (mvSataConfigEdmaMode(pMvSataAdapter, channelNum,
731 MV_EDMA_MODE_NOT_QUEUED, 0) == MV_FALSE)
732 {
733 MV_ERROR("RR18xx [%d] channel %d Error: mvSataConfigEdmaMode failed\n",
734 pMvSataAdapter->adapterId, channelNum);
735 return -1;
736 }
737 }
738 /* Enable EDMA */
739 if (mvSataEnableChannelDma(pMvSataAdapter, channelNum) == MV_FALSE)
740 {
741 MV_ERROR("RR18xx [%d] Failed to enable DMA, channel=%d\n",
742 pMvSataAdapter->adapterId, channelNum);
743 return -1;
744 }
745 MV_ERROR("RR18xx [%d,%d]: channel started successfully\n",
746 pMvSataAdapter->adapterId, channelNum);
747
748 #ifndef FOR_DEMO
749 set_fail_led(pMvSataAdapter, channelNum, 0);
750 #endif
751 return 0;
752 }
753
754 static void
hptmv_handle_event(void * data,int flag)755 hptmv_handle_event(void * data, int flag)
756 {
757 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)data;
758 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter;
759 MV_U8 channelIndex;
760
761 /* mvOsSemTake(&pMvSataAdapter->semaphore); */
762 for (channelIndex = 0; channelIndex < MV_SATA_CHANNELS_NUM; channelIndex++)
763 {
764 switch(pAdapter->sataEvents[channelIndex])
765 {
766 case SATA_EVENT_CHANNEL_CONNECTED:
767 /* Handle only connects */
768 if (flag == 1)
769 break;
770 KdPrint(("RR18xx [%d,%d]: new device connected\n",
771 pMvSataAdapter->adapterId, channelIndex));
772 hptmv_init_channel(pAdapter, channelIndex);
773 if (mvSataConfigureChannel( pMvSataAdapter, channelIndex) == MV_FALSE)
774 {
775 MV_ERROR("RR18xx [%d,%d] Failed to configure\n",
776 pMvSataAdapter->adapterId, channelIndex);
777 hptmv_free_channel(pAdapter, channelIndex);
778 }
779 else
780 {
781 /*mvSataChannelHardReset(pMvSataAdapter, channel);*/
782 if (start_channel( pAdapter, channelIndex))
783 {
784 MV_ERROR("RR18xx [%d,%d]Failed to start channel\n",
785 pMvSataAdapter->adapterId, channelIndex);
786 hptmv_free_channel(pAdapter, channelIndex);
787 }
788 else
789 {
790 device_change(pAdapter, channelIndex, TRUE);
791 }
792 }
793 pAdapter->sataEvents[channelIndex] = SATA_EVENT_NO_CHANGE;
794 break;
795
796 case SATA_EVENT_CHANNEL_DISCONNECTED:
797 /* Handle only disconnects */
798 if (flag == 0)
799 break;
800 KdPrint(("RR18xx [%d,%d]: device disconnected\n",
801 pMvSataAdapter->adapterId, channelIndex));
802 /* Flush pending commands */
803 if(pMvSataAdapter->sataChannel[channelIndex])
804 {
805 _VBUS_INST(&pAdapter->VBus)
806 mvSataFlushDmaQueue (pMvSataAdapter, channelIndex,
807 MV_FLUSH_TYPE_CALLBACK);
808 CheckPendingCall(_VBUS_P0);
809 mvSataRemoveChannel(pMvSataAdapter,channelIndex);
810 hptmv_free_channel(pAdapter, channelIndex);
811 pMvSataAdapter->sataChannel[channelIndex] = NULL;
812 KdPrint(("RR18xx [%d,%d]: channel removed\n",
813 pMvSataAdapter->adapterId, channelIndex));
814 if (pAdapter->outstandingCommands==0 && DPC_Request_Nums==0)
815 Check_Idle_Call(pAdapter);
816 }
817 else
818 {
819 KdPrint(("RR18xx [%d,%d]: channel already removed!!\n",
820 pMvSataAdapter->adapterId, channelIndex));
821 }
822 pAdapter->sataEvents[channelIndex] = SATA_EVENT_NO_CHANGE;
823 break;
824
825 case SATA_EVENT_NO_CHANGE:
826 break;
827
828 default:
829 break;
830 }
831 }
832 /* mvOsSemRelease(&pMvSataAdapter->semaphore); */
833 }
834
835 #define EVENT_CONNECT 1
836 #define EVENT_DISCONNECT 0
837
838 static void
hptmv_handle_event_connect(void * data)839 hptmv_handle_event_connect(void *data)
840 {
841 hptmv_handle_event (data, 0);
842 }
843
844 static void
hptmv_handle_event_disconnect(void * data)845 hptmv_handle_event_disconnect(void *data)
846 {
847 hptmv_handle_event (data, 1);
848 }
849
850 static MV_BOOLEAN
hptmv_event_notify(MV_SATA_ADAPTER * pMvSataAdapter,MV_EVENT_TYPE eventType,MV_U32 param1,MV_U32 param2)851 hptmv_event_notify(MV_SATA_ADAPTER *pMvSataAdapter, MV_EVENT_TYPE eventType,
852 MV_U32 param1, MV_U32 param2)
853 {
854 IAL_ADAPTER_T *pAdapter = pMvSataAdapter->IALData;
855
856 switch (eventType)
857 {
858 case MV_EVENT_TYPE_SATA_CABLE:
859 {
860 MV_U8 channel = param2;
861
862 if (param1 == EVENT_CONNECT)
863 {
864 pAdapter->sataEvents[channel] = SATA_EVENT_CHANNEL_CONNECTED;
865 KdPrint(("RR18xx [%d,%d]: device connected event received\n",
866 pMvSataAdapter->adapterId, channel));
867 /* Delete previous timers (if multiple drives connected in the same time */
868 callout_reset(&pAdapter->event_timer_connect, 10*hz, hptmv_handle_event_connect, pAdapter);
869 }
870 else if (param1 == EVENT_DISCONNECT)
871 {
872 pAdapter->sataEvents[channel] = SATA_EVENT_CHANNEL_DISCONNECTED;
873 KdPrint(("RR18xx [%d,%d]: device disconnected event received \n",
874 pMvSataAdapter->adapterId, channel));
875 device_change(pAdapter, channel, FALSE);
876 /* Delete previous timers (if multiple drives disconnected in the same time */
877 /* callout_reset(&pAdapter->event_timer_disconnect, 10*hz, hptmv_handle_event_disconnect, pAdapter); */
878 /*It is not necessary to wait, handle it directly*/
879 hptmv_handle_event_disconnect(pAdapter);
880 }
881 else
882 {
883
884 MV_ERROR("RR18xx: illigal value for param1(%d) at "
885 "connect/disconect event, host=%d\n", param1,
886 pMvSataAdapter->adapterId );
887
888 }
889 }
890 break;
891 case MV_EVENT_TYPE_ADAPTER_ERROR:
892 KdPrint(("RR18xx: DEVICE error event received, pci cause "
893 "reg=%x, don't how to handle this\n", param1));
894 return MV_TRUE;
895 default:
896 MV_ERROR("RR18xx[%d]: unknown event type (%d)\n",
897 pMvSataAdapter->adapterId, eventType);
898 return MV_FALSE;
899 }
900 return MV_TRUE;
901 }
902
903 static int
hptmv_allocate_edma_queues(IAL_ADAPTER_T * pAdapter)904 hptmv_allocate_edma_queues(IAL_ADAPTER_T *pAdapter)
905 {
906 pAdapter->requestsArrayBaseAddr = (MV_U8 *)contigmalloc(REQUESTS_ARRAY_SIZE,
907 M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul);
908 if (pAdapter->requestsArrayBaseAddr == NULL)
909 {
910 MV_ERROR("RR18xx[%d]: Failed to allocate memory for EDMA request"
911 " queues\n", pAdapter->mvSataAdapter.adapterId);
912 return -1;
913 }
914 pAdapter->requestsArrayBaseDmaAddr = fOsPhysicalAddress(pAdapter->requestsArrayBaseAddr);
915 pAdapter->requestsArrayBaseAlignedAddr = pAdapter->requestsArrayBaseAddr;
916 pAdapter->requestsArrayBaseAlignedAddr += MV_EDMA_REQUEST_QUEUE_SIZE;
917 pAdapter->requestsArrayBaseAlignedAddr = (MV_U8 *)
918 (((ULONG_PTR)pAdapter->requestsArrayBaseAlignedAddr) & ~(ULONG_PTR)(MV_EDMA_REQUEST_QUEUE_SIZE - 1));
919 pAdapter->requestsArrayBaseDmaAlignedAddr = pAdapter->requestsArrayBaseDmaAddr;
920 pAdapter->requestsArrayBaseDmaAlignedAddr += MV_EDMA_REQUEST_QUEUE_SIZE;
921 pAdapter->requestsArrayBaseDmaAlignedAddr &= ~(ULONG_PTR)(MV_EDMA_REQUEST_QUEUE_SIZE - 1);
922
923 if ((pAdapter->requestsArrayBaseDmaAlignedAddr - pAdapter->requestsArrayBaseDmaAddr) !=
924 (pAdapter->requestsArrayBaseAlignedAddr - pAdapter->requestsArrayBaseAddr))
925 {
926 MV_ERROR("RR18xx[%d]: Error in Request Quueues Alignment\n",
927 pAdapter->mvSataAdapter.adapterId);
928 contigfree(pAdapter->requestsArrayBaseAddr, REQUESTS_ARRAY_SIZE, M_DEVBUF);
929 return -1;
930 }
931 /* response queues */
932 pAdapter->responsesArrayBaseAddr = (MV_U8 *)contigmalloc(RESPONSES_ARRAY_SIZE,
933 M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul);
934 if (pAdapter->responsesArrayBaseAddr == NULL)
935 {
936 MV_ERROR("RR18xx[%d]: Failed to allocate memory for EDMA response"
937 " queues\n", pAdapter->mvSataAdapter.adapterId);
938 contigfree(pAdapter->requestsArrayBaseAddr, RESPONSES_ARRAY_SIZE, M_DEVBUF);
939 return -1;
940 }
941 pAdapter->responsesArrayBaseDmaAddr = fOsPhysicalAddress(pAdapter->responsesArrayBaseAddr);
942 pAdapter->responsesArrayBaseAlignedAddr = pAdapter->responsesArrayBaseAddr;
943 pAdapter->responsesArrayBaseAlignedAddr += MV_EDMA_RESPONSE_QUEUE_SIZE;
944 pAdapter->responsesArrayBaseAlignedAddr = (MV_U8 *)
945 (((ULONG_PTR)pAdapter->responsesArrayBaseAlignedAddr) & ~(ULONG_PTR)(MV_EDMA_RESPONSE_QUEUE_SIZE - 1));
946 pAdapter->responsesArrayBaseDmaAlignedAddr = pAdapter->responsesArrayBaseDmaAddr;
947 pAdapter->responsesArrayBaseDmaAlignedAddr += MV_EDMA_RESPONSE_QUEUE_SIZE;
948 pAdapter->responsesArrayBaseDmaAlignedAddr &= ~(ULONG_PTR)(MV_EDMA_RESPONSE_QUEUE_SIZE - 1);
949
950 if ((pAdapter->responsesArrayBaseDmaAlignedAddr - pAdapter->responsesArrayBaseDmaAddr) !=
951 (pAdapter->responsesArrayBaseAlignedAddr - pAdapter->responsesArrayBaseAddr))
952 {
953 MV_ERROR("RR18xx[%d]: Error in Response Quueues Alignment\n",
954 pAdapter->mvSataAdapter.adapterId);
955 contigfree(pAdapter->requestsArrayBaseAddr, REQUESTS_ARRAY_SIZE, M_DEVBUF);
956 contigfree(pAdapter->responsesArrayBaseAddr, RESPONSES_ARRAY_SIZE, M_DEVBUF);
957 return -1;
958 }
959 return 0;
960 }
961
962 static void
hptmv_free_edma_queues(IAL_ADAPTER_T * pAdapter)963 hptmv_free_edma_queues(IAL_ADAPTER_T *pAdapter)
964 {
965 contigfree(pAdapter->requestsArrayBaseAddr, REQUESTS_ARRAY_SIZE, M_DEVBUF);
966 contigfree(pAdapter->responsesArrayBaseAddr, RESPONSES_ARRAY_SIZE, M_DEVBUF);
967 }
968
969 static PVOID
AllocatePRDTable(IAL_ADAPTER_T * pAdapter)970 AllocatePRDTable(IAL_ADAPTER_T *pAdapter)
971 {
972 PVOID ret;
973 if (pAdapter->pFreePRDLink) {
974 KdPrint(("pAdapter->pFreePRDLink:%p\n",pAdapter->pFreePRDLink));
975 ret = pAdapter->pFreePRDLink;
976 pAdapter->pFreePRDLink = *(void**)ret;
977 return ret;
978 }
979 return NULL;
980 }
981
982 static void
FreePRDTable(IAL_ADAPTER_T * pAdapter,PVOID PRDTable)983 FreePRDTable(IAL_ADAPTER_T *pAdapter, PVOID PRDTable)
984 {
985 *(void**)PRDTable = pAdapter->pFreePRDLink;
986 pAdapter->pFreePRDLink = PRDTable;
987 }
988
989 extern PVDevice fGetFirstChild(PVDevice pLogical);
990 extern void fResetBootMark(PVDevice pLogical);
991 static void
fRegisterVdevice(IAL_ADAPTER_T * pAdapter)992 fRegisterVdevice(IAL_ADAPTER_T *pAdapter)
993 {
994 PVDevice pPhysical, pLogical;
995 PVBus pVBus;
996 int i,j;
997
998 for(i=0;i<MV_SATA_CHANNELS_NUM;i++) {
999 pPhysical = &(pAdapter->VDevices[i]);
1000 pLogical = pPhysical;
1001 while (pLogical->pParent) pLogical = pLogical->pParent;
1002 if (pLogical->vf_online==0) {
1003 pPhysical->vf_bootmark = pLogical->vf_bootmark = 0;
1004 continue;
1005 }
1006 if (pLogical->VDeviceType==VD_SPARE || pPhysical!=fGetFirstChild(pLogical))
1007 continue;
1008
1009 pVBus = &pAdapter->VBus;
1010 if(pVBus)
1011 {
1012 j=0;
1013 while(j<MAX_VDEVICE_PER_VBUS && pVBus->pVDevice[j]) j++;
1014 if(j<MAX_VDEVICE_PER_VBUS){
1015 pVBus->pVDevice[j] = pLogical;
1016 pLogical->pVBus = pVBus;
1017
1018 if (j>0 && pLogical->vf_bootmark) {
1019 if (pVBus->pVDevice[0]->vf_bootmark) {
1020 fResetBootMark(pLogical);
1021 }
1022 else {
1023 do { pVBus->pVDevice[j] = pVBus->pVDevice[j-1]; } while (--j);
1024 pVBus->pVDevice[0] = pLogical;
1025 }
1026 }
1027 }
1028 }
1029 }
1030 }
1031
1032 PVDevice
GetSpareDisk(_VBUS_ARG PVDevice pArray)1033 GetSpareDisk(_VBUS_ARG PVDevice pArray)
1034 {
1035 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)pArray->pVBus->OsExt;
1036 LBA_T capacity = LongDiv(pArray->VDeviceCapacity, pArray->u.array.bArnMember-1);
1037 LBA_T thiscap, maxcap = MAX_LBA_T;
1038 PVDevice pVDevice, pFind = NULL;
1039 int i;
1040
1041 for(i=0;i<MV_SATA_CHANNELS_NUM;i++)
1042 {
1043 pVDevice = &pAdapter->VDevices[i];
1044 if(!pVDevice)
1045 continue;
1046 thiscap = pArray->vf_format_v2? pVDevice->u.disk.dDeRealCapacity : pVDevice->VDeviceCapacity;
1047 /* find the smallest usable spare disk */
1048 if (pVDevice->VDeviceType==VD_SPARE &&
1049 pVDevice->u.disk.df_on_line &&
1050 thiscap < maxcap &&
1051 thiscap >= capacity)
1052 {
1053 maxcap = pVDevice->VDeviceCapacity;
1054 pFind = pVDevice;
1055 }
1056 }
1057 return pFind;
1058 }
1059
1060 /******************************************************************
1061 * IO ATA Command
1062 *******************************************************************/
1063 int HPTLIBAPI
fDeReadWrite(PDevice pDev,ULONG Lba,UCHAR Cmd,void * tmpBuffer)1064 fDeReadWrite(PDevice pDev, ULONG Lba, UCHAR Cmd, void *tmpBuffer)
1065 {
1066 return mvReadWrite(pDev->mv, Lba, Cmd, tmpBuffer);
1067 }
1068
fDeSelectMode(PDevice pDev,UCHAR NewMode)1069 void HPTLIBAPI fDeSelectMode(PDevice pDev, UCHAR NewMode)
1070 {
1071 MV_SATA_CHANNEL *pSataChannel = pDev->mv;
1072 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter;
1073 MV_U8 channelIndex = pSataChannel->channelNumber;
1074 UCHAR mvMode;
1075 /* 508x don't use MW-DMA? */
1076 if (NewMode>4 && NewMode<8) NewMode = 4;
1077 pDev->bDeModeSetting = NewMode;
1078 if (NewMode<=4)
1079 mvMode = MV_ATA_TRANSFER_PIO_0 + NewMode;
1080 else
1081 mvMode = MV_ATA_TRANSFER_UDMA_0 + (NewMode-8);
1082
1083 /*To fix 88i8030 bug*/
1084 if (mvMode > MV_ATA_TRANSFER_UDMA_0 && mvMode < MV_ATA_TRANSFER_UDMA_4)
1085 mvMode = MV_ATA_TRANSFER_UDMA_0;
1086
1087 mvSataDisableChannelDma(pSataAdapter, channelIndex);
1088 /* Flush pending commands */
1089 mvSataFlushDmaQueue (pSataAdapter, channelIndex, MV_FLUSH_TYPE_NONE);
1090
1091 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex,
1092 MV_ATA_SET_FEATURES_TRANSFER,
1093 mvMode, 0, 0, 0) == MV_FALSE)
1094 {
1095 KdPrint(("channel %d: Set Features failed\n", channelIndex));
1096 }
1097 /* Enable EDMA */
1098 if (mvSataEnableChannelDma(pSataAdapter, channelIndex) == MV_FALSE)
1099 KdPrint(("Failed to enable DMA, channel=%d", channelIndex));
1100 }
1101
fDeSetTCQ(PDevice pDev,int enable,int depth)1102 int HPTLIBAPI fDeSetTCQ(PDevice pDev, int enable, int depth)
1103 {
1104 MV_SATA_CHANNEL *pSataChannel = pDev->mv;
1105 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter;
1106 MV_U8 channelIndex = pSataChannel->channelNumber;
1107 IAL_ADAPTER_T *pAdapter = pSataAdapter->IALData;
1108 MV_CHANNEL *channelInfo = &(pAdapter->mvChannel[channelIndex]);
1109 int dmaActive = pSataChannel->queueCommandsEnabled;
1110 int ret = 0;
1111
1112 if (dmaActive) {
1113 mvSataDisableChannelDma(pSataAdapter, channelIndex);
1114 mvSataFlushDmaQueue(pSataAdapter,channelIndex,MV_FLUSH_TYPE_CALLBACK);
1115 }
1116
1117 if (enable) {
1118 if (pSataChannel->queuedDMA == MV_EDMA_MODE_NOT_QUEUED &&
1119 (pSataChannel->identifyDevice[IDEN_SUPPORTED_COMMANDS2] & (0x2))) {
1120 UCHAR depth = ((pSataChannel->identifyDevice[IDEN_QUEUE_DEPTH]) & 0x1f) + 1;
1121 channelInfo->queueDepth = (depth==32)? 31 : depth;
1122 mvSataConfigEdmaMode(pSataAdapter, channelIndex, MV_EDMA_MODE_QUEUED, depth);
1123 ret = 1;
1124 }
1125 }
1126 else
1127 {
1128 if (pSataChannel->queuedDMA != MV_EDMA_MODE_NOT_QUEUED) {
1129 channelInfo->queueDepth = 2;
1130 mvSataConfigEdmaMode(pSataAdapter, channelIndex, MV_EDMA_MODE_NOT_QUEUED, 0);
1131 ret = 1;
1132 }
1133 }
1134
1135 if (dmaActive)
1136 mvSataEnableChannelDma(pSataAdapter,channelIndex);
1137 return ret;
1138 }
1139
fDeSetNCQ(PDevice pDev,int enable,int depth)1140 int HPTLIBAPI fDeSetNCQ(PDevice pDev, int enable, int depth)
1141 {
1142 return 0;
1143 }
1144
fDeSetWriteCache(PDevice pDev,int enable)1145 int HPTLIBAPI fDeSetWriteCache(PDevice pDev, int enable)
1146 {
1147 MV_SATA_CHANNEL *pSataChannel = pDev->mv;
1148 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter;
1149 MV_U8 channelIndex = pSataChannel->channelNumber;
1150 IAL_ADAPTER_T *pAdapter = pSataAdapter->IALData;
1151 MV_CHANNEL *channelInfo = &(pAdapter->mvChannel[channelIndex]);
1152 int dmaActive = pSataChannel->queueCommandsEnabled;
1153 int ret = 0;
1154
1155 if (dmaActive) {
1156 mvSataDisableChannelDma(pSataAdapter, channelIndex);
1157 mvSataFlushDmaQueue(pSataAdapter,channelIndex,MV_FLUSH_TYPE_CALLBACK);
1158 }
1159
1160 if ((pSataChannel->identifyDevice[82] & (0x20))) {
1161 if (enable) {
1162 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex,
1163 MV_ATA_SET_FEATURES_ENABLE_WCACHE, 0, 0, 0, 0))
1164 {
1165 channelInfo->writeCacheEnabled = MV_TRUE;
1166 ret = 1;
1167 }
1168 }
1169 else {
1170 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex,
1171 MV_ATA_SET_FEATURES_DISABLE_WCACHE, 0, 0, 0, 0))
1172 {
1173 channelInfo->writeCacheEnabled = MV_FALSE;
1174 ret = 1;
1175 }
1176 }
1177 }
1178
1179 if (dmaActive)
1180 mvSataEnableChannelDma(pSataAdapter,channelIndex);
1181 return ret;
1182 }
1183
fDeSetReadAhead(PDevice pDev,int enable)1184 int HPTLIBAPI fDeSetReadAhead(PDevice pDev, int enable)
1185 {
1186 MV_SATA_CHANNEL *pSataChannel = pDev->mv;
1187 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter;
1188 MV_U8 channelIndex = pSataChannel->channelNumber;
1189 IAL_ADAPTER_T *pAdapter = pSataAdapter->IALData;
1190 MV_CHANNEL *channelInfo = &(pAdapter->mvChannel[channelIndex]);
1191 int dmaActive = pSataChannel->queueCommandsEnabled;
1192 int ret = 0;
1193
1194 if (dmaActive) {
1195 mvSataDisableChannelDma(pSataAdapter, channelIndex);
1196 mvSataFlushDmaQueue(pSataAdapter,channelIndex,MV_FLUSH_TYPE_CALLBACK);
1197 }
1198
1199 if ((pSataChannel->identifyDevice[82] & (0x40))) {
1200 if (enable) {
1201 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex,
1202 MV_ATA_SET_FEATURES_ENABLE_RLA, 0, 0, 0, 0))
1203 {
1204 channelInfo->readAheadEnabled = MV_TRUE;
1205 ret = 1;
1206 }
1207 }
1208 else {
1209 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex,
1210 MV_ATA_SET_FEATURES_DISABLE_RLA, 0, 0, 0, 0))
1211 {
1212 channelInfo->readAheadEnabled = MV_FALSE;
1213 ret = 1;
1214 }
1215 }
1216 }
1217
1218 if (dmaActive)
1219 mvSataEnableChannelDma(pSataAdapter,channelIndex);
1220 return ret;
1221 }
1222
1223 #ifdef SUPPORT_ARRAY
1224 #define IdeRegisterVDevice fCheckArray
1225 #else
1226 void
IdeRegisterVDevice(PDevice pDev)1227 IdeRegisterVDevice(PDevice pDev)
1228 {
1229 PVDevice pVDev = Map2pVDevice(pDev);
1230
1231 pVDev->VDeviceType = pDev->df_atapi? VD_ATAPI :
1232 pDev->df_removable_drive? VD_REMOVABLE : VD_SINGLE_DISK;
1233 pVDev->vf_online = 1;
1234 pVDev->VDeviceCapacity = pDev->dDeRealCapacity;
1235 pVDev->pfnSendCommand = pfnSendCommand[pVDev->VDeviceType];
1236 pVDev->pfnDeviceFailed = pfnDeviceFailed[pVDev->VDeviceType];
1237 }
1238 #endif
1239
1240 static __inline PBUS_DMAMAP
dmamap_get(struct IALAdapter * pAdapter)1241 dmamap_get(struct IALAdapter * pAdapter)
1242 {
1243 PBUS_DMAMAP p = pAdapter->pbus_dmamap_list;
1244 if (p)
1245 pAdapter->pbus_dmamap_list = p-> next;
1246 return p;
1247 }
1248
1249 static __inline void
dmamap_put(PBUS_DMAMAP p)1250 dmamap_put(PBUS_DMAMAP p)
1251 {
1252 p->next = p->pAdapter->pbus_dmamap_list;
1253 p->pAdapter->pbus_dmamap_list = p;
1254 }
1255
1256 /*Since mtx not provide the initialize when declare, so we Final init here to initialize the global mtx*/
1257 #define override_kernel_driver()
1258
hpt_init(void * dummy)1259 static void hpt_init(void *dummy)
1260 {
1261 override_kernel_driver();
1262 lockinit(&driver_lock, "hptsleeplock", 0, LK_CANRECURSE);
1263 }
1264 SYSINIT(hptinit, SI_SUB_CONFIGURE, SI_ORDER_FIRST, hpt_init, NULL);
1265
1266 static int num_adapters = 0;
1267 static int
init_adapter(IAL_ADAPTER_T * pAdapter)1268 init_adapter(IAL_ADAPTER_T *pAdapter)
1269 {
1270 PVBus _vbus_p = &pAdapter->VBus;
1271 MV_SATA_ADAPTER *pMvSataAdapter;
1272 int i, channel, rid;
1273
1274 PVDevice pVDev;
1275
1276 lock_driver();
1277
1278 pAdapter->next = 0;
1279
1280 if(gIal_Adapter == NULL){
1281 gIal_Adapter = pAdapter;
1282 pCurAdapter = gIal_Adapter;
1283 }
1284 else {
1285 pCurAdapter->next = pAdapter;
1286 pCurAdapter = pAdapter;
1287 }
1288
1289 pAdapter->outstandingCommands = 0;
1290
1291 pMvSataAdapter = &(pAdapter->mvSataAdapter);
1292 _vbus_p->OsExt = (void *)pAdapter;
1293 pMvSataAdapter->IALData = pAdapter;
1294
1295 if (bus_dma_tag_create(NULL,/* parent */
1296 4, /* alignment */
1297 BUS_SPACE_MAXADDR_32BIT+1, /* boundary */
1298 BUS_SPACE_MAXADDR, /* lowaddr */
1299 BUS_SPACE_MAXADDR, /* highaddr */
1300 PAGE_SIZE * (MAX_SG_DESCRIPTORS-1), /* maxsize */
1301 MAX_SG_DESCRIPTORS, /* nsegments */
1302 0x10000, /* maxsegsize */
1303 BUS_DMA_WAITOK, /* flags */
1304 &pAdapter->io_dma_parent /* tag */))
1305 {
1306 return ENXIO;
1307 }
1308
1309
1310 if (hptmv_allocate_edma_queues(pAdapter))
1311 {
1312 MV_ERROR("RR18xx: Failed to allocate memory for EDMA queues\n");
1313 unlock_driver();
1314 return ENOMEM;
1315 }
1316
1317 /* also map EPROM address */
1318 rid = 0x10;
1319 if (!(pAdapter->mem_res = bus_alloc_resource(pAdapter->hpt_dev, SYS_RES_MEMORY, &rid,
1320 0, ~0, MV_SATA_PCI_BAR0_SPACE_SIZE+0x40000, RF_ACTIVE))
1321 ||
1322 !(pMvSataAdapter->adapterIoBaseAddress = rman_get_virtual(pAdapter->mem_res)))
1323 {
1324 MV_ERROR("RR18xx: Failed to remap memory space\n");
1325 hptmv_free_edma_queues(pAdapter);
1326 unlock_driver();
1327 return ENXIO;
1328 }
1329 else
1330 {
1331 KdPrint(("RR18xx: io base address 0x%p\n", pMvSataAdapter->adapterIoBaseAddress));
1332 }
1333
1334 pMvSataAdapter->adapterId = num_adapters++;
1335 /* get the revision ID */
1336 pMvSataAdapter->pciConfigRevisionId = pci_read_config(pAdapter->hpt_dev, PCIR_REVID, 1);
1337 pMvSataAdapter->pciConfigDeviceId = pci_get_device(pAdapter->hpt_dev);
1338
1339 /* init RR18xx */
1340 pMvSataAdapter->intCoalThre[0]= 1;
1341 pMvSataAdapter->intCoalThre[1]= 1;
1342 pMvSataAdapter->intTimeThre[0] = 1;
1343 pMvSataAdapter->intTimeThre[1] = 1;
1344 pMvSataAdapter->pciCommand = 0x0107E371;
1345 pMvSataAdapter->pciSerrMask = 0xd77fe6ul;
1346 pMvSataAdapter->pciInterruptMask = 0xd77fe6ul;
1347 pMvSataAdapter->mvSataEventNotify = hptmv_event_notify;
1348
1349 if (mvSataInitAdapter(pMvSataAdapter) == MV_FALSE)
1350 {
1351 MV_ERROR("RR18xx[%d]: core failed to initialize the adapter\n",
1352 pMvSataAdapter->adapterId);
1353 unregister:
1354 bus_release_resource(pAdapter->hpt_dev, SYS_RES_MEMORY, rid, pAdapter->mem_res);
1355 hptmv_free_edma_queues(pAdapter);
1356 unlock_driver();
1357 return ENXIO;
1358 }
1359 pAdapter->ver_601 = pMvSataAdapter->pcbVersion;
1360
1361 #ifndef FOR_DEMO
1362 set_fail_leds(pMvSataAdapter, 0);
1363 #endif
1364
1365 /* setup command blocks */
1366 KdPrint(("Allocate command blocks\n"));
1367 _vbus_(pFreeCommands) = NULL;
1368 pAdapter->pCommandBlocks =
1369 kmalloc(sizeof(struct _Command) * MAX_COMMAND_BLOCKS_FOR_EACH_VBUS, M_DEVBUF, M_NOWAIT);
1370 KdPrint(("pCommandBlocks:%p\n",pAdapter->pCommandBlocks));
1371 if (!pAdapter->pCommandBlocks) {
1372 MV_ERROR("insufficient memory\n");
1373 goto unregister;
1374 }
1375
1376 for (i=0; i<MAX_COMMAND_BLOCKS_FOR_EACH_VBUS; i++) {
1377 FreeCommand(_VBUS_P &(pAdapter->pCommandBlocks[i]));
1378 }
1379
1380 /*Set up the bus_dmamap*/
1381 pAdapter->pbus_dmamap = (PBUS_DMAMAP)kmalloc (sizeof(struct _BUS_DMAMAP) * MAX_QUEUE_COMM, M_DEVBUF, M_NOWAIT);
1382 if(!pAdapter->pbus_dmamap) {
1383 MV_ERROR("insufficient memory\n");
1384 kfree(pAdapter->pCommandBlocks, M_DEVBUF);
1385 goto unregister;
1386 }
1387
1388 memset((void *)pAdapter->pbus_dmamap, 0, sizeof(struct _BUS_DMAMAP) * MAX_QUEUE_COMM);
1389 pAdapter->pbus_dmamap_list = 0;
1390 for (i=0; i < MAX_QUEUE_COMM; i++) {
1391 PBUS_DMAMAP pmap = &(pAdapter->pbus_dmamap[i]);
1392 pmap->pAdapter = pAdapter;
1393 dmamap_put(pmap);
1394
1395 if(bus_dmamap_create(pAdapter->io_dma_parent, 0, &pmap->dma_map)) {
1396 MV_ERROR("Can not allocate dma map\n");
1397 kfree(pAdapter->pCommandBlocks, M_DEVBUF);
1398 kfree(pAdapter->pbus_dmamap, M_DEVBUF);
1399 goto unregister;
1400 }
1401 }
1402 /* setup PRD Tables */
1403 KdPrint(("Allocate PRD Tables\n"));
1404 pAdapter->pFreePRDLink = 0;
1405
1406 pAdapter->prdTableAddr = (PUCHAR)contigmalloc(
1407 (PRD_ENTRIES_SIZE*PRD_TABLES_FOR_VBUS + 32), M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul);
1408
1409 KdPrint(("prdTableAddr:%p\n",pAdapter->prdTableAddr));
1410 if (!pAdapter->prdTableAddr) {
1411 MV_ERROR("insufficient PRD Tables\n");
1412 goto unregister;
1413 }
1414 pAdapter->prdTableAlignedAddr = (PUCHAR)(((ULONG_PTR)pAdapter->prdTableAddr + 0x1f) & ~(ULONG_PTR)0x1fL);
1415 {
1416 PUCHAR PRDTable = pAdapter->prdTableAlignedAddr;
1417 for (i=0; i<PRD_TABLES_FOR_VBUS; i++)
1418 {
1419 /* KdPrint(("i=%d,pAdapter->pFreePRDLink=%p\n",i,pAdapter->pFreePRDLink)); */
1420 FreePRDTable(pAdapter, PRDTable);
1421 PRDTable += PRD_ENTRIES_SIZE;
1422 }
1423 }
1424
1425 /* enable the adapter interrupts */
1426
1427 /* configure and start the connected channels*/
1428 for (channel = 0; channel < MV_SATA_CHANNELS_NUM; channel++)
1429 {
1430 pAdapter->mvChannel[channel].online = MV_FALSE;
1431 if (mvSataIsStorageDeviceConnected(pMvSataAdapter, channel)
1432 == MV_TRUE)
1433 {
1434 KdPrint(("RR18xx[%d]: channel %d is connected\n",
1435 pMvSataAdapter->adapterId, channel));
1436
1437 if (hptmv_init_channel(pAdapter, channel) == 0)
1438 {
1439 if (mvSataConfigureChannel(pMvSataAdapter, channel) == MV_FALSE)
1440 {
1441 MV_ERROR("RR18xx[%d]: Failed to configure channel"
1442 " %d\n",pMvSataAdapter->adapterId, channel);
1443 hptmv_free_channel(pAdapter, channel);
1444 }
1445 else
1446 {
1447 if (start_channel(pAdapter, channel))
1448 {
1449 MV_ERROR("RR18xx[%d]: Failed to start channel,"
1450 " channel=%d\n",pMvSataAdapter->adapterId,
1451 channel);
1452 hptmv_free_channel(pAdapter, channel);
1453 }
1454 pAdapter->mvChannel[channel].online = MV_TRUE;
1455 /* mvSataChannelSetEdmaLoopBackMode(pMvSataAdapter,
1456 channel,
1457 MV_TRUE);*/
1458 }
1459 }
1460 }
1461 KdPrint(("pAdapter->mvChannel[channel].online:%x, channel:%d\n",
1462 pAdapter->mvChannel[channel].online, channel));
1463 }
1464
1465 #ifdef SUPPORT_ARRAY
1466 for(i = MAX_ARRAY_DEVICE - 1; i >= 0; i--) {
1467 pVDev = ArrayTables(i);
1468 mArFreeArrayTable(pVDev);
1469 }
1470 #endif
1471
1472 KdPrint(("Initialize Devices\n"));
1473 for (channel = 0; channel < MV_SATA_CHANNELS_NUM; channel++) {
1474 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channel];
1475 if (pMvSataChannel) {
1476 init_vdev_params(pAdapter, channel);
1477 IdeRegisterVDevice(&pAdapter->VDevices[channel].u.disk);
1478 }
1479 }
1480 #ifdef SUPPORT_ARRAY
1481 CheckArrayCritical(_VBUS_P0);
1482 #endif
1483 _vbus_p->nInstances = 1;
1484 fRegisterVdevice(pAdapter);
1485
1486 for (channel=0;channel<MV_SATA_CHANNELS_NUM;channel++) {
1487 pVDev = _vbus_p->pVDevice[channel];
1488 if (pVDev && pVDev->vf_online)
1489 fCheckBootable(pVDev);
1490 }
1491
1492 #if defined(SUPPORT_ARRAY) && defined(_RAID5N_)
1493 init_raid5_memory(_VBUS_P0);
1494 _vbus_(r5).enable_write_back = 1;
1495 kprintf("RR18xx: RAID5 write-back %s\n", _vbus_(r5).enable_write_back? "enabled" : "disabled");
1496 #endif
1497
1498 mvSataUnmaskAdapterInterrupt(pMvSataAdapter);
1499 unlock_driver();
1500 return 0;
1501 }
1502
1503 int
MvSataResetChannel(MV_SATA_ADAPTER * pMvSataAdapter,MV_U8 channel)1504 MvSataResetChannel(MV_SATA_ADAPTER *pMvSataAdapter, MV_U8 channel)
1505 {
1506 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)pMvSataAdapter->IALData;
1507
1508 mvSataDisableChannelDma(pMvSataAdapter, channel);
1509 /* Flush pending commands */
1510 mvSataFlushDmaQueue (pMvSataAdapter, channel, MV_FLUSH_TYPE_CALLBACK);
1511
1512 /* Software reset channel */
1513 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channel) == MV_FALSE)
1514 {
1515 MV_ERROR("RR18xx [%d,%d]: failed to perform Software reset\n",
1516 pMvSataAdapter->adapterId, channel);
1517 hptmv_free_channel(pAdapter, channel);
1518 return -1;
1519 }
1520
1521 /* Hardware reset channel */
1522 if (mvSataChannelHardReset(pMvSataAdapter, channel)== MV_FALSE)
1523 {
1524 MV_ERROR("RR18xx [%d,%d] Failed to Hard reser the SATA channel\n",
1525 pMvSataAdapter->adapterId, channel);
1526 hptmv_free_channel(pAdapter, channel);
1527 return -1;
1528 }
1529
1530 if (mvSataIsStorageDeviceConnected(pMvSataAdapter, channel) == MV_FALSE)
1531 {
1532 MV_ERROR("RR18xx [%d,%d] Failed to Connect Device\n",
1533 pMvSataAdapter->adapterId, channel);
1534 hptmv_free_channel(pAdapter, channel);
1535 return -1;
1536 }else
1537 {
1538 MV_ERROR("channel %d: perform recalibrate command", channel);
1539 if (!mvStorageDevATAExecuteNonUDMACommand(pMvSataAdapter, channel,
1540 MV_NON_UDMA_PROTOCOL_NON_DATA,
1541 MV_FALSE,
1542 NULL, /* pBuffer*/
1543 0, /* count */
1544 0, /*features*/
1545 /* sectorCount */
1546 0,
1547 0, /* lbaLow */
1548 0, /* lbaMid */
1549 /* lbaHigh */
1550 0,
1551 0, /* device */
1552 /* command */
1553 0x10))
1554 MV_ERROR("channel %d: recalibrate failed", channel);
1555
1556 /* Set transfer mode */
1557 if((mvStorageDevATASetFeatures(pMvSataAdapter, channel,
1558 MV_ATA_SET_FEATURES_TRANSFER,
1559 MV_ATA_TRANSFER_PIO_SLOW, 0, 0, 0) == MV_FALSE) ||
1560 (mvStorageDevATASetFeatures(pMvSataAdapter, channel,
1561 MV_ATA_SET_FEATURES_TRANSFER,
1562 pAdapter->mvChannel[channel].maxPioModeSupported, 0, 0, 0) == MV_FALSE) ||
1563 (mvStorageDevATASetFeatures(pMvSataAdapter, channel,
1564 MV_ATA_SET_FEATURES_TRANSFER,
1565 pAdapter->mvChannel[channel].maxUltraDmaModeSupported, 0, 0, 0) == MV_FALSE) )
1566 {
1567 MV_ERROR("channel %d: Set Features failed", channel);
1568 hptmv_free_channel(pAdapter, channel);
1569 return -1;
1570 }
1571 /* Enable EDMA */
1572 if (mvSataEnableChannelDma(pMvSataAdapter, channel) == MV_FALSE)
1573 {
1574 MV_ERROR("Failed to enable DMA, channel=%d", channel);
1575 hptmv_free_channel(pAdapter, channel);
1576 return -1;
1577 }
1578 }
1579 return 0;
1580 }
1581
1582 static int
fResetActiveCommands(PVBus _vbus_p)1583 fResetActiveCommands(PVBus _vbus_p)
1584 {
1585 MV_SATA_ADAPTER *pMvSataAdapter = &((IAL_ADAPTER_T *)_vbus_p->OsExt)->mvSataAdapter;
1586 MV_U8 channel;
1587 for (channel=0;channel< MV_SATA_CHANNELS_NUM;channel++) {
1588 if (pMvSataAdapter->sataChannel[channel] && pMvSataAdapter->sataChannel[channel]->outstandingCommands)
1589 MvSataResetChannel(pMvSataAdapter,channel);
1590 }
1591 return 0;
1592 }
1593
fCompleteAllCommandsSynchronously(PVBus _vbus_p)1594 void fCompleteAllCommandsSynchronously(PVBus _vbus_p)
1595 {
1596 UINT cont;
1597 ULONG ticks = 0;
1598 MV_U8 channel;
1599 MV_SATA_ADAPTER *pMvSataAdapter = &((IAL_ADAPTER_T *)_vbus_p->OsExt)->mvSataAdapter;
1600 MV_SATA_CHANNEL *pMvSataChannel;
1601
1602 do {
1603 check_cmds:
1604 cont = 0;
1605 CheckPendingCall(_VBUS_P0);
1606 #ifdef _RAID5N_
1607 dataxfer_poll();
1608 xor_poll();
1609 #endif
1610 for (channel=0;channel< MV_SATA_CHANNELS_NUM;channel++) {
1611 pMvSataChannel = pMvSataAdapter->sataChannel[channel];
1612 if (pMvSataChannel && pMvSataChannel->outstandingCommands)
1613 {
1614 while (pMvSataChannel->outstandingCommands) {
1615 if (!mvSataInterruptServiceRoutine(pMvSataAdapter)) {
1616 StallExec(1000);
1617 if (ticks++ > 3000) {
1618 MvSataResetChannel(pMvSataAdapter,channel);
1619 goto check_cmds;
1620 }
1621 }
1622 else
1623 ticks = 0;
1624 }
1625 cont = 1;
1626 }
1627 }
1628 } while (cont);
1629 }
1630
1631 void
fResetVBus(_VBUS_ARG0)1632 fResetVBus(_VBUS_ARG0)
1633 {
1634 KdPrint(("fMvResetBus(%p)", _vbus_p));
1635
1636 /* some commands may already finished. */
1637 CheckPendingCall(_VBUS_P0);
1638
1639 fResetActiveCommands(_vbus_p);
1640 /*
1641 * the other pending commands may still be finished successfully.
1642 */
1643 fCompleteAllCommandsSynchronously(_vbus_p);
1644
1645 /* Now there should be no pending commands. No more action needed. */
1646 CheckIdleCall(_VBUS_P0);
1647
1648 KdPrint(("fMvResetBus() done"));
1649 }
1650
1651 /*No rescan function*/
1652 void
fRescanAllDevice(_VBUS_ARG0)1653 fRescanAllDevice(_VBUS_ARG0)
1654 {
1655 }
1656
1657 static MV_BOOLEAN
CommandCompletionCB(MV_SATA_ADAPTER * pMvSataAdapter,MV_U8 channelNum,MV_COMPLETION_TYPE comp_type,MV_VOID_PTR commandId,MV_U16 responseFlags,MV_U32 timeStamp,MV_STORAGE_DEVICE_REGISTERS * registerStruct)1658 CommandCompletionCB(MV_SATA_ADAPTER *pMvSataAdapter,
1659 MV_U8 channelNum,
1660 MV_COMPLETION_TYPE comp_type,
1661 MV_VOID_PTR commandId,
1662 MV_U16 responseFlags,
1663 MV_U32 timeStamp,
1664 MV_STORAGE_DEVICE_REGISTERS *registerStruct)
1665 {
1666 PCommand pCmd = (PCommand) commandId;
1667 _VBUS_INST(pCmd->pVDevice->pVBus)
1668
1669 if (pCmd->uScratch.sata_param.prdAddr)
1670 FreePRDTable(pMvSataAdapter->IALData,pCmd->uScratch.sata_param.prdAddr);
1671
1672 switch (comp_type)
1673 {
1674 case MV_COMPLETION_TYPE_NORMAL:
1675 pCmd->Result = RETURN_SUCCESS;
1676 break;
1677 case MV_COMPLETION_TYPE_ABORT:
1678 pCmd->Result = RETURN_BUS_RESET;
1679 break;
1680 case MV_COMPLETION_TYPE_ERROR:
1681 MV_ERROR("IAL: COMPLETION ERROR, adapter %d, channel %d, flags=%x\n",
1682 pMvSataAdapter->adapterId, channelNum, responseFlags);
1683
1684 if (responseFlags & 4) {
1685 MV_ERROR("ATA regs: error %x, sector count %x, LBA low %x, LBA mid %x,"
1686 " LBA high %x, device %x, status %x\n",
1687 registerStruct->errorRegister,
1688 registerStruct->sectorCountRegister,
1689 registerStruct->lbaLowRegister,
1690 registerStruct->lbaMidRegister,
1691 registerStruct->lbaHighRegister,
1692 registerStruct->deviceRegister,
1693 registerStruct->statusRegister);
1694 }
1695 /*We can't do handleEdmaError directly here, because CommandCompletionCB is called by
1696 * mv's ISR, if we retry the command, than the internel data structure may be destroyed*/
1697 pCmd->uScratch.sata_param.responseFlags = responseFlags;
1698 pCmd->uScratch.sata_param.bIdeStatus = registerStruct->statusRegister;
1699 pCmd->uScratch.sata_param.errorRegister = registerStruct->errorRegister;
1700 pCmd->pVDevice->u.disk.QueueLength--;
1701 CallAfterReturn(_VBUS_P (DPC_PROC)handleEdmaError,pCmd);
1702 return TRUE;
1703
1704 default:
1705 MV_ERROR(" Unknown completion type (%d)\n", comp_type);
1706 return MV_FALSE;
1707 }
1708
1709 if (pCmd->uCmd.Ide.Command == IDE_COMMAND_VERIFY && pCmd->uScratch.sata_param.cmd_priv > 1) {
1710 pCmd->uScratch.sata_param.cmd_priv --;
1711 return TRUE;
1712 }
1713 pCmd->pVDevice->u.disk.QueueLength--;
1714 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1715 return TRUE;
1716 }
1717
1718 void
fDeviceSendCommand(_VBUS_ARG PCommand pCmd)1719 fDeviceSendCommand(_VBUS_ARG PCommand pCmd)
1720 {
1721 MV_SATA_EDMA_PRD_ENTRY *pPRDTable = NULL;
1722 MV_SATA_ADAPTER *pMvSataAdapter;
1723 MV_SATA_CHANNEL *pMvSataChannel;
1724 PVDevice pVDevice = pCmd->pVDevice;
1725 PDevice pDevice = &pVDevice->u.disk;
1726 LBA_T Lba = pCmd->uCmd.Ide.Lba;
1727 USHORT nSector = pCmd->uCmd.Ide.nSectors;
1728
1729 MV_QUEUE_COMMAND_RESULT result;
1730 MV_QUEUE_COMMAND_INFO commandInfo;
1731 MV_UDMA_COMMAND_PARAMS *pUdmaParams = &commandInfo.commandParams.udmaCommand;
1732 MV_NONE_UDMA_COMMAND_PARAMS *pNoUdmaParams = &commandInfo.commandParams.NoneUdmaCommand;
1733
1734 MV_BOOLEAN is48bit;
1735 MV_U8 channel;
1736 int i=0;
1737
1738 DECLARE_BUFFER(FPSCAT_GATH, tmpSg);
1739
1740 if (!pDevice->df_on_line) {
1741 MV_ERROR("Device is offline");
1742 pCmd->Result = RETURN_BAD_DEVICE;
1743 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1744 return;
1745 }
1746
1747 pDevice->HeadPosition = pCmd->uCmd.Ide.Lba + pCmd->uCmd.Ide.nSectors;
1748 pMvSataChannel = pDevice->mv;
1749 pMvSataAdapter = pMvSataChannel->mvSataAdapter;
1750 channel = pMvSataChannel->channelNumber;
1751
1752 /* old RAID0 has hidden lba. Remember to clear dDeHiddenLba when delete array! */
1753 Lba += pDevice->dDeHiddenLba;
1754 /* check LBA */
1755 if (Lba+nSector-1 > pDevice->dDeRealCapacity) {
1756 pCmd->Result = RETURN_INVALID_REQUEST;
1757 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1758 return;
1759 }
1760
1761 /*
1762 * always use 48bit LBA if drive supports it.
1763 * Some Seagate drives report error if you use a 28-bit command
1764 * to access sector 0xfffffff.
1765 */
1766 is48bit = pMvSataChannel->lba48Address;
1767
1768 switch (pCmd->uCmd.Ide.Command)
1769 {
1770 case IDE_COMMAND_READ:
1771 case IDE_COMMAND_WRITE:
1772 if (pDevice->bDeModeSetting<8) goto pio;
1773
1774 commandInfo.type = MV_QUEUED_COMMAND_TYPE_UDMA;
1775 pUdmaParams->isEXT = is48bit;
1776 pUdmaParams->numOfSectors = nSector;
1777 pUdmaParams->lowLBAAddress = Lba;
1778 pUdmaParams->highLBAAddress = 0;
1779 pUdmaParams->prdHighAddr = 0;
1780 pUdmaParams->callBack = CommandCompletionCB;
1781 pUdmaParams->commandId = (MV_VOID_PTR )pCmd;
1782 if(pCmd->uCmd.Ide.Command == IDE_COMMAND_READ)
1783 pUdmaParams->readWrite = MV_UDMA_TYPE_READ;
1784 else
1785 pUdmaParams->readWrite = MV_UDMA_TYPE_WRITE;
1786
1787 if (pCmd->pSgTable && pCmd->cf_physical_sg) {
1788 FPSCAT_GATH sg1=tmpSg, sg2=pCmd->pSgTable;
1789 do { *sg1++=*sg2; } while ((sg2++->wSgFlag & SG_FLAG_EOT)==0);
1790 }
1791 else {
1792 if (!pCmd->pfnBuildSgl || !pCmd->pfnBuildSgl(_VBUS_P pCmd, tmpSg, 0)) {
1793 pio:
1794 mvSataDisableChannelDma(pMvSataAdapter, channel);
1795 mvSataFlushDmaQueue(pMvSataAdapter, channel, MV_FLUSH_TYPE_CALLBACK);
1796
1797 if (pCmd->pSgTable && pCmd->cf_physical_sg==0) {
1798 FPSCAT_GATH sg1=tmpSg, sg2=pCmd->pSgTable;
1799 do { *sg1++=*sg2; } while ((sg2++->wSgFlag & SG_FLAG_EOT)==0);
1800 }
1801 else {
1802 if (!pCmd->pfnBuildSgl || !pCmd->pfnBuildSgl(_VBUS_P pCmd, tmpSg, 1)) {
1803 pCmd->Result = RETURN_NEED_LOGICAL_SG;
1804 goto finish_cmd;
1805 }
1806 }
1807
1808 do {
1809 ULONG size = tmpSg->wSgSize? tmpSg->wSgSize : 0x10000;
1810 ULONG_PTR addr = tmpSg->dSgAddress;
1811 if (size & 0x1ff) {
1812 pCmd->Result = RETURN_INVALID_REQUEST;
1813 goto finish_cmd;
1814 }
1815 if (mvStorageDevATAExecuteNonUDMACommand(pMvSataAdapter, channel,
1816 (pCmd->cf_data_out)?MV_NON_UDMA_PROTOCOL_PIO_DATA_OUT:MV_NON_UDMA_PROTOCOL_PIO_DATA_IN,
1817 is48bit,
1818 (MV_U16_PTR)addr,
1819 size >> 1, /* count */
1820 0, /* features N/A */
1821 (MV_U16)(size>>9), /*sector count*/
1822 (MV_U16)( (is48bit? (MV_U16)((Lba >> 16) & 0xFF00) : 0 ) | (UCHAR)(Lba & 0xFF) ), /*lbalow*/
1823 (MV_U16)((Lba >> 8) & 0xFF), /* lbaMid */
1824 (MV_U16)((Lba >> 16) & 0xFF),/* lbaHigh */
1825 (MV_U8)(0x40 | (is48bit ? 0 : (UCHAR)(Lba >> 24) & 0xFF )),/* device */
1826 (MV_U8)(is48bit ? (pCmd->cf_data_in?IDE_COMMAND_READ_EXT:IDE_COMMAND_WRITE_EXT):pCmd->uCmd.Ide.Command)
1827 )==MV_FALSE)
1828 {
1829 pCmd->Result = RETURN_IDE_ERROR;
1830 goto finish_cmd;
1831 }
1832 Lba += size>>9;
1833 if(Lba & 0xF0000000) is48bit = MV_TRUE;
1834 }
1835 while ((tmpSg++->wSgFlag & SG_FLAG_EOT)==0);
1836 pCmd->Result = RETURN_SUCCESS;
1837 finish_cmd:
1838 mvSataEnableChannelDma(pMvSataAdapter,channel);
1839 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1840 return;
1841 }
1842 }
1843
1844 pPRDTable = (MV_SATA_EDMA_PRD_ENTRY *) AllocatePRDTable(pMvSataAdapter->IALData);
1845 KdPrint(("pPRDTable:%p\n",pPRDTable));
1846 if (!pPRDTable) {
1847 pCmd->Result = RETURN_DEVICE_BUSY;
1848 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1849 HPT_ASSERT(0);
1850 return;
1851 }
1852
1853 do{
1854 pPRDTable[i].highBaseAddr = (sizeof(tmpSg->dSgAddress)>4 ? (MV_U32)(tmpSg->dSgAddress>>32) : 0);
1855 pPRDTable[i].flags = (MV_U16)tmpSg->wSgFlag;
1856 pPRDTable[i].byteCount = (MV_U16)tmpSg->wSgSize;
1857 pPRDTable[i].lowBaseAddr = (MV_U32)tmpSg->dSgAddress;
1858 pPRDTable[i].reserved = 0;
1859 i++;
1860 }while((tmpSg++->wSgFlag & SG_FLAG_EOT)==0);
1861
1862 pUdmaParams->prdLowAddr = (ULONG)fOsPhysicalAddress(pPRDTable);
1863 if ((pUdmaParams->numOfSectors == 256) && (pMvSataChannel->lba48Address == MV_FALSE)) {
1864 pUdmaParams->numOfSectors = 0;
1865 }
1866
1867 pCmd->uScratch.sata_param.prdAddr = (PVOID)pPRDTable;
1868
1869 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo);
1870
1871 if (result != MV_QUEUE_COMMAND_RESULT_OK)
1872 {
1873 queue_failed:
1874 switch (result)
1875 {
1876 case MV_QUEUE_COMMAND_RESULT_BAD_LBA_ADDRESS:
1877 MV_ERROR("IAL Error: Edma Queue command failed. Bad LBA "
1878 "LBA[31:0](0x%08x)\n", pUdmaParams->lowLBAAddress);
1879 pCmd->Result = RETURN_IDE_ERROR;
1880 break;
1881 case MV_QUEUE_COMMAND_RESULT_QUEUED_MODE_DISABLED:
1882 MV_ERROR("IAL Error: Edma Queue command failed. EDMA"
1883 " disabled adapter %d channel %d\n",
1884 pMvSataAdapter->adapterId, channel);
1885 mvSataEnableChannelDma(pMvSataAdapter,channel);
1886 pCmd->Result = RETURN_IDE_ERROR;
1887 break;
1888 case MV_QUEUE_COMMAND_RESULT_FULL:
1889 MV_ERROR("IAL Error: Edma Queue command failed. Queue is"
1890 " Full adapter %d channel %d\n",
1891 pMvSataAdapter->adapterId, channel);
1892 pCmd->Result = RETURN_DEVICE_BUSY;
1893 break;
1894 case MV_QUEUE_COMMAND_RESULT_BAD_PARAMS:
1895 MV_ERROR("IAL Error: Edma Queue command failed. (Bad "
1896 "Params), pMvSataAdapter: %p, pSataChannel: %p.\n",
1897 pMvSataAdapter, pMvSataAdapter->sataChannel[channel]);
1898 pCmd->Result = RETURN_IDE_ERROR;
1899 break;
1900 default:
1901 MV_ERROR("IAL Error: Bad result value (%d) from queue"
1902 " command\n", result);
1903 pCmd->Result = RETURN_IDE_ERROR;
1904 }
1905 if(pPRDTable)
1906 FreePRDTable(pMvSataAdapter->IALData,pPRDTable);
1907 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1908 }
1909 pDevice->QueueLength++;
1910 return;
1911
1912 case IDE_COMMAND_VERIFY:
1913 commandInfo.type = MV_QUEUED_COMMAND_TYPE_NONE_UDMA;
1914 pNoUdmaParams->bufPtr = NULL;
1915 pNoUdmaParams->callBack = CommandCompletionCB;
1916 pNoUdmaParams->commandId = (MV_VOID_PTR)pCmd;
1917 pNoUdmaParams->count = 0;
1918 pNoUdmaParams->features = 0;
1919 pNoUdmaParams->protocolType = MV_NON_UDMA_PROTOCOL_NON_DATA;
1920
1921 pCmd->uScratch.sata_param.cmd_priv = 1;
1922 if (pMvSataChannel->lba48Address == MV_TRUE){
1923 pNoUdmaParams->command = MV_ATA_COMMAND_READ_VERIFY_SECTORS_EXT;
1924 pNoUdmaParams->isEXT = MV_TRUE;
1925 pNoUdmaParams->lbaHigh = (MV_U16)((Lba & 0xff0000) >> 16);
1926 pNoUdmaParams->lbaMid = (MV_U16)((Lba & 0xff00) >> 8);
1927 pNoUdmaParams->lbaLow =
1928 (MV_U16)(((Lba & 0xff000000) >> 16)| (Lba & 0xff));
1929 pNoUdmaParams->sectorCount = nSector;
1930 pNoUdmaParams->device = 0x40;
1931 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo);
1932 if (result != MV_QUEUE_COMMAND_RESULT_OK){
1933 goto queue_failed;
1934 }
1935 return;
1936 }
1937 else{
1938 pNoUdmaParams->command = MV_ATA_COMMAND_READ_VERIFY_SECTORS;
1939 pNoUdmaParams->isEXT = MV_FALSE;
1940 pNoUdmaParams->lbaHigh = (MV_U16)((Lba & 0xff0000) >> 16);
1941 pNoUdmaParams->lbaMid = (MV_U16)((Lba & 0xff00) >> 8);
1942 pNoUdmaParams->lbaLow = (MV_U16)(Lba & 0xff);
1943 pNoUdmaParams->sectorCount = 0xff & nSector;
1944 pNoUdmaParams->device = (MV_U8)(0x40 |
1945 ((Lba & 0xf000000) >> 24));
1946 pNoUdmaParams->callBack = CommandCompletionCB;
1947 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo);
1948 /*FIXME: how about the commands already queued? but marvel also forgets to consider this*/
1949 if (result != MV_QUEUE_COMMAND_RESULT_OK){
1950 goto queue_failed;
1951 }
1952 }
1953 break;
1954 default:
1955 pCmd->Result = RETURN_INVALID_REQUEST;
1956 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1957 break;
1958 }
1959 }
1960
1961 /**********************************************************
1962 *
1963 * Probe the hostadapter.
1964 *
1965 **********************************************************/
1966 static int
hpt_probe(device_t dev)1967 hpt_probe(device_t dev)
1968 {
1969 if ((pci_get_vendor(dev) == MV_SATA_VENDOR_ID) &&
1970 (pci_get_device(dev) == MV_SATA_DEVICE_ID_5081
1971 #ifdef FOR_DEMO
1972 || pci_get_device(dev) == MV_SATA_DEVICE_ID_5080
1973 #endif
1974 ))
1975 {
1976 KdPrintI((CONTROLLER_NAME " found\n"));
1977 device_set_desc(dev, CONTROLLER_NAME);
1978 return 0;
1979 }
1980 else
1981 return(ENXIO);
1982 }
1983
1984 /***********************************************************
1985 *
1986 * Auto configuration: attach and init a host adapter.
1987 *
1988 ***********************************************************/
1989 static int
hpt_attach(device_t dev)1990 hpt_attach(device_t dev)
1991 {
1992 IAL_ADAPTER_T * pAdapter = device_get_softc(dev);
1993 int rid;
1994 union ccb *ccb;
1995 struct cam_devq *devq;
1996 struct cam_sim *hpt_vsim;
1997
1998 kprintf("%s Version %s \n", DRIVER_NAME, DRIVER_VERSION);
1999
2000 if (!pAdapter)
2001 {
2002 pAdapter = (IAL_ADAPTER_T *)kmalloc(sizeof (IAL_ADAPTER_T), M_DEVBUF, M_NOWAIT);
2003 device_set_softc(dev, (void *)pAdapter);
2004 }
2005
2006 if (!pAdapter) return (ENOMEM);
2007 bzero(pAdapter, sizeof(IAL_ADAPTER_T));
2008
2009 pAdapter->hpt_dev = dev;
2010
2011 rid = init_adapter(pAdapter);
2012 if (rid)
2013 return rid;
2014
2015 rid = 0;
2016 if ((pAdapter->hpt_irq = bus_alloc_resource(pAdapter->hpt_dev, SYS_RES_IRQ, &rid, 0, ~0ul, 1, RF_SHAREABLE | RF_ACTIVE)) == NULL)
2017 {
2018 hpt_printk(("can't allocate interrupt\n"));
2019 return(ENXIO);
2020 }
2021
2022 if (bus_setup_intr(pAdapter->hpt_dev, pAdapter->hpt_irq, 0,
2023 hpt_intr, pAdapter, &pAdapter->hpt_intr, NULL))
2024 {
2025 hpt_printk(("can't set up interrupt\n"));
2026 kfree(pAdapter, M_DEVBUF);
2027 return(ENXIO);
2028 }
2029
2030 ccb = xpt_alloc_ccb();
2031 ccb->ccb_h.pinfo.priority = 1;
2032 ccb->ccb_h.pinfo.index = CAM_UNQUEUED_INDEX;
2033
2034 /*
2035 * Create the device queue for our SIM(s).
2036 */
2037 if((devq = cam_simq_alloc(8/*MAX_QUEUE_COMM*/)) == NULL)
2038 {
2039 KdPrint(("ENXIO\n"));
2040 return ENOMEM;
2041 }
2042
2043 /*
2044 * Construct our SIM entry
2045 */
2046 hpt_vsim = cam_sim_alloc(hpt_action, hpt_poll, __str(PROC_DIR_NAME),
2047 pAdapter, device_get_unit(pAdapter->hpt_dev), &sim_mplock, 1, 8, devq);
2048 cam_simq_release(devq);
2049 if (hpt_vsim == NULL) {
2050 return ENOMEM;
2051 }
2052
2053 if (xpt_bus_register(hpt_vsim, 0) != CAM_SUCCESS)
2054 {
2055 cam_sim_free(hpt_vsim);
2056 hpt_vsim = NULL;
2057 return ENXIO;
2058 }
2059
2060 if(xpt_create_path(&pAdapter->path, /*periph */ NULL,
2061 cam_sim_path(hpt_vsim), CAM_TARGET_WILDCARD,
2062 CAM_LUN_WILDCARD) != CAM_REQ_CMP)
2063 {
2064 xpt_bus_deregister(cam_sim_path(hpt_vsim));
2065 cam_sim_free(hpt_vsim);
2066 hpt_vsim = NULL;
2067 return ENXIO;
2068 }
2069
2070 xpt_setup_ccb(&ccb->ccb_h, pAdapter->path, /*priority*/5);
2071 ccb->ccb_h.func_code = XPT_SASYNC_CB;
2072 ccb->csa.event_enable = AC_LOST_DEVICE;
2073 ccb->csa.callback = hpt_async;
2074 ccb->csa.callback_arg = hpt_vsim;
2075 xpt_action(ccb);
2076 xpt_free_ccb(&ccb->ccb_h);
2077
2078 callout_init(&pAdapter->event_timer_connect);
2079 callout_init(&pAdapter->event_timer_disconnect);
2080
2081 if (device_get_unit(dev) == 0) {
2082 /* Start the work thread. XXX */
2083 launch_worker_thread();
2084
2085 /*
2086 * hpt_worker_thread needs to be suspended after shutdown
2087 * sync, when fs sync finished.
2088 */
2089 pAdapter->eh = EVENTHANDLER_REGISTER(shutdown_post_sync,
2090 shutdown_kproc, hptdaemonproc, SHUTDOWN_PRI_FIRST);
2091 }
2092
2093 return 0;
2094 }
2095
2096 static int
hpt_detach(device_t dev)2097 hpt_detach(device_t dev)
2098 {
2099 return (EBUSY);
2100 }
2101
2102
2103 /***************************************************************
2104 * The poll function is used to simulate the interrupt when
2105 * the interrupt subsystem is not functioning.
2106 *
2107 ***************************************************************/
2108 static void
hpt_poll(struct cam_sim * sim)2109 hpt_poll(struct cam_sim *sim)
2110 {
2111 hpt_intr((void *)cam_sim_softc(sim));
2112 }
2113
2114 /****************************************************************
2115 * Name: hpt_intr
2116 * Description: Interrupt handler.
2117 ****************************************************************/
2118 static void
hpt_intr(void * arg)2119 hpt_intr(void *arg)
2120 {
2121 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)arg;
2122
2123 lock_driver();
2124 /* KdPrintI(("----- Entering Isr() -----\n")); */
2125 if (mvSataInterruptServiceRoutine(&pAdapter->mvSataAdapter) == MV_TRUE)
2126 {
2127 _VBUS_INST(&pAdapter->VBus)
2128 CheckPendingCall(_VBUS_P0);
2129 }
2130
2131 /* KdPrintI(("----- Leaving Isr() -----\n")); */
2132 unlock_driver();
2133 }
2134
2135 /**********************************************************
2136 * Asynchronous Events
2137 *********************************************************/
2138 #if (!defined(UNREFERENCED_PARAMETER))
2139 #define UNREFERENCED_PARAMETER(x) (void)(x)
2140 #endif
2141
2142 static void
hpt_async(void * callback_arg,u_int32_t code,struct cam_path * path,void * arg)2143 hpt_async(void * callback_arg, u_int32_t code, struct cam_path * path,
2144 void * arg)
2145 {
2146 /* debug XXXX */
2147 panic("Here");
2148 UNREFERENCED_PARAMETER(callback_arg);
2149 UNREFERENCED_PARAMETER(code);
2150 UNREFERENCED_PARAMETER(path);
2151 UNREFERENCED_PARAMETER(arg);
2152
2153 }
2154
2155 static void
FlushAdapter(IAL_ADAPTER_T * pAdapter)2156 FlushAdapter(IAL_ADAPTER_T *pAdapter)
2157 {
2158 int i;
2159
2160 hpt_printk(("flush all devices\n"));
2161
2162 /* flush all devices */
2163 for (i=0; i<MAX_VDEVICE_PER_VBUS; i++) {
2164 PVDevice pVDev = pAdapter->VBus.pVDevice[i];
2165 if(pVDev) fFlushVDev(pVDev);
2166 }
2167 }
2168
2169 static int
hpt_shutdown(device_t dev)2170 hpt_shutdown(device_t dev)
2171 {
2172 IAL_ADAPTER_T *pAdapter;
2173
2174 pAdapter = device_get_softc(dev);
2175 if (pAdapter == NULL)
2176 return (EINVAL);
2177
2178 EVENTHANDLER_DEREGISTER(shutdown_post_sync, pAdapter->eh);
2179 FlushAdapter(pAdapter);
2180 /* give the flush some time to happen,
2181 *otherwise "shutdown -p now" will make file system corrupted */
2182 DELAY(1000 * 1000 * 5);
2183 return 0;
2184 }
2185
2186 void
Check_Idle_Call(IAL_ADAPTER_T * pAdapter)2187 Check_Idle_Call(IAL_ADAPTER_T *pAdapter)
2188 {
2189 _VBUS_INST(&pAdapter->VBus)
2190
2191 if (mWaitingForIdle(_VBUS_P0)) {
2192 CheckIdleCall(_VBUS_P0);
2193 #ifdef SUPPORT_ARRAY
2194 {
2195 int i;
2196 PVDevice pArray;
2197 for(i = 0; i < MAX_ARRAY_PER_VBUS; i++){
2198 if ((pArray=ArrayTables(i))->u.array.dArStamp==0)
2199 continue;
2200 else if (pArray->u.array.rf_auto_rebuild) {
2201 KdPrint(("auto rebuild.\n"));
2202 pArray->u.array.rf_auto_rebuild = 0;
2203 hpt_queue_dpc((HPT_DPC)hpt_rebuild_data_block, pAdapter, pArray, DUPLICATE);
2204 }
2205 }
2206 }
2207 #endif
2208 }
2209 /* launch the awaiting commands blocked by mWaitingForIdle */
2210 while(pAdapter->pending_Q!= NULL)
2211 {
2212 _VBUS_INST(&pAdapter->VBus)
2213 union ccb *ccb = (union ccb *)pAdapter->pending_Q->ccb_h.ccb_ccb_ptr;
2214 hpt_free_ccb(&pAdapter->pending_Q, ccb);
2215 CallAfterReturn(_VBUS_P (DPC_PROC)OsSendCommand, ccb);
2216 }
2217 }
2218
2219 static void
ccb_done(union ccb * ccb)2220 ccb_done(union ccb *ccb)
2221 {
2222 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter;
2223 IAL_ADAPTER_T * pAdapter = pmap->pAdapter;
2224 KdPrintI(("ccb_done: ccb %p status %x\n", ccb, ccb->ccb_h.status));
2225
2226 dmamap_put(pmap);
2227 xpt_done(ccb);
2228
2229 pAdapter->outstandingCommands--;
2230
2231 if (pAdapter->outstandingCommands == 0)
2232 {
2233 if(DPC_Request_Nums == 0)
2234 Check_Idle_Call(pAdapter);
2235 }
2236 }
2237
2238 /****************************************************************
2239 * Name: hpt_action
2240 * Description: Process a queued command from the CAM layer.
2241 * Parameters: sim - Pointer to SIM object
2242 * ccb - Pointer to SCSI command structure.
2243 ****************************************************************/
2244
2245 static void
hpt_action(struct cam_sim * sim,union ccb * ccb)2246 hpt_action(struct cam_sim *sim, union ccb *ccb)
2247 {
2248 IAL_ADAPTER_T * pAdapter = (IAL_ADAPTER_T *) cam_sim_softc(sim);
2249 PBUS_DMAMAP pmap;
2250 _VBUS_INST(&pAdapter->VBus)
2251
2252 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("hpt_action\n"));
2253 KdPrint(("hpt_action(%lx,%lx{%x})\n", (u_long)sim, (u_long)ccb, ccb->ccb_h.func_code));
2254
2255 switch (ccb->ccb_h.func_code)
2256 {
2257 case XPT_SCSI_IO: /* Execute the requested I/O operation */
2258 {
2259 /* ccb->ccb_h.path_id is not our bus id - don't check it */
2260
2261 if (ccb->ccb_h.target_lun) {
2262 ccb->ccb_h.status = CAM_LUN_INVALID;
2263 xpt_done(ccb);
2264 return;
2265 }
2266 if (ccb->ccb_h.target_id >= MAX_VDEVICE_PER_VBUS ||
2267 pAdapter->VBus.pVDevice[ccb->ccb_h.target_id]==0) {
2268 ccb->ccb_h.status = CAM_TID_INVALID;
2269 xpt_done(ccb);
2270 return;
2271 }
2272
2273 lock_driver();
2274 if (pAdapter->outstandingCommands==0 && DPC_Request_Nums==0)
2275 Check_Idle_Call(pAdapter);
2276
2277 pmap = dmamap_get(pAdapter);
2278 HPT_ASSERT(pmap);
2279 ccb->ccb_adapter = pmap;
2280 memset((void *)pmap->psg, 0, sizeof(pmap->psg));
2281
2282 if (mWaitingForIdle(_VBUS_P0))
2283 hpt_queue_ccb(&pAdapter->pending_Q, ccb);
2284 else
2285 OsSendCommand(_VBUS_P ccb);
2286 unlock_driver();
2287
2288 /* KdPrint(("leave scsiio\n")); */
2289 break;
2290 }
2291
2292 case XPT_RESET_BUS:
2293 KdPrint(("reset bus\n"));
2294 lock_driver();
2295 fResetVBus(_VBUS_P0);
2296 unlock_driver();
2297 xpt_done(ccb);
2298 break;
2299
2300 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */
2301 case XPT_EN_LUN: /* Enable LUN as a target */
2302 case XPT_TARGET_IO: /* Execute target I/O request */
2303 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */
2304 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/
2305 case XPT_ABORT: /* Abort the specified CCB */
2306 case XPT_TERM_IO: /* Terminate the I/O process */
2307 /* XXX Implement */
2308 ccb->ccb_h.status = CAM_REQ_INVALID;
2309 xpt_done(ccb);
2310 break;
2311
2312 case XPT_GET_TRAN_SETTINGS:
2313 case XPT_SET_TRAN_SETTINGS:
2314 /* XXX Implement */
2315 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL;
2316 xpt_done(ccb);
2317 break;
2318
2319 case XPT_CALC_GEOMETRY:
2320 cam_calc_geometry(&ccb->ccg, 1);
2321 xpt_done(ccb);
2322 break;
2323
2324 case XPT_PATH_INQ: /* Path routing inquiry */
2325 {
2326 struct ccb_pathinq *cpi = &ccb->cpi;
2327
2328 cpi->version_num = 1; /* XXX??? */
2329 cpi->hba_inquiry = PI_SDTR_ABLE;
2330 cpi->target_sprt = 0;
2331 /* Not necessary to reset bus */
2332 cpi->hba_misc = PIM_NOBUSRESET;
2333 cpi->hba_eng_cnt = 0;
2334
2335 cpi->max_target = MAX_VDEVICE_PER_VBUS;
2336 cpi->max_lun = 0;
2337 cpi->initiator_id = MAX_VDEVICE_PER_VBUS;
2338
2339 cpi->bus_id = cam_sim_bus(sim);
2340 cpi->base_transfer_speed = 3300;
2341 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
2342 strncpy(cpi->hba_vid, "HPT ", HBA_IDLEN);
2343 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
2344 cpi->unit_number = cam_sim_unit(sim);
2345 cpi->transport = XPORT_SPI;
2346 cpi->transport_version = 2;
2347 cpi->protocol = PROTO_SCSI;
2348 cpi->protocol_version = SCSI_REV_2;
2349 cpi->maxio = HPTMV_DFLTPHYS;
2350 cpi->ccb_h.status = CAM_REQ_CMP;
2351 xpt_done(ccb);
2352 break;
2353 }
2354
2355 default:
2356 KdPrint(("invalid cmd\n"));
2357 ccb->ccb_h.status = CAM_REQ_INVALID;
2358 xpt_done(ccb);
2359 break;
2360 }
2361 /* KdPrint(("leave hpt_action..............\n")); */
2362 }
2363
2364 /* shall be called at lock_driver() */
2365 static void
hpt_queue_ccb(union ccb ** ccb_Q,union ccb * ccb)2366 hpt_queue_ccb(union ccb **ccb_Q, union ccb *ccb)
2367 {
2368 if(*ccb_Q == NULL)
2369 ccb->ccb_h.ccb_ccb_ptr = ccb;
2370 else {
2371 ccb->ccb_h.ccb_ccb_ptr = (*ccb_Q)->ccb_h.ccb_ccb_ptr;
2372 (*ccb_Q)->ccb_h.ccb_ccb_ptr = (char *)ccb;
2373 }
2374
2375 *ccb_Q = ccb;
2376 }
2377
2378 /* shall be called at lock_driver() */
2379 static void
hpt_free_ccb(union ccb ** ccb_Q,union ccb * ccb)2380 hpt_free_ccb(union ccb **ccb_Q, union ccb *ccb)
2381 {
2382 union ccb *TempCCB;
2383
2384 TempCCB = *ccb_Q;
2385
2386 if(ccb->ccb_h.ccb_ccb_ptr == ccb) /*it means SCpnt is the last one in CURRCMDs*/
2387 *ccb_Q = NULL;
2388 else {
2389 while(TempCCB->ccb_h.ccb_ccb_ptr != (char *)ccb)
2390 TempCCB = (union ccb *)TempCCB->ccb_h.ccb_ccb_ptr;
2391
2392 TempCCB->ccb_h.ccb_ccb_ptr = ccb->ccb_h.ccb_ccb_ptr;
2393
2394 if(*ccb_Q == ccb)
2395 *ccb_Q = TempCCB;
2396 }
2397 }
2398
2399 #ifdef SUPPORT_ARRAY
2400 /***************************************************************************
2401 * Function: hpt_worker_thread
2402 * Description: Do background rebuilding. Execute in kernel thread context.
2403 * Returns: None
2404 ***************************************************************************/
hpt_worker_thread(void)2405 static void hpt_worker_thread(void)
2406 {
2407 for(;;) {
2408 while (DpcQueue_First!=DpcQueue_Last) {
2409 ST_HPT_DPC p;
2410 lock_driver();
2411 p = DpcQueue[DpcQueue_First];
2412 DpcQueue_First++;
2413 DpcQueue_First %= MAX_DPC;
2414 DPC_Request_Nums++;
2415 unlock_driver();
2416 p.dpc(p.pAdapter, p.arg, p.flags);
2417
2418 lock_driver();
2419 DPC_Request_Nums--;
2420 /* since we may have prevented Check_Idle_Call, do it here */
2421 if (DPC_Request_Nums==0) {
2422 if (p.pAdapter->outstandingCommands == 0) {
2423 _VBUS_INST(&p.pAdapter->VBus);
2424 Check_Idle_Call(p.pAdapter);
2425 CheckPendingCall(_VBUS_P0);
2426 }
2427 }
2428 unlock_driver();
2429
2430 /*Schedule out*/
2431 tsleep((caddr_t)hpt_worker_thread, 0, "sched", 1);
2432 if (SIGISMEMBER(curproc->p_siglist, SIGSTOP)) {
2433 /* abort rebuilding process. */
2434 IAL_ADAPTER_T *pAdapter;
2435 PVDevice pArray;
2436 PVBus _vbus_p;
2437 int i;
2438 pAdapter = gIal_Adapter;
2439
2440 while(pAdapter != NULL){
2441
2442 _vbus_p = &pAdapter->VBus;
2443
2444 for (i=0;i<MAX_ARRAY_PER_VBUS;i++)
2445 {
2446 if ((pArray=ArrayTables(i))->u.array.dArStamp==0)
2447 continue;
2448 else if (pArray->u.array.rf_rebuilding ||
2449 pArray->u.array.rf_verifying ||
2450 pArray->u.array.rf_initializing)
2451 {
2452 pArray->u.array.rf_abort_rebuild = 1;
2453 }
2454 }
2455 pAdapter = pAdapter->next;
2456 }
2457 }
2458 }
2459
2460 /*Remove this debug option*/
2461 /*
2462 #ifdef DEBUG
2463 if (SIGISMEMBER(curproc->p_siglist, SIGSTOP))
2464 tsleep((caddr_t)hpt_worker_thread, 0, "hptrdy", 2*hz);
2465 #endif
2466 */
2467 kproc_suspend_loop();
2468 tsleep((caddr_t)hpt_worker_thread, 0, "hptrdy", 2*hz); /* wait for something to do */
2469 }
2470 }
2471
2472 static struct kproc_desc hpt_kp = {
2473 "hpt_wt",
2474 hpt_worker_thread,
2475 &hptdaemonproc
2476 };
2477
2478 /*Start this thread in the hpt_attach, to prevent kernel from loading it without our controller.*/
2479 static void
launch_worker_thread(void)2480 launch_worker_thread(void)
2481 {
2482 IAL_ADAPTER_T *pAdapTemp;
2483
2484 kproc_start(&hpt_kp);
2485
2486 for (pAdapTemp = gIal_Adapter; pAdapTemp; pAdapTemp = pAdapTemp->next) {
2487
2488 _VBUS_INST(&pAdapTemp->VBus)
2489 int i;
2490 PVDevice pVDev;
2491
2492 for(i = 0; i < MAX_ARRAY_PER_VBUS; i++)
2493 if ((pVDev=ArrayTables(i))->u.array.dArStamp==0)
2494 continue;
2495 else{
2496 if (pVDev->u.array.rf_need_rebuild && !pVDev->u.array.rf_rebuilding)
2497 hpt_queue_dpc((HPT_DPC)hpt_rebuild_data_block, pAdapTemp, pVDev,
2498 (UCHAR)((pVDev->u.array.CriticalMembers || pVDev->VDeviceType == VD_RAID_1)? DUPLICATE : REBUILD_PARITY));
2499 }
2500 }
2501 }
2502 /*
2503 *SYSINIT(hptwt, SI_SUB_KTHREAD_IDLE, SI_ORDER_FIRST, launch_worker_thread, NULL);
2504 */
2505
2506 #endif
2507
2508 /********************************************************************************/
2509
fOsBuildSgl(_VBUS_ARG PCommand pCmd,FPSCAT_GATH pSg,int logical)2510 static int HPTLIBAPI fOsBuildSgl(_VBUS_ARG PCommand pCmd, FPSCAT_GATH pSg, int logical)
2511 {
2512 union ccb *ccb = (union ccb *)pCmd->pOrgCommand;
2513 bus_dma_segment_t *sgList = (bus_dma_segment_t *)ccb->csio.data_ptr;
2514 int idx;
2515
2516 if(logical) {
2517 if (ccb->ccb_h.flags & CAM_DATA_PHYS)
2518 panic("physical address unsupported");
2519
2520 if (ccb->ccb_h.flags & CAM_SCATTER_VALID) {
2521 if (ccb->ccb_h.flags & CAM_SG_LIST_PHYS)
2522 panic("physical address unsupported");
2523
2524 for (idx = 0; idx < ccb->csio.sglist_cnt; idx++) {
2525 pSg[idx].dSgAddress = (ULONG_PTR)(UCHAR *)sgList[idx].ds_addr;
2526 pSg[idx].wSgSize = sgList[idx].ds_len;
2527 pSg[idx].wSgFlag = (idx==ccb->csio.sglist_cnt-1)? SG_FLAG_EOT : 0;
2528 }
2529 }
2530 else {
2531 pSg->dSgAddress = (ULONG_PTR)(UCHAR *)ccb->csio.data_ptr;
2532 pSg->wSgSize = ccb->csio.dxfer_len;
2533 pSg->wSgFlag = SG_FLAG_EOT;
2534 }
2535 return TRUE;
2536 }
2537
2538 /* since we have provided physical sg, nobody will ask us to build physical sg */
2539 HPT_ASSERT(0);
2540 return FALSE;
2541 }
2542
2543 /*******************************************************************************/
2544 ULONG HPTLIBAPI
GetStamp(void)2545 GetStamp(void)
2546 {
2547 /*
2548 * the system variable, ticks, can't be used since it hasn't yet been active
2549 * when our driver starts (ticks==0, it's a invalid stamp value)
2550 */
2551 ULONG stamp;
2552 do { stamp = krandom(); } while (stamp==0);
2553 return stamp;
2554 }
2555
2556
2557 static void
SetInquiryData(PINQUIRYDATA inquiryData,PVDevice pVDev)2558 SetInquiryData(PINQUIRYDATA inquiryData, PVDevice pVDev)
2559 {
2560 int i;
2561 IDENTIFY_DATA2 *pIdentify = (IDENTIFY_DATA2*)pVDev->u.disk.mv->identifyDevice;
2562
2563 inquiryData->DeviceType = T_DIRECT; /*DIRECT_ACCESS_DEVICE*/
2564 inquiryData->AdditionalLength = (UCHAR)(sizeof(INQUIRYDATA) - 5);
2565 #ifndef SERIAL_CMDS
2566 inquiryData->CommandQueue = 1;
2567 #endif
2568
2569 switch(pVDev->VDeviceType) {
2570 case VD_SINGLE_DISK:
2571 case VD_ATAPI:
2572 case VD_REMOVABLE:
2573 /* Set the removable bit, if applicable. */
2574 if ((pVDev->u.disk.df_removable_drive) || (pIdentify->GeneralConfiguration & 0x80))
2575 inquiryData->RemovableMedia = 1;
2576
2577 /* Fill in vendor identification fields. */
2578 for (i = 0; i < 8; i += 2) {
2579 inquiryData->VendorId[i] = ((PUCHAR)pIdentify->ModelNumber)[i + 1];
2580 inquiryData->VendorId[i+1] = ((PUCHAR)pIdentify->ModelNumber)[i];
2581
2582 }
2583
2584 /* Initialize unused portion of product id. */
2585 for (i = 0; i < 4; i++) inquiryData->ProductId[12+i] = ' ';
2586
2587 /* firmware revision */
2588 for (i = 0; i < 4; i += 2)
2589 {
2590 inquiryData->ProductRevisionLevel[i] = ((PUCHAR)pIdentify->FirmwareRevision)[i+1];
2591 inquiryData->ProductRevisionLevel[i+1] = ((PUCHAR)pIdentify->FirmwareRevision)[i];
2592 }
2593 break;
2594 default:
2595 memcpy(&inquiryData->VendorId, "RR18xx ", 8);
2596 #ifdef SUPPORT_ARRAY
2597 switch(pVDev->VDeviceType){
2598 case VD_RAID_0:
2599 if ((pVDev->u.array.pMember[0] && mIsArray(pVDev->u.array.pMember[0])) ||
2600 (pVDev->u.array.pMember[1] && mIsArray(pVDev->u.array.pMember[1])))
2601 memcpy(&inquiryData->ProductId, "RAID 1/0 Array ", 16);
2602 else
2603 memcpy(&inquiryData->ProductId, "RAID 0 Array ", 16);
2604 break;
2605 case VD_RAID_1:
2606 if ((pVDev->u.array.pMember[0] && mIsArray(pVDev->u.array.pMember[0])) ||
2607 (pVDev->u.array.pMember[1] && mIsArray(pVDev->u.array.pMember[1])))
2608 memcpy(&inquiryData->ProductId, "RAID 0/1 Array ", 16);
2609 else
2610 memcpy(&inquiryData->ProductId, "RAID 1 Array ", 16);
2611 break;
2612 case VD_RAID_5:
2613 memcpy(&inquiryData->ProductId, "RAID 5 Array ", 16);
2614 break;
2615 case VD_JBOD:
2616 memcpy(&inquiryData->ProductId, "JBOD Array ", 16);
2617 break;
2618 }
2619 #endif
2620 memcpy(&inquiryData->ProductRevisionLevel, "3.00", 4);
2621 break;
2622 }
2623 }
2624
2625 static void
hpt_timeout(void * arg)2626 hpt_timeout(void *arg)
2627 {
2628 _VBUS_INST(&((PBUS_DMAMAP)((union ccb *)arg)->ccb_adapter)->pAdapter->VBus)
2629 lock_driver();
2630 fResetVBus(_VBUS_P0);
2631 unlock_driver();
2632 }
2633
2634 static void
hpt_io_dmamap_callback(void * arg,bus_dma_segment_t * segs,int nsegs,int error)2635 hpt_io_dmamap_callback(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
2636 {
2637 PCommand pCmd = (PCommand)arg;
2638 union ccb *ccb = pCmd->pOrgCommand;
2639 struct ccb_hdr *ccb_h = &ccb->ccb_h;
2640 PBUS_DMAMAP pmap = (PBUS_DMAMAP) ccb->ccb_adapter;
2641 IAL_ADAPTER_T *pAdapter = pmap->pAdapter;
2642 PVDevice pVDev = pAdapter->VBus.pVDevice[ccb_h->target_id];
2643 FPSCAT_GATH psg = pCmd->pSgTable;
2644 int idx;
2645 _VBUS_INST(pVDev->pVBus)
2646
2647 HPT_ASSERT(pCmd->cf_physical_sg);
2648
2649 if (error || nsegs == 0)
2650 panic("busdma error");
2651
2652 HPT_ASSERT(nsegs<= MAX_SG_DESCRIPTORS);
2653
2654 for (idx = 0; idx < nsegs; idx++, psg++) {
2655 psg->dSgAddress = (ULONG_PTR)(UCHAR *)segs[idx].ds_addr;
2656 psg->wSgSize = segs[idx].ds_len;
2657 psg->wSgFlag = (idx == nsegs-1)? SG_FLAG_EOT: 0;
2658 /* KdPrint(("psg[%d]:add=%p,size=%x,flag=%x\n", idx, psg->dSgAddress,psg->wSgSize,psg->wSgFlag)); */
2659 }
2660 /* psg[-1].wSgFlag = SG_FLAG_EOT; */
2661
2662 if (pCmd->cf_data_in) {
2663 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_PREREAD);
2664 }
2665 else if (pCmd->cf_data_out) {
2666 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_PREWRITE);
2667 }
2668
2669 callout_reset(ccb->ccb_h.timeout_ch, 20*hz, hpt_timeout, ccb);
2670 pVDev->pfnSendCommand(_VBUS_P pCmd);
2671 CheckPendingCall(_VBUS_P0);
2672 }
2673
2674
2675
2676 static void HPTLIBAPI
OsSendCommand(_VBUS_ARG union ccb * ccb)2677 OsSendCommand(_VBUS_ARG union ccb *ccb)
2678 {
2679 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter;
2680 IAL_ADAPTER_T *pAdapter = pmap->pAdapter;
2681 struct ccb_hdr *ccb_h = &ccb->ccb_h;
2682 struct ccb_scsiio *csio = &ccb->csio;
2683 PVDevice pVDev = pAdapter->VBus.pVDevice[ccb_h->target_id];
2684
2685 KdPrintI(("OsSendCommand: ccb %p cdb %x-%x-%x\n",
2686 ccb,
2687 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[0],
2688 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[4],
2689 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[8]
2690 ));
2691
2692 pAdapter->outstandingCommands++;
2693
2694 if (pVDev == NULL || pVDev->vf_online == 0) {
2695 ccb->ccb_h.status = CAM_REQ_INVALID;
2696 ccb_done(ccb);
2697 goto Command_Complished;
2698 }
2699
2700 switch(ccb->csio.cdb_io.cdb_bytes[0])
2701 {
2702 case TEST_UNIT_READY:
2703 case START_STOP_UNIT:
2704 case SYNCHRONIZE_CACHE:
2705 /* FALLTHROUGH */
2706 ccb->ccb_h.status = CAM_REQ_CMP;
2707 break;
2708
2709 case INQUIRY:
2710 ZeroMemory(ccb->csio.data_ptr, ccb->csio.dxfer_len);
2711 SetInquiryData((PINQUIRYDATA)ccb->csio.data_ptr, pVDev);
2712 ccb_h->status = CAM_REQ_CMP;
2713 break;
2714
2715 case READ_CAPACITY:
2716 {
2717 UCHAR *rbuf=csio->data_ptr;
2718 unsigned int cap;
2719
2720 if (pVDev->VDeviceCapacity > 0xfffffffful) {
2721 cap = 0xfffffffful;
2722 } else {
2723 cap = pVDev->VDeviceCapacity - 1;
2724 }
2725
2726 rbuf[0] = (UCHAR)(cap>>24);
2727 rbuf[1] = (UCHAR)(cap>>16);
2728 rbuf[2] = (UCHAR)(cap>>8);
2729 rbuf[3] = (UCHAR)cap;
2730 /* Claim 512 byte blocks (big-endian). */
2731 rbuf[4] = 0;
2732 rbuf[5] = 0;
2733 rbuf[6] = 2;
2734 rbuf[7] = 0;
2735
2736 ccb_h->status = CAM_REQ_CMP;
2737 break;
2738 }
2739
2740 case 0x9e: /*SERVICE_ACTION_IN*/
2741 {
2742 UCHAR *rbuf = csio->data_ptr;
2743 LBA_T cap = pVDev->VDeviceCapacity - 1;
2744
2745 rbuf[0] = (UCHAR)(cap>>56);
2746 rbuf[1] = (UCHAR)(cap>>48);
2747 rbuf[2] = (UCHAR)(cap>>40);
2748 rbuf[3] = (UCHAR)(cap>>32);
2749 rbuf[4] = (UCHAR)(cap>>24);
2750 rbuf[5] = (UCHAR)(cap>>16);
2751 rbuf[6] = (UCHAR)(cap>>8);
2752 rbuf[7] = (UCHAR)cap;
2753 rbuf[8] = 0;
2754 rbuf[9] = 0;
2755 rbuf[10] = 2;
2756 rbuf[11] = 0;
2757
2758 ccb_h->status = CAM_REQ_CMP;
2759 break;
2760 }
2761
2762 case READ_6:
2763 case WRITE_6:
2764 case READ_10:
2765 case WRITE_10:
2766 case 0x88: /* READ_16 */
2767 case 0x8a: /* WRITE_16 */
2768 case 0x13:
2769 case 0x2f:
2770 {
2771 UCHAR Cdb[16];
2772 UCHAR CdbLength;
2773 _VBUS_INST(pVDev->pVBus)
2774 PCommand pCmd = AllocateCommand(_VBUS_P0);
2775 HPT_ASSERT(pCmd);
2776
2777 CdbLength = csio->cdb_len;
2778 if ((ccb->ccb_h.flags & CAM_CDB_POINTER) != 0)
2779 {
2780 if ((ccb->ccb_h.flags & CAM_CDB_PHYS) == 0)
2781 {
2782 bcopy(csio->cdb_io.cdb_ptr, Cdb, CdbLength);
2783 }
2784 else
2785 {
2786 KdPrintE(("ERROR!!!\n"));
2787 ccb->ccb_h.status = CAM_REQ_INVALID;
2788 break;
2789 }
2790 }
2791 else
2792 {
2793 bcopy(csio->cdb_io.cdb_bytes, Cdb, CdbLength);
2794 }
2795
2796 pCmd->pOrgCommand = ccb;
2797 pCmd->pVDevice = pVDev;
2798 pCmd->pfnCompletion = fOsCommandDone;
2799 pCmd->pfnBuildSgl = fOsBuildSgl;
2800 pCmd->pSgTable = pmap->psg;
2801
2802 switch (Cdb[0])
2803 {
2804 case READ_6:
2805 case WRITE_6:
2806 case 0x13:
2807 pCmd->uCmd.Ide.Lba = ((ULONG)Cdb[1] << 16) | ((ULONG)Cdb[2] << 8) | (ULONG)Cdb[3];
2808 pCmd->uCmd.Ide.nSectors = (USHORT) Cdb[4];
2809 break;
2810
2811 case 0x88: /* READ_16 */
2812 case 0x8a: /* WRITE_16 */
2813 pCmd->uCmd.Ide.Lba =
2814 (HPT_U64)Cdb[2] << 56 |
2815 (HPT_U64)Cdb[3] << 48 |
2816 (HPT_U64)Cdb[4] << 40 |
2817 (HPT_U64)Cdb[5] << 32 |
2818 (HPT_U64)Cdb[6] << 24 |
2819 (HPT_U64)Cdb[7] << 16 |
2820 (HPT_U64)Cdb[8] << 8 |
2821 (HPT_U64)Cdb[9];
2822 pCmd->uCmd.Ide.nSectors = (USHORT)Cdb[12] << 8 | (USHORT)Cdb[13];
2823 break;
2824
2825 default:
2826 pCmd->uCmd.Ide.Lba = (ULONG)Cdb[5] | ((ULONG)Cdb[4] << 8) | ((ULONG)Cdb[3] << 16) | ((ULONG)Cdb[2] << 24);
2827 pCmd->uCmd.Ide.nSectors = (USHORT) Cdb[8] | ((USHORT)Cdb[7]<<8);
2828 break;
2829 }
2830
2831 switch (Cdb[0])
2832 {
2833 case READ_6:
2834 case READ_10:
2835 case 0x88: /* READ_16 */
2836 pCmd->uCmd.Ide.Command = IDE_COMMAND_READ;
2837 pCmd->cf_data_in = 1;
2838 break;
2839
2840 case WRITE_6:
2841 case WRITE_10:
2842 case 0x8a: /* WRITE_16 */
2843 pCmd->uCmd.Ide.Command = IDE_COMMAND_WRITE;
2844 pCmd->cf_data_out = 1;
2845 break;
2846 case 0x13:
2847 case 0x2f:
2848 pCmd->uCmd.Ide.Command = IDE_COMMAND_VERIFY;
2849 break;
2850 }
2851 /*///////////////////////// */
2852 if (ccb->ccb_h.flags & CAM_SCATTER_VALID) {
2853 int idx;
2854 bus_dma_segment_t *sgList = (bus_dma_segment_t *)ccb->csio.data_ptr;
2855
2856 if (ccb->ccb_h.flags & CAM_SG_LIST_PHYS)
2857 pCmd->cf_physical_sg = 1;
2858
2859 for (idx = 0; idx < ccb->csio.sglist_cnt; idx++) {
2860 pCmd->pSgTable[idx].dSgAddress = (ULONG_PTR)(UCHAR *)sgList[idx].ds_addr;
2861 pCmd->pSgTable[idx].wSgSize = sgList[idx].ds_len;
2862 pCmd->pSgTable[idx].wSgFlag= (idx==ccb->csio.sglist_cnt-1)?SG_FLAG_EOT: 0;
2863 }
2864
2865 callout_reset(ccb->ccb_h.timeout_ch, 20 * hz,
2866 hpt_timeout, ccb);
2867 pVDev->pfnSendCommand(_VBUS_P pCmd);
2868 }
2869 else {
2870 int error;
2871 pCmd->cf_physical_sg = 1;
2872 error = bus_dmamap_load(pAdapter->io_dma_parent,
2873 pmap->dma_map,
2874 ccb->csio.data_ptr, ccb->csio.dxfer_len,
2875 hpt_io_dmamap_callback, pCmd,
2876 BUS_DMA_WAITOK
2877 );
2878 KdPrint(("bus_dmamap_load return %d\n", error));
2879 if (error && error!=EINPROGRESS) {
2880 hpt_printk(("bus_dmamap_load error %d\n", error));
2881 FreeCommand(_VBUS_P pCmd);
2882 ccb->ccb_h.status = CAM_REQ_CMP_ERR;
2883 dmamap_put(pmap);
2884 pAdapter->outstandingCommands--;
2885 xpt_done(ccb);
2886 }
2887 }
2888 goto Command_Complished;
2889 }
2890
2891 default:
2892 ccb->ccb_h.status = CAM_REQ_INVALID;
2893 break;
2894 }
2895 ccb_done(ccb);
2896 Command_Complished:
2897 CheckPendingCall(_VBUS_P0);
2898 return;
2899 }
2900
2901 static void HPTLIBAPI
fOsCommandDone(_VBUS_ARG PCommand pCmd)2902 fOsCommandDone(_VBUS_ARG PCommand pCmd)
2903 {
2904 union ccb *ccb = pCmd->pOrgCommand;
2905 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter;
2906 IAL_ADAPTER_T *pAdapter = pmap->pAdapter;
2907
2908 KdPrint(("fOsCommandDone(pcmd=%p, result=%d)\n", pCmd, pCmd->Result));
2909
2910 callout_stop(ccb->ccb_h.timeout_ch);
2911
2912 switch(pCmd->Result) {
2913 case RETURN_SUCCESS:
2914 ccb->ccb_h.status = CAM_REQ_CMP;
2915 break;
2916 case RETURN_BAD_DEVICE:
2917 ccb->ccb_h.status = CAM_DEV_NOT_THERE;
2918 break;
2919 case RETURN_DEVICE_BUSY:
2920 ccb->ccb_h.status = CAM_BUSY;
2921 break;
2922 case RETURN_INVALID_REQUEST:
2923 ccb->ccb_h.status = CAM_REQ_INVALID;
2924 break;
2925 case RETURN_SELECTION_TIMEOUT:
2926 ccb->ccb_h.status = CAM_SEL_TIMEOUT;
2927 break;
2928 case RETURN_RETRY:
2929 ccb->ccb_h.status = CAM_BUSY;
2930 break;
2931 default:
2932 ccb->ccb_h.status = CAM_SCSI_STATUS_ERROR;
2933 break;
2934 }
2935
2936 if (pCmd->cf_data_in) {
2937 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_POSTREAD);
2938 }
2939 else if (pCmd->cf_data_out) {
2940 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_POSTWRITE);
2941 }
2942
2943 bus_dmamap_unload(pAdapter->io_dma_parent, pmap->dma_map);
2944
2945 FreeCommand(_VBUS_P pCmd);
2946 ccb_done(ccb);
2947 }
2948
2949 int
hpt_queue_dpc(HPT_DPC dpc,IAL_ADAPTER_T * pAdapter,void * arg,UCHAR flags)2950 hpt_queue_dpc(HPT_DPC dpc, IAL_ADAPTER_T * pAdapter, void *arg, UCHAR flags)
2951 {
2952 int p;
2953
2954 p = (DpcQueue_Last + 1) % MAX_DPC;
2955 if (p==DpcQueue_First) {
2956 KdPrint(("DPC Queue full!\n"));
2957 return -1;
2958 }
2959
2960 DpcQueue[DpcQueue_Last].dpc = dpc;
2961 DpcQueue[DpcQueue_Last].pAdapter = pAdapter;
2962 DpcQueue[DpcQueue_Last].arg = arg;
2963 DpcQueue[DpcQueue_Last].flags = flags;
2964 DpcQueue_Last = p;
2965
2966 return 0;
2967 }
2968
2969 #ifdef _RAID5N_
2970 /*
2971 * Allocate memory above 16M, otherwise we may eat all low memory for ISA devices.
2972 * How about the memory for 5081 request/response array and PRD table?
2973 */
2974 void
os_alloc_page(_VBUS_ARG0)2975 *os_alloc_page(_VBUS_ARG0)
2976 {
2977 return (void *)contigmalloc(0x1000, M_DEVBUF, M_NOWAIT, 0x1000000, 0xffffffff, PAGE_SIZE, 0ul);
2978 }
2979
2980 void
os_alloc_dma_page(_VBUS_ARG0)2981 *os_alloc_dma_page(_VBUS_ARG0)
2982 {
2983 return (void *)contigmalloc(0x1000, M_DEVBUF, M_NOWAIT, 0x1000000, 0xffffffff, PAGE_SIZE, 0ul);
2984 }
2985
2986 void
os_free_page(_VBUS_ARG void * p)2987 os_free_page(_VBUS_ARG void *p)
2988 {
2989 contigfree(p, 0x1000, M_DEVBUF);
2990 }
2991
2992 void
os_free_dma_page(_VBUS_ARG void * p)2993 os_free_dma_page(_VBUS_ARG void *p)
2994 {
2995 contigfree(p, 0x1000, M_DEVBUF);
2996 }
2997
2998 void
DoXor1(ULONG * p0,ULONG * p1,ULONG * p2,UINT nBytes)2999 DoXor1(ULONG *p0, ULONG *p1, ULONG *p2, UINT nBytes)
3000 {
3001 UINT i;
3002 for (i = 0; i < nBytes / 4; i++) *p0++ = *p1++ ^ *p2++;
3003 }
3004
3005 void
DoXor2(ULONG * p0,ULONG * p2,UINT nBytes)3006 DoXor2(ULONG *p0, ULONG *p2, UINT nBytes)
3007 {
3008 UINT i;
3009 for (i = 0; i < nBytes / 4; i++) *p0++ ^= *p2++;
3010 }
3011 #endif
3012