1 /*
2  * Copyright 2010 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  *
23  * Authors:
24  *     Alex Deucher <alexander.deucher@amd.com>
25  */
26 
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD: stable/9/sys/dev/drm2/radeon/evergreen_blit_shaders.c 254885 2013-08-25 19:37:15Z dumbbell $");
29 
30 #include <dev/drm2/drmP.h>
31 
32 /*
33  * evergreen cards need to use the 3D engine to blit data which requires
34  * quite a bit of hw state setup.  Rather than pull the whole 3D driver
35  * (which normally generates the 3D state) into the DRM, we opt to use
36  * statically generated state tables.  The regsiter state and shaders
37  * were hand generated to support blitting functionality.  See the 3D
38  * driver or documentation for descriptions of the registers and
39  * shader instructions.
40  */
41 
42 const u32 evergreen_default_state[] =
43 {
44 	0xc0016900,
45 	0x0000023b,
46 	0x00000000, /* SQ_LDS_ALLOC_PS */
47 
48 	0xc0066900,
49 	0x00000240,
50 	0x00000000, /* SQ_ESGS_RING_ITEMSIZE */
51 	0x00000000,
52 	0x00000000,
53 	0x00000000,
54 	0x00000000,
55 	0x00000000,
56 
57 	0xc0046900,
58 	0x00000247,
59 	0x00000000, /* SQ_GS_VERT_ITEMSIZE */
60 	0x00000000,
61 	0x00000000,
62 	0x00000000,
63 
64 	0xc0026900,
65 	0x00000010,
66 	0x00000000, /* DB_Z_INFO */
67 	0x00000000, /* DB_STENCIL_INFO */
68 
69 	0xc0016900,
70 	0x00000200,
71 	0x00000000, /* DB_DEPTH_CONTROL */
72 
73 	0xc0066900,
74 	0x00000000,
75 	0x00000060, /* DB_RENDER_CONTROL */
76 	0x00000000, /* DB_COUNT_CONTROL */
77 	0x00000000, /* DB_DEPTH_VIEW */
78 	0x0000002a, /* DB_RENDER_OVERRIDE */
79 	0x00000000, /* DB_RENDER_OVERRIDE2 */
80 	0x00000000, /* DB_HTILE_DATA_BASE */
81 
82 	0xc0026900,
83 	0x0000000a,
84 	0x00000000, /* DB_STENCIL_CLEAR */
85 	0x00000000, /* DB_DEPTH_CLEAR */
86 
87 	0xc0016900,
88 	0x000002dc,
89 	0x0000aa00, /* DB_ALPHA_TO_MASK */
90 
91 	0xc0016900,
92 	0x00000080,
93 	0x00000000, /* PA_SC_WINDOW_OFFSET */
94 
95 	0xc00d6900,
96 	0x00000083,
97 	0x0000ffff, /* PA_SC_CLIPRECT_RULE */
98 	0x00000000, /* PA_SC_CLIPRECT_0_TL */
99 	0x20002000, /* PA_SC_CLIPRECT_0_BR */
100 	0x00000000,
101 	0x20002000,
102 	0x00000000,
103 	0x20002000,
104 	0x00000000,
105 	0x20002000,
106 	0xaaaaaaaa, /* PA_SC_EDGERULE */
107 	0x00000000, /* PA_SU_HARDWARE_SCREEN_OFFSET */
108 	0x0000000f, /* CB_TARGET_MASK */
109 	0x0000000f, /* CB_SHADER_MASK */
110 
111 	0xc0226900,
112 	0x00000094,
113 	0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */
114 	0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */
115 	0x80000000,
116 	0x20002000,
117 	0x80000000,
118 	0x20002000,
119 	0x80000000,
120 	0x20002000,
121 	0x80000000,
122 	0x20002000,
123 	0x80000000,
124 	0x20002000,
125 	0x80000000,
126 	0x20002000,
127 	0x80000000,
128 	0x20002000,
129 	0x80000000,
130 	0x20002000,
131 	0x80000000,
132 	0x20002000,
133 	0x80000000,
134 	0x20002000,
135 	0x80000000,
136 	0x20002000,
137 	0x80000000,
138 	0x20002000,
139 	0x80000000,
140 	0x20002000,
141 	0x80000000,
142 	0x20002000,
143 	0x80000000,
144 	0x20002000,
145 	0x00000000, /* PA_SC_VPORT_ZMIN_0 */
146 	0x3f800000, /* PA_SC_VPORT_ZMAX_0 */
147 
148 	0xc0016900,
149 	0x000000d4,
150 	0x00000000, /* SX_MISC */
151 
152 	0xc0026900,
153 	0x00000292,
154 	0x00000000, /* PA_SC_MODE_CNTL_0 */
155 	0x00000000, /* PA_SC_MODE_CNTL_1 */
156 
157 	0xc0106900,
158 	0x00000300,
159 	0x00000000, /* PA_SC_LINE_CNTL */
160 	0x00000000, /* PA_SC_AA_CONFIG */
161 	0x00000005, /* PA_SU_VTX_CNTL */
162 	0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */
163 	0x3f800000, /* PA_CL_GB_VERT_DISC_ADJ */
164 	0x3f800000, /* PA_CL_GB_HORZ_CLIP_ADJ */
165 	0x3f800000, /* PA_CL_GB_HORZ_DISC_ADJ */
166 	0x00000000, /* PA_SC_AA_SAMPLE_LOCS_0 */
167 	0x00000000, /*  */
168 	0x00000000, /*  */
169 	0x00000000, /*  */
170 	0x00000000, /*  */
171 	0x00000000, /*  */
172 	0x00000000, /*  */
173 	0x00000000, /* PA_SC_AA_SAMPLE_LOCS_7 */
174 	0xffffffff, /* PA_SC_AA_MASK */
175 
176 	0xc00d6900,
177 	0x00000202,
178 	0x00cc0010, /* CB_COLOR_CONTROL */
179 	0x00000210, /* DB_SHADER_CONTROL */
180 	0x00010000, /* PA_CL_CLIP_CNTL */
181 	0x00000004, /* PA_SU_SC_MODE_CNTL */
182 	0x00000100, /* PA_CL_VTE_CNTL */
183 	0x00000000, /* PA_CL_VS_OUT_CNTL */
184 	0x00000000, /* PA_CL_NANINF_CNTL */
185 	0x00000000, /* PA_SU_LINE_STIPPLE_CNTL */
186 	0x00000000, /* PA_SU_LINE_STIPPLE_SCALE */
187 	0x00000000, /* PA_SU_PRIM_FILTER_CNTL */
188 	0x00000000, /*  */
189 	0x00000000, /*  */
190 	0x00000000, /* SQ_DYN_GPR_RESOURCE_LIMIT_1 */
191 
192 	0xc0066900,
193 	0x000002de,
194 	0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
195 	0x00000000, /*  */
196 	0x00000000, /*  */
197 	0x00000000, /*  */
198 	0x00000000, /*  */
199 	0x00000000, /*  */
200 
201 	0xc0016900,
202 	0x00000229,
203 	0x00000000, /* SQ_PGM_START_FS */
204 
205 	0xc0016900,
206 	0x0000022a,
207 	0x00000000, /* SQ_PGM_RESOURCES_FS */
208 
209 	0xc0096900,
210 	0x00000100,
211 	0x00ffffff, /* VGT_MAX_VTX_INDX */
212 	0x00000000, /*  */
213 	0x00000000, /*  */
214 	0x00000000, /*  */
215 	0x00000000, /* SX_ALPHA_TEST_CONTROL */
216 	0x00000000, /* CB_BLEND_RED */
217 	0x00000000, /* CB_BLEND_GREEN */
218 	0x00000000, /* CB_BLEND_BLUE */
219 	0x00000000, /* CB_BLEND_ALPHA */
220 
221 	0xc0026900,
222 	0x000002a8,
223 	0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
224 	0x00000000, /*  */
225 
226 	0xc0026900,
227 	0x000002ad,
228 	0x00000000, /* VGT_REUSE_OFF */
229 	0x00000000, /*  */
230 
231 	0xc0116900,
232 	0x00000280,
233 	0x00000000, /* PA_SU_POINT_SIZE */
234 	0x00000000, /* PA_SU_POINT_MINMAX */
235 	0x00000008, /* PA_SU_LINE_CNTL */
236 	0x00000000, /* PA_SC_LINE_STIPPLE */
237 	0x00000000, /* VGT_OUTPUT_PATH_CNTL */
238 	0x00000000, /* VGT_HOS_CNTL */
239 	0x00000000, /*  */
240 	0x00000000, /*  */
241 	0x00000000, /*  */
242 	0x00000000, /*  */
243 	0x00000000, /*  */
244 	0x00000000, /*  */
245 	0x00000000, /*  */
246 	0x00000000, /*  */
247 	0x00000000, /*  */
248 	0x00000000, /*  */
249 	0x00000000, /* VGT_GS_MODE */
250 
251 	0xc0016900,
252 	0x000002a1,
253 	0x00000000, /* VGT_PRIMITIVEID_EN */
254 
255 	0xc0016900,
256 	0x000002a5,
257 	0x00000000, /* VGT_MULTI_PRIM_IB_RESET_EN */
258 
259 	0xc0016900,
260 	0x000002d5,
261 	0x00000000, /* VGT_SHADER_STAGES_EN */
262 
263 	0xc0026900,
264 	0x000002e5,
265 	0x00000000, /* VGT_STRMOUT_CONFIG */
266 	0x00000000, /*  */
267 
268 	0xc0016900,
269 	0x000001e0,
270 	0x00000000, /* CB_BLEND0_CONTROL */
271 
272 	0xc0016900,
273 	0x000001b1,
274 	0x00000000, /* SPI_VS_OUT_CONFIG */
275 
276 	0xc0016900,
277 	0x00000187,
278 	0x00000000, /* SPI_VS_OUT_ID_0 */
279 
280 	0xc0016900,
281 	0x00000191,
282 	0x00000100, /* SPI_PS_INPUT_CNTL_0 */
283 
284 	0xc00b6900,
285 	0x000001b3,
286 	0x20000001, /* SPI_PS_IN_CONTROL_0 */
287 	0x00000000, /* SPI_PS_IN_CONTROL_1 */
288 	0x00000000, /* SPI_INTERP_CONTROL_0 */
289 	0x00000000, /* SPI_INPUT_Z */
290 	0x00000000, /* SPI_FOG_CNTL */
291 	0x00100000, /* SPI_BARYC_CNTL */
292 	0x00000000, /* SPI_PS_IN_CONTROL_2 */
293 	0x00000000, /*  */
294 	0x00000000, /*  */
295 	0x00000000, /*  */
296 	0x00000000, /*  */
297 
298 	0xc0026900,
299 	0x00000316,
300 	0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */
301 	0x00000010, /*  */
302 };
303 
304 const u32 evergreen_vs[] =
305 {
306 	0x00000004,
307 	0x80800400,
308 	0x0000a03c,
309 	0x95000688,
310 	0x00004000,
311 	0x15200688,
312 	0x00000000,
313 	0x00000000,
314 	0x3c000000,
315 	0x67961001,
316 #ifdef __BIG_ENDIAN
317 	0x000a0000,
318 #else
319 	0x00080000,
320 #endif
321 	0x00000000,
322 	0x1c000000,
323 	0x67961000,
324 #ifdef __BIG_ENDIAN
325 	0x00020008,
326 #else
327 	0x00000008,
328 #endif
329 	0x00000000,
330 };
331 
332 const u32 evergreen_ps[] =
333 {
334 	0x00000003,
335 	0xa00c0000,
336 	0x00000008,
337 	0x80400000,
338 	0x00000000,
339 	0x95200688,
340 	0x00380400,
341 	0x00146b10,
342 	0x00380000,
343 	0x20146b10,
344 	0x00380400,
345 	0x40146b00,
346 	0x80380000,
347 	0x60146b00,
348 	0x00000000,
349 	0x00000000,
350 	0x00000010,
351 	0x000d1000,
352 	0xb0800000,
353 	0x00000000,
354 };
355 
356 const u32 evergreen_ps_size = DRM_ARRAY_SIZE(evergreen_ps);
357 const u32 evergreen_vs_size = DRM_ARRAY_SIZE(evergreen_vs);
358 const u32 evergreen_default_size = DRM_ARRAY_SIZE(evergreen_default_state);
359