1 /*******************************************************************************
2
3 Copyright (c) 2001-2003, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 *******************************************************************************/
33
34 /* $OpenBSD: if_em_hw.c,v 1.4 2004/04/18 04:15:00 henric Exp $ */
35 /* if_em_hw.c
36 * Shared functions for accessing and configuring the MAC
37 */
38
39 #ifdef __FreeBSD__
40 #include <sys/cdefs.h>
41 __FBSDID("$FreeBSD: if_em_hw.c,v 1.13 2004/02/10 21:31:09 pdeuskar Exp $");
42 #endif
43
44 #include "bpfilter.h"
45 #include "vlan.h"
46
47 #include <sys/param.h>
48 #include <sys/systm.h>
49 #include <sys/sockio.h>
50 #include <sys/mbuf.h>
51 #include <sys/malloc.h>
52 #include <sys/kernel.h>
53 #include <sys/device.h>
54 #include <sys/socket.h>
55
56 #include <net/if.h>
57 #include <net/if_dl.h>
58 #include <net/if_media.h>
59
60 #ifdef INET
61 #include <netinet/in.h>
62 #include <netinet/in_systm.h>
63 #include <netinet/in_var.h>
64 #include <netinet/ip.h>
65 #include <netinet/if_ether.h>
66 #endif
67
68 #if NVLAN > 0
69 #include <net/if_types.h>
70 #include <net/if_vlan_var.h>
71 #endif
72
73 #if NBPFILTER > 0
74 #include <net/bpf.h>
75 #endif
76
77 #include <uvm/uvm_extern.h>
78
79 #include <dev/pci/pcireg.h>
80 #include <dev/pci/pcivar.h>
81 #include <dev/pci/pcidevs.h>
82
83 #include <dev/pci/if_em_hw.h>
84
85 static int32_t em_set_phy_type(struct em_hw *hw);
86 static void em_phy_init_script(struct em_hw *hw);
87 static int32_t em_setup_copper_link(struct em_hw *hw);
88 static int32_t em_setup_fiber_serdes_link(struct em_hw *hw);
89 static int32_t em_adjust_serdes_amplitude(struct em_hw *hw);
90 static int32_t em_phy_force_speed_duplex(struct em_hw *hw);
91 static int32_t em_config_mac_to_phy(struct em_hw *hw);
92 static void em_raise_mdi_clk(struct em_hw *hw, uint32_t *ctrl);
93 static void em_lower_mdi_clk(struct em_hw *hw, uint32_t *ctrl);
94 static void em_shift_out_mdi_bits(struct em_hw *hw, uint32_t data,
95 uint16_t count);
96 static uint16_t em_shift_in_mdi_bits(struct em_hw *hw);
97 static int32_t em_phy_reset_dsp(struct em_hw *hw);
98 static int32_t em_write_eeprom_spi(struct em_hw *hw, uint16_t offset,
99 uint16_t words, uint16_t *data);
100 static int32_t em_write_eeprom_microwire(struct em_hw *hw,
101 uint16_t offset, uint16_t words,
102 uint16_t *data);
103 static int32_t em_spi_eeprom_ready(struct em_hw *hw);
104 static void em_raise_ee_clk(struct em_hw *hw, uint32_t *eecd);
105 static void em_lower_ee_clk(struct em_hw *hw, uint32_t *eecd);
106 static void em_shift_out_ee_bits(struct em_hw *hw, uint16_t data,
107 uint16_t count);
108 static int32_t em_write_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr,
109 uint16_t phy_data);
110 static int32_t em_read_phy_reg_ex(struct em_hw *hw,uint32_t reg_addr,
111 uint16_t *phy_data);
112 static uint16_t em_shift_in_ee_bits(struct em_hw *hw, uint16_t count);
113 static int32_t em_acquire_eeprom(struct em_hw *hw);
114 static void em_release_eeprom(struct em_hw *hw);
115 static void em_standby_eeprom(struct em_hw *hw);
116 static int32_t em_id_led_init(struct em_hw * hw);
117 static int32_t em_set_vco_speed(struct em_hw *hw);
118
119 /* IGP cable length table */
120 static const
121 uint16_t em_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
122 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
123 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
124 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
125 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
126 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
127 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
128 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
129 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
130
131
132 /******************************************************************************
133 * Set the phy type member in the hw struct.
134 *
135 * hw - Struct containing variables accessed by shared code
136 *****************************************************************************/
137 int32_t
em_set_phy_type(struct em_hw * hw)138 em_set_phy_type(struct em_hw *hw)
139 {
140 DEBUGFUNC("em_set_phy_type");
141
142 switch(hw->phy_id) {
143 case M88E1000_E_PHY_ID:
144 case M88E1000_I_PHY_ID:
145 case M88E1011_I_PHY_ID:
146 hw->phy_type = em_phy_m88;
147 break;
148 case IGP01E1000_I_PHY_ID:
149 if(hw->mac_type == em_82541 ||
150 hw->mac_type == em_82541_rev_2 ||
151 hw->mac_type == em_82547 ||
152 hw->mac_type == em_82547_rev_2) {
153 hw->phy_type = em_phy_igp;
154 break;
155 }
156 /* Fall Through */
157 default:
158 /* Should never have loaded on this device */
159 hw->phy_type = em_phy_undefined;
160 return -E1000_ERR_PHY_TYPE;
161 }
162
163 return E1000_SUCCESS;
164 }
165
166 /******************************************************************************
167 * IGP phy init script - initializes the GbE PHY
168 *
169 * hw - Struct containing variables accessed by shared code
170 *****************************************************************************/
171 static void
em_phy_init_script(struct em_hw * hw)172 em_phy_init_script(struct em_hw *hw)
173 {
174 DEBUGFUNC("em_phy_init_script");
175
176 if(hw->phy_init_script) {
177 msec_delay(20);
178
179 em_write_phy_reg(hw,0x0000,0x0140);
180
181 msec_delay(5);
182
183 if(hw->mac_type == em_82541 || hw->mac_type == em_82547) {
184 em_write_phy_reg(hw, 0x1F95, 0x0001);
185
186 em_write_phy_reg(hw, 0x1F71, 0xBD21);
187
188 em_write_phy_reg(hw, 0x1F79, 0x0018);
189
190 em_write_phy_reg(hw, 0x1F30, 0x1600);
191
192 em_write_phy_reg(hw, 0x1F31, 0x0014);
193
194 em_write_phy_reg(hw, 0x1F32, 0x161C);
195
196 em_write_phy_reg(hw, 0x1F94, 0x0003);
197
198 em_write_phy_reg(hw, 0x1F96, 0x003F);
199
200 em_write_phy_reg(hw, 0x2010, 0x0008);
201 } else {
202 em_write_phy_reg(hw, 0x1F73, 0x0099);
203 }
204
205 em_write_phy_reg(hw, 0x0000, 0x3300);
206
207 if(hw->mac_type == em_82547) {
208 uint16_t fused, fine, coarse;
209
210 /* Move to analog registers page */
211 em_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
212
213 if(!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
214 em_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
215
216 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
217 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
218
219 if(coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
220 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
221 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
222 } else if(coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
223 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
224
225 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
226 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
227 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
228
229 em_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
230 em_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
231 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
232 }
233 }
234 }
235 }
236
237 /******************************************************************************
238 * Set the mac type member in the hw struct.
239 *
240 * hw - Struct containing variables accessed by shared code
241 *****************************************************************************/
242 int32_t
em_set_mac_type(struct em_hw * hw)243 em_set_mac_type(struct em_hw *hw)
244 {
245 DEBUGFUNC("em_set_mac_type");
246
247 switch (hw->device_id) {
248 case E1000_DEV_ID_82542:
249 switch (hw->revision_id) {
250 case E1000_82542_2_0_REV_ID:
251 hw->mac_type = em_82542_rev2_0;
252 break;
253 case E1000_82542_2_1_REV_ID:
254 hw->mac_type = em_82542_rev2_1;
255 break;
256 default:
257 /* Invalid 82542 revision ID */
258 return -E1000_ERR_MAC_TYPE;
259 }
260 break;
261 case E1000_DEV_ID_82543GC_FIBER:
262 case E1000_DEV_ID_82543GC_COPPER:
263 hw->mac_type = em_82543;
264 break;
265 case E1000_DEV_ID_82544EI_COPPER:
266 case E1000_DEV_ID_82544EI_FIBER:
267 case E1000_DEV_ID_82544GC_COPPER:
268 case E1000_DEV_ID_82544GC_LOM:
269 hw->mac_type = em_82544;
270 break;
271 case E1000_DEV_ID_82540EM:
272 case E1000_DEV_ID_82540EM_LOM:
273 case E1000_DEV_ID_82540EP:
274 case E1000_DEV_ID_82540EP_LOM:
275 case E1000_DEV_ID_82540EP_LP:
276 hw->mac_type = em_82540;
277 break;
278 case E1000_DEV_ID_82545EM_COPPER:
279 case E1000_DEV_ID_82545EM_FIBER:
280 hw->mac_type = em_82545;
281 break;
282 case E1000_DEV_ID_82545GM_COPPER:
283 case E1000_DEV_ID_82545GM_FIBER:
284 case E1000_DEV_ID_82545GM_SERDES:
285 hw->mac_type = em_82545_rev_3;
286 break;
287 case E1000_DEV_ID_82546EB_COPPER:
288 case E1000_DEV_ID_82546EB_FIBER:
289 case E1000_DEV_ID_82546EB_QUAD_COPPER:
290 hw->mac_type = em_82546;
291 break;
292 case E1000_DEV_ID_82546GB_COPPER:
293 case E1000_DEV_ID_82546GB_FIBER:
294 case E1000_DEV_ID_82546GB_SERDES:
295 hw->mac_type = em_82546_rev_3;
296 break;
297 case E1000_DEV_ID_82541EI:
298 case E1000_DEV_ID_82541EI_MOBILE:
299 hw->mac_type = em_82541;
300 break;
301 case E1000_DEV_ID_82541ER:
302 case E1000_DEV_ID_82541GI:
303 case E1000_DEV_ID_82541GI_MOBILE:
304 hw->mac_type = em_82541_rev_2;
305 break;
306 case E1000_DEV_ID_82547EI:
307 hw->mac_type = em_82547;
308 break;
309 case E1000_DEV_ID_82547GI:
310 hw->mac_type = em_82547_rev_2;
311 break;
312 default:
313 /* Should never have loaded on this device */
314 return -E1000_ERR_MAC_TYPE;
315 }
316
317 return E1000_SUCCESS;
318 }
319
320 /*****************************************************************************
321 * Set media type and TBI compatibility.
322 *
323 * hw - Struct containing variables accessed by shared code
324 * **************************************************************************/
325 void
em_set_media_type(struct em_hw * hw)326 em_set_media_type(struct em_hw *hw)
327 {
328 uint32_t status;
329
330 DEBUGFUNC("em_set_media_type");
331
332 if(hw->mac_type != em_82543) {
333 /* tbi_compatibility is only valid on 82543 */
334 hw->tbi_compatibility_en = FALSE;
335 }
336
337 switch (hw->device_id) {
338 case E1000_DEV_ID_82545GM_SERDES:
339 case E1000_DEV_ID_82546GB_SERDES:
340 hw->media_type = em_media_type_internal_serdes;
341 break;
342 default:
343 if(hw->mac_type >= em_82543) {
344 status = E1000_READ_REG(hw, STATUS);
345 if(status & E1000_STATUS_TBIMODE) {
346 hw->media_type = em_media_type_fiber;
347 /* tbi_compatibility not valid on fiber */
348 hw->tbi_compatibility_en = FALSE;
349 } else {
350 hw->media_type = em_media_type_copper;
351 }
352 } else {
353 /* This is an 82542 (fiber only) */
354 hw->media_type = em_media_type_fiber;
355 }
356 }
357 }
358
359 /******************************************************************************
360 * Reset the transmit and receive units; mask and clear all interrupts.
361 *
362 * hw - Struct containing variables accessed by shared code
363 *****************************************************************************/
364 int32_t
em_reset_hw(struct em_hw * hw)365 em_reset_hw(struct em_hw *hw)
366 {
367 uint32_t ctrl;
368 uint32_t ctrl_ext;
369 uint32_t icr;
370 uint32_t manc;
371 uint32_t led_ctrl;
372
373 DEBUGFUNC("em_reset_hw");
374
375 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
376 if(hw->mac_type == em_82542_rev2_0) {
377 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
378 em_pci_clear_mwi(hw);
379 }
380
381 /* Clear interrupt mask to stop board from generating interrupts */
382 DEBUGOUT("Masking off all interrupts\n");
383 E1000_WRITE_REG(hw, IMC, 0xffffffff);
384
385 /* Disable the Transmit and Receive units. Then delay to allow
386 * any pending transactions to complete before we hit the MAC with
387 * the global reset.
388 */
389 E1000_WRITE_REG(hw, RCTL, 0);
390 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
391 E1000_WRITE_FLUSH(hw);
392
393 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
394 hw->tbi_compatibility_on = FALSE;
395
396 /* Delay to allow any outstanding PCI transactions to complete before
397 * resetting the device
398 */
399 msec_delay(10);
400
401 ctrl = E1000_READ_REG(hw, CTRL);
402
403 /* Must reset the PHY before resetting the MAC */
404 if((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
405 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
406 msec_delay(5);
407 }
408
409 /* Issue a global reset to the MAC. This will reset the chip's
410 * transmit, receive, DMA, and link units. It will not effect
411 * the current PCI configuration. The global reset bit is self-
412 * clearing, and should clear within a microsecond.
413 */
414 DEBUGOUT("Issuing a global reset to MAC\n");
415
416 switch(hw->mac_type) {
417 case em_82544:
418 case em_82540:
419 case em_82545:
420 case em_82546:
421 case em_82541:
422 case em_82541_rev_2:
423 /* These controllers can't ack the 64-bit write when issuing the
424 * reset, so use IO-mapping as a workaround to issue the reset */
425 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
426 break;
427 case em_82545_rev_3:
428 case em_82546_rev_3:
429 /* Reset is performed on a shadow of the control register */
430 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
431 break;
432 default:
433 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
434 break;
435 }
436
437 /* After MAC reset, force reload of EEPROM to restore power-on settings to
438 * device. Later controllers reload the EEPROM automatically, so just wait
439 * for reload to complete.
440 */
441 switch(hw->mac_type) {
442 case em_82542_rev2_0:
443 case em_82542_rev2_1:
444 case em_82543:
445 case em_82544:
446 /* Wait for reset to complete */
447 usec_delay(10);
448 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
449 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
450 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
451 E1000_WRITE_FLUSH(hw);
452 /* Wait for EEPROM reload */
453 msec_delay(2);
454 break;
455 case em_82541:
456 case em_82541_rev_2:
457 case em_82547:
458 case em_82547_rev_2:
459 /* Wait for EEPROM reload */
460 msec_delay(20);
461 break;
462 default:
463 /* Wait for EEPROM reload (it happens automatically) */
464 msec_delay(5);
465 break;
466 }
467
468 /* Disable HW ARPs on ASF enabled adapters */
469 if(hw->mac_type >= em_82540) {
470 manc = E1000_READ_REG(hw, MANC);
471 manc &= ~(E1000_MANC_ARP_EN);
472 E1000_WRITE_REG(hw, MANC, manc);
473 }
474
475 if((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
476 em_phy_init_script(hw);
477
478 /* Configure activity LED after PHY reset */
479 led_ctrl = E1000_READ_REG(hw, LEDCTL);
480 led_ctrl &= IGP_ACTIVITY_LED_MASK;
481 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
482 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
483 }
484
485 /* Clear interrupt mask to stop board from generating interrupts */
486 DEBUGOUT("Masking off all interrupts\n");
487 E1000_WRITE_REG(hw, IMC, 0xffffffff);
488
489 /* Clear any pending interrupt events. */
490 icr = E1000_READ_REG(hw, ICR);
491
492 /* If MWI was previously enabled, reenable it. */
493 if(hw->mac_type == em_82542_rev2_0) {
494 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
495 em_pci_set_mwi(hw);
496 }
497
498 return E1000_SUCCESS;
499 }
500
501 /******************************************************************************
502 * Performs basic configuration of the adapter.
503 *
504 * hw - Struct containing variables accessed by shared code
505 *
506 * Assumes that the controller has previously been reset and is in a
507 * post-reset uninitialized state. Initializes the receive address registers,
508 * multicast table, and VLAN filter table. Calls routines to setup link
509 * configuration and flow control settings. Clears all on-chip counters. Leaves
510 * the transmit and receive units disabled and uninitialized.
511 *****************************************************************************/
512 int32_t
em_init_hw(struct em_hw * hw)513 em_init_hw(struct em_hw *hw)
514 {
515 uint32_t ctrl;
516 uint32_t i;
517 int32_t ret_val;
518 uint16_t pcix_cmd_word;
519 uint16_t pcix_stat_hi_word;
520 uint16_t cmd_mmrbc;
521 uint16_t stat_mmrbc;
522
523 DEBUGFUNC("em_init_hw");
524
525 /* Initialize Identification LED */
526 if((ret_val = em_id_led_init(hw))) {
527 DEBUGOUT("Error Initializing Identification LED\n");
528 return ret_val;
529 }
530
531 /* Set the media type and TBI compatibility */
532 em_set_media_type(hw);
533
534 /* Disabling VLAN filtering. */
535 DEBUGOUT("Initializing the IEEE VLAN\n");
536 E1000_WRITE_REG(hw, VET, 0);
537
538 em_clear_vfta(hw);
539
540 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
541 if(hw->mac_type == em_82542_rev2_0) {
542 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
543 em_pci_clear_mwi(hw);
544 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
545 E1000_WRITE_FLUSH(hw);
546 msec_delay(5);
547 }
548
549 /* Setup the receive address. This involves initializing all of the Receive
550 * Address Registers (RARs 0 - 15).
551 */
552 em_init_rx_addrs(hw);
553
554 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
555 if(hw->mac_type == em_82542_rev2_0) {
556 E1000_WRITE_REG(hw, RCTL, 0);
557 E1000_WRITE_FLUSH(hw);
558 msec_delay(1);
559 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
560 em_pci_set_mwi(hw);
561 }
562
563 /* Zero out the Multicast HASH table */
564 DEBUGOUT("Zeroing the MTA\n");
565 for(i = 0; i < E1000_MC_TBL_SIZE; i++)
566 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
567
568 /* Set the PCI priority bit correctly in the CTRL register. This
569 * determines if the adapter gives priority to receives, or if it
570 * gives equal priority to transmits and receives.
571 */
572 if(hw->dma_fairness) {
573 ctrl = E1000_READ_REG(hw, CTRL);
574 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
575 }
576
577 switch(hw->mac_type) {
578 case em_82545_rev_3:
579 case em_82546_rev_3:
580 break;
581 default:
582 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
583 if(hw->bus_type == em_bus_type_pcix) {
584 em_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
585 em_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI,
586 &pcix_stat_hi_word);
587 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
588 PCIX_COMMAND_MMRBC_SHIFT;
589 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
590 PCIX_STATUS_HI_MMRBC_SHIFT;
591 if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
592 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
593 if(cmd_mmrbc > stat_mmrbc) {
594 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
595 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
596 em_write_pci_cfg(hw, PCIX_COMMAND_REGISTER,
597 &pcix_cmd_word);
598 }
599 }
600 break;
601 }
602
603 /* Call a subroutine to configure the link and setup flow control. */
604 ret_val = em_setup_link(hw);
605
606 /* Set the transmit descriptor write-back policy */
607 if(hw->mac_type > em_82544) {
608 ctrl = E1000_READ_REG(hw, TXDCTL);
609 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
610 E1000_WRITE_REG(hw, TXDCTL, ctrl);
611 }
612
613 /* Clear all of the statistics registers (clear on read). It is
614 * important that we do this after we have tried to establish link
615 * because the symbol error count will increment wildly if there
616 * is no link.
617 */
618 em_clear_hw_cntrs(hw);
619
620 return ret_val;
621 }
622
623 /******************************************************************************
624 * Adjust SERDES output amplitude based on EEPROM setting.
625 *
626 * hw - Struct containing variables accessed by shared code.
627 *****************************************************************************/
628 static int32_t
em_adjust_serdes_amplitude(struct em_hw * hw)629 em_adjust_serdes_amplitude(struct em_hw *hw)
630 {
631 uint16_t eeprom_data;
632 int32_t ret_val;
633
634 DEBUGFUNC("em_adjust_serdes_amplitude");
635
636 if(hw->media_type != em_media_type_internal_serdes)
637 return E1000_SUCCESS;
638
639 switch(hw->mac_type) {
640 case em_82545_rev_3:
641 case em_82546_rev_3:
642 break;
643 default:
644 return E1000_SUCCESS;
645 }
646
647 if ((ret_val = em_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,
648 &eeprom_data))) {
649 return ret_val;
650 }
651
652 if(eeprom_data != EEPROM_RESERVED_WORD) {
653 /* Adjust SERDES output amplitude only. */
654 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
655 if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL,
656 eeprom_data)))
657 return ret_val;
658 }
659
660 return E1000_SUCCESS;
661 }
662
663 /******************************************************************************
664 * Configures flow control and link settings.
665 *
666 * hw - Struct containing variables accessed by shared code
667 *
668 * Determines which flow control settings to use. Calls the apropriate media-
669 * specific link configuration function. Configures the flow control settings.
670 * Assuming the adapter has a valid link partner, a valid link should be
671 * established. Assumes the hardware has previously been reset and the
672 * transmitter and receiver are not enabled.
673 *****************************************************************************/
674 int32_t
em_setup_link(struct em_hw * hw)675 em_setup_link(struct em_hw *hw)
676 {
677 uint32_t ctrl_ext;
678 int32_t ret_val;
679 uint16_t eeprom_data;
680
681 DEBUGFUNC("em_setup_link");
682
683 /* Read and store word 0x0F of the EEPROM. This word contains bits
684 * that determine the hardware's default PAUSE (flow control) mode,
685 * a bit that determines whether the HW defaults to enabling or
686 * disabling auto-negotiation, and the direction of the
687 * SW defined pins. If there is no SW over-ride of the flow
688 * control setting, then the variable hw->fc will
689 * be initialized based on a value in the EEPROM.
690 */
691 if(em_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data) < 0) {
692 DEBUGOUT("EEPROM Read Error\n");
693 return -E1000_ERR_EEPROM;
694 }
695
696 if(hw->fc == em_fc_default) {
697 if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
698 hw->fc = em_fc_none;
699 else if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
700 EEPROM_WORD0F_ASM_DIR)
701 hw->fc = em_fc_tx_pause;
702 else
703 hw->fc = em_fc_full;
704 }
705
706 /* We want to save off the original Flow Control configuration just
707 * in case we get disconnected and then reconnected into a different
708 * hub or switch with different Flow Control capabilities.
709 */
710 if(hw->mac_type == em_82542_rev2_0)
711 hw->fc &= (~em_fc_tx_pause);
712
713 if((hw->mac_type < em_82543) && (hw->report_tx_early == 1))
714 hw->fc &= (~em_fc_rx_pause);
715
716 hw->original_fc = hw->fc;
717
718 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
719
720 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
721 * polarity value for the SW controlled pins, and setup the
722 * Extended Device Control reg with that info.
723 * This is needed because one of the SW controlled pins is used for
724 * signal detection. So this should be done before em_setup_pcs_link()
725 * or em_phy_setup() is called.
726 */
727 if(hw->mac_type == em_82543) {
728 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
729 SWDPIO__EXT_SHIFT);
730 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
731 }
732
733 /* Call the necessary subroutine to configure the link. */
734 ret_val = (hw->media_type == em_media_type_copper) ?
735 em_setup_copper_link(hw) :
736 em_setup_fiber_serdes_link(hw);
737
738 /* Initialize the flow control address, type, and PAUSE timer
739 * registers to their default values. This is done even if flow
740 * control is disabled, because it does not hurt anything to
741 * initialize these registers.
742 */
743 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
744
745 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
746 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
747 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
748 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
749
750 /* Set the flow control receive threshold registers. Normally,
751 * these registers will be set to a default threshold that may be
752 * adjusted later by the driver's runtime code. However, if the
753 * ability to transmit pause frames in not enabled, then these
754 * registers will be set to 0.
755 */
756 if(!(hw->fc & em_fc_tx_pause)) {
757 E1000_WRITE_REG(hw, FCRTL, 0);
758 E1000_WRITE_REG(hw, FCRTH, 0);
759 } else {
760 /* We need to set up the Receive Threshold high and low water marks
761 * as well as (optionally) enabling the transmission of XON frames.
762 */
763 if(hw->fc_send_xon) {
764 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
765 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
766 } else {
767 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
768 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
769 }
770 }
771 return ret_val;
772 }
773
774 /******************************************************************************
775 * Sets up link for a fiber based or serdes based adapter
776 *
777 * hw - Struct containing variables accessed by shared code
778 *
779 * Manipulates Physical Coding Sublayer functions in order to configure
780 * link. Assumes the hardware has been previously reset and the transmitter
781 * and receiver are not enabled.
782 *****************************************************************************/
783 static int32_t
em_setup_fiber_serdes_link(struct em_hw * hw)784 em_setup_fiber_serdes_link(struct em_hw *hw)
785 {
786 uint32_t ctrl;
787 uint32_t status;
788 uint32_t txcw = 0;
789 uint32_t i;
790 uint32_t signal = 0;
791 int32_t ret_val;
792
793 DEBUGFUNC("em_setup_fiber_serdes_link");
794
795 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
796 * set when the optics detect a signal. On older adapters, it will be
797 * cleared when there is a signal. This applies to fiber media only.
798 * If we're on serdes media, adjust the output amplitude to value set in
799 * the EEPROM.
800 */
801 ctrl = E1000_READ_REG(hw, CTRL);
802 if(hw->media_type == em_media_type_fiber)
803 signal = (hw->mac_type > em_82544) ? E1000_CTRL_SWDPIN1 : 0;
804
805 if((ret_val = em_adjust_serdes_amplitude(hw)))
806 return ret_val;
807
808 /* Take the link out of reset */
809 ctrl &= ~(E1000_CTRL_LRST);
810
811 /* Adjust VCO speed to improve BER performance */
812 if((ret_val = em_set_vco_speed(hw)))
813 return ret_val;
814
815 em_config_collision_dist(hw);
816
817 /* Check for a software override of the flow control settings, and setup
818 * the device accordingly. If auto-negotiation is enabled, then software
819 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
820 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
821 * auto-negotiation is disabled, then software will have to manually
822 * configure the two flow control enable bits in the CTRL register.
823 *
824 * The possible values of the "fc" parameter are:
825 * 0: Flow control is completely disabled
826 * 1: Rx flow control is enabled (we can receive pause frames, but
827 * not send pause frames).
828 * 2: Tx flow control is enabled (we can send pause frames but we do
829 * not support receiving pause frames).
830 * 3: Both Rx and TX flow control (symmetric) are enabled.
831 */
832 switch (hw->fc) {
833 case em_fc_none:
834 /* Flow control is completely disabled by a software over-ride. */
835 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
836 break;
837 case em_fc_rx_pause:
838 /* RX Flow control is enabled and TX Flow control is disabled by a
839 * software over-ride. Since there really isn't a way to advertise
840 * that we are capable of RX Pause ONLY, we will advertise that we
841 * support both symmetric and asymmetric RX PAUSE. Later, we will
842 * disable the adapter's ability to send PAUSE frames.
843 */
844 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
845 break;
846 case em_fc_tx_pause:
847 /* TX Flow control is enabled, and RX Flow control is disabled, by a
848 * software over-ride.
849 */
850 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
851 break;
852 case em_fc_full:
853 /* Flow control (both RX and TX) is enabled by a software over-ride. */
854 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
855 break;
856 default:
857 DEBUGOUT("Flow control param set incorrectly\n");
858 return -E1000_ERR_CONFIG;
859 break;
860 }
861
862 /* Since auto-negotiation is enabled, take the link out of reset (the link
863 * will be in reset, because we previously reset the chip). This will
864 * restart auto-negotiation. If auto-neogtiation is successful then the
865 * link-up status bit will be set and the flow control enable bits (RFCE
866 * and TFCE) will be set according to their negotiated value.
867 */
868 DEBUGOUT("Auto-negotiation enabled\n");
869
870 E1000_WRITE_REG(hw, TXCW, txcw);
871 E1000_WRITE_REG(hw, CTRL, ctrl);
872 E1000_WRITE_FLUSH(hw);
873
874 hw->txcw = txcw;
875 msec_delay(1);
876
877 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
878 * indication in the Device Status Register. Time-out if a link isn't
879 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
880 * less than 500 milliseconds even if the other end is doing it in SW).
881 * For internal serdes, we just assume a signal is present, then poll.
882 */
883 if(hw->media_type == em_media_type_internal_serdes ||
884 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
885 DEBUGOUT("Looking for Link\n");
886 for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
887 msec_delay(10);
888 status = E1000_READ_REG(hw, STATUS);
889 if(status & E1000_STATUS_LU) break;
890 }
891 if(i == (LINK_UP_TIMEOUT / 10)) {
892 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
893 hw->autoneg_failed = 1;
894 /* AutoNeg failed to achieve a link, so we'll call
895 * em_check_for_link. This routine will force the link up if
896 * we detect a signal. This will allow us to communicate with
897 * non-autonegotiating link partners.
898 */
899 if((ret_val = em_check_for_link(hw))) {
900 DEBUGOUT("Error while checking for link\n");
901 return ret_val;
902 }
903 hw->autoneg_failed = 0;
904 } else {
905 hw->autoneg_failed = 0;
906 DEBUGOUT("Valid Link Found\n");
907 }
908 } else {
909 DEBUGOUT("No Signal Detected\n");
910 }
911 return E1000_SUCCESS;
912 }
913
914 /******************************************************************************
915 * Detects which PHY is present and the speed and duplex
916 *
917 * hw - Struct containing variables accessed by shared code
918 ******************************************************************************/
919 static int32_t
em_setup_copper_link(struct em_hw * hw)920 em_setup_copper_link(struct em_hw *hw)
921 {
922 uint32_t ctrl;
923 uint32_t led_ctrl;
924 int32_t ret_val;
925 uint16_t i;
926 uint16_t phy_data;
927
928 DEBUGFUNC("em_setup_copper_link");
929
930 ctrl = E1000_READ_REG(hw, CTRL);
931 /* With 82543, we need to force speed and duplex on the MAC equal to what
932 * the PHY speed and duplex configuration is. In addition, we need to
933 * perform a hardware reset on the PHY to take it out of reset.
934 */
935 if(hw->mac_type > em_82543) {
936 ctrl |= E1000_CTRL_SLU;
937 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
938 E1000_WRITE_REG(hw, CTRL, ctrl);
939 } else {
940 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
941 E1000_WRITE_REG(hw, CTRL, ctrl);
942 em_phy_hw_reset(hw);
943 }
944
945 /* Make sure we have a valid PHY */
946 if((ret_val = em_detect_gig_phy(hw))) {
947 DEBUGOUT("Error, did not detect valid phy.\n");
948 return ret_val;
949 }
950 DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
951
952 if(hw->mac_type <= em_82543 ||
953 hw->mac_type == em_82541 || hw->mac_type == em_82547 ||
954 hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2)
955 hw->phy_reset_disable = FALSE;
956
957 if(!hw->phy_reset_disable) {
958 if (hw->phy_type == em_phy_igp) {
959
960 if((ret_val = em_phy_reset(hw))) {
961 DEBUGOUT("Error Resetting the PHY\n");
962 return ret_val;
963 }
964
965 /* Wait 10ms for MAC to configure PHY from eeprom settings */
966 msec_delay(15);
967
968 /* Configure activity LED after PHY reset */
969 led_ctrl = E1000_READ_REG(hw, LEDCTL);
970 led_ctrl &= IGP_ACTIVITY_LED_MASK;
971 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
972 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
973
974 /* disable lplu d3 during driver init */
975 if((ret_val = em_set_d3_lplu_state(hw, FALSE))) {
976 DEBUGOUT("Error Disabling LPLU D3\n");
977 return ret_val;
978 }
979
980 /* Configure mdi-mdix settings */
981 if((ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
982 &phy_data)))
983 return ret_val;
984
985 if((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
986 hw->dsp_config_state = em_dsp_config_disabled;
987 /* Force MDI for IGP B-0 PHY */
988 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX |
989 IGP01E1000_PSCR_FORCE_MDI_MDIX);
990 hw->mdix = 1;
991
992 } else {
993 hw->dsp_config_state = em_dsp_config_enabled;
994 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
995
996 switch (hw->mdix) {
997 case 1:
998 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
999 break;
1000 case 2:
1001 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1002 break;
1003 case 0:
1004 default:
1005 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1006 break;
1007 }
1008 }
1009 if((ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
1010 phy_data)))
1011 return ret_val;
1012
1013 /* set auto-master slave resolution settings */
1014 if(hw->autoneg) {
1015 em_ms_type phy_ms_setting = hw->master_slave;
1016
1017 if(hw->ffe_config_state == em_ffe_config_active)
1018 hw->ffe_config_state = em_ffe_config_enabled;
1019
1020 if(hw->dsp_config_state == em_dsp_config_activated)
1021 hw->dsp_config_state = em_dsp_config_enabled;
1022
1023 /* when autonegotiation advertisment is only 1000Mbps then we
1024 * should disable SmartSpeed and enable Auto MasterSlave
1025 * resolution as hardware default. */
1026 if(hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1027 /* Disable SmartSpeed */
1028 if((ret_val = em_read_phy_reg(hw,
1029 IGP01E1000_PHY_PORT_CONFIG,
1030 &phy_data)))
1031 return ret_val;
1032 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1033 if((ret_val = em_write_phy_reg(hw,
1034 IGP01E1000_PHY_PORT_CONFIG,
1035 phy_data)))
1036 return ret_val;
1037 /* Set auto Master/Slave resolution process */
1038 if((ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL,
1039 &phy_data)))
1040 return ret_val;
1041 phy_data &= ~CR_1000T_MS_ENABLE;
1042 if((ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL,
1043 phy_data)))
1044 return ret_val;
1045 }
1046
1047 if((ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL,
1048 &phy_data)))
1049 return ret_val;
1050
1051 /* load defaults for future use */
1052 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1053 ((phy_data & CR_1000T_MS_VALUE) ?
1054 em_ms_force_master :
1055 em_ms_force_slave) :
1056 em_ms_auto;
1057
1058 switch (phy_ms_setting) {
1059 case em_ms_force_master:
1060 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1061 break;
1062 case em_ms_force_slave:
1063 phy_data |= CR_1000T_MS_ENABLE;
1064 phy_data &= ~(CR_1000T_MS_VALUE);
1065 break;
1066 case em_ms_auto:
1067 phy_data &= ~CR_1000T_MS_ENABLE;
1068 default:
1069 break;
1070 }
1071 if((ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL,
1072 phy_data)))
1073 return ret_val;
1074 }
1075 } else {
1076 /* Enable CRS on TX. This must be set for half-duplex operation. */
1077 if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1078 &phy_data)))
1079 return ret_val;
1080
1081 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1082
1083 /* Options:
1084 * MDI/MDI-X = 0 (default)
1085 * 0 - Auto for all speeds
1086 * 1 - MDI mode
1087 * 2 - MDI-X mode
1088 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1089 */
1090 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1091
1092 switch (hw->mdix) {
1093 case 1:
1094 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1095 break;
1096 case 2:
1097 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1098 break;
1099 case 3:
1100 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1101 break;
1102 case 0:
1103 default:
1104 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1105 break;
1106 }
1107
1108 /* Options:
1109 * disable_polarity_correction = 0 (default)
1110 * Automatic Correction for Reversed Cable Polarity
1111 * 0 - Disabled
1112 * 1 - Enabled
1113 */
1114 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1115 if(hw->disable_polarity_correction == 1)
1116 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1117 if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1118 phy_data)))
1119 return ret_val;
1120
1121 /* Force TX_CLK in the Extended PHY Specific Control Register
1122 * to 25MHz clock.
1123 */
1124 if((ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1125 &phy_data)))
1126 return ret_val;
1127
1128 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1129
1130 if (hw->phy_revision < M88E1011_I_REV_4) {
1131 /* Configure Master and Slave downshift values */
1132 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1133 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1134 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1135 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1136 if((ret_val = em_write_phy_reg(hw,
1137 M88E1000_EXT_PHY_SPEC_CTRL,
1138 phy_data)))
1139 return ret_val;
1140 }
1141
1142 /* SW Reset the PHY so all changes take effect */
1143 if((ret_val = em_phy_reset(hw))) {
1144 DEBUGOUT("Error Resetting the PHY\n");
1145 return ret_val;
1146 }
1147 }
1148
1149 /* Options:
1150 * autoneg = 1 (default)
1151 * PHY will advertise value(s) parsed from
1152 * autoneg_advertised and fc
1153 * autoneg = 0
1154 * PHY will be set to 10H, 10F, 100H, or 100F
1155 * depending on value parsed from forced_speed_duplex.
1156 */
1157
1158 /* Is autoneg enabled? This is enabled by default or by software
1159 * override. If so, call em_phy_setup_autoneg routine to parse the
1160 * autoneg_advertised and fc options. If autoneg is NOT enabled, then
1161 * the user should have provided a speed/duplex override. If so, then
1162 * call em_phy_force_speed_duplex to parse and set this up.
1163 */
1164 if(hw->autoneg) {
1165 /* Perform some bounds checking on the hw->autoneg_advertised
1166 * parameter. If this variable is zero, then set it to the default.
1167 */
1168 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1169
1170 /* If autoneg_advertised is zero, we assume it was not defaulted
1171 * by the calling code so we set to advertise full capability.
1172 */
1173 if(hw->autoneg_advertised == 0)
1174 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1175
1176 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1177 if((ret_val = em_phy_setup_autoneg(hw))) {
1178 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1179 return ret_val;
1180 }
1181 DEBUGOUT("Restarting Auto-Neg\n");
1182
1183 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1184 * the Auto Neg Restart bit in the PHY control register.
1185 */
1186 if((ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data)))
1187 return ret_val;
1188
1189 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1190 if((ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data)))
1191 return ret_val;
1192
1193 /* Does the user want to wait for Auto-Neg to complete here, or
1194 * check at a later time (for example, callback routine).
1195 */
1196 if(hw->wait_autoneg_complete) {
1197 if((ret_val = em_wait_autoneg(hw))) {
1198 DEBUGOUT("Error while waiting for autoneg to complete\n");
1199 return ret_val;
1200 }
1201 }
1202 hw->get_link_status = TRUE;
1203 } else {
1204 DEBUGOUT("Forcing speed and duplex\n");
1205 if((ret_val = em_phy_force_speed_duplex(hw))) {
1206 DEBUGOUT("Error Forcing Speed and Duplex\n");
1207 return ret_val;
1208 }
1209 }
1210 } /* !hw->phy_reset_disable */
1211
1212 /* Check link status. Wait up to 100 microseconds for link to become
1213 * valid.
1214 */
1215 for(i = 0; i < 10; i++) {
1216 if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data)))
1217 return ret_val;
1218 if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data)))
1219 return ret_val;
1220
1221 if(phy_data & MII_SR_LINK_STATUS) {
1222 /* We have link, so we need to finish the config process:
1223 * 1) Set up the MAC to the current PHY speed/duplex
1224 * if we are on 82543. If we
1225 * are on newer silicon, we only need to configure
1226 * collision distance in the Transmit Control Register.
1227 * 2) Set up flow control on the MAC to that established with
1228 * the link partner.
1229 */
1230 if(hw->mac_type >= em_82544) {
1231 em_config_collision_dist(hw);
1232 } else {
1233 if((ret_val = em_config_mac_to_phy(hw))) {
1234 DEBUGOUT("Error configuring MAC to PHY settings\n");
1235 return ret_val;
1236 }
1237 }
1238 if((ret_val = em_config_fc_after_link_up(hw))) {
1239 DEBUGOUT("Error Configuring Flow Control\n");
1240 return ret_val;
1241 }
1242 DEBUGOUT("Valid link established!!!\n");
1243
1244 if(hw->phy_type == em_phy_igp) {
1245 if((ret_val = em_config_dsp_after_link_change(hw, TRUE))) {
1246 DEBUGOUT("Error Configuring DSP after link up\n");
1247 return ret_val;
1248 }
1249 }
1250 DEBUGOUT("Valid link established!!!\n");
1251 return E1000_SUCCESS;
1252 }
1253 usec_delay(10);
1254 }
1255
1256 DEBUGOUT("Unable to establish link!!!\n");
1257 return E1000_SUCCESS;
1258 }
1259
1260 /******************************************************************************
1261 * Configures PHY autoneg and flow control advertisement settings
1262 *
1263 * hw - Struct containing variables accessed by shared code
1264 ******************************************************************************/
1265 int32_t
em_phy_setup_autoneg(struct em_hw * hw)1266 em_phy_setup_autoneg(struct em_hw *hw)
1267 {
1268 int32_t ret_val;
1269 uint16_t mii_autoneg_adv_reg;
1270 uint16_t mii_1000t_ctrl_reg;
1271
1272 DEBUGFUNC("em_phy_setup_autoneg");
1273
1274 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1275 if((ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV,
1276 &mii_autoneg_adv_reg)))
1277 return ret_val;
1278
1279 /* Read the MII 1000Base-T Control Register (Address 9). */
1280 if((ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg)))
1281 return ret_val;
1282
1283 /* Need to parse both autoneg_advertised and fc and set up
1284 * the appropriate PHY registers. First we will parse for
1285 * autoneg_advertised software override. Since we can advertise
1286 * a plethora of combinations, we need to check each bit
1287 * individually.
1288 */
1289
1290 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1291 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1292 * the 1000Base-T Control Register (Address 9).
1293 */
1294 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
1295 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1296
1297 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
1298
1299 /* Do we want to advertise 10 Mb Half Duplex? */
1300 if(hw->autoneg_advertised & ADVERTISE_10_HALF) {
1301 DEBUGOUT("Advertise 10mb Half duplex\n");
1302 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1303 }
1304
1305 /* Do we want to advertise 10 Mb Full Duplex? */
1306 if(hw->autoneg_advertised & ADVERTISE_10_FULL) {
1307 DEBUGOUT("Advertise 10mb Full duplex\n");
1308 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1309 }
1310
1311 /* Do we want to advertise 100 Mb Half Duplex? */
1312 if(hw->autoneg_advertised & ADVERTISE_100_HALF) {
1313 DEBUGOUT("Advertise 100mb Half duplex\n");
1314 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1315 }
1316
1317 /* Do we want to advertise 100 Mb Full Duplex? */
1318 if(hw->autoneg_advertised & ADVERTISE_100_FULL) {
1319 DEBUGOUT("Advertise 100mb Full duplex\n");
1320 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1321 }
1322
1323 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1324 if(hw->autoneg_advertised & ADVERTISE_1000_HALF) {
1325 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
1326 }
1327
1328 /* Do we want to advertise 1000 Mb Full Duplex? */
1329 if(hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1330 DEBUGOUT("Advertise 1000mb Full duplex\n");
1331 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1332 }
1333
1334 /* Check for a software override of the flow control settings, and
1335 * setup the PHY advertisement registers accordingly. If
1336 * auto-negotiation is enabled, then software will have to set the
1337 * "PAUSE" bits to the correct value in the Auto-Negotiation
1338 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
1339 *
1340 * The possible values of the "fc" parameter are:
1341 * 0: Flow control is completely disabled
1342 * 1: Rx flow control is enabled (we can receive pause frames
1343 * but not send pause frames).
1344 * 2: Tx flow control is enabled (we can send pause frames
1345 * but we do not support receiving pause frames).
1346 * 3: Both Rx and TX flow control (symmetric) are enabled.
1347 * other: No software override. The flow control configuration
1348 * in the EEPROM is used.
1349 */
1350 switch (hw->fc) {
1351 case em_fc_none: /* 0 */
1352 /* Flow control (RX & TX) is completely disabled by a
1353 * software over-ride.
1354 */
1355 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1356 break;
1357 case em_fc_rx_pause: /* 1 */
1358 /* RX Flow control is enabled, and TX Flow control is
1359 * disabled, by a software over-ride.
1360 */
1361 /* Since there really isn't a way to advertise that we are
1362 * capable of RX Pause ONLY, we will advertise that we
1363 * support both symmetric and asymmetric RX PAUSE. Later
1364 * (in em_config_fc_after_link_up) we will disable the
1365 *hw's ability to send PAUSE frames.
1366 */
1367 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1368 break;
1369 case em_fc_tx_pause: /* 2 */
1370 /* TX Flow control is enabled, and RX Flow control is
1371 * disabled, by a software over-ride.
1372 */
1373 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1374 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1375 break;
1376 case em_fc_full: /* 3 */
1377 /* Flow control (both RX and TX) is enabled by a software
1378 * over-ride.
1379 */
1380 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1381 break;
1382 default:
1383 DEBUGOUT("Flow control param set incorrectly\n");
1384 return -E1000_ERR_CONFIG;
1385 }
1386
1387 if((ret_val = em_write_phy_reg(hw, PHY_AUTONEG_ADV,
1388 mii_autoneg_adv_reg)))
1389 return ret_val;
1390
1391 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1392
1393 if((ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg)))
1394 return ret_val;
1395
1396 return E1000_SUCCESS;
1397 }
1398
1399 /******************************************************************************
1400 * Force PHY speed and duplex settings to hw->forced_speed_duplex
1401 *
1402 * hw - Struct containing variables accessed by shared code
1403 ******************************************************************************/
1404 static int32_t
em_phy_force_speed_duplex(struct em_hw * hw)1405 em_phy_force_speed_duplex(struct em_hw *hw)
1406 {
1407 uint32_t ctrl;
1408 int32_t ret_val;
1409 uint16_t mii_ctrl_reg;
1410 uint16_t mii_status_reg;
1411 uint16_t phy_data;
1412 uint16_t i;
1413
1414 DEBUGFUNC("em_phy_force_speed_duplex");
1415
1416 /* Turn off Flow control if we are forcing speed and duplex. */
1417 hw->fc = em_fc_none;
1418
1419 DEBUGOUT1("hw->fc = %d\n", hw->fc);
1420
1421 /* Read the Device Control Register. */
1422 ctrl = E1000_READ_REG(hw, CTRL);
1423
1424 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
1425 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1426 ctrl &= ~(DEVICE_SPEED_MASK);
1427
1428 /* Clear the Auto Speed Detect Enable bit. */
1429 ctrl &= ~E1000_CTRL_ASDE;
1430
1431 /* Read the MII Control Register. */
1432 if((ret_val = em_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg)))
1433 return ret_val;
1434
1435 /* We need to disable autoneg in order to force link and duplex. */
1436
1437 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
1438
1439 /* Are we forcing Full or Half Duplex? */
1440 if(hw->forced_speed_duplex == em_100_full ||
1441 hw->forced_speed_duplex == em_10_full) {
1442 /* We want to force full duplex so we SET the full duplex bits in the
1443 * Device and MII Control Registers.
1444 */
1445 ctrl |= E1000_CTRL_FD;
1446 mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
1447 DEBUGOUT("Full Duplex\n");
1448 } else {
1449 /* We want to force half duplex so we CLEAR the full duplex bits in
1450 * the Device and MII Control Registers.
1451 */
1452 ctrl &= ~E1000_CTRL_FD;
1453 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
1454 DEBUGOUT("Half Duplex\n");
1455 }
1456
1457 /* Are we forcing 100Mbps??? */
1458 if(hw->forced_speed_duplex == em_100_full ||
1459 hw->forced_speed_duplex == em_100_half) {
1460 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
1461 ctrl |= E1000_CTRL_SPD_100;
1462 mii_ctrl_reg |= MII_CR_SPEED_100;
1463 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1464 DEBUGOUT("Forcing 100mb ");
1465 } else {
1466 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
1467 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1468 mii_ctrl_reg |= MII_CR_SPEED_10;
1469 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1470 DEBUGOUT("Forcing 10mb ");
1471 }
1472
1473 em_config_collision_dist(hw);
1474
1475 /* Write the configured values back to the Device Control Reg. */
1476 E1000_WRITE_REG(hw, CTRL, ctrl);
1477
1478 if (hw->phy_type == em_phy_m88) {
1479 if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1480 &phy_data)))
1481 return ret_val;
1482
1483 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1484 * forced whenever speed are duplex are forced.
1485 */
1486 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1487 if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1488 phy_data)))
1489 return ret_val;
1490
1491 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
1492
1493 /* Need to reset the PHY or these changes will be ignored */
1494 mii_ctrl_reg |= MII_CR_RESET;
1495 } else {
1496 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1497 * forced whenever speed or duplex are forced.
1498 */
1499 if((ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
1500 &phy_data)))
1501 return ret_val;
1502
1503 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1504 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1505
1506 if((ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
1507 phy_data)))
1508 return ret_val;
1509 }
1510
1511 /* Write back the modified PHY MII control register. */
1512 if((ret_val = em_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg)))
1513 return ret_val;
1514
1515 usec_delay(1);
1516
1517 /* The wait_autoneg_complete flag may be a little misleading here.
1518 * Since we are forcing speed and duplex, Auto-Neg is not enabled.
1519 * But we do want to delay for a period while forcing only so we
1520 * don't generate false No Link messages. So we will wait here
1521 * only if the user has set wait_autoneg_complete to 1, which is
1522 * the default.
1523 */
1524 if(hw->wait_autoneg_complete) {
1525 /* We will wait for autoneg to complete. */
1526 DEBUGOUT("Waiting for forced speed/duplex link.\n");
1527 mii_status_reg = 0;
1528
1529 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
1530 for(i = PHY_FORCE_TIME; i > 0; i--) {
1531 /* Read the MII Status Register and wait for Auto-Neg Complete bit
1532 * to be set.
1533 */
1534 if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
1535 return ret_val;
1536
1537 if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
1538 return ret_val;
1539
1540 if(mii_status_reg & MII_SR_LINK_STATUS) break;
1541 msec_delay(100);
1542 }
1543 if((i == 0) && (hw->phy_type == em_phy_m88)) {
1544 /* We didn't get link. Reset the DSP and wait again for link. */
1545 if((ret_val = em_phy_reset_dsp(hw))) {
1546 DEBUGOUT("Error Resetting PHY DSP\n");
1547 return ret_val;
1548 }
1549 }
1550 /* This loop will early-out if the link condition has been met. */
1551 for(i = PHY_FORCE_TIME; i > 0; i--) {
1552 if(mii_status_reg & MII_SR_LINK_STATUS) break;
1553 msec_delay(100);
1554 /* Read the MII Status Register and wait for Auto-Neg Complete bit
1555 * to be set.
1556 */
1557 if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
1558 return ret_val;
1559
1560 if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
1561 return ret_val;
1562 }
1563 }
1564
1565 if (hw->phy_type == em_phy_m88) {
1566 /* Because we reset the PHY above, we need to re-force TX_CLK in the
1567 * Extended PHY Specific Control Register to 25MHz clock. This value
1568 * defaults back to a 2.5MHz clock when the PHY is reset.
1569 */
1570 if((ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1571 &phy_data)))
1572 return ret_val;
1573
1574 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1575 if((ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1576 phy_data)))
1577 return ret_val;
1578
1579 /* In addition, because of the s/w reset above, we need to enable CRS on
1580 * TX. This must be set for both full and half duplex operation.
1581 */
1582 if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1583 &phy_data)))
1584 return ret_val;
1585
1586 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1587 if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1588 phy_data)))
1589 return ret_val;
1590
1591 /* Polarity reversal workaround for forced 10F/10H links. */
1592 if(hw->mac_type <= em_82544 &&
1593 (hw->forced_speed_duplex == em_10_full ||
1594 hw->forced_speed_duplex == em_10_half)) {
1595 if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT,
1596 0x0019)))
1597 return ret_val;
1598 if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL,
1599 0x8F0F)))
1600 return ret_val;
1601 /* IEEE requirement is 150ms */
1602 msec_delay(200);
1603 if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT,
1604 0x0019)))
1605 return ret_val;
1606 if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL,
1607 0x8F00)))
1608 return ret_val;
1609 }
1610 }
1611 return E1000_SUCCESS;
1612 }
1613
1614 /******************************************************************************
1615 * Sets the collision distance in the Transmit Control register
1616 *
1617 * hw - Struct containing variables accessed by shared code
1618 *
1619 * Link should have been established previously. Reads the speed and duplex
1620 * information from the Device Status register.
1621 ******************************************************************************/
1622 void
em_config_collision_dist(struct em_hw * hw)1623 em_config_collision_dist(struct em_hw *hw)
1624 {
1625 uint32_t tctl;
1626
1627 DEBUGFUNC("em_config_collision_dist");
1628
1629 tctl = E1000_READ_REG(hw, TCTL);
1630
1631 tctl &= ~E1000_TCTL_COLD;
1632 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
1633
1634 E1000_WRITE_REG(hw, TCTL, tctl);
1635 E1000_WRITE_FLUSH(hw);
1636 }
1637
1638 /******************************************************************************
1639 * Sets MAC speed and duplex settings to reflect the those in the PHY
1640 *
1641 * hw - Struct containing variables accessed by shared code
1642 * mii_reg - data to write to the MII control register
1643 *
1644 * The contents of the PHY register containing the needed information need to
1645 * be passed in.
1646 ******************************************************************************/
1647 static int32_t
em_config_mac_to_phy(struct em_hw * hw)1648 em_config_mac_to_phy(struct em_hw *hw)
1649 {
1650 uint32_t ctrl;
1651 int32_t ret_val;
1652 uint16_t phy_data;
1653
1654 DEBUGFUNC("em_config_mac_to_phy");
1655
1656 /* Read the Device Control Register and set the bits to Force Speed
1657 * and Duplex.
1658 */
1659 ctrl = E1000_READ_REG(hw, CTRL);
1660 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1661 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
1662
1663 /* Set up duplex in the Device Control and Transmit Control
1664 * registers depending on negotiated values.
1665 */
1666 if (hw->phy_type == em_phy_igp) {
1667 if((ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
1668 &phy_data)))
1669 return ret_val;
1670
1671 if(phy_data & IGP01E1000_PSSR_FULL_DUPLEX) ctrl |= E1000_CTRL_FD;
1672 else ctrl &= ~E1000_CTRL_FD;
1673
1674 em_config_collision_dist(hw);
1675
1676 /* Set up speed in the Device Control register depending on
1677 * negotiated values.
1678 */
1679 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
1680 IGP01E1000_PSSR_SPEED_1000MBPS)
1681 ctrl |= E1000_CTRL_SPD_1000;
1682 else if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
1683 IGP01E1000_PSSR_SPEED_100MBPS)
1684 ctrl |= E1000_CTRL_SPD_100;
1685 } else {
1686 if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
1687 &phy_data)))
1688 return ret_val;
1689
1690 if(phy_data & M88E1000_PSSR_DPLX) ctrl |= E1000_CTRL_FD;
1691 else ctrl &= ~E1000_CTRL_FD;
1692
1693 em_config_collision_dist(hw);
1694
1695 /* Set up speed in the Device Control register depending on
1696 * negotiated values.
1697 */
1698 if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
1699 ctrl |= E1000_CTRL_SPD_1000;
1700 else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
1701 ctrl |= E1000_CTRL_SPD_100;
1702 }
1703 /* Write the configured values back to the Device Control Reg. */
1704 E1000_WRITE_REG(hw, CTRL, ctrl);
1705 return E1000_SUCCESS;
1706 }
1707
1708 /******************************************************************************
1709 * Forces the MAC's flow control settings.
1710 *
1711 * hw - Struct containing variables accessed by shared code
1712 *
1713 * Sets the TFCE and RFCE bits in the device control register to reflect
1714 * the adapter settings. TFCE and RFCE need to be explicitly set by
1715 * software when a Copper PHY is used because autonegotiation is managed
1716 * by the PHY rather than the MAC. Software must also configure these
1717 * bits when link is forced on a fiber connection.
1718 *****************************************************************************/
1719 int32_t
em_force_mac_fc(struct em_hw * hw)1720 em_force_mac_fc(struct em_hw *hw)
1721 {
1722 uint32_t ctrl;
1723
1724 DEBUGFUNC("em_force_mac_fc");
1725
1726 /* Get the current configuration of the Device Control Register */
1727 ctrl = E1000_READ_REG(hw, CTRL);
1728
1729 /* Because we didn't get link via the internal auto-negotiation
1730 * mechanism (we either forced link or we got link via PHY
1731 * auto-neg), we have to manually enable/disable transmit an
1732 * receive flow control.
1733 *
1734 * The "Case" statement below enables/disable flow control
1735 * according to the "hw->fc" parameter.
1736 *
1737 * The possible values of the "fc" parameter are:
1738 * 0: Flow control is completely disabled
1739 * 1: Rx flow control is enabled (we can receive pause
1740 * frames but not send pause frames).
1741 * 2: Tx flow control is enabled (we can send pause frames
1742 * frames but we do not receive pause frames).
1743 * 3: Both Rx and TX flow control (symmetric) is enabled.
1744 * other: No other values should be possible at this point.
1745 */
1746
1747 switch (hw->fc) {
1748 case em_fc_none:
1749 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1750 break;
1751 case em_fc_rx_pause:
1752 ctrl &= (~E1000_CTRL_TFCE);
1753 ctrl |= E1000_CTRL_RFCE;
1754 break;
1755 case em_fc_tx_pause:
1756 ctrl &= (~E1000_CTRL_RFCE);
1757 ctrl |= E1000_CTRL_TFCE;
1758 break;
1759 case em_fc_full:
1760 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1761 break;
1762 default:
1763 DEBUGOUT("Flow control param set incorrectly\n");
1764 return -E1000_ERR_CONFIG;
1765 }
1766
1767 /* Disable TX Flow Control for 82542 (rev 2.0) */
1768 if(hw->mac_type == em_82542_rev2_0)
1769 ctrl &= (~E1000_CTRL_TFCE);
1770
1771 E1000_WRITE_REG(hw, CTRL, ctrl);
1772 return E1000_SUCCESS;
1773 }
1774
1775 /******************************************************************************
1776 * Configures flow control settings after link is established
1777 *
1778 * hw - Struct containing variables accessed by shared code
1779 *
1780 * Should be called immediately after a valid link has been established.
1781 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
1782 * and autonegotiation is enabled, the MAC flow control settings will be set
1783 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
1784 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
1785 *****************************************************************************/
1786 int32_t
em_config_fc_after_link_up(struct em_hw * hw)1787 em_config_fc_after_link_up(struct em_hw *hw)
1788 {
1789 int32_t ret_val;
1790 uint16_t mii_status_reg;
1791 uint16_t mii_nway_adv_reg;
1792 uint16_t mii_nway_lp_ability_reg;
1793 uint16_t speed;
1794 uint16_t duplex;
1795
1796 DEBUGFUNC("em_config_fc_after_link_up");
1797
1798 /* Check for the case where we have fiber media and auto-neg failed
1799 * so we had to force link. In this case, we need to force the
1800 * configuration of the MAC to match the "fc" parameter.
1801 */
1802 if(((hw->media_type == em_media_type_fiber) && (hw->autoneg_failed)) ||
1803 ((hw->media_type == em_media_type_internal_serdes) && (hw->autoneg_failed)) ||
1804 ((hw->media_type == em_media_type_copper) && (!hw->autoneg))) {
1805 if((ret_val = em_force_mac_fc(hw))) {
1806 DEBUGOUT("Error forcing flow control settings\n");
1807 return ret_val;
1808 }
1809 }
1810
1811 /* Check for the case where we have copper media and auto-neg is
1812 * enabled. In this case, we need to check and see if Auto-Neg
1813 * has completed, and if so, how the PHY and link partner has
1814 * flow control configured.
1815 */
1816 if((hw->media_type == em_media_type_copper) && hw->autoneg) {
1817 /* Read the MII Status Register and check to see if AutoNeg
1818 * has completed. We read this twice because this reg has
1819 * some "sticky" (latched) bits.
1820 */
1821 if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
1822 return ret_val;
1823 if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
1824 return ret_val;
1825
1826 if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
1827 /* The AutoNeg process has completed, so we now need to
1828 * read both the Auto Negotiation Advertisement Register
1829 * (Address 4) and the Auto_Negotiation Base Page Ability
1830 * Register (Address 5) to determine how flow control was
1831 * negotiated.
1832 */
1833 if((ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV,
1834 &mii_nway_adv_reg)))
1835 return ret_val;
1836 if((ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY,
1837 &mii_nway_lp_ability_reg)))
1838 return ret_val;
1839
1840 /* Two bits in the Auto Negotiation Advertisement Register
1841 * (Address 4) and two bits in the Auto Negotiation Base
1842 * Page Ability Register (Address 5) determine flow control
1843 * for both the PHY and the link partner. The following
1844 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1845 * 1999, describes these PAUSE resolution bits and how flow
1846 * control is determined based upon these settings.
1847 * NOTE: DC = Don't Care
1848 *
1849 * LOCAL DEVICE | LINK PARTNER
1850 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1851 *-------|---------|-------|---------|--------------------
1852 * 0 | 0 | DC | DC | em_fc_none
1853 * 0 | 1 | 0 | DC | em_fc_none
1854 * 0 | 1 | 1 | 0 | em_fc_none
1855 * 0 | 1 | 1 | 1 | em_fc_tx_pause
1856 * 1 | 0 | 0 | DC | em_fc_none
1857 * 1 | DC | 1 | DC | em_fc_full
1858 * 1 | 1 | 0 | 0 | em_fc_none
1859 * 1 | 1 | 0 | 1 | em_fc_rx_pause
1860 *
1861 */
1862 /* Are both PAUSE bits set to 1? If so, this implies
1863 * Symmetric Flow Control is enabled at both ends. The
1864 * ASM_DIR bits are irrelevant per the spec.
1865 *
1866 * For Symmetric Flow Control:
1867 *
1868 * LOCAL DEVICE | LINK PARTNER
1869 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1870 *-------|---------|-------|---------|--------------------
1871 * 1 | DC | 1 | DC | em_fc_full
1872 *
1873 */
1874 if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1875 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1876 /* Now we need to check if the user selected RX ONLY
1877 * of pause frames. In this case, we had to advertise
1878 * FULL flow control because we could not advertise RX
1879 * ONLY. Hence, we must now check to see if we need to
1880 * turn OFF the TRANSMISSION of PAUSE frames.
1881 */
1882 if(hw->original_fc == em_fc_full) {
1883 hw->fc = em_fc_full;
1884 DEBUGOUT("Flow Control = FULL.\r\n");
1885 } else {
1886 hw->fc = em_fc_rx_pause;
1887 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1888 }
1889 }
1890 /* For receiving PAUSE frames ONLY.
1891 *
1892 * LOCAL DEVICE | LINK PARTNER
1893 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1894 *-------|---------|-------|---------|--------------------
1895 * 0 | 1 | 1 | 1 | em_fc_tx_pause
1896 *
1897 */
1898 else if(!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1899 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1900 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1901 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1902 hw->fc = em_fc_tx_pause;
1903 DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n");
1904 }
1905 /* For transmitting PAUSE frames ONLY.
1906 *
1907 * LOCAL DEVICE | LINK PARTNER
1908 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1909 *-------|---------|-------|---------|--------------------
1910 * 1 | 1 | 0 | 1 | em_fc_rx_pause
1911 *
1912 */
1913 else if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1914 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1915 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1916 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1917 hw->fc = em_fc_rx_pause;
1918 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1919 }
1920 /* Per the IEEE spec, at this point flow control should be
1921 * disabled. However, we want to consider that we could
1922 * be connected to a legacy switch that doesn't advertise
1923 * desired flow control, but can be forced on the link
1924 * partner. So if we advertised no flow control, that is
1925 * what we will resolve to. If we advertised some kind of
1926 * receive capability (Rx Pause Only or Full Flow Control)
1927 * and the link partner advertised none, we will configure
1928 * ourselves to enable Rx Flow Control only. We can do
1929 * this safely for two reasons: If the link partner really
1930 * didn't want flow control enabled, and we enable Rx, no
1931 * harm done since we won't be receiving any PAUSE frames
1932 * anyway. If the intent on the link partner was to have
1933 * flow control enabled, then by us enabling RX only, we
1934 * can at least receive pause frames and process them.
1935 * This is a good idea because in most cases, since we are
1936 * predominantly a server NIC, more times than not we will
1937 * be asked to delay transmission of packets than asking
1938 * our link partner to pause transmission of frames.
1939 */
1940 else if((hw->original_fc == em_fc_none ||
1941 hw->original_fc == em_fc_tx_pause) ||
1942 hw->fc_strict_ieee) {
1943 hw->fc = em_fc_none;
1944 DEBUGOUT("Flow Control = NONE.\r\n");
1945 } else {
1946 hw->fc = em_fc_rx_pause;
1947 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1948 }
1949
1950 /* Now we need to do one last check... If we auto-
1951 * negotiated to HALF DUPLEX, flow control should not be
1952 * enabled per IEEE 802.3 spec.
1953 */
1954 if((ret_val = em_get_speed_and_duplex(hw, &speed, &duplex))) {
1955 DEBUGOUT("Error getting link speed and duplex\n");
1956 return ret_val;
1957 }
1958
1959 if(duplex == HALF_DUPLEX)
1960 hw->fc = em_fc_none;
1961
1962 /* Now we call a subroutine to actually force the MAC
1963 * controller to use the correct flow control settings.
1964 */
1965 if((ret_val = em_force_mac_fc(hw))) {
1966 DEBUGOUT("Error forcing flow control settings\n");
1967 return ret_val;
1968 }
1969 } else {
1970 DEBUGOUT("Copper PHY and Auto Neg has not completed.\r\n");
1971 }
1972 }
1973 return E1000_SUCCESS;
1974 }
1975
1976 /******************************************************************************
1977 * Checks to see if the link status of the hardware has changed.
1978 *
1979 * hw - Struct containing variables accessed by shared code
1980 *
1981 * Called by any function that needs to check the link status of the adapter.
1982 *****************************************************************************/
1983 int32_t
em_check_for_link(struct em_hw * hw)1984 em_check_for_link(struct em_hw *hw)
1985 {
1986 uint32_t rxcw;
1987 uint32_t ctrl;
1988 uint32_t status;
1989 uint32_t rctl;
1990 uint32_t signal = 0;
1991 int32_t ret_val;
1992 uint16_t phy_data;
1993
1994 DEBUGFUNC("em_check_for_link");
1995
1996 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
1997 * set when the optics detect a signal. On older adapters, it will be
1998 * cleared when there is a signal. This applies to fiber media only.
1999 */
2000 if(hw->media_type == em_media_type_fiber)
2001 signal = (hw->mac_type > em_82544) ? E1000_CTRL_SWDPIN1 : 0;
2002
2003 ctrl = E1000_READ_REG(hw, CTRL);
2004 status = E1000_READ_REG(hw, STATUS);
2005 rxcw = E1000_READ_REG(hw, RXCW);
2006
2007 /* If we have a copper PHY then we only want to go out to the PHY
2008 * registers to see if Auto-Neg has completed and/or if our link
2009 * status has changed. The get_link_status flag will be set if we
2010 * receive a Link Status Change interrupt or we have Rx Sequence
2011 * Errors.
2012 */
2013 if((hw->media_type == em_media_type_copper) && hw->get_link_status) {
2014 /* First we want to see if the MII Status Register reports
2015 * link. If so, then we want to get the current speed/duplex
2016 * of the PHY.
2017 * Read the register twice since the link bit is sticky.
2018 */
2019 if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data)))
2020 return ret_val;
2021 if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data)))
2022 return ret_val;
2023
2024 if(phy_data & MII_SR_LINK_STATUS) {
2025 hw->get_link_status = FALSE;
2026 /* Check if there was DownShift, must be checked immediately after
2027 * link-up */
2028 em_check_downshift(hw);
2029
2030 } else {
2031 /* No link detected */
2032 em_config_dsp_after_link_change(hw, FALSE);
2033 return 0;
2034 }
2035
2036 /* If we are forcing speed/duplex, then we simply return since
2037 * we have already determined whether we have link or not.
2038 */
2039 if(!hw->autoneg) return -E1000_ERR_CONFIG;
2040
2041 /* optimize the dsp settings for the igp phy */
2042 em_config_dsp_after_link_change(hw, TRUE);
2043
2044 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
2045 * have Si on board that is 82544 or newer, Auto
2046 * Speed Detection takes care of MAC speed/duplex
2047 * configuration. So we only need to configure Collision
2048 * Distance in the MAC. Otherwise, we need to force
2049 * speed/duplex on the MAC to the current PHY speed/duplex
2050 * settings.
2051 */
2052 if(hw->mac_type >= em_82544)
2053 em_config_collision_dist(hw);
2054 else {
2055 if((ret_val = em_config_mac_to_phy(hw))) {
2056 DEBUGOUT("Error configuring MAC to PHY settings\n");
2057 return ret_val;
2058 }
2059 }
2060
2061 /* Configure Flow Control now that Auto-Neg has completed. First, we
2062 * need to restore the desired flow control settings because we may
2063 * have had to re-autoneg with a different link partner.
2064 */
2065 if((ret_val = em_config_fc_after_link_up(hw))) {
2066 DEBUGOUT("Error configuring flow control\n");
2067 return ret_val;
2068 }
2069
2070 /* At this point we know that we are on copper and we have
2071 * auto-negotiated link. These are conditions for checking the link
2072 * partner capability register. We use the link speed to determine if
2073 * TBI compatibility needs to be turned on or off. If the link is not
2074 * at gigabit speed, then TBI compatibility is not needed. If we are
2075 * at gigabit speed, we turn on TBI compatibility.
2076 */
2077 if(hw->tbi_compatibility_en) {
2078 uint16_t speed, duplex;
2079 em_get_speed_and_duplex(hw, &speed, &duplex);
2080 if(speed != SPEED_1000) {
2081 /* If link speed is not set to gigabit speed, we do not need
2082 * to enable TBI compatibility.
2083 */
2084 if(hw->tbi_compatibility_on) {
2085 /* If we previously were in the mode, turn it off. */
2086 rctl = E1000_READ_REG(hw, RCTL);
2087 rctl &= ~E1000_RCTL_SBP;
2088 E1000_WRITE_REG(hw, RCTL, rctl);
2089 hw->tbi_compatibility_on = FALSE;
2090 }
2091 } else {
2092 /* If TBI compatibility is was previously off, turn it on. For
2093 * compatibility with a TBI link partner, we will store bad
2094 * packets. Some frames have an additional byte on the end and
2095 * will look like CRC errors to to the hardware.
2096 */
2097 if(!hw->tbi_compatibility_on) {
2098 hw->tbi_compatibility_on = TRUE;
2099 rctl = E1000_READ_REG(hw, RCTL);
2100 rctl |= E1000_RCTL_SBP;
2101 E1000_WRITE_REG(hw, RCTL, rctl);
2102 }
2103 }
2104 }
2105 }
2106 /* If we don't have link (auto-negotiation failed or link partner cannot
2107 * auto-negotiate), the cable is plugged in (we have signal), and our
2108 * link partner is not trying to auto-negotiate with us (we are receiving
2109 * idles or data), we need to force link up. We also need to give
2110 * auto-negotiation time to complete, in case the cable was just plugged
2111 * in. The autoneg_failed flag does this.
2112 */
2113 else if((((hw->media_type == em_media_type_fiber) &&
2114 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
2115 (hw->media_type == em_media_type_internal_serdes)) &&
2116 (!(status & E1000_STATUS_LU)) &&
2117 (!(rxcw & E1000_RXCW_C))) {
2118 if(hw->autoneg_failed == 0) {
2119 hw->autoneg_failed = 1;
2120 return 0;
2121 }
2122 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
2123
2124 /* Disable auto-negotiation in the TXCW register */
2125 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
2126
2127 /* Force link-up and also force full-duplex. */
2128 ctrl = E1000_READ_REG(hw, CTRL);
2129 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
2130 E1000_WRITE_REG(hw, CTRL, ctrl);
2131
2132 /* Configure Flow Control after forcing link up. */
2133 if((ret_val = em_config_fc_after_link_up(hw))) {
2134 DEBUGOUT("Error configuring flow control\n");
2135 return ret_val;
2136 }
2137 }
2138 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
2139 * auto-negotiation in the TXCW register and disable forced link in the
2140 * Device Control register in an attempt to auto-negotiate with our link
2141 * partner.
2142 */
2143 else if(((hw->media_type == em_media_type_fiber) ||
2144 (hw->media_type == em_media_type_internal_serdes)) &&
2145 (ctrl & E1000_CTRL_SLU) &&
2146 (rxcw & E1000_RXCW_C)) {
2147 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
2148 E1000_WRITE_REG(hw, TXCW, hw->txcw);
2149 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
2150
2151 hw->serdes_link_down = FALSE;
2152 }
2153 /* If we force link for non-auto-negotiation switch, check link status
2154 * based on MAC synchronization for internal serdes media type.
2155 */
2156 else if((hw->media_type == em_media_type_internal_serdes) &&
2157 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
2158 /* SYNCH bit and IV bit are sticky. */
2159 usec_delay(10);
2160 if(E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
2161 if(!(rxcw & E1000_RXCW_IV)) {
2162 hw->serdes_link_down = FALSE;
2163 DEBUGOUT("SERDES: Link is up.\n");
2164 }
2165 } else {
2166 hw->serdes_link_down = TRUE;
2167 DEBUGOUT("SERDES: Link is down.\n");
2168 }
2169 }
2170 if((hw->media_type == em_media_type_internal_serdes) &&
2171 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
2172 hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS));
2173 }
2174 return E1000_SUCCESS;
2175 }
2176
2177 /******************************************************************************
2178 * Detects the current speed and duplex settings of the hardware.
2179 *
2180 * hw - Struct containing variables accessed by shared code
2181 * speed - Speed of the connection
2182 * duplex - Duplex setting of the connection
2183 *****************************************************************************/
2184 int32_t
em_get_speed_and_duplex(struct em_hw * hw,uint16_t * speed,uint16_t * duplex)2185 em_get_speed_and_duplex(struct em_hw *hw,
2186 uint16_t *speed,
2187 uint16_t *duplex)
2188 {
2189 uint32_t status;
2190 int32_t ret_val;
2191 uint16_t phy_data;
2192
2193 DEBUGFUNC("em_get_speed_and_duplex");
2194
2195 if(hw->mac_type >= em_82543) {
2196 status = E1000_READ_REG(hw, STATUS);
2197 if(status & E1000_STATUS_SPEED_1000) {
2198 *speed = SPEED_1000;
2199 DEBUGOUT("1000 Mbs, ");
2200 } else if(status & E1000_STATUS_SPEED_100) {
2201 *speed = SPEED_100;
2202 DEBUGOUT("100 Mbs, ");
2203 } else {
2204 *speed = SPEED_10;
2205 DEBUGOUT("10 Mbs, ");
2206 }
2207
2208 if(status & E1000_STATUS_FD) {
2209 *duplex = FULL_DUPLEX;
2210 DEBUGOUT("Full Duplex\r\n");
2211 } else {
2212 *duplex = HALF_DUPLEX;
2213 DEBUGOUT(" Half Duplex\r\n");
2214 }
2215 } else {
2216 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
2217 *speed = SPEED_1000;
2218 *duplex = FULL_DUPLEX;
2219 }
2220
2221 /* IGP01 PHY may advertise full duplex operation after speed downgrade even
2222 * if it is operating at half duplex. Here we set the duplex settings to
2223 * match the duplex in the link partner's capabilities.
2224 */
2225 if(hw->phy_type == em_phy_igp && hw->speed_downgraded) {
2226 if((ret_val = em_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data)))
2227 return ret_val;
2228
2229 if(!(phy_data & NWAY_ER_LP_NWAY_CAPS))
2230 *duplex = HALF_DUPLEX;
2231 else {
2232 if((ret_val == em_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data)))
2233 return ret_val;
2234 if((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
2235 (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
2236 *duplex = HALF_DUPLEX;
2237 }
2238 }
2239
2240 return E1000_SUCCESS;
2241 }
2242
2243 /******************************************************************************
2244 * Blocks until autoneg completes or times out (~4.5 seconds)
2245 *
2246 * hw - Struct containing variables accessed by shared code
2247 ******************************************************************************/
2248 int32_t
em_wait_autoneg(struct em_hw * hw)2249 em_wait_autoneg(struct em_hw *hw)
2250 {
2251 int32_t ret_val;
2252 uint16_t i;
2253 uint16_t phy_data;
2254
2255 DEBUGFUNC("em_wait_autoneg");
2256 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
2257
2258 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2259 for(i = PHY_AUTO_NEG_TIME; i > 0; i--) {
2260 /* Read the MII Status Register and wait for Auto-Neg
2261 * Complete bit to be set.
2262 */
2263 if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data)))
2264 return ret_val;
2265 if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data)))
2266 return ret_val;
2267 if(phy_data & MII_SR_AUTONEG_COMPLETE) {
2268 return E1000_SUCCESS;
2269 }
2270 msec_delay(100);
2271 }
2272 return E1000_SUCCESS;
2273 }
2274
2275 /******************************************************************************
2276 * Raises the Management Data Clock
2277 *
2278 * hw - Struct containing variables accessed by shared code
2279 * ctrl - Device control register's current value
2280 ******************************************************************************/
2281 static void
em_raise_mdi_clk(struct em_hw * hw,uint32_t * ctrl)2282 em_raise_mdi_clk(struct em_hw *hw,
2283 uint32_t *ctrl)
2284 {
2285 /* Raise the clock input to the Management Data Clock (by setting the MDC
2286 * bit), and then delay 10 microseconds.
2287 */
2288 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
2289 E1000_WRITE_FLUSH(hw);
2290 usec_delay(10);
2291 }
2292
2293 /******************************************************************************
2294 * Lowers the Management Data Clock
2295 *
2296 * hw - Struct containing variables accessed by shared code
2297 * ctrl - Device control register's current value
2298 ******************************************************************************/
2299 static void
em_lower_mdi_clk(struct em_hw * hw,uint32_t * ctrl)2300 em_lower_mdi_clk(struct em_hw *hw,
2301 uint32_t *ctrl)
2302 {
2303 /* Lower the clock input to the Management Data Clock (by clearing the MDC
2304 * bit), and then delay 10 microseconds.
2305 */
2306 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
2307 E1000_WRITE_FLUSH(hw);
2308 usec_delay(10);
2309 }
2310
2311 /******************************************************************************
2312 * Shifts data bits out to the PHY
2313 *
2314 * hw - Struct containing variables accessed by shared code
2315 * data - Data to send out to the PHY
2316 * count - Number of bits to shift out
2317 *
2318 * Bits are shifted out in MSB to LSB order.
2319 ******************************************************************************/
2320 static void
em_shift_out_mdi_bits(struct em_hw * hw,uint32_t data,uint16_t count)2321 em_shift_out_mdi_bits(struct em_hw *hw,
2322 uint32_t data,
2323 uint16_t count)
2324 {
2325 uint32_t ctrl;
2326 uint32_t mask;
2327
2328 /* We need to shift "count" number of bits out to the PHY. So, the value
2329 * in the "data" parameter will be shifted out to the PHY one bit at a
2330 * time. In order to do this, "data" must be broken down into bits.
2331 */
2332 mask = 0x01;
2333 mask <<= (count - 1);
2334
2335 ctrl = E1000_READ_REG(hw, CTRL);
2336
2337 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
2338 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
2339
2340 while(mask) {
2341 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
2342 * then raising and lowering the Management Data Clock. A "0" is
2343 * shifted out to the PHY by setting the MDIO bit to "0" and then
2344 * raising and lowering the clock.
2345 */
2346 if(data & mask) ctrl |= E1000_CTRL_MDIO;
2347 else ctrl &= ~E1000_CTRL_MDIO;
2348
2349 E1000_WRITE_REG(hw, CTRL, ctrl);
2350 E1000_WRITE_FLUSH(hw);
2351
2352 usec_delay(10);
2353
2354 em_raise_mdi_clk(hw, &ctrl);
2355 em_lower_mdi_clk(hw, &ctrl);
2356
2357 mask = mask >> 1;
2358 }
2359 }
2360
2361 /******************************************************************************
2362 * Shifts data bits in from the PHY
2363 *
2364 * hw - Struct containing variables accessed by shared code
2365 *
2366 * Bits are shifted in in MSB to LSB order.
2367 ******************************************************************************/
2368 static uint16_t
em_shift_in_mdi_bits(struct em_hw * hw)2369 em_shift_in_mdi_bits(struct em_hw *hw)
2370 {
2371 uint32_t ctrl;
2372 uint16_t data = 0;
2373 uint8_t i;
2374
2375 /* In order to read a register from the PHY, we need to shift in a total
2376 * of 18 bits from the PHY. The first two bit (turnaround) times are used
2377 * to avoid contention on the MDIO pin when a read operation is performed.
2378 * These two bits are ignored by us and thrown away. Bits are "shifted in"
2379 * by raising the input to the Management Data Clock (setting the MDC bit),
2380 * and then reading the value of the MDIO bit.
2381 */
2382 ctrl = E1000_READ_REG(hw, CTRL);
2383
2384 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
2385 ctrl &= ~E1000_CTRL_MDIO_DIR;
2386 ctrl &= ~E1000_CTRL_MDIO;
2387
2388 E1000_WRITE_REG(hw, CTRL, ctrl);
2389 E1000_WRITE_FLUSH(hw);
2390
2391 /* Raise and Lower the clock before reading in the data. This accounts for
2392 * the turnaround bits. The first clock occurred when we clocked out the
2393 * last bit of the Register Address.
2394 */
2395 em_raise_mdi_clk(hw, &ctrl);
2396 em_lower_mdi_clk(hw, &ctrl);
2397
2398 for(data = 0, i = 0; i < 16; i++) {
2399 data = data << 1;
2400 em_raise_mdi_clk(hw, &ctrl);
2401 ctrl = E1000_READ_REG(hw, CTRL);
2402 /* Check to see if we shifted in a "1". */
2403 if(ctrl & E1000_CTRL_MDIO) data |= 1;
2404 em_lower_mdi_clk(hw, &ctrl);
2405 }
2406
2407 em_raise_mdi_clk(hw, &ctrl);
2408 em_lower_mdi_clk(hw, &ctrl);
2409
2410 return data;
2411 }
2412
2413 /*****************************************************************************
2414 * Reads the value from a PHY register, if the value is on a specific non zero
2415 * page, sets the page first.
2416 * hw - Struct containing variables accessed by shared code
2417 * reg_addr - address of the PHY register to read
2418 ******************************************************************************/
2419 int32_t
em_read_phy_reg(struct em_hw * hw,uint32_t reg_addr,uint16_t * phy_data)2420 em_read_phy_reg(struct em_hw *hw,
2421 uint32_t reg_addr,
2422 uint16_t *phy_data)
2423 {
2424 uint32_t ret_val;
2425
2426 DEBUGFUNC("em_read_phy_reg");
2427
2428 if(hw->phy_type == em_phy_igp &&
2429 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2430 if((ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2431 (uint16_t)reg_addr)))
2432 return ret_val;
2433 }
2434
2435 ret_val = em_read_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT & reg_addr,
2436 phy_data);
2437
2438 return ret_val;
2439 }
2440
2441 int32_t
em_read_phy_reg_ex(struct em_hw * hw,uint32_t reg_addr,uint16_t * phy_data)2442 em_read_phy_reg_ex(struct em_hw *hw,
2443 uint32_t reg_addr,
2444 uint16_t *phy_data)
2445 {
2446 uint32_t i;
2447 uint32_t mdic = 0;
2448 const uint32_t phy_addr = 1;
2449
2450 DEBUGFUNC("em_read_phy_reg_ex");
2451
2452 if(reg_addr > MAX_PHY_REG_ADDRESS) {
2453 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
2454 return -E1000_ERR_PARAM;
2455 }
2456
2457 if(hw->mac_type > em_82543) {
2458 /* Set up Op-code, Phy Address, and register address in the MDI
2459 * Control register. The MAC will take care of interfacing with the
2460 * PHY to retrieve the desired data.
2461 */
2462 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
2463 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2464 (E1000_MDIC_OP_READ));
2465
2466 E1000_WRITE_REG(hw, MDIC, mdic);
2467
2468 /* Poll the ready bit to see if the MDI read completed */
2469 for(i = 0; i < 64; i++) {
2470 usec_delay(50);
2471 mdic = E1000_READ_REG(hw, MDIC);
2472 if(mdic & E1000_MDIC_READY) break;
2473 }
2474 if(!(mdic & E1000_MDIC_READY)) {
2475 DEBUGOUT("MDI Read did not complete\n");
2476 return -E1000_ERR_PHY;
2477 }
2478 if(mdic & E1000_MDIC_ERROR) {
2479 DEBUGOUT("MDI Error\n");
2480 return -E1000_ERR_PHY;
2481 }
2482 *phy_data = (uint16_t) mdic;
2483 } else {
2484 /* We must first send a preamble through the MDIO pin to signal the
2485 * beginning of an MII instruction. This is done by sending 32
2486 * consecutive "1" bits.
2487 */
2488 em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2489
2490 /* Now combine the next few fields that are required for a read
2491 * operation. We use this method instead of calling the
2492 * em_shift_out_mdi_bits routine five different times. The format of
2493 * a MII read instruction consists of a shift out of 14 bits and is
2494 * defined as follows:
2495 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
2496 * followed by a shift in of 18 bits. This first two bits shifted in
2497 * are TurnAround bits used to avoid contention on the MDIO pin when a
2498 * READ operation is performed. These two bits are thrown away
2499 * followed by a shift in of 16 bits which contains the desired data.
2500 */
2501 mdic = ((reg_addr) | (phy_addr << 5) |
2502 (PHY_OP_READ << 10) | (PHY_SOF << 12));
2503
2504 em_shift_out_mdi_bits(hw, mdic, 14);
2505
2506 /* Now that we've shifted out the read command to the MII, we need to
2507 * "shift in" the 16-bit value (18 total bits) of the requested PHY
2508 * register address.
2509 */
2510 *phy_data = em_shift_in_mdi_bits(hw);
2511 }
2512 return E1000_SUCCESS;
2513 }
2514
2515 /******************************************************************************
2516 * Writes a value to a PHY register
2517 *
2518 * hw - Struct containing variables accessed by shared code
2519 * reg_addr - address of the PHY register to write
2520 * data - data to write to the PHY
2521 ******************************************************************************/
2522 int32_t
em_write_phy_reg(struct em_hw * hw,uint32_t reg_addr,uint16_t phy_data)2523 em_write_phy_reg(struct em_hw *hw,
2524 uint32_t reg_addr,
2525 uint16_t phy_data)
2526 {
2527 uint32_t ret_val;
2528
2529 DEBUGFUNC("em_write_phy_reg");
2530
2531 if(hw->phy_type == em_phy_igp &&
2532 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2533 if((ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2534 (uint16_t)reg_addr)))
2535 return ret_val;
2536 }
2537
2538 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT & reg_addr,
2539 phy_data);
2540
2541 return ret_val;
2542 }
2543
2544 int32_t
em_write_phy_reg_ex(struct em_hw * hw,uint32_t reg_addr,uint16_t phy_data)2545 em_write_phy_reg_ex(struct em_hw *hw,
2546 uint32_t reg_addr,
2547 uint16_t phy_data)
2548 {
2549 uint32_t i;
2550 uint32_t mdic = 0;
2551 const uint32_t phy_addr = 1;
2552
2553 DEBUGFUNC("em_write_phy_reg_ex");
2554
2555 if(reg_addr > MAX_PHY_REG_ADDRESS) {
2556 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
2557 return -E1000_ERR_PARAM;
2558 }
2559
2560 if(hw->mac_type > em_82543) {
2561 /* Set up Op-code, Phy Address, register address, and data intended
2562 * for the PHY register in the MDI Control register. The MAC will take
2563 * care of interfacing with the PHY to send the desired data.
2564 */
2565 mdic = (((uint32_t) phy_data) |
2566 (reg_addr << E1000_MDIC_REG_SHIFT) |
2567 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2568 (E1000_MDIC_OP_WRITE));
2569
2570 E1000_WRITE_REG(hw, MDIC, mdic);
2571
2572 /* Poll the ready bit to see if the MDI read completed */
2573 for(i = 0; i < 640; i++) {
2574 usec_delay(5);
2575 mdic = E1000_READ_REG(hw, MDIC);
2576 if(mdic & E1000_MDIC_READY) break;
2577 }
2578 if(!(mdic & E1000_MDIC_READY)) {
2579 DEBUGOUT("MDI Write did not complete\n");
2580 return -E1000_ERR_PHY;
2581 }
2582 } else {
2583 /* We'll need to use the SW defined pins to shift the write command
2584 * out to the PHY. We first send a preamble to the PHY to signal the
2585 * beginning of the MII instruction. This is done by sending 32
2586 * consecutive "1" bits.
2587 */
2588 em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2589
2590 /* Now combine the remaining required fields that will indicate a
2591 * write operation. We use this method instead of calling the
2592 * em_shift_out_mdi_bits routine for each field in the command. The
2593 * format of a MII write instruction is as follows:
2594 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
2595 */
2596 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
2597 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
2598 mdic <<= 16;
2599 mdic |= (uint32_t) phy_data;
2600
2601 em_shift_out_mdi_bits(hw, mdic, 32);
2602 }
2603
2604 return E1000_SUCCESS;
2605 }
2606
2607 /******************************************************************************
2608 * Returns the PHY to the power-on reset state
2609 *
2610 * hw - Struct containing variables accessed by shared code
2611 ******************************************************************************/
2612 void
em_phy_hw_reset(struct em_hw * hw)2613 em_phy_hw_reset(struct em_hw *hw)
2614 {
2615 uint32_t ctrl, ctrl_ext;
2616 uint32_t led_ctrl;
2617
2618 DEBUGFUNC("em_phy_hw_reset");
2619
2620 DEBUGOUT("Resetting Phy...\n");
2621
2622 if(hw->mac_type > em_82543) {
2623 /* Read the device control register and assert the E1000_CTRL_PHY_RST
2624 * bit. Then, take it out of reset.
2625 */
2626 ctrl = E1000_READ_REG(hw, CTRL);
2627 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
2628 E1000_WRITE_FLUSH(hw);
2629 msec_delay(10);
2630 E1000_WRITE_REG(hw, CTRL, ctrl);
2631 E1000_WRITE_FLUSH(hw);
2632 } else {
2633 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
2634 * bit to put the PHY into reset. Then, take it out of reset.
2635 */
2636 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
2637 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
2638 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
2639 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2640 E1000_WRITE_FLUSH(hw);
2641 msec_delay(10);
2642 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
2643 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2644 E1000_WRITE_FLUSH(hw);
2645 }
2646 usec_delay(150);
2647
2648 if((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
2649 /* Configure activity LED after PHY reset */
2650 led_ctrl = E1000_READ_REG(hw, LEDCTL);
2651 led_ctrl &= IGP_ACTIVITY_LED_MASK;
2652 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2653 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
2654 }
2655 }
2656
2657 /******************************************************************************
2658 * Resets the PHY
2659 *
2660 * hw - Struct containing variables accessed by shared code
2661 *
2662 * Sets bit 15 of the MII Control regiser
2663 ******************************************************************************/
2664 int32_t
em_phy_reset(struct em_hw * hw)2665 em_phy_reset(struct em_hw *hw)
2666 {
2667 int32_t ret_val;
2668 uint16_t phy_data;
2669
2670 DEBUGFUNC("em_phy_reset");
2671
2672 if(hw->mac_type != em_82541_rev_2) {
2673 if((ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data)))
2674 return ret_val;
2675
2676 phy_data |= MII_CR_RESET;
2677 if((ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data)))
2678 return ret_val;
2679
2680 usec_delay(1);
2681 } else em_phy_hw_reset(hw);
2682
2683 if(hw->phy_type == em_phy_igp)
2684 em_phy_init_script(hw);
2685
2686 return E1000_SUCCESS;
2687 }
2688
2689 /******************************************************************************
2690 * Probes the expected PHY address for known PHY IDs
2691 *
2692 * hw - Struct containing variables accessed by shared code
2693 ******************************************************************************/
2694 int32_t
em_detect_gig_phy(struct em_hw * hw)2695 em_detect_gig_phy(struct em_hw *hw)
2696 {
2697 int32_t phy_init_status, ret_val;
2698 uint16_t phy_id_high, phy_id_low;
2699 boolean_t match = FALSE;
2700
2701 DEBUGFUNC("em_detect_gig_phy");
2702
2703 /* Read the PHY ID Registers to identify which PHY is onboard. */
2704 if((ret_val = em_read_phy_reg(hw, PHY_ID1, &phy_id_high)))
2705 return ret_val;
2706
2707 hw->phy_id = (uint32_t) (phy_id_high << 16);
2708 usec_delay(20);
2709 if((ret_val = em_read_phy_reg(hw, PHY_ID2, &phy_id_low)))
2710 return ret_val;
2711
2712 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
2713 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
2714
2715 switch(hw->mac_type) {
2716 case em_82543:
2717 if(hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
2718 break;
2719 case em_82544:
2720 if(hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
2721 break;
2722 case em_82540:
2723 case em_82545:
2724 case em_82545_rev_3:
2725 case em_82546:
2726 case em_82546_rev_3:
2727 if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
2728 break;
2729 case em_82541:
2730 case em_82541_rev_2:
2731 case em_82547:
2732 case em_82547_rev_2:
2733 if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
2734 break;
2735 default:
2736 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
2737 return -E1000_ERR_CONFIG;
2738 }
2739 phy_init_status = em_set_phy_type(hw);
2740
2741 if ((match) && (phy_init_status == E1000_SUCCESS)) {
2742 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
2743 return E1000_SUCCESS;
2744 }
2745 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
2746 return -E1000_ERR_PHY;
2747 }
2748
2749 /******************************************************************************
2750 * Resets the PHY's DSP
2751 *
2752 * hw - Struct containing variables accessed by shared code
2753 ******************************************************************************/
2754 static int32_t
em_phy_reset_dsp(struct em_hw * hw)2755 em_phy_reset_dsp(struct em_hw *hw)
2756 {
2757 int32_t ret_val;
2758 DEBUGFUNC("em_phy_reset_dsp");
2759
2760 do {
2761 if((ret_val = em_write_phy_reg(hw, 29, 0x001d))) break;
2762 if((ret_val = em_write_phy_reg(hw, 30, 0x00c1))) break;
2763 if((ret_val = em_write_phy_reg(hw, 30, 0x0000))) break;
2764 ret_val = E1000_SUCCESS;
2765 } while(0);
2766
2767 return ret_val;
2768 }
2769
2770 /******************************************************************************
2771 * Get PHY information from various PHY registers for igp PHY only.
2772 *
2773 * hw - Struct containing variables accessed by shared code
2774 * phy_info - PHY information structure
2775 ******************************************************************************/
2776 int32_t
em_phy_igp_get_info(struct em_hw * hw,struct em_phy_info * phy_info)2777 em_phy_igp_get_info(struct em_hw *hw,
2778 struct em_phy_info *phy_info)
2779 {
2780 int32_t ret_val;
2781 uint16_t phy_data, polarity, min_length, max_length, average;
2782
2783 DEBUGFUNC("em_phy_igp_get_info");
2784
2785 /* The downshift status is checked only once, after link is established,
2786 * and it stored in the hw->speed_downgraded parameter. */
2787 phy_info->downshift = hw->speed_downgraded;
2788
2789 /* IGP01E1000 does not need to support it. */
2790 phy_info->extended_10bt_distance = em_10bt_ext_dist_enable_normal;
2791
2792 /* IGP01E1000 always correct polarity reversal */
2793 phy_info->polarity_correction = em_polarity_reversal_enabled;
2794
2795 /* Check polarity status */
2796 if((ret_val = em_check_polarity(hw, &polarity)))
2797 return ret_val;
2798
2799 phy_info->cable_polarity = polarity;
2800
2801 if((ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
2802 &phy_data)))
2803 return ret_val;
2804
2805 phy_info->mdix_mode = (phy_data & IGP01E1000_PSSR_MDIX) >>
2806 IGP01E1000_PSSR_MDIX_SHIFT;
2807
2808 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
2809 IGP01E1000_PSSR_SPEED_1000MBPS) {
2810 /* Local/Remote Receiver Information are only valid at 1000 Mbps */
2811 if((ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data)))
2812 return ret_val;
2813
2814 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
2815 SR_1000T_LOCAL_RX_STATUS_SHIFT;
2816 phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
2817 SR_1000T_REMOTE_RX_STATUS_SHIFT;
2818
2819 /* Get cable length */
2820 if((ret_val = em_get_cable_length(hw, &min_length, &max_length)))
2821 return ret_val;
2822
2823 /* transalte to old method */
2824 average = (max_length + min_length) / 2;
2825
2826 if(average <= em_igp_cable_length_50)
2827 phy_info->cable_length = em_cable_length_50;
2828 else if(average <= em_igp_cable_length_80)
2829 phy_info->cable_length = em_cable_length_50_80;
2830 else if(average <= em_igp_cable_length_110)
2831 phy_info->cable_length = em_cable_length_80_110;
2832 else if(average <= em_igp_cable_length_140)
2833 phy_info->cable_length = em_cable_length_110_140;
2834 else
2835 phy_info->cable_length = em_cable_length_140;
2836 }
2837
2838 return E1000_SUCCESS;
2839 }
2840
2841 /******************************************************************************
2842 * Get PHY information from various PHY registers fot m88 PHY only.
2843 *
2844 * hw - Struct containing variables accessed by shared code
2845 * phy_info - PHY information structure
2846 ******************************************************************************/
2847 int32_t
em_phy_m88_get_info(struct em_hw * hw,struct em_phy_info * phy_info)2848 em_phy_m88_get_info(struct em_hw *hw,
2849 struct em_phy_info *phy_info)
2850 {
2851 int32_t ret_val;
2852 uint16_t phy_data, polarity;
2853
2854 DEBUGFUNC("em_phy_m88_get_info");
2855
2856 /* The downshift status is checked only once, after link is established,
2857 * and it stored in the hw->speed_downgraded parameter. */
2858 phy_info->downshift = hw->speed_downgraded;
2859
2860 if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data)))
2861 return ret_val;
2862
2863 phy_info->extended_10bt_distance =
2864 (phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
2865 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT;
2866 phy_info->polarity_correction =
2867 (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
2868 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT;
2869
2870 /* Check polarity status */
2871 if((ret_val = em_check_polarity(hw, &polarity)))
2872 return ret_val;
2873
2874 phy_info->cable_polarity = polarity;
2875
2876 if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data)))
2877 return ret_val;
2878
2879 phy_info->mdix_mode = (phy_data & M88E1000_PSSR_MDIX) >>
2880 M88E1000_PSSR_MDIX_SHIFT;
2881
2882 if(phy_data & M88E1000_PSSR_1000MBS) {
2883 /* Cable Length Estimation and Local/Remote Receiver Informatoion
2884 * are only valid at 1000 Mbps
2885 */
2886 phy_info->cable_length = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2887 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
2888
2889 if((ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data)))
2890 return ret_val;
2891
2892 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
2893 SR_1000T_LOCAL_RX_STATUS_SHIFT;
2894
2895 phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
2896 SR_1000T_REMOTE_RX_STATUS_SHIFT;
2897 }
2898
2899 return E1000_SUCCESS;
2900 }
2901
2902 /******************************************************************************
2903 * Get PHY information from various PHY registers
2904 *
2905 * hw - Struct containing variables accessed by shared code
2906 * phy_info - PHY information structure
2907 ******************************************************************************/
2908 int32_t
em_phy_get_info(struct em_hw * hw,struct em_phy_info * phy_info)2909 em_phy_get_info(struct em_hw *hw,
2910 struct em_phy_info *phy_info)
2911 {
2912 int32_t ret_val;
2913 uint16_t phy_data;
2914
2915 DEBUGFUNC("em_phy_get_info");
2916
2917 phy_info->cable_length = em_cable_length_undefined;
2918 phy_info->extended_10bt_distance = em_10bt_ext_dist_enable_undefined;
2919 phy_info->cable_polarity = em_rev_polarity_undefined;
2920 phy_info->downshift = em_downshift_undefined;
2921 phy_info->polarity_correction = em_polarity_reversal_undefined;
2922 phy_info->mdix_mode = em_auto_x_mode_undefined;
2923 phy_info->local_rx = em_1000t_rx_status_undefined;
2924 phy_info->remote_rx = em_1000t_rx_status_undefined;
2925
2926 if(hw->media_type != em_media_type_copper) {
2927 DEBUGOUT("PHY info is only valid for copper media\n");
2928 return -E1000_ERR_CONFIG;
2929 }
2930
2931 if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data)))
2932 return ret_val;
2933
2934 if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data)))
2935 return ret_val;
2936
2937 if((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
2938 DEBUGOUT("PHY info is only valid if link is up\n");
2939 return -E1000_ERR_CONFIG;
2940 }
2941
2942 if(hw->phy_type == em_phy_igp)
2943 return em_phy_igp_get_info(hw, phy_info);
2944 else
2945 return em_phy_m88_get_info(hw, phy_info);
2946 }
2947
2948 int32_t
em_validate_mdi_setting(struct em_hw * hw)2949 em_validate_mdi_setting(struct em_hw *hw)
2950 {
2951 DEBUGFUNC("em_validate_mdi_settings");
2952
2953 if(!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
2954 DEBUGOUT("Invalid MDI setting detected\n");
2955 hw->mdix = 1;
2956 return -E1000_ERR_CONFIG;
2957 }
2958 return E1000_SUCCESS;
2959 }
2960
2961
2962 /******************************************************************************
2963 * Sets up eeprom variables in the hw struct. Must be called after mac_type
2964 * is configured.
2965 *
2966 * hw - Struct containing variables accessed by shared code
2967 *****************************************************************************/
2968 void
em_init_eeprom_params(struct em_hw * hw)2969 em_init_eeprom_params(struct em_hw *hw)
2970 {
2971 struct em_eeprom_info *eeprom = &hw->eeprom;
2972 uint32_t eecd = E1000_READ_REG(hw, EECD);
2973 uint16_t eeprom_size;
2974
2975 DEBUGFUNC("em_init_eeprom_params");
2976
2977 switch (hw->mac_type) {
2978 case em_82542_rev2_0:
2979 case em_82542_rev2_1:
2980 case em_82543:
2981 case em_82544:
2982 eeprom->type = em_eeprom_microwire;
2983 eeprom->word_size = 64;
2984 eeprom->opcode_bits = 3;
2985 eeprom->address_bits = 6;
2986 eeprom->delay_usec = 50;
2987 break;
2988 case em_82540:
2989 case em_82545:
2990 case em_82545_rev_3:
2991 case em_82546:
2992 case em_82546_rev_3:
2993 eeprom->type = em_eeprom_microwire;
2994 eeprom->opcode_bits = 3;
2995 eeprom->delay_usec = 50;
2996 if(eecd & E1000_EECD_SIZE) {
2997 eeprom->word_size = 256;
2998 eeprom->address_bits = 8;
2999 } else {
3000 eeprom->word_size = 64;
3001 eeprom->address_bits = 6;
3002 }
3003 break;
3004 case em_82541:
3005 case em_82541_rev_2:
3006 case em_82547:
3007 case em_82547_rev_2:
3008 if (eecd & E1000_EECD_TYPE) {
3009 eeprom->type = em_eeprom_spi;
3010 eeprom->opcode_bits = 8;
3011 eeprom->delay_usec = 1;
3012 if (eecd & E1000_EECD_ADDR_BITS) {
3013 eeprom->page_size = 32;
3014 eeprom->address_bits = 16;
3015 } else {
3016 eeprom->page_size = 8;
3017 eeprom->address_bits = 8;
3018 }
3019 } else {
3020 eeprom->type = em_eeprom_microwire;
3021 eeprom->opcode_bits = 3;
3022 eeprom->delay_usec = 50;
3023 if (eecd & E1000_EECD_ADDR_BITS) {
3024 eeprom->word_size = 256;
3025 eeprom->address_bits = 8;
3026 } else {
3027 eeprom->word_size = 64;
3028 eeprom->address_bits = 6;
3029 }
3030 }
3031 break;
3032 default:
3033 eeprom->type = em_eeprom_spi;
3034 eeprom->opcode_bits = 8;
3035 eeprom->delay_usec = 1;
3036 if (eecd & E1000_EECD_ADDR_BITS) {
3037 eeprom->page_size = 32;
3038 eeprom->address_bits = 16;
3039 } else {
3040 eeprom->page_size = 8;
3041 eeprom->address_bits = 8;
3042 }
3043 break;
3044 }
3045
3046 if (eeprom->type == em_eeprom_spi) {
3047 eeprom->word_size = 64;
3048 if (em_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size) == 0) {
3049 eeprom_size &= EEPROM_SIZE_MASK;
3050
3051 switch (eeprom_size) {
3052 case EEPROM_SIZE_16KB:
3053 eeprom->word_size = 8192;
3054 break;
3055 case EEPROM_SIZE_8KB:
3056 eeprom->word_size = 4096;
3057 break;
3058 case EEPROM_SIZE_4KB:
3059 eeprom->word_size = 2048;
3060 break;
3061 case EEPROM_SIZE_2KB:
3062 eeprom->word_size = 1024;
3063 break;
3064 case EEPROM_SIZE_1KB:
3065 eeprom->word_size = 512;
3066 break;
3067 case EEPROM_SIZE_512B:
3068 eeprom->word_size = 256;
3069 break;
3070 case EEPROM_SIZE_128B:
3071 default:
3072 eeprom->word_size = 64;
3073 break;
3074 }
3075 }
3076 }
3077 }
3078
3079 /******************************************************************************
3080 * Raises the EEPROM's clock input.
3081 *
3082 * hw - Struct containing variables accessed by shared code
3083 * eecd - EECD's current value
3084 *****************************************************************************/
3085 static void
em_raise_ee_clk(struct em_hw * hw,uint32_t * eecd)3086 em_raise_ee_clk(struct em_hw *hw,
3087 uint32_t *eecd)
3088 {
3089 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
3090 * wait <delay> microseconds.
3091 */
3092 *eecd = *eecd | E1000_EECD_SK;
3093 E1000_WRITE_REG(hw, EECD, *eecd);
3094 E1000_WRITE_FLUSH(hw);
3095 usec_delay(hw->eeprom.delay_usec);
3096 }
3097
3098 /******************************************************************************
3099 * Lowers the EEPROM's clock input.
3100 *
3101 * hw - Struct containing variables accessed by shared code
3102 * eecd - EECD's current value
3103 *****************************************************************************/
3104 static void
em_lower_ee_clk(struct em_hw * hw,uint32_t * eecd)3105 em_lower_ee_clk(struct em_hw *hw,
3106 uint32_t *eecd)
3107 {
3108 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
3109 * wait 50 microseconds.
3110 */
3111 *eecd = *eecd & ~E1000_EECD_SK;
3112 E1000_WRITE_REG(hw, EECD, *eecd);
3113 E1000_WRITE_FLUSH(hw);
3114 usec_delay(hw->eeprom.delay_usec);
3115 }
3116
3117 /******************************************************************************
3118 * Shift data bits out to the EEPROM.
3119 *
3120 * hw - Struct containing variables accessed by shared code
3121 * data - data to send to the EEPROM
3122 * count - number of bits to shift out
3123 *****************************************************************************/
3124 static void
em_shift_out_ee_bits(struct em_hw * hw,uint16_t data,uint16_t count)3125 em_shift_out_ee_bits(struct em_hw *hw,
3126 uint16_t data,
3127 uint16_t count)
3128 {
3129 struct em_eeprom_info *eeprom = &hw->eeprom;
3130 uint32_t eecd;
3131 uint32_t mask;
3132
3133 /* We need to shift "count" bits out to the EEPROM. So, value in the
3134 * "data" parameter will be shifted out to the EEPROM one bit at a time.
3135 * In order to do this, "data" must be broken down into bits.
3136 */
3137 mask = 0x01 << (count - 1);
3138 eecd = E1000_READ_REG(hw, EECD);
3139 if (eeprom->type == em_eeprom_microwire) {
3140 eecd &= ~E1000_EECD_DO;
3141 } else if (eeprom->type == em_eeprom_spi) {
3142 eecd |= E1000_EECD_DO;
3143 }
3144 do {
3145 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
3146 * and then raising and then lowering the clock (the SK bit controls
3147 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
3148 * by setting "DI" to "0" and then raising and then lowering the clock.
3149 */
3150 eecd &= ~E1000_EECD_DI;
3151
3152 if(data & mask)
3153 eecd |= E1000_EECD_DI;
3154
3155 E1000_WRITE_REG(hw, EECD, eecd);
3156 E1000_WRITE_FLUSH(hw);
3157
3158 usec_delay(eeprom->delay_usec);
3159
3160 em_raise_ee_clk(hw, &eecd);
3161 em_lower_ee_clk(hw, &eecd);
3162
3163 mask = mask >> 1;
3164
3165 } while(mask);
3166
3167 /* We leave the "DI" bit set to "0" when we leave this routine. */
3168 eecd &= ~E1000_EECD_DI;
3169 E1000_WRITE_REG(hw, EECD, eecd);
3170 }
3171
3172 /******************************************************************************
3173 * Shift data bits in from the EEPROM
3174 *
3175 * hw - Struct containing variables accessed by shared code
3176 *****************************************************************************/
3177 static uint16_t
em_shift_in_ee_bits(struct em_hw * hw,uint16_t count)3178 em_shift_in_ee_bits(struct em_hw *hw,
3179 uint16_t count)
3180 {
3181 uint32_t eecd;
3182 uint32_t i;
3183 uint16_t data;
3184
3185 /* In order to read a register from the EEPROM, we need to shift 'count'
3186 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
3187 * input to the EEPROM (setting the SK bit), and then reading the value of
3188 * the "DO" bit. During this "shifting in" process the "DI" bit should
3189 * always be clear.
3190 */
3191
3192 eecd = E1000_READ_REG(hw, EECD);
3193
3194 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
3195 data = 0;
3196
3197 for(i = 0; i < count; i++) {
3198 data = data << 1;
3199 em_raise_ee_clk(hw, &eecd);
3200
3201 eecd = E1000_READ_REG(hw, EECD);
3202
3203 eecd &= ~(E1000_EECD_DI);
3204 if(eecd & E1000_EECD_DO)
3205 data |= 1;
3206
3207 em_lower_ee_clk(hw, &eecd);
3208 }
3209
3210 return data;
3211 }
3212
3213 /******************************************************************************
3214 * Prepares EEPROM for access
3215 *
3216 * hw - Struct containing variables accessed by shared code
3217 *
3218 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
3219 * function should be called before issuing a command to the EEPROM.
3220 *****************************************************************************/
3221 static int32_t
em_acquire_eeprom(struct em_hw * hw)3222 em_acquire_eeprom(struct em_hw *hw)
3223 {
3224 struct em_eeprom_info *eeprom = &hw->eeprom;
3225 uint32_t eecd, i=0;
3226
3227 DEBUGFUNC("em_acquire_eeprom");
3228
3229 eecd = E1000_READ_REG(hw, EECD);
3230
3231 /* Request EEPROM Access */
3232 if(hw->mac_type > em_82544) {
3233 eecd |= E1000_EECD_REQ;
3234 E1000_WRITE_REG(hw, EECD, eecd);
3235 eecd = E1000_READ_REG(hw, EECD);
3236 while((!(eecd & E1000_EECD_GNT)) &&
3237 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
3238 i++;
3239 usec_delay(5);
3240 eecd = E1000_READ_REG(hw, EECD);
3241 }
3242 if(!(eecd & E1000_EECD_GNT)) {
3243 eecd &= ~E1000_EECD_REQ;
3244 E1000_WRITE_REG(hw, EECD, eecd);
3245 DEBUGOUT("Could not acquire EEPROM grant\n");
3246 return -E1000_ERR_EEPROM;
3247 }
3248 }
3249
3250 /* Setup EEPROM for Read/Write */
3251
3252 if (eeprom->type == em_eeprom_microwire) {
3253 /* Clear SK and DI */
3254 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
3255 E1000_WRITE_REG(hw, EECD, eecd);
3256
3257 /* Set CS */
3258 eecd |= E1000_EECD_CS;
3259 E1000_WRITE_REG(hw, EECD, eecd);
3260 } else if (eeprom->type == em_eeprom_spi) {
3261 /* Clear SK and CS */
3262 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3263 E1000_WRITE_REG(hw, EECD, eecd);
3264 usec_delay(1);
3265 }
3266
3267 return E1000_SUCCESS;
3268 }
3269
3270 /******************************************************************************
3271 * Returns EEPROM to a "standby" state
3272 *
3273 * hw - Struct containing variables accessed by shared code
3274 *****************************************************************************/
3275 static void
em_standby_eeprom(struct em_hw * hw)3276 em_standby_eeprom(struct em_hw *hw)
3277 {
3278 struct em_eeprom_info *eeprom = &hw->eeprom;
3279 uint32_t eecd;
3280
3281 eecd = E1000_READ_REG(hw, EECD);
3282
3283 if(eeprom->type == em_eeprom_microwire) {
3284 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3285 E1000_WRITE_REG(hw, EECD, eecd);
3286 E1000_WRITE_FLUSH(hw);
3287 usec_delay(eeprom->delay_usec);
3288
3289 /* Clock high */
3290 eecd |= E1000_EECD_SK;
3291 E1000_WRITE_REG(hw, EECD, eecd);
3292 E1000_WRITE_FLUSH(hw);
3293 usec_delay(eeprom->delay_usec);
3294
3295 /* Select EEPROM */
3296 eecd |= E1000_EECD_CS;
3297 E1000_WRITE_REG(hw, EECD, eecd);
3298 E1000_WRITE_FLUSH(hw);
3299 usec_delay(eeprom->delay_usec);
3300
3301 /* Clock low */
3302 eecd &= ~E1000_EECD_SK;
3303 E1000_WRITE_REG(hw, EECD, eecd);
3304 E1000_WRITE_FLUSH(hw);
3305 usec_delay(eeprom->delay_usec);
3306 } else if(eeprom->type == em_eeprom_spi) {
3307 /* Toggle CS to flush commands */
3308 eecd |= E1000_EECD_CS;
3309 E1000_WRITE_REG(hw, EECD, eecd);
3310 E1000_WRITE_FLUSH(hw);
3311 usec_delay(eeprom->delay_usec);
3312 eecd &= ~E1000_EECD_CS;
3313 E1000_WRITE_REG(hw, EECD, eecd);
3314 E1000_WRITE_FLUSH(hw);
3315 usec_delay(eeprom->delay_usec);
3316 }
3317 }
3318
3319 /******************************************************************************
3320 * Terminates a command by inverting the EEPROM's chip select pin
3321 *
3322 * hw - Struct containing variables accessed by shared code
3323 *****************************************************************************/
3324 static void
em_release_eeprom(struct em_hw * hw)3325 em_release_eeprom(struct em_hw *hw)
3326 {
3327 uint32_t eecd;
3328
3329 DEBUGFUNC("em_release_eeprom");
3330
3331 eecd = E1000_READ_REG(hw, EECD);
3332
3333 if (hw->eeprom.type == em_eeprom_spi) {
3334 eecd |= E1000_EECD_CS; /* Pull CS high */
3335 eecd &= ~E1000_EECD_SK; /* Lower SCK */
3336
3337 E1000_WRITE_REG(hw, EECD, eecd);
3338
3339 usec_delay(hw->eeprom.delay_usec);
3340 } else if(hw->eeprom.type == em_eeprom_microwire) {
3341 /* cleanup eeprom */
3342
3343 /* CS on Microwire is active-high */
3344 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
3345
3346 E1000_WRITE_REG(hw, EECD, eecd);
3347
3348 /* Rising edge of clock */
3349 eecd |= E1000_EECD_SK;
3350 E1000_WRITE_REG(hw, EECD, eecd);
3351 E1000_WRITE_FLUSH(hw);
3352 usec_delay(hw->eeprom.delay_usec);
3353
3354 /* Falling edge of clock */
3355 eecd &= ~E1000_EECD_SK;
3356 E1000_WRITE_REG(hw, EECD, eecd);
3357 E1000_WRITE_FLUSH(hw);
3358 usec_delay(hw->eeprom.delay_usec);
3359 }
3360
3361 /* Stop requesting EEPROM access */
3362 if(hw->mac_type > em_82544) {
3363 eecd &= ~E1000_EECD_REQ;
3364 E1000_WRITE_REG(hw, EECD, eecd);
3365 }
3366 }
3367
3368 /******************************************************************************
3369 * Reads a 16 bit word from the EEPROM.
3370 *
3371 * hw - Struct containing variables accessed by shared code
3372 *****************************************************************************/
3373 int32_t
em_spi_eeprom_ready(struct em_hw * hw)3374 em_spi_eeprom_ready(struct em_hw *hw)
3375 {
3376 uint16_t retry_count = 0;
3377 uint8_t spi_stat_reg;
3378
3379 DEBUGFUNC("em_spi_eeprom_ready");
3380
3381 /* Read "Status Register" repeatedly until the LSB is cleared. The
3382 * EEPROM will signal that the command has been completed by clearing
3383 * bit 0 of the internal status register. If it's not cleared within
3384 * 5 milliseconds, then error out.
3385 */
3386 retry_count = 0;
3387 do {
3388 em_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
3389 hw->eeprom.opcode_bits);
3390 spi_stat_reg = (uint8_t)em_shift_in_ee_bits(hw, 8);
3391 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
3392 break;
3393
3394 usec_delay(5);
3395 retry_count += 5;
3396
3397 } while(retry_count < EEPROM_MAX_RETRY_SPI);
3398
3399 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
3400 * only 0-5mSec on 5V devices)
3401 */
3402 if(retry_count >= EEPROM_MAX_RETRY_SPI) {
3403 DEBUGOUT("SPI EEPROM Status error\n");
3404 return -E1000_ERR_EEPROM;
3405 }
3406
3407 return E1000_SUCCESS;
3408 }
3409
3410 /******************************************************************************
3411 * Reads a 16 bit word from the EEPROM.
3412 *
3413 * hw - Struct containing variables accessed by shared code
3414 * offset - offset of word in the EEPROM to read
3415 * data - word read from the EEPROM
3416 * words - number of words to read
3417 *****************************************************************************/
3418 int32_t
em_read_eeprom(struct em_hw * hw,uint16_t offset,uint16_t words,uint16_t * data)3419 em_read_eeprom(struct em_hw *hw,
3420 uint16_t offset,
3421 uint16_t words,
3422 uint16_t *data)
3423 {
3424 struct em_eeprom_info *eeprom = &hw->eeprom;
3425 uint32_t i = 0;
3426
3427 DEBUGFUNC("em_read_eeprom");
3428
3429 /* A check for invalid values: offset too large, too many words, and not
3430 * enough words.
3431 */
3432 if((offset > eeprom->word_size) || (words > eeprom->word_size - offset) ||
3433 (words == 0)) {
3434 DEBUGOUT("\"words\" parameter out of bounds\n");
3435 return -E1000_ERR_EEPROM;
3436 }
3437
3438 /* Prepare the EEPROM for reading */
3439 if(em_acquire_eeprom(hw) != E1000_SUCCESS)
3440 return -E1000_ERR_EEPROM;
3441
3442 if(eeprom->type == em_eeprom_spi) {
3443 uint16_t word_in;
3444 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
3445
3446 if(em_spi_eeprom_ready(hw)) {
3447 em_release_eeprom(hw);
3448 return -E1000_ERR_EEPROM;
3449 }
3450
3451 em_standby_eeprom(hw);
3452
3453 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
3454 if((eeprom->address_bits == 8) && (offset >= 128))
3455 read_opcode |= EEPROM_A8_OPCODE_SPI;
3456
3457 /* Send the READ command (opcode + addr) */
3458 em_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
3459 em_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
3460
3461 /* Read the data. The address of the eeprom internally increments with
3462 * each byte (spi) being read, saving on the overhead of eeprom setup
3463 * and tear-down. The address counter will roll over if reading beyond
3464 * the size of the eeprom, thus allowing the entire memory to be read
3465 * starting from any offset. */
3466 for (i = 0; i < words; i++) {
3467 word_in = em_shift_in_ee_bits(hw, 16);
3468 data[i] = (word_in >> 8) | (word_in << 8);
3469 }
3470 } else if(eeprom->type == em_eeprom_microwire) {
3471 for (i = 0; i < words; i++) {
3472 /* Send the READ command (opcode + addr) */
3473 em_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
3474 eeprom->opcode_bits);
3475 em_shift_out_ee_bits(hw, (uint16_t)(offset + i),
3476 eeprom->address_bits);
3477
3478 /* Read the data. For microwire, each word requires the overhead
3479 * of eeprom setup and tear-down. */
3480 data[i] = em_shift_in_ee_bits(hw, 16);
3481 em_standby_eeprom(hw);
3482 }
3483 }
3484
3485 /* End this read operation */
3486 em_release_eeprom(hw);
3487
3488 return E1000_SUCCESS;
3489 }
3490
3491 /******************************************************************************
3492 * Verifies that the EEPROM has a valid checksum
3493 *
3494 * hw - Struct containing variables accessed by shared code
3495 *
3496 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
3497 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
3498 * valid.
3499 *****************************************************************************/
3500 int32_t
em_validate_eeprom_checksum(struct em_hw * hw)3501 em_validate_eeprom_checksum(struct em_hw *hw)
3502 {
3503 uint16_t checksum = 0;
3504 uint16_t i, eeprom_data;
3505
3506 DEBUGFUNC("em_validate_eeprom_checksum");
3507
3508 for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
3509 if(em_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
3510 DEBUGOUT("EEPROM Read Error\n");
3511 return -E1000_ERR_EEPROM;
3512 }
3513 checksum += eeprom_data;
3514 }
3515
3516 if(checksum == (uint16_t) EEPROM_SUM)
3517 return E1000_SUCCESS;
3518 else {
3519 DEBUGOUT("EEPROM Checksum Invalid\n");
3520 return -E1000_ERR_EEPROM;
3521 }
3522 }
3523
3524 /******************************************************************************
3525 * Calculates the EEPROM checksum and writes it to the EEPROM
3526 *
3527 * hw - Struct containing variables accessed by shared code
3528 *
3529 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
3530 * Writes the difference to word offset 63 of the EEPROM.
3531 *****************************************************************************/
3532 int32_t
em_update_eeprom_checksum(struct em_hw * hw)3533 em_update_eeprom_checksum(struct em_hw *hw)
3534 {
3535 uint16_t checksum = 0;
3536 uint16_t i, eeprom_data;
3537
3538 DEBUGFUNC("em_update_eeprom_checksum");
3539
3540 for(i = 0; i < EEPROM_CHECKSUM_REG; i++) {
3541 if(em_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
3542 DEBUGOUT("EEPROM Read Error\n");
3543 return -E1000_ERR_EEPROM;
3544 }
3545 checksum += eeprom_data;
3546 }
3547 checksum = (uint16_t) EEPROM_SUM - checksum;
3548 if(em_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
3549 DEBUGOUT("EEPROM Write Error\n");
3550 return -E1000_ERR_EEPROM;
3551 }
3552 return E1000_SUCCESS;
3553 }
3554
3555 /******************************************************************************
3556 * Parent function for writing words to the different EEPROM types.
3557 *
3558 * hw - Struct containing variables accessed by shared code
3559 * offset - offset within the EEPROM to be written to
3560 * words - number of words to write
3561 * data - 16 bit word to be written to the EEPROM
3562 *
3563 * If em_update_eeprom_checksum is not called after this function, the
3564 * EEPROM will most likely contain an invalid checksum.
3565 *****************************************************************************/
3566 int32_t
em_write_eeprom(struct em_hw * hw,uint16_t offset,uint16_t words,uint16_t * data)3567 em_write_eeprom(struct em_hw *hw,
3568 uint16_t offset,
3569 uint16_t words,
3570 uint16_t *data)
3571 {
3572 struct em_eeprom_info *eeprom = &hw->eeprom;
3573 int32_t status = 0;
3574
3575 DEBUGFUNC("em_write_eeprom");
3576
3577 /* A check for invalid values: offset too large, too many words, and not
3578 * enough words.
3579 */
3580 if((offset > eeprom->word_size) || (words > eeprom->word_size - offset) ||
3581 (words == 0)) {
3582 DEBUGOUT("\"words\" parameter out of bounds\n");
3583 return -E1000_ERR_EEPROM;
3584 }
3585
3586 /* Prepare the EEPROM for writing */
3587 if (em_acquire_eeprom(hw) != E1000_SUCCESS)
3588 return -E1000_ERR_EEPROM;
3589
3590 if(eeprom->type == em_eeprom_microwire) {
3591 status = em_write_eeprom_microwire(hw, offset, words, data);
3592 } else {
3593 status = em_write_eeprom_spi(hw, offset, words, data);
3594 msec_delay(10);
3595 }
3596
3597 /* Done with writing */
3598 em_release_eeprom(hw);
3599
3600 return status;
3601 }
3602
3603 /******************************************************************************
3604 * Writes a 16 bit word to a given offset in an SPI EEPROM.
3605 *
3606 * hw - Struct containing variables accessed by shared code
3607 * offset - offset within the EEPROM to be written to
3608 * words - number of words to write
3609 * data - pointer to array of 8 bit words to be written to the EEPROM
3610 *
3611 *****************************************************************************/
3612 int32_t
em_write_eeprom_spi(struct em_hw * hw,uint16_t offset,uint16_t words,uint16_t * data)3613 em_write_eeprom_spi(struct em_hw *hw,
3614 uint16_t offset,
3615 uint16_t words,
3616 uint16_t *data)
3617 {
3618 struct em_eeprom_info *eeprom = &hw->eeprom;
3619 uint16_t widx = 0;
3620
3621 DEBUGFUNC("em_write_eeprom_spi");
3622
3623 while (widx < words) {
3624 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI;
3625
3626 if(em_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
3627
3628 em_standby_eeprom(hw);
3629
3630 /* Send the WRITE ENABLE command (8 bit opcode ) */
3631 em_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
3632 eeprom->opcode_bits);
3633
3634 em_standby_eeprom(hw);
3635
3636 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
3637 if((eeprom->address_bits == 8) && (offset >= 128))
3638 write_opcode |= EEPROM_A8_OPCODE_SPI;
3639
3640 /* Send the Write command (8-bit opcode + addr) */
3641 em_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
3642
3643 em_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2),
3644 eeprom->address_bits);
3645
3646 /* Send the data */
3647
3648 /* Loop to allow for up to whole page write (32 bytes) of eeprom */
3649 while (widx < words) {
3650 uint16_t word_out = data[widx];
3651 word_out = (word_out >> 8) | (word_out << 8);
3652 em_shift_out_ee_bits(hw, word_out, 16);
3653 widx++;
3654
3655 /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
3656 * operation, while the smaller eeproms are capable of an 8-byte
3657 * PAGE WRITE operation. Break the inner loop to pass new address
3658 */
3659 if((((offset + widx)*2) % eeprom->page_size) == 0) {
3660 em_standby_eeprom(hw);
3661 break;
3662 }
3663 }
3664 }
3665
3666 return E1000_SUCCESS;
3667 }
3668
3669 /******************************************************************************
3670 * Writes a 16 bit word to a given offset in a Microwire EEPROM.
3671 *
3672 * hw - Struct containing variables accessed by shared code
3673 * offset - offset within the EEPROM to be written to
3674 * words - number of words to write
3675 * data - pointer to array of 16 bit words to be written to the EEPROM
3676 *
3677 *****************************************************************************/
3678 int32_t
em_write_eeprom_microwire(struct em_hw * hw,uint16_t offset,uint16_t words,uint16_t * data)3679 em_write_eeprom_microwire(struct em_hw *hw,
3680 uint16_t offset,
3681 uint16_t words,
3682 uint16_t *data)
3683 {
3684 struct em_eeprom_info *eeprom = &hw->eeprom;
3685 uint32_t eecd;
3686 uint16_t words_written = 0;
3687 uint16_t i = 0;
3688
3689 DEBUGFUNC("em_write_eeprom_microwire");
3690
3691 /* Send the write enable command to the EEPROM (3-bit opcode plus
3692 * 6/8-bit dummy address beginning with 11). It's less work to include
3693 * the 11 of the dummy address as part of the opcode than it is to shift
3694 * it over the correct number of bits for the address. This puts the
3695 * EEPROM into write/erase mode.
3696 */
3697 em_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
3698 (uint16_t)(eeprom->opcode_bits + 2));
3699
3700 em_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
3701
3702 /* Prepare the EEPROM */
3703 em_standby_eeprom(hw);
3704
3705 while (words_written < words) {
3706 /* Send the Write command (3-bit opcode + addr) */
3707 em_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
3708 eeprom->opcode_bits);
3709
3710 em_shift_out_ee_bits(hw, (uint16_t)(offset + words_written),
3711 eeprom->address_bits);
3712
3713 /* Send the data */
3714 em_shift_out_ee_bits(hw, data[words_written], 16);
3715
3716 /* Toggle the CS line. This in effect tells the EEPROM to execute
3717 * the previous command.
3718 */
3719 em_standby_eeprom(hw);
3720
3721 /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will
3722 * signal that the command has been completed by raising the DO signal.
3723 * If DO does not go high in 10 milliseconds, then error out.
3724 */
3725 for(i = 0; i < 200; i++) {
3726 eecd = E1000_READ_REG(hw, EECD);
3727 if(eecd & E1000_EECD_DO) break;
3728 usec_delay(50);
3729 }
3730 if(i == 200) {
3731 DEBUGOUT("EEPROM Write did not complete\n");
3732 return -E1000_ERR_EEPROM;
3733 }
3734
3735 /* Recover from write */
3736 em_standby_eeprom(hw);
3737
3738 words_written++;
3739 }
3740
3741 /* Send the write disable command to the EEPROM (3-bit opcode plus
3742 * 6/8-bit dummy address beginning with 10). It's less work to include
3743 * the 10 of the dummy address as part of the opcode than it is to shift
3744 * it over the correct number of bits for the address. This takes the
3745 * EEPROM out of write/erase mode.
3746 */
3747 em_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
3748 (uint16_t)(eeprom->opcode_bits + 2));
3749
3750 em_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
3751
3752 return E1000_SUCCESS;
3753 }
3754
3755 /******************************************************************************
3756 * Reads the adapter's part number from the EEPROM
3757 *
3758 * hw - Struct containing variables accessed by shared code
3759 * part_num - Adapter's part number
3760 *****************************************************************************/
3761 int32_t
em_read_part_num(struct em_hw * hw,uint32_t * part_num)3762 em_read_part_num(struct em_hw *hw,
3763 uint32_t *part_num)
3764 {
3765 uint16_t offset = EEPROM_PBA_BYTE_1;
3766 uint16_t eeprom_data;
3767
3768 DEBUGFUNC("em_read_part_num");
3769
3770 /* Get word 0 from EEPROM */
3771 if(em_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
3772 DEBUGOUT("EEPROM Read Error\n");
3773 return -E1000_ERR_EEPROM;
3774 }
3775 /* Save word 0 in upper half of part_num */
3776 *part_num = (uint32_t) (eeprom_data << 16);
3777
3778 /* Get word 1 from EEPROM */
3779 if(em_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) {
3780 DEBUGOUT("EEPROM Read Error\n");
3781 return -E1000_ERR_EEPROM;
3782 }
3783 /* Save word 1 in lower half of part_num */
3784 *part_num |= eeprom_data;
3785
3786 return E1000_SUCCESS;
3787 }
3788
3789 /******************************************************************************
3790 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
3791 * second function of dual function devices
3792 *
3793 * hw - Struct containing variables accessed by shared code
3794 *****************************************************************************/
3795 int32_t
em_read_mac_addr(struct em_hw * hw)3796 em_read_mac_addr(struct em_hw * hw)
3797 {
3798 uint16_t offset;
3799 uint16_t eeprom_data, i;
3800
3801 DEBUGFUNC("em_read_mac_addr");
3802
3803 for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
3804 offset = i >> 1;
3805 if(em_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
3806 DEBUGOUT("EEPROM Read Error\n");
3807 return -E1000_ERR_EEPROM;
3808 }
3809 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF);
3810 hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8);
3811 }
3812 if(((hw->mac_type == em_82546) || (hw->mac_type == em_82546_rev_3)) &&
3813 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1))
3814 hw->perm_mac_addr[5] ^= 0x01;
3815
3816 for(i = 0; i < NODE_ADDRESS_SIZE; i++)
3817 hw->mac_addr[i] = hw->perm_mac_addr[i];
3818 return E1000_SUCCESS;
3819 }
3820
3821 /******************************************************************************
3822 * Initializes receive address filters.
3823 *
3824 * hw - Struct containing variables accessed by shared code
3825 *
3826 * Places the MAC address in receive address register 0 and clears the rest
3827 * of the receive addresss registers. Clears the multicast table. Assumes
3828 * the receiver is in reset when the routine is called.
3829 *****************************************************************************/
3830 void
em_init_rx_addrs(struct em_hw * hw)3831 em_init_rx_addrs(struct em_hw *hw)
3832 {
3833 uint32_t i;
3834
3835 DEBUGFUNC("em_init_rx_addrs");
3836
3837 /* Setup the receive address. */
3838 DEBUGOUT("Programming MAC Address into RAR[0]\n");
3839
3840 em_rar_set(hw, hw->mac_addr, 0);
3841
3842 /* Zero out the other 15 receive addresses. */
3843 DEBUGOUT("Clearing RAR[1-15]\n");
3844 for(i = 1; i < E1000_RAR_ENTRIES; i++) {
3845 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
3846 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
3847 }
3848 }
3849
3850 /******************************************************************************
3851 * Updates the MAC's list of multicast addresses.
3852 *
3853 * hw - Struct containing variables accessed by shared code
3854 * mc_addr_list - the list of new multicast addresses
3855 * mc_addr_count - number of addresses
3856 * pad - number of bytes between addresses in the list
3857 * rar_used_count - offset where to start adding mc addresses into the RAR's
3858 *
3859 * The given list replaces any existing list. Clears the last 15 receive
3860 * address registers and the multicast table. Uses receive address registers
3861 * for the first 15 multicast addresses, and hashes the rest into the
3862 * multicast table.
3863 *****************************************************************************/
3864 void
em_mc_addr_list_update(struct em_hw * hw,uint8_t * mc_addr_list,uint32_t mc_addr_count,uint32_t pad,uint32_t rar_used_count)3865 em_mc_addr_list_update(struct em_hw *hw,
3866 uint8_t *mc_addr_list,
3867 uint32_t mc_addr_count,
3868 uint32_t pad,
3869 uint32_t rar_used_count)
3870 {
3871 uint32_t hash_value;
3872 uint32_t i;
3873
3874 DEBUGFUNC("em_mc_addr_list_update");
3875
3876 /* Set the new number of MC addresses that we are being requested to use. */
3877 hw->num_mc_addrs = mc_addr_count;
3878
3879 /* Clear RAR[1-15] */
3880 DEBUGOUT(" Clearing RAR[1-15]\n");
3881 for(i = rar_used_count; i < E1000_RAR_ENTRIES; i++) {
3882 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
3883 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
3884 }
3885
3886 /* Clear the MTA */
3887 DEBUGOUT(" Clearing MTA\n");
3888 for(i = 0; i < E1000_NUM_MTA_REGISTERS; i++) {
3889 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
3890 }
3891
3892 /* Add the new addresses */
3893 for(i = 0; i < mc_addr_count; i++) {
3894 DEBUGOUT(" Adding the multicast addresses:\n");
3895 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
3896 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)],
3897 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1],
3898 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2],
3899 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3],
3900 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4],
3901 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]);
3902
3903 hash_value = em_hash_mc_addr(hw,
3904 mc_addr_list +
3905 (i * (ETH_LENGTH_OF_ADDRESS + pad)));
3906
3907 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value);
3908
3909 /* Place this multicast address in the RAR if there is room, *
3910 * else put it in the MTA
3911 */
3912 if(rar_used_count < E1000_RAR_ENTRIES) {
3913 em_rar_set(hw,
3914 mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)),
3915 rar_used_count);
3916 rar_used_count++;
3917 } else {
3918 em_mta_set(hw, hash_value);
3919 }
3920 }
3921 DEBUGOUT("MC Update Complete\n");
3922 }
3923
3924 /******************************************************************************
3925 * Hashes an address to determine its location in the multicast table
3926 *
3927 * hw - Struct containing variables accessed by shared code
3928 * mc_addr - the multicast address to hash
3929 *****************************************************************************/
3930 uint32_t
em_hash_mc_addr(struct em_hw * hw,uint8_t * mc_addr)3931 em_hash_mc_addr(struct em_hw *hw,
3932 uint8_t *mc_addr)
3933 {
3934 uint32_t hash_value = 0;
3935
3936 /* The portion of the address that is used for the hash table is
3937 * determined by the mc_filter_type setting.
3938 */
3939 switch (hw->mc_filter_type) {
3940 /* [0] [1] [2] [3] [4] [5]
3941 * 01 AA 00 12 34 56
3942 * LSB MSB
3943 */
3944 case 0:
3945 /* [47:36] i.e. 0x563 for above example address */
3946 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
3947 break;
3948 case 1:
3949 /* [46:35] i.e. 0xAC6 for above example address */
3950 hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5));
3951 break;
3952 case 2:
3953 /* [45:34] i.e. 0x5D8 for above example address */
3954 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
3955 break;
3956 case 3:
3957 /* [43:32] i.e. 0x634 for above example address */
3958 hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8));
3959 break;
3960 }
3961
3962 hash_value &= 0xFFF;
3963 return hash_value;
3964 }
3965
3966 /******************************************************************************
3967 * Sets the bit in the multicast table corresponding to the hash value.
3968 *
3969 * hw - Struct containing variables accessed by shared code
3970 * hash_value - Multicast address hash value
3971 *****************************************************************************/
3972 void
em_mta_set(struct em_hw * hw,uint32_t hash_value)3973 em_mta_set(struct em_hw *hw,
3974 uint32_t hash_value)
3975 {
3976 uint32_t hash_bit, hash_reg;
3977 uint32_t mta;
3978 uint32_t temp;
3979
3980 /* The MTA is a register array of 128 32-bit registers.
3981 * It is treated like an array of 4096 bits. We want to set
3982 * bit BitArray[hash_value]. So we figure out what register
3983 * the bit is in, read it, OR in the new bit, then write
3984 * back the new value. The register is determined by the
3985 * upper 7 bits of the hash value and the bit within that
3986 * register are determined by the lower 5 bits of the value.
3987 */
3988 hash_reg = (hash_value >> 5) & 0x7F;
3989 hash_bit = hash_value & 0x1F;
3990
3991 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
3992
3993 mta |= (1 << hash_bit);
3994
3995 /* If we are on an 82544 and we are trying to write an odd offset
3996 * in the MTA, save off the previous entry before writing and
3997 * restore the old value after writing.
3998 */
3999 if((hw->mac_type == em_82544) && ((hash_reg & 0x1) == 1)) {
4000 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
4001 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
4002 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
4003 } else {
4004 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
4005 }
4006 }
4007
4008 /******************************************************************************
4009 * Puts an ethernet address into a receive address register.
4010 *
4011 * hw - Struct containing variables accessed by shared code
4012 * addr - Address to put into receive address register
4013 * index - Receive address register to write
4014 *****************************************************************************/
4015 void
em_rar_set(struct em_hw * hw,uint8_t * addr,uint32_t index)4016 em_rar_set(struct em_hw *hw,
4017 uint8_t *addr,
4018 uint32_t index)
4019 {
4020 uint32_t rar_low, rar_high;
4021
4022 /* HW expects these in little endian so we reverse the byte order
4023 * from network order (big endian) to little endian
4024 */
4025 rar_low = ((uint32_t) addr[0] |
4026 ((uint32_t) addr[1] << 8) |
4027 ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24));
4028
4029 rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8) | E1000_RAH_AV);
4030
4031 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
4032 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
4033 }
4034
4035 /******************************************************************************
4036 * Writes a value to the specified offset in the VLAN filter table.
4037 *
4038 * hw - Struct containing variables accessed by shared code
4039 * offset - Offset in VLAN filer table to write
4040 * value - Value to write into VLAN filter table
4041 *****************************************************************************/
4042 void
em_write_vfta(struct em_hw * hw,uint32_t offset,uint32_t value)4043 em_write_vfta(struct em_hw *hw,
4044 uint32_t offset,
4045 uint32_t value)
4046 {
4047 uint32_t temp;
4048
4049 if((hw->mac_type == em_82544) && ((offset & 0x1) == 1)) {
4050 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
4051 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4052 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
4053 } else {
4054 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4055 }
4056 }
4057
4058 /******************************************************************************
4059 * Clears the VLAN filer table
4060 *
4061 * hw - Struct containing variables accessed by shared code
4062 *****************************************************************************/
4063 void
em_clear_vfta(struct em_hw * hw)4064 em_clear_vfta(struct em_hw *hw)
4065 {
4066 uint32_t offset;
4067
4068 for(offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
4069 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
4070 }
4071
4072 static int32_t
em_id_led_init(struct em_hw * hw)4073 em_id_led_init(struct em_hw * hw)
4074 {
4075 uint32_t ledctl;
4076 const uint32_t ledctl_mask = 0x000000FF;
4077 const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON;
4078 const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
4079 uint16_t eeprom_data, i, temp;
4080 const uint16_t led_mask = 0x0F;
4081
4082 DEBUGFUNC("em_id_led_init");
4083
4084 if(hw->mac_type < em_82540) {
4085 /* Nothing to do */
4086 return E1000_SUCCESS;
4087 }
4088
4089 ledctl = E1000_READ_REG(hw, LEDCTL);
4090 hw->ledctl_default = ledctl;
4091 hw->ledctl_mode1 = hw->ledctl_default;
4092 hw->ledctl_mode2 = hw->ledctl_default;
4093
4094 if(em_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
4095 DEBUGOUT("EEPROM Read Error\n");
4096 return -E1000_ERR_EEPROM;
4097 }
4098 if((eeprom_data== ID_LED_RESERVED_0000) ||
4099 (eeprom_data == ID_LED_RESERVED_FFFF)) eeprom_data = ID_LED_DEFAULT;
4100 for(i = 0; i < 4; i++) {
4101 temp = (eeprom_data >> (i << 2)) & led_mask;
4102 switch(temp) {
4103 case ID_LED_ON1_DEF2:
4104 case ID_LED_ON1_ON2:
4105 case ID_LED_ON1_OFF2:
4106 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
4107 hw->ledctl_mode1 |= ledctl_on << (i << 3);
4108 break;
4109 case ID_LED_OFF1_DEF2:
4110 case ID_LED_OFF1_ON2:
4111 case ID_LED_OFF1_OFF2:
4112 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
4113 hw->ledctl_mode1 |= ledctl_off << (i << 3);
4114 break;
4115 default:
4116 /* Do nothing */
4117 break;
4118 }
4119 switch(temp) {
4120 case ID_LED_DEF1_ON2:
4121 case ID_LED_ON1_ON2:
4122 case ID_LED_OFF1_ON2:
4123 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
4124 hw->ledctl_mode2 |= ledctl_on << (i << 3);
4125 break;
4126 case ID_LED_DEF1_OFF2:
4127 case ID_LED_ON1_OFF2:
4128 case ID_LED_OFF1_OFF2:
4129 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
4130 hw->ledctl_mode2 |= ledctl_off << (i << 3);
4131 break;
4132 default:
4133 /* Do nothing */
4134 break;
4135 }
4136 }
4137 return E1000_SUCCESS;
4138 }
4139
4140 /******************************************************************************
4141 * Prepares SW controlable LED for use and saves the current state of the LED.
4142 *
4143 * hw - Struct containing variables accessed by shared code
4144 *****************************************************************************/
4145 int32_t
em_setup_led(struct em_hw * hw)4146 em_setup_led(struct em_hw *hw)
4147 {
4148 uint32_t ledctl;
4149 int32_t ret_val = E1000_SUCCESS;
4150
4151 DEBUGFUNC("em_setup_led");
4152
4153 switch(hw->mac_type) {
4154 case em_82542_rev2_0:
4155 case em_82542_rev2_1:
4156 case em_82543:
4157 case em_82544:
4158 /* No setup necessary */
4159 break;
4160 case em_82541:
4161 case em_82547:
4162 case em_82541_rev_2:
4163 case em_82547_rev_2:
4164 /* Turn off PHY Smart Power Down (if enabled) */
4165 if((ret_val = em_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
4166 &hw->phy_spd_default)))
4167 return ret_val;
4168 if((ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
4169 (uint16_t)(hw->phy_spd_default &
4170 ~IGP01E1000_GMII_SPD))))
4171 return ret_val;
4172 /* Fall Through */
4173 default:
4174 if(hw->media_type == em_media_type_fiber) {
4175 ledctl = E1000_READ_REG(hw, LEDCTL);
4176 /* Save current LEDCTL settings */
4177 hw->ledctl_default = ledctl;
4178 /* Turn off LED0 */
4179 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
4180 E1000_LEDCTL_LED0_BLINK |
4181 E1000_LEDCTL_LED0_MODE_MASK);
4182 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
4183 E1000_LEDCTL_LED0_MODE_SHIFT);
4184 E1000_WRITE_REG(hw, LEDCTL, ledctl);
4185 } else if(hw->media_type == em_media_type_copper)
4186 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
4187 break;
4188 }
4189
4190 return E1000_SUCCESS;
4191 }
4192
4193 /******************************************************************************
4194 * Restores the saved state of the SW controlable LED.
4195 *
4196 * hw - Struct containing variables accessed by shared code
4197 *****************************************************************************/
4198 int32_t
em_cleanup_led(struct em_hw * hw)4199 em_cleanup_led(struct em_hw *hw)
4200 {
4201 int32_t ret_val = E1000_SUCCESS;
4202
4203 DEBUGFUNC("em_cleanup_led");
4204
4205 switch(hw->mac_type) {
4206 case em_82542_rev2_0:
4207 case em_82542_rev2_1:
4208 case em_82543:
4209 case em_82544:
4210 /* No cleanup necessary */
4211 break;
4212 case em_82541:
4213 case em_82547:
4214 case em_82541_rev_2:
4215 case em_82547_rev_2:
4216 /* Turn on PHY Smart Power Down (if previously enabled) */
4217 if((ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
4218 hw->phy_spd_default)))
4219 return ret_val;
4220 /* Fall Through */
4221 default:
4222 /* Restore LEDCTL settings */
4223 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default);
4224 break;
4225 }
4226
4227 return E1000_SUCCESS;
4228 }
4229
4230 /******************************************************************************
4231 * Turns on the software controllable LED
4232 *
4233 * hw - Struct containing variables accessed by shared code
4234 *****************************************************************************/
4235 int32_t
em_led_on(struct em_hw * hw)4236 em_led_on(struct em_hw *hw)
4237 {
4238 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
4239
4240 DEBUGFUNC("em_led_on");
4241
4242 switch(hw->mac_type) {
4243 case em_82542_rev2_0:
4244 case em_82542_rev2_1:
4245 case em_82543:
4246 /* Set SW Defineable Pin 0 to turn on the LED */
4247 ctrl |= E1000_CTRL_SWDPIN0;
4248 ctrl |= E1000_CTRL_SWDPIO0;
4249 break;
4250 case em_82544:
4251 if(hw->media_type == em_media_type_fiber) {
4252 /* Set SW Defineable Pin 0 to turn on the LED */
4253 ctrl |= E1000_CTRL_SWDPIN0;
4254 ctrl |= E1000_CTRL_SWDPIO0;
4255 } else {
4256 /* Clear SW Defineable Pin 0 to turn on the LED */
4257 ctrl &= ~E1000_CTRL_SWDPIN0;
4258 ctrl |= E1000_CTRL_SWDPIO0;
4259 }
4260 break;
4261 default:
4262 if(hw->media_type == em_media_type_fiber) {
4263 /* Clear SW Defineable Pin 0 to turn on the LED */
4264 ctrl &= ~E1000_CTRL_SWDPIN0;
4265 ctrl |= E1000_CTRL_SWDPIO0;
4266 } else if(hw->media_type == em_media_type_copper) {
4267 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2);
4268 return E1000_SUCCESS;
4269 }
4270 break;
4271 }
4272
4273 E1000_WRITE_REG(hw, CTRL, ctrl);
4274
4275 return E1000_SUCCESS;
4276 }
4277
4278 /******************************************************************************
4279 * Turns off the software controllable LED
4280 *
4281 * hw - Struct containing variables accessed by shared code
4282 *****************************************************************************/
4283 int32_t
em_led_off(struct em_hw * hw)4284 em_led_off(struct em_hw *hw)
4285 {
4286 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
4287
4288 DEBUGFUNC("em_led_off");
4289
4290 switch(hw->mac_type) {
4291 case em_82542_rev2_0:
4292 case em_82542_rev2_1:
4293 case em_82543:
4294 /* Clear SW Defineable Pin 0 to turn off the LED */
4295 ctrl &= ~E1000_CTRL_SWDPIN0;
4296 ctrl |= E1000_CTRL_SWDPIO0;
4297 break;
4298 case em_82544:
4299 if(hw->media_type == em_media_type_fiber) {
4300 /* Clear SW Defineable Pin 0 to turn off the LED */
4301 ctrl &= ~E1000_CTRL_SWDPIN0;
4302 ctrl |= E1000_CTRL_SWDPIO0;
4303 } else {
4304 /* Set SW Defineable Pin 0 to turn off the LED */
4305 ctrl |= E1000_CTRL_SWDPIN0;
4306 ctrl |= E1000_CTRL_SWDPIO0;
4307 }
4308 break;
4309 default:
4310 if(hw->media_type == em_media_type_fiber) {
4311 /* Set SW Defineable Pin 0 to turn off the LED */
4312 ctrl |= E1000_CTRL_SWDPIN0;
4313 ctrl |= E1000_CTRL_SWDPIO0;
4314 } else if(hw->media_type == em_media_type_copper) {
4315 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
4316 return E1000_SUCCESS;
4317 }
4318 break;
4319 }
4320
4321 E1000_WRITE_REG(hw, CTRL, ctrl);
4322
4323 return E1000_SUCCESS;
4324 }
4325
4326 /******************************************************************************
4327 * Clears all hardware statistics counters.
4328 *
4329 * hw - Struct containing variables accessed by shared code
4330 *****************************************************************************/
4331 void
em_clear_hw_cntrs(struct em_hw * hw)4332 em_clear_hw_cntrs(struct em_hw *hw)
4333 {
4334 volatile uint32_t temp;
4335
4336 temp = E1000_READ_REG(hw, CRCERRS);
4337 temp = E1000_READ_REG(hw, SYMERRS);
4338 temp = E1000_READ_REG(hw, MPC);
4339 temp = E1000_READ_REG(hw, SCC);
4340 temp = E1000_READ_REG(hw, ECOL);
4341 temp = E1000_READ_REG(hw, MCC);
4342 temp = E1000_READ_REG(hw, LATECOL);
4343 temp = E1000_READ_REG(hw, COLC);
4344 temp = E1000_READ_REG(hw, DC);
4345 temp = E1000_READ_REG(hw, SEC);
4346 temp = E1000_READ_REG(hw, RLEC);
4347 temp = E1000_READ_REG(hw, XONRXC);
4348 temp = E1000_READ_REG(hw, XONTXC);
4349 temp = E1000_READ_REG(hw, XOFFRXC);
4350 temp = E1000_READ_REG(hw, XOFFTXC);
4351 temp = E1000_READ_REG(hw, FCRUC);
4352 temp = E1000_READ_REG(hw, PRC64);
4353 temp = E1000_READ_REG(hw, PRC127);
4354 temp = E1000_READ_REG(hw, PRC255);
4355 temp = E1000_READ_REG(hw, PRC511);
4356 temp = E1000_READ_REG(hw, PRC1023);
4357 temp = E1000_READ_REG(hw, PRC1522);
4358 temp = E1000_READ_REG(hw, GPRC);
4359 temp = E1000_READ_REG(hw, BPRC);
4360 temp = E1000_READ_REG(hw, MPRC);
4361 temp = E1000_READ_REG(hw, GPTC);
4362 temp = E1000_READ_REG(hw, GORCL);
4363 temp = E1000_READ_REG(hw, GORCH);
4364 temp = E1000_READ_REG(hw, GOTCL);
4365 temp = E1000_READ_REG(hw, GOTCH);
4366 temp = E1000_READ_REG(hw, RNBC);
4367 temp = E1000_READ_REG(hw, RUC);
4368 temp = E1000_READ_REG(hw, RFC);
4369 temp = E1000_READ_REG(hw, ROC);
4370 temp = E1000_READ_REG(hw, RJC);
4371 temp = E1000_READ_REG(hw, TORL);
4372 temp = E1000_READ_REG(hw, TORH);
4373 temp = E1000_READ_REG(hw, TOTL);
4374 temp = E1000_READ_REG(hw, TOTH);
4375 temp = E1000_READ_REG(hw, TPR);
4376 temp = E1000_READ_REG(hw, TPT);
4377 temp = E1000_READ_REG(hw, PTC64);
4378 temp = E1000_READ_REG(hw, PTC127);
4379 temp = E1000_READ_REG(hw, PTC255);
4380 temp = E1000_READ_REG(hw, PTC511);
4381 temp = E1000_READ_REG(hw, PTC1023);
4382 temp = E1000_READ_REG(hw, PTC1522);
4383 temp = E1000_READ_REG(hw, MPTC);
4384 temp = E1000_READ_REG(hw, BPTC);
4385
4386 if(hw->mac_type < em_82543) return;
4387
4388 temp = E1000_READ_REG(hw, ALGNERRC);
4389 temp = E1000_READ_REG(hw, RXERRC);
4390 temp = E1000_READ_REG(hw, TNCRS);
4391 temp = E1000_READ_REG(hw, CEXTERR);
4392 temp = E1000_READ_REG(hw, TSCTC);
4393 temp = E1000_READ_REG(hw, TSCTFC);
4394
4395 if(hw->mac_type <= em_82544) return;
4396
4397 temp = E1000_READ_REG(hw, MGTPRC);
4398 temp = E1000_READ_REG(hw, MGTPDC);
4399 temp = E1000_READ_REG(hw, MGTPTC);
4400 }
4401
4402 /******************************************************************************
4403 * Resets Adaptive IFS to its default state.
4404 *
4405 * hw - Struct containing variables accessed by shared code
4406 *
4407 * Call this after em_init_hw. You may override the IFS defaults by setting
4408 * hw->ifs_params_forced to TRUE. However, you must initialize hw->
4409 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
4410 * before calling this function.
4411 *****************************************************************************/
4412 void
em_reset_adaptive(struct em_hw * hw)4413 em_reset_adaptive(struct em_hw *hw)
4414 {
4415 DEBUGFUNC("em_reset_adaptive");
4416
4417 if(hw->adaptive_ifs) {
4418 if(!hw->ifs_params_forced) {
4419 hw->current_ifs_val = 0;
4420 hw->ifs_min_val = IFS_MIN;
4421 hw->ifs_max_val = IFS_MAX;
4422 hw->ifs_step_size = IFS_STEP;
4423 hw->ifs_ratio = IFS_RATIO;
4424 }
4425 hw->in_ifs_mode = FALSE;
4426 E1000_WRITE_REG(hw, AIT, 0);
4427 } else {
4428 DEBUGOUT("Not in Adaptive IFS mode!\n");
4429 }
4430 }
4431
4432 /******************************************************************************
4433 * Called during the callback/watchdog routine to update IFS value based on
4434 * the ratio of transmits to collisions.
4435 *
4436 * hw - Struct containing variables accessed by shared code
4437 * tx_packets - Number of transmits since last callback
4438 * total_collisions - Number of collisions since last callback
4439 *****************************************************************************/
4440 void
em_update_adaptive(struct em_hw * hw)4441 em_update_adaptive(struct em_hw *hw)
4442 {
4443 DEBUGFUNC("em_update_adaptive");
4444
4445 if(hw->adaptive_ifs) {
4446 if((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
4447 if(hw->tx_packet_delta > MIN_NUM_XMITS) {
4448 hw->in_ifs_mode = TRUE;
4449 if(hw->current_ifs_val < hw->ifs_max_val) {
4450 if(hw->current_ifs_val == 0)
4451 hw->current_ifs_val = hw->ifs_min_val;
4452 else
4453 hw->current_ifs_val += hw->ifs_step_size;
4454 E1000_WRITE_REG(hw, AIT, hw->current_ifs_val);
4455 }
4456 }
4457 } else {
4458 if(hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
4459 hw->current_ifs_val = 0;
4460 hw->in_ifs_mode = FALSE;
4461 E1000_WRITE_REG(hw, AIT, 0);
4462 }
4463 }
4464 } else {
4465 DEBUGOUT("Not in Adaptive IFS mode!\n");
4466 }
4467 }
4468
4469 /******************************************************************************
4470 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
4471 *
4472 * hw - Struct containing variables accessed by shared code
4473 * frame_len - The length of the frame in question
4474 * mac_addr - The Ethernet destination address of the frame in question
4475 *****************************************************************************/
4476 void
em_tbi_adjust_stats(struct em_hw * hw,struct em_hw_stats * stats,uint32_t frame_len,uint8_t * mac_addr)4477 em_tbi_adjust_stats(struct em_hw *hw,
4478 struct em_hw_stats *stats,
4479 uint32_t frame_len,
4480 uint8_t *mac_addr)
4481 {
4482 uint64_t carry_bit;
4483
4484 /* First adjust the frame length. */
4485 frame_len--;
4486 /* We need to adjust the statistics counters, since the hardware
4487 * counters overcount this packet as a CRC error and undercount
4488 * the packet as a good packet
4489 */
4490 /* This packet should not be counted as a CRC error. */
4491 stats->crcerrs--;
4492 /* This packet does count as a Good Packet Received. */
4493 stats->gprc++;
4494
4495 /* Adjust the Good Octets received counters */
4496 carry_bit = 0x80000000 & stats->gorcl;
4497 stats->gorcl += frame_len;
4498 /* If the high bit of Gorcl (the low 32 bits of the Good Octets
4499 * Received Count) was one before the addition,
4500 * AND it is zero after, then we lost the carry out,
4501 * need to add one to Gorch (Good Octets Received Count High).
4502 * This could be simplified if all environments supported
4503 * 64-bit integers.
4504 */
4505 if(carry_bit && ((stats->gorcl & 0x80000000) == 0))
4506 stats->gorch++;
4507 /* Is this a broadcast or multicast? Check broadcast first,
4508 * since the test for a multicast frame will test positive on
4509 * a broadcast frame.
4510 */
4511 if((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff))
4512 /* Broadcast packet */
4513 stats->bprc++;
4514 else if(*mac_addr & 0x01)
4515 /* Multicast packet */
4516 stats->mprc++;
4517
4518 if(frame_len == hw->max_frame_size) {
4519 /* In this case, the hardware has overcounted the number of
4520 * oversize frames.
4521 */
4522 if(stats->roc > 0)
4523 stats->roc--;
4524 }
4525
4526 /* Adjust the bin counters when the extra byte put the frame in the
4527 * wrong bin. Remember that the frame_len was adjusted above.
4528 */
4529 if(frame_len == 64) {
4530 stats->prc64++;
4531 stats->prc127--;
4532 } else if(frame_len == 127) {
4533 stats->prc127++;
4534 stats->prc255--;
4535 } else if(frame_len == 255) {
4536 stats->prc255++;
4537 stats->prc511--;
4538 } else if(frame_len == 511) {
4539 stats->prc511++;
4540 stats->prc1023--;
4541 } else if(frame_len == 1023) {
4542 stats->prc1023++;
4543 stats->prc1522--;
4544 } else if(frame_len == 1522) {
4545 stats->prc1522++;
4546 }
4547 }
4548
4549 /******************************************************************************
4550 * Gets the current PCI bus type, speed, and width of the hardware
4551 *
4552 * hw - Struct containing variables accessed by shared code
4553 *****************************************************************************/
4554 void
em_get_bus_info(struct em_hw * hw)4555 em_get_bus_info(struct em_hw *hw)
4556 {
4557 uint32_t status;
4558
4559 if(hw->mac_type < em_82543) {
4560 hw->bus_type = em_bus_type_unknown;
4561 hw->bus_speed = em_bus_speed_unknown;
4562 hw->bus_width = em_bus_width_unknown;
4563 return;
4564 }
4565
4566 status = E1000_READ_REG(hw, STATUS);
4567 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
4568 em_bus_type_pcix : em_bus_type_pci;
4569
4570 if(hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
4571 hw->bus_speed = (hw->bus_type == em_bus_type_pci) ?
4572 em_bus_speed_66 : em_bus_speed_120;
4573 } else if(hw->bus_type == em_bus_type_pci) {
4574 hw->bus_speed = (status & E1000_STATUS_PCI66) ?
4575 em_bus_speed_66 : em_bus_speed_33;
4576 } else {
4577 switch (status & E1000_STATUS_PCIX_SPEED) {
4578 case E1000_STATUS_PCIX_SPEED_66:
4579 hw->bus_speed = em_bus_speed_66;
4580 break;
4581 case E1000_STATUS_PCIX_SPEED_100:
4582 hw->bus_speed = em_bus_speed_100;
4583 break;
4584 case E1000_STATUS_PCIX_SPEED_133:
4585 hw->bus_speed = em_bus_speed_133;
4586 break;
4587 default:
4588 hw->bus_speed = em_bus_speed_reserved;
4589 break;
4590 }
4591 }
4592 hw->bus_width = (status & E1000_STATUS_BUS64) ?
4593 em_bus_width_64 : em_bus_width_32;
4594 }
4595 /******************************************************************************
4596 * Reads a value from one of the devices registers using port I/O (as opposed
4597 * memory mapped I/O). Only 82544 and newer devices support port I/O.
4598 *
4599 * hw - Struct containing variables accessed by shared code
4600 * offset - offset to read from
4601 *****************************************************************************/
4602 uint32_t
em_read_reg_io(struct em_hw * hw,uint32_t offset)4603 em_read_reg_io(struct em_hw *hw,
4604 uint32_t offset)
4605 {
4606 unsigned long io_addr = hw->io_base;
4607 unsigned long io_data = hw->io_base + 4;
4608
4609 em_io_write(hw, io_addr, offset);
4610 return em_io_read(hw, io_data);
4611 }
4612
4613 /******************************************************************************
4614 * Writes a value to one of the devices registers using port I/O (as opposed to
4615 * memory mapped I/O). Only 82544 and newer devices support port I/O.
4616 *
4617 * hw - Struct containing variables accessed by shared code
4618 * offset - offset to write to
4619 * value - value to write
4620 *****************************************************************************/
4621 void
em_write_reg_io(struct em_hw * hw,uint32_t offset,uint32_t value)4622 em_write_reg_io(struct em_hw *hw,
4623 uint32_t offset,
4624 uint32_t value)
4625 {
4626 unsigned long io_addr = hw->io_base;
4627 unsigned long io_data = hw->io_base + 4;
4628
4629 em_io_write(hw, io_addr, offset);
4630 em_io_write(hw, io_data, value);
4631 }
4632
4633
4634 /******************************************************************************
4635 * Estimates the cable length.
4636 *
4637 * hw - Struct containing variables accessed by shared code
4638 * min_length - The estimated minimum length
4639 * max_length - The estimated maximum length
4640 *
4641 * returns: - E1000_ERR_XXX
4642 * E1000_SUCCESS
4643 *
4644 * This function always returns a ranged length (minimum & maximum).
4645 * So for M88 phy's, this function interprets the one value returned from the
4646 * register to the minimum and maximum range.
4647 * For IGP phy's, the function calculates the range by the AGC registers.
4648 *****************************************************************************/
4649 int32_t
em_get_cable_length(struct em_hw * hw,uint16_t * min_length,uint16_t * max_length)4650 em_get_cable_length(struct em_hw *hw,
4651 uint16_t *min_length,
4652 uint16_t *max_length)
4653 {
4654 int32_t ret_val;
4655 uint16_t agc_value = 0;
4656 uint16_t cur_agc, min_agc = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
4657 uint16_t i, phy_data;
4658
4659 DEBUGFUNC("em_get_cable_length");
4660
4661 *min_length = *max_length = 0;
4662
4663 /* Use old method for Phy older than IGP */
4664 if(hw->phy_type == em_phy_m88) {
4665 if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
4666 &phy_data)))
4667 return ret_val;
4668
4669 /* Convert the enum value to ranged values */
4670 switch((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
4671 M88E1000_PSSR_CABLE_LENGTH_SHIFT) {
4672 case em_cable_length_50:
4673 *min_length = 0;
4674 *max_length = em_igp_cable_length_50;
4675 break;
4676 case em_cable_length_50_80:
4677 *min_length = em_igp_cable_length_50;
4678 *max_length = em_igp_cable_length_80;
4679 break;
4680 case em_cable_length_80_110:
4681 *min_length = em_igp_cable_length_80;
4682 *max_length = em_igp_cable_length_110;
4683 break;
4684 case em_cable_length_110_140:
4685 *min_length = em_igp_cable_length_110;
4686 *max_length = em_igp_cable_length_140;
4687 break;
4688 case em_cable_length_140:
4689 *min_length = em_igp_cable_length_140;
4690 *max_length = em_igp_cable_length_170;
4691 break;
4692 default:
4693 return -E1000_ERR_PHY;
4694 break;
4695 }
4696 } else if(hw->phy_type == em_phy_igp) { /* For IGP PHY */
4697 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
4698 {IGP01E1000_PHY_AGC_A,
4699 IGP01E1000_PHY_AGC_B,
4700 IGP01E1000_PHY_AGC_C,
4701 IGP01E1000_PHY_AGC_D};
4702 /* Read the AGC registers for all channels */
4703 for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
4704
4705 if((ret_val = em_read_phy_reg(hw, agc_reg_array[i], &phy_data)))
4706 return ret_val;
4707
4708 cur_agc = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
4709
4710 /* Array bound check. */
4711 if((cur_agc >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
4712 (cur_agc == 0))
4713 return -E1000_ERR_PHY;
4714
4715 agc_value += cur_agc;
4716
4717 /* Update minimal AGC value. */
4718 if(min_agc > cur_agc)
4719 min_agc = cur_agc;
4720 }
4721
4722 /* Remove the minimal AGC result for length < 50m */
4723 if(agc_value < IGP01E1000_PHY_CHANNEL_NUM * em_igp_cable_length_50) {
4724 agc_value -= min_agc;
4725
4726 /* Get the average length of the remaining 3 channels */
4727 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
4728 } else {
4729 /* Get the average length of all the 4 channels. */
4730 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
4731 }
4732
4733 /* Set the range of the calculated length. */
4734 *min_length = ((em_igp_cable_length_table[agc_value] -
4735 IGP01E1000_AGC_RANGE) > 0) ?
4736 (em_igp_cable_length_table[agc_value] -
4737 IGP01E1000_AGC_RANGE) : 0;
4738 *max_length = em_igp_cable_length_table[agc_value] +
4739 IGP01E1000_AGC_RANGE;
4740 }
4741
4742 return E1000_SUCCESS;
4743 }
4744
4745 /******************************************************************************
4746 * Check the cable polarity
4747 *
4748 * hw - Struct containing variables accessed by shared code
4749 * polarity - output parameter : 0 - Polarity is not reversed
4750 * 1 - Polarity is reversed.
4751 *
4752 * returns: - E1000_ERR_XXX
4753 * E1000_SUCCESS
4754 *
4755 * For phy's older then IGP, this function simply reads the polarity bit in the
4756 * Phy Status register. For IGP phy's, this bit is valid only if link speed is
4757 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will
4758 * return 0. If the link speed is 1000 Mbps the polarity status is in the
4759 * IGP01E1000_PHY_PCS_INIT_REG.
4760 *****************************************************************************/
4761 int32_t
em_check_polarity(struct em_hw * hw,uint16_t * polarity)4762 em_check_polarity(struct em_hw *hw,
4763 uint16_t *polarity)
4764 {
4765 int32_t ret_val;
4766 uint16_t phy_data;
4767
4768 DEBUGFUNC("em_check_polarity");
4769
4770 if(hw->phy_type == em_phy_m88) {
4771 /* return the Polarity bit in the Status register. */
4772 if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
4773 &phy_data)))
4774 return ret_val;
4775 *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >>
4776 M88E1000_PSSR_REV_POLARITY_SHIFT;
4777 } else if(hw->phy_type == em_phy_igp) {
4778 /* Read the Status register to check the speed */
4779 if((ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
4780 &phy_data)))
4781 return ret_val;
4782
4783 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
4784 * find the polarity status */
4785 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
4786 IGP01E1000_PSSR_SPEED_1000MBPS) {
4787
4788 /* Read the GIG initialization PCS register (0x00B4) */
4789 if((ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
4790 &phy_data)))
4791 return ret_val;
4792
4793 /* Check the polarity bits */
4794 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? 1 : 0;
4795 } else {
4796 /* For 10 Mbps, read the polarity bit in the status register. (for
4797 * 100 Mbps this bit is always 0) */
4798 *polarity = phy_data & IGP01E1000_PSSR_POLARITY_REVERSED;
4799 }
4800 }
4801 return E1000_SUCCESS;
4802 }
4803
4804 /******************************************************************************
4805 * Check if Downshift occured
4806 *
4807 * hw - Struct containing variables accessed by shared code
4808 * downshift - output parameter : 0 - No Downshift ocured.
4809 * 1 - Downshift ocured.
4810 *
4811 * returns: - E1000_ERR_XXX
4812 * E1000_SUCCESS
4813 *
4814 * For phy's older then IGP, this function reads the Downshift bit in the Phy
4815 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the
4816 * Link Health register. In IGP this bit is latched high, so the driver must
4817 * read it immediately after link is established.
4818 *****************************************************************************/
4819 int32_t
em_check_downshift(struct em_hw * hw)4820 em_check_downshift(struct em_hw *hw)
4821 {
4822 int32_t ret_val;
4823 uint16_t phy_data;
4824
4825 DEBUGFUNC("em_check_downshift");
4826
4827 if(hw->phy_type == em_phy_igp) {
4828 if((ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
4829 &phy_data)))
4830 return ret_val;
4831
4832 hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
4833 }
4834 else if(hw->phy_type == em_phy_m88) {
4835 if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
4836 &phy_data)))
4837 return ret_val;
4838
4839 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
4840 M88E1000_PSSR_DOWNSHIFT_SHIFT;
4841 }
4842 return E1000_SUCCESS;
4843 }
4844
4845 /*****************************************************************************
4846 *
4847 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
4848 * gigabit link is achieved to improve link quality.
4849 *
4850 * hw: Struct containing variables accessed by shared code
4851 *
4852 * returns: - E1000_ERR_PHY if fail to read/write the PHY
4853 * E1000_SUCCESS at any other case.
4854 *
4855 ****************************************************************************/
4856
4857 int32_t
em_config_dsp_after_link_change(struct em_hw * hw,boolean_t link_up)4858 em_config_dsp_after_link_change(struct em_hw *hw,
4859 boolean_t link_up)
4860 {
4861 int32_t ret_val;
4862 uint16_t phy_data, speed, duplex, i;
4863 uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
4864 {IGP01E1000_PHY_AGC_PARAM_A,
4865 IGP01E1000_PHY_AGC_PARAM_B,
4866 IGP01E1000_PHY_AGC_PARAM_C,
4867 IGP01E1000_PHY_AGC_PARAM_D};
4868 uint16_t min_length, max_length;
4869
4870 DEBUGFUNC("em_config_dsp_after_link_change");
4871
4872 if(hw->phy_type != em_phy_igp)
4873 return E1000_SUCCESS;
4874
4875 if(link_up) {
4876 if((ret_val = em_get_speed_and_duplex(hw, &speed, &duplex))) {
4877 DEBUGOUT("Error getting link speed and duplex\n");
4878 return ret_val;
4879 }
4880
4881 if(speed == SPEED_1000) {
4882
4883 em_get_cable_length(hw, &min_length, &max_length);
4884
4885 if((hw->dsp_config_state == em_dsp_config_enabled) &&
4886 min_length >= em_igp_cable_length_50) {
4887
4888 for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
4889 if((ret_val = em_read_phy_reg(hw, dsp_reg_array[i],
4890 &phy_data)))
4891 return ret_val;
4892
4893 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
4894
4895 if((ret_val = em_write_phy_reg(hw, dsp_reg_array[i],
4896 phy_data)))
4897 return ret_val;
4898 }
4899 hw->dsp_config_state = em_dsp_config_activated;
4900 }
4901
4902 if((hw->ffe_config_state == em_ffe_config_enabled) &&
4903 (min_length < em_igp_cable_length_50)) {
4904
4905 uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
4906 uint32_t idle_errs = 0;
4907
4908 /* clear previous idle error counts */
4909 if((ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS,
4910 &phy_data)))
4911 return ret_val;
4912
4913 for(i = 0; i < ffe_idle_err_timeout; i++) {
4914 usec_delay(1000);
4915 if((ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS,
4916 &phy_data)))
4917 return ret_val;
4918
4919 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
4920 if(idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
4921 hw->ffe_config_state = em_ffe_config_active;
4922
4923 if((ret_val = em_write_phy_reg(hw,
4924 IGP01E1000_PHY_DSP_FFE,
4925 IGP01E1000_PHY_DSP_FFE_CM_CP)))
4926 return ret_val;
4927 break;
4928 }
4929
4930 if(idle_errs)
4931 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100;
4932 }
4933 }
4934 }
4935 } else {
4936 if(hw->dsp_config_state == em_dsp_config_activated) {
4937 if((ret_val = em_write_phy_reg(hw, 0x0000,
4938 IGP01E1000_IEEE_FORCE_GIGA)))
4939 return ret_val;
4940 for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
4941 if((ret_val = em_read_phy_reg(hw, dsp_reg_array[i],
4942 &phy_data)))
4943 return ret_val;
4944
4945 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
4946 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
4947
4948 if((ret_val = em_write_phy_reg(hw,dsp_reg_array[i],
4949 phy_data)))
4950 return ret_val;
4951 }
4952
4953 if((ret_val = em_write_phy_reg(hw, 0x0000,
4954 IGP01E1000_IEEE_RESTART_AUTONEG)))
4955 return ret_val;
4956
4957 hw->dsp_config_state = em_dsp_config_enabled;
4958 }
4959
4960 if(hw->ffe_config_state == em_ffe_config_active) {
4961 if((ret_val = em_write_phy_reg(hw, 0x0000,
4962 IGP01E1000_IEEE_FORCE_GIGA)))
4963 return ret_val;
4964 if((ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
4965 IGP01E1000_PHY_DSP_FFE_DEFAULT)))
4966 return ret_val;
4967
4968 if((ret_val = em_write_phy_reg(hw, 0x0000,
4969 IGP01E1000_IEEE_RESTART_AUTONEG)))
4970 return ret_val;
4971 hw->ffe_config_state = em_ffe_config_enabled;
4972 }
4973 }
4974 return E1000_SUCCESS;
4975 }
4976
4977 /*****************************************************************************
4978 *
4979 * This function sets the lplu state according to the active flag. When
4980 * activating lplu this function also disables smart speed and vise versa.
4981 * lplu will not be activated unless the device autonegotiation advertisment
4982 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
4983 * hw: Struct containing variables accessed by shared code
4984 * active - true to enable lplu false to disable lplu.
4985 *
4986 * returns: - E1000_ERR_PHY if fail to read/write the PHY
4987 * E1000_SUCCESS at any other case.
4988 *
4989 ****************************************************************************/
4990
4991 int32_t
em_set_d3_lplu_state(struct em_hw * hw,boolean_t active)4992 em_set_d3_lplu_state(struct em_hw *hw,
4993 boolean_t active)
4994 {
4995 int32_t ret_val;
4996 uint16_t phy_data;
4997 DEBUGFUNC("em_set_d3_lplu_state");
4998
4999 if(!((hw->mac_type == em_82541_rev_2) ||
5000 (hw->mac_type == em_82547_rev_2)))
5001 return E1000_SUCCESS;
5002
5003 /* During driver activity LPLU should not be used or it will attain link
5004 * from the lowest speeds starting from 10Mbps. The capability is used for
5005 * Dx transitions and states */
5006 if((ret_val = em_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data)))
5007 return ret_val;
5008
5009 if(!active) {
5010 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
5011 if((ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data)))
5012 return ret_val;
5013
5014 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
5015 * Dx states where the power conservation is most important. During
5016 * driver activity we should enable SmartSpeed, so performance is
5017 * maintained. */
5018 if((ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5019 &phy_data)))
5020 return ret_val;
5021
5022 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
5023 if((ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5024 phy_data)))
5025 return ret_val;
5026
5027 } else if((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
5028 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) ||
5029 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
5030
5031 phy_data |= IGP01E1000_GMII_FLEX_SPD;
5032 if((ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data)))
5033 return ret_val;
5034
5035 /* When LPLU is enabled we should disable SmartSpeed */
5036 if((ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5037 &phy_data)))
5038 return ret_val;
5039
5040 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5041 if((ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5042 phy_data)))
5043 return ret_val;
5044
5045 }
5046 return E1000_SUCCESS;
5047 }
5048
5049 /******************************************************************************
5050 * Change VCO speed register to improve Bit Error Rate performance of SERDES.
5051 *
5052 * hw - Struct containing variables accessed by shared code
5053 *****************************************************************************/
5054 static int32_t
em_set_vco_speed(struct em_hw * hw)5055 em_set_vco_speed(struct em_hw *hw)
5056 {
5057 int32_t ret_val;
5058 uint16_t default_page = 0;
5059 uint16_t phy_data;
5060
5061 DEBUGFUNC("em_set_vco_speed");
5062
5063 switch(hw->mac_type) {
5064 case em_82545_rev_3:
5065 case em_82546_rev_3:
5066 break;
5067 default:
5068 return E1000_SUCCESS;
5069 }
5070
5071 /* Set PHY register 30, page 5, bit 8 to 0 */
5072
5073 if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT,
5074 &default_page)))
5075 return ret_val;
5076
5077 if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005)))
5078 return ret_val;
5079
5080 if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data)))
5081 return ret_val;
5082
5083 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
5084 if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data)))
5085 return ret_val;
5086
5087 /* Set PHY register 30, page 4, bit 11 to 1 */
5088
5089 if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004)))
5090 return ret_val;
5091
5092 if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data)))
5093 return ret_val;
5094
5095 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
5096 if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data)))
5097 return ret_val;
5098
5099 if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT,
5100 default_page)))
5101 return ret_val;
5102
5103 return E1000_SUCCESS;
5104 }
5105
5106