1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987-2022 Free Software Foundation, Inc.
3
4 This file is part of GCC.
5
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
10
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
19
20 #include "config.h"
21 #include "system.h"
22 #include "coretypes.h"
23 #include "backend.h"
24 #include "target.h"
25 #include "rtl.h"
26 #include "tree.h"
27 #include "predict.h"
28 #include "df.h"
29 #include "memmodel.h"
30 #include "tm_p.h"
31 #include "optabs.h"
32 #include "regs.h"
33 #include "ira.h"
34 #include "recog.h"
35
36 #include "rtl-error.h"
37 #include "expr.h"
38 #include "addresses.h"
39 #include "cfgrtl.h"
40 #include "cfgbuild.h"
41 #include "reload.h"
42 #include "except.h"
43 #include "dumpfile.h"
44 #include "rtl-iter.h"
45 #include "function-abi.h"
46
47 /* This file contains the reload pass of the compiler, which is
48 run after register allocation has been done. It checks that
49 each insn is valid (operands required to be in registers really
50 are in registers of the proper class) and fixes up invalid ones
51 by copying values temporarily into registers for the insns
52 that need them.
53
54 The results of register allocation are described by the vector
55 reg_renumber; the insns still contain pseudo regs, but reg_renumber
56 can be used to find which hard reg, if any, a pseudo reg is in.
57
58 The technique we always use is to free up a few hard regs that are
59 called ``reload regs'', and for each place where a pseudo reg
60 must be in a hard reg, copy it temporarily into one of the reload regs.
61
62 Reload regs are allocated locally for every instruction that needs
63 reloads. When there are pseudos which are allocated to a register that
64 has been chosen as a reload reg, such pseudos must be ``spilled''.
65 This means that they go to other hard regs, or to stack slots if no other
66 available hard regs can be found. Spilling can invalidate more
67 insns, requiring additional need for reloads, so we must keep checking
68 until the process stabilizes.
69
70 For machines with different classes of registers, we must keep track
71 of the register class needed for each reload, and make sure that
72 we allocate enough reload registers of each class.
73
74 The file reload.cc contains the code that checks one insn for
75 validity and reports the reloads that it needs. This file
76 is in charge of scanning the entire rtl code, accumulating the
77 reload needs, spilling, assigning reload registers to use for
78 fixing up each insn, and generating the new insns to copy values
79 into the reload registers. */
80
81 struct target_reload default_target_reload;
82 #if SWITCHABLE_TARGET
83 struct target_reload *this_target_reload = &default_target_reload;
84 #endif
85
86 #define spill_indirect_levels \
87 (this_target_reload->x_spill_indirect_levels)
88
89 /* During reload_as_needed, element N contains a REG rtx for the hard reg
90 into which reg N has been reloaded (perhaps for a previous insn). */
91 static rtx *reg_last_reload_reg;
92
93 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
94 for an output reload that stores into reg N. */
95 static regset_head reg_has_output_reload;
96
97 /* Indicates which hard regs are reload-registers for an output reload
98 in the current insn. */
99 static HARD_REG_SET reg_is_output_reload;
100
101 /* Widest mode in which each pseudo reg is referred to (via subreg). */
102 static machine_mode *reg_max_ref_mode;
103
104 /* Vector to remember old contents of reg_renumber before spilling. */
105 static short *reg_old_renumber;
106
107 /* During reload_as_needed, element N contains the last pseudo regno reloaded
108 into hard register N. If that pseudo reg occupied more than one register,
109 reg_reloaded_contents points to that pseudo for each spill register in
110 use; all of these must remain set for an inheritance to occur. */
111 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
112
113 /* During reload_as_needed, element N contains the insn for which
114 hard register N was last used. Its contents are significant only
115 when reg_reloaded_valid is set for this register. */
116 static rtx_insn *reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
117
118 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
119 static HARD_REG_SET reg_reloaded_valid;
120 /* Indicate if the register was dead at the end of the reload.
121 This is only valid if reg_reloaded_contents is set and valid. */
122 static HARD_REG_SET reg_reloaded_dead;
123
124 /* Number of spill-regs so far; number of valid elements of spill_regs. */
125 static int n_spills;
126
127 /* In parallel with spill_regs, contains REG rtx's for those regs.
128 Holds the last rtx used for any given reg, or 0 if it has never
129 been used for spilling yet. This rtx is reused, provided it has
130 the proper mode. */
131 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
132
133 /* In parallel with spill_regs, contains nonzero for a spill reg
134 that was stored after the last time it was used.
135 The precise value is the insn generated to do the store. */
136 static rtx_insn *spill_reg_store[FIRST_PSEUDO_REGISTER];
137
138 /* This is the register that was stored with spill_reg_store. This is a
139 copy of reload_out / reload_out_reg when the value was stored; if
140 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
141 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
142
143 /* This table is the inverse mapping of spill_regs:
144 indexed by hard reg number,
145 it contains the position of that reg in spill_regs,
146 or -1 for something that is not in spill_regs.
147
148 ?!? This is no longer accurate. */
149 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
150
151 /* This reg set indicates registers that can't be used as spill registers for
152 the currently processed insn. These are the hard registers which are live
153 during the insn, but not allocated to pseudos, as well as fixed
154 registers. */
155 static HARD_REG_SET bad_spill_regs;
156
157 /* These are the hard registers that can't be used as spill register for any
158 insn. This includes registers used for user variables and registers that
159 we can't eliminate. A register that appears in this set also can't be used
160 to retry register allocation. */
161 static HARD_REG_SET bad_spill_regs_global;
162
163 /* Describes order of use of registers for reloading
164 of spilled pseudo-registers. `n_spills' is the number of
165 elements that are actually valid; new ones are added at the end.
166
167 Both spill_regs and spill_reg_order are used on two occasions:
168 once during find_reload_regs, where they keep track of the spill registers
169 for a single insn, but also during reload_as_needed where they show all
170 the registers ever used by reload. For the latter case, the information
171 is calculated during finish_spills. */
172 static short spill_regs[FIRST_PSEUDO_REGISTER];
173
174 /* This vector of reg sets indicates, for each pseudo, which hard registers
175 may not be used for retrying global allocation because the register was
176 formerly spilled from one of them. If we allowed reallocating a pseudo to
177 a register that it was already allocated to, reload might not
178 terminate. */
179 static HARD_REG_SET *pseudo_previous_regs;
180
181 /* This vector of reg sets indicates, for each pseudo, which hard
182 registers may not be used for retrying global allocation because they
183 are used as spill registers during one of the insns in which the
184 pseudo is live. */
185 static HARD_REG_SET *pseudo_forbidden_regs;
186
187 /* All hard regs that have been used as spill registers for any insn are
188 marked in this set. */
189 static HARD_REG_SET used_spill_regs;
190
191 /* Index of last register assigned as a spill register. We allocate in
192 a round-robin fashion. */
193 static int last_spill_reg;
194
195 /* Record the stack slot for each spilled hard register. */
196 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
197
198 /* Width allocated so far for that stack slot. */
199 static poly_uint64_pod spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
200
201 /* Record which pseudos needed to be spilled. */
202 static regset_head spilled_pseudos;
203
204 /* Record which pseudos changed their allocation in finish_spills. */
205 static regset_head changed_allocation_pseudos;
206
207 /* Used for communication between order_regs_for_reload and count_pseudo.
208 Used to avoid counting one pseudo twice. */
209 static regset_head pseudos_counted;
210
211 /* First uid used by insns created by reload in this function.
212 Used in find_equiv_reg. */
213 int reload_first_uid;
214
215 /* Flag set by local-alloc or global-alloc if anything is live in
216 a call-clobbered reg across calls. */
217 int caller_save_needed;
218
219 /* Set to 1 while reload_as_needed is operating.
220 Required by some machines to handle any generated moves differently. */
221 int reload_in_progress = 0;
222
223 /* This obstack is used for allocation of rtl during register elimination.
224 The allocated storage can be freed once find_reloads has processed the
225 insn. */
226 static struct obstack reload_obstack;
227
228 /* Points to the beginning of the reload_obstack. All insn_chain structures
229 are allocated first. */
230 static char *reload_startobj;
231
232 /* The point after all insn_chain structures. Used to quickly deallocate
233 memory allocated in copy_reloads during calculate_needs_all_insns. */
234 static char *reload_firstobj;
235
236 /* This points before all local rtl generated by register elimination.
237 Used to quickly free all memory after processing one insn. */
238 static char *reload_insn_firstobj;
239
240 /* List of insn_chain instructions, one for every insn that reload needs to
241 examine. */
242 class insn_chain *reload_insn_chain;
243
244 /* TRUE if we potentially left dead insns in the insn stream and want to
245 run DCE immediately after reload, FALSE otherwise. */
246 static bool need_dce;
247
248 /* List of all insns needing reloads. */
249 static class insn_chain *insns_need_reload;
250
251 /* This structure is used to record information about register eliminations.
252 Each array entry describes one possible way of eliminating a register
253 in favor of another. If there is more than one way of eliminating a
254 particular register, the most preferred should be specified first. */
255
256 struct elim_table
257 {
258 int from; /* Register number to be eliminated. */
259 int to; /* Register number used as replacement. */
260 poly_int64_pod initial_offset; /* Initial difference between values. */
261 int can_eliminate; /* Nonzero if this elimination can be done. */
262 int can_eliminate_previous; /* Value returned by TARGET_CAN_ELIMINATE
263 target hook in previous scan over insns
264 made by reload. */
265 poly_int64_pod offset; /* Current offset between the two regs. */
266 poly_int64_pod previous_offset; /* Offset at end of previous insn. */
267 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
268 rtx from_rtx; /* REG rtx for the register to be eliminated.
269 We cannot simply compare the number since
270 we might then spuriously replace a hard
271 register corresponding to a pseudo
272 assigned to the reg to be eliminated. */
273 rtx to_rtx; /* REG rtx for the replacement. */
274 };
275
276 static struct elim_table *reg_eliminate = 0;
277
278 /* This is an intermediate structure to initialize the table. It has
279 exactly the members provided by ELIMINABLE_REGS. */
280 static const struct elim_table_1
281 {
282 const int from;
283 const int to;
284 } reg_eliminate_1[] =
285
286 ELIMINABLE_REGS;
287
288 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
289
290 /* Record the number of pending eliminations that have an offset not equal
291 to their initial offset. If nonzero, we use a new copy of each
292 replacement result in any insns encountered. */
293 int num_not_at_initial_offset;
294
295 /* Count the number of registers that we may be able to eliminate. */
296 static int num_eliminable;
297 /* And the number of registers that are equivalent to a constant that
298 can be eliminated to frame_pointer / arg_pointer + constant. */
299 static int num_eliminable_invariants;
300
301 /* For each label, we record the offset of each elimination. If we reach
302 a label by more than one path and an offset differs, we cannot do the
303 elimination. This information is indexed by the difference of the
304 number of the label and the first label number. We can't offset the
305 pointer itself as this can cause problems on machines with segmented
306 memory. The first table is an array of flags that records whether we
307 have yet encountered a label and the second table is an array of arrays,
308 one entry in the latter array for each elimination. */
309
310 static int first_label_num;
311 static char *offsets_known_at;
312 static poly_int64_pod (*offsets_at)[NUM_ELIMINABLE_REGS];
313
314 vec<reg_equivs_t, va_gc> *reg_equivs;
315
316 /* Stack of addresses where an rtx has been changed. We can undo the
317 changes by popping items off the stack and restoring the original
318 value at each location.
319
320 We use this simplistic undo capability rather than copy_rtx as copy_rtx
321 will not make a deep copy of a normally sharable rtx, such as
322 (const (plus (symbol_ref) (const_int))). If such an expression appears
323 as R1 in gen_reload_chain_without_interm_reg_p, then a shared
324 rtx expression would be changed. See PR 42431. */
325
326 typedef rtx *rtx_p;
327 static vec<rtx_p> substitute_stack;
328
329 /* Number of labels in the current function. */
330
331 static int num_labels;
332
333 static void replace_pseudos_in (rtx *, machine_mode, rtx);
334 static void maybe_fix_stack_asms (void);
335 static void copy_reloads (class insn_chain *);
336 static void calculate_needs_all_insns (int);
337 static int find_reg (class insn_chain *, int);
338 static void find_reload_regs (class insn_chain *);
339 static void select_reload_regs (void);
340 static void delete_caller_save_insns (void);
341
342 static void spill_failure (rtx_insn *, enum reg_class);
343 static void count_spilled_pseudo (int, int, int);
344 static void delete_dead_insn (rtx_insn *);
345 static void alter_reg (int, int, bool);
346 static void set_label_offsets (rtx, rtx_insn *, int);
347 static void check_eliminable_occurrences (rtx);
348 static void elimination_effects (rtx, machine_mode);
349 static rtx eliminate_regs_1 (rtx, machine_mode, rtx, bool, bool);
350 static int eliminate_regs_in_insn (rtx_insn *, int);
351 static void update_eliminable_offsets (void);
352 static void mark_not_eliminable (rtx, const_rtx, void *);
353 static void set_initial_elim_offsets (void);
354 static bool verify_initial_elim_offsets (void);
355 static void set_initial_label_offsets (void);
356 static void set_offsets_for_label (rtx_insn *);
357 static void init_eliminable_invariants (rtx_insn *, bool);
358 static void init_elim_table (void);
359 static void free_reg_equiv (void);
360 static void update_eliminables (HARD_REG_SET *);
361 static bool update_eliminables_and_spill (void);
362 static void elimination_costs_in_insn (rtx_insn *);
363 static void spill_hard_reg (unsigned int, int);
364 static int finish_spills (int);
365 static void scan_paradoxical_subregs (rtx);
366 static void count_pseudo (int);
367 static void order_regs_for_reload (class insn_chain *);
368 static void reload_as_needed (int);
369 static void forget_old_reloads_1 (rtx, const_rtx, void *);
370 static void forget_marked_reloads (regset);
371 static int reload_reg_class_lower (const void *, const void *);
372 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
373 machine_mode);
374 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
375 machine_mode);
376 static int reload_reg_free_p (unsigned int, int, enum reload_type);
377 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
378 rtx, rtx, int, int);
379 static int free_for_value_p (int, machine_mode, int, enum reload_type,
380 rtx, rtx, int, int);
381 static int allocate_reload_reg (class insn_chain *, int, int);
382 static int conflicts_with_override (rtx);
383 static void failed_reload (rtx_insn *, int);
384 static int set_reload_reg (int, int);
385 static void choose_reload_regs_init (class insn_chain *, rtx *);
386 static void choose_reload_regs (class insn_chain *);
387 static void emit_input_reload_insns (class insn_chain *, struct reload *,
388 rtx, int);
389 static void emit_output_reload_insns (class insn_chain *, struct reload *,
390 int);
391 static void do_input_reload (class insn_chain *, struct reload *, int);
392 static void do_output_reload (class insn_chain *, struct reload *, int);
393 static void emit_reload_insns (class insn_chain *);
394 static void delete_output_reload (rtx_insn *, int, int, rtx);
395 static void delete_address_reloads (rtx_insn *, rtx_insn *);
396 static void delete_address_reloads_1 (rtx_insn *, rtx, rtx_insn *);
397 static void inc_for_reload (rtx, rtx, rtx, poly_int64);
398 static void substitute (rtx *, const_rtx, rtx);
399 static bool gen_reload_chain_without_interm_reg_p (int, int);
400 static int reloads_conflict (int, int);
401 static rtx_insn *gen_reload (rtx, rtx, int, enum reload_type);
402 static rtx_insn *emit_insn_if_valid_for_reload (rtx);
403
404 /* Initialize the reload pass. This is called at the beginning of compilation
405 and may be called again if the target is reinitialized. */
406
407 void
init_reload(void)408 init_reload (void)
409 {
410 int i;
411
412 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
413 Set spill_indirect_levels to the number of levels such addressing is
414 permitted, zero if it is not permitted at all. */
415
416 rtx tem
417 = gen_rtx_MEM (Pmode,
418 gen_rtx_PLUS (Pmode,
419 gen_rtx_REG (Pmode,
420 LAST_VIRTUAL_REGISTER + 1),
421 gen_int_mode (4, Pmode)));
422 spill_indirect_levels = 0;
423
424 while (memory_address_p (QImode, tem))
425 {
426 spill_indirect_levels++;
427 tem = gen_rtx_MEM (Pmode, tem);
428 }
429
430 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
431
432 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
433 indirect_symref_ok = memory_address_p (QImode, tem);
434
435 /* See if reg+reg is a valid (and offsettable) address. */
436
437 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
438 {
439 tem = gen_rtx_PLUS (Pmode,
440 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
441 gen_rtx_REG (Pmode, i));
442
443 /* This way, we make sure that reg+reg is an offsettable address. */
444 tem = plus_constant (Pmode, tem, 4);
445
446 for (int mode = 0; mode < MAX_MACHINE_MODE; mode++)
447 if (!double_reg_address_ok[mode]
448 && memory_address_p ((enum machine_mode)mode, tem))
449 double_reg_address_ok[mode] = 1;
450 }
451
452 /* Initialize obstack for our rtl allocation. */
453 if (reload_startobj == NULL)
454 {
455 gcc_obstack_init (&reload_obstack);
456 reload_startobj = XOBNEWVAR (&reload_obstack, char, 0);
457 }
458
459 INIT_REG_SET (&spilled_pseudos);
460 INIT_REG_SET (&changed_allocation_pseudos);
461 INIT_REG_SET (&pseudos_counted);
462 }
463
464 /* List of insn chains that are currently unused. */
465 static class insn_chain *unused_insn_chains = 0;
466
467 /* Allocate an empty insn_chain structure. */
468 class insn_chain *
new_insn_chain(void)469 new_insn_chain (void)
470 {
471 class insn_chain *c;
472
473 if (unused_insn_chains == 0)
474 {
475 c = XOBNEW (&reload_obstack, class insn_chain);
476 INIT_REG_SET (&c->live_throughout);
477 INIT_REG_SET (&c->dead_or_set);
478 }
479 else
480 {
481 c = unused_insn_chains;
482 unused_insn_chains = c->next;
483 }
484 c->is_caller_save_insn = 0;
485 c->need_operand_change = 0;
486 c->need_reload = 0;
487 c->need_elim = 0;
488 return c;
489 }
490
491 /* Small utility function to set all regs in hard reg set TO which are
492 allocated to pseudos in regset FROM. */
493
494 void
compute_use_by_pseudos(HARD_REG_SET * to,regset from)495 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
496 {
497 unsigned int regno;
498 reg_set_iterator rsi;
499
500 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
501 {
502 int r = reg_renumber[regno];
503
504 if (r < 0)
505 {
506 /* reload_combine uses the information from DF_LIVE_IN,
507 which might still contain registers that have not
508 actually been allocated since they have an
509 equivalence. */
510 gcc_assert (ira_conflicts_p || reload_completed);
511 }
512 else
513 add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r);
514 }
515 }
516
517 /* Replace all pseudos found in LOC with their corresponding
518 equivalences. */
519
520 static void
replace_pseudos_in(rtx * loc,machine_mode mem_mode,rtx usage)521 replace_pseudos_in (rtx *loc, machine_mode mem_mode, rtx usage)
522 {
523 rtx x = *loc;
524 enum rtx_code code;
525 const char *fmt;
526 int i, j;
527
528 if (! x)
529 return;
530
531 code = GET_CODE (x);
532 if (code == REG)
533 {
534 unsigned int regno = REGNO (x);
535
536 if (regno < FIRST_PSEUDO_REGISTER)
537 return;
538
539 x = eliminate_regs_1 (x, mem_mode, usage, true, false);
540 if (x != *loc)
541 {
542 *loc = x;
543 replace_pseudos_in (loc, mem_mode, usage);
544 return;
545 }
546
547 if (reg_equiv_constant (regno))
548 *loc = reg_equiv_constant (regno);
549 else if (reg_equiv_invariant (regno))
550 *loc = reg_equiv_invariant (regno);
551 else if (reg_equiv_mem (regno))
552 *loc = reg_equiv_mem (regno);
553 else if (reg_equiv_address (regno))
554 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address (regno));
555 else
556 {
557 gcc_assert (!REG_P (regno_reg_rtx[regno])
558 || REGNO (regno_reg_rtx[regno]) != regno);
559 *loc = regno_reg_rtx[regno];
560 }
561
562 return;
563 }
564 else if (code == MEM)
565 {
566 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
567 return;
568 }
569
570 /* Process each of our operands recursively. */
571 fmt = GET_RTX_FORMAT (code);
572 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
573 if (*fmt == 'e')
574 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
575 else if (*fmt == 'E')
576 for (j = 0; j < XVECLEN (x, i); j++)
577 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
578 }
579
580 /* Determine if the current function has an exception receiver block
581 that reaches the exit block via non-exceptional edges */
582
583 static bool
has_nonexceptional_receiver(void)584 has_nonexceptional_receiver (void)
585 {
586 edge e;
587 edge_iterator ei;
588 basic_block *tos, *worklist, bb;
589
590 /* If we're not optimizing, then just err on the safe side. */
591 if (!optimize)
592 return true;
593
594 /* First determine which blocks can reach exit via normal paths. */
595 tos = worklist = XNEWVEC (basic_block, n_basic_blocks_for_fn (cfun) + 1);
596
597 FOR_EACH_BB_FN (bb, cfun)
598 bb->flags &= ~BB_REACHABLE;
599
600 /* Place the exit block on our worklist. */
601 EXIT_BLOCK_PTR_FOR_FN (cfun)->flags |= BB_REACHABLE;
602 *tos++ = EXIT_BLOCK_PTR_FOR_FN (cfun);
603
604 /* Iterate: find everything reachable from what we've already seen. */
605 while (tos != worklist)
606 {
607 bb = *--tos;
608
609 FOR_EACH_EDGE (e, ei, bb->preds)
610 if (!(e->flags & EDGE_ABNORMAL))
611 {
612 basic_block src = e->src;
613
614 if (!(src->flags & BB_REACHABLE))
615 {
616 src->flags |= BB_REACHABLE;
617 *tos++ = src;
618 }
619 }
620 }
621 free (worklist);
622
623 /* Now see if there's a reachable block with an exceptional incoming
624 edge. */
625 FOR_EACH_BB_FN (bb, cfun)
626 if (bb->flags & BB_REACHABLE && bb_has_abnormal_pred (bb))
627 return true;
628
629 /* No exceptional block reached exit unexceptionally. */
630 return false;
631 }
632
633 /* Grow (or allocate) the REG_EQUIVS array from its current size (which may be
634 zero elements) to MAX_REG_NUM elements.
635
636 Initialize all new fields to NULL and update REG_EQUIVS_SIZE. */
637 void
grow_reg_equivs(void)638 grow_reg_equivs (void)
639 {
640 int old_size = vec_safe_length (reg_equivs);
641 int max_regno = max_reg_num ();
642 int i;
643 reg_equivs_t ze;
644
645 memset (&ze, 0, sizeof (reg_equivs_t));
646 vec_safe_reserve (reg_equivs, max_regno);
647 for (i = old_size; i < max_regno; i++)
648 reg_equivs->quick_insert (i, ze);
649 }
650
651
652 /* Global variables used by reload and its subroutines. */
653
654 /* The current basic block while in calculate_elim_costs_all_insns. */
655 static basic_block elim_bb;
656
657 /* Set during calculate_needs if an insn needs register elimination. */
658 static int something_needs_elimination;
659 /* Set during calculate_needs if an insn needs an operand changed. */
660 static int something_needs_operands_changed;
661 /* Set by alter_regs if we spilled a register to the stack. */
662 static bool something_was_spilled;
663
664 /* Nonzero means we couldn't get enough spill regs. */
665 static int failure;
666
667 /* Temporary array of pseudo-register number. */
668 static int *temp_pseudo_reg_arr;
669
670 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
671 If that insn didn't set the register (i.e., it copied the register to
672 memory), just delete that insn instead of the equivalencing insn plus
673 anything now dead. If we call delete_dead_insn on that insn, we may
674 delete the insn that actually sets the register if the register dies
675 there and that is incorrect. */
676 static void
remove_init_insns()677 remove_init_insns ()
678 {
679 for (int i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
680 {
681 if (reg_renumber[i] < 0 && reg_equiv_init (i) != 0)
682 {
683 rtx list;
684 for (list = reg_equiv_init (i); list; list = XEXP (list, 1))
685 {
686 rtx_insn *equiv_insn = as_a <rtx_insn *> (XEXP (list, 0));
687
688 /* If we already deleted the insn or if it may trap, we can't
689 delete it. The latter case shouldn't happen, but can
690 if an insn has a variable address, gets a REG_EH_REGION
691 note added to it, and then gets converted into a load
692 from a constant address. */
693 if (NOTE_P (equiv_insn)
694 || can_throw_internal (equiv_insn))
695 ;
696 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
697 delete_dead_insn (equiv_insn);
698 else
699 SET_INSN_DELETED (equiv_insn);
700 }
701 }
702 }
703 }
704
705 /* Return true if remove_init_insns will delete INSN. */
706 static bool
will_delete_init_insn_p(rtx_insn * insn)707 will_delete_init_insn_p (rtx_insn *insn)
708 {
709 rtx set = single_set (insn);
710 if (!set || !REG_P (SET_DEST (set)))
711 return false;
712 unsigned regno = REGNO (SET_DEST (set));
713
714 if (can_throw_internal (insn))
715 return false;
716
717 if (regno < FIRST_PSEUDO_REGISTER || reg_renumber[regno] >= 0)
718 return false;
719
720 for (rtx list = reg_equiv_init (regno); list; list = XEXP (list, 1))
721 {
722 rtx equiv_insn = XEXP (list, 0);
723 if (equiv_insn == insn)
724 return true;
725 }
726 return false;
727 }
728
729 /* Main entry point for the reload pass.
730
731 FIRST is the first insn of the function being compiled.
732
733 GLOBAL nonzero means we were called from global_alloc
734 and should attempt to reallocate any pseudoregs that we
735 displace from hard regs we will use for reloads.
736 If GLOBAL is zero, we do not have enough information to do that,
737 so any pseudo reg that is spilled must go to the stack.
738
739 Return value is TRUE if reload likely left dead insns in the
740 stream and a DCE pass should be run to elimiante them. Else the
741 return value is FALSE. */
742
743 bool
reload(rtx_insn * first,int global)744 reload (rtx_insn *first, int global)
745 {
746 int i, n;
747 rtx_insn *insn;
748 struct elim_table *ep;
749 basic_block bb;
750 bool inserted;
751
752 /* Make sure even insns with volatile mem refs are recognizable. */
753 init_recog ();
754
755 failure = 0;
756
757 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
758
759 /* Make sure that the last insn in the chain
760 is not something that needs reloading. */
761 emit_note (NOTE_INSN_DELETED);
762
763 /* Enable find_equiv_reg to distinguish insns made by reload. */
764 reload_first_uid = get_max_uid ();
765
766 /* Initialize the secondary memory table. */
767 clear_secondary_mem ();
768
769 /* We don't have a stack slot for any spill reg yet. */
770 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
771 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
772
773 /* Initialize the save area information for caller-save, in case some
774 are needed. */
775 init_save_areas ();
776
777 /* Compute which hard registers are now in use
778 as homes for pseudo registers.
779 This is done here rather than (eg) in global_alloc
780 because this point is reached even if not optimizing. */
781 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
782 mark_home_live (i);
783
784 /* A function that has a nonlocal label that can reach the exit
785 block via non-exceptional paths must save all call-saved
786 registers. */
787 if (cfun->has_nonlocal_label
788 && has_nonexceptional_receiver ())
789 crtl->saves_all_registers = 1;
790
791 if (crtl->saves_all_registers)
792 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
793 if (! crtl->abi->clobbers_full_reg_p (i)
794 && ! fixed_regs[i]
795 && ! LOCAL_REGNO (i))
796 df_set_regs_ever_live (i, true);
797
798 /* Find all the pseudo registers that didn't get hard regs
799 but do have known equivalent constants or memory slots.
800 These include parameters (known equivalent to parameter slots)
801 and cse'd or loop-moved constant memory addresses.
802
803 Record constant equivalents in reg_equiv_constant
804 so they will be substituted by find_reloads.
805 Record memory equivalents in reg_mem_equiv so they can
806 be substituted eventually by altering the REG-rtx's. */
807
808 grow_reg_equivs ();
809 reg_old_renumber = XCNEWVEC (short, max_regno);
810 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
811 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
812 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
813
814 CLEAR_HARD_REG_SET (bad_spill_regs_global);
815
816 init_eliminable_invariants (first, true);
817 init_elim_table ();
818
819 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
820 stack slots to the pseudos that lack hard regs or equivalents.
821 Do not touch virtual registers. */
822
823 temp_pseudo_reg_arr = XNEWVEC (int, max_regno - LAST_VIRTUAL_REGISTER - 1);
824 for (n = 0, i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
825 temp_pseudo_reg_arr[n++] = i;
826
827 if (ira_conflicts_p)
828 /* Ask IRA to order pseudo-registers for better stack slot
829 sharing. */
830 ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr, n, reg_max_ref_mode);
831
832 for (i = 0; i < n; i++)
833 alter_reg (temp_pseudo_reg_arr[i], -1, false);
834
835 /* If we have some registers we think can be eliminated, scan all insns to
836 see if there is an insn that sets one of these registers to something
837 other than itself plus a constant. If so, the register cannot be
838 eliminated. Doing this scan here eliminates an extra pass through the
839 main reload loop in the most common case where register elimination
840 cannot be done. */
841 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
842 if (INSN_P (insn))
843 note_pattern_stores (PATTERN (insn), mark_not_eliminable, NULL);
844
845 maybe_fix_stack_asms ();
846
847 insns_need_reload = 0;
848 something_needs_elimination = 0;
849
850 /* Initialize to -1, which means take the first spill register. */
851 last_spill_reg = -1;
852
853 /* Spill any hard regs that we know we can't eliminate. */
854 CLEAR_HARD_REG_SET (used_spill_regs);
855 /* There can be multiple ways to eliminate a register;
856 they should be listed adjacently.
857 Elimination for any register fails only if all possible ways fail. */
858 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
859 {
860 int from = ep->from;
861 int can_eliminate = 0;
862 do
863 {
864 can_eliminate |= ep->can_eliminate;
865 ep++;
866 }
867 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
868 if (! can_eliminate)
869 spill_hard_reg (from, 1);
870 }
871
872 if (!HARD_FRAME_POINTER_IS_FRAME_POINTER && frame_pointer_needed)
873 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
874
875 finish_spills (global);
876
877 /* From now on, we may need to generate moves differently. We may also
878 allow modifications of insns which cause them to not be recognized.
879 Any such modifications will be cleaned up during reload itself. */
880 reload_in_progress = 1;
881
882 /* This loop scans the entire function each go-round
883 and repeats until one repetition spills no additional hard regs. */
884 for (;;)
885 {
886 int something_changed;
887 poly_int64 starting_frame_size;
888
889 starting_frame_size = get_frame_size ();
890 something_was_spilled = false;
891
892 set_initial_elim_offsets ();
893 set_initial_label_offsets ();
894
895 /* For each pseudo register that has an equivalent location defined,
896 try to eliminate any eliminable registers (such as the frame pointer)
897 assuming initial offsets for the replacement register, which
898 is the normal case.
899
900 If the resulting location is directly addressable, substitute
901 the MEM we just got directly for the old REG.
902
903 If it is not addressable but is a constant or the sum of a hard reg
904 and constant, it is probably not addressable because the constant is
905 out of range, in that case record the address; we will generate
906 hairy code to compute the address in a register each time it is
907 needed. Similarly if it is a hard register, but one that is not
908 valid as an address register.
909
910 If the location is not addressable, but does not have one of the
911 above forms, assign a stack slot. We have to do this to avoid the
912 potential of producing lots of reloads if, e.g., a location involves
913 a pseudo that didn't get a hard register and has an equivalent memory
914 location that also involves a pseudo that didn't get a hard register.
915
916 Perhaps at some point we will improve reload_when_needed handling
917 so this problem goes away. But that's very hairy. */
918
919 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
920 if (reg_renumber[i] < 0 && reg_equiv_memory_loc (i))
921 {
922 rtx x = eliminate_regs (reg_equiv_memory_loc (i), VOIDmode,
923 NULL_RTX);
924
925 if (strict_memory_address_addr_space_p
926 (GET_MODE (regno_reg_rtx[i]), XEXP (x, 0),
927 MEM_ADDR_SPACE (x)))
928 reg_equiv_mem (i) = x, reg_equiv_address (i) = 0;
929 else if (CONSTANT_P (XEXP (x, 0))
930 || (REG_P (XEXP (x, 0))
931 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
932 || (GET_CODE (XEXP (x, 0)) == PLUS
933 && REG_P (XEXP (XEXP (x, 0), 0))
934 && (REGNO (XEXP (XEXP (x, 0), 0))
935 < FIRST_PSEUDO_REGISTER)
936 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
937 reg_equiv_address (i) = XEXP (x, 0), reg_equiv_mem (i) = 0;
938 else
939 {
940 /* Make a new stack slot. Then indicate that something
941 changed so we go back and recompute offsets for
942 eliminable registers because the allocation of memory
943 below might change some offset. reg_equiv_{mem,address}
944 will be set up for this pseudo on the next pass around
945 the loop. */
946 reg_equiv_memory_loc (i) = 0;
947 reg_equiv_init (i) = 0;
948 alter_reg (i, -1, true);
949 }
950 }
951
952 if (caller_save_needed)
953 setup_save_areas ();
954
955 if (maybe_ne (starting_frame_size, 0) && crtl->stack_alignment_needed)
956 {
957 /* If we have a stack frame, we must align it now. The
958 stack size may be a part of the offset computation for
959 register elimination. So if this changes the stack size,
960 then repeat the elimination bookkeeping. We don't
961 realign when there is no stack, as that will cause a
962 stack frame when none is needed should
963 TARGET_STARTING_FRAME_OFFSET not be already aligned to
964 STACK_BOUNDARY. */
965 assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
966 }
967 /* If we allocated another stack slot, redo elimination bookkeeping. */
968 if (something_was_spilled
969 || maybe_ne (starting_frame_size, get_frame_size ()))
970 {
971 if (update_eliminables_and_spill ())
972 finish_spills (0);
973 continue;
974 }
975
976 if (caller_save_needed)
977 {
978 save_call_clobbered_regs ();
979 /* That might have allocated new insn_chain structures. */
980 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
981 }
982
983 calculate_needs_all_insns (global);
984
985 if (! ira_conflicts_p)
986 /* Don't do it for IRA. We need this info because we don't
987 change live_throughout and dead_or_set for chains when IRA
988 is used. */
989 CLEAR_REG_SET (&spilled_pseudos);
990
991 something_changed = 0;
992
993 /* If we allocated any new memory locations, make another pass
994 since it might have changed elimination offsets. */
995 if (something_was_spilled
996 || maybe_ne (starting_frame_size, get_frame_size ()))
997 something_changed = 1;
998
999 /* Even if the frame size remained the same, we might still have
1000 changed elimination offsets, e.g. if find_reloads called
1001 force_const_mem requiring the back end to allocate a constant
1002 pool base register that needs to be saved on the stack. */
1003 else if (!verify_initial_elim_offsets ())
1004 something_changed = 1;
1005
1006 if (update_eliminables_and_spill ())
1007 {
1008 finish_spills (0);
1009 something_changed = 1;
1010 }
1011 else
1012 {
1013 select_reload_regs ();
1014 if (failure)
1015 goto failed;
1016 if (insns_need_reload)
1017 something_changed |= finish_spills (global);
1018 }
1019
1020 if (! something_changed)
1021 break;
1022
1023 if (caller_save_needed)
1024 delete_caller_save_insns ();
1025
1026 obstack_free (&reload_obstack, reload_firstobj);
1027 }
1028
1029 /* If global-alloc was run, notify it of any register eliminations we have
1030 done. */
1031 if (global)
1032 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1033 if (ep->can_eliminate)
1034 mark_elimination (ep->from, ep->to);
1035
1036 remove_init_insns ();
1037
1038 /* Use the reload registers where necessary
1039 by generating move instructions to move the must-be-register
1040 values into or out of the reload registers. */
1041
1042 if (insns_need_reload != 0 || something_needs_elimination
1043 || something_needs_operands_changed)
1044 {
1045 poly_int64 old_frame_size = get_frame_size ();
1046
1047 reload_as_needed (global);
1048
1049 gcc_assert (known_eq (old_frame_size, get_frame_size ()));
1050
1051 gcc_assert (verify_initial_elim_offsets ());
1052 }
1053
1054 /* If we were able to eliminate the frame pointer, show that it is no
1055 longer live at the start of any basic block. If it ls live by
1056 virtue of being in a pseudo, that pseudo will be marked live
1057 and hence the frame pointer will be known to be live via that
1058 pseudo. */
1059
1060 if (! frame_pointer_needed)
1061 FOR_EACH_BB_FN (bb, cfun)
1062 bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM);
1063
1064 /* Come here (with failure set nonzero) if we can't get enough spill
1065 regs. */
1066 failed:
1067
1068 CLEAR_REG_SET (&changed_allocation_pseudos);
1069 CLEAR_REG_SET (&spilled_pseudos);
1070 reload_in_progress = 0;
1071
1072 /* Now eliminate all pseudo regs by modifying them into
1073 their equivalent memory references.
1074 The REG-rtx's for the pseudos are modified in place,
1075 so all insns that used to refer to them now refer to memory.
1076
1077 For a reg that has a reg_equiv_address, all those insns
1078 were changed by reloading so that no insns refer to it any longer;
1079 but the DECL_RTL of a variable decl may refer to it,
1080 and if so this causes the debugging info to mention the variable. */
1081
1082 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1083 {
1084 rtx addr = 0;
1085
1086 if (reg_equiv_mem (i))
1087 addr = XEXP (reg_equiv_mem (i), 0);
1088
1089 if (reg_equiv_address (i))
1090 addr = reg_equiv_address (i);
1091
1092 if (addr)
1093 {
1094 if (reg_renumber[i] < 0)
1095 {
1096 rtx reg = regno_reg_rtx[i];
1097
1098 REG_USERVAR_P (reg) = 0;
1099 PUT_CODE (reg, MEM);
1100 XEXP (reg, 0) = addr;
1101 if (reg_equiv_memory_loc (i))
1102 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc (i));
1103 else
1104 MEM_ATTRS (reg) = 0;
1105 MEM_NOTRAP_P (reg) = 1;
1106 }
1107 else if (reg_equiv_mem (i))
1108 XEXP (reg_equiv_mem (i), 0) = addr;
1109 }
1110
1111 /* We don't want complex addressing modes in debug insns
1112 if simpler ones will do, so delegitimize equivalences
1113 in debug insns. */
1114 if (MAY_HAVE_DEBUG_BIND_INSNS && reg_renumber[i] < 0)
1115 {
1116 rtx reg = regno_reg_rtx[i];
1117 rtx equiv = 0;
1118 df_ref use, next;
1119
1120 if (reg_equiv_constant (i))
1121 equiv = reg_equiv_constant (i);
1122 else if (reg_equiv_invariant (i))
1123 equiv = reg_equiv_invariant (i);
1124 else if (reg && MEM_P (reg))
1125 equiv = targetm.delegitimize_address (reg);
1126 else if (reg && REG_P (reg) && (int)REGNO (reg) != i)
1127 equiv = reg;
1128
1129 if (equiv == reg)
1130 continue;
1131
1132 for (use = DF_REG_USE_CHAIN (i); use; use = next)
1133 {
1134 insn = DF_REF_INSN (use);
1135
1136 /* Make sure the next ref is for a different instruction,
1137 so that we're not affected by the rescan. */
1138 next = DF_REF_NEXT_REG (use);
1139 while (next && DF_REF_INSN (next) == insn)
1140 next = DF_REF_NEXT_REG (next);
1141
1142 if (DEBUG_BIND_INSN_P (insn))
1143 {
1144 if (!equiv)
1145 {
1146 INSN_VAR_LOCATION_LOC (insn) = gen_rtx_UNKNOWN_VAR_LOC ();
1147 df_insn_rescan_debug_internal (insn);
1148 }
1149 else
1150 INSN_VAR_LOCATION_LOC (insn)
1151 = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn),
1152 reg, equiv);
1153 }
1154 }
1155 }
1156 }
1157
1158 /* We must set reload_completed now since the cleanup_subreg_operands call
1159 below will re-recognize each insn and reload may have generated insns
1160 which are only valid during and after reload. */
1161 reload_completed = 1;
1162
1163 /* Make a pass over all the insns and delete all USEs which we inserted
1164 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1165 notes. Delete all CLOBBER insns, except those that refer to the return
1166 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1167 from misarranging variable-array code, and simplify (subreg (reg))
1168 operands. Strip and regenerate REG_INC notes that may have been moved
1169 around. */
1170
1171 for (insn = first; insn; insn = NEXT_INSN (insn))
1172 if (INSN_P (insn))
1173 {
1174 rtx *pnote;
1175
1176 if (CALL_P (insn))
1177 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1178 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1179
1180 if ((GET_CODE (PATTERN (insn)) == USE
1181 /* We mark with QImode USEs introduced by reload itself. */
1182 && (GET_MODE (insn) == QImode
1183 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1184 || (GET_CODE (PATTERN (insn)) == CLOBBER
1185 && (!MEM_P (XEXP (PATTERN (insn), 0))
1186 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1187 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1188 && XEXP (XEXP (PATTERN (insn), 0), 0)
1189 != stack_pointer_rtx))
1190 && (!REG_P (XEXP (PATTERN (insn), 0))
1191 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1192 {
1193 delete_insn (insn);
1194 continue;
1195 }
1196
1197 /* Some CLOBBERs may survive until here and still reference unassigned
1198 pseudos with const equivalent, which may in turn cause ICE in later
1199 passes if the reference remains in place. */
1200 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1201 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1202 VOIDmode, PATTERN (insn));
1203
1204 /* Discard obvious no-ops, even without -O. This optimization
1205 is fast and doesn't interfere with debugging. */
1206 if (NONJUMP_INSN_P (insn)
1207 && GET_CODE (PATTERN (insn)) == SET
1208 && REG_P (SET_SRC (PATTERN (insn)))
1209 && REG_P (SET_DEST (PATTERN (insn)))
1210 && (REGNO (SET_SRC (PATTERN (insn)))
1211 == REGNO (SET_DEST (PATTERN (insn)))))
1212 {
1213 delete_insn (insn);
1214 continue;
1215 }
1216
1217 pnote = ®_NOTES (insn);
1218 while (*pnote != 0)
1219 {
1220 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1221 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1222 || REG_NOTE_KIND (*pnote) == REG_INC)
1223 *pnote = XEXP (*pnote, 1);
1224 else
1225 pnote = &XEXP (*pnote, 1);
1226 }
1227
1228 if (AUTO_INC_DEC)
1229 add_auto_inc_notes (insn, PATTERN (insn));
1230
1231 /* Simplify (subreg (reg)) if it appears as an operand. */
1232 cleanup_subreg_operands (insn);
1233
1234 /* Clean up invalid ASMs so that they don't confuse later passes.
1235 See PR 21299. */
1236 if (asm_noperands (PATTERN (insn)) >= 0)
1237 {
1238 extract_insn (insn);
1239 if (!constrain_operands (1, get_enabled_alternatives (insn)))
1240 {
1241 error_for_asm (insn,
1242 "%<asm%> operand has impossible constraints");
1243 delete_insn (insn);
1244 continue;
1245 }
1246 }
1247 }
1248
1249 free (temp_pseudo_reg_arr);
1250
1251 /* Indicate that we no longer have known memory locations or constants. */
1252 free_reg_equiv ();
1253
1254 free (reg_max_ref_mode);
1255 free (reg_old_renumber);
1256 free (pseudo_previous_regs);
1257 free (pseudo_forbidden_regs);
1258
1259 CLEAR_HARD_REG_SET (used_spill_regs);
1260 for (i = 0; i < n_spills; i++)
1261 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1262
1263 /* Free all the insn_chain structures at once. */
1264 obstack_free (&reload_obstack, reload_startobj);
1265 unused_insn_chains = 0;
1266
1267 inserted = fixup_abnormal_edges ();
1268
1269 /* We've possibly turned single trapping insn into multiple ones. */
1270 if (cfun->can_throw_non_call_exceptions)
1271 {
1272 auto_sbitmap blocks (last_basic_block_for_fn (cfun));
1273 bitmap_ones (blocks);
1274 find_many_sub_basic_blocks (blocks);
1275 }
1276
1277 if (inserted)
1278 commit_edge_insertions ();
1279
1280 /* Replacing pseudos with their memory equivalents might have
1281 created shared rtx. Subsequent passes would get confused
1282 by this, so unshare everything here. */
1283 unshare_all_rtl_again (first);
1284
1285 #ifdef STACK_BOUNDARY
1286 /* init_emit has set the alignment of the hard frame pointer
1287 to STACK_BOUNDARY. It is very likely no longer valid if
1288 the hard frame pointer was used for register allocation. */
1289 if (!frame_pointer_needed)
1290 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1291 #endif
1292
1293 substitute_stack.release ();
1294
1295 gcc_assert (bitmap_empty_p (&spilled_pseudos));
1296
1297 reload_completed = !failure;
1298
1299 return need_dce;
1300 }
1301
1302 /* Yet another special case. Unfortunately, reg-stack forces people to
1303 write incorrect clobbers in asm statements. These clobbers must not
1304 cause the register to appear in bad_spill_regs, otherwise we'll call
1305 fatal_insn later. We clear the corresponding regnos in the live
1306 register sets to avoid this.
1307 The whole thing is rather sick, I'm afraid. */
1308
1309 static void
maybe_fix_stack_asms(void)1310 maybe_fix_stack_asms (void)
1311 {
1312 #ifdef STACK_REGS
1313 const char *constraints[MAX_RECOG_OPERANDS];
1314 machine_mode operand_mode[MAX_RECOG_OPERANDS];
1315 class insn_chain *chain;
1316
1317 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1318 {
1319 int i, noperands;
1320 HARD_REG_SET clobbered, allowed;
1321 rtx pat;
1322
1323 if (! INSN_P (chain->insn)
1324 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1325 continue;
1326 pat = PATTERN (chain->insn);
1327 if (GET_CODE (pat) != PARALLEL)
1328 continue;
1329
1330 CLEAR_HARD_REG_SET (clobbered);
1331 CLEAR_HARD_REG_SET (allowed);
1332
1333 /* First, make a mask of all stack regs that are clobbered. */
1334 for (i = 0; i < XVECLEN (pat, 0); i++)
1335 {
1336 rtx t = XVECEXP (pat, 0, i);
1337 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1338 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1339 }
1340
1341 /* Get the operand values and constraints out of the insn. */
1342 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1343 constraints, operand_mode, NULL);
1344
1345 /* For every operand, see what registers are allowed. */
1346 for (i = 0; i < noperands; i++)
1347 {
1348 const char *p = constraints[i];
1349 /* For every alternative, we compute the class of registers allowed
1350 for reloading in CLS, and merge its contents into the reg set
1351 ALLOWED. */
1352 int cls = (int) NO_REGS;
1353
1354 for (;;)
1355 {
1356 char c = *p;
1357
1358 if (c == '\0' || c == ',' || c == '#')
1359 {
1360 /* End of one alternative - mark the regs in the current
1361 class, and reset the class. */
1362 allowed |= reg_class_contents[cls];
1363 cls = NO_REGS;
1364 p++;
1365 if (c == '#')
1366 do {
1367 c = *p++;
1368 } while (c != '\0' && c != ',');
1369 if (c == '\0')
1370 break;
1371 continue;
1372 }
1373
1374 switch (c)
1375 {
1376 case 'g':
1377 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1378 break;
1379
1380 default:
1381 enum constraint_num cn = lookup_constraint (p);
1382 if (insn_extra_address_constraint (cn))
1383 cls = (int) reg_class_subunion[cls]
1384 [(int) base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
1385 ADDRESS, SCRATCH)];
1386 else
1387 cls = (int) reg_class_subunion[cls]
1388 [reg_class_for_constraint (cn)];
1389 break;
1390 }
1391 p += CONSTRAINT_LEN (c, p);
1392 }
1393 }
1394 /* Those of the registers which are clobbered, but allowed by the
1395 constraints, must be usable as reload registers. So clear them
1396 out of the life information. */
1397 allowed &= clobbered;
1398 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1399 if (TEST_HARD_REG_BIT (allowed, i))
1400 {
1401 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1402 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1403 }
1404 }
1405
1406 #endif
1407 }
1408
1409 /* Copy the global variables n_reloads and rld into the corresponding elts
1410 of CHAIN. */
1411 static void
copy_reloads(class insn_chain * chain)1412 copy_reloads (class insn_chain *chain)
1413 {
1414 chain->n_reloads = n_reloads;
1415 chain->rld = XOBNEWVEC (&reload_obstack, struct reload, n_reloads);
1416 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1417 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1418 }
1419
1420 /* Walk the chain of insns, and determine for each whether it needs reloads
1421 and/or eliminations. Build the corresponding insns_need_reload list, and
1422 set something_needs_elimination as appropriate. */
1423 static void
calculate_needs_all_insns(int global)1424 calculate_needs_all_insns (int global)
1425 {
1426 class insn_chain **pprev_reload = &insns_need_reload;
1427 class insn_chain *chain, *next = 0;
1428
1429 something_needs_elimination = 0;
1430
1431 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1432 for (chain = reload_insn_chain; chain != 0; chain = next)
1433 {
1434 rtx_insn *insn = chain->insn;
1435
1436 next = chain->next;
1437
1438 /* Clear out the shortcuts. */
1439 chain->n_reloads = 0;
1440 chain->need_elim = 0;
1441 chain->need_reload = 0;
1442 chain->need_operand_change = 0;
1443
1444 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1445 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1446 what effects this has on the known offsets at labels. */
1447
1448 if (LABEL_P (insn) || JUMP_P (insn) || JUMP_TABLE_DATA_P (insn)
1449 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1450 set_label_offsets (insn, insn, 0);
1451
1452 if (INSN_P (insn))
1453 {
1454 rtx old_body = PATTERN (insn);
1455 int old_code = INSN_CODE (insn);
1456 rtx old_notes = REG_NOTES (insn);
1457 int did_elimination = 0;
1458 int operands_changed = 0;
1459
1460 /* Skip insns that only set an equivalence. */
1461 if (will_delete_init_insn_p (insn))
1462 continue;
1463
1464 /* If needed, eliminate any eliminable registers. */
1465 if (num_eliminable || num_eliminable_invariants)
1466 did_elimination = eliminate_regs_in_insn (insn, 0);
1467
1468 /* Analyze the instruction. */
1469 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1470 global, spill_reg_order);
1471
1472 /* If a no-op set needs more than one reload, this is likely
1473 to be something that needs input address reloads. We
1474 can't get rid of this cleanly later, and it is of no use
1475 anyway, so discard it now.
1476 We only do this when expensive_optimizations is enabled,
1477 since this complements reload inheritance / output
1478 reload deletion, and it can make debugging harder. */
1479 if (flag_expensive_optimizations && n_reloads > 1)
1480 {
1481 rtx set = single_set (insn);
1482 if (set
1483 &&
1484 ((SET_SRC (set) == SET_DEST (set)
1485 && REG_P (SET_SRC (set))
1486 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1487 || (REG_P (SET_SRC (set)) && REG_P (SET_DEST (set))
1488 && reg_renumber[REGNO (SET_SRC (set))] < 0
1489 && reg_renumber[REGNO (SET_DEST (set))] < 0
1490 && reg_equiv_memory_loc (REGNO (SET_SRC (set))) != NULL
1491 && reg_equiv_memory_loc (REGNO (SET_DEST (set))) != NULL
1492 && rtx_equal_p (reg_equiv_memory_loc (REGNO (SET_SRC (set))),
1493 reg_equiv_memory_loc (REGNO (SET_DEST (set)))))))
1494 {
1495 if (ira_conflicts_p)
1496 /* Inform IRA about the insn deletion. */
1497 ira_mark_memory_move_deletion (REGNO (SET_DEST (set)),
1498 REGNO (SET_SRC (set)));
1499 delete_insn (insn);
1500 /* Delete it from the reload chain. */
1501 if (chain->prev)
1502 chain->prev->next = next;
1503 else
1504 reload_insn_chain = next;
1505 if (next)
1506 next->prev = chain->prev;
1507 chain->next = unused_insn_chains;
1508 unused_insn_chains = chain;
1509 continue;
1510 }
1511 }
1512 if (num_eliminable)
1513 update_eliminable_offsets ();
1514
1515 /* Remember for later shortcuts which insns had any reloads or
1516 register eliminations. */
1517 chain->need_elim = did_elimination;
1518 chain->need_reload = n_reloads > 0;
1519 chain->need_operand_change = operands_changed;
1520
1521 /* Discard any register replacements done. */
1522 if (did_elimination)
1523 {
1524 obstack_free (&reload_obstack, reload_insn_firstobj);
1525 PATTERN (insn) = old_body;
1526 INSN_CODE (insn) = old_code;
1527 REG_NOTES (insn) = old_notes;
1528 something_needs_elimination = 1;
1529 }
1530
1531 something_needs_operands_changed |= operands_changed;
1532
1533 if (n_reloads != 0)
1534 {
1535 copy_reloads (chain);
1536 *pprev_reload = chain;
1537 pprev_reload = &chain->next_need_reload;
1538 }
1539 }
1540 }
1541 *pprev_reload = 0;
1542 }
1543
1544 /* This function is called from the register allocator to set up estimates
1545 for the cost of eliminating pseudos which have REG_EQUIV equivalences to
1546 an invariant. The structure is similar to calculate_needs_all_insns. */
1547
1548 void
calculate_elim_costs_all_insns(void)1549 calculate_elim_costs_all_insns (void)
1550 {
1551 int *reg_equiv_init_cost;
1552 basic_block bb;
1553 int i;
1554
1555 reg_equiv_init_cost = XCNEWVEC (int, max_regno);
1556 init_elim_table ();
1557 init_eliminable_invariants (get_insns (), false);
1558
1559 set_initial_elim_offsets ();
1560 set_initial_label_offsets ();
1561
1562 FOR_EACH_BB_FN (bb, cfun)
1563 {
1564 rtx_insn *insn;
1565 elim_bb = bb;
1566
1567 FOR_BB_INSNS (bb, insn)
1568 {
1569 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1570 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1571 what effects this has on the known offsets at labels. */
1572
1573 if (LABEL_P (insn) || JUMP_P (insn) || JUMP_TABLE_DATA_P (insn)
1574 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1575 set_label_offsets (insn, insn, 0);
1576
1577 if (INSN_P (insn))
1578 {
1579 rtx set = single_set (insn);
1580
1581 /* Skip insns that only set an equivalence. */
1582 if (set && REG_P (SET_DEST (set))
1583 && reg_renumber[REGNO (SET_DEST (set))] < 0
1584 && (reg_equiv_constant (REGNO (SET_DEST (set)))
1585 || reg_equiv_invariant (REGNO (SET_DEST (set)))))
1586 {
1587 unsigned regno = REGNO (SET_DEST (set));
1588 rtx_insn_list *init = reg_equiv_init (regno);
1589 if (init)
1590 {
1591 rtx t = eliminate_regs_1 (SET_SRC (set), VOIDmode, insn,
1592 false, true);
1593 machine_mode mode = GET_MODE (SET_DEST (set));
1594 int cost = set_src_cost (t, mode,
1595 optimize_bb_for_speed_p (bb));
1596 int freq = REG_FREQ_FROM_BB (bb);
1597
1598 reg_equiv_init_cost[regno] = cost * freq;
1599 continue;
1600 }
1601 }
1602 /* If needed, eliminate any eliminable registers. */
1603 if (num_eliminable || num_eliminable_invariants)
1604 elimination_costs_in_insn (insn);
1605
1606 if (num_eliminable)
1607 update_eliminable_offsets ();
1608 }
1609 }
1610 }
1611 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1612 {
1613 if (reg_equiv_invariant (i))
1614 {
1615 if (reg_equiv_init (i))
1616 {
1617 int cost = reg_equiv_init_cost[i];
1618 if (dump_file)
1619 fprintf (dump_file,
1620 "Reg %d has equivalence, initial gains %d\n", i, cost);
1621 if (cost != 0)
1622 ira_adjust_equiv_reg_cost (i, cost);
1623 }
1624 else
1625 {
1626 if (dump_file)
1627 fprintf (dump_file,
1628 "Reg %d had equivalence, but can't be eliminated\n",
1629 i);
1630 ira_adjust_equiv_reg_cost (i, 0);
1631 }
1632 }
1633 }
1634
1635 free (reg_equiv_init_cost);
1636 free (offsets_known_at);
1637 free (offsets_at);
1638 offsets_at = NULL;
1639 offsets_known_at = NULL;
1640 }
1641
1642 /* Comparison function for qsort to decide which of two reloads
1643 should be handled first. *P1 and *P2 are the reload numbers. */
1644
1645 static int
reload_reg_class_lower(const void * r1p,const void * r2p)1646 reload_reg_class_lower (const void *r1p, const void *r2p)
1647 {
1648 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1649 int t;
1650
1651 /* Consider required reloads before optional ones. */
1652 t = rld[r1].optional - rld[r2].optional;
1653 if (t != 0)
1654 return t;
1655
1656 /* Count all solitary classes before non-solitary ones. */
1657 t = ((reg_class_size[(int) rld[r2].rclass] == 1)
1658 - (reg_class_size[(int) rld[r1].rclass] == 1));
1659 if (t != 0)
1660 return t;
1661
1662 /* Aside from solitaires, consider all multi-reg groups first. */
1663 t = rld[r2].nregs - rld[r1].nregs;
1664 if (t != 0)
1665 return t;
1666
1667 /* Consider reloads in order of increasing reg-class number. */
1668 t = (int) rld[r1].rclass - (int) rld[r2].rclass;
1669 if (t != 0)
1670 return t;
1671
1672 /* If reloads are equally urgent, sort by reload number,
1673 so that the results of qsort leave nothing to chance. */
1674 return r1 - r2;
1675 }
1676
1677 /* The cost of spilling each hard reg. */
1678 static int spill_cost[FIRST_PSEUDO_REGISTER];
1679
1680 /* When spilling multiple hard registers, we use SPILL_COST for the first
1681 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1682 only the first hard reg for a multi-reg pseudo. */
1683 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1684
1685 /* Map of hard regno to pseudo regno currently occupying the hard
1686 reg. */
1687 static int hard_regno_to_pseudo_regno[FIRST_PSEUDO_REGISTER];
1688
1689 /* Update the spill cost arrays, considering that pseudo REG is live. */
1690
1691 static void
count_pseudo(int reg)1692 count_pseudo (int reg)
1693 {
1694 int freq = REG_FREQ (reg);
1695 int r = reg_renumber[reg];
1696 int nregs;
1697
1698 /* Ignore spilled pseudo-registers which can be here only if IRA is used. */
1699 if (ira_conflicts_p && r < 0)
1700 return;
1701
1702 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1703 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1704 return;
1705
1706 SET_REGNO_REG_SET (&pseudos_counted, reg);
1707
1708 gcc_assert (r >= 0);
1709
1710 spill_add_cost[r] += freq;
1711 nregs = hard_regno_nregs (r, PSEUDO_REGNO_MODE (reg));
1712 while (nregs-- > 0)
1713 {
1714 hard_regno_to_pseudo_regno[r + nregs] = reg;
1715 spill_cost[r + nregs] += freq;
1716 }
1717 }
1718
1719 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1720 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1721
1722 static void
order_regs_for_reload(class insn_chain * chain)1723 order_regs_for_reload (class insn_chain *chain)
1724 {
1725 unsigned i;
1726 HARD_REG_SET used_by_pseudos;
1727 HARD_REG_SET used_by_pseudos2;
1728 reg_set_iterator rsi;
1729
1730 bad_spill_regs = fixed_reg_set;
1731
1732 memset (spill_cost, 0, sizeof spill_cost);
1733 memset (spill_add_cost, 0, sizeof spill_add_cost);
1734 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1735 hard_regno_to_pseudo_regno[i] = -1;
1736
1737 /* Count number of uses of each hard reg by pseudo regs allocated to it
1738 and then order them by decreasing use. First exclude hard registers
1739 that are live in or across this insn. */
1740
1741 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1742 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1743 bad_spill_regs |= used_by_pseudos;
1744 bad_spill_regs |= used_by_pseudos2;
1745
1746 /* Now find out which pseudos are allocated to it, and update
1747 hard_reg_n_uses. */
1748 CLEAR_REG_SET (&pseudos_counted);
1749
1750 EXECUTE_IF_SET_IN_REG_SET
1751 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1752 {
1753 count_pseudo (i);
1754 }
1755 EXECUTE_IF_SET_IN_REG_SET
1756 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1757 {
1758 count_pseudo (i);
1759 }
1760 CLEAR_REG_SET (&pseudos_counted);
1761 }
1762
1763 /* Vector of reload-numbers showing the order in which the reloads should
1764 be processed. */
1765 static short reload_order[MAX_RELOADS];
1766
1767 /* This is used to keep track of the spill regs used in one insn. */
1768 static HARD_REG_SET used_spill_regs_local;
1769
1770 /* We decided to spill hard register SPILLED, which has a size of
1771 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1772 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1773 update SPILL_COST/SPILL_ADD_COST. */
1774
1775 static void
count_spilled_pseudo(int spilled,int spilled_nregs,int reg)1776 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1777 {
1778 int freq = REG_FREQ (reg);
1779 int r = reg_renumber[reg];
1780 int nregs;
1781
1782 /* Ignore spilled pseudo-registers which can be here only if IRA is used. */
1783 if (ira_conflicts_p && r < 0)
1784 return;
1785
1786 gcc_assert (r >= 0);
1787
1788 nregs = hard_regno_nregs (r, PSEUDO_REGNO_MODE (reg));
1789
1790 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1791 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1792 return;
1793
1794 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1795
1796 spill_add_cost[r] -= freq;
1797 while (nregs-- > 0)
1798 {
1799 hard_regno_to_pseudo_regno[r + nregs] = -1;
1800 spill_cost[r + nregs] -= freq;
1801 }
1802 }
1803
1804 /* Find reload register to use for reload number ORDER. */
1805
1806 static int
find_reg(class insn_chain * chain,int order)1807 find_reg (class insn_chain *chain, int order)
1808 {
1809 int rnum = reload_order[order];
1810 struct reload *rl = rld + rnum;
1811 int best_cost = INT_MAX;
1812 int best_reg = -1;
1813 unsigned int i, j, n;
1814 int k;
1815 HARD_REG_SET not_usable;
1816 HARD_REG_SET used_by_other_reload;
1817 reg_set_iterator rsi;
1818 static int regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1819 static int best_regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1820
1821 not_usable = (bad_spill_regs
1822 | bad_spill_regs_global
1823 | ~reg_class_contents[rl->rclass]);
1824
1825 CLEAR_HARD_REG_SET (used_by_other_reload);
1826 for (k = 0; k < order; k++)
1827 {
1828 int other = reload_order[k];
1829
1830 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1831 for (j = 0; j < rld[other].nregs; j++)
1832 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1833 }
1834
1835 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1836 {
1837 #ifdef REG_ALLOC_ORDER
1838 unsigned int regno = reg_alloc_order[i];
1839 #else
1840 unsigned int regno = i;
1841 #endif
1842
1843 if (! TEST_HARD_REG_BIT (not_usable, regno)
1844 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1845 && targetm.hard_regno_mode_ok (regno, rl->mode))
1846 {
1847 int this_cost = spill_cost[regno];
1848 int ok = 1;
1849 unsigned int this_nregs = hard_regno_nregs (regno, rl->mode);
1850
1851 for (j = 1; j < this_nregs; j++)
1852 {
1853 this_cost += spill_add_cost[regno + j];
1854 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1855 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1856 ok = 0;
1857 }
1858 if (! ok)
1859 continue;
1860
1861 if (ira_conflicts_p)
1862 {
1863 /* Ask IRA to find a better pseudo-register for
1864 spilling. */
1865 for (n = j = 0; j < this_nregs; j++)
1866 {
1867 int r = hard_regno_to_pseudo_regno[regno + j];
1868
1869 if (r < 0)
1870 continue;
1871 if (n == 0 || regno_pseudo_regs[n - 1] != r)
1872 regno_pseudo_regs[n++] = r;
1873 }
1874 regno_pseudo_regs[n++] = -1;
1875 if (best_reg < 0
1876 || ira_better_spill_reload_regno_p (regno_pseudo_regs,
1877 best_regno_pseudo_regs,
1878 rl->in, rl->out,
1879 chain->insn))
1880 {
1881 best_reg = regno;
1882 for (j = 0;; j++)
1883 {
1884 best_regno_pseudo_regs[j] = regno_pseudo_regs[j];
1885 if (regno_pseudo_regs[j] < 0)
1886 break;
1887 }
1888 }
1889 continue;
1890 }
1891
1892 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1893 this_cost--;
1894 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1895 this_cost--;
1896 if (this_cost < best_cost
1897 /* Among registers with equal cost, prefer caller-saved ones, or
1898 use REG_ALLOC_ORDER if it is defined. */
1899 || (this_cost == best_cost
1900 #ifdef REG_ALLOC_ORDER
1901 && (inv_reg_alloc_order[regno]
1902 < inv_reg_alloc_order[best_reg])
1903 #else
1904 && crtl->abi->clobbers_full_reg_p (regno)
1905 && !crtl->abi->clobbers_full_reg_p (best_reg)
1906 #endif
1907 ))
1908 {
1909 best_reg = regno;
1910 best_cost = this_cost;
1911 }
1912 }
1913 }
1914 if (best_reg == -1)
1915 return 0;
1916
1917 if (dump_file)
1918 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1919
1920 rl->nregs = hard_regno_nregs (best_reg, rl->mode);
1921 rl->regno = best_reg;
1922
1923 EXECUTE_IF_SET_IN_REG_SET
1924 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1925 {
1926 count_spilled_pseudo (best_reg, rl->nregs, j);
1927 }
1928
1929 EXECUTE_IF_SET_IN_REG_SET
1930 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1931 {
1932 count_spilled_pseudo (best_reg, rl->nregs, j);
1933 }
1934
1935 for (i = 0; i < rl->nregs; i++)
1936 {
1937 gcc_assert (spill_cost[best_reg + i] == 0);
1938 gcc_assert (spill_add_cost[best_reg + i] == 0);
1939 gcc_assert (hard_regno_to_pseudo_regno[best_reg + i] == -1);
1940 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1941 }
1942 return 1;
1943 }
1944
1945 /* Find more reload regs to satisfy the remaining need of an insn, which
1946 is given by CHAIN.
1947 Do it by ascending class number, since otherwise a reg
1948 might be spilled for a big class and might fail to count
1949 for a smaller class even though it belongs to that class. */
1950
1951 static void
find_reload_regs(class insn_chain * chain)1952 find_reload_regs (class insn_chain *chain)
1953 {
1954 int i;
1955
1956 /* In order to be certain of getting the registers we need,
1957 we must sort the reloads into order of increasing register class.
1958 Then our grabbing of reload registers will parallel the process
1959 that provided the reload registers. */
1960 for (i = 0; i < chain->n_reloads; i++)
1961 {
1962 /* Show whether this reload already has a hard reg. */
1963 if (chain->rld[i].reg_rtx)
1964 {
1965 chain->rld[i].regno = REGNO (chain->rld[i].reg_rtx);
1966 chain->rld[i].nregs = REG_NREGS (chain->rld[i].reg_rtx);
1967 }
1968 else
1969 chain->rld[i].regno = -1;
1970 reload_order[i] = i;
1971 }
1972
1973 n_reloads = chain->n_reloads;
1974 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1975
1976 CLEAR_HARD_REG_SET (used_spill_regs_local);
1977
1978 if (dump_file)
1979 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1980
1981 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1982
1983 /* Compute the order of preference for hard registers to spill. */
1984
1985 order_regs_for_reload (chain);
1986
1987 for (i = 0; i < n_reloads; i++)
1988 {
1989 int r = reload_order[i];
1990
1991 /* Ignore reloads that got marked inoperative. */
1992 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1993 && ! rld[r].optional
1994 && rld[r].regno == -1)
1995 if (! find_reg (chain, i))
1996 {
1997 if (dump_file)
1998 fprintf (dump_file, "reload failure for reload %d\n", r);
1999 spill_failure (chain->insn, rld[r].rclass);
2000 failure = 1;
2001 return;
2002 }
2003 }
2004
2005 chain->used_spill_regs = used_spill_regs_local;
2006 used_spill_regs |= used_spill_regs_local;
2007
2008 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
2009 }
2010
2011 static void
select_reload_regs(void)2012 select_reload_regs (void)
2013 {
2014 class insn_chain *chain;
2015
2016 /* Try to satisfy the needs for each insn. */
2017 for (chain = insns_need_reload; chain != 0;
2018 chain = chain->next_need_reload)
2019 find_reload_regs (chain);
2020 }
2021
2022 /* Delete all insns that were inserted by emit_caller_save_insns during
2023 this iteration. */
2024 static void
delete_caller_save_insns(void)2025 delete_caller_save_insns (void)
2026 {
2027 class insn_chain *c = reload_insn_chain;
2028
2029 while (c != 0)
2030 {
2031 while (c != 0 && c->is_caller_save_insn)
2032 {
2033 class insn_chain *next = c->next;
2034 rtx_insn *insn = c->insn;
2035
2036 if (c == reload_insn_chain)
2037 reload_insn_chain = next;
2038 delete_insn (insn);
2039
2040 if (next)
2041 next->prev = c->prev;
2042 if (c->prev)
2043 c->prev->next = next;
2044 c->next = unused_insn_chains;
2045 unused_insn_chains = c;
2046 c = next;
2047 }
2048 if (c != 0)
2049 c = c->next;
2050 }
2051 }
2052
2053 /* Handle the failure to find a register to spill.
2054 INSN should be one of the insns which needed this particular spill reg. */
2055
2056 static void
spill_failure(rtx_insn * insn,enum reg_class rclass)2057 spill_failure (rtx_insn *insn, enum reg_class rclass)
2058 {
2059 if (asm_noperands (PATTERN (insn)) >= 0)
2060 error_for_asm (insn, "cannot find a register in class %qs while "
2061 "reloading %<asm%>",
2062 reg_class_names[rclass]);
2063 else
2064 {
2065 error ("unable to find a register to spill in class %qs",
2066 reg_class_names[rclass]);
2067
2068 if (dump_file)
2069 {
2070 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
2071 debug_reload_to_stream (dump_file);
2072 }
2073 fatal_insn ("this is the insn:", insn);
2074 }
2075 }
2076
2077 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2078 data that is dead in INSN. */
2079
2080 static void
delete_dead_insn(rtx_insn * insn)2081 delete_dead_insn (rtx_insn *insn)
2082 {
2083 rtx_insn *prev = prev_active_insn (insn);
2084 rtx prev_dest;
2085
2086 /* If the previous insn sets a register that dies in our insn make
2087 a note that we want to run DCE immediately after reload.
2088
2089 We used to delete the previous insn & recurse, but that's wrong for
2090 block local equivalences. Instead of trying to figure out the exact
2091 circumstances where we can delete the potentially dead insns, just
2092 let DCE do the job. */
2093 if (prev && BLOCK_FOR_INSN (prev) == BLOCK_FOR_INSN (insn)
2094 && GET_CODE (PATTERN (prev)) == SET
2095 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
2096 && reg_mentioned_p (prev_dest, PATTERN (insn))
2097 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2098 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2099 need_dce = 1;
2100
2101 SET_INSN_DELETED (insn);
2102 }
2103
2104 /* Modify the home of pseudo-reg I.
2105 The new home is present in reg_renumber[I].
2106
2107 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2108 or it may be -1, meaning there is none or it is not relevant.
2109 This is used so that all pseudos spilled from a given hard reg
2110 can share one stack slot. */
2111
2112 static void
alter_reg(int i,int from_reg,bool dont_share_p)2113 alter_reg (int i, int from_reg, bool dont_share_p)
2114 {
2115 /* When outputting an inline function, this can happen
2116 for a reg that isn't actually used. */
2117 if (regno_reg_rtx[i] == 0)
2118 return;
2119
2120 /* If the reg got changed to a MEM at rtl-generation time,
2121 ignore it. */
2122 if (!REG_P (regno_reg_rtx[i]))
2123 return;
2124
2125 /* Modify the reg-rtx to contain the new hard reg
2126 number or else to contain its pseudo reg number. */
2127 SET_REGNO (regno_reg_rtx[i],
2128 reg_renumber[i] >= 0 ? reg_renumber[i] : i);
2129
2130 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2131 allocate a stack slot for it. */
2132
2133 if (reg_renumber[i] < 0
2134 && REG_N_REFS (i) > 0
2135 && reg_equiv_constant (i) == 0
2136 && (reg_equiv_invariant (i) == 0
2137 || reg_equiv_init (i) == 0)
2138 && reg_equiv_memory_loc (i) == 0)
2139 {
2140 rtx x = NULL_RTX;
2141 machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2142 poly_uint64 inherent_size = GET_MODE_SIZE (mode);
2143 unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2144 machine_mode wider_mode = wider_subreg_mode (mode, reg_max_ref_mode[i]);
2145 poly_uint64 total_size = GET_MODE_SIZE (wider_mode);
2146 /* ??? Seems strange to derive the minimum alignment from the size,
2147 but that's the traditional behavior. For polynomial-size modes,
2148 the natural extension is to use the minimum possible size. */
2149 unsigned int min_align
2150 = constant_lower_bound (GET_MODE_BITSIZE (reg_max_ref_mode[i]));
2151 poly_int64 adjust = 0;
2152
2153 something_was_spilled = true;
2154
2155 if (ira_conflicts_p)
2156 {
2157 /* Mark the spill for IRA. */
2158 SET_REGNO_REG_SET (&spilled_pseudos, i);
2159 if (!dont_share_p)
2160 x = ira_reuse_stack_slot (i, inherent_size, total_size);
2161 }
2162
2163 if (x)
2164 ;
2165
2166 /* Each pseudo reg has an inherent size which comes from its own mode,
2167 and a total size which provides room for paradoxical subregs
2168 which refer to the pseudo reg in wider modes.
2169
2170 We can use a slot already allocated if it provides both
2171 enough inherent space and enough total space.
2172 Otherwise, we allocate a new slot, making sure that it has no less
2173 inherent space, and no less total space, then the previous slot. */
2174 else if (from_reg == -1 || (!dont_share_p && ira_conflicts_p))
2175 {
2176 rtx stack_slot;
2177
2178 /* The sizes are taken from a subreg operation, which guarantees
2179 that they're ordered. */
2180 gcc_checking_assert (ordered_p (total_size, inherent_size));
2181
2182 /* No known place to spill from => no slot to reuse. */
2183 x = assign_stack_local (mode, total_size,
2184 min_align > inherent_align
2185 || maybe_gt (total_size, inherent_size)
2186 ? -1 : 0);
2187
2188 stack_slot = x;
2189
2190 /* Cancel the big-endian correction done in assign_stack_local.
2191 Get the address of the beginning of the slot. This is so we
2192 can do a big-endian correction unconditionally below. */
2193 if (BYTES_BIG_ENDIAN)
2194 {
2195 adjust = inherent_size - total_size;
2196 if (maybe_ne (adjust, 0))
2197 {
2198 poly_uint64 total_bits = total_size * BITS_PER_UNIT;
2199 machine_mode mem_mode
2200 = int_mode_for_size (total_bits, 1).else_blk ();
2201 stack_slot = adjust_address_nv (x, mem_mode, adjust);
2202 }
2203 }
2204
2205 if (! dont_share_p && ira_conflicts_p)
2206 /* Inform IRA about allocation a new stack slot. */
2207 ira_mark_new_stack_slot (stack_slot, i, total_size);
2208 }
2209
2210 /* Reuse a stack slot if possible. */
2211 else if (spill_stack_slot[from_reg] != 0
2212 && known_ge (spill_stack_slot_width[from_reg], total_size)
2213 && known_ge (GET_MODE_SIZE
2214 (GET_MODE (spill_stack_slot[from_reg])),
2215 inherent_size)
2216 && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2217 x = spill_stack_slot[from_reg];
2218
2219 /* Allocate a bigger slot. */
2220 else
2221 {
2222 /* Compute maximum size needed, both for inherent size
2223 and for total size. */
2224 rtx stack_slot;
2225
2226 if (spill_stack_slot[from_reg])
2227 {
2228 if (partial_subreg_p (mode,
2229 GET_MODE (spill_stack_slot[from_reg])))
2230 mode = GET_MODE (spill_stack_slot[from_reg]);
2231 total_size = ordered_max (total_size,
2232 spill_stack_slot_width[from_reg]);
2233 if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2234 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2235 }
2236
2237 /* The sizes are taken from a subreg operation, which guarantees
2238 that they're ordered. */
2239 gcc_checking_assert (ordered_p (total_size, inherent_size));
2240
2241 /* Make a slot with that size. */
2242 x = assign_stack_local (mode, total_size,
2243 min_align > inherent_align
2244 || maybe_gt (total_size, inherent_size)
2245 ? -1 : 0);
2246 stack_slot = x;
2247
2248 /* Cancel the big-endian correction done in assign_stack_local.
2249 Get the address of the beginning of the slot. This is so we
2250 can do a big-endian correction unconditionally below. */
2251 if (BYTES_BIG_ENDIAN)
2252 {
2253 adjust = GET_MODE_SIZE (mode) - total_size;
2254 if (maybe_ne (adjust, 0))
2255 {
2256 poly_uint64 total_bits = total_size * BITS_PER_UNIT;
2257 machine_mode mem_mode
2258 = int_mode_for_size (total_bits, 1).else_blk ();
2259 stack_slot = adjust_address_nv (x, mem_mode, adjust);
2260 }
2261 }
2262
2263 spill_stack_slot[from_reg] = stack_slot;
2264 spill_stack_slot_width[from_reg] = total_size;
2265 }
2266
2267 /* On a big endian machine, the "address" of the slot
2268 is the address of the low part that fits its inherent mode. */
2269 adjust += subreg_size_lowpart_offset (inherent_size, total_size);
2270
2271 /* If we have any adjustment to make, or if the stack slot is the
2272 wrong mode, make a new stack slot. */
2273 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2274
2275 /* Set all of the memory attributes as appropriate for a spill. */
2276 set_mem_attrs_for_spill (x);
2277
2278 /* Save the stack slot for later. */
2279 reg_equiv_memory_loc (i) = x;
2280 }
2281 }
2282
2283 /* Mark the slots in regs_ever_live for the hard regs used by
2284 pseudo-reg number REGNO, accessed in MODE. */
2285
2286 static void
mark_home_live_1(int regno,machine_mode mode)2287 mark_home_live_1 (int regno, machine_mode mode)
2288 {
2289 int i, lim;
2290
2291 i = reg_renumber[regno];
2292 if (i < 0)
2293 return;
2294 lim = end_hard_regno (mode, i);
2295 while (i < lim)
2296 df_set_regs_ever_live (i++, true);
2297 }
2298
2299 /* Mark the slots in regs_ever_live for the hard regs
2300 used by pseudo-reg number REGNO. */
2301
2302 void
mark_home_live(int regno)2303 mark_home_live (int regno)
2304 {
2305 if (reg_renumber[regno] >= 0)
2306 mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno));
2307 }
2308
2309 /* This function handles the tracking of elimination offsets around branches.
2310
2311 X is a piece of RTL being scanned.
2312
2313 INSN is the insn that it came from, if any.
2314
2315 INITIAL_P is nonzero if we are to set the offset to be the initial
2316 offset and zero if we are setting the offset of the label to be the
2317 current offset. */
2318
2319 static void
set_label_offsets(rtx x,rtx_insn * insn,int initial_p)2320 set_label_offsets (rtx x, rtx_insn *insn, int initial_p)
2321 {
2322 enum rtx_code code = GET_CODE (x);
2323 rtx tem;
2324 unsigned int i;
2325 struct elim_table *p;
2326
2327 switch (code)
2328 {
2329 case LABEL_REF:
2330 if (LABEL_REF_NONLOCAL_P (x))
2331 return;
2332
2333 x = label_ref_label (x);
2334
2335 /* fall through */
2336
2337 case CODE_LABEL:
2338 /* If we know nothing about this label, set the desired offsets. Note
2339 that this sets the offset at a label to be the offset before a label
2340 if we don't know anything about the label. This is not correct for
2341 the label after a BARRIER, but is the best guess we can make. If
2342 we guessed wrong, we will suppress an elimination that might have
2343 been possible had we been able to guess correctly. */
2344
2345 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2346 {
2347 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2348 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2349 = (initial_p ? reg_eliminate[i].initial_offset
2350 : reg_eliminate[i].offset);
2351 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2352 }
2353
2354 /* Otherwise, if this is the definition of a label and it is
2355 preceded by a BARRIER, set our offsets to the known offset of
2356 that label. */
2357
2358 else if (x == insn
2359 && (tem = prev_nonnote_insn (insn)) != 0
2360 && BARRIER_P (tem))
2361 set_offsets_for_label (insn);
2362 else
2363 /* If neither of the above cases is true, compare each offset
2364 with those previously recorded and suppress any eliminations
2365 where the offsets disagree. */
2366
2367 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2368 if (maybe_ne (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i],
2369 (initial_p ? reg_eliminate[i].initial_offset
2370 : reg_eliminate[i].offset)))
2371 reg_eliminate[i].can_eliminate = 0;
2372
2373 return;
2374
2375 case JUMP_TABLE_DATA:
2376 set_label_offsets (PATTERN (insn), insn, initial_p);
2377 return;
2378
2379 case JUMP_INSN:
2380 set_label_offsets (PATTERN (insn), insn, initial_p);
2381
2382 /* fall through */
2383
2384 case INSN:
2385 case CALL_INSN:
2386 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2387 to indirectly and hence must have all eliminations at their
2388 initial offsets. */
2389 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2390 if (REG_NOTE_KIND (tem) == REG_LABEL_OPERAND)
2391 set_label_offsets (XEXP (tem, 0), insn, 1);
2392 return;
2393
2394 case PARALLEL:
2395 case ADDR_VEC:
2396 case ADDR_DIFF_VEC:
2397 /* Each of the labels in the parallel or address vector must be
2398 at their initial offsets. We want the first field for PARALLEL
2399 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2400
2401 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2402 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2403 insn, initial_p);
2404 return;
2405
2406 case SET:
2407 /* We only care about setting PC. If the source is not RETURN,
2408 IF_THEN_ELSE, or a label, disable any eliminations not at
2409 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2410 isn't one of those possibilities. For branches to a label,
2411 call ourselves recursively.
2412
2413 Note that this can disable elimination unnecessarily when we have
2414 a non-local goto since it will look like a non-constant jump to
2415 someplace in the current function. This isn't a significant
2416 problem since such jumps will normally be when all elimination
2417 pairs are back to their initial offsets. */
2418
2419 if (SET_DEST (x) != pc_rtx)
2420 return;
2421
2422 switch (GET_CODE (SET_SRC (x)))
2423 {
2424 case PC:
2425 case RETURN:
2426 return;
2427
2428 case LABEL_REF:
2429 set_label_offsets (SET_SRC (x), insn, initial_p);
2430 return;
2431
2432 case IF_THEN_ELSE:
2433 tem = XEXP (SET_SRC (x), 1);
2434 if (GET_CODE (tem) == LABEL_REF)
2435 set_label_offsets (label_ref_label (tem), insn, initial_p);
2436 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2437 break;
2438
2439 tem = XEXP (SET_SRC (x), 2);
2440 if (GET_CODE (tem) == LABEL_REF)
2441 set_label_offsets (label_ref_label (tem), insn, initial_p);
2442 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2443 break;
2444 return;
2445
2446 default:
2447 break;
2448 }
2449
2450 /* If we reach here, all eliminations must be at their initial
2451 offset because we are doing a jump to a variable address. */
2452 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2453 if (maybe_ne (p->offset, p->initial_offset))
2454 p->can_eliminate = 0;
2455 break;
2456
2457 default:
2458 break;
2459 }
2460 }
2461
2462 /* This function examines every reg that occurs in X and adjusts the
2463 costs for its elimination which are gathered by IRA. INSN is the
2464 insn in which X occurs. We do not recurse into MEM expressions. */
2465
2466 static void
note_reg_elim_costly(const_rtx x,rtx insn)2467 note_reg_elim_costly (const_rtx x, rtx insn)
2468 {
2469 subrtx_iterator::array_type array;
2470 FOR_EACH_SUBRTX (iter, array, x, NONCONST)
2471 {
2472 const_rtx x = *iter;
2473 if (MEM_P (x))
2474 iter.skip_subrtxes ();
2475 else if (REG_P (x)
2476 && REGNO (x) >= FIRST_PSEUDO_REGISTER
2477 && reg_equiv_init (REGNO (x))
2478 && reg_equiv_invariant (REGNO (x)))
2479 {
2480 rtx t = reg_equiv_invariant (REGNO (x));
2481 rtx new_rtx = eliminate_regs_1 (t, Pmode, insn, true, true);
2482 int cost = set_src_cost (new_rtx, Pmode,
2483 optimize_bb_for_speed_p (elim_bb));
2484 int freq = REG_FREQ_FROM_BB (elim_bb);
2485
2486 if (cost != 0)
2487 ira_adjust_equiv_reg_cost (REGNO (x), -cost * freq);
2488 }
2489 }
2490 }
2491
2492 /* Scan X and replace any eliminable registers (such as fp) with a
2493 replacement (such as sp), plus an offset.
2494
2495 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2496 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2497 MEM, we are allowed to replace a sum of a register and the constant zero
2498 with the register, which we cannot do outside a MEM. In addition, we need
2499 to record the fact that a register is referenced outside a MEM.
2500
2501 If INSN is an insn, it is the insn containing X. If we replace a REG
2502 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2503 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2504 the REG is being modified.
2505
2506 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2507 That's used when we eliminate in expressions stored in notes.
2508 This means, do not set ref_outside_mem even if the reference
2509 is outside of MEMs.
2510
2511 If FOR_COSTS is true, we are being called before reload in order to
2512 estimate the costs of keeping registers with an equivalence unallocated.
2513
2514 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2515 replacements done assuming all offsets are at their initial values. If
2516 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2517 encounter, return the actual location so that find_reloads will do
2518 the proper thing. */
2519
2520 static rtx
eliminate_regs_1(rtx x,machine_mode mem_mode,rtx insn,bool may_use_invariant,bool for_costs)2521 eliminate_regs_1 (rtx x, machine_mode mem_mode, rtx insn,
2522 bool may_use_invariant, bool for_costs)
2523 {
2524 enum rtx_code code = GET_CODE (x);
2525 struct elim_table *ep;
2526 int regno;
2527 rtx new_rtx;
2528 int i, j;
2529 const char *fmt;
2530 int copied = 0;
2531
2532 if (! current_function_decl)
2533 return x;
2534
2535 switch (code)
2536 {
2537 CASE_CONST_ANY:
2538 case CONST:
2539 case SYMBOL_REF:
2540 case CODE_LABEL:
2541 case PC:
2542 case ASM_INPUT:
2543 case ADDR_VEC:
2544 case ADDR_DIFF_VEC:
2545 case RETURN:
2546 return x;
2547
2548 case REG:
2549 regno = REGNO (x);
2550
2551 /* First handle the case where we encounter a bare register that
2552 is eliminable. Replace it with a PLUS. */
2553 if (regno < FIRST_PSEUDO_REGISTER)
2554 {
2555 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2556 ep++)
2557 if (ep->from_rtx == x && ep->can_eliminate)
2558 return plus_constant (Pmode, ep->to_rtx, ep->previous_offset);
2559
2560 }
2561 else if (reg_renumber && reg_renumber[regno] < 0
2562 && reg_equivs
2563 && reg_equiv_invariant (regno))
2564 {
2565 if (may_use_invariant || (insn && DEBUG_INSN_P (insn)))
2566 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant (regno)),
2567 mem_mode, insn, true, for_costs);
2568 /* There exists at least one use of REGNO that cannot be
2569 eliminated. Prevent the defining insn from being deleted. */
2570 reg_equiv_init (regno) = NULL;
2571 if (!for_costs)
2572 alter_reg (regno, -1, true);
2573 }
2574 return x;
2575
2576 /* You might think handling MINUS in a manner similar to PLUS is a
2577 good idea. It is not. It has been tried multiple times and every
2578 time the change has had to have been reverted.
2579
2580 Other parts of reload know a PLUS is special (gen_reload for example)
2581 and require special code to handle code a reloaded PLUS operand.
2582
2583 Also consider backends where the flags register is clobbered by a
2584 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2585 lea instruction comes to mind). If we try to reload a MINUS, we
2586 may kill the flags register that was holding a useful value.
2587
2588 So, please before trying to handle MINUS, consider reload as a
2589 whole instead of this little section as well as the backend issues. */
2590 case PLUS:
2591 /* If this is the sum of an eliminable register and a constant, rework
2592 the sum. */
2593 if (REG_P (XEXP (x, 0))
2594 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2595 && CONSTANT_P (XEXP (x, 1)))
2596 {
2597 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2598 ep++)
2599 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2600 {
2601 /* The only time we want to replace a PLUS with a REG (this
2602 occurs when the constant operand of the PLUS is the negative
2603 of the offset) is when we are inside a MEM. We won't want
2604 to do so at other times because that would change the
2605 structure of the insn in a way that reload can't handle.
2606 We special-case the commonest situation in
2607 eliminate_regs_in_insn, so just replace a PLUS with a
2608 PLUS here, unless inside a MEM. In DEBUG_INSNs, it is
2609 always ok to replace a PLUS with just a REG. */
2610 if ((mem_mode != 0 || (insn && DEBUG_INSN_P (insn)))
2611 && CONST_INT_P (XEXP (x, 1))
2612 && known_eq (INTVAL (XEXP (x, 1)), -ep->previous_offset))
2613 return ep->to_rtx;
2614 else
2615 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2616 plus_constant (Pmode, XEXP (x, 1),
2617 ep->previous_offset));
2618 }
2619
2620 /* If the register is not eliminable, we are done since the other
2621 operand is a constant. */
2622 return x;
2623 }
2624
2625 /* If this is part of an address, we want to bring any constant to the
2626 outermost PLUS. We will do this by doing register replacement in
2627 our operands and seeing if a constant shows up in one of them.
2628
2629 Note that there is no risk of modifying the structure of the insn,
2630 since we only get called for its operands, thus we are either
2631 modifying the address inside a MEM, or something like an address
2632 operand of a load-address insn. */
2633
2634 {
2635 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
2636 for_costs);
2637 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2638 for_costs);
2639
2640 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2641 {
2642 /* If one side is a PLUS and the other side is a pseudo that
2643 didn't get a hard register but has a reg_equiv_constant,
2644 we must replace the constant here since it may no longer
2645 be in the position of any operand. */
2646 if (GET_CODE (new0) == PLUS && REG_P (new1)
2647 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2648 && reg_renumber[REGNO (new1)] < 0
2649 && reg_equivs
2650 && reg_equiv_constant (REGNO (new1)) != 0)
2651 new1 = reg_equiv_constant (REGNO (new1));
2652 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2653 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2654 && reg_renumber[REGNO (new0)] < 0
2655 && reg_equiv_constant (REGNO (new0)) != 0)
2656 new0 = reg_equiv_constant (REGNO (new0));
2657
2658 new_rtx = form_sum (GET_MODE (x), new0, new1);
2659
2660 /* As above, if we are not inside a MEM we do not want to
2661 turn a PLUS into something else. We might try to do so here
2662 for an addition of 0 if we aren't optimizing. */
2663 if (! mem_mode && GET_CODE (new_rtx) != PLUS)
2664 return gen_rtx_PLUS (GET_MODE (x), new_rtx, const0_rtx);
2665 else
2666 return new_rtx;
2667 }
2668 }
2669 return x;
2670
2671 case MULT:
2672 /* If this is the product of an eliminable register and a
2673 constant, apply the distribute law and move the constant out
2674 so that we have (plus (mult ..) ..). This is needed in order
2675 to keep load-address insns valid. This case is pathological.
2676 We ignore the possibility of overflow here. */
2677 if (REG_P (XEXP (x, 0))
2678 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2679 && CONST_INT_P (XEXP (x, 1)))
2680 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2681 ep++)
2682 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2683 {
2684 if (! mem_mode
2685 /* Refs inside notes or in DEBUG_INSNs don't count for
2686 this purpose. */
2687 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2688 || GET_CODE (insn) == INSN_LIST
2689 || DEBUG_INSN_P (insn))))
2690 ep->ref_outside_mem = 1;
2691
2692 return
2693 plus_constant (Pmode,
2694 gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2695 ep->previous_offset * INTVAL (XEXP (x, 1)));
2696 }
2697
2698 /* fall through */
2699
2700 case CALL:
2701 case COMPARE:
2702 /* See comments before PLUS about handling MINUS. */
2703 case MINUS:
2704 case DIV: case UDIV:
2705 case MOD: case UMOD:
2706 case AND: case IOR: case XOR:
2707 case ROTATERT: case ROTATE:
2708 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2709 case NE: case EQ:
2710 case GE: case GT: case GEU: case GTU:
2711 case LE: case LT: case LEU: case LTU:
2712 {
2713 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
2714 for_costs);
2715 rtx new1 = XEXP (x, 1)
2716 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false,
2717 for_costs) : 0;
2718
2719 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2720 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2721 }
2722 return x;
2723
2724 case EXPR_LIST:
2725 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2726 if (XEXP (x, 0))
2727 {
2728 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
2729 for_costs);
2730 if (new_rtx != XEXP (x, 0))
2731 {
2732 /* If this is a REG_DEAD note, it is not valid anymore.
2733 Using the eliminated version could result in creating a
2734 REG_DEAD note for the stack or frame pointer. */
2735 if (REG_NOTE_KIND (x) == REG_DEAD)
2736 return (XEXP (x, 1)
2737 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2738 for_costs)
2739 : NULL_RTX);
2740
2741 x = alloc_reg_note (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1));
2742 }
2743 }
2744
2745 /* fall through */
2746
2747 case INSN_LIST:
2748 case INT_LIST:
2749 /* Now do eliminations in the rest of the chain. If this was
2750 an EXPR_LIST, this might result in allocating more memory than is
2751 strictly needed, but it simplifies the code. */
2752 if (XEXP (x, 1))
2753 {
2754 new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2755 for_costs);
2756 if (new_rtx != XEXP (x, 1))
2757 return
2758 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx);
2759 }
2760 return x;
2761
2762 case PRE_INC:
2763 case POST_INC:
2764 case PRE_DEC:
2765 case POST_DEC:
2766 /* We do not support elimination of a register that is modified.
2767 elimination_effects has already make sure that this does not
2768 happen. */
2769 return x;
2770
2771 case PRE_MODIFY:
2772 case POST_MODIFY:
2773 /* We do not support elimination of a register that is modified.
2774 elimination_effects has already make sure that this does not
2775 happen. The only remaining case we need to consider here is
2776 that the increment value may be an eliminable register. */
2777 if (GET_CODE (XEXP (x, 1)) == PLUS
2778 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2779 {
2780 rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
2781 insn, true, for_costs);
2782
2783 if (new_rtx != XEXP (XEXP (x, 1), 1))
2784 return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2785 gen_rtx_PLUS (GET_MODE (x),
2786 XEXP (x, 0), new_rtx));
2787 }
2788 return x;
2789
2790 case STRICT_LOW_PART:
2791 case NEG: case NOT:
2792 case SIGN_EXTEND: case ZERO_EXTEND:
2793 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2794 case FLOAT: case FIX:
2795 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2796 case ABS:
2797 case SQRT:
2798 case FFS:
2799 case CLZ:
2800 case CTZ:
2801 case POPCOUNT:
2802 case PARITY:
2803 case BSWAP:
2804 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
2805 for_costs);
2806 if (new_rtx != XEXP (x, 0))
2807 return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx);
2808 return x;
2809
2810 case SUBREG:
2811 /* Similar to above processing, but preserve SUBREG_BYTE.
2812 Convert (subreg (mem)) to (mem) if not paradoxical.
2813 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2814 pseudo didn't get a hard reg, we must replace this with the
2815 eliminated version of the memory location because push_reload
2816 may do the replacement in certain circumstances. */
2817 if (REG_P (SUBREG_REG (x))
2818 && !paradoxical_subreg_p (x)
2819 && reg_equivs
2820 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x))) != 0)
2821 {
2822 new_rtx = SUBREG_REG (x);
2823 }
2824 else
2825 new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false, for_costs);
2826
2827 if (new_rtx != SUBREG_REG (x))
2828 {
2829 poly_int64 x_size = GET_MODE_SIZE (GET_MODE (x));
2830 poly_int64 new_size = GET_MODE_SIZE (GET_MODE (new_rtx));
2831
2832 if (MEM_P (new_rtx)
2833 && ((partial_subreg_p (GET_MODE (x), GET_MODE (new_rtx))
2834 /* On RISC machines, combine can create rtl of the form
2835 (set (subreg:m1 (reg:m2 R) 0) ...)
2836 where m1 < m2, and expects something interesting to
2837 happen to the entire word. Moreover, it will use the
2838 (reg:m2 R) later, expecting all bits to be preserved.
2839 So if the number of words is the same, preserve the
2840 subreg so that push_reload can see it. */
2841 && !(WORD_REGISTER_OPERATIONS
2842 && known_equal_after_align_down (x_size - 1,
2843 new_size - 1,
2844 UNITS_PER_WORD)))
2845 || known_eq (x_size, new_size))
2846 )
2847 return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x));
2848 else if (insn && GET_CODE (insn) == DEBUG_INSN)
2849 return gen_rtx_raw_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
2850 else
2851 return gen_rtx_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
2852 }
2853
2854 return x;
2855
2856 case MEM:
2857 /* Our only special processing is to pass the mode of the MEM to our
2858 recursive call and copy the flags. While we are here, handle this
2859 case more efficiently. */
2860
2861 new_rtx = eliminate_regs_1 (XEXP (x, 0), GET_MODE (x), insn, true,
2862 for_costs);
2863 if (for_costs
2864 && memory_address_p (GET_MODE (x), XEXP (x, 0))
2865 && !memory_address_p (GET_MODE (x), new_rtx))
2866 note_reg_elim_costly (XEXP (x, 0), insn);
2867
2868 return replace_equiv_address_nv (x, new_rtx);
2869
2870 case USE:
2871 /* Handle insn_list USE that a call to a pure function may generate. */
2872 new_rtx = eliminate_regs_1 (XEXP (x, 0), VOIDmode, insn, false,
2873 for_costs);
2874 if (new_rtx != XEXP (x, 0))
2875 return gen_rtx_USE (GET_MODE (x), new_rtx);
2876 return x;
2877
2878 case CLOBBER:
2879 case ASM_OPERANDS:
2880 gcc_assert (insn && DEBUG_INSN_P (insn));
2881 break;
2882
2883 case SET:
2884 gcc_unreachable ();
2885
2886 default:
2887 break;
2888 }
2889
2890 /* Process each of our operands recursively. If any have changed, make a
2891 copy of the rtx. */
2892 fmt = GET_RTX_FORMAT (code);
2893 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2894 {
2895 if (*fmt == 'e')
2896 {
2897 new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false,
2898 for_costs);
2899 if (new_rtx != XEXP (x, i) && ! copied)
2900 {
2901 x = shallow_copy_rtx (x);
2902 copied = 1;
2903 }
2904 XEXP (x, i) = new_rtx;
2905 }
2906 else if (*fmt == 'E')
2907 {
2908 int copied_vec = 0;
2909 for (j = 0; j < XVECLEN (x, i); j++)
2910 {
2911 new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false,
2912 for_costs);
2913 if (new_rtx != XVECEXP (x, i, j) && ! copied_vec)
2914 {
2915 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2916 XVEC (x, i)->elem);
2917 if (! copied)
2918 {
2919 x = shallow_copy_rtx (x);
2920 copied = 1;
2921 }
2922 XVEC (x, i) = new_v;
2923 copied_vec = 1;
2924 }
2925 XVECEXP (x, i, j) = new_rtx;
2926 }
2927 }
2928 }
2929
2930 return x;
2931 }
2932
2933 rtx
eliminate_regs(rtx x,machine_mode mem_mode,rtx insn)2934 eliminate_regs (rtx x, machine_mode mem_mode, rtx insn)
2935 {
2936 if (reg_eliminate == NULL)
2937 {
2938 gcc_assert (targetm.no_register_allocation);
2939 return x;
2940 }
2941 return eliminate_regs_1 (x, mem_mode, insn, false, false);
2942 }
2943
2944 /* Scan rtx X for modifications of elimination target registers. Update
2945 the table of eliminables to reflect the changed state. MEM_MODE is
2946 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2947
2948 static void
elimination_effects(rtx x,machine_mode mem_mode)2949 elimination_effects (rtx x, machine_mode mem_mode)
2950 {
2951 enum rtx_code code = GET_CODE (x);
2952 struct elim_table *ep;
2953 int regno;
2954 int i, j;
2955 const char *fmt;
2956
2957 switch (code)
2958 {
2959 CASE_CONST_ANY:
2960 case CONST:
2961 case SYMBOL_REF:
2962 case CODE_LABEL:
2963 case PC:
2964 case ASM_INPUT:
2965 case ADDR_VEC:
2966 case ADDR_DIFF_VEC:
2967 case RETURN:
2968 return;
2969
2970 case REG:
2971 regno = REGNO (x);
2972
2973 /* First handle the case where we encounter a bare register that
2974 is eliminable. Replace it with a PLUS. */
2975 if (regno < FIRST_PSEUDO_REGISTER)
2976 {
2977 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2978 ep++)
2979 if (ep->from_rtx == x && ep->can_eliminate)
2980 {
2981 if (! mem_mode)
2982 ep->ref_outside_mem = 1;
2983 return;
2984 }
2985
2986 }
2987 else if (reg_renumber[regno] < 0
2988 && reg_equivs
2989 && reg_equiv_constant (regno)
2990 && ! function_invariant_p (reg_equiv_constant (regno)))
2991 elimination_effects (reg_equiv_constant (regno), mem_mode);
2992 return;
2993
2994 case PRE_INC:
2995 case POST_INC:
2996 case PRE_DEC:
2997 case POST_DEC:
2998 case POST_MODIFY:
2999 case PRE_MODIFY:
3000 /* If we modify the source of an elimination rule, disable it. */
3001 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3002 if (ep->from_rtx == XEXP (x, 0))
3003 ep->can_eliminate = 0;
3004
3005 /* If we modify the target of an elimination rule by adding a constant,
3006 update its offset. If we modify the target in any other way, we'll
3007 have to disable the rule as well. */
3008 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3009 if (ep->to_rtx == XEXP (x, 0))
3010 {
3011 poly_int64 size = GET_MODE_SIZE (mem_mode);
3012
3013 /* If more bytes than MEM_MODE are pushed, account for them. */
3014 #ifdef PUSH_ROUNDING
3015 if (ep->to_rtx == stack_pointer_rtx)
3016 size = PUSH_ROUNDING (size);
3017 #endif
3018 if (code == PRE_DEC || code == POST_DEC)
3019 ep->offset += size;
3020 else if (code == PRE_INC || code == POST_INC)
3021 ep->offset -= size;
3022 else if (code == PRE_MODIFY || code == POST_MODIFY)
3023 {
3024 if (GET_CODE (XEXP (x, 1)) == PLUS
3025 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
3026 && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
3027 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
3028 else
3029 ep->can_eliminate = 0;
3030 }
3031 }
3032
3033 /* These two aren't unary operators. */
3034 if (code == POST_MODIFY || code == PRE_MODIFY)
3035 break;
3036
3037 /* Fall through to generic unary operation case. */
3038 gcc_fallthrough ();
3039 case STRICT_LOW_PART:
3040 case NEG: case NOT:
3041 case SIGN_EXTEND: case ZERO_EXTEND:
3042 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
3043 case FLOAT: case FIX:
3044 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
3045 case ABS:
3046 case SQRT:
3047 case FFS:
3048 case CLZ:
3049 case CTZ:
3050 case POPCOUNT:
3051 case PARITY:
3052 case BSWAP:
3053 elimination_effects (XEXP (x, 0), mem_mode);
3054 return;
3055
3056 case SUBREG:
3057 if (REG_P (SUBREG_REG (x))
3058 && !paradoxical_subreg_p (x)
3059 && reg_equivs
3060 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x))) != 0)
3061 return;
3062
3063 elimination_effects (SUBREG_REG (x), mem_mode);
3064 return;
3065
3066 case USE:
3067 /* If using a register that is the source of an eliminate we still
3068 think can be performed, note it cannot be performed since we don't
3069 know how this register is used. */
3070 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3071 if (ep->from_rtx == XEXP (x, 0))
3072 ep->can_eliminate = 0;
3073
3074 elimination_effects (XEXP (x, 0), mem_mode);
3075 return;
3076
3077 case CLOBBER:
3078 /* If clobbering a register that is the replacement register for an
3079 elimination we still think can be performed, note that it cannot
3080 be performed. Otherwise, we need not be concerned about it. */
3081 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3082 if (ep->to_rtx == XEXP (x, 0))
3083 ep->can_eliminate = 0;
3084
3085 elimination_effects (XEXP (x, 0), mem_mode);
3086 return;
3087
3088 case SET:
3089 /* Check for setting a register that we know about. */
3090 if (REG_P (SET_DEST (x)))
3091 {
3092 /* See if this is setting the replacement register for an
3093 elimination.
3094
3095 If DEST is the hard frame pointer, we do nothing because we
3096 assume that all assignments to the frame pointer are for
3097 non-local gotos and are being done at a time when they are valid
3098 and do not disturb anything else. Some machines want to
3099 eliminate a fake argument pointer (or even a fake frame pointer)
3100 with either the real frame or the stack pointer. Assignments to
3101 the hard frame pointer must not prevent this elimination. */
3102
3103 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3104 ep++)
3105 if (ep->to_rtx == SET_DEST (x)
3106 && SET_DEST (x) != hard_frame_pointer_rtx)
3107 {
3108 /* If it is being incremented, adjust the offset. Otherwise,
3109 this elimination can't be done. */
3110 rtx src = SET_SRC (x);
3111
3112 if (GET_CODE (src) == PLUS
3113 && XEXP (src, 0) == SET_DEST (x)
3114 && CONST_INT_P (XEXP (src, 1)))
3115 ep->offset -= INTVAL (XEXP (src, 1));
3116 else
3117 ep->can_eliminate = 0;
3118 }
3119 }
3120
3121 elimination_effects (SET_DEST (x), VOIDmode);
3122 elimination_effects (SET_SRC (x), VOIDmode);
3123 return;
3124
3125 case MEM:
3126 /* Our only special processing is to pass the mode of the MEM to our
3127 recursive call. */
3128 elimination_effects (XEXP (x, 0), GET_MODE (x));
3129 return;
3130
3131 default:
3132 break;
3133 }
3134
3135 fmt = GET_RTX_FORMAT (code);
3136 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3137 {
3138 if (*fmt == 'e')
3139 elimination_effects (XEXP (x, i), mem_mode);
3140 else if (*fmt == 'E')
3141 for (j = 0; j < XVECLEN (x, i); j++)
3142 elimination_effects (XVECEXP (x, i, j), mem_mode);
3143 }
3144 }
3145
3146 /* Descend through rtx X and verify that no references to eliminable registers
3147 remain. If any do remain, mark the involved register as not
3148 eliminable. */
3149
3150 static void
check_eliminable_occurrences(rtx x)3151 check_eliminable_occurrences (rtx x)
3152 {
3153 const char *fmt;
3154 int i;
3155 enum rtx_code code;
3156
3157 if (x == 0)
3158 return;
3159
3160 code = GET_CODE (x);
3161
3162 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
3163 {
3164 struct elim_table *ep;
3165
3166 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3167 if (ep->from_rtx == x)
3168 ep->can_eliminate = 0;
3169 return;
3170 }
3171
3172 fmt = GET_RTX_FORMAT (code);
3173 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3174 {
3175 if (*fmt == 'e')
3176 check_eliminable_occurrences (XEXP (x, i));
3177 else if (*fmt == 'E')
3178 {
3179 int j;
3180 for (j = 0; j < XVECLEN (x, i); j++)
3181 check_eliminable_occurrences (XVECEXP (x, i, j));
3182 }
3183 }
3184 }
3185
3186 /* Scan INSN and eliminate all eliminable registers in it.
3187
3188 If REPLACE is nonzero, do the replacement destructively. Also
3189 delete the insn as dead it if it is setting an eliminable register.
3190
3191 If REPLACE is zero, do all our allocations in reload_obstack.
3192
3193 If no eliminations were done and this insn doesn't require any elimination
3194 processing (these are not identical conditions: it might be updating sp,
3195 but not referencing fp; this needs to be seen during reload_as_needed so
3196 that the offset between fp and sp can be taken into consideration), zero
3197 is returned. Otherwise, 1 is returned. */
3198
3199 static int
eliminate_regs_in_insn(rtx_insn * insn,int replace)3200 eliminate_regs_in_insn (rtx_insn *insn, int replace)
3201 {
3202 int icode = recog_memoized (insn);
3203 rtx old_body = PATTERN (insn);
3204 int insn_is_asm = asm_noperands (old_body) >= 0;
3205 rtx old_set = single_set (insn);
3206 rtx new_body;
3207 int val = 0;
3208 int i;
3209 rtx substed_operand[MAX_RECOG_OPERANDS];
3210 rtx orig_operand[MAX_RECOG_OPERANDS];
3211 struct elim_table *ep;
3212 rtx plus_src, plus_cst_src;
3213
3214 if (! insn_is_asm && icode < 0)
3215 {
3216 gcc_assert (DEBUG_INSN_P (insn)
3217 || GET_CODE (PATTERN (insn)) == USE
3218 || GET_CODE (PATTERN (insn)) == CLOBBER
3219 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
3220 if (DEBUG_BIND_INSN_P (insn))
3221 INSN_VAR_LOCATION_LOC (insn)
3222 = eliminate_regs (INSN_VAR_LOCATION_LOC (insn), VOIDmode, insn);
3223 return 0;
3224 }
3225
3226 /* We allow one special case which happens to work on all machines we
3227 currently support: a single set with the source or a REG_EQUAL
3228 note being a PLUS of an eliminable register and a constant. */
3229 plus_src = plus_cst_src = 0;
3230 if (old_set && REG_P (SET_DEST (old_set)))
3231 {
3232 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3233 plus_src = SET_SRC (old_set);
3234 /* First see if the source is of the form (plus (...) CST). */
3235 if (plus_src
3236 && CONST_INT_P (XEXP (plus_src, 1)))
3237 plus_cst_src = plus_src;
3238 else if (REG_P (SET_SRC (old_set))
3239 || plus_src)
3240 {
3241 /* Otherwise, see if we have a REG_EQUAL note of the form
3242 (plus (...) CST). */
3243 rtx links;
3244 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3245 {
3246 if ((REG_NOTE_KIND (links) == REG_EQUAL
3247 || REG_NOTE_KIND (links) == REG_EQUIV)
3248 && GET_CODE (XEXP (links, 0)) == PLUS
3249 && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3250 {
3251 plus_cst_src = XEXP (links, 0);
3252 break;
3253 }
3254 }
3255 }
3256
3257 /* Check that the first operand of the PLUS is a hard reg or
3258 the lowpart subreg of one. */
3259 if (plus_cst_src)
3260 {
3261 rtx reg = XEXP (plus_cst_src, 0);
3262 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3263 reg = SUBREG_REG (reg);
3264
3265 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3266 plus_cst_src = 0;
3267 }
3268 }
3269 if (plus_cst_src)
3270 {
3271 rtx reg = XEXP (plus_cst_src, 0);
3272 poly_int64 offset = INTVAL (XEXP (plus_cst_src, 1));
3273
3274 if (GET_CODE (reg) == SUBREG)
3275 reg = SUBREG_REG (reg);
3276
3277 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3278 if (ep->from_rtx == reg && ep->can_eliminate)
3279 {
3280 rtx to_rtx = ep->to_rtx;
3281 offset += ep->offset;
3282 offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src));
3283
3284 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3285 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3286 to_rtx);
3287 /* If we have a nonzero offset, and the source is already
3288 a simple REG, the following transformation would
3289 increase the cost of the insn by replacing a simple REG
3290 with (plus (reg sp) CST). So try only when we already
3291 had a PLUS before. */
3292 if (known_eq (offset, 0) || plus_src)
3293 {
3294 rtx new_src = plus_constant (GET_MODE (to_rtx),
3295 to_rtx, offset);
3296
3297 new_body = old_body;
3298 if (! replace)
3299 {
3300 new_body = copy_insn (old_body);
3301 if (REG_NOTES (insn))
3302 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3303 }
3304 PATTERN (insn) = new_body;
3305 old_set = single_set (insn);
3306
3307 /* First see if this insn remains valid when we make the
3308 change. If not, try to replace the whole pattern with
3309 a simple set (this may help if the original insn was a
3310 PARALLEL that was only recognized as single_set due to
3311 REG_UNUSED notes). If this isn't valid either, keep
3312 the INSN_CODE the same and let reload fix it up. */
3313 if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3314 {
3315 rtx new_pat = gen_rtx_SET (SET_DEST (old_set), new_src);
3316
3317 if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3318 SET_SRC (old_set) = new_src;
3319 }
3320 }
3321 else
3322 break;
3323
3324 val = 1;
3325 /* This can't have an effect on elimination offsets, so skip right
3326 to the end. */
3327 goto done;
3328 }
3329 }
3330
3331 /* Determine the effects of this insn on elimination offsets. */
3332 elimination_effects (old_body, VOIDmode);
3333
3334 /* Eliminate all eliminable registers occurring in operands that
3335 can be handled by reload. */
3336 extract_insn (insn);
3337 for (i = 0; i < recog_data.n_operands; i++)
3338 {
3339 orig_operand[i] = recog_data.operand[i];
3340 substed_operand[i] = recog_data.operand[i];
3341
3342 /* For an asm statement, every operand is eliminable. */
3343 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3344 {
3345 bool is_set_src, in_plus;
3346
3347 /* Check for setting a register that we know about. */
3348 if (recog_data.operand_type[i] != OP_IN
3349 && REG_P (orig_operand[i]))
3350 {
3351 /* If we are assigning to a register that can be eliminated, it
3352 must be as part of a PARALLEL, since the code above handles
3353 single SETs. We must indicate that we can no longer
3354 eliminate this reg. */
3355 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3356 ep++)
3357 if (ep->from_rtx == orig_operand[i])
3358 ep->can_eliminate = 0;
3359 }
3360
3361 /* Companion to the above plus substitution, we can allow
3362 invariants as the source of a plain move. */
3363 is_set_src = false;
3364 if (old_set
3365 && recog_data.operand_loc[i] == &SET_SRC (old_set))
3366 is_set_src = true;
3367 in_plus = false;
3368 if (plus_src
3369 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3370 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3371 in_plus = true;
3372
3373 substed_operand[i]
3374 = eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3375 replace ? insn : NULL_RTX,
3376 is_set_src || in_plus, false);
3377 if (substed_operand[i] != orig_operand[i])
3378 val = 1;
3379 /* Terminate the search in check_eliminable_occurrences at
3380 this point. */
3381 *recog_data.operand_loc[i] = 0;
3382
3383 /* If an output operand changed from a REG to a MEM and INSN is an
3384 insn, write a CLOBBER insn. */
3385 if (recog_data.operand_type[i] != OP_IN
3386 && REG_P (orig_operand[i])
3387 && MEM_P (substed_operand[i])
3388 && replace)
3389 emit_insn_after (gen_clobber (orig_operand[i]), insn);
3390 }
3391 }
3392
3393 for (i = 0; i < recog_data.n_dups; i++)
3394 *recog_data.dup_loc[i]
3395 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3396
3397 /* If any eliminable remain, they aren't eliminable anymore. */
3398 check_eliminable_occurrences (old_body);
3399
3400 /* Substitute the operands; the new values are in the substed_operand
3401 array. */
3402 for (i = 0; i < recog_data.n_operands; i++)
3403 *recog_data.operand_loc[i] = substed_operand[i];
3404 for (i = 0; i < recog_data.n_dups; i++)
3405 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3406
3407 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3408 re-recognize the insn. We do this in case we had a simple addition
3409 but now can do this as a load-address. This saves an insn in this
3410 common case.
3411 If re-recognition fails, the old insn code number will still be used,
3412 and some register operands may have changed into PLUS expressions.
3413 These will be handled by find_reloads by loading them into a register
3414 again. */
3415
3416 if (val)
3417 {
3418 /* If we aren't replacing things permanently and we changed something,
3419 make another copy to ensure that all the RTL is new. Otherwise
3420 things can go wrong if find_reload swaps commutative operands
3421 and one is inside RTL that has been copied while the other is not. */
3422 new_body = old_body;
3423 if (! replace)
3424 {
3425 new_body = copy_insn (old_body);
3426 if (REG_NOTES (insn))
3427 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3428 }
3429 PATTERN (insn) = new_body;
3430
3431 /* If we had a move insn but now we don't, rerecognize it. This will
3432 cause spurious re-recognition if the old move had a PARALLEL since
3433 the new one still will, but we can't call single_set without
3434 having put NEW_BODY into the insn and the re-recognition won't
3435 hurt in this rare case. */
3436 /* ??? Why this huge if statement - why don't we just rerecognize the
3437 thing always? */
3438 if (! insn_is_asm
3439 && old_set != 0
3440 && ((REG_P (SET_SRC (old_set))
3441 && (GET_CODE (new_body) != SET
3442 || !REG_P (SET_SRC (new_body))))
3443 /* If this was a load from or store to memory, compare
3444 the MEM in recog_data.operand to the one in the insn.
3445 If they are not equal, then rerecognize the insn. */
3446 || (old_set != 0
3447 && ((MEM_P (SET_SRC (old_set))
3448 && SET_SRC (old_set) != recog_data.operand[1])
3449 || (MEM_P (SET_DEST (old_set))
3450 && SET_DEST (old_set) != recog_data.operand[0])))
3451 /* If this was an add insn before, rerecognize. */
3452 || GET_CODE (SET_SRC (old_set)) == PLUS))
3453 {
3454 int new_icode = recog (PATTERN (insn), insn, 0);
3455 if (new_icode >= 0)
3456 INSN_CODE (insn) = new_icode;
3457 }
3458 }
3459
3460 /* Restore the old body. If there were any changes to it, we made a copy
3461 of it while the changes were still in place, so we'll correctly return
3462 a modified insn below. */
3463 if (! replace)
3464 {
3465 /* Restore the old body. */
3466 for (i = 0; i < recog_data.n_operands; i++)
3467 /* Restoring a top-level match_parallel would clobber the new_body
3468 we installed in the insn. */
3469 if (recog_data.operand_loc[i] != &PATTERN (insn))
3470 *recog_data.operand_loc[i] = orig_operand[i];
3471 for (i = 0; i < recog_data.n_dups; i++)
3472 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3473 }
3474
3475 /* Update all elimination pairs to reflect the status after the current
3476 insn. The changes we make were determined by the earlier call to
3477 elimination_effects.
3478
3479 We also detect cases where register elimination cannot be done,
3480 namely, if a register would be both changed and referenced outside a MEM
3481 in the resulting insn since such an insn is often undefined and, even if
3482 not, we cannot know what meaning will be given to it. Note that it is
3483 valid to have a register used in an address in an insn that changes it
3484 (presumably with a pre- or post-increment or decrement).
3485
3486 If anything changes, return nonzero. */
3487
3488 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3489 {
3490 if (maybe_ne (ep->previous_offset, ep->offset) && ep->ref_outside_mem)
3491 ep->can_eliminate = 0;
3492
3493 ep->ref_outside_mem = 0;
3494
3495 if (maybe_ne (ep->previous_offset, ep->offset))
3496 val = 1;
3497 }
3498
3499 done:
3500 /* If we changed something, perform elimination in REG_NOTES. This is
3501 needed even when REPLACE is zero because a REG_DEAD note might refer
3502 to a register that we eliminate and could cause a different number
3503 of spill registers to be needed in the final reload pass than in
3504 the pre-passes. */
3505 if (val && REG_NOTES (insn) != 0)
3506 REG_NOTES (insn)
3507 = eliminate_regs_1 (REG_NOTES (insn), VOIDmode, REG_NOTES (insn), true,
3508 false);
3509
3510 return val;
3511 }
3512
3513 /* Like eliminate_regs_in_insn, but only estimate costs for the use of the
3514 register allocator. INSN is the instruction we need to examine, we perform
3515 eliminations in its operands and record cases where eliminating a reg with
3516 an invariant equivalence would add extra cost. */
3517
3518 #pragma GCC diagnostic push
3519 #pragma GCC diagnostic warning "-Wmaybe-uninitialized"
3520 static void
elimination_costs_in_insn(rtx_insn * insn)3521 elimination_costs_in_insn (rtx_insn *insn)
3522 {
3523 int icode = recog_memoized (insn);
3524 rtx old_body = PATTERN (insn);
3525 int insn_is_asm = asm_noperands (old_body) >= 0;
3526 rtx old_set = single_set (insn);
3527 int i;
3528 rtx orig_operand[MAX_RECOG_OPERANDS];
3529 rtx orig_dup[MAX_RECOG_OPERANDS];
3530 struct elim_table *ep;
3531 rtx plus_src, plus_cst_src;
3532 bool sets_reg_p;
3533
3534 if (! insn_is_asm && icode < 0)
3535 {
3536 gcc_assert (DEBUG_INSN_P (insn)
3537 || GET_CODE (PATTERN (insn)) == USE
3538 || GET_CODE (PATTERN (insn)) == CLOBBER
3539 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
3540 return;
3541 }
3542
3543 if (old_set != 0 && REG_P (SET_DEST (old_set))
3544 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3545 {
3546 /* Check for setting an eliminable register. */
3547 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3548 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3549 return;
3550 }
3551
3552 /* We allow one special case which happens to work on all machines we
3553 currently support: a single set with the source or a REG_EQUAL
3554 note being a PLUS of an eliminable register and a constant. */
3555 plus_src = plus_cst_src = 0;
3556 sets_reg_p = false;
3557 if (old_set && REG_P (SET_DEST (old_set)))
3558 {
3559 sets_reg_p = true;
3560 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3561 plus_src = SET_SRC (old_set);
3562 /* First see if the source is of the form (plus (...) CST). */
3563 if (plus_src
3564 && CONST_INT_P (XEXP (plus_src, 1)))
3565 plus_cst_src = plus_src;
3566 else if (REG_P (SET_SRC (old_set))
3567 || plus_src)
3568 {
3569 /* Otherwise, see if we have a REG_EQUAL note of the form
3570 (plus (...) CST). */
3571 rtx links;
3572 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3573 {
3574 if ((REG_NOTE_KIND (links) == REG_EQUAL
3575 || REG_NOTE_KIND (links) == REG_EQUIV)
3576 && GET_CODE (XEXP (links, 0)) == PLUS
3577 && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3578 {
3579 plus_cst_src = XEXP (links, 0);
3580 break;
3581 }
3582 }
3583 }
3584 }
3585
3586 /* Determine the effects of this insn on elimination offsets. */
3587 elimination_effects (old_body, VOIDmode);
3588
3589 /* Eliminate all eliminable registers occurring in operands that
3590 can be handled by reload. */
3591 extract_insn (insn);
3592 int n_dups = recog_data.n_dups;
3593 for (i = 0; i < n_dups; i++)
3594 orig_dup[i] = *recog_data.dup_loc[i];
3595
3596 int n_operands = recog_data.n_operands;
3597 for (i = 0; i < n_operands; i++)
3598 {
3599 orig_operand[i] = recog_data.operand[i];
3600
3601 /* For an asm statement, every operand is eliminable. */
3602 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3603 {
3604 bool is_set_src, in_plus;
3605
3606 /* Check for setting a register that we know about. */
3607 if (recog_data.operand_type[i] != OP_IN
3608 && REG_P (orig_operand[i]))
3609 {
3610 /* If we are assigning to a register that can be eliminated, it
3611 must be as part of a PARALLEL, since the code above handles
3612 single SETs. We must indicate that we can no longer
3613 eliminate this reg. */
3614 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3615 ep++)
3616 if (ep->from_rtx == orig_operand[i])
3617 ep->can_eliminate = 0;
3618 }
3619
3620 /* Companion to the above plus substitution, we can allow
3621 invariants as the source of a plain move. */
3622 is_set_src = false;
3623 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3624 is_set_src = true;
3625 if (is_set_src && !sets_reg_p)
3626 note_reg_elim_costly (SET_SRC (old_set), insn);
3627 in_plus = false;
3628 if (plus_src && sets_reg_p
3629 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3630 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3631 in_plus = true;
3632
3633 eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3634 NULL_RTX,
3635 is_set_src || in_plus, true);
3636 /* Terminate the search in check_eliminable_occurrences at
3637 this point. */
3638 *recog_data.operand_loc[i] = 0;
3639 }
3640 }
3641
3642 for (i = 0; i < n_dups; i++)
3643 *recog_data.dup_loc[i]
3644 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3645
3646 /* If any eliminable remain, they aren't eliminable anymore. */
3647 check_eliminable_occurrences (old_body);
3648
3649 /* Restore the old body. */
3650 for (i = 0; i < n_operands; i++)
3651 *recog_data.operand_loc[i] = orig_operand[i];
3652 for (i = 0; i < n_dups; i++)
3653 *recog_data.dup_loc[i] = orig_dup[i];
3654
3655 /* Update all elimination pairs to reflect the status after the current
3656 insn. The changes we make were determined by the earlier call to
3657 elimination_effects. */
3658
3659 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3660 {
3661 if (maybe_ne (ep->previous_offset, ep->offset) && ep->ref_outside_mem)
3662 ep->can_eliminate = 0;
3663
3664 ep->ref_outside_mem = 0;
3665 }
3666
3667 return;
3668 }
3669 #pragma GCC diagnostic pop
3670
3671 /* Loop through all elimination pairs.
3672 Recalculate the number not at initial offset.
3673
3674 Compute the maximum offset (minimum offset if the stack does not
3675 grow downward) for each elimination pair. */
3676
3677 static void
update_eliminable_offsets(void)3678 update_eliminable_offsets (void)
3679 {
3680 struct elim_table *ep;
3681
3682 num_not_at_initial_offset = 0;
3683 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3684 {
3685 ep->previous_offset = ep->offset;
3686 if (ep->can_eliminate && maybe_ne (ep->offset, ep->initial_offset))
3687 num_not_at_initial_offset++;
3688 }
3689 }
3690
3691 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3692 replacement we currently believe is valid, mark it as not eliminable if X
3693 modifies DEST in any way other than by adding a constant integer to it.
3694
3695 If DEST is the frame pointer, we do nothing because we assume that
3696 all assignments to the hard frame pointer are nonlocal gotos and are being
3697 done at a time when they are valid and do not disturb anything else.
3698 Some machines want to eliminate a fake argument pointer with either the
3699 frame or stack pointer. Assignments to the hard frame pointer must not
3700 prevent this elimination.
3701
3702 Called via note_stores from reload before starting its passes to scan
3703 the insns of the function. */
3704
3705 static void
mark_not_eliminable(rtx dest,const_rtx x,void * data ATTRIBUTE_UNUSED)3706 mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
3707 {
3708 unsigned int i;
3709
3710 /* A SUBREG of a hard register here is just changing its mode. We should
3711 not see a SUBREG of an eliminable hard register, but check just in
3712 case. */
3713 if (GET_CODE (dest) == SUBREG)
3714 dest = SUBREG_REG (dest);
3715
3716 if (dest == hard_frame_pointer_rtx)
3717 return;
3718
3719 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3720 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3721 && (GET_CODE (x) != SET
3722 || GET_CODE (SET_SRC (x)) != PLUS
3723 || XEXP (SET_SRC (x), 0) != dest
3724 || !CONST_INT_P (XEXP (SET_SRC (x), 1))))
3725 {
3726 reg_eliminate[i].can_eliminate_previous
3727 = reg_eliminate[i].can_eliminate = 0;
3728 num_eliminable--;
3729 }
3730 }
3731
3732 /* Verify that the initial elimination offsets did not change since the
3733 last call to set_initial_elim_offsets. This is used to catch cases
3734 where something illegal happened during reload_as_needed that could
3735 cause incorrect code to be generated if we did not check for it. */
3736
3737 static bool
verify_initial_elim_offsets(void)3738 verify_initial_elim_offsets (void)
3739 {
3740 poly_int64 t;
3741 struct elim_table *ep;
3742
3743 if (!num_eliminable)
3744 return true;
3745
3746 targetm.compute_frame_layout ();
3747 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3748 {
3749 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3750 if (maybe_ne (t, ep->initial_offset))
3751 return false;
3752 }
3753
3754 return true;
3755 }
3756
3757 /* Reset all offsets on eliminable registers to their initial values. */
3758
3759 static void
set_initial_elim_offsets(void)3760 set_initial_elim_offsets (void)
3761 {
3762 struct elim_table *ep = reg_eliminate;
3763
3764 targetm.compute_frame_layout ();
3765 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3766 {
3767 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3768 ep->previous_offset = ep->offset = ep->initial_offset;
3769 }
3770
3771 num_not_at_initial_offset = 0;
3772 }
3773
3774 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3775
3776 static void
set_initial_eh_label_offset(rtx label)3777 set_initial_eh_label_offset (rtx label)
3778 {
3779 set_label_offsets (label, NULL, 1);
3780 }
3781
3782 /* Initialize the known label offsets.
3783 Set a known offset for each forced label to be at the initial offset
3784 of each elimination. We do this because we assume that all
3785 computed jumps occur from a location where each elimination is
3786 at its initial offset.
3787 For all other labels, show that we don't know the offsets. */
3788
3789 static void
set_initial_label_offsets(void)3790 set_initial_label_offsets (void)
3791 {
3792 memset (offsets_known_at, 0, num_labels);
3793
3794 unsigned int i;
3795 rtx_insn *insn;
3796 FOR_EACH_VEC_SAFE_ELT (forced_labels, i, insn)
3797 set_label_offsets (insn, NULL, 1);
3798
3799 for (rtx_insn_list *x = nonlocal_goto_handler_labels; x; x = x->next ())
3800 if (x->insn ())
3801 set_label_offsets (x->insn (), NULL, 1);
3802
3803 for_each_eh_label (set_initial_eh_label_offset);
3804 }
3805
3806 /* Set all elimination offsets to the known values for the code label given
3807 by INSN. */
3808
3809 static void
set_offsets_for_label(rtx_insn * insn)3810 set_offsets_for_label (rtx_insn *insn)
3811 {
3812 unsigned int i;
3813 int label_nr = CODE_LABEL_NUMBER (insn);
3814 struct elim_table *ep;
3815
3816 num_not_at_initial_offset = 0;
3817 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3818 {
3819 ep->offset = ep->previous_offset
3820 = offsets_at[label_nr - first_label_num][i];
3821 if (ep->can_eliminate && maybe_ne (ep->offset, ep->initial_offset))
3822 num_not_at_initial_offset++;
3823 }
3824 }
3825
3826 /* See if anything that happened changes which eliminations are valid.
3827 For example, on the SPARC, whether or not the frame pointer can
3828 be eliminated can depend on what registers have been used. We need
3829 not check some conditions again (such as flag_omit_frame_pointer)
3830 since they can't have changed. */
3831
3832 static void
update_eliminables(HARD_REG_SET * pset)3833 update_eliminables (HARD_REG_SET *pset)
3834 {
3835 int previous_frame_pointer_needed = frame_pointer_needed;
3836 struct elim_table *ep;
3837
3838 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3839 if ((ep->from == HARD_FRAME_POINTER_REGNUM
3840 && targetm.frame_pointer_required ())
3841 || ! targetm.can_eliminate (ep->from, ep->to)
3842 )
3843 ep->can_eliminate = 0;
3844
3845 /* Look for the case where we have discovered that we can't replace
3846 register A with register B and that means that we will now be
3847 trying to replace register A with register C. This means we can
3848 no longer replace register C with register B and we need to disable
3849 such an elimination, if it exists. This occurs often with A == ap,
3850 B == sp, and C == fp. */
3851
3852 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3853 {
3854 struct elim_table *op;
3855 int new_to = -1;
3856
3857 if (! ep->can_eliminate && ep->can_eliminate_previous)
3858 {
3859 /* Find the current elimination for ep->from, if there is a
3860 new one. */
3861 for (op = reg_eliminate;
3862 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3863 if (op->from == ep->from && op->can_eliminate)
3864 {
3865 new_to = op->to;
3866 break;
3867 }
3868
3869 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3870 disable it. */
3871 for (op = reg_eliminate;
3872 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3873 if (op->from == new_to && op->to == ep->to)
3874 op->can_eliminate = 0;
3875 }
3876 }
3877
3878 /* See if any registers that we thought we could eliminate the previous
3879 time are no longer eliminable. If so, something has changed and we
3880 must spill the register. Also, recompute the number of eliminable
3881 registers and see if the frame pointer is needed; it is if there is
3882 no elimination of the frame pointer that we can perform. */
3883
3884 frame_pointer_needed = 1;
3885 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3886 {
3887 if (ep->can_eliminate
3888 && ep->from == FRAME_POINTER_REGNUM
3889 && ep->to != HARD_FRAME_POINTER_REGNUM
3890 && (! SUPPORTS_STACK_ALIGNMENT
3891 || ! crtl->stack_realign_needed))
3892 frame_pointer_needed = 0;
3893
3894 if (! ep->can_eliminate && ep->can_eliminate_previous)
3895 {
3896 ep->can_eliminate_previous = 0;
3897 SET_HARD_REG_BIT (*pset, ep->from);
3898 num_eliminable--;
3899 }
3900 }
3901
3902 /* If we didn't need a frame pointer last time, but we do now, spill
3903 the hard frame pointer. */
3904 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3905 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3906 }
3907
3908 /* Call update_eliminables an spill any registers we can't eliminate anymore.
3909 Return true iff a register was spilled. */
3910
3911 static bool
update_eliminables_and_spill(void)3912 update_eliminables_and_spill (void)
3913 {
3914 int i;
3915 bool did_spill = false;
3916 HARD_REG_SET to_spill;
3917 CLEAR_HARD_REG_SET (to_spill);
3918 update_eliminables (&to_spill);
3919 used_spill_regs &= ~to_spill;
3920
3921 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3922 if (TEST_HARD_REG_BIT (to_spill, i))
3923 {
3924 spill_hard_reg (i, 1);
3925 did_spill = true;
3926
3927 /* Regardless of the state of spills, if we previously had
3928 a register that we thought we could eliminate, but now
3929 cannot eliminate, we must run another pass.
3930
3931 Consider pseudos which have an entry in reg_equiv_* which
3932 reference an eliminable register. We must make another pass
3933 to update reg_equiv_* so that we do not substitute in the
3934 old value from when we thought the elimination could be
3935 performed. */
3936 }
3937 return did_spill;
3938 }
3939
3940 /* Return true if X is used as the target register of an elimination. */
3941
3942 bool
elimination_target_reg_p(rtx x)3943 elimination_target_reg_p (rtx x)
3944 {
3945 struct elim_table *ep;
3946
3947 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3948 if (ep->to_rtx == x && ep->can_eliminate)
3949 return true;
3950
3951 return false;
3952 }
3953
3954 /* Initialize the table of registers to eliminate.
3955 Pre-condition: global flag frame_pointer_needed has been set before
3956 calling this function. */
3957
3958 static void
init_elim_table(void)3959 init_elim_table (void)
3960 {
3961 struct elim_table *ep;
3962 const struct elim_table_1 *ep1;
3963
3964 if (!reg_eliminate)
3965 reg_eliminate = XCNEWVEC (struct elim_table, NUM_ELIMINABLE_REGS);
3966
3967 num_eliminable = 0;
3968
3969 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3970 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3971 {
3972 ep->from = ep1->from;
3973 ep->to = ep1->to;
3974 ep->can_eliminate = ep->can_eliminate_previous
3975 = (targetm.can_eliminate (ep->from, ep->to)
3976 && ! (ep->to == STACK_POINTER_REGNUM
3977 && frame_pointer_needed
3978 && (! SUPPORTS_STACK_ALIGNMENT
3979 || ! stack_realign_fp)));
3980 }
3981
3982 /* Count the number of eliminable registers and build the FROM and TO
3983 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3984 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3985 We depend on this. */
3986 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3987 {
3988 num_eliminable += ep->can_eliminate;
3989 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3990 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3991 }
3992 }
3993
3994 /* Find all the pseudo registers that didn't get hard regs
3995 but do have known equivalent constants or memory slots.
3996 These include parameters (known equivalent to parameter slots)
3997 and cse'd or loop-moved constant memory addresses.
3998
3999 Record constant equivalents in reg_equiv_constant
4000 so they will be substituted by find_reloads.
4001 Record memory equivalents in reg_mem_equiv so they can
4002 be substituted eventually by altering the REG-rtx's. */
4003
4004 static void
init_eliminable_invariants(rtx_insn * first,bool do_subregs)4005 init_eliminable_invariants (rtx_insn *first, bool do_subregs)
4006 {
4007 int i;
4008 rtx_insn *insn;
4009
4010 grow_reg_equivs ();
4011 if (do_subregs)
4012 reg_max_ref_mode = XCNEWVEC (machine_mode, max_regno);
4013 else
4014 reg_max_ref_mode = NULL;
4015
4016 num_eliminable_invariants = 0;
4017
4018 first_label_num = get_first_label_num ();
4019 num_labels = max_label_num () - first_label_num;
4020
4021 /* Allocate the tables used to store offset information at labels. */
4022 offsets_known_at = XNEWVEC (char, num_labels);
4023 offsets_at = (poly_int64_pod (*)[NUM_ELIMINABLE_REGS])
4024 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (poly_int64));
4025
4026 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
4027 to. If DO_SUBREGS is true, also find all paradoxical subregs and
4028 find largest such for each pseudo. FIRST is the head of the insn
4029 list. */
4030
4031 for (insn = first; insn; insn = NEXT_INSN (insn))
4032 {
4033 rtx set = single_set (insn);
4034
4035 /* We may introduce USEs that we want to remove at the end, so
4036 we'll mark them with QImode. Make sure there are no
4037 previously-marked insns left by say regmove. */
4038 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
4039 && GET_MODE (insn) != VOIDmode)
4040 PUT_MODE (insn, VOIDmode);
4041
4042 if (do_subregs && NONDEBUG_INSN_P (insn))
4043 scan_paradoxical_subregs (PATTERN (insn));
4044
4045 if (set != 0 && REG_P (SET_DEST (set)))
4046 {
4047 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
4048 rtx x;
4049
4050 if (! note)
4051 continue;
4052
4053 i = REGNO (SET_DEST (set));
4054 x = XEXP (note, 0);
4055
4056 if (i <= LAST_VIRTUAL_REGISTER)
4057 continue;
4058
4059 /* If flag_pic and we have constant, verify it's legitimate. */
4060 if (!CONSTANT_P (x)
4061 || !flag_pic || LEGITIMATE_PIC_OPERAND_P (x))
4062 {
4063 /* It can happen that a REG_EQUIV note contains a MEM
4064 that is not a legitimate memory operand. As later
4065 stages of reload assume that all addresses found
4066 in the reg_equiv_* arrays were originally legitimate,
4067 we ignore such REG_EQUIV notes. */
4068 if (memory_operand (x, VOIDmode))
4069 {
4070 /* Always unshare the equivalence, so we can
4071 substitute into this insn without touching the
4072 equivalence. */
4073 reg_equiv_memory_loc (i) = copy_rtx (x);
4074 }
4075 else if (function_invariant_p (x))
4076 {
4077 machine_mode mode;
4078
4079 mode = GET_MODE (SET_DEST (set));
4080 if (GET_CODE (x) == PLUS)
4081 {
4082 /* This is PLUS of frame pointer and a constant,
4083 and might be shared. Unshare it. */
4084 reg_equiv_invariant (i) = copy_rtx (x);
4085 num_eliminable_invariants++;
4086 }
4087 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
4088 {
4089 reg_equiv_invariant (i) = x;
4090 num_eliminable_invariants++;
4091 }
4092 else if (targetm.legitimate_constant_p (mode, x))
4093 reg_equiv_constant (i) = x;
4094 else
4095 {
4096 reg_equiv_memory_loc (i) = force_const_mem (mode, x);
4097 if (! reg_equiv_memory_loc (i))
4098 reg_equiv_init (i) = NULL;
4099 }
4100 }
4101 else
4102 {
4103 reg_equiv_init (i) = NULL;
4104 continue;
4105 }
4106 }
4107 else
4108 reg_equiv_init (i) = NULL;
4109 }
4110 }
4111
4112 if (dump_file)
4113 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4114 if (reg_equiv_init (i))
4115 {
4116 fprintf (dump_file, "init_insns for %u: ", i);
4117 print_inline_rtx (dump_file, reg_equiv_init (i), 20);
4118 fprintf (dump_file, "\n");
4119 }
4120 }
4121
4122 /* Indicate that we no longer have known memory locations or constants.
4123 Free all data involved in tracking these. */
4124
4125 static void
free_reg_equiv(void)4126 free_reg_equiv (void)
4127 {
4128 int i;
4129
4130 free (offsets_known_at);
4131 free (offsets_at);
4132 offsets_at = 0;
4133 offsets_known_at = 0;
4134
4135 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4136 if (reg_equiv_alt_mem_list (i))
4137 free_EXPR_LIST_list (®_equiv_alt_mem_list (i));
4138 vec_free (reg_equivs);
4139 }
4140
4141 /* Kick all pseudos out of hard register REGNO.
4142
4143 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
4144 because we found we can't eliminate some register. In the case, no pseudos
4145 are allowed to be in the register, even if they are only in a block that
4146 doesn't require spill registers, unlike the case when we are spilling this
4147 hard reg to produce another spill register.
4148
4149 Return nonzero if any pseudos needed to be kicked out. */
4150
4151 static void
spill_hard_reg(unsigned int regno,int cant_eliminate)4152 spill_hard_reg (unsigned int regno, int cant_eliminate)
4153 {
4154 int i;
4155
4156 if (cant_eliminate)
4157 {
4158 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
4159 df_set_regs_ever_live (regno, true);
4160 }
4161
4162 /* Spill every pseudo reg that was allocated to this reg
4163 or to something that overlaps this reg. */
4164
4165 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4166 if (reg_renumber[i] >= 0
4167 && (unsigned int) reg_renumber[i] <= regno
4168 && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno)
4169 SET_REGNO_REG_SET (&spilled_pseudos, i);
4170 }
4171
4172 /* After spill_hard_reg was called and/or find_reload_regs was run for all
4173 insns that need reloads, this function is used to actually spill pseudo
4174 registers and try to reallocate them. It also sets up the spill_regs
4175 array for use by choose_reload_regs.
4176
4177 GLOBAL nonzero means we should attempt to reallocate any pseudo registers
4178 that we displace from hard registers. */
4179
4180 static int
finish_spills(int global)4181 finish_spills (int global)
4182 {
4183 class insn_chain *chain;
4184 int something_changed = 0;
4185 unsigned i;
4186 reg_set_iterator rsi;
4187
4188 /* Build the spill_regs array for the function. */
4189 /* If there are some registers still to eliminate and one of the spill regs
4190 wasn't ever used before, additional stack space may have to be
4191 allocated to store this register. Thus, we may have changed the offset
4192 between the stack and frame pointers, so mark that something has changed.
4193
4194 One might think that we need only set VAL to 1 if this is a call-used
4195 register. However, the set of registers that must be saved by the
4196 prologue is not identical to the call-used set. For example, the
4197 register used by the call insn for the return PC is a call-used register,
4198 but must be saved by the prologue. */
4199
4200 n_spills = 0;
4201 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4202 if (TEST_HARD_REG_BIT (used_spill_regs, i))
4203 {
4204 spill_reg_order[i] = n_spills;
4205 spill_regs[n_spills++] = i;
4206 if (num_eliminable && ! df_regs_ever_live_p (i))
4207 something_changed = 1;
4208 df_set_regs_ever_live (i, true);
4209 }
4210 else
4211 spill_reg_order[i] = -1;
4212
4213 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
4214 if (reg_renumber[i] >= 0)
4215 {
4216 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
4217 /* Mark it as no longer having a hard register home. */
4218 reg_renumber[i] = -1;
4219 if (ira_conflicts_p)
4220 /* Inform IRA about the change. */
4221 ira_mark_allocation_change (i);
4222 /* We will need to scan everything again. */
4223 something_changed = 1;
4224 }
4225
4226 /* Retry global register allocation if possible. */
4227 if (global && ira_conflicts_p)
4228 {
4229 unsigned int n;
4230
4231 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
4232 /* For every insn that needs reloads, set the registers used as spill
4233 regs in pseudo_forbidden_regs for every pseudo live across the
4234 insn. */
4235 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
4236 {
4237 EXECUTE_IF_SET_IN_REG_SET
4238 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
4239 {
4240 pseudo_forbidden_regs[i] |= chain->used_spill_regs;
4241 }
4242 EXECUTE_IF_SET_IN_REG_SET
4243 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
4244 {
4245 pseudo_forbidden_regs[i] |= chain->used_spill_regs;
4246 }
4247 }
4248
4249 /* Retry allocating the pseudos spilled in IRA and the
4250 reload. For each reg, merge the various reg sets that
4251 indicate which hard regs can't be used, and call
4252 ira_reassign_pseudos. */
4253 for (n = 0, i = FIRST_PSEUDO_REGISTER; i < (unsigned) max_regno; i++)
4254 if (reg_old_renumber[i] != reg_renumber[i])
4255 {
4256 if (reg_renumber[i] < 0)
4257 temp_pseudo_reg_arr[n++] = i;
4258 else
4259 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
4260 }
4261 if (ira_reassign_pseudos (temp_pseudo_reg_arr, n,
4262 bad_spill_regs_global,
4263 pseudo_forbidden_regs, pseudo_previous_regs,
4264 &spilled_pseudos))
4265 something_changed = 1;
4266 }
4267 /* Fix up the register information in the insn chain.
4268 This involves deleting those of the spilled pseudos which did not get
4269 a new hard register home from the live_{before,after} sets. */
4270 for (chain = reload_insn_chain; chain; chain = chain->next)
4271 {
4272 HARD_REG_SET used_by_pseudos;
4273 HARD_REG_SET used_by_pseudos2;
4274
4275 if (! ira_conflicts_p)
4276 {
4277 /* Don't do it for IRA because IRA and the reload still can
4278 assign hard registers to the spilled pseudos on next
4279 reload iterations. */
4280 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
4281 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
4282 }
4283 /* Mark any unallocated hard regs as available for spills. That
4284 makes inheritance work somewhat better. */
4285 if (chain->need_reload)
4286 {
4287 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
4288 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
4289 used_by_pseudos |= used_by_pseudos2;
4290
4291 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
4292 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
4293 /* Value of chain->used_spill_regs from previous iteration
4294 may be not included in the value calculated here because
4295 of possible removing caller-saves insns (see function
4296 delete_caller_save_insns. */
4297 chain->used_spill_regs = ~used_by_pseudos & used_spill_regs;
4298 }
4299 }
4300
4301 CLEAR_REG_SET (&changed_allocation_pseudos);
4302 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4303 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
4304 {
4305 int regno = reg_renumber[i];
4306 if (reg_old_renumber[i] == regno)
4307 continue;
4308
4309 SET_REGNO_REG_SET (&changed_allocation_pseudos, i);
4310
4311 alter_reg (i, reg_old_renumber[i], false);
4312 reg_old_renumber[i] = regno;
4313 if (dump_file)
4314 {
4315 if (regno == -1)
4316 fprintf (dump_file, " Register %d now on stack.\n\n", i);
4317 else
4318 fprintf (dump_file, " Register %d now in %d.\n\n",
4319 i, reg_renumber[i]);
4320 }
4321 }
4322
4323 return something_changed;
4324 }
4325
4326 /* Find all paradoxical subregs within X and update reg_max_ref_mode. */
4327
4328 static void
scan_paradoxical_subregs(rtx x)4329 scan_paradoxical_subregs (rtx x)
4330 {
4331 int i;
4332 const char *fmt;
4333 enum rtx_code code = GET_CODE (x);
4334
4335 switch (code)
4336 {
4337 case REG:
4338 case CONST:
4339 case SYMBOL_REF:
4340 case LABEL_REF:
4341 CASE_CONST_ANY:
4342 case PC:
4343 case USE:
4344 case CLOBBER:
4345 return;
4346
4347 case SUBREG:
4348 if (REG_P (SUBREG_REG (x)))
4349 {
4350 unsigned int regno = REGNO (SUBREG_REG (x));
4351 if (partial_subreg_p (reg_max_ref_mode[regno], GET_MODE (x)))
4352 {
4353 reg_max_ref_mode[regno] = GET_MODE (x);
4354 mark_home_live_1 (regno, GET_MODE (x));
4355 }
4356 }
4357 return;
4358
4359 default:
4360 break;
4361 }
4362
4363 fmt = GET_RTX_FORMAT (code);
4364 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4365 {
4366 if (fmt[i] == 'e')
4367 scan_paradoxical_subregs (XEXP (x, i));
4368 else if (fmt[i] == 'E')
4369 {
4370 int j;
4371 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4372 scan_paradoxical_subregs (XVECEXP (x, i, j));
4373 }
4374 }
4375 }
4376
4377 /* *OP_PTR and *OTHER_PTR are two operands to a conceptual reload.
4378 If *OP_PTR is a paradoxical subreg, try to remove that subreg
4379 and apply the corresponding narrowing subreg to *OTHER_PTR.
4380 Return true if the operands were changed, false otherwise. */
4381
4382 static bool
strip_paradoxical_subreg(rtx * op_ptr,rtx * other_ptr)4383 strip_paradoxical_subreg (rtx *op_ptr, rtx *other_ptr)
4384 {
4385 rtx op, inner, other, tem;
4386
4387 op = *op_ptr;
4388 if (!paradoxical_subreg_p (op))
4389 return false;
4390 inner = SUBREG_REG (op);
4391
4392 other = *other_ptr;
4393 tem = gen_lowpart_common (GET_MODE (inner), other);
4394 if (!tem)
4395 return false;
4396
4397 /* If the lowpart operation turned a hard register into a subreg,
4398 rather than simplifying it to another hard register, then the
4399 mode change cannot be properly represented. For example, OTHER
4400 might be valid in its current mode, but not in the new one. */
4401 if (GET_CODE (tem) == SUBREG
4402 && REG_P (other)
4403 && HARD_REGISTER_P (other))
4404 return false;
4405
4406 *op_ptr = inner;
4407 *other_ptr = tem;
4408 return true;
4409 }
4410
4411 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4412 examine all of the reload insns between PREV and NEXT exclusive, and
4413 annotate all that may trap. */
4414
4415 static void
fixup_eh_region_note(rtx_insn * insn,rtx_insn * prev,rtx_insn * next)4416 fixup_eh_region_note (rtx_insn *insn, rtx_insn *prev, rtx_insn *next)
4417 {
4418 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
4419 if (note == NULL)
4420 return;
4421 if (!insn_could_throw_p (insn))
4422 remove_note (insn, note);
4423 copy_reg_eh_region_note_forward (note, NEXT_INSN (prev), next);
4424 }
4425
4426 /* Reload pseudo-registers into hard regs around each insn as needed.
4427 Additional register load insns are output before the insn that needs it
4428 and perhaps store insns after insns that modify the reloaded pseudo reg.
4429
4430 reg_last_reload_reg and reg_reloaded_contents keep track of
4431 which registers are already available in reload registers.
4432 We update these for the reloads that we perform,
4433 as the insns are scanned. */
4434
4435 static void
reload_as_needed(int live_known)4436 reload_as_needed (int live_known)
4437 {
4438 class insn_chain *chain;
4439 #if AUTO_INC_DEC
4440 int i;
4441 #endif
4442 rtx_note *marker;
4443
4444 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
4445 memset (spill_reg_store, 0, sizeof spill_reg_store);
4446 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
4447 INIT_REG_SET (®_has_output_reload);
4448 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4449
4450 set_initial_elim_offsets ();
4451
4452 /* Generate a marker insn that we will move around. */
4453 marker = emit_note (NOTE_INSN_DELETED);
4454 unlink_insn_chain (marker, marker);
4455
4456 for (chain = reload_insn_chain; chain; chain = chain->next)
4457 {
4458 rtx_insn *prev = 0;
4459 rtx_insn *insn = chain->insn;
4460 rtx_insn *old_next = NEXT_INSN (insn);
4461 #if AUTO_INC_DEC
4462 rtx_insn *old_prev = PREV_INSN (insn);
4463 #endif
4464
4465 if (will_delete_init_insn_p (insn))
4466 continue;
4467
4468 /* If we pass a label, copy the offsets from the label information
4469 into the current offsets of each elimination. */
4470 if (LABEL_P (insn))
4471 set_offsets_for_label (insn);
4472
4473 else if (INSN_P (insn))
4474 {
4475 regset_head regs_to_forget;
4476 INIT_REG_SET (®s_to_forget);
4477 note_stores (insn, forget_old_reloads_1, ®s_to_forget);
4478
4479 /* If this is a USE and CLOBBER of a MEM, ensure that any
4480 references to eliminable registers have been removed. */
4481
4482 if ((GET_CODE (PATTERN (insn)) == USE
4483 || GET_CODE (PATTERN (insn)) == CLOBBER)
4484 && MEM_P (XEXP (PATTERN (insn), 0)))
4485 XEXP (XEXP (PATTERN (insn), 0), 0)
4486 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4487 GET_MODE (XEXP (PATTERN (insn), 0)),
4488 NULL_RTX);
4489
4490 /* If we need to do register elimination processing, do so.
4491 This might delete the insn, in which case we are done. */
4492 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4493 {
4494 eliminate_regs_in_insn (insn, 1);
4495 if (NOTE_P (insn))
4496 {
4497 update_eliminable_offsets ();
4498 CLEAR_REG_SET (®s_to_forget);
4499 continue;
4500 }
4501 }
4502
4503 /* If need_elim is nonzero but need_reload is zero, one might think
4504 that we could simply set n_reloads to 0. However, find_reloads
4505 could have done some manipulation of the insn (such as swapping
4506 commutative operands), and these manipulations are lost during
4507 the first pass for every insn that needs register elimination.
4508 So the actions of find_reloads must be redone here. */
4509
4510 if (! chain->need_elim && ! chain->need_reload
4511 && ! chain->need_operand_change)
4512 n_reloads = 0;
4513 /* First find the pseudo regs that must be reloaded for this insn.
4514 This info is returned in the tables reload_... (see reload.h).
4515 Also modify the body of INSN by substituting RELOAD
4516 rtx's for those pseudo regs. */
4517 else
4518 {
4519 CLEAR_REG_SET (®_has_output_reload);
4520 CLEAR_HARD_REG_SET (reg_is_output_reload);
4521
4522 find_reloads (insn, 1, spill_indirect_levels, live_known,
4523 spill_reg_order);
4524 }
4525
4526 if (n_reloads > 0)
4527 {
4528 rtx_insn *next = NEXT_INSN (insn);
4529
4530 /* ??? PREV can get deleted by reload inheritance.
4531 Work around this by emitting a marker note. */
4532 prev = PREV_INSN (insn);
4533 reorder_insns_nobb (marker, marker, prev);
4534
4535 /* Now compute which reload regs to reload them into. Perhaps
4536 reusing reload regs from previous insns, or else output
4537 load insns to reload them. Maybe output store insns too.
4538 Record the choices of reload reg in reload_reg_rtx. */
4539 choose_reload_regs (chain);
4540
4541 /* Generate the insns to reload operands into or out of
4542 their reload regs. */
4543 emit_reload_insns (chain);
4544
4545 /* Substitute the chosen reload regs from reload_reg_rtx
4546 into the insn's body (or perhaps into the bodies of other
4547 load and store insn that we just made for reloading
4548 and that we moved the structure into). */
4549 subst_reloads (insn);
4550
4551 prev = PREV_INSN (marker);
4552 unlink_insn_chain (marker, marker);
4553
4554 /* Adjust the exception region notes for loads and stores. */
4555 if (cfun->can_throw_non_call_exceptions && !CALL_P (insn))
4556 fixup_eh_region_note (insn, prev, next);
4557
4558 /* Adjust the location of REG_ARGS_SIZE. */
4559 rtx p = find_reg_note (insn, REG_ARGS_SIZE, NULL_RTX);
4560 if (p)
4561 {
4562 remove_note (insn, p);
4563 fixup_args_size_notes (prev, PREV_INSN (next),
4564 get_args_size (p));
4565 }
4566
4567 /* If this was an ASM, make sure that all the reload insns
4568 we have generated are valid. If not, give an error
4569 and delete them. */
4570 if (asm_noperands (PATTERN (insn)) >= 0)
4571 for (rtx_insn *p = NEXT_INSN (prev);
4572 p != next;
4573 p = NEXT_INSN (p))
4574 if (p != insn && INSN_P (p)
4575 && GET_CODE (PATTERN (p)) != USE
4576 && (recog_memoized (p) < 0
4577 || (extract_insn (p),
4578 !(constrain_operands (1,
4579 get_enabled_alternatives (p))))))
4580 {
4581 error_for_asm (insn,
4582 "%<asm%> operand requires "
4583 "impossible reload");
4584 delete_insn (p);
4585 }
4586 }
4587
4588 if (num_eliminable && chain->need_elim)
4589 update_eliminable_offsets ();
4590
4591 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4592 is no longer validly lying around to save a future reload.
4593 Note that this does not detect pseudos that were reloaded
4594 for this insn in order to be stored in
4595 (obeying register constraints). That is correct; such reload
4596 registers ARE still valid. */
4597 forget_marked_reloads (®s_to_forget);
4598 CLEAR_REG_SET (®s_to_forget);
4599
4600 /* There may have been CLOBBER insns placed after INSN. So scan
4601 between INSN and NEXT and use them to forget old reloads. */
4602 for (rtx_insn *x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4603 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4604 note_stores (x, forget_old_reloads_1, NULL);
4605
4606 #if AUTO_INC_DEC
4607 /* Likewise for regs altered by auto-increment in this insn.
4608 REG_INC notes have been changed by reloading:
4609 find_reloads_address_1 records substitutions for them,
4610 which have been performed by subst_reloads above. */
4611 for (i = n_reloads - 1; i >= 0; i--)
4612 {
4613 rtx in_reg = rld[i].in_reg;
4614 if (in_reg)
4615 {
4616 enum rtx_code code = GET_CODE (in_reg);
4617 /* PRE_INC / PRE_DEC will have the reload register ending up
4618 with the same value as the stack slot, but that doesn't
4619 hold true for POST_INC / POST_DEC. Either we have to
4620 convert the memory access to a true POST_INC / POST_DEC,
4621 or we can't use the reload register for inheritance. */
4622 if ((code == POST_INC || code == POST_DEC)
4623 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4624 REGNO (rld[i].reg_rtx))
4625 /* Make sure it is the inc/dec pseudo, and not
4626 some other (e.g. output operand) pseudo. */
4627 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4628 == REGNO (XEXP (in_reg, 0))))
4629
4630 {
4631 rtx reload_reg = rld[i].reg_rtx;
4632 machine_mode mode = GET_MODE (reload_reg);
4633 int n = 0;
4634 rtx_insn *p;
4635
4636 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4637 {
4638 /* We really want to ignore REG_INC notes here, so
4639 use PATTERN (p) as argument to reg_set_p . */
4640 if (reg_set_p (reload_reg, PATTERN (p)))
4641 break;
4642 n = count_occurrences (PATTERN (p), reload_reg, 0);
4643 if (! n)
4644 continue;
4645 if (n == 1)
4646 {
4647 rtx replace_reg
4648 = gen_rtx_fmt_e (code, mode, reload_reg);
4649
4650 validate_replace_rtx_group (reload_reg,
4651 replace_reg, p);
4652 n = verify_changes (0);
4653
4654 /* We must also verify that the constraints
4655 are met after the replacement. Make sure
4656 extract_insn is only called for an insn
4657 where the replacements were found to be
4658 valid so far. */
4659 if (n)
4660 {
4661 extract_insn (p);
4662 n = constrain_operands (1,
4663 get_enabled_alternatives (p));
4664 }
4665
4666 /* If the constraints were not met, then
4667 undo the replacement, else confirm it. */
4668 if (!n)
4669 cancel_changes (0);
4670 else
4671 confirm_change_group ();
4672 }
4673 break;
4674 }
4675 if (n == 1)
4676 {
4677 add_reg_note (p, REG_INC, reload_reg);
4678 /* Mark this as having an output reload so that the
4679 REG_INC processing code below won't invalidate
4680 the reload for inheritance. */
4681 SET_HARD_REG_BIT (reg_is_output_reload,
4682 REGNO (reload_reg));
4683 SET_REGNO_REG_SET (®_has_output_reload,
4684 REGNO (XEXP (in_reg, 0)));
4685 }
4686 else
4687 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4688 NULL);
4689 }
4690 else if ((code == PRE_INC || code == PRE_DEC)
4691 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4692 REGNO (rld[i].reg_rtx))
4693 /* Make sure it is the inc/dec pseudo, and not
4694 some other (e.g. output operand) pseudo. */
4695 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4696 == REGNO (XEXP (in_reg, 0))))
4697 {
4698 SET_HARD_REG_BIT (reg_is_output_reload,
4699 REGNO (rld[i].reg_rtx));
4700 SET_REGNO_REG_SET (®_has_output_reload,
4701 REGNO (XEXP (in_reg, 0)));
4702 }
4703 else if (code == PRE_INC || code == PRE_DEC
4704 || code == POST_INC || code == POST_DEC)
4705 {
4706 int in_regno = REGNO (XEXP (in_reg, 0));
4707
4708 if (reg_last_reload_reg[in_regno] != NULL_RTX)
4709 {
4710 int in_hard_regno;
4711 bool forget_p = true;
4712
4713 in_hard_regno = REGNO (reg_last_reload_reg[in_regno]);
4714 if (TEST_HARD_REG_BIT (reg_reloaded_valid,
4715 in_hard_regno))
4716 {
4717 for (rtx_insn *x = (old_prev ?
4718 NEXT_INSN (old_prev) : insn);
4719 x != old_next;
4720 x = NEXT_INSN (x))
4721 if (x == reg_reloaded_insn[in_hard_regno])
4722 {
4723 forget_p = false;
4724 break;
4725 }
4726 }
4727 /* If for some reasons, we didn't set up
4728 reg_last_reload_reg in this insn,
4729 invalidate inheritance from previous
4730 insns for the incremented/decremented
4731 register. Such registers will be not in
4732 reg_has_output_reload. Invalidate it
4733 also if the corresponding element in
4734 reg_reloaded_insn is also
4735 invalidated. */
4736 if (forget_p)
4737 forget_old_reloads_1 (XEXP (in_reg, 0),
4738 NULL_RTX, NULL);
4739 }
4740 }
4741 }
4742 }
4743 /* If a pseudo that got a hard register is auto-incremented,
4744 we must purge records of copying it into pseudos without
4745 hard registers. */
4746 for (rtx x = REG_NOTES (insn); x; x = XEXP (x, 1))
4747 if (REG_NOTE_KIND (x) == REG_INC)
4748 {
4749 /* See if this pseudo reg was reloaded in this insn.
4750 If so, its last-reload info is still valid
4751 because it is based on this insn's reload. */
4752 for (i = 0; i < n_reloads; i++)
4753 if (rld[i].out == XEXP (x, 0))
4754 break;
4755
4756 if (i == n_reloads)
4757 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4758 }
4759 #endif
4760 }
4761 /* A reload reg's contents are unknown after a label. */
4762 if (LABEL_P (insn))
4763 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4764
4765 /* Don't assume a reload reg is still good after a call insn
4766 if it is a call-used reg, or if it contains a value that will
4767 be partially clobbered by the call. */
4768 else if (CALL_P (insn))
4769 {
4770 reg_reloaded_valid
4771 &= ~insn_callee_abi (insn).full_and_partial_reg_clobbers ();
4772
4773 /* If this is a call to a setjmp-type function, we must not
4774 reuse any reload reg contents across the call; that will
4775 just be clobbered by other uses of the register in later
4776 code, before the longjmp. */
4777 if (find_reg_note (insn, REG_SETJMP, NULL_RTX))
4778 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4779 }
4780 }
4781
4782 /* Clean up. */
4783 free (reg_last_reload_reg);
4784 CLEAR_REG_SET (®_has_output_reload);
4785 }
4786
4787 /* Discard all record of any value reloaded from X,
4788 or reloaded in X from someplace else;
4789 unless X is an output reload reg of the current insn.
4790
4791 X may be a hard reg (the reload reg)
4792 or it may be a pseudo reg that was reloaded from.
4793
4794 When DATA is non-NULL just mark the registers in regset
4795 to be forgotten later. */
4796
4797 static void
forget_old_reloads_1(rtx x,const_rtx,void * data)4798 forget_old_reloads_1 (rtx x, const_rtx, void *data)
4799 {
4800 unsigned int regno;
4801 unsigned int nr;
4802 regset regs = (regset) data;
4803
4804 /* note_stores does give us subregs of hard regs,
4805 subreg_regno_offset requires a hard reg. */
4806 while (GET_CODE (x) == SUBREG)
4807 {
4808 /* We ignore the subreg offset when calculating the regno,
4809 because we are using the entire underlying hard register
4810 below. */
4811 x = SUBREG_REG (x);
4812 }
4813
4814 if (!REG_P (x))
4815 return;
4816
4817 regno = REGNO (x);
4818
4819 if (regno >= FIRST_PSEUDO_REGISTER)
4820 nr = 1;
4821 else
4822 {
4823 unsigned int i;
4824
4825 nr = REG_NREGS (x);
4826 /* Storing into a spilled-reg invalidates its contents.
4827 This can happen if a block-local pseudo is allocated to that reg
4828 and it wasn't spilled because this block's total need is 0.
4829 Then some insn might have an optional reload and use this reg. */
4830 if (!regs)
4831 for (i = 0; i < nr; i++)
4832 /* But don't do this if the reg actually serves as an output
4833 reload reg in the current instruction. */
4834 if (n_reloads == 0
4835 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4836 {
4837 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4838 spill_reg_store[regno + i] = 0;
4839 }
4840 }
4841
4842 if (regs)
4843 while (nr-- > 0)
4844 SET_REGNO_REG_SET (regs, regno + nr);
4845 else
4846 {
4847 /* Since value of X has changed,
4848 forget any value previously copied from it. */
4849
4850 while (nr-- > 0)
4851 /* But don't forget a copy if this is the output reload
4852 that establishes the copy's validity. */
4853 if (n_reloads == 0
4854 || !REGNO_REG_SET_P (®_has_output_reload, regno + nr))
4855 reg_last_reload_reg[regno + nr] = 0;
4856 }
4857 }
4858
4859 /* Forget the reloads marked in regset by previous function. */
4860 static void
forget_marked_reloads(regset regs)4861 forget_marked_reloads (regset regs)
4862 {
4863 unsigned int reg;
4864 reg_set_iterator rsi;
4865 EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4866 {
4867 if (reg < FIRST_PSEUDO_REGISTER
4868 /* But don't do this if the reg actually serves as an output
4869 reload reg in the current instruction. */
4870 && (n_reloads == 0
4871 || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4872 {
4873 CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4874 spill_reg_store[reg] = 0;
4875 }
4876 if (n_reloads == 0
4877 || !REGNO_REG_SET_P (®_has_output_reload, reg))
4878 reg_last_reload_reg[reg] = 0;
4879 }
4880 }
4881
4882 /* The following HARD_REG_SETs indicate when each hard register is
4883 used for a reload of various parts of the current insn. */
4884
4885 /* If reg is unavailable for all reloads. */
4886 static HARD_REG_SET reload_reg_unavailable;
4887 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4888 static HARD_REG_SET reload_reg_used;
4889 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4890 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4891 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4892 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4893 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4894 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4895 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4896 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4897 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4898 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4899 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4900 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4901 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4902 static HARD_REG_SET reload_reg_used_in_op_addr;
4903 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4904 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4905 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4906 static HARD_REG_SET reload_reg_used_in_insn;
4907 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4908 static HARD_REG_SET reload_reg_used_in_other_addr;
4909
4910 /* If reg is in use as a reload reg for any sort of reload. */
4911 static HARD_REG_SET reload_reg_used_at_all;
4912
4913 /* If reg is use as an inherited reload. We just mark the first register
4914 in the group. */
4915 static HARD_REG_SET reload_reg_used_for_inherit;
4916
4917 /* Records which hard regs are used in any way, either as explicit use or
4918 by being allocated to a pseudo during any point of the current insn. */
4919 static HARD_REG_SET reg_used_in_insn;
4920
4921 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4922 TYPE. MODE is used to indicate how many consecutive regs are
4923 actually used. */
4924
4925 static void
mark_reload_reg_in_use(unsigned int regno,int opnum,enum reload_type type,machine_mode mode)4926 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4927 machine_mode mode)
4928 {
4929 switch (type)
4930 {
4931 case RELOAD_OTHER:
4932 add_to_hard_reg_set (&reload_reg_used, mode, regno);
4933 break;
4934
4935 case RELOAD_FOR_INPUT_ADDRESS:
4936 add_to_hard_reg_set (&reload_reg_used_in_input_addr[opnum], mode, regno);
4937 break;
4938
4939 case RELOAD_FOR_INPADDR_ADDRESS:
4940 add_to_hard_reg_set (&reload_reg_used_in_inpaddr_addr[opnum], mode, regno);
4941 break;
4942
4943 case RELOAD_FOR_OUTPUT_ADDRESS:
4944 add_to_hard_reg_set (&reload_reg_used_in_output_addr[opnum], mode, regno);
4945 break;
4946
4947 case RELOAD_FOR_OUTADDR_ADDRESS:
4948 add_to_hard_reg_set (&reload_reg_used_in_outaddr_addr[opnum], mode, regno);
4949 break;
4950
4951 case RELOAD_FOR_OPERAND_ADDRESS:
4952 add_to_hard_reg_set (&reload_reg_used_in_op_addr, mode, regno);
4953 break;
4954
4955 case RELOAD_FOR_OPADDR_ADDR:
4956 add_to_hard_reg_set (&reload_reg_used_in_op_addr_reload, mode, regno);
4957 break;
4958
4959 case RELOAD_FOR_OTHER_ADDRESS:
4960 add_to_hard_reg_set (&reload_reg_used_in_other_addr, mode, regno);
4961 break;
4962
4963 case RELOAD_FOR_INPUT:
4964 add_to_hard_reg_set (&reload_reg_used_in_input[opnum], mode, regno);
4965 break;
4966
4967 case RELOAD_FOR_OUTPUT:
4968 add_to_hard_reg_set (&reload_reg_used_in_output[opnum], mode, regno);
4969 break;
4970
4971 case RELOAD_FOR_INSN:
4972 add_to_hard_reg_set (&reload_reg_used_in_insn, mode, regno);
4973 break;
4974 }
4975
4976 add_to_hard_reg_set (&reload_reg_used_at_all, mode, regno);
4977 }
4978
4979 /* Similarly, but show REGNO is no longer in use for a reload. */
4980
4981 static void
clear_reload_reg_in_use(unsigned int regno,int opnum,enum reload_type type,machine_mode mode)4982 clear_reload_reg_in_use (unsigned int regno, int opnum,
4983 enum reload_type type, machine_mode mode)
4984 {
4985 unsigned int nregs = hard_regno_nregs (regno, mode);
4986 unsigned int start_regno, end_regno, r;
4987 int i;
4988 /* A complication is that for some reload types, inheritance might
4989 allow multiple reloads of the same types to share a reload register.
4990 We set check_opnum if we have to check only reloads with the same
4991 operand number, and check_any if we have to check all reloads. */
4992 int check_opnum = 0;
4993 int check_any = 0;
4994 HARD_REG_SET *used_in_set;
4995
4996 switch (type)
4997 {
4998 case RELOAD_OTHER:
4999 used_in_set = &reload_reg_used;
5000 break;
5001
5002 case RELOAD_FOR_INPUT_ADDRESS:
5003 used_in_set = &reload_reg_used_in_input_addr[opnum];
5004 break;
5005
5006 case RELOAD_FOR_INPADDR_ADDRESS:
5007 check_opnum = 1;
5008 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
5009 break;
5010
5011 case RELOAD_FOR_OUTPUT_ADDRESS:
5012 used_in_set = &reload_reg_used_in_output_addr[opnum];
5013 break;
5014
5015 case RELOAD_FOR_OUTADDR_ADDRESS:
5016 check_opnum = 1;
5017 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
5018 break;
5019
5020 case RELOAD_FOR_OPERAND_ADDRESS:
5021 used_in_set = &reload_reg_used_in_op_addr;
5022 break;
5023
5024 case RELOAD_FOR_OPADDR_ADDR:
5025 check_any = 1;
5026 used_in_set = &reload_reg_used_in_op_addr_reload;
5027 break;
5028
5029 case RELOAD_FOR_OTHER_ADDRESS:
5030 used_in_set = &reload_reg_used_in_other_addr;
5031 check_any = 1;
5032 break;
5033
5034 case RELOAD_FOR_INPUT:
5035 used_in_set = &reload_reg_used_in_input[opnum];
5036 break;
5037
5038 case RELOAD_FOR_OUTPUT:
5039 used_in_set = &reload_reg_used_in_output[opnum];
5040 break;
5041
5042 case RELOAD_FOR_INSN:
5043 used_in_set = &reload_reg_used_in_insn;
5044 break;
5045 default:
5046 gcc_unreachable ();
5047 }
5048 /* We resolve conflicts with remaining reloads of the same type by
5049 excluding the intervals of reload registers by them from the
5050 interval of freed reload registers. Since we only keep track of
5051 one set of interval bounds, we might have to exclude somewhat
5052 more than what would be necessary if we used a HARD_REG_SET here.
5053 But this should only happen very infrequently, so there should
5054 be no reason to worry about it. */
5055
5056 start_regno = regno;
5057 end_regno = regno + nregs;
5058 if (check_opnum || check_any)
5059 {
5060 for (i = n_reloads - 1; i >= 0; i--)
5061 {
5062 if (rld[i].when_needed == type
5063 && (check_any || rld[i].opnum == opnum)
5064 && rld[i].reg_rtx)
5065 {
5066 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
5067 unsigned int conflict_end
5068 = end_hard_regno (rld[i].mode, conflict_start);
5069
5070 /* If there is an overlap with the first to-be-freed register,
5071 adjust the interval start. */
5072 if (conflict_start <= start_regno && conflict_end > start_regno)
5073 start_regno = conflict_end;
5074 /* Otherwise, if there is a conflict with one of the other
5075 to-be-freed registers, adjust the interval end. */
5076 if (conflict_start > start_regno && conflict_start < end_regno)
5077 end_regno = conflict_start;
5078 }
5079 }
5080 }
5081
5082 for (r = start_regno; r < end_regno; r++)
5083 CLEAR_HARD_REG_BIT (*used_in_set, r);
5084 }
5085
5086 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
5087 specified by OPNUM and TYPE. */
5088
5089 static int
reload_reg_free_p(unsigned int regno,int opnum,enum reload_type type)5090 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
5091 {
5092 int i;
5093
5094 /* In use for a RELOAD_OTHER means it's not available for anything. */
5095 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
5096 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5097 return 0;
5098
5099 switch (type)
5100 {
5101 case RELOAD_OTHER:
5102 /* In use for anything means we can't use it for RELOAD_OTHER. */
5103 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
5104 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5105 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
5106 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
5107 return 0;
5108
5109 for (i = 0; i < reload_n_operands; i++)
5110 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5111 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5112 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5113 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5114 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
5115 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5116 return 0;
5117
5118 return 1;
5119
5120 case RELOAD_FOR_INPUT:
5121 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5122 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
5123 return 0;
5124
5125 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5126 return 0;
5127
5128 /* If it is used for some other input, can't use it. */
5129 for (i = 0; i < reload_n_operands; i++)
5130 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5131 return 0;
5132
5133 /* If it is used in a later operand's address, can't use it. */
5134 for (i = opnum + 1; i < reload_n_operands; i++)
5135 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5136 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5137 return 0;
5138
5139 return 1;
5140
5141 case RELOAD_FOR_INPUT_ADDRESS:
5142 /* Can't use a register if it is used for an input address for this
5143 operand or used as an input in an earlier one. */
5144 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
5145 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
5146 return 0;
5147
5148 for (i = 0; i < opnum; i++)
5149 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5150 return 0;
5151
5152 return 1;
5153
5154 case RELOAD_FOR_INPADDR_ADDRESS:
5155 /* Can't use a register if it is used for an input address
5156 for this operand or used as an input in an earlier
5157 one. */
5158 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
5159 return 0;
5160
5161 for (i = 0; i < opnum; i++)
5162 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5163 return 0;
5164
5165 return 1;
5166
5167 case RELOAD_FOR_OUTPUT_ADDRESS:
5168 /* Can't use a register if it is used for an output address for this
5169 operand or used as an output in this or a later operand. Note
5170 that multiple output operands are emitted in reverse order, so
5171 the conflicting ones are those with lower indices. */
5172 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
5173 return 0;
5174
5175 for (i = 0; i <= opnum; i++)
5176 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5177 return 0;
5178
5179 return 1;
5180
5181 case RELOAD_FOR_OUTADDR_ADDRESS:
5182 /* Can't use a register if it is used for an output address
5183 for this operand or used as an output in this or a
5184 later operand. Note that multiple output operands are
5185 emitted in reverse order, so the conflicting ones are
5186 those with lower indices. */
5187 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
5188 return 0;
5189
5190 for (i = 0; i <= opnum; i++)
5191 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5192 return 0;
5193
5194 return 1;
5195
5196 case RELOAD_FOR_OPERAND_ADDRESS:
5197 for (i = 0; i < reload_n_operands; i++)
5198 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5199 return 0;
5200
5201 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5202 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5203
5204 case RELOAD_FOR_OPADDR_ADDR:
5205 for (i = 0; i < reload_n_operands; i++)
5206 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5207 return 0;
5208
5209 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
5210
5211 case RELOAD_FOR_OUTPUT:
5212 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
5213 outputs, or an operand address for this or an earlier output.
5214 Note that multiple output operands are emitted in reverse order,
5215 so the conflicting ones are those with higher indices. */
5216 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
5217 return 0;
5218
5219 for (i = 0; i < reload_n_operands; i++)
5220 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5221 return 0;
5222
5223 for (i = opnum; i < reload_n_operands; i++)
5224 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5225 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5226 return 0;
5227
5228 return 1;
5229
5230 case RELOAD_FOR_INSN:
5231 for (i = 0; i < reload_n_operands; i++)
5232 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
5233 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5234 return 0;
5235
5236 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5237 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5238
5239 case RELOAD_FOR_OTHER_ADDRESS:
5240 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
5241
5242 default:
5243 gcc_unreachable ();
5244 }
5245 }
5246
5247 /* Return 1 if the value in reload reg REGNO, as used by the reload with
5248 the number RELOADNUM, is still available in REGNO at the end of the insn.
5249
5250 We can assume that the reload reg was already tested for availability
5251 at the time it is needed, and we should not check this again,
5252 in case the reg has already been marked in use. */
5253
5254 static int
reload_reg_reaches_end_p(unsigned int regno,int reloadnum)5255 reload_reg_reaches_end_p (unsigned int regno, int reloadnum)
5256 {
5257 int opnum = rld[reloadnum].opnum;
5258 enum reload_type type = rld[reloadnum].when_needed;
5259 int i;
5260
5261 /* See if there is a reload with the same type for this operand, using
5262 the same register. This case is not handled by the code below. */
5263 for (i = reloadnum + 1; i < n_reloads; i++)
5264 {
5265 rtx reg;
5266
5267 if (rld[i].opnum != opnum || rld[i].when_needed != type)
5268 continue;
5269 reg = rld[i].reg_rtx;
5270 if (reg == NULL_RTX)
5271 continue;
5272 if (regno >= REGNO (reg) && regno < END_REGNO (reg))
5273 return 0;
5274 }
5275
5276 switch (type)
5277 {
5278 case RELOAD_OTHER:
5279 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
5280 its value must reach the end. */
5281 return 1;
5282
5283 /* If this use is for part of the insn,
5284 its value reaches if no subsequent part uses the same register.
5285 Just like the above function, don't try to do this with lots
5286 of fallthroughs. */
5287
5288 case RELOAD_FOR_OTHER_ADDRESS:
5289 /* Here we check for everything else, since these don't conflict
5290 with anything else and everything comes later. */
5291
5292 for (i = 0; i < reload_n_operands; i++)
5293 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5294 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5295 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
5296 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5297 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5298 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5299 return 0;
5300
5301 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5302 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
5303 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5304 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
5305
5306 case RELOAD_FOR_INPUT_ADDRESS:
5307 case RELOAD_FOR_INPADDR_ADDRESS:
5308 /* Similar, except that we check only for this and subsequent inputs
5309 and the address of only subsequent inputs and we do not need
5310 to check for RELOAD_OTHER objects since they are known not to
5311 conflict. */
5312
5313 for (i = opnum; i < reload_n_operands; i++)
5314 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5315 return 0;
5316
5317 /* Reload register of reload with type RELOAD_FOR_INPADDR_ADDRESS
5318 could be killed if the register is also used by reload with type
5319 RELOAD_FOR_INPUT_ADDRESS, so check it. */
5320 if (type == RELOAD_FOR_INPADDR_ADDRESS
5321 && TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno))
5322 return 0;
5323
5324 for (i = opnum + 1; i < reload_n_operands; i++)
5325 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5326 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5327 return 0;
5328
5329 for (i = 0; i < reload_n_operands; i++)
5330 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5331 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5332 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5333 return 0;
5334
5335 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5336 return 0;
5337
5338 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5339 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5340 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5341
5342 case RELOAD_FOR_INPUT:
5343 /* Similar to input address, except we start at the next operand for
5344 both input and input address and we do not check for
5345 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5346 would conflict. */
5347
5348 for (i = opnum + 1; i < reload_n_operands; i++)
5349 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5350 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5351 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5352 return 0;
5353
5354 /* ... fall through ... */
5355
5356 case RELOAD_FOR_OPERAND_ADDRESS:
5357 /* Check outputs and their addresses. */
5358
5359 for (i = 0; i < reload_n_operands; i++)
5360 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5361 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5362 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5363 return 0;
5364
5365 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
5366
5367 case RELOAD_FOR_OPADDR_ADDR:
5368 for (i = 0; i < reload_n_operands; i++)
5369 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5370 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5371 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5372 return 0;
5373
5374 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5375 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5376 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5377
5378 case RELOAD_FOR_INSN:
5379 /* These conflict with other outputs with RELOAD_OTHER. So
5380 we need only check for output addresses. */
5381
5382 opnum = reload_n_operands;
5383
5384 /* fall through */
5385
5386 case RELOAD_FOR_OUTPUT:
5387 case RELOAD_FOR_OUTPUT_ADDRESS:
5388 case RELOAD_FOR_OUTADDR_ADDRESS:
5389 /* We already know these can't conflict with a later output. So the
5390 only thing to check are later output addresses.
5391 Note that multiple output operands are emitted in reverse order,
5392 so the conflicting ones are those with lower indices. */
5393 for (i = 0; i < opnum; i++)
5394 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5395 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5396 return 0;
5397
5398 /* Reload register of reload with type RELOAD_FOR_OUTADDR_ADDRESS
5399 could be killed if the register is also used by reload with type
5400 RELOAD_FOR_OUTPUT_ADDRESS, so check it. */
5401 if (type == RELOAD_FOR_OUTADDR_ADDRESS
5402 && TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
5403 return 0;
5404
5405 return 1;
5406
5407 default:
5408 gcc_unreachable ();
5409 }
5410 }
5411
5412 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5413 every register in REG. */
5414
5415 static bool
reload_reg_rtx_reaches_end_p(rtx reg,int reloadnum)5416 reload_reg_rtx_reaches_end_p (rtx reg, int reloadnum)
5417 {
5418 unsigned int i;
5419
5420 for (i = REGNO (reg); i < END_REGNO (reg); i++)
5421 if (!reload_reg_reaches_end_p (i, reloadnum))
5422 return false;
5423 return true;
5424 }
5425
5426
5427 /* Returns whether R1 and R2 are uniquely chained: the value of one
5428 is used by the other, and that value is not used by any other
5429 reload for this insn. This is used to partially undo the decision
5430 made in find_reloads when in the case of multiple
5431 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5432 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5433 reloads. This code tries to avoid the conflict created by that
5434 change. It might be cleaner to explicitly keep track of which
5435 RELOAD_FOR_OPADDR_ADDR reload is associated with which
5436 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5437 this after the fact. */
5438 static bool
reloads_unique_chain_p(int r1,int r2)5439 reloads_unique_chain_p (int r1, int r2)
5440 {
5441 int i;
5442
5443 /* We only check input reloads. */
5444 if (! rld[r1].in || ! rld[r2].in)
5445 return false;
5446
5447 /* Avoid anything with output reloads. */
5448 if (rld[r1].out || rld[r2].out)
5449 return false;
5450
5451 /* "chained" means one reload is a component of the other reload,
5452 not the same as the other reload. */
5453 if (rld[r1].opnum != rld[r2].opnum
5454 || rtx_equal_p (rld[r1].in, rld[r2].in)
5455 || rld[r1].optional || rld[r2].optional
5456 || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
5457 || reg_mentioned_p (rld[r2].in, rld[r1].in)))
5458 return false;
5459
5460 /* The following loop assumes that r1 is the reload that feeds r2. */
5461 if (r1 > r2)
5462 std::swap (r1, r2);
5463
5464 for (i = 0; i < n_reloads; i ++)
5465 /* Look for input reloads that aren't our two */
5466 if (i != r1 && i != r2 && rld[i].in)
5467 {
5468 /* If our reload is mentioned at all, it isn't a simple chain. */
5469 if (reg_mentioned_p (rld[r1].in, rld[i].in))
5470 return false;
5471 }
5472 return true;
5473 }
5474
5475 /* The recursive function change all occurrences of WHAT in *WHERE
5476 to REPL. */
5477 static void
substitute(rtx * where,const_rtx what,rtx repl)5478 substitute (rtx *where, const_rtx what, rtx repl)
5479 {
5480 const char *fmt;
5481 int i;
5482 enum rtx_code code;
5483
5484 if (*where == 0)
5485 return;
5486
5487 if (*where == what || rtx_equal_p (*where, what))
5488 {
5489 /* Record the location of the changed rtx. */
5490 substitute_stack.safe_push (where);
5491 *where = repl;
5492 return;
5493 }
5494
5495 code = GET_CODE (*where);
5496 fmt = GET_RTX_FORMAT (code);
5497 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5498 {
5499 if (fmt[i] == 'E')
5500 {
5501 int j;
5502
5503 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
5504 substitute (&XVECEXP (*where, i, j), what, repl);
5505 }
5506 else if (fmt[i] == 'e')
5507 substitute (&XEXP (*where, i), what, repl);
5508 }
5509 }
5510
5511 /* The function returns TRUE if chain of reload R1 and R2 (in any
5512 order) can be evaluated without usage of intermediate register for
5513 the reload containing another reload. It is important to see
5514 gen_reload to understand what the function is trying to do. As an
5515 example, let us have reload chain
5516
5517 r2: const
5518 r1: <something> + const
5519
5520 and reload R2 got reload reg HR. The function returns true if
5521 there is a correct insn HR = HR + <something>. Otherwise,
5522 gen_reload will use intermediate register (and this is the reload
5523 reg for R1) to reload <something>.
5524
5525 We need this function to find a conflict for chain reloads. In our
5526 example, if HR = HR + <something> is incorrect insn, then we cannot
5527 use HR as a reload register for R2. If we do use it then we get a
5528 wrong code:
5529
5530 HR = const
5531 HR = <something>
5532 HR = HR + HR
5533
5534 */
5535 static bool
gen_reload_chain_without_interm_reg_p(int r1,int r2)5536 gen_reload_chain_without_interm_reg_p (int r1, int r2)
5537 {
5538 /* Assume other cases in gen_reload are not possible for
5539 chain reloads or do need an intermediate hard registers. */
5540 bool result = true;
5541 int regno, code;
5542 rtx out, in;
5543 rtx_insn *insn;
5544 rtx_insn *last = get_last_insn ();
5545
5546 /* Make r2 a component of r1. */
5547 if (reg_mentioned_p (rld[r1].in, rld[r2].in))
5548 std::swap (r1, r2);
5549
5550 gcc_assert (reg_mentioned_p (rld[r2].in, rld[r1].in));
5551 regno = rld[r1].regno >= 0 ? rld[r1].regno : rld[r2].regno;
5552 gcc_assert (regno >= 0);
5553 out = gen_rtx_REG (rld[r1].mode, regno);
5554 in = rld[r1].in;
5555 substitute (&in, rld[r2].in, gen_rtx_REG (rld[r2].mode, regno));
5556
5557 /* If IN is a paradoxical SUBREG, remove it and try to put the
5558 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
5559 strip_paradoxical_subreg (&in, &out);
5560
5561 if (GET_CODE (in) == PLUS
5562 && (REG_P (XEXP (in, 0))
5563 || GET_CODE (XEXP (in, 0)) == SUBREG
5564 || MEM_P (XEXP (in, 0)))
5565 && (REG_P (XEXP (in, 1))
5566 || GET_CODE (XEXP (in, 1)) == SUBREG
5567 || CONSTANT_P (XEXP (in, 1))
5568 || MEM_P (XEXP (in, 1))))
5569 {
5570 insn = emit_insn (gen_rtx_SET (out, in));
5571 code = recog_memoized (insn);
5572 result = false;
5573
5574 if (code >= 0)
5575 {
5576 extract_insn (insn);
5577 /* We want constrain operands to treat this insn strictly in
5578 its validity determination, i.e., the way it would after
5579 reload has completed. */
5580 result = constrain_operands (1, get_enabled_alternatives (insn));
5581 }
5582
5583 delete_insns_since (last);
5584 }
5585
5586 /* Restore the original value at each changed address within R1. */
5587 while (!substitute_stack.is_empty ())
5588 {
5589 rtx *where = substitute_stack.pop ();
5590 *where = rld[r2].in;
5591 }
5592
5593 return result;
5594 }
5595
5596 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5597 Return 0 otherwise.
5598
5599 This function uses the same algorithm as reload_reg_free_p above. */
5600
5601 static int
reloads_conflict(int r1,int r2)5602 reloads_conflict (int r1, int r2)
5603 {
5604 enum reload_type r1_type = rld[r1].when_needed;
5605 enum reload_type r2_type = rld[r2].when_needed;
5606 int r1_opnum = rld[r1].opnum;
5607 int r2_opnum = rld[r2].opnum;
5608
5609 /* RELOAD_OTHER conflicts with everything. */
5610 if (r2_type == RELOAD_OTHER)
5611 return 1;
5612
5613 /* Otherwise, check conflicts differently for each type. */
5614
5615 switch (r1_type)
5616 {
5617 case RELOAD_FOR_INPUT:
5618 return (r2_type == RELOAD_FOR_INSN
5619 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5620 || r2_type == RELOAD_FOR_OPADDR_ADDR
5621 || r2_type == RELOAD_FOR_INPUT
5622 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5623 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5624 && r2_opnum > r1_opnum));
5625
5626 case RELOAD_FOR_INPUT_ADDRESS:
5627 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5628 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5629
5630 case RELOAD_FOR_INPADDR_ADDRESS:
5631 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5632 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5633
5634 case RELOAD_FOR_OUTPUT_ADDRESS:
5635 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5636 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5637
5638 case RELOAD_FOR_OUTADDR_ADDRESS:
5639 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5640 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5641
5642 case RELOAD_FOR_OPERAND_ADDRESS:
5643 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5644 || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
5645 && (!reloads_unique_chain_p (r1, r2)
5646 || !gen_reload_chain_without_interm_reg_p (r1, r2))));
5647
5648 case RELOAD_FOR_OPADDR_ADDR:
5649 return (r2_type == RELOAD_FOR_INPUT
5650 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5651
5652 case RELOAD_FOR_OUTPUT:
5653 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5654 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5655 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5656 && r2_opnum >= r1_opnum));
5657
5658 case RELOAD_FOR_INSN:
5659 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5660 || r2_type == RELOAD_FOR_INSN
5661 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5662
5663 case RELOAD_FOR_OTHER_ADDRESS:
5664 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5665
5666 case RELOAD_OTHER:
5667 return 1;
5668
5669 default:
5670 gcc_unreachable ();
5671 }
5672 }
5673
5674 /* Indexed by reload number, 1 if incoming value
5675 inherited from previous insns. */
5676 static char reload_inherited[MAX_RELOADS];
5677
5678 /* For an inherited reload, this is the insn the reload was inherited from,
5679 if we know it. Otherwise, this is 0. */
5680 static rtx_insn *reload_inheritance_insn[MAX_RELOADS];
5681
5682 /* If nonzero, this is a place to get the value of the reload,
5683 rather than using reload_in. */
5684 static rtx reload_override_in[MAX_RELOADS];
5685
5686 /* For each reload, the hard register number of the register used,
5687 or -1 if we did not need a register for this reload. */
5688 static int reload_spill_index[MAX_RELOADS];
5689
5690 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5691 static rtx reload_reg_rtx_for_input[MAX_RELOADS];
5692
5693 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5694 static rtx reload_reg_rtx_for_output[MAX_RELOADS];
5695
5696 /* Subroutine of free_for_value_p, used to check a single register.
5697 START_REGNO is the starting regno of the full reload register
5698 (possibly comprising multiple hard registers) that we are considering. */
5699
5700 static int
reload_reg_free_for_value_p(int start_regno,int regno,int opnum,enum reload_type type,rtx value,rtx out,int reloadnum,int ignore_address_reloads)5701 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
5702 enum reload_type type, rtx value, rtx out,
5703 int reloadnum, int ignore_address_reloads)
5704 {
5705 int time1;
5706 /* Set if we see an input reload that must not share its reload register
5707 with any new earlyclobber, but might otherwise share the reload
5708 register with an output or input-output reload. */
5709 int check_earlyclobber = 0;
5710 int i;
5711 int copy = 0;
5712
5713 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5714 return 0;
5715
5716 if (out == const0_rtx)
5717 {
5718 copy = 1;
5719 out = NULL_RTX;
5720 }
5721
5722 /* We use some pseudo 'time' value to check if the lifetimes of the
5723 new register use would overlap with the one of a previous reload
5724 that is not read-only or uses a different value.
5725 The 'time' used doesn't have to be linear in any shape or form, just
5726 monotonic.
5727 Some reload types use different 'buckets' for each operand.
5728 So there are MAX_RECOG_OPERANDS different time values for each
5729 such reload type.
5730 We compute TIME1 as the time when the register for the prospective
5731 new reload ceases to be live, and TIME2 for each existing
5732 reload as the time when that the reload register of that reload
5733 becomes live.
5734 Where there is little to be gained by exact lifetime calculations,
5735 we just make conservative assumptions, i.e. a longer lifetime;
5736 this is done in the 'default:' cases. */
5737 switch (type)
5738 {
5739 case RELOAD_FOR_OTHER_ADDRESS:
5740 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5741 time1 = copy ? 0 : 1;
5742 break;
5743 case RELOAD_OTHER:
5744 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5745 break;
5746 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5747 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5748 respectively, to the time values for these, we get distinct time
5749 values. To get distinct time values for each operand, we have to
5750 multiply opnum by at least three. We round that up to four because
5751 multiply by four is often cheaper. */
5752 case RELOAD_FOR_INPADDR_ADDRESS:
5753 time1 = opnum * 4 + 2;
5754 break;
5755 case RELOAD_FOR_INPUT_ADDRESS:
5756 time1 = opnum * 4 + 3;
5757 break;
5758 case RELOAD_FOR_INPUT:
5759 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5760 executes (inclusive). */
5761 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5762 break;
5763 case RELOAD_FOR_OPADDR_ADDR:
5764 /* opnum * 4 + 4
5765 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5766 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5767 break;
5768 case RELOAD_FOR_OPERAND_ADDRESS:
5769 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5770 is executed. */
5771 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5772 break;
5773 case RELOAD_FOR_OUTADDR_ADDRESS:
5774 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5775 break;
5776 case RELOAD_FOR_OUTPUT_ADDRESS:
5777 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5778 break;
5779 default:
5780 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5781 }
5782
5783 for (i = 0; i < n_reloads; i++)
5784 {
5785 rtx reg = rld[i].reg_rtx;
5786 if (reg && REG_P (reg)
5787 && (unsigned) regno - true_regnum (reg) < REG_NREGS (reg)
5788 && i != reloadnum)
5789 {
5790 rtx other_input = rld[i].in;
5791
5792 /* If the other reload loads the same input value, that
5793 will not cause a conflict only if it's loading it into
5794 the same register. */
5795 if (true_regnum (reg) != start_regno)
5796 other_input = NULL_RTX;
5797 if (! other_input || ! rtx_equal_p (other_input, value)
5798 || rld[i].out || out)
5799 {
5800 int time2;
5801 switch (rld[i].when_needed)
5802 {
5803 case RELOAD_FOR_OTHER_ADDRESS:
5804 time2 = 0;
5805 break;
5806 case RELOAD_FOR_INPADDR_ADDRESS:
5807 /* find_reloads makes sure that a
5808 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5809 by at most one - the first -
5810 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5811 address reload is inherited, the address address reload
5812 goes away, so we can ignore this conflict. */
5813 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5814 && ignore_address_reloads
5815 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5816 Then the address address is still needed to store
5817 back the new address. */
5818 && ! rld[reloadnum].out)
5819 continue;
5820 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5821 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5822 reloads go away. */
5823 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5824 && ignore_address_reloads
5825 /* Unless we are reloading an auto_inc expression. */
5826 && ! rld[reloadnum].out)
5827 continue;
5828 time2 = rld[i].opnum * 4 + 2;
5829 break;
5830 case RELOAD_FOR_INPUT_ADDRESS:
5831 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5832 && ignore_address_reloads
5833 && ! rld[reloadnum].out)
5834 continue;
5835 time2 = rld[i].opnum * 4 + 3;
5836 break;
5837 case RELOAD_FOR_INPUT:
5838 time2 = rld[i].opnum * 4 + 4;
5839 check_earlyclobber = 1;
5840 break;
5841 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5842 == MAX_RECOG_OPERAND * 4 */
5843 case RELOAD_FOR_OPADDR_ADDR:
5844 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5845 && ignore_address_reloads
5846 && ! rld[reloadnum].out)
5847 continue;
5848 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5849 break;
5850 case RELOAD_FOR_OPERAND_ADDRESS:
5851 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5852 check_earlyclobber = 1;
5853 break;
5854 case RELOAD_FOR_INSN:
5855 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5856 break;
5857 case RELOAD_FOR_OUTPUT:
5858 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5859 instruction is executed. */
5860 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5861 break;
5862 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5863 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5864 value. */
5865 case RELOAD_FOR_OUTADDR_ADDRESS:
5866 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5867 && ignore_address_reloads
5868 && ! rld[reloadnum].out)
5869 continue;
5870 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5871 break;
5872 case RELOAD_FOR_OUTPUT_ADDRESS:
5873 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5874 break;
5875 case RELOAD_OTHER:
5876 /* If there is no conflict in the input part, handle this
5877 like an output reload. */
5878 if (! rld[i].in || rtx_equal_p (other_input, value))
5879 {
5880 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5881 /* Earlyclobbered outputs must conflict with inputs. */
5882 if (earlyclobber_operand_p (rld[i].out))
5883 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5884
5885 break;
5886 }
5887 time2 = 1;
5888 /* RELOAD_OTHER might be live beyond instruction execution,
5889 but this is not obvious when we set time2 = 1. So check
5890 here if there might be a problem with the new reload
5891 clobbering the register used by the RELOAD_OTHER. */
5892 if (out)
5893 return 0;
5894 break;
5895 default:
5896 return 0;
5897 }
5898 if ((time1 >= time2
5899 && (! rld[i].in || rld[i].out
5900 || ! rtx_equal_p (other_input, value)))
5901 || (out && rld[reloadnum].out_reg
5902 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5903 return 0;
5904 }
5905 }
5906 }
5907
5908 /* Earlyclobbered outputs must conflict with inputs. */
5909 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5910 return 0;
5911
5912 return 1;
5913 }
5914
5915 /* Return 1 if the value in reload reg REGNO, as used by a reload
5916 needed for the part of the insn specified by OPNUM and TYPE,
5917 may be used to load VALUE into it.
5918
5919 MODE is the mode in which the register is used, this is needed to
5920 determine how many hard regs to test.
5921
5922 Other read-only reloads with the same value do not conflict
5923 unless OUT is nonzero and these other reloads have to live while
5924 output reloads live.
5925 If OUT is CONST0_RTX, this is a special case: it means that the
5926 test should not be for using register REGNO as reload register, but
5927 for copying from register REGNO into the reload register.
5928
5929 RELOADNUM is the number of the reload we want to load this value for;
5930 a reload does not conflict with itself.
5931
5932 When IGNORE_ADDRESS_RELOADS is set, we cannot have conflicts with
5933 reloads that load an address for the very reload we are considering.
5934
5935 The caller has to make sure that there is no conflict with the return
5936 register. */
5937
5938 static int
free_for_value_p(int regno,machine_mode mode,int opnum,enum reload_type type,rtx value,rtx out,int reloadnum,int ignore_address_reloads)5939 free_for_value_p (int regno, machine_mode mode, int opnum,
5940 enum reload_type type, rtx value, rtx out, int reloadnum,
5941 int ignore_address_reloads)
5942 {
5943 int nregs = hard_regno_nregs (regno, mode);
5944 while (nregs-- > 0)
5945 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5946 value, out, reloadnum,
5947 ignore_address_reloads))
5948 return 0;
5949 return 1;
5950 }
5951
5952 /* Return nonzero if the rtx X is invariant over the current function. */
5953 /* ??? Actually, the places where we use this expect exactly what is
5954 tested here, and not everything that is function invariant. In
5955 particular, the frame pointer and arg pointer are special cased;
5956 pic_offset_table_rtx is not, and we must not spill these things to
5957 memory. */
5958
5959 int
function_invariant_p(const_rtx x)5960 function_invariant_p (const_rtx x)
5961 {
5962 if (CONSTANT_P (x))
5963 return 1;
5964 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
5965 return 1;
5966 if (GET_CODE (x) == PLUS
5967 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
5968 && GET_CODE (XEXP (x, 1)) == CONST_INT)
5969 return 1;
5970 return 0;
5971 }
5972
5973 /* Determine whether the reload reg X overlaps any rtx'es used for
5974 overriding inheritance. Return nonzero if so. */
5975
5976 static int
conflicts_with_override(rtx x)5977 conflicts_with_override (rtx x)
5978 {
5979 int i;
5980 for (i = 0; i < n_reloads; i++)
5981 if (reload_override_in[i]
5982 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5983 return 1;
5984 return 0;
5985 }
5986
5987 /* Give an error message saying we failed to find a reload for INSN,
5988 and clear out reload R. */
5989 static void
failed_reload(rtx_insn * insn,int r)5990 failed_reload (rtx_insn *insn, int r)
5991 {
5992 if (asm_noperands (PATTERN (insn)) < 0)
5993 /* It's the compiler's fault. */
5994 fatal_insn ("could not find a spill register", insn);
5995
5996 /* It's the user's fault; the operand's mode and constraint
5997 don't match. Disable this reload so we don't crash in final. */
5998 error_for_asm (insn,
5999 "%<asm%> operand constraint incompatible with operand size");
6000 rld[r].in = 0;
6001 rld[r].out = 0;
6002 rld[r].reg_rtx = 0;
6003 rld[r].optional = 1;
6004 rld[r].secondary_p = 1;
6005 }
6006
6007 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
6008 for reload R. If it's valid, get an rtx for it. Return nonzero if
6009 successful. */
6010 static int
set_reload_reg(int i,int r)6011 set_reload_reg (int i, int r)
6012 {
6013 int regno;
6014 rtx reg = spill_reg_rtx[i];
6015
6016 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
6017 spill_reg_rtx[i] = reg
6018 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
6019
6020 regno = true_regnum (reg);
6021
6022 /* Detect when the reload reg can't hold the reload mode.
6023 This used to be one `if', but Sequent compiler can't handle that. */
6024 if (targetm.hard_regno_mode_ok (regno, rld[r].mode))
6025 {
6026 machine_mode test_mode = VOIDmode;
6027 if (rld[r].in)
6028 test_mode = GET_MODE (rld[r].in);
6029 /* If rld[r].in has VOIDmode, it means we will load it
6030 in whatever mode the reload reg has: to wit, rld[r].mode.
6031 We have already tested that for validity. */
6032 /* Aside from that, we need to test that the expressions
6033 to reload from or into have modes which are valid for this
6034 reload register. Otherwise the reload insns would be invalid. */
6035 if (! (rld[r].in != 0 && test_mode != VOIDmode
6036 && !targetm.hard_regno_mode_ok (regno, test_mode)))
6037 if (! (rld[r].out != 0
6038 && !targetm.hard_regno_mode_ok (regno, GET_MODE (rld[r].out))))
6039 {
6040 /* The reg is OK. */
6041 last_spill_reg = i;
6042
6043 /* Mark as in use for this insn the reload regs we use
6044 for this. */
6045 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
6046 rld[r].when_needed, rld[r].mode);
6047
6048 rld[r].reg_rtx = reg;
6049 reload_spill_index[r] = spill_regs[i];
6050 return 1;
6051 }
6052 }
6053 return 0;
6054 }
6055
6056 /* Find a spill register to use as a reload register for reload R.
6057 LAST_RELOAD is nonzero if this is the last reload for the insn being
6058 processed.
6059
6060 Set rld[R].reg_rtx to the register allocated.
6061
6062 We return 1 if successful, or 0 if we couldn't find a spill reg and
6063 we didn't change anything. */
6064
6065 static int
allocate_reload_reg(class insn_chain * chain ATTRIBUTE_UNUSED,int r,int last_reload)6066 allocate_reload_reg (class insn_chain *chain ATTRIBUTE_UNUSED, int r,
6067 int last_reload)
6068 {
6069 int i, pass, count;
6070
6071 /* If we put this reload ahead, thinking it is a group,
6072 then insist on finding a group. Otherwise we can grab a
6073 reg that some other reload needs.
6074 (That can happen when we have a 68000 DATA_OR_FP_REG
6075 which is a group of data regs or one fp reg.)
6076 We need not be so restrictive if there are no more reloads
6077 for this insn.
6078
6079 ??? Really it would be nicer to have smarter handling
6080 for that kind of reg class, where a problem like this is normal.
6081 Perhaps those classes should be avoided for reloading
6082 by use of more alternatives. */
6083
6084 int force_group = rld[r].nregs > 1 && ! last_reload;
6085
6086 /* If we want a single register and haven't yet found one,
6087 take any reg in the right class and not in use.
6088 If we want a consecutive group, here is where we look for it.
6089
6090 We use three passes so we can first look for reload regs to
6091 reuse, which are already in use for other reloads in this insn,
6092 and only then use additional registers which are not "bad", then
6093 finally any register.
6094
6095 I think that maximizing reuse is needed to make sure we don't
6096 run out of reload regs. Suppose we have three reloads, and
6097 reloads A and B can share regs. These need two regs.
6098 Suppose A and B are given different regs.
6099 That leaves none for C. */
6100 for (pass = 0; pass < 3; pass++)
6101 {
6102 /* I is the index in spill_regs.
6103 We advance it round-robin between insns to use all spill regs
6104 equally, so that inherited reloads have a chance
6105 of leapfrogging each other. */
6106
6107 i = last_spill_reg;
6108
6109 for (count = 0; count < n_spills; count++)
6110 {
6111 int rclass = (int) rld[r].rclass;
6112 int regnum;
6113
6114 i++;
6115 if (i >= n_spills)
6116 i -= n_spills;
6117 regnum = spill_regs[i];
6118
6119 if ((reload_reg_free_p (regnum, rld[r].opnum,
6120 rld[r].when_needed)
6121 || (rld[r].in
6122 /* We check reload_reg_used to make sure we
6123 don't clobber the return register. */
6124 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
6125 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
6126 rld[r].when_needed, rld[r].in,
6127 rld[r].out, r, 1)))
6128 && TEST_HARD_REG_BIT (reg_class_contents[rclass], regnum)
6129 && targetm.hard_regno_mode_ok (regnum, rld[r].mode)
6130 /* Look first for regs to share, then for unshared. But
6131 don't share regs used for inherited reloads; they are
6132 the ones we want to preserve. */
6133 && (pass
6134 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
6135 regnum)
6136 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
6137 regnum))))
6138 {
6139 int nr = hard_regno_nregs (regnum, rld[r].mode);
6140
6141 /* During the second pass we want to avoid reload registers
6142 which are "bad" for this reload. */
6143 if (pass == 1
6144 && ira_bad_reload_regno (regnum, rld[r].in, rld[r].out))
6145 continue;
6146
6147 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
6148 (on 68000) got us two FP regs. If NR is 1,
6149 we would reject both of them. */
6150 if (force_group)
6151 nr = rld[r].nregs;
6152 /* If we need only one reg, we have already won. */
6153 if (nr == 1)
6154 {
6155 /* But reject a single reg if we demand a group. */
6156 if (force_group)
6157 continue;
6158 break;
6159 }
6160 /* Otherwise check that as many consecutive regs as we need
6161 are available here. */
6162 while (nr > 1)
6163 {
6164 int regno = regnum + nr - 1;
6165 if (!(TEST_HARD_REG_BIT (reg_class_contents[rclass], regno)
6166 && spill_reg_order[regno] >= 0
6167 && reload_reg_free_p (regno, rld[r].opnum,
6168 rld[r].when_needed)))
6169 break;
6170 nr--;
6171 }
6172 if (nr == 1)
6173 break;
6174 }
6175 }
6176
6177 /* If we found something on the current pass, omit later passes. */
6178 if (count < n_spills)
6179 break;
6180 }
6181
6182 /* We should have found a spill register by now. */
6183 if (count >= n_spills)
6184 return 0;
6185
6186 /* I is the index in SPILL_REG_RTX of the reload register we are to
6187 allocate. Get an rtx for it and find its register number. */
6188
6189 return set_reload_reg (i, r);
6190 }
6191
6192 /* Initialize all the tables needed to allocate reload registers.
6193 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
6194 is the array we use to restore the reg_rtx field for every reload. */
6195
6196 static void
choose_reload_regs_init(class insn_chain * chain,rtx * save_reload_reg_rtx)6197 choose_reload_regs_init (class insn_chain *chain, rtx *save_reload_reg_rtx)
6198 {
6199 int i;
6200
6201 for (i = 0; i < n_reloads; i++)
6202 rld[i].reg_rtx = save_reload_reg_rtx[i];
6203
6204 memset (reload_inherited, 0, MAX_RELOADS);
6205 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
6206 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
6207
6208 CLEAR_HARD_REG_SET (reload_reg_used);
6209 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
6210 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
6211 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
6212 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
6213 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
6214
6215 CLEAR_HARD_REG_SET (reg_used_in_insn);
6216 {
6217 HARD_REG_SET tmp;
6218 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
6219 reg_used_in_insn |= tmp;
6220 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
6221 reg_used_in_insn |= tmp;
6222 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
6223 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
6224 }
6225
6226 for (i = 0; i < reload_n_operands; i++)
6227 {
6228 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
6229 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
6230 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
6231 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
6232 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
6233 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
6234 }
6235
6236 reload_reg_unavailable = ~chain->used_spill_regs;
6237
6238 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
6239
6240 for (i = 0; i < n_reloads; i++)
6241 /* If we have already decided to use a certain register,
6242 don't use it in another way. */
6243 if (rld[i].reg_rtx)
6244 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
6245 rld[i].when_needed, rld[i].mode);
6246 }
6247
6248 /* If X is not a subreg, return it unmodified. If it is a subreg,
6249 look up whether we made a replacement for the SUBREG_REG. Return
6250 either the replacement or the SUBREG_REG. */
6251
6252 static rtx
replaced_subreg(rtx x)6253 replaced_subreg (rtx x)
6254 {
6255 if (GET_CODE (x) == SUBREG)
6256 return find_replacement (&SUBREG_REG (x));
6257 return x;
6258 }
6259
6260 /* Compute the offset to pass to subreg_regno_offset, for a pseudo of
6261 mode OUTERMODE that is available in a hard reg of mode INNERMODE.
6262 SUBREG is non-NULL if the pseudo is a subreg whose reg is a pseudo,
6263 otherwise it is NULL. */
6264
6265 static poly_int64
compute_reload_subreg_offset(machine_mode outermode,rtx subreg,machine_mode innermode)6266 compute_reload_subreg_offset (machine_mode outermode,
6267 rtx subreg,
6268 machine_mode innermode)
6269 {
6270 poly_int64 outer_offset;
6271 machine_mode middlemode;
6272
6273 if (!subreg)
6274 return subreg_lowpart_offset (outermode, innermode);
6275
6276 outer_offset = SUBREG_BYTE (subreg);
6277 middlemode = GET_MODE (SUBREG_REG (subreg));
6278
6279 /* If SUBREG is paradoxical then return the normal lowpart offset
6280 for OUTERMODE and INNERMODE. Our caller has already checked
6281 that OUTERMODE fits in INNERMODE. */
6282 if (paradoxical_subreg_p (outermode, middlemode))
6283 return subreg_lowpart_offset (outermode, innermode);
6284
6285 /* SUBREG is normal, but may not be lowpart; return OUTER_OFFSET
6286 plus the normal lowpart offset for MIDDLEMODE and INNERMODE. */
6287 return outer_offset + subreg_lowpart_offset (middlemode, innermode);
6288 }
6289
6290 /* Assign hard reg targets for the pseudo-registers we must reload
6291 into hard regs for this insn.
6292 Also output the instructions to copy them in and out of the hard regs.
6293
6294 For machines with register classes, we are responsible for
6295 finding a reload reg in the proper class. */
6296
6297 static void
choose_reload_regs(class insn_chain * chain)6298 choose_reload_regs (class insn_chain *chain)
6299 {
6300 rtx_insn *insn = chain->insn;
6301 int i, j;
6302 unsigned int max_group_size = 1;
6303 enum reg_class group_class = NO_REGS;
6304 int pass, win, inheritance;
6305
6306 rtx save_reload_reg_rtx[MAX_RELOADS];
6307
6308 /* In order to be certain of getting the registers we need,
6309 we must sort the reloads into order of increasing register class.
6310 Then our grabbing of reload registers will parallel the process
6311 that provided the reload registers.
6312
6313 Also note whether any of the reloads wants a consecutive group of regs.
6314 If so, record the maximum size of the group desired and what
6315 register class contains all the groups needed by this insn. */
6316
6317 for (j = 0; j < n_reloads; j++)
6318 {
6319 reload_order[j] = j;
6320 if (rld[j].reg_rtx != NULL_RTX)
6321 {
6322 gcc_assert (REG_P (rld[j].reg_rtx)
6323 && HARD_REGISTER_P (rld[j].reg_rtx));
6324 reload_spill_index[j] = REGNO (rld[j].reg_rtx);
6325 }
6326 else
6327 reload_spill_index[j] = -1;
6328
6329 if (rld[j].nregs > 1)
6330 {
6331 max_group_size = MAX (rld[j].nregs, max_group_size);
6332 group_class
6333 = reg_class_superunion[(int) rld[j].rclass][(int) group_class];
6334 }
6335
6336 save_reload_reg_rtx[j] = rld[j].reg_rtx;
6337 }
6338
6339 if (n_reloads > 1)
6340 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
6341
6342 /* If -O, try first with inheritance, then turning it off.
6343 If not -O, don't do inheritance.
6344 Using inheritance when not optimizing leads to paradoxes
6345 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
6346 because one side of the comparison might be inherited. */
6347 win = 0;
6348 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
6349 {
6350 choose_reload_regs_init (chain, save_reload_reg_rtx);
6351
6352 /* Process the reloads in order of preference just found.
6353 Beyond this point, subregs can be found in reload_reg_rtx.
6354
6355 This used to look for an existing reloaded home for all of the
6356 reloads, and only then perform any new reloads. But that could lose
6357 if the reloads were done out of reg-class order because a later
6358 reload with a looser constraint might have an old home in a register
6359 needed by an earlier reload with a tighter constraint.
6360
6361 To solve this, we make two passes over the reloads, in the order
6362 described above. In the first pass we try to inherit a reload
6363 from a previous insn. If there is a later reload that needs a
6364 class that is a proper subset of the class being processed, we must
6365 also allocate a spill register during the first pass.
6366
6367 Then make a second pass over the reloads to allocate any reloads
6368 that haven't been given registers yet. */
6369
6370 for (j = 0; j < n_reloads; j++)
6371 {
6372 int r = reload_order[j];
6373 rtx search_equiv = NULL_RTX;
6374
6375 /* Ignore reloads that got marked inoperative. */
6376 if (rld[r].out == 0 && rld[r].in == 0
6377 && ! rld[r].secondary_p)
6378 continue;
6379
6380 /* If find_reloads chose to use reload_in or reload_out as a reload
6381 register, we don't need to chose one. Otherwise, try even if it
6382 found one since we might save an insn if we find the value lying
6383 around.
6384 Try also when reload_in is a pseudo without a hard reg. */
6385 if (rld[r].in != 0 && rld[r].reg_rtx != 0
6386 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
6387 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
6388 && !MEM_P (rld[r].in)
6389 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
6390 continue;
6391
6392 #if 0 /* No longer needed for correct operation.
6393 It might give better code, or might not; worth an experiment? */
6394 /* If this is an optional reload, we can't inherit from earlier insns
6395 until we are sure that any non-optional reloads have been allocated.
6396 The following code takes advantage of the fact that optional reloads
6397 are at the end of reload_order. */
6398 if (rld[r].optional != 0)
6399 for (i = 0; i < j; i++)
6400 if ((rld[reload_order[i]].out != 0
6401 || rld[reload_order[i]].in != 0
6402 || rld[reload_order[i]].secondary_p)
6403 && ! rld[reload_order[i]].optional
6404 && rld[reload_order[i]].reg_rtx == 0)
6405 allocate_reload_reg (chain, reload_order[i], 0);
6406 #endif
6407
6408 /* First see if this pseudo is already available as reloaded
6409 for a previous insn. We cannot try to inherit for reloads
6410 that are smaller than the maximum number of registers needed
6411 for groups unless the register we would allocate cannot be used
6412 for the groups.
6413
6414 We could check here to see if this is a secondary reload for
6415 an object that is already in a register of the desired class.
6416 This would avoid the need for the secondary reload register.
6417 But this is complex because we can't easily determine what
6418 objects might want to be loaded via this reload. So let a
6419 register be allocated here. In `emit_reload_insns' we suppress
6420 one of the loads in the case described above. */
6421
6422 if (inheritance)
6423 {
6424 poly_int64 byte = 0;
6425 int regno = -1;
6426 machine_mode mode = VOIDmode;
6427 rtx subreg = NULL_RTX;
6428
6429 if (rld[r].in == 0)
6430 ;
6431 else if (REG_P (rld[r].in))
6432 {
6433 regno = REGNO (rld[r].in);
6434 mode = GET_MODE (rld[r].in);
6435 }
6436 else if (REG_P (rld[r].in_reg))
6437 {
6438 regno = REGNO (rld[r].in_reg);
6439 mode = GET_MODE (rld[r].in_reg);
6440 }
6441 else if (GET_CODE (rld[r].in_reg) == SUBREG
6442 && REG_P (SUBREG_REG (rld[r].in_reg)))
6443 {
6444 regno = REGNO (SUBREG_REG (rld[r].in_reg));
6445 if (regno < FIRST_PSEUDO_REGISTER)
6446 regno = subreg_regno (rld[r].in_reg);
6447 else
6448 {
6449 subreg = rld[r].in_reg;
6450 byte = SUBREG_BYTE (subreg);
6451 }
6452 mode = GET_MODE (rld[r].in_reg);
6453 }
6454 #if AUTO_INC_DEC
6455 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
6456 && REG_P (XEXP (rld[r].in_reg, 0)))
6457 {
6458 regno = REGNO (XEXP (rld[r].in_reg, 0));
6459 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
6460 rld[r].out = rld[r].in;
6461 }
6462 #endif
6463 #if 0
6464 /* This won't work, since REGNO can be a pseudo reg number.
6465 Also, it takes much more hair to keep track of all the things
6466 that can invalidate an inherited reload of part of a pseudoreg. */
6467 else if (GET_CODE (rld[r].in) == SUBREG
6468 && REG_P (SUBREG_REG (rld[r].in)))
6469 regno = subreg_regno (rld[r].in);
6470 #endif
6471
6472 if (regno >= 0
6473 && reg_last_reload_reg[regno] != 0
6474 && (known_ge
6475 (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg[regno])),
6476 GET_MODE_SIZE (mode) + byte))
6477 /* Verify that the register it's in can be used in
6478 mode MODE. */
6479 && (REG_CAN_CHANGE_MODE_P
6480 (REGNO (reg_last_reload_reg[regno]),
6481 GET_MODE (reg_last_reload_reg[regno]),
6482 mode)))
6483 {
6484 enum reg_class rclass = rld[r].rclass, last_class;
6485 rtx last_reg = reg_last_reload_reg[regno];
6486
6487 i = REGNO (last_reg);
6488 byte = compute_reload_subreg_offset (mode,
6489 subreg,
6490 GET_MODE (last_reg));
6491 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
6492 last_class = REGNO_REG_CLASS (i);
6493
6494 if (reg_reloaded_contents[i] == regno
6495 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
6496 && targetm.hard_regno_mode_ok (i, rld[r].mode)
6497 && (TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], i)
6498 /* Even if we can't use this register as a reload
6499 register, we might use it for reload_override_in,
6500 if copying it to the desired class is cheap
6501 enough. */
6502 || ((register_move_cost (mode, last_class, rclass)
6503 < memory_move_cost (mode, rclass, true))
6504 && (secondary_reload_class (1, rclass, mode,
6505 last_reg)
6506 == NO_REGS)
6507 && !(targetm.secondary_memory_needed
6508 (mode, last_class, rclass))))
6509 && (rld[r].nregs == max_group_size
6510 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
6511 i))
6512 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
6513 rld[r].when_needed, rld[r].in,
6514 const0_rtx, r, 1))
6515 {
6516 /* If a group is needed, verify that all the subsequent
6517 registers still have their values intact. */
6518 int nr = hard_regno_nregs (i, rld[r].mode);
6519 int k;
6520
6521 for (k = 1; k < nr; k++)
6522 if (reg_reloaded_contents[i + k] != regno
6523 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
6524 break;
6525
6526 if (k == nr)
6527 {
6528 int i1;
6529 int bad_for_class;
6530
6531 last_reg = (GET_MODE (last_reg) == mode
6532 ? last_reg : gen_rtx_REG (mode, i));
6533
6534 bad_for_class = 0;
6535 for (k = 0; k < nr; k++)
6536 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6537 i+k);
6538
6539 /* We found a register that contains the
6540 value we need. If this register is the
6541 same as an `earlyclobber' operand of the
6542 current insn, just mark it as a place to
6543 reload from since we can't use it as the
6544 reload register itself. */
6545
6546 for (i1 = 0; i1 < n_earlyclobbers; i1++)
6547 if (reg_overlap_mentioned_for_reload_p
6548 (reg_last_reload_reg[regno],
6549 reload_earlyclobbers[i1]))
6550 break;
6551
6552 if (i1 != n_earlyclobbers
6553 || ! (free_for_value_p (i, rld[r].mode,
6554 rld[r].opnum,
6555 rld[r].when_needed, rld[r].in,
6556 rld[r].out, r, 1))
6557 /* Don't use it if we'd clobber a pseudo reg. */
6558 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
6559 && rld[r].out
6560 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
6561 /* Don't clobber the frame pointer. */
6562 || (i == HARD_FRAME_POINTER_REGNUM
6563 && frame_pointer_needed
6564 && rld[r].out)
6565 /* Don't really use the inherited spill reg
6566 if we need it wider than we've got it. */
6567 || paradoxical_subreg_p (rld[r].mode, mode)
6568 || bad_for_class
6569
6570 /* If find_reloads chose reload_out as reload
6571 register, stay with it - that leaves the
6572 inherited register for subsequent reloads. */
6573 || (rld[r].out && rld[r].reg_rtx
6574 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
6575 {
6576 if (! rld[r].optional)
6577 {
6578 reload_override_in[r] = last_reg;
6579 reload_inheritance_insn[r]
6580 = reg_reloaded_insn[i];
6581 }
6582 }
6583 else
6584 {
6585 int k;
6586 /* We can use this as a reload reg. */
6587 /* Mark the register as in use for this part of
6588 the insn. */
6589 mark_reload_reg_in_use (i,
6590 rld[r].opnum,
6591 rld[r].when_needed,
6592 rld[r].mode);
6593 rld[r].reg_rtx = last_reg;
6594 reload_inherited[r] = 1;
6595 reload_inheritance_insn[r]
6596 = reg_reloaded_insn[i];
6597 reload_spill_index[r] = i;
6598 for (k = 0; k < nr; k++)
6599 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6600 i + k);
6601 }
6602 }
6603 }
6604 }
6605 }
6606
6607 /* Here's another way to see if the value is already lying around. */
6608 if (inheritance
6609 && rld[r].in != 0
6610 && ! reload_inherited[r]
6611 && rld[r].out == 0
6612 && (CONSTANT_P (rld[r].in)
6613 || GET_CODE (rld[r].in) == PLUS
6614 || REG_P (rld[r].in)
6615 || MEM_P (rld[r].in))
6616 && (rld[r].nregs == max_group_size
6617 || ! reg_classes_intersect_p (rld[r].rclass, group_class)))
6618 search_equiv = rld[r].in;
6619
6620 if (search_equiv)
6621 {
6622 rtx equiv
6623 = find_equiv_reg (search_equiv, insn, rld[r].rclass,
6624 -1, NULL, 0, rld[r].mode);
6625 int regno = 0;
6626
6627 if (equiv != 0)
6628 {
6629 if (REG_P (equiv))
6630 regno = REGNO (equiv);
6631 else
6632 {
6633 /* This must be a SUBREG of a hard register.
6634 Make a new REG since this might be used in an
6635 address and not all machines support SUBREGs
6636 there. */
6637 gcc_assert (GET_CODE (equiv) == SUBREG);
6638 regno = subreg_regno (equiv);
6639 equiv = gen_rtx_REG (rld[r].mode, regno);
6640 /* If we choose EQUIV as the reload register, but the
6641 loop below decides to cancel the inheritance, we'll
6642 end up reloading EQUIV in rld[r].mode, not the mode
6643 it had originally. That isn't safe when EQUIV isn't
6644 available as a spill register since its value might
6645 still be live at this point. */
6646 for (i = regno; i < regno + (int) rld[r].nregs; i++)
6647 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
6648 equiv = 0;
6649 }
6650 }
6651
6652 /* If we found a spill reg, reject it unless it is free
6653 and of the desired class. */
6654 if (equiv != 0)
6655 {
6656 int regs_used = 0;
6657 int bad_for_class = 0;
6658 int max_regno = regno + rld[r].nregs;
6659
6660 for (i = regno; i < max_regno; i++)
6661 {
6662 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
6663 i);
6664 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6665 i);
6666 }
6667
6668 if ((regs_used
6669 && ! free_for_value_p (regno, rld[r].mode,
6670 rld[r].opnum, rld[r].when_needed,
6671 rld[r].in, rld[r].out, r, 1))
6672 || bad_for_class)
6673 equiv = 0;
6674 }
6675
6676 if (equiv != 0
6677 && !targetm.hard_regno_mode_ok (regno, rld[r].mode))
6678 equiv = 0;
6679
6680 /* We found a register that contains the value we need.
6681 If this register is the same as an `earlyclobber' operand
6682 of the current insn, just mark it as a place to reload from
6683 since we can't use it as the reload register itself. */
6684
6685 if (equiv != 0)
6686 for (i = 0; i < n_earlyclobbers; i++)
6687 if (reg_overlap_mentioned_for_reload_p (equiv,
6688 reload_earlyclobbers[i]))
6689 {
6690 if (! rld[r].optional)
6691 reload_override_in[r] = equiv;
6692 equiv = 0;
6693 break;
6694 }
6695
6696 /* If the equiv register we have found is explicitly clobbered
6697 in the current insn, it depends on the reload type if we
6698 can use it, use it for reload_override_in, or not at all.
6699 In particular, we then can't use EQUIV for a
6700 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6701
6702 if (equiv != 0)
6703 {
6704 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
6705 switch (rld[r].when_needed)
6706 {
6707 case RELOAD_FOR_OTHER_ADDRESS:
6708 case RELOAD_FOR_INPADDR_ADDRESS:
6709 case RELOAD_FOR_INPUT_ADDRESS:
6710 case RELOAD_FOR_OPADDR_ADDR:
6711 break;
6712 case RELOAD_OTHER:
6713 case RELOAD_FOR_INPUT:
6714 case RELOAD_FOR_OPERAND_ADDRESS:
6715 if (! rld[r].optional)
6716 reload_override_in[r] = equiv;
6717 /* Fall through. */
6718 default:
6719 equiv = 0;
6720 break;
6721 }
6722 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
6723 switch (rld[r].when_needed)
6724 {
6725 case RELOAD_FOR_OTHER_ADDRESS:
6726 case RELOAD_FOR_INPADDR_ADDRESS:
6727 case RELOAD_FOR_INPUT_ADDRESS:
6728 case RELOAD_FOR_OPADDR_ADDR:
6729 case RELOAD_FOR_OPERAND_ADDRESS:
6730 case RELOAD_FOR_INPUT:
6731 break;
6732 case RELOAD_OTHER:
6733 if (! rld[r].optional)
6734 reload_override_in[r] = equiv;
6735 /* Fall through. */
6736 default:
6737 equiv = 0;
6738 break;
6739 }
6740 }
6741
6742 /* If we found an equivalent reg, say no code need be generated
6743 to load it, and use it as our reload reg. */
6744 if (equiv != 0
6745 && (regno != HARD_FRAME_POINTER_REGNUM
6746 || !frame_pointer_needed))
6747 {
6748 int nr = hard_regno_nregs (regno, rld[r].mode);
6749 int k;
6750 rld[r].reg_rtx = equiv;
6751 reload_spill_index[r] = regno;
6752 reload_inherited[r] = 1;
6753
6754 /* If reg_reloaded_valid is not set for this register,
6755 there might be a stale spill_reg_store lying around.
6756 We must clear it, since otherwise emit_reload_insns
6757 might delete the store. */
6758 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6759 spill_reg_store[regno] = NULL;
6760 /* If any of the hard registers in EQUIV are spill
6761 registers, mark them as in use for this insn. */
6762 for (k = 0; k < nr; k++)
6763 {
6764 i = spill_reg_order[regno + k];
6765 if (i >= 0)
6766 {
6767 mark_reload_reg_in_use (regno, rld[r].opnum,
6768 rld[r].when_needed,
6769 rld[r].mode);
6770 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6771 regno + k);
6772 }
6773 }
6774 }
6775 }
6776
6777 /* If we found a register to use already, or if this is an optional
6778 reload, we are done. */
6779 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6780 continue;
6781
6782 #if 0
6783 /* No longer needed for correct operation. Might or might
6784 not give better code on the average. Want to experiment? */
6785
6786 /* See if there is a later reload that has a class different from our
6787 class that intersects our class or that requires less register
6788 than our reload. If so, we must allocate a register to this
6789 reload now, since that reload might inherit a previous reload
6790 and take the only available register in our class. Don't do this
6791 for optional reloads since they will force all previous reloads
6792 to be allocated. Also don't do this for reloads that have been
6793 turned off. */
6794
6795 for (i = j + 1; i < n_reloads; i++)
6796 {
6797 int s = reload_order[i];
6798
6799 if ((rld[s].in == 0 && rld[s].out == 0
6800 && ! rld[s].secondary_p)
6801 || rld[s].optional)
6802 continue;
6803
6804 if ((rld[s].rclass != rld[r].rclass
6805 && reg_classes_intersect_p (rld[r].rclass,
6806 rld[s].rclass))
6807 || rld[s].nregs < rld[r].nregs)
6808 break;
6809 }
6810
6811 if (i == n_reloads)
6812 continue;
6813
6814 allocate_reload_reg (chain, r, j == n_reloads - 1);
6815 #endif
6816 }
6817
6818 /* Now allocate reload registers for anything non-optional that
6819 didn't get one yet. */
6820 for (j = 0; j < n_reloads; j++)
6821 {
6822 int r = reload_order[j];
6823
6824 /* Ignore reloads that got marked inoperative. */
6825 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6826 continue;
6827
6828 /* Skip reloads that already have a register allocated or are
6829 optional. */
6830 if (rld[r].reg_rtx != 0 || rld[r].optional)
6831 continue;
6832
6833 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
6834 break;
6835 }
6836
6837 /* If that loop got all the way, we have won. */
6838 if (j == n_reloads)
6839 {
6840 win = 1;
6841 break;
6842 }
6843
6844 /* Loop around and try without any inheritance. */
6845 }
6846
6847 if (! win)
6848 {
6849 /* First undo everything done by the failed attempt
6850 to allocate with inheritance. */
6851 choose_reload_regs_init (chain, save_reload_reg_rtx);
6852
6853 /* Some sanity tests to verify that the reloads found in the first
6854 pass are identical to the ones we have now. */
6855 gcc_assert (chain->n_reloads == n_reloads);
6856
6857 for (i = 0; i < n_reloads; i++)
6858 {
6859 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6860 continue;
6861 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6862 for (j = 0; j < n_spills; j++)
6863 if (spill_regs[j] == chain->rld[i].regno)
6864 if (! set_reload_reg (j, i))
6865 failed_reload (chain->insn, i);
6866 }
6867 }
6868
6869 /* If we thought we could inherit a reload, because it seemed that
6870 nothing else wanted the same reload register earlier in the insn,
6871 verify that assumption, now that all reloads have been assigned.
6872 Likewise for reloads where reload_override_in has been set. */
6873
6874 /* If doing expensive optimizations, do one preliminary pass that doesn't
6875 cancel any inheritance, but removes reloads that have been needed only
6876 for reloads that we know can be inherited. */
6877 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6878 {
6879 for (j = 0; j < n_reloads; j++)
6880 {
6881 int r = reload_order[j];
6882 rtx check_reg;
6883 rtx tem;
6884 if (reload_inherited[r] && rld[r].reg_rtx)
6885 check_reg = rld[r].reg_rtx;
6886 else if (reload_override_in[r]
6887 && (REG_P (reload_override_in[r])
6888 || GET_CODE (reload_override_in[r]) == SUBREG))
6889 check_reg = reload_override_in[r];
6890 else
6891 continue;
6892 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6893 rld[r].opnum, rld[r].when_needed, rld[r].in,
6894 (reload_inherited[r]
6895 ? rld[r].out : const0_rtx),
6896 r, 1))
6897 {
6898 if (pass)
6899 continue;
6900 reload_inherited[r] = 0;
6901 reload_override_in[r] = 0;
6902 }
6903 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6904 reload_override_in, then we do not need its related
6905 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6906 likewise for other reload types.
6907 We handle this by removing a reload when its only replacement
6908 is mentioned in reload_in of the reload we are going to inherit.
6909 A special case are auto_inc expressions; even if the input is
6910 inherited, we still need the address for the output. We can
6911 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6912 If we succeeded removing some reload and we are doing a preliminary
6913 pass just to remove such reloads, make another pass, since the
6914 removal of one reload might allow us to inherit another one. */
6915 else if (rld[r].in
6916 && rld[r].out != rld[r].in
6917 && remove_address_replacements (rld[r].in))
6918 {
6919 if (pass)
6920 pass = 2;
6921 }
6922 /* If we needed a memory location for the reload, we also have to
6923 remove its related reloads. */
6924 else if (rld[r].in
6925 && rld[r].out != rld[r].in
6926 && (tem = replaced_subreg (rld[r].in), REG_P (tem))
6927 && REGNO (tem) < FIRST_PSEUDO_REGISTER
6928 && (targetm.secondary_memory_needed
6929 (rld[r].inmode, REGNO_REG_CLASS (REGNO (tem)),
6930 rld[r].rclass))
6931 && remove_address_replacements
6932 (get_secondary_mem (tem, rld[r].inmode, rld[r].opnum,
6933 rld[r].when_needed)))
6934 {
6935 if (pass)
6936 pass = 2;
6937 }
6938 }
6939 }
6940
6941 /* Now that reload_override_in is known valid,
6942 actually override reload_in. */
6943 for (j = 0; j < n_reloads; j++)
6944 if (reload_override_in[j])
6945 rld[j].in = reload_override_in[j];
6946
6947 /* If this reload won't be done because it has been canceled or is
6948 optional and not inherited, clear reload_reg_rtx so other
6949 routines (such as subst_reloads) don't get confused. */
6950 for (j = 0; j < n_reloads; j++)
6951 if (rld[j].reg_rtx != 0
6952 && ((rld[j].optional && ! reload_inherited[j])
6953 || (rld[j].in == 0 && rld[j].out == 0
6954 && ! rld[j].secondary_p)))
6955 {
6956 int regno = true_regnum (rld[j].reg_rtx);
6957
6958 if (spill_reg_order[regno] >= 0)
6959 clear_reload_reg_in_use (regno, rld[j].opnum,
6960 rld[j].when_needed, rld[j].mode);
6961 rld[j].reg_rtx = 0;
6962 reload_spill_index[j] = -1;
6963 }
6964
6965 /* Record which pseudos and which spill regs have output reloads. */
6966 for (j = 0; j < n_reloads; j++)
6967 {
6968 int r = reload_order[j];
6969
6970 i = reload_spill_index[r];
6971
6972 /* I is nonneg if this reload uses a register.
6973 If rld[r].reg_rtx is 0, this is an optional reload
6974 that we opted to ignore. */
6975 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
6976 && rld[r].reg_rtx != 0)
6977 {
6978 int nregno = REGNO (rld[r].out_reg);
6979 int nr = 1;
6980
6981 if (nregno < FIRST_PSEUDO_REGISTER)
6982 nr = hard_regno_nregs (nregno, rld[r].mode);
6983
6984 while (--nr >= 0)
6985 SET_REGNO_REG_SET (®_has_output_reload,
6986 nregno + nr);
6987
6988 if (i >= 0)
6989 add_to_hard_reg_set (®_is_output_reload, rld[r].mode, i);
6990
6991 gcc_assert (rld[r].when_needed == RELOAD_OTHER
6992 || rld[r].when_needed == RELOAD_FOR_OUTPUT
6993 || rld[r].when_needed == RELOAD_FOR_INSN);
6994 }
6995 }
6996 }
6997
6998 /* Deallocate the reload register for reload R. This is called from
6999 remove_address_replacements. */
7000
7001 void
deallocate_reload_reg(int r)7002 deallocate_reload_reg (int r)
7003 {
7004 int regno;
7005
7006 if (! rld[r].reg_rtx)
7007 return;
7008 regno = true_regnum (rld[r].reg_rtx);
7009 rld[r].reg_rtx = 0;
7010 if (spill_reg_order[regno] >= 0)
7011 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
7012 rld[r].mode);
7013 reload_spill_index[r] = -1;
7014 }
7015
7016 /* These arrays are filled by emit_reload_insns and its subroutines. */
7017 static rtx_insn *input_reload_insns[MAX_RECOG_OPERANDS];
7018 static rtx_insn *other_input_address_reload_insns = 0;
7019 static rtx_insn *other_input_reload_insns = 0;
7020 static rtx_insn *input_address_reload_insns[MAX_RECOG_OPERANDS];
7021 static rtx_insn *inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
7022 static rtx_insn *output_reload_insns[MAX_RECOG_OPERANDS];
7023 static rtx_insn *output_address_reload_insns[MAX_RECOG_OPERANDS];
7024 static rtx_insn *outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
7025 static rtx_insn *operand_reload_insns = 0;
7026 static rtx_insn *other_operand_reload_insns = 0;
7027 static rtx_insn *other_output_reload_insns[MAX_RECOG_OPERANDS];
7028
7029 /* Values to be put in spill_reg_store are put here first. Instructions
7030 must only be placed here if the associated reload register reaches
7031 the end of the instruction's reload sequence. */
7032 static rtx_insn *new_spill_reg_store[FIRST_PSEUDO_REGISTER];
7033 static HARD_REG_SET reg_reloaded_died;
7034
7035 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
7036 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
7037 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
7038 adjusted register, and return true. Otherwise, return false. */
7039 static bool
reload_adjust_reg_for_temp(rtx * reload_reg,rtx alt_reload_reg,enum reg_class new_class,machine_mode new_mode)7040 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
7041 enum reg_class new_class,
7042 machine_mode new_mode)
7043
7044 {
7045 rtx reg;
7046
7047 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
7048 {
7049 unsigned regno = REGNO (reg);
7050
7051 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
7052 continue;
7053 if (GET_MODE (reg) != new_mode)
7054 {
7055 if (!targetm.hard_regno_mode_ok (regno, new_mode))
7056 continue;
7057 if (hard_regno_nregs (regno, new_mode) > REG_NREGS (reg))
7058 continue;
7059 reg = reload_adjust_reg_for_mode (reg, new_mode);
7060 }
7061 *reload_reg = reg;
7062 return true;
7063 }
7064 return false;
7065 }
7066
7067 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
7068 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
7069 nonzero, if that is suitable. On success, change *RELOAD_REG to the
7070 adjusted register, and return true. Otherwise, return false. */
7071 static bool
reload_adjust_reg_for_icode(rtx * reload_reg,rtx alt_reload_reg,enum insn_code icode)7072 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
7073 enum insn_code icode)
7074
7075 {
7076 enum reg_class new_class = scratch_reload_class (icode);
7077 machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
7078
7079 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
7080 new_class, new_mode);
7081 }
7082
7083 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
7084 has the number J. OLD contains the value to be used as input. */
7085
7086 static void
emit_input_reload_insns(class insn_chain * chain,struct reload * rl,rtx old,int j)7087 emit_input_reload_insns (class insn_chain *chain, struct reload *rl,
7088 rtx old, int j)
7089 {
7090 rtx_insn *insn = chain->insn;
7091 rtx reloadreg;
7092 rtx oldequiv_reg = 0;
7093 rtx oldequiv = 0;
7094 int special = 0;
7095 machine_mode mode;
7096 rtx_insn **where;
7097
7098 /* delete_output_reload is only invoked properly if old contains
7099 the original pseudo register. Since this is replaced with a
7100 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
7101 find the pseudo in RELOAD_IN_REG. This is also used to
7102 determine whether a secondary reload is needed. */
7103 if (reload_override_in[j]
7104 && (REG_P (rl->in_reg)
7105 || (GET_CODE (rl->in_reg) == SUBREG
7106 && REG_P (SUBREG_REG (rl->in_reg)))))
7107 {
7108 oldequiv = old;
7109 old = rl->in_reg;
7110 }
7111 if (oldequiv == 0)
7112 oldequiv = old;
7113 else if (REG_P (oldequiv))
7114 oldequiv_reg = oldequiv;
7115 else if (GET_CODE (oldequiv) == SUBREG)
7116 oldequiv_reg = SUBREG_REG (oldequiv);
7117
7118 reloadreg = reload_reg_rtx_for_input[j];
7119 mode = GET_MODE (reloadreg);
7120
7121 /* If we are reloading from a register that was recently stored in
7122 with an output-reload, see if we can prove there was
7123 actually no need to store the old value in it. */
7124
7125 if (optimize && REG_P (oldequiv)
7126 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
7127 && spill_reg_store[REGNO (oldequiv)]
7128 && REG_P (old)
7129 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
7130 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
7131 rl->out_reg)))
7132 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
7133
7134 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
7135 OLDEQUIV. */
7136
7137 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
7138 oldequiv = SUBREG_REG (oldequiv);
7139 if (GET_MODE (oldequiv) != VOIDmode
7140 && mode != GET_MODE (oldequiv))
7141 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
7142
7143 /* Switch to the right place to emit the reload insns. */
7144 switch (rl->when_needed)
7145 {
7146 case RELOAD_OTHER:
7147 where = &other_input_reload_insns;
7148 break;
7149 case RELOAD_FOR_INPUT:
7150 where = &input_reload_insns[rl->opnum];
7151 break;
7152 case RELOAD_FOR_INPUT_ADDRESS:
7153 where = &input_address_reload_insns[rl->opnum];
7154 break;
7155 case RELOAD_FOR_INPADDR_ADDRESS:
7156 where = &inpaddr_address_reload_insns[rl->opnum];
7157 break;
7158 case RELOAD_FOR_OUTPUT_ADDRESS:
7159 where = &output_address_reload_insns[rl->opnum];
7160 break;
7161 case RELOAD_FOR_OUTADDR_ADDRESS:
7162 where = &outaddr_address_reload_insns[rl->opnum];
7163 break;
7164 case RELOAD_FOR_OPERAND_ADDRESS:
7165 where = &operand_reload_insns;
7166 break;
7167 case RELOAD_FOR_OPADDR_ADDR:
7168 where = &other_operand_reload_insns;
7169 break;
7170 case RELOAD_FOR_OTHER_ADDRESS:
7171 where = &other_input_address_reload_insns;
7172 break;
7173 default:
7174 gcc_unreachable ();
7175 }
7176
7177 push_to_sequence (*where);
7178
7179 /* Auto-increment addresses must be reloaded in a special way. */
7180 if (rl->out && ! rl->out_reg)
7181 {
7182 /* We are not going to bother supporting the case where a
7183 incremented register can't be copied directly from
7184 OLDEQUIV since this seems highly unlikely. */
7185 gcc_assert (rl->secondary_in_reload < 0);
7186
7187 if (reload_inherited[j])
7188 oldequiv = reloadreg;
7189
7190 old = XEXP (rl->in_reg, 0);
7191
7192 /* Prevent normal processing of this reload. */
7193 special = 1;
7194 /* Output a special code sequence for this case. */
7195 inc_for_reload (reloadreg, oldequiv, rl->out, rl->inc);
7196 }
7197
7198 /* If we are reloading a pseudo-register that was set by the previous
7199 insn, see if we can get rid of that pseudo-register entirely
7200 by redirecting the previous insn into our reload register. */
7201
7202 else if (optimize && REG_P (old)
7203 && REGNO (old) >= FIRST_PSEUDO_REGISTER
7204 && dead_or_set_p (insn, old)
7205 /* This is unsafe if some other reload
7206 uses the same reg first. */
7207 && ! conflicts_with_override (reloadreg)
7208 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
7209 rl->when_needed, old, rl->out, j, 0))
7210 {
7211 rtx_insn *temp = PREV_INSN (insn);
7212 while (temp && (NOTE_P (temp) || DEBUG_INSN_P (temp)))
7213 temp = PREV_INSN (temp);
7214 if (temp
7215 && NONJUMP_INSN_P (temp)
7216 && GET_CODE (PATTERN (temp)) == SET
7217 && SET_DEST (PATTERN (temp)) == old
7218 /* Make sure we can access insn_operand_constraint. */
7219 && asm_noperands (PATTERN (temp)) < 0
7220 /* This is unsafe if operand occurs more than once in current
7221 insn. Perhaps some occurrences aren't reloaded. */
7222 && count_occurrences (PATTERN (insn), old, 0) == 1)
7223 {
7224 rtx old = SET_DEST (PATTERN (temp));
7225 /* Store into the reload register instead of the pseudo. */
7226 SET_DEST (PATTERN (temp)) = reloadreg;
7227
7228 /* Verify that resulting insn is valid.
7229
7230 Note that we have replaced the destination of TEMP with
7231 RELOADREG. If TEMP references RELOADREG within an
7232 autoincrement addressing mode, then the resulting insn
7233 is ill-formed and we must reject this optimization. */
7234 extract_insn (temp);
7235 if (constrain_operands (1, get_enabled_alternatives (temp))
7236 && (!AUTO_INC_DEC || ! find_reg_note (temp, REG_INC, reloadreg)))
7237 {
7238 /* If the previous insn is an output reload, the source is
7239 a reload register, and its spill_reg_store entry will
7240 contain the previous destination. This is now
7241 invalid. */
7242 if (REG_P (SET_SRC (PATTERN (temp)))
7243 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
7244 {
7245 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7246 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7247 }
7248
7249 /* If these are the only uses of the pseudo reg,
7250 pretend for GDB it lives in the reload reg we used. */
7251 if (REG_N_DEATHS (REGNO (old)) == 1
7252 && REG_N_SETS (REGNO (old)) == 1)
7253 {
7254 reg_renumber[REGNO (old)] = REGNO (reloadreg);
7255 if (ira_conflicts_p)
7256 /* Inform IRA about the change. */
7257 ira_mark_allocation_change (REGNO (old));
7258 alter_reg (REGNO (old), -1, false);
7259 }
7260 special = 1;
7261
7262 /* Adjust any debug insns between temp and insn. */
7263 while ((temp = NEXT_INSN (temp)) != insn)
7264 if (DEBUG_BIND_INSN_P (temp))
7265 INSN_VAR_LOCATION_LOC (temp)
7266 = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (temp),
7267 old, reloadreg);
7268 else
7269 gcc_assert (DEBUG_INSN_P (temp) || NOTE_P (temp));
7270 }
7271 else
7272 {
7273 SET_DEST (PATTERN (temp)) = old;
7274 }
7275 }
7276 }
7277
7278 /* We can't do that, so output an insn to load RELOADREG. */
7279
7280 /* If we have a secondary reload, pick up the secondary register
7281 and icode, if any. If OLDEQUIV and OLD are different or
7282 if this is an in-out reload, recompute whether or not we
7283 still need a secondary register and what the icode should
7284 be. If we still need a secondary register and the class or
7285 icode is different, go back to reloading from OLD if using
7286 OLDEQUIV means that we got the wrong type of register. We
7287 cannot have different class or icode due to an in-out reload
7288 because we don't make such reloads when both the input and
7289 output need secondary reload registers. */
7290
7291 if (! special && rl->secondary_in_reload >= 0)
7292 {
7293 rtx second_reload_reg = 0;
7294 rtx third_reload_reg = 0;
7295 int secondary_reload = rl->secondary_in_reload;
7296 rtx real_oldequiv = oldequiv;
7297 rtx real_old = old;
7298 rtx tmp;
7299 enum insn_code icode;
7300 enum insn_code tertiary_icode = CODE_FOR_nothing;
7301
7302 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7303 and similarly for OLD.
7304 See comments in get_secondary_reload in reload.cc. */
7305 /* If it is a pseudo that cannot be replaced with its
7306 equivalent MEM, we must fall back to reload_in, which
7307 will have all the necessary substitutions registered.
7308 Likewise for a pseudo that can't be replaced with its
7309 equivalent constant.
7310
7311 Take extra care for subregs of such pseudos. Note that
7312 we cannot use reg_equiv_mem in this case because it is
7313 not in the right mode. */
7314
7315 tmp = oldequiv;
7316 if (GET_CODE (tmp) == SUBREG)
7317 tmp = SUBREG_REG (tmp);
7318 if (REG_P (tmp)
7319 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7320 && (reg_equiv_memory_loc (REGNO (tmp)) != 0
7321 || reg_equiv_constant (REGNO (tmp)) != 0))
7322 {
7323 if (! reg_equiv_mem (REGNO (tmp))
7324 || num_not_at_initial_offset
7325 || GET_CODE (oldequiv) == SUBREG)
7326 real_oldequiv = rl->in;
7327 else
7328 real_oldequiv = reg_equiv_mem (REGNO (tmp));
7329 }
7330
7331 tmp = old;
7332 if (GET_CODE (tmp) == SUBREG)
7333 tmp = SUBREG_REG (tmp);
7334 if (REG_P (tmp)
7335 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7336 && (reg_equiv_memory_loc (REGNO (tmp)) != 0
7337 || reg_equiv_constant (REGNO (tmp)) != 0))
7338 {
7339 if (! reg_equiv_mem (REGNO (tmp))
7340 || num_not_at_initial_offset
7341 || GET_CODE (old) == SUBREG)
7342 real_old = rl->in;
7343 else
7344 real_old = reg_equiv_mem (REGNO (tmp));
7345 }
7346
7347 second_reload_reg = rld[secondary_reload].reg_rtx;
7348 if (rld[secondary_reload].secondary_in_reload >= 0)
7349 {
7350 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
7351
7352 third_reload_reg = rld[tertiary_reload].reg_rtx;
7353 tertiary_icode = rld[secondary_reload].secondary_in_icode;
7354 /* We'd have to add more code for quartary reloads. */
7355 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
7356 }
7357 icode = rl->secondary_in_icode;
7358
7359 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
7360 || (rl->in != 0 && rl->out != 0))
7361 {
7362 secondary_reload_info sri, sri2;
7363 enum reg_class new_class, new_t_class;
7364
7365 sri.icode = CODE_FOR_nothing;
7366 sri.prev_sri = NULL;
7367 new_class
7368 = (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
7369 rl->rclass, mode,
7370 &sri);
7371
7372 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
7373 second_reload_reg = 0;
7374 else if (new_class == NO_REGS)
7375 {
7376 if (reload_adjust_reg_for_icode (&second_reload_reg,
7377 third_reload_reg,
7378 (enum insn_code) sri.icode))
7379 {
7380 icode = (enum insn_code) sri.icode;
7381 third_reload_reg = 0;
7382 }
7383 else
7384 {
7385 oldequiv = old;
7386 real_oldequiv = real_old;
7387 }
7388 }
7389 else if (sri.icode != CODE_FOR_nothing)
7390 /* We currently lack a way to express this in reloads. */
7391 gcc_unreachable ();
7392 else
7393 {
7394 sri2.icode = CODE_FOR_nothing;
7395 sri2.prev_sri = &sri;
7396 new_t_class
7397 = (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
7398 new_class, mode,
7399 &sri);
7400 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
7401 {
7402 if (reload_adjust_reg_for_temp (&second_reload_reg,
7403 third_reload_reg,
7404 new_class, mode))
7405 {
7406 third_reload_reg = 0;
7407 tertiary_icode = (enum insn_code) sri2.icode;
7408 }
7409 else
7410 {
7411 oldequiv = old;
7412 real_oldequiv = real_old;
7413 }
7414 }
7415 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
7416 {
7417 rtx intermediate = second_reload_reg;
7418
7419 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7420 new_class, mode)
7421 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
7422 ((enum insn_code)
7423 sri2.icode)))
7424 {
7425 second_reload_reg = intermediate;
7426 tertiary_icode = (enum insn_code) sri2.icode;
7427 }
7428 else
7429 {
7430 oldequiv = old;
7431 real_oldequiv = real_old;
7432 }
7433 }
7434 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
7435 {
7436 rtx intermediate = second_reload_reg;
7437
7438 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7439 new_class, mode)
7440 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
7441 new_t_class, mode))
7442 {
7443 second_reload_reg = intermediate;
7444 tertiary_icode = (enum insn_code) sri2.icode;
7445 }
7446 else
7447 {
7448 oldequiv = old;
7449 real_oldequiv = real_old;
7450 }
7451 }
7452 else
7453 {
7454 /* This could be handled more intelligently too. */
7455 oldequiv = old;
7456 real_oldequiv = real_old;
7457 }
7458 }
7459 }
7460
7461 /* If we still need a secondary reload register, check
7462 to see if it is being used as a scratch or intermediate
7463 register and generate code appropriately. If we need
7464 a scratch register, use REAL_OLDEQUIV since the form of
7465 the insn may depend on the actual address if it is
7466 a MEM. */
7467
7468 if (second_reload_reg)
7469 {
7470 if (icode != CODE_FOR_nothing)
7471 {
7472 /* We'd have to add extra code to handle this case. */
7473 gcc_assert (!third_reload_reg);
7474
7475 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
7476 second_reload_reg));
7477 special = 1;
7478 }
7479 else
7480 {
7481 /* See if we need a scratch register to load the
7482 intermediate register (a tertiary reload). */
7483 if (tertiary_icode != CODE_FOR_nothing)
7484 {
7485 emit_insn ((GEN_FCN (tertiary_icode)
7486 (second_reload_reg, real_oldequiv,
7487 third_reload_reg)));
7488 }
7489 else if (third_reload_reg)
7490 {
7491 gen_reload (third_reload_reg, real_oldequiv,
7492 rl->opnum,
7493 rl->when_needed);
7494 gen_reload (second_reload_reg, third_reload_reg,
7495 rl->opnum,
7496 rl->when_needed);
7497 }
7498 else
7499 gen_reload (second_reload_reg, real_oldequiv,
7500 rl->opnum,
7501 rl->when_needed);
7502
7503 oldequiv = second_reload_reg;
7504 }
7505 }
7506 }
7507
7508 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
7509 {
7510 rtx real_oldequiv = oldequiv;
7511
7512 if ((REG_P (oldequiv)
7513 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
7514 && (reg_equiv_memory_loc (REGNO (oldequiv)) != 0
7515 || reg_equiv_constant (REGNO (oldequiv)) != 0))
7516 || (GET_CODE (oldequiv) == SUBREG
7517 && REG_P (SUBREG_REG (oldequiv))
7518 && (REGNO (SUBREG_REG (oldequiv))
7519 >= FIRST_PSEUDO_REGISTER)
7520 && ((reg_equiv_memory_loc (REGNO (SUBREG_REG (oldequiv))) != 0)
7521 || (reg_equiv_constant (REGNO (SUBREG_REG (oldequiv))) != 0)))
7522 || (CONSTANT_P (oldequiv)
7523 && (targetm.preferred_reload_class (oldequiv,
7524 REGNO_REG_CLASS (REGNO (reloadreg)))
7525 == NO_REGS)))
7526 real_oldequiv = rl->in;
7527 gen_reload (reloadreg, real_oldequiv, rl->opnum,
7528 rl->when_needed);
7529 }
7530
7531 if (cfun->can_throw_non_call_exceptions)
7532 copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7533
7534 /* End this sequence. */
7535 *where = get_insns ();
7536 end_sequence ();
7537
7538 /* Update reload_override_in so that delete_address_reloads_1
7539 can see the actual register usage. */
7540 if (oldequiv_reg)
7541 reload_override_in[j] = oldequiv;
7542 }
7543
7544 /* Generate insns to for the output reload RL, which is for the insn described
7545 by CHAIN and has the number J. */
7546 static void
emit_output_reload_insns(class insn_chain * chain,struct reload * rl,int j)7547 emit_output_reload_insns (class insn_chain *chain, struct reload *rl,
7548 int j)
7549 {
7550 rtx reloadreg;
7551 rtx_insn *insn = chain->insn;
7552 int special = 0;
7553 rtx old = rl->out;
7554 machine_mode mode;
7555 rtx_insn *p;
7556 rtx rl_reg_rtx;
7557
7558 if (rl->when_needed == RELOAD_OTHER)
7559 start_sequence ();
7560 else
7561 push_to_sequence (output_reload_insns[rl->opnum]);
7562
7563 rl_reg_rtx = reload_reg_rtx_for_output[j];
7564 mode = GET_MODE (rl_reg_rtx);
7565
7566 reloadreg = rl_reg_rtx;
7567
7568 /* If we need two reload regs, set RELOADREG to the intermediate
7569 one, since it will be stored into OLD. We might need a secondary
7570 register only for an input reload, so check again here. */
7571
7572 if (rl->secondary_out_reload >= 0)
7573 {
7574 rtx real_old = old;
7575 int secondary_reload = rl->secondary_out_reload;
7576 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
7577
7578 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
7579 && reg_equiv_mem (REGNO (old)) != 0)
7580 real_old = reg_equiv_mem (REGNO (old));
7581
7582 if (secondary_reload_class (0, rl->rclass, mode, real_old) != NO_REGS)
7583 {
7584 rtx second_reloadreg = reloadreg;
7585 reloadreg = rld[secondary_reload].reg_rtx;
7586
7587 /* See if RELOADREG is to be used as a scratch register
7588 or as an intermediate register. */
7589 if (rl->secondary_out_icode != CODE_FOR_nothing)
7590 {
7591 /* We'd have to add extra code to handle this case. */
7592 gcc_assert (tertiary_reload < 0);
7593
7594 emit_insn ((GEN_FCN (rl->secondary_out_icode)
7595 (real_old, second_reloadreg, reloadreg)));
7596 special = 1;
7597 }
7598 else
7599 {
7600 /* See if we need both a scratch and intermediate reload
7601 register. */
7602
7603 enum insn_code tertiary_icode
7604 = rld[secondary_reload].secondary_out_icode;
7605
7606 /* We'd have to add more code for quartary reloads. */
7607 gcc_assert (tertiary_reload < 0
7608 || rld[tertiary_reload].secondary_out_reload < 0);
7609
7610 if (GET_MODE (reloadreg) != mode)
7611 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7612
7613 if (tertiary_icode != CODE_FOR_nothing)
7614 {
7615 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7616
7617 /* Copy primary reload reg to secondary reload reg.
7618 (Note that these have been swapped above, then
7619 secondary reload reg to OLD using our insn.) */
7620
7621 /* If REAL_OLD is a paradoxical SUBREG, remove it
7622 and try to put the opposite SUBREG on
7623 RELOADREG. */
7624 strip_paradoxical_subreg (&real_old, &reloadreg);
7625
7626 gen_reload (reloadreg, second_reloadreg,
7627 rl->opnum, rl->when_needed);
7628 emit_insn ((GEN_FCN (tertiary_icode)
7629 (real_old, reloadreg, third_reloadreg)));
7630 special = 1;
7631 }
7632
7633 else
7634 {
7635 /* Copy between the reload regs here and then to
7636 OUT later. */
7637
7638 gen_reload (reloadreg, second_reloadreg,
7639 rl->opnum, rl->when_needed);
7640 if (tertiary_reload >= 0)
7641 {
7642 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7643
7644 gen_reload (third_reloadreg, reloadreg,
7645 rl->opnum, rl->when_needed);
7646 reloadreg = third_reloadreg;
7647 }
7648 }
7649 }
7650 }
7651 }
7652
7653 /* Output the last reload insn. */
7654 if (! special)
7655 {
7656 rtx set;
7657
7658 /* Don't output the last reload if OLD is not the dest of
7659 INSN and is in the src and is clobbered by INSN. */
7660 if (! flag_expensive_optimizations
7661 || !REG_P (old)
7662 || !(set = single_set (insn))
7663 || rtx_equal_p (old, SET_DEST (set))
7664 || !reg_mentioned_p (old, SET_SRC (set))
7665 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7666 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7667 gen_reload (old, reloadreg, rl->opnum,
7668 rl->when_needed);
7669 }
7670
7671 /* Look at all insns we emitted, just to be safe. */
7672 for (p = get_insns (); p; p = NEXT_INSN (p))
7673 if (INSN_P (p))
7674 {
7675 rtx pat = PATTERN (p);
7676
7677 /* If this output reload doesn't come from a spill reg,
7678 clear any memory of reloaded copies of the pseudo reg.
7679 If this output reload comes from a spill reg,
7680 reg_has_output_reload will make this do nothing. */
7681 note_stores (p, forget_old_reloads_1, NULL);
7682
7683 if (reg_mentioned_p (rl_reg_rtx, pat))
7684 {
7685 rtx set = single_set (insn);
7686 if (reload_spill_index[j] < 0
7687 && set
7688 && SET_SRC (set) == rl_reg_rtx)
7689 {
7690 int src = REGNO (SET_SRC (set));
7691
7692 reload_spill_index[j] = src;
7693 SET_HARD_REG_BIT (reg_is_output_reload, src);
7694 if (find_regno_note (insn, REG_DEAD, src))
7695 SET_HARD_REG_BIT (reg_reloaded_died, src);
7696 }
7697 if (HARD_REGISTER_P (rl_reg_rtx))
7698 {
7699 int s = rl->secondary_out_reload;
7700 set = single_set (p);
7701 /* If this reload copies only to the secondary reload
7702 register, the secondary reload does the actual
7703 store. */
7704 if (s >= 0 && set == NULL_RTX)
7705 /* We can't tell what function the secondary reload
7706 has and where the actual store to the pseudo is
7707 made; leave new_spill_reg_store alone. */
7708 ;
7709 else if (s >= 0
7710 && SET_SRC (set) == rl_reg_rtx
7711 && SET_DEST (set) == rld[s].reg_rtx)
7712 {
7713 /* Usually the next instruction will be the
7714 secondary reload insn; if we can confirm
7715 that it is, setting new_spill_reg_store to
7716 that insn will allow an extra optimization. */
7717 rtx s_reg = rld[s].reg_rtx;
7718 rtx_insn *next = NEXT_INSN (p);
7719 rld[s].out = rl->out;
7720 rld[s].out_reg = rl->out_reg;
7721 set = single_set (next);
7722 if (set && SET_SRC (set) == s_reg
7723 && reload_reg_rtx_reaches_end_p (s_reg, s))
7724 {
7725 SET_HARD_REG_BIT (reg_is_output_reload,
7726 REGNO (s_reg));
7727 new_spill_reg_store[REGNO (s_reg)] = next;
7728 }
7729 }
7730 else if (reload_reg_rtx_reaches_end_p (rl_reg_rtx, j))
7731 new_spill_reg_store[REGNO (rl_reg_rtx)] = p;
7732 }
7733 }
7734 }
7735
7736 if (rl->when_needed == RELOAD_OTHER)
7737 {
7738 emit_insn (other_output_reload_insns[rl->opnum]);
7739 other_output_reload_insns[rl->opnum] = get_insns ();
7740 }
7741 else
7742 output_reload_insns[rl->opnum] = get_insns ();
7743
7744 if (cfun->can_throw_non_call_exceptions)
7745 copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7746
7747 end_sequence ();
7748 }
7749
7750 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7751 and has the number J. */
7752 static void
do_input_reload(class insn_chain * chain,struct reload * rl,int j)7753 do_input_reload (class insn_chain *chain, struct reload *rl, int j)
7754 {
7755 rtx_insn *insn = chain->insn;
7756 rtx old = (rl->in && MEM_P (rl->in)
7757 ? rl->in_reg : rl->in);
7758 rtx reg_rtx = rl->reg_rtx;
7759
7760 if (old && reg_rtx)
7761 {
7762 machine_mode mode;
7763
7764 /* Determine the mode to reload in.
7765 This is very tricky because we have three to choose from.
7766 There is the mode the insn operand wants (rl->inmode).
7767 There is the mode of the reload register RELOADREG.
7768 There is the intrinsic mode of the operand, which we could find
7769 by stripping some SUBREGs.
7770 It turns out that RELOADREG's mode is irrelevant:
7771 we can change that arbitrarily.
7772
7773 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7774 then the reload reg may not support QImode moves, so use SImode.
7775 If foo is in memory due to spilling a pseudo reg, this is safe,
7776 because the QImode value is in the least significant part of a
7777 slot big enough for a SImode. If foo is some other sort of
7778 memory reference, then it is impossible to reload this case,
7779 so previous passes had better make sure this never happens.
7780
7781 Then consider a one-word union which has SImode and one of its
7782 members is a float, being fetched as (SUBREG:SF union:SI).
7783 We must fetch that as SFmode because we could be loading into
7784 a float-only register. In this case OLD's mode is correct.
7785
7786 Consider an immediate integer: it has VOIDmode. Here we need
7787 to get a mode from something else.
7788
7789 In some cases, there is a fourth mode, the operand's
7790 containing mode. If the insn specifies a containing mode for
7791 this operand, it overrides all others.
7792
7793 I am not sure whether the algorithm here is always right,
7794 but it does the right things in those cases. */
7795
7796 mode = GET_MODE (old);
7797 if (mode == VOIDmode)
7798 mode = rl->inmode;
7799
7800 /* We cannot use gen_lowpart_common since it can do the wrong thing
7801 when REG_RTX has a multi-word mode. Note that REG_RTX must
7802 always be a REG here. */
7803 if (GET_MODE (reg_rtx) != mode)
7804 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7805 }
7806 reload_reg_rtx_for_input[j] = reg_rtx;
7807
7808 if (old != 0
7809 /* AUTO_INC reloads need to be handled even if inherited. We got an
7810 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7811 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7812 && ! rtx_equal_p (reg_rtx, old)
7813 && reg_rtx != 0)
7814 emit_input_reload_insns (chain, rld + j, old, j);
7815
7816 /* When inheriting a wider reload, we have a MEM in rl->in,
7817 e.g. inheriting a SImode output reload for
7818 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7819 if (optimize && reload_inherited[j] && rl->in
7820 && MEM_P (rl->in)
7821 && MEM_P (rl->in_reg)
7822 && reload_spill_index[j] >= 0
7823 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7824 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7825
7826 /* If we are reloading a register that was recently stored in with an
7827 output-reload, see if we can prove there was
7828 actually no need to store the old value in it. */
7829
7830 if (optimize
7831 && (reload_inherited[j] || reload_override_in[j])
7832 && reg_rtx
7833 && REG_P (reg_rtx)
7834 && spill_reg_store[REGNO (reg_rtx)] != 0
7835 #if 0
7836 /* There doesn't seem to be any reason to restrict this to pseudos
7837 and doing so loses in the case where we are copying from a
7838 register of the wrong class. */
7839 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)])
7840 #endif
7841 /* The insn might have already some references to stackslots
7842 replaced by MEMs, while reload_out_reg still names the
7843 original pseudo. */
7844 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)])
7845 || rtx_equal_p (spill_reg_stored_to[REGNO (reg_rtx)], rl->out_reg)))
7846 delete_output_reload (insn, j, REGNO (reg_rtx), reg_rtx);
7847 }
7848
7849 /* Do output reloading for reload RL, which is for the insn described by
7850 CHAIN and has the number J.
7851 ??? At some point we need to support handling output reloads of
7852 JUMP_INSNs. */
7853 static void
do_output_reload(class insn_chain * chain,struct reload * rl,int j)7854 do_output_reload (class insn_chain *chain, struct reload *rl, int j)
7855 {
7856 rtx note, old;
7857 rtx_insn *insn = chain->insn;
7858 /* If this is an output reload that stores something that is
7859 not loaded in this same reload, see if we can eliminate a previous
7860 store. */
7861 rtx pseudo = rl->out_reg;
7862 rtx reg_rtx = rl->reg_rtx;
7863
7864 if (rl->out && reg_rtx)
7865 {
7866 machine_mode mode;
7867
7868 /* Determine the mode to reload in.
7869 See comments above (for input reloading). */
7870 mode = GET_MODE (rl->out);
7871 if (mode == VOIDmode)
7872 {
7873 /* VOIDmode should never happen for an output. */
7874 if (asm_noperands (PATTERN (insn)) < 0)
7875 /* It's the compiler's fault. */
7876 fatal_insn ("VOIDmode on an output", insn);
7877 error_for_asm (insn, "output operand is constant in %<asm%>");
7878 /* Prevent crash--use something we know is valid. */
7879 mode = word_mode;
7880 rl->out = gen_rtx_REG (mode, REGNO (reg_rtx));
7881 }
7882 if (GET_MODE (reg_rtx) != mode)
7883 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7884 }
7885 reload_reg_rtx_for_output[j] = reg_rtx;
7886
7887 if (pseudo
7888 && optimize
7889 && REG_P (pseudo)
7890 && ! rtx_equal_p (rl->in_reg, pseudo)
7891 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7892 && reg_last_reload_reg[REGNO (pseudo)])
7893 {
7894 int pseudo_no = REGNO (pseudo);
7895 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7896
7897 /* We don't need to test full validity of last_regno for
7898 inherit here; we only want to know if the store actually
7899 matches the pseudo. */
7900 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7901 && reg_reloaded_contents[last_regno] == pseudo_no
7902 && spill_reg_store[last_regno]
7903 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7904 delete_output_reload (insn, j, last_regno, reg_rtx);
7905 }
7906
7907 old = rl->out_reg;
7908 if (old == 0
7909 || reg_rtx == 0
7910 || rtx_equal_p (old, reg_rtx))
7911 return;
7912
7913 /* An output operand that dies right away does need a reload,
7914 but need not be copied from it. Show the new location in the
7915 REG_UNUSED note. */
7916 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7917 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7918 {
7919 XEXP (note, 0) = reg_rtx;
7920 return;
7921 }
7922 /* Likewise for a SUBREG of an operand that dies. */
7923 else if (GET_CODE (old) == SUBREG
7924 && REG_P (SUBREG_REG (old))
7925 && (note = find_reg_note (insn, REG_UNUSED,
7926 SUBREG_REG (old))) != 0)
7927 {
7928 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), reg_rtx);
7929 return;
7930 }
7931 else if (GET_CODE (old) == SCRATCH)
7932 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7933 but we don't want to make an output reload. */
7934 return;
7935
7936 /* If is a JUMP_INSN, we can't support output reloads yet. */
7937 gcc_assert (NONJUMP_INSN_P (insn));
7938
7939 emit_output_reload_insns (chain, rld + j, j);
7940 }
7941
7942 /* A reload copies values of MODE from register SRC to register DEST.
7943 Return true if it can be treated for inheritance purposes like a
7944 group of reloads, each one reloading a single hard register. The
7945 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
7946 occupy the same number of hard registers. */
7947
7948 static bool
inherit_piecemeal_p(int dest ATTRIBUTE_UNUSED,int src ATTRIBUTE_UNUSED,machine_mode mode ATTRIBUTE_UNUSED)7949 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED,
7950 int src ATTRIBUTE_UNUSED,
7951 machine_mode mode ATTRIBUTE_UNUSED)
7952 {
7953 return (REG_CAN_CHANGE_MODE_P (dest, mode, reg_raw_mode[dest])
7954 && REG_CAN_CHANGE_MODE_P (src, mode, reg_raw_mode[src]));
7955 }
7956
7957 /* Output insns to reload values in and out of the chosen reload regs. */
7958
7959 static void
emit_reload_insns(class insn_chain * chain)7960 emit_reload_insns (class insn_chain *chain)
7961 {
7962 rtx_insn *insn = chain->insn;
7963
7964 int j;
7965
7966 CLEAR_HARD_REG_SET (reg_reloaded_died);
7967
7968 for (j = 0; j < reload_n_operands; j++)
7969 input_reload_insns[j] = input_address_reload_insns[j]
7970 = inpaddr_address_reload_insns[j]
7971 = output_reload_insns[j] = output_address_reload_insns[j]
7972 = outaddr_address_reload_insns[j]
7973 = other_output_reload_insns[j] = 0;
7974 other_input_address_reload_insns = 0;
7975 other_input_reload_insns = 0;
7976 operand_reload_insns = 0;
7977 other_operand_reload_insns = 0;
7978
7979 /* Dump reloads into the dump file. */
7980 if (dump_file)
7981 {
7982 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7983 debug_reload_to_stream (dump_file);
7984 }
7985
7986 for (j = 0; j < n_reloads; j++)
7987 if (rld[j].reg_rtx && HARD_REGISTER_P (rld[j].reg_rtx))
7988 {
7989 unsigned int i;
7990
7991 for (i = REGNO (rld[j].reg_rtx); i < END_REGNO (rld[j].reg_rtx); i++)
7992 new_spill_reg_store[i] = 0;
7993 }
7994
7995 /* Now output the instructions to copy the data into and out of the
7996 reload registers. Do these in the order that the reloads were reported,
7997 since reloads of base and index registers precede reloads of operands
7998 and the operands may need the base and index registers reloaded. */
7999
8000 for (j = 0; j < n_reloads; j++)
8001 {
8002 do_input_reload (chain, rld + j, j);
8003 do_output_reload (chain, rld + j, j);
8004 }
8005
8006 /* Now write all the insns we made for reloads in the order expected by
8007 the allocation functions. Prior to the insn being reloaded, we write
8008 the following reloads:
8009
8010 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
8011
8012 RELOAD_OTHER reloads.
8013
8014 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
8015 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
8016 RELOAD_FOR_INPUT reload for the operand.
8017
8018 RELOAD_FOR_OPADDR_ADDRS reloads.
8019
8020 RELOAD_FOR_OPERAND_ADDRESS reloads.
8021
8022 After the insn being reloaded, we write the following:
8023
8024 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
8025 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
8026 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
8027 reloads for the operand. The RELOAD_OTHER output reloads are
8028 output in descending order by reload number. */
8029
8030 emit_insn_before (other_input_address_reload_insns, insn);
8031 emit_insn_before (other_input_reload_insns, insn);
8032
8033 for (j = 0; j < reload_n_operands; j++)
8034 {
8035 emit_insn_before (inpaddr_address_reload_insns[j], insn);
8036 emit_insn_before (input_address_reload_insns[j], insn);
8037 emit_insn_before (input_reload_insns[j], insn);
8038 }
8039
8040 emit_insn_before (other_operand_reload_insns, insn);
8041 emit_insn_before (operand_reload_insns, insn);
8042
8043 for (j = 0; j < reload_n_operands; j++)
8044 {
8045 rtx_insn *x = emit_insn_after (outaddr_address_reload_insns[j], insn);
8046 x = emit_insn_after (output_address_reload_insns[j], x);
8047 x = emit_insn_after (output_reload_insns[j], x);
8048 emit_insn_after (other_output_reload_insns[j], x);
8049 }
8050
8051 /* For all the spill regs newly reloaded in this instruction,
8052 record what they were reloaded from, so subsequent instructions
8053 can inherit the reloads.
8054
8055 Update spill_reg_store for the reloads of this insn.
8056 Copy the elements that were updated in the loop above. */
8057
8058 for (j = 0; j < n_reloads; j++)
8059 {
8060 int r = reload_order[j];
8061 int i = reload_spill_index[r];
8062
8063 /* If this is a non-inherited input reload from a pseudo, we must
8064 clear any memory of a previous store to the same pseudo. Only do
8065 something if there will not be an output reload for the pseudo
8066 being reloaded. */
8067 if (rld[r].in_reg != 0
8068 && ! (reload_inherited[r] || reload_override_in[r]))
8069 {
8070 rtx reg = rld[r].in_reg;
8071
8072 if (GET_CODE (reg) == SUBREG)
8073 reg = SUBREG_REG (reg);
8074
8075 if (REG_P (reg)
8076 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
8077 && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg)))
8078 {
8079 int nregno = REGNO (reg);
8080
8081 if (reg_last_reload_reg[nregno])
8082 {
8083 int last_regno = REGNO (reg_last_reload_reg[nregno]);
8084
8085 if (reg_reloaded_contents[last_regno] == nregno)
8086 spill_reg_store[last_regno] = 0;
8087 }
8088 }
8089 }
8090
8091 /* I is nonneg if this reload used a register.
8092 If rld[r].reg_rtx is 0, this is an optional reload
8093 that we opted to ignore. */
8094
8095 if (i >= 0 && rld[r].reg_rtx != 0)
8096 {
8097 int nr = hard_regno_nregs (i, GET_MODE (rld[r].reg_rtx));
8098 int k;
8099
8100 /* For a multi register reload, we need to check if all or part
8101 of the value lives to the end. */
8102 for (k = 0; k < nr; k++)
8103 if (reload_reg_reaches_end_p (i + k, r))
8104 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
8105
8106 /* Maybe the spill reg contains a copy of reload_out. */
8107 if (rld[r].out != 0
8108 && (REG_P (rld[r].out)
8109 || (rld[r].out_reg
8110 ? REG_P (rld[r].out_reg)
8111 /* The reload value is an auto-modification of
8112 some kind. For PRE_INC, POST_INC, PRE_DEC
8113 and POST_DEC, we record an equivalence
8114 between the reload register and the operand
8115 on the optimistic assumption that we can make
8116 the equivalence hold. reload_as_needed must
8117 then either make it hold or invalidate the
8118 equivalence.
8119
8120 PRE_MODIFY and POST_MODIFY addresses are reloaded
8121 somewhat differently, and allowing them here leads
8122 to problems. */
8123 : (GET_CODE (rld[r].out) != POST_MODIFY
8124 && GET_CODE (rld[r].out) != PRE_MODIFY))))
8125 {
8126 rtx reg;
8127
8128 reg = reload_reg_rtx_for_output[r];
8129 if (reload_reg_rtx_reaches_end_p (reg, r))
8130 {
8131 machine_mode mode = GET_MODE (reg);
8132 int regno = REGNO (reg);
8133 int nregs = REG_NREGS (reg);
8134 rtx out = (REG_P (rld[r].out)
8135 ? rld[r].out
8136 : rld[r].out_reg
8137 ? rld[r].out_reg
8138 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
8139 int out_regno = REGNO (out);
8140 int out_nregs = (!HARD_REGISTER_NUM_P (out_regno) ? 1
8141 : hard_regno_nregs (out_regno, mode));
8142 bool piecemeal;
8143
8144 spill_reg_store[regno] = new_spill_reg_store[regno];
8145 spill_reg_stored_to[regno] = out;
8146 reg_last_reload_reg[out_regno] = reg;
8147
8148 piecemeal = (HARD_REGISTER_NUM_P (out_regno)
8149 && nregs == out_nregs
8150 && inherit_piecemeal_p (out_regno, regno, mode));
8151
8152 /* If OUT_REGNO is a hard register, it may occupy more than
8153 one register. If it does, say what is in the
8154 rest of the registers assuming that both registers
8155 agree on how many words the object takes. If not,
8156 invalidate the subsequent registers. */
8157
8158 if (HARD_REGISTER_NUM_P (out_regno))
8159 for (k = 1; k < out_nregs; k++)
8160 reg_last_reload_reg[out_regno + k]
8161 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
8162
8163 /* Now do the inverse operation. */
8164 for (k = 0; k < nregs; k++)
8165 {
8166 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8167 reg_reloaded_contents[regno + k]
8168 = (!HARD_REGISTER_NUM_P (out_regno) || !piecemeal
8169 ? out_regno
8170 : out_regno + k);
8171 reg_reloaded_insn[regno + k] = insn;
8172 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8173 }
8174 }
8175 }
8176 /* Maybe the spill reg contains a copy of reload_in. Only do
8177 something if there will not be an output reload for
8178 the register being reloaded. */
8179 else if (rld[r].out_reg == 0
8180 && rld[r].in != 0
8181 && ((REG_P (rld[r].in)
8182 && !HARD_REGISTER_P (rld[r].in)
8183 && !REGNO_REG_SET_P (®_has_output_reload,
8184 REGNO (rld[r].in)))
8185 || (REG_P (rld[r].in_reg)
8186 && !REGNO_REG_SET_P (®_has_output_reload,
8187 REGNO (rld[r].in_reg))))
8188 && !reg_set_p (reload_reg_rtx_for_input[r], PATTERN (insn)))
8189 {
8190 rtx reg;
8191
8192 reg = reload_reg_rtx_for_input[r];
8193 if (reload_reg_rtx_reaches_end_p (reg, r))
8194 {
8195 machine_mode mode;
8196 int regno;
8197 int nregs;
8198 int in_regno;
8199 int in_nregs;
8200 rtx in;
8201 bool piecemeal;
8202
8203 mode = GET_MODE (reg);
8204 regno = REGNO (reg);
8205 nregs = REG_NREGS (reg);
8206 if (REG_P (rld[r].in)
8207 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
8208 in = rld[r].in;
8209 else if (REG_P (rld[r].in_reg))
8210 in = rld[r].in_reg;
8211 else
8212 in = XEXP (rld[r].in_reg, 0);
8213 in_regno = REGNO (in);
8214
8215 in_nregs = (!HARD_REGISTER_NUM_P (in_regno) ? 1
8216 : hard_regno_nregs (in_regno, mode));
8217
8218 reg_last_reload_reg[in_regno] = reg;
8219
8220 piecemeal = (HARD_REGISTER_NUM_P (in_regno)
8221 && nregs == in_nregs
8222 && inherit_piecemeal_p (regno, in_regno, mode));
8223
8224 if (HARD_REGISTER_NUM_P (in_regno))
8225 for (k = 1; k < in_nregs; k++)
8226 reg_last_reload_reg[in_regno + k]
8227 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
8228
8229 /* Unless we inherited this reload, show we haven't
8230 recently done a store.
8231 Previous stores of inherited auto_inc expressions
8232 also have to be discarded. */
8233 if (! reload_inherited[r]
8234 || (rld[r].out && ! rld[r].out_reg))
8235 spill_reg_store[regno] = 0;
8236
8237 for (k = 0; k < nregs; k++)
8238 {
8239 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8240 reg_reloaded_contents[regno + k]
8241 = (!HARD_REGISTER_NUM_P (in_regno) || !piecemeal
8242 ? in_regno
8243 : in_regno + k);
8244 reg_reloaded_insn[regno + k] = insn;
8245 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8246 }
8247 }
8248 }
8249 }
8250
8251 /* The following if-statement was #if 0'd in 1.34 (or before...).
8252 It's reenabled in 1.35 because supposedly nothing else
8253 deals with this problem. */
8254
8255 /* If a register gets output-reloaded from a non-spill register,
8256 that invalidates any previous reloaded copy of it.
8257 But forget_old_reloads_1 won't get to see it, because
8258 it thinks only about the original insn. So invalidate it here.
8259 Also do the same thing for RELOAD_OTHER constraints where the
8260 output is discarded. */
8261 if (i < 0
8262 && ((rld[r].out != 0
8263 && (REG_P (rld[r].out)
8264 || (MEM_P (rld[r].out)
8265 && REG_P (rld[r].out_reg))))
8266 || (rld[r].out == 0 && rld[r].out_reg
8267 && REG_P (rld[r].out_reg))))
8268 {
8269 rtx out = ((rld[r].out && REG_P (rld[r].out))
8270 ? rld[r].out : rld[r].out_reg);
8271 int out_regno = REGNO (out);
8272 machine_mode mode = GET_MODE (out);
8273
8274 /* REG_RTX is now set or clobbered by the main instruction.
8275 As the comment above explains, forget_old_reloads_1 only
8276 sees the original instruction, and there is no guarantee
8277 that the original instruction also clobbered REG_RTX.
8278 For example, if find_reloads sees that the input side of
8279 a matched operand pair dies in this instruction, it may
8280 use the input register as the reload register.
8281
8282 Calling forget_old_reloads_1 is a waste of effort if
8283 REG_RTX is also the output register.
8284
8285 If we know that REG_RTX holds the value of a pseudo
8286 register, the code after the call will record that fact. */
8287 if (rld[r].reg_rtx && rld[r].reg_rtx != out)
8288 forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
8289
8290 if (!HARD_REGISTER_NUM_P (out_regno))
8291 {
8292 rtx src_reg;
8293 rtx_insn *store_insn = NULL;
8294
8295 reg_last_reload_reg[out_regno] = 0;
8296
8297 /* If we can find a hard register that is stored, record
8298 the storing insn so that we may delete this insn with
8299 delete_output_reload. */
8300 src_reg = reload_reg_rtx_for_output[r];
8301
8302 if (src_reg)
8303 {
8304 if (reload_reg_rtx_reaches_end_p (src_reg, r))
8305 store_insn = new_spill_reg_store[REGNO (src_reg)];
8306 else
8307 src_reg = NULL_RTX;
8308 }
8309 else
8310 {
8311 /* If this is an optional reload, try to find the
8312 source reg from an input reload. */
8313 rtx set = single_set (insn);
8314 if (set && SET_DEST (set) == rld[r].out)
8315 {
8316 int k;
8317
8318 src_reg = SET_SRC (set);
8319 store_insn = insn;
8320 for (k = 0; k < n_reloads; k++)
8321 {
8322 if (rld[k].in == src_reg)
8323 {
8324 src_reg = reload_reg_rtx_for_input[k];
8325 break;
8326 }
8327 }
8328 }
8329 }
8330 if (src_reg && REG_P (src_reg)
8331 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
8332 {
8333 int src_regno, src_nregs, k;
8334 rtx note;
8335
8336 gcc_assert (GET_MODE (src_reg) == mode);
8337 src_regno = REGNO (src_reg);
8338 src_nregs = hard_regno_nregs (src_regno, mode);
8339 /* The place where to find a death note varies with
8340 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
8341 necessarily checked exactly in the code that moves
8342 notes, so just check both locations. */
8343 note = find_regno_note (insn, REG_DEAD, src_regno);
8344 if (! note && store_insn)
8345 note = find_regno_note (store_insn, REG_DEAD, src_regno);
8346 for (k = 0; k < src_nregs; k++)
8347 {
8348 spill_reg_store[src_regno + k] = store_insn;
8349 spill_reg_stored_to[src_regno + k] = out;
8350 reg_reloaded_contents[src_regno + k] = out_regno;
8351 reg_reloaded_insn[src_regno + k] = store_insn;
8352 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + k);
8353 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + k);
8354 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + k);
8355 if (note)
8356 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
8357 else
8358 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
8359 }
8360 reg_last_reload_reg[out_regno] = src_reg;
8361 /* We have to set reg_has_output_reload here, or else
8362 forget_old_reloads_1 will clear reg_last_reload_reg
8363 right away. */
8364 SET_REGNO_REG_SET (®_has_output_reload,
8365 out_regno);
8366 }
8367 }
8368 else
8369 {
8370 int k, out_nregs = hard_regno_nregs (out_regno, mode);
8371
8372 for (k = 0; k < out_nregs; k++)
8373 reg_last_reload_reg[out_regno + k] = 0;
8374 }
8375 }
8376 }
8377 reg_reloaded_dead |= reg_reloaded_died;
8378 }
8379
8380 /* Go through the motions to emit INSN and test if it is strictly valid.
8381 Return the emitted insn if valid, else return NULL. */
8382
8383 static rtx_insn *
emit_insn_if_valid_for_reload(rtx pat)8384 emit_insn_if_valid_for_reload (rtx pat)
8385 {
8386 rtx_insn *last = get_last_insn ();
8387 int code;
8388
8389 rtx_insn *insn = emit_insn (pat);
8390 code = recog_memoized (insn);
8391
8392 if (code >= 0)
8393 {
8394 extract_insn (insn);
8395 /* We want constrain operands to treat this insn strictly in its
8396 validity determination, i.e., the way it would after reload has
8397 completed. */
8398 if (constrain_operands (1, get_enabled_alternatives (insn)))
8399 return insn;
8400 }
8401
8402 delete_insns_since (last);
8403 return NULL;
8404 }
8405
8406 /* Emit code to perform a reload from IN (which may be a reload register) to
8407 OUT (which may also be a reload register). IN or OUT is from operand
8408 OPNUM with reload type TYPE.
8409
8410 Returns first insn emitted. */
8411
8412 static rtx_insn *
gen_reload(rtx out,rtx in,int opnum,enum reload_type type)8413 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
8414 {
8415 rtx_insn *last = get_last_insn ();
8416 rtx_insn *tem;
8417 rtx tem1, tem2;
8418
8419 /* If IN is a paradoxical SUBREG, remove it and try to put the
8420 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
8421 if (!strip_paradoxical_subreg (&in, &out))
8422 strip_paradoxical_subreg (&out, &in);
8423
8424 /* How to do this reload can get quite tricky. Normally, we are being
8425 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8426 register that didn't get a hard register. In that case we can just
8427 call emit_move_insn.
8428
8429 We can also be asked to reload a PLUS that adds a register or a MEM to
8430 another register, constant or MEM. This can occur during frame pointer
8431 elimination and while reloading addresses. This case is handled by
8432 trying to emit a single insn to perform the add. If it is not valid,
8433 we use a two insn sequence.
8434
8435 Or we can be asked to reload an unary operand that was a fragment of
8436 an addressing mode, into a register. If it isn't recognized as-is,
8437 we try making the unop operand and the reload-register the same:
8438 (set reg:X (unop:X expr:Y))
8439 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8440
8441 Finally, we could be called to handle an 'o' constraint by putting
8442 an address into a register. In that case, we first try to do this
8443 with a named pattern of "reload_load_address". If no such pattern
8444 exists, we just emit a SET insn and hope for the best (it will normally
8445 be valid on machines that use 'o').
8446
8447 This entire process is made complex because reload will never
8448 process the insns we generate here and so we must ensure that
8449 they will fit their constraints and also by the fact that parts of
8450 IN might be being reloaded separately and replaced with spill registers.
8451 Because of this, we are, in some sense, just guessing the right approach
8452 here. The one listed above seems to work.
8453
8454 ??? At some point, this whole thing needs to be rethought. */
8455
8456 if (GET_CODE (in) == PLUS
8457 && (REG_P (XEXP (in, 0))
8458 || GET_CODE (XEXP (in, 0)) == SUBREG
8459 || MEM_P (XEXP (in, 0)))
8460 && (REG_P (XEXP (in, 1))
8461 || GET_CODE (XEXP (in, 1)) == SUBREG
8462 || CONSTANT_P (XEXP (in, 1))
8463 || MEM_P (XEXP (in, 1))))
8464 {
8465 /* We need to compute the sum of a register or a MEM and another
8466 register, constant, or MEM, and put it into the reload
8467 register. The best possible way of doing this is if the machine
8468 has a three-operand ADD insn that accepts the required operands.
8469
8470 The simplest approach is to try to generate such an insn and see if it
8471 is recognized and matches its constraints. If so, it can be used.
8472
8473 It might be better not to actually emit the insn unless it is valid,
8474 but we need to pass the insn as an operand to `recog' and
8475 `extract_insn' and it is simpler to emit and then delete the insn if
8476 not valid than to dummy things up. */
8477
8478 rtx op0, op1, tem;
8479 rtx_insn *insn;
8480 enum insn_code code;
8481
8482 op0 = find_replacement (&XEXP (in, 0));
8483 op1 = find_replacement (&XEXP (in, 1));
8484
8485 /* Since constraint checking is strict, commutativity won't be
8486 checked, so we need to do that here to avoid spurious failure
8487 if the add instruction is two-address and the second operand
8488 of the add is the same as the reload reg, which is frequently
8489 the case. If the insn would be A = B + A, rearrange it so
8490 it will be A = A + B as constrain_operands expects. */
8491
8492 if (REG_P (XEXP (in, 1))
8493 && REGNO (out) == REGNO (XEXP (in, 1)))
8494 tem = op0, op0 = op1, op1 = tem;
8495
8496 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
8497 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
8498
8499 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (out, in));
8500 if (insn)
8501 return insn;
8502
8503 /* If that failed, we must use a conservative two-insn sequence.
8504
8505 Use a move to copy one operand into the reload register. Prefer
8506 to reload a constant, MEM or pseudo since the move patterns can
8507 handle an arbitrary operand. If OP1 is not a constant, MEM or
8508 pseudo and OP1 is not a valid operand for an add instruction, then
8509 reload OP1.
8510
8511 After reloading one of the operands into the reload register, add
8512 the reload register to the output register.
8513
8514 If there is another way to do this for a specific machine, a
8515 DEFINE_PEEPHOLE should be specified that recognizes the sequence
8516 we emit below. */
8517
8518 code = optab_handler (add_optab, GET_MODE (out));
8519
8520 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
8521 || (REG_P (op1)
8522 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
8523 || (code != CODE_FOR_nothing
8524 && !insn_operand_matches (code, 2, op1)))
8525 tem = op0, op0 = op1, op1 = tem;
8526
8527 gen_reload (out, op0, opnum, type);
8528
8529 /* If OP0 and OP1 are the same, we can use OUT for OP1.
8530 This fixes a problem on the 32K where the stack pointer cannot
8531 be used as an operand of an add insn. */
8532
8533 if (rtx_equal_p (op0, op1))
8534 op1 = out;
8535
8536 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
8537 if (insn)
8538 {
8539 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8540 set_dst_reg_note (insn, REG_EQUIV, in, out);
8541 return insn;
8542 }
8543
8544 /* If that failed, copy the address register to the reload register.
8545 Then add the constant to the reload register. */
8546
8547 gcc_assert (!reg_overlap_mentioned_p (out, op0));
8548 gen_reload (out, op1, opnum, type);
8549 insn = emit_insn (gen_add2_insn (out, op0));
8550 set_dst_reg_note (insn, REG_EQUIV, in, out);
8551 }
8552
8553 /* If we need a memory location to do the move, do it that way. */
8554 else if ((tem1 = replaced_subreg (in), tem2 = replaced_subreg (out),
8555 (REG_P (tem1) && REG_P (tem2)))
8556 && REGNO (tem1) < FIRST_PSEUDO_REGISTER
8557 && REGNO (tem2) < FIRST_PSEUDO_REGISTER
8558 && targetm.secondary_memory_needed (GET_MODE (out),
8559 REGNO_REG_CLASS (REGNO (tem1)),
8560 REGNO_REG_CLASS (REGNO (tem2))))
8561 {
8562 /* Get the memory to use and rewrite both registers to its mode. */
8563 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
8564
8565 if (GET_MODE (loc) != GET_MODE (out))
8566 out = gen_rtx_REG (GET_MODE (loc), reg_or_subregno (out));
8567
8568 if (GET_MODE (loc) != GET_MODE (in))
8569 in = gen_rtx_REG (GET_MODE (loc), reg_or_subregno (in));
8570
8571 gen_reload (loc, in, opnum, type);
8572 gen_reload (out, loc, opnum, type);
8573 }
8574 else if (REG_P (out) && UNARY_P (in))
8575 {
8576 rtx op1;
8577 rtx out_moded;
8578 rtx_insn *set;
8579
8580 op1 = find_replacement (&XEXP (in, 0));
8581 if (op1 != XEXP (in, 0))
8582 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
8583
8584 /* First, try a plain SET. */
8585 set = emit_insn_if_valid_for_reload (gen_rtx_SET (out, in));
8586 if (set)
8587 return set;
8588
8589 /* If that failed, move the inner operand to the reload
8590 register, and try the same unop with the inner expression
8591 replaced with the reload register. */
8592
8593 if (GET_MODE (op1) != GET_MODE (out))
8594 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
8595 else
8596 out_moded = out;
8597
8598 gen_reload (out_moded, op1, opnum, type);
8599
8600 rtx temp = gen_rtx_SET (out, gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
8601 out_moded));
8602 rtx_insn *insn = emit_insn_if_valid_for_reload (temp);
8603 if (insn)
8604 {
8605 set_unique_reg_note (insn, REG_EQUIV, in);
8606 return insn;
8607 }
8608
8609 fatal_insn ("failure trying to reload:", set);
8610 }
8611 /* If IN is a simple operand, use gen_move_insn. */
8612 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
8613 {
8614 tem = emit_insn (gen_move_insn (out, in));
8615 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8616 mark_jump_label (in, tem, 0);
8617 }
8618
8619 else if (targetm.have_reload_load_address ())
8620 emit_insn (targetm.gen_reload_load_address (out, in));
8621
8622 /* Otherwise, just write (set OUT IN) and hope for the best. */
8623 else
8624 emit_insn (gen_rtx_SET (out, in));
8625
8626 /* Return the first insn emitted.
8627 We cannot just return get_last_insn, because there may have
8628 been multiple instructions emitted. Also note that gen_move_insn may
8629 emit more than one insn itself, so we cannot assume that there is one
8630 insn emitted per emit_insn_before call. */
8631
8632 return last ? NEXT_INSN (last) : get_insns ();
8633 }
8634
8635 /* Delete a previously made output-reload whose result we now believe
8636 is not needed. First we double-check.
8637
8638 INSN is the insn now being processed.
8639 LAST_RELOAD_REG is the hard register number for which we want to delete
8640 the last output reload.
8641 J is the reload-number that originally used REG. The caller has made
8642 certain that reload J doesn't use REG any longer for input.
8643 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8644
8645 static void
delete_output_reload(rtx_insn * insn,int j,int last_reload_reg,rtx new_reload_reg)8646 delete_output_reload (rtx_insn *insn, int j, int last_reload_reg,
8647 rtx new_reload_reg)
8648 {
8649 rtx_insn *output_reload_insn = spill_reg_store[last_reload_reg];
8650 rtx reg = spill_reg_stored_to[last_reload_reg];
8651 int k;
8652 int n_occurrences;
8653 int n_inherited = 0;
8654 rtx substed;
8655 unsigned regno;
8656 int nregs;
8657
8658 /* It is possible that this reload has been only used to set another reload
8659 we eliminated earlier and thus deleted this instruction too. */
8660 if (output_reload_insn->deleted ())
8661 return;
8662
8663 /* Get the raw pseudo-register referred to. */
8664
8665 while (GET_CODE (reg) == SUBREG)
8666 reg = SUBREG_REG (reg);
8667 substed = reg_equiv_memory_loc (REGNO (reg));
8668
8669 /* This is unsafe if the operand occurs more often in the current
8670 insn than it is inherited. */
8671 for (k = n_reloads - 1; k >= 0; k--)
8672 {
8673 rtx reg2 = rld[k].in;
8674 if (! reg2)
8675 continue;
8676 if (MEM_P (reg2) || reload_override_in[k])
8677 reg2 = rld[k].in_reg;
8678
8679 if (AUTO_INC_DEC && rld[k].out && ! rld[k].out_reg)
8680 reg2 = XEXP (rld[k].in_reg, 0);
8681
8682 while (GET_CODE (reg2) == SUBREG)
8683 reg2 = SUBREG_REG (reg2);
8684 if (rtx_equal_p (reg2, reg))
8685 {
8686 if (reload_inherited[k] || reload_override_in[k] || k == j)
8687 n_inherited++;
8688 else
8689 return;
8690 }
8691 }
8692 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8693 if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8694 n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8695 reg, 0);
8696 if (substed)
8697 n_occurrences += count_occurrences (PATTERN (insn),
8698 eliminate_regs (substed, VOIDmode,
8699 NULL_RTX), 0);
8700 for (rtx i1 = reg_equiv_alt_mem_list (REGNO (reg)); i1; i1 = XEXP (i1, 1))
8701 {
8702 gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8703 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8704 }
8705 if (n_occurrences > n_inherited)
8706 return;
8707
8708 regno = REGNO (reg);
8709 nregs = REG_NREGS (reg);
8710
8711 /* If the pseudo-reg we are reloading is no longer referenced
8712 anywhere between the store into it and here,
8713 and we're within the same basic block, then the value can only
8714 pass through the reload reg and end up here.
8715 Otherwise, give up--return. */
8716 for (rtx_insn *i1 = NEXT_INSN (output_reload_insn);
8717 i1 != insn; i1 = NEXT_INSN (i1))
8718 {
8719 if (NOTE_INSN_BASIC_BLOCK_P (i1))
8720 return;
8721 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8722 && refers_to_regno_p (regno, regno + nregs, PATTERN (i1), NULL))
8723 {
8724 /* If this is USE in front of INSN, we only have to check that
8725 there are no more references than accounted for by inheritance. */
8726 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8727 {
8728 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8729 i1 = NEXT_INSN (i1);
8730 }
8731 if (n_occurrences <= n_inherited && i1 == insn)
8732 break;
8733 return;
8734 }
8735 }
8736
8737 /* We will be deleting the insn. Remove the spill reg information. */
8738 for (k = hard_regno_nregs (last_reload_reg, GET_MODE (reg)); k-- > 0; )
8739 {
8740 spill_reg_store[last_reload_reg + k] = 0;
8741 spill_reg_stored_to[last_reload_reg + k] = 0;
8742 }
8743
8744 /* The caller has already checked that REG dies or is set in INSN.
8745 It has also checked that we are optimizing, and thus some
8746 inaccuracies in the debugging information are acceptable.
8747 So we could just delete output_reload_insn. But in some cases
8748 we can improve the debugging information without sacrificing
8749 optimization - maybe even improving the code: See if the pseudo
8750 reg has been completely replaced with reload regs. If so, delete
8751 the store insn and forget we had a stack slot for the pseudo. */
8752 if (rld[j].out != rld[j].in
8753 && REG_N_DEATHS (REGNO (reg)) == 1
8754 && REG_N_SETS (REGNO (reg)) == 1
8755 && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS
8756 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8757 {
8758 rtx_insn *i2;
8759
8760 /* We know that it was used only between here and the beginning of
8761 the current basic block. (We also know that the last use before
8762 INSN was the output reload we are thinking of deleting, but never
8763 mind that.) Search that range; see if any ref remains. */
8764 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8765 {
8766 rtx set = single_set (i2);
8767
8768 /* Uses which just store in the pseudo don't count,
8769 since if they are the only uses, they are dead. */
8770 if (set != 0 && SET_DEST (set) == reg)
8771 continue;
8772 if (LABEL_P (i2) || JUMP_P (i2))
8773 break;
8774 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8775 && reg_mentioned_p (reg, PATTERN (i2)))
8776 {
8777 /* Some other ref remains; just delete the output reload we
8778 know to be dead. */
8779 delete_address_reloads (output_reload_insn, insn);
8780 delete_insn (output_reload_insn);
8781 return;
8782 }
8783 }
8784
8785 /* Delete the now-dead stores into this pseudo. Note that this
8786 loop also takes care of deleting output_reload_insn. */
8787 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8788 {
8789 rtx set = single_set (i2);
8790
8791 if (set != 0 && SET_DEST (set) == reg)
8792 {
8793 delete_address_reloads (i2, insn);
8794 delete_insn (i2);
8795 }
8796 if (LABEL_P (i2) || JUMP_P (i2))
8797 break;
8798 }
8799
8800 /* For the debugging info, say the pseudo lives in this reload reg. */
8801 reg_renumber[REGNO (reg)] = REGNO (new_reload_reg);
8802 if (ira_conflicts_p)
8803 /* Inform IRA about the change. */
8804 ira_mark_allocation_change (REGNO (reg));
8805 alter_reg (REGNO (reg), -1, false);
8806 }
8807 else
8808 {
8809 delete_address_reloads (output_reload_insn, insn);
8810 delete_insn (output_reload_insn);
8811 }
8812 }
8813
8814 /* We are going to delete DEAD_INSN. Recursively delete loads of
8815 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8816 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8817 static void
delete_address_reloads(rtx_insn * dead_insn,rtx_insn * current_insn)8818 delete_address_reloads (rtx_insn *dead_insn, rtx_insn *current_insn)
8819 {
8820 rtx set = single_set (dead_insn);
8821 rtx set2, dst;
8822 rtx_insn *prev, *next;
8823 if (set)
8824 {
8825 rtx dst = SET_DEST (set);
8826 if (MEM_P (dst))
8827 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8828 }
8829 /* If we deleted the store from a reloaded post_{in,de}c expression,
8830 we can delete the matching adds. */
8831 prev = PREV_INSN (dead_insn);
8832 next = NEXT_INSN (dead_insn);
8833 if (! prev || ! next)
8834 return;
8835 set = single_set (next);
8836 set2 = single_set (prev);
8837 if (! set || ! set2
8838 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8839 || !CONST_INT_P (XEXP (SET_SRC (set), 1))
8840 || !CONST_INT_P (XEXP (SET_SRC (set2), 1)))
8841 return;
8842 dst = SET_DEST (set);
8843 if (! rtx_equal_p (dst, SET_DEST (set2))
8844 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8845 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8846 || (INTVAL (XEXP (SET_SRC (set), 1))
8847 != -INTVAL (XEXP (SET_SRC (set2), 1))))
8848 return;
8849 delete_related_insns (prev);
8850 delete_related_insns (next);
8851 }
8852
8853 /* Subfunction of delete_address_reloads: process registers found in X. */
8854 static void
delete_address_reloads_1(rtx_insn * dead_insn,rtx x,rtx_insn * current_insn)8855 delete_address_reloads_1 (rtx_insn *dead_insn, rtx x, rtx_insn *current_insn)
8856 {
8857 rtx_insn *prev, *i2;
8858 rtx set, dst;
8859 int i, j;
8860 enum rtx_code code = GET_CODE (x);
8861
8862 if (code != REG)
8863 {
8864 const char *fmt = GET_RTX_FORMAT (code);
8865 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8866 {
8867 if (fmt[i] == 'e')
8868 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8869 else if (fmt[i] == 'E')
8870 {
8871 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8872 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8873 current_insn);
8874 }
8875 }
8876 return;
8877 }
8878
8879 if (spill_reg_order[REGNO (x)] < 0)
8880 return;
8881
8882 /* Scan backwards for the insn that sets x. This might be a way back due
8883 to inheritance. */
8884 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8885 {
8886 code = GET_CODE (prev);
8887 if (code == CODE_LABEL || code == JUMP_INSN)
8888 return;
8889 if (!INSN_P (prev))
8890 continue;
8891 if (reg_set_p (x, PATTERN (prev)))
8892 break;
8893 if (reg_referenced_p (x, PATTERN (prev)))
8894 return;
8895 }
8896 if (! prev || INSN_UID (prev) < reload_first_uid)
8897 return;
8898 /* Check that PREV only sets the reload register. */
8899 set = single_set (prev);
8900 if (! set)
8901 return;
8902 dst = SET_DEST (set);
8903 if (!REG_P (dst)
8904 || ! rtx_equal_p (dst, x))
8905 return;
8906 if (! reg_set_p (dst, PATTERN (dead_insn)))
8907 {
8908 /* Check if DST was used in a later insn -
8909 it might have been inherited. */
8910 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8911 {
8912 if (LABEL_P (i2))
8913 break;
8914 if (! INSN_P (i2))
8915 continue;
8916 if (reg_referenced_p (dst, PATTERN (i2)))
8917 {
8918 /* If there is a reference to the register in the current insn,
8919 it might be loaded in a non-inherited reload. If no other
8920 reload uses it, that means the register is set before
8921 referenced. */
8922 if (i2 == current_insn)
8923 {
8924 for (j = n_reloads - 1; j >= 0; j--)
8925 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8926 || reload_override_in[j] == dst)
8927 return;
8928 for (j = n_reloads - 1; j >= 0; j--)
8929 if (rld[j].in && rld[j].reg_rtx == dst)
8930 break;
8931 if (j >= 0)
8932 break;
8933 }
8934 return;
8935 }
8936 if (JUMP_P (i2))
8937 break;
8938 /* If DST is still live at CURRENT_INSN, check if it is used for
8939 any reload. Note that even if CURRENT_INSN sets DST, we still
8940 have to check the reloads. */
8941 if (i2 == current_insn)
8942 {
8943 for (j = n_reloads - 1; j >= 0; j--)
8944 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8945 || reload_override_in[j] == dst)
8946 return;
8947 /* ??? We can't finish the loop here, because dst might be
8948 allocated to a pseudo in this block if no reload in this
8949 block needs any of the classes containing DST - see
8950 spill_hard_reg. There is no easy way to tell this, so we
8951 have to scan till the end of the basic block. */
8952 }
8953 if (reg_set_p (dst, PATTERN (i2)))
8954 break;
8955 }
8956 }
8957 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8958 reg_reloaded_contents[REGNO (dst)] = -1;
8959 delete_insn (prev);
8960 }
8961
8962 /* Output reload-insns to reload VALUE into RELOADREG.
8963 VALUE is an autoincrement or autodecrement RTX whose operand
8964 is a register or memory location;
8965 so reloading involves incrementing that location.
8966 IN is either identical to VALUE, or some cheaper place to reload from.
8967
8968 INC_AMOUNT is the number to increment or decrement by (always positive).
8969 This cannot be deduced from VALUE. */
8970
8971 static void
inc_for_reload(rtx reloadreg,rtx in,rtx value,poly_int64 inc_amount)8972 inc_for_reload (rtx reloadreg, rtx in, rtx value, poly_int64 inc_amount)
8973 {
8974 /* REG or MEM to be copied and incremented. */
8975 rtx incloc = find_replacement (&XEXP (value, 0));
8976 /* Nonzero if increment after copying. */
8977 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
8978 || GET_CODE (value) == POST_MODIFY);
8979 rtx_insn *last;
8980 rtx inc;
8981 rtx_insn *add_insn;
8982 int code;
8983 rtx real_in = in == value ? incloc : in;
8984
8985 /* No hard register is equivalent to this register after
8986 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
8987 we could inc/dec that register as well (maybe even using it for
8988 the source), but I'm not sure it's worth worrying about. */
8989 if (REG_P (incloc))
8990 reg_last_reload_reg[REGNO (incloc)] = 0;
8991
8992 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
8993 {
8994 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
8995 inc = find_replacement (&XEXP (XEXP (value, 1), 1));
8996 }
8997 else
8998 {
8999 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
9000 inc_amount = -inc_amount;
9001
9002 inc = gen_int_mode (inc_amount, Pmode);
9003 }
9004
9005 /* If this is post-increment, first copy the location to the reload reg. */
9006 if (post && real_in != reloadreg)
9007 emit_insn (gen_move_insn (reloadreg, real_in));
9008
9009 if (in == value)
9010 {
9011 /* See if we can directly increment INCLOC. Use a method similar to
9012 that in gen_reload. */
9013
9014 last = get_last_insn ();
9015 add_insn = emit_insn (gen_rtx_SET (incloc,
9016 gen_rtx_PLUS (GET_MODE (incloc),
9017 incloc, inc)));
9018
9019 code = recog_memoized (add_insn);
9020 if (code >= 0)
9021 {
9022 extract_insn (add_insn);
9023 if (constrain_operands (1, get_enabled_alternatives (add_insn)))
9024 {
9025 /* If this is a pre-increment and we have incremented the value
9026 where it lives, copy the incremented value to RELOADREG to
9027 be used as an address. */
9028
9029 if (! post)
9030 emit_insn (gen_move_insn (reloadreg, incloc));
9031 return;
9032 }
9033 }
9034 delete_insns_since (last);
9035 }
9036
9037 /* If couldn't do the increment directly, must increment in RELOADREG.
9038 The way we do this depends on whether this is pre- or post-increment.
9039 For pre-increment, copy INCLOC to the reload register, increment it
9040 there, then save back. */
9041
9042 if (! post)
9043 {
9044 if (in != reloadreg)
9045 emit_insn (gen_move_insn (reloadreg, real_in));
9046 emit_insn (gen_add2_insn (reloadreg, inc));
9047 emit_insn (gen_move_insn (incloc, reloadreg));
9048 }
9049 else
9050 {
9051 /* Postincrement.
9052 Because this might be a jump insn or a compare, and because RELOADREG
9053 may not be available after the insn in an input reload, we must do
9054 the incrementation before the insn being reloaded for.
9055
9056 We have already copied IN to RELOADREG. Increment the copy in
9057 RELOADREG, save that back, then decrement RELOADREG so it has
9058 the original value. */
9059
9060 emit_insn (gen_add2_insn (reloadreg, inc));
9061 emit_insn (gen_move_insn (incloc, reloadreg));
9062 if (CONST_INT_P (inc))
9063 emit_insn (gen_add2_insn (reloadreg,
9064 gen_int_mode (-INTVAL (inc),
9065 GET_MODE (reloadreg))));
9066 else
9067 emit_insn (gen_sub2_insn (reloadreg, inc));
9068 }
9069 }
9070