1 /*-
2 * Copyright (c) 1995, David Greenman
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD: stable/9/sys/dev/ed/if_ed.c 264943 2014-04-25 21:32:38Z marius $");
30
31 /*
32 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet
33 * adapters. By David Greenman, 29-April-1993
34 *
35 * Currently supports the Western Digital/SMC 8003 and 8013 series,
36 * the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000,
37 * and a variety of similar clones.
38 *
39 */
40
41 #include "opt_ed.h"
42
43 #include <sys/param.h>
44 #include <sys/systm.h>
45 #include <sys/sockio.h>
46 #include <sys/mbuf.h>
47 #include <sys/kernel.h>
48 #include <sys/socket.h>
49 #include <sys/sysctl.h>
50 #include <sys/syslog.h>
51
52 #include <sys/bus.h>
53
54 #include <machine/bus.h>
55 #include <sys/rman.h>
56 #include <machine/resource.h>
57
58 #include <net/ethernet.h>
59 #include <net/if.h>
60 #include <net/if_arp.h>
61 #include <net/if_dl.h>
62 #include <net/if_mib.h>
63 #include <net/if_media.h>
64 #include <net/if_types.h>
65
66 #include <net/bpf.h>
67
68 #include <dev/ed/if_edreg.h>
69 #include <dev/ed/if_edvar.h>
70 #include <sys/kdb.h>
71
72 devclass_t ed_devclass;
73
74 static void ed_init(void *);
75 static void ed_init_locked(struct ed_softc *);
76 static int ed_ioctl(struct ifnet *, u_long, caddr_t);
77 static void ed_start(struct ifnet *);
78 static void ed_start_locked(struct ifnet *);
79 static void ed_reset(struct ifnet *);
80 static void ed_tick(void *);
81 static void ed_watchdog(struct ed_softc *);
82
83 static void ed_ds_getmcaf(struct ed_softc *, uint32_t *);
84
85 static void ed_get_packet(struct ed_softc *, bus_size_t, u_short);
86 static void ed_stop_hw(struct ed_softc *sc);
87
88 static __inline void ed_rint(struct ed_softc *);
89 static __inline void ed_xmit(struct ed_softc *);
90 static __inline void ed_ring_copy(struct ed_softc *, bus_size_t, char *,
91 u_short);
92
93 static void ed_setrcr(struct ed_softc *);
94
95 /*
96 * Generic probe routine for testing for the existance of a DS8390.
97 * Must be called after the NIC has just been reset. This routine
98 * works by looking at certain register values that are guaranteed
99 * to be initialized a certain way after power-up or reset. Seems
100 * not to currently work on the 83C690.
101 *
102 * Specifically:
103 *
104 * Register reset bits set bits
105 * Command Register (CR) TXP, STA RD2, STP
106 * Interrupt Status (ISR) RST
107 * Interrupt Mask (IMR) All bits
108 * Data Control (DCR) LAS
109 * Transmit Config. (TCR) LB1, LB0
110 *
111 * We only look at the CR and ISR registers, however, because looking at
112 * the others would require changing register pages (which would be
113 * intrusive if this isn't an 8390).
114 *
115 * Return 1 if 8390 was found, 0 if not.
116 */
117
118 int
ed_probe_generic8390(struct ed_softc * sc)119 ed_probe_generic8390(struct ed_softc *sc)
120 {
121 if ((ed_nic_inb(sc, ED_P0_CR) &
122 (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) !=
123 (ED_CR_RD2 | ED_CR_STP))
124 return (0);
125 if ((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST)
126 return (0);
127
128 return (1);
129 }
130
131 void
ed_disable_16bit_access(struct ed_softc * sc)132 ed_disable_16bit_access(struct ed_softc *sc)
133 {
134 /*
135 * Disable 16 bit access to shared memory
136 */
137 if (sc->isa16bit && sc->vendor == ED_VENDOR_WD_SMC) {
138 if (sc->chip_type == ED_CHIP_TYPE_WD790)
139 ed_asic_outb(sc, ED_WD_MSR, 0x00);
140 ed_asic_outb(sc, ED_WD_LAAR,
141 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
142 }
143 }
144
145 void
ed_enable_16bit_access(struct ed_softc * sc)146 ed_enable_16bit_access(struct ed_softc *sc)
147 {
148 if (sc->isa16bit && sc->vendor == ED_VENDOR_WD_SMC) {
149 ed_asic_outb(sc, ED_WD_LAAR,
150 sc->wd_laar_proto | ED_WD_LAAR_M16EN);
151 if (sc->chip_type == ED_CHIP_TYPE_WD790)
152 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB);
153 }
154 }
155
156 /*
157 * Allocate a port resource with the given resource id.
158 */
159 int
ed_alloc_port(device_t dev,int rid,int size)160 ed_alloc_port(device_t dev, int rid, int size)
161 {
162 struct ed_softc *sc = device_get_softc(dev);
163 struct resource *res;
164
165 res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
166 0ul, ~0ul, size, RF_ACTIVE);
167 if (res) {
168 sc->port_res = res;
169 sc->port_used = size;
170 sc->port_bst = rman_get_bustag(res);
171 sc->port_bsh = rman_get_bushandle(res);
172 return (0);
173 }
174 return (ENOENT);
175 }
176
177 /*
178 * Allocate a memory resource with the given resource id.
179 */
180 int
ed_alloc_memory(device_t dev,int rid,int size)181 ed_alloc_memory(device_t dev, int rid, int size)
182 {
183 struct ed_softc *sc = device_get_softc(dev);
184 struct resource *res;
185
186 res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
187 0ul, ~0ul, size, RF_ACTIVE);
188 if (res) {
189 sc->mem_res = res;
190 sc->mem_used = size;
191 sc->mem_bst = rman_get_bustag(res);
192 sc->mem_bsh = rman_get_bushandle(res);
193 return (0);
194 }
195 return (ENOENT);
196 }
197
198 /*
199 * Allocate an irq resource with the given resource id.
200 */
201 int
ed_alloc_irq(device_t dev,int rid,int flags)202 ed_alloc_irq(device_t dev, int rid, int flags)
203 {
204 struct ed_softc *sc = device_get_softc(dev);
205 struct resource *res;
206
207 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE | flags);
208 if (res) {
209 sc->irq_res = res;
210 return (0);
211 }
212 return (ENOENT);
213 }
214
215 /*
216 * Release all resources
217 */
218 void
ed_release_resources(device_t dev)219 ed_release_resources(device_t dev)
220 {
221 struct ed_softc *sc = device_get_softc(dev);
222
223 if (sc->port_res)
224 bus_free_resource(dev, SYS_RES_IOPORT, sc->port_res);
225 if (sc->port_res2)
226 bus_free_resource(dev, SYS_RES_IOPORT, sc->port_res2);
227 if (sc->mem_res)
228 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res);
229 if (sc->irq_res)
230 bus_free_resource(dev, SYS_RES_IRQ, sc->irq_res);
231 sc->port_res = 0;
232 sc->port_res2 = 0;
233 sc->mem_res = 0;
234 sc->irq_res = 0;
235 if (sc->ifp)
236 if_free(sc->ifp);
237 }
238
239 /*
240 * Install interface into kernel networking data structures
241 */
242 int
ed_attach(device_t dev)243 ed_attach(device_t dev)
244 {
245 struct ed_softc *sc = device_get_softc(dev);
246 struct ifnet *ifp;
247
248 sc->dev = dev;
249 ED_LOCK_INIT(sc);
250 ifp = sc->ifp = if_alloc(IFT_ETHER);
251 if (ifp == NULL) {
252 device_printf(dev, "can not if_alloc()\n");
253 ED_LOCK_DESTROY(sc);
254 return (ENOSPC);
255 }
256
257 if (sc->readmem == NULL) {
258 if (sc->mem_shared) {
259 if (sc->isa16bit)
260 sc->readmem = ed_shmem_readmem16;
261 else
262 sc->readmem = ed_shmem_readmem8;
263 } else {
264 sc->readmem = ed_pio_readmem;
265 }
266 }
267 if (sc->sc_write_mbufs == NULL) {
268 device_printf(dev, "No write mbufs routine set\n");
269 return (ENXIO);
270 }
271
272 callout_init_mtx(&sc->tick_ch, ED_MUTEX(sc), 0);
273 /*
274 * Set interface to stopped condition (reset)
275 */
276 ed_stop_hw(sc);
277
278 /*
279 * Initialize ifnet structure
280 */
281 ifp->if_softc = sc;
282 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
283 ifp->if_start = ed_start;
284 ifp->if_ioctl = ed_ioctl;
285 ifp->if_init = ed_init;
286 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
287 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
288 IFQ_SET_READY(&ifp->if_snd);
289 ifp->if_linkmib = &sc->mibdata;
290 ifp->if_linkmiblen = sizeof sc->mibdata;
291 /*
292 * XXX - should do a better job.
293 */
294 if (sc->chip_type == ED_CHIP_TYPE_WD790)
295 sc->mibdata.dot3StatsEtherChipSet =
296 DOT3CHIPSET(dot3VendorWesternDigital,
297 dot3ChipSetWesternDigital83C790);
298 else
299 sc->mibdata.dot3StatsEtherChipSet =
300 DOT3CHIPSET(dot3VendorNational,
301 dot3ChipSetNational8390);
302 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS;
303
304 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
305 /*
306 * Set default state for LINK2 flag (used to disable the
307 * tranceiver for AUI operation), based on config option.
308 * We only set this flag before we attach the device, so there's
309 * no race. It is convenient to allow users to turn this off
310 * by default in the kernel config, but given our more advanced
311 * boot time configuration options, this might no longer be needed.
312 */
313 if (device_get_flags(dev) & ED_FLAGS_DISABLE_TRANCEIVER)
314 ifp->if_flags |= IFF_LINK2;
315
316 /*
317 * Attach the interface
318 */
319 ether_ifattach(ifp, sc->enaddr);
320 /* device attach does transition from UNCONFIGURED to IDLE state */
321
322 sc->tx_mem = sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE;
323 sc->rx_mem = (sc->rec_page_stop - sc->rec_page_start) * ED_PAGE_SIZE;
324 SYSCTL_ADD_STRING(device_get_sysctl_ctx(dev),
325 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
326 0, "type", CTLFLAG_RD, sc->type_str, 0,
327 "Type of chip in card");
328 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
329 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
330 1, "TxMem", CTLFLAG_RD, &sc->tx_mem, 0,
331 "Memory set aside for transmitting packets");
332 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
333 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
334 2, "RxMem", CTLFLAG_RD, &sc->rx_mem, 0,
335 "Memory set aside for receiving packets");
336 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
337 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
338 3, "Mem", CTLFLAG_RD, &sc->mem_size, 0,
339 "Total Card Memory");
340 if (bootverbose) {
341 if (sc->type_str && (*sc->type_str != 0))
342 device_printf(dev, "type %s ", sc->type_str);
343 else
344 device_printf(dev, "type unknown (0x%x) ", sc->type);
345
346 #ifdef ED_HPP
347 if (sc->vendor == ED_VENDOR_HP)
348 printf("(%s %s IO)",
349 (sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS) ?
350 "16-bit" : "32-bit",
351 sc->hpp_mem_start ? "memory mapped" : "regular");
352 else
353 #endif
354 printf("%s", sc->isa16bit ? "(16 bit)" : "(8 bit)");
355
356 #if defined(ED_HPP) || defined(ED_3C503)
357 printf("%s", (((sc->vendor == ED_VENDOR_3COM) ||
358 (sc->vendor == ED_VENDOR_HP)) &&
359 (ifp->if_flags & IFF_LINK2)) ?
360 " tranceiver disabled" : "");
361 #endif
362 printf("\n");
363 }
364 return (0);
365 }
366
367 /*
368 * Detach the driver from the hardware and other systems in the kernel.
369 */
370 int
ed_detach(device_t dev)371 ed_detach(device_t dev)
372 {
373 struct ed_softc *sc = device_get_softc(dev);
374 struct ifnet *ifp = sc->ifp;
375
376 if (mtx_initialized(ED_MUTEX(sc)))
377 ED_ASSERT_UNLOCKED(sc);
378 if (ifp) {
379 ED_LOCK(sc);
380 if (bus_child_present(dev))
381 ed_stop(sc);
382 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
383 ED_UNLOCK(sc);
384 ether_ifdetach(ifp);
385 callout_drain(&sc->tick_ch);
386 }
387 if (sc->irq_res != NULL && sc->irq_handle)
388 bus_teardown_intr(dev, sc->irq_res, sc->irq_handle);
389 ed_release_resources(dev);
390 if (sc->miibus)
391 device_delete_child(dev, sc->miibus);
392 if (mtx_initialized(ED_MUTEX(sc)))
393 ED_LOCK_DESTROY(sc);
394 bus_generic_detach(dev);
395 return (0);
396 }
397
398 /*
399 * Reset interface.
400 */
401 static void
ed_reset(struct ifnet * ifp)402 ed_reset(struct ifnet *ifp)
403 {
404 struct ed_softc *sc = ifp->if_softc;
405
406 ED_ASSERT_LOCKED(sc);
407 /*
408 * Stop interface and re-initialize.
409 */
410 ed_stop(sc);
411 ed_init_locked(sc);
412 }
413
414 static void
ed_stop_hw(struct ed_softc * sc)415 ed_stop_hw(struct ed_softc *sc)
416 {
417 int n = 5000;
418
419 /*
420 * Stop everything on the interface, and select page 0 registers.
421 */
422 ed_nic_barrier(sc, ED_P0_CR, 1,
423 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
424 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
425 ed_nic_barrier(sc, ED_P0_CR, 1,
426 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
427
428 /*
429 * Wait for interface to enter stopped state, but limit # of checks to
430 * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but
431 * just in case it's an old one.
432 *
433 * The AX88x90 chips don't seem to implement this behavor. The
434 * datasheets say it is only turned on when the chip enters a RESET
435 * state and is silent about behavior for the stopped state we just
436 * entered.
437 */
438 if (sc->chip_type == ED_CHIP_TYPE_AX88190 ||
439 sc->chip_type == ED_CHIP_TYPE_AX88790)
440 return;
441 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) == 0) && --n)
442 continue;
443 if (n <= 0)
444 device_printf(sc->dev, "ed_stop_hw RST never set\n");
445 }
446
447 /*
448 * Take interface offline.
449 */
450 void
ed_stop(struct ed_softc * sc)451 ed_stop(struct ed_softc *sc)
452 {
453 ED_ASSERT_LOCKED(sc);
454 callout_stop(&sc->tick_ch);
455 ed_stop_hw(sc);
456 }
457
458 /*
459 * Periodic timer used to drive the watchdog and attachment-specific
460 * tick handler.
461 */
462 static void
ed_tick(void * arg)463 ed_tick(void *arg)
464 {
465 struct ed_softc *sc;
466
467 sc = arg;
468 ED_ASSERT_LOCKED(sc);
469 if (sc->sc_tick)
470 sc->sc_tick(sc);
471 if (sc->tx_timer != 0 && --sc->tx_timer == 0)
472 ed_watchdog(sc);
473 callout_reset(&sc->tick_ch, hz, ed_tick, sc);
474 }
475
476 /*
477 * Device timeout/watchdog routine. Entered if the device neglects to
478 * generate an interrupt after a transmit has been started on it.
479 */
480 static void
ed_watchdog(struct ed_softc * sc)481 ed_watchdog(struct ed_softc *sc)
482 {
483 struct ifnet *ifp;
484
485 ifp = sc->ifp;
486 log(LOG_ERR, "%s: device timeout\n", ifp->if_xname);
487 ifp->if_oerrors++;
488
489 ed_reset(ifp);
490 }
491
492 /*
493 * Initialize device.
494 */
495 static void
ed_init(void * xsc)496 ed_init(void *xsc)
497 {
498 struct ed_softc *sc = xsc;
499
500 ED_ASSERT_UNLOCKED(sc);
501 ED_LOCK(sc);
502 ed_init_locked(sc);
503 ED_UNLOCK(sc);
504 }
505
506 static void
ed_init_locked(struct ed_softc * sc)507 ed_init_locked(struct ed_softc *sc)
508 {
509 struct ifnet *ifp = sc->ifp;
510 int i;
511
512 ED_ASSERT_LOCKED(sc);
513
514 /*
515 * Initialize the NIC in the exact order outlined in the NS manual.
516 * This init procedure is "mandatory"...don't change what or when
517 * things happen.
518 */
519
520 /* reset transmitter flags */
521 sc->xmit_busy = 0;
522 sc->tx_timer = 0;
523
524 sc->txb_inuse = 0;
525 sc->txb_new = 0;
526 sc->txb_next_tx = 0;
527
528 /* This variable is used below - don't move this assignment */
529 sc->next_packet = sc->rec_page_start + 1;
530
531 /*
532 * Set interface for page 0, Remote DMA complete, Stopped
533 */
534 ed_nic_barrier(sc, ED_P0_CR, 1,
535 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
536 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
537 ed_nic_barrier(sc, ED_P0_CR, 1,
538 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
539
540 if (sc->isa16bit)
541 /*
542 * Set FIFO threshold to 8, No auto-init Remote DMA, byte
543 * order=80x86, word-wide DMA xfers,
544 */
545 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS);
546 else
547 /*
548 * Same as above, but byte-wide DMA xfers
549 */
550 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
551
552 /*
553 * Clear Remote Byte Count Registers
554 */
555 ed_nic_outb(sc, ED_P0_RBCR0, 0);
556 ed_nic_outb(sc, ED_P0_RBCR1, 0);
557
558 /*
559 * For the moment, don't store incoming packets in memory.
560 */
561 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_MON);
562
563 /*
564 * Place NIC in internal loopback mode
565 */
566 ed_nic_outb(sc, ED_P0_TCR, ED_TCR_LB0);
567
568 /*
569 * Initialize transmit/receive (ring-buffer) Page Start
570 */
571 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start);
572 ed_nic_outb(sc, ED_P0_PSTART, sc->rec_page_start);
573 /* Set lower bits of byte addressable framing to 0 */
574 if (sc->chip_type == ED_CHIP_TYPE_WD790)
575 ed_nic_outb(sc, 0x09, 0);
576
577 /*
578 * Initialize Receiver (ring-buffer) Page Stop and Boundry
579 */
580 ed_nic_outb(sc, ED_P0_PSTOP, sc->rec_page_stop);
581 ed_nic_outb(sc, ED_P0_BNRY, sc->rec_page_start);
582
583 /*
584 * Clear all interrupts. A '1' in each bit position clears the
585 * corresponding flag.
586 */
587 ed_nic_outb(sc, ED_P0_ISR, 0xff);
588
589 /*
590 * Enable the following interrupts: receive/transmit complete,
591 * receive/transmit error, and Receiver OverWrite.
592 *
593 * Counter overflow and Remote DMA complete are *not* enabled.
594 */
595 ed_nic_outb(sc, ED_P0_IMR,
596 ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE);
597
598 /*
599 * Program Command Register for page 1
600 */
601 ed_nic_barrier(sc, ED_P0_CR, 1,
602 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
603 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
604 ed_nic_barrier(sc, ED_P0_CR, 1,
605 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
606
607 /*
608 * Copy out our station address
609 */
610 for (i = 0; i < ETHER_ADDR_LEN; ++i)
611 ed_nic_outb(sc, ED_P1_PAR(i), IF_LLADDR(sc->ifp)[i]);
612
613 /*
614 * Set Current Page pointer to next_packet (initialized above)
615 */
616 ed_nic_outb(sc, ED_P1_CURR, sc->next_packet);
617
618 /*
619 * Program Receiver Configuration Register and multicast filter. CR is
620 * set to page 0 on return.
621 */
622 ed_setrcr(sc);
623
624 /*
625 * Take interface out of loopback
626 */
627 ed_nic_outb(sc, ED_P0_TCR, 0);
628
629 if (sc->sc_mediachg)
630 sc->sc_mediachg(sc);
631
632 /*
633 * Set 'running' flag, and clear output active flag.
634 */
635 ifp->if_drv_flags |= IFF_DRV_RUNNING;
636 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
637
638 /*
639 * ...and attempt to start output
640 */
641 ed_start_locked(ifp);
642
643 callout_reset(&sc->tick_ch, hz, ed_tick, sc);
644 }
645
646 /*
647 * This routine actually starts the transmission on the interface
648 */
649 static __inline void
ed_xmit(struct ed_softc * sc)650 ed_xmit(struct ed_softc *sc)
651 {
652 unsigned short len;
653
654 len = sc->txb_len[sc->txb_next_tx];
655
656 /*
657 * Set NIC for page 0 register access
658 */
659 ed_nic_barrier(sc, ED_P0_CR, 1,
660 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
661 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
662 ed_nic_barrier(sc, ED_P0_CR, 1,
663 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
664
665 /*
666 * Set TX buffer start page
667 */
668 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start +
669 sc->txb_next_tx * ED_TXBUF_SIZE);
670
671 /*
672 * Set TX length
673 */
674 ed_nic_outb(sc, ED_P0_TBCR0, len);
675 ed_nic_outb(sc, ED_P0_TBCR1, len >> 8);
676
677 /*
678 * Set page 0, Remote DMA complete, Transmit Packet, and *Start*
679 */
680 ed_nic_barrier(sc, ED_P0_CR, 1,
681 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
682 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA);
683 ed_nic_barrier(sc, ED_P0_CR, 1,
684 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
685 sc->xmit_busy = 1;
686
687 /*
688 * Point to next transmit buffer slot and wrap if necessary.
689 */
690 sc->txb_next_tx++;
691 if (sc->txb_next_tx == sc->txb_cnt)
692 sc->txb_next_tx = 0;
693
694 /*
695 * Set a timer just in case we never hear from the board again
696 */
697 sc->tx_timer = 2;
698 }
699
700 /*
701 * Start output on interface.
702 * We make two assumptions here:
703 * 1) that the current priority is set to splimp _before_ this code
704 * is called *and* is returned to the appropriate priority after
705 * return
706 * 2) that the IFF_DRV_OACTIVE flag is checked before this code is called
707 * (i.e. that the output part of the interface is idle)
708 */
709 static void
ed_start(struct ifnet * ifp)710 ed_start(struct ifnet *ifp)
711 {
712 struct ed_softc *sc = ifp->if_softc;
713
714 ED_ASSERT_UNLOCKED(sc);
715 ED_LOCK(sc);
716 ed_start_locked(ifp);
717 ED_UNLOCK(sc);
718 }
719
720 static void
ed_start_locked(struct ifnet * ifp)721 ed_start_locked(struct ifnet *ifp)
722 {
723 struct ed_softc *sc = ifp->if_softc;
724 struct mbuf *m0, *m;
725 bus_size_t buffer;
726 int len;
727
728 ED_ASSERT_LOCKED(sc);
729 outloop:
730
731 /*
732 * First, see if there are buffered packets and an idle transmitter -
733 * should never happen at this point.
734 */
735 if (sc->txb_inuse && (sc->xmit_busy == 0)) {
736 printf("ed: packets buffered, but transmitter idle\n");
737 ed_xmit(sc);
738 }
739
740 /*
741 * See if there is room to put another packet in the buffer.
742 */
743 if (sc->txb_inuse == sc->txb_cnt) {
744
745 /*
746 * No room. Indicate this to the outside world and exit.
747 */
748 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
749 return;
750 }
751 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
752 if (m == 0) {
753
754 /*
755 * We are using the !OACTIVE flag to indicate to the outside
756 * world that we can accept an additional packet rather than
757 * that the transmitter is _actually_ active. Indeed, the
758 * transmitter may be active, but if we haven't filled all the
759 * buffers with data then we still want to accept more.
760 */
761 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
762 return;
763 }
764
765 /*
766 * Copy the mbuf chain into the transmit buffer
767 */
768 m0 = m;
769
770 /* txb_new points to next open buffer slot */
771 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE);
772
773 len = sc->sc_write_mbufs(sc, m, buffer);
774 if (len == 0) {
775 m_freem(m0);
776 goto outloop;
777 }
778
779 sc->txb_len[sc->txb_new] = max(len, (ETHER_MIN_LEN-ETHER_CRC_LEN));
780
781 sc->txb_inuse++;
782
783 /*
784 * Point to next buffer slot and wrap if necessary.
785 */
786 sc->txb_new++;
787 if (sc->txb_new == sc->txb_cnt)
788 sc->txb_new = 0;
789
790 if (sc->xmit_busy == 0)
791 ed_xmit(sc);
792
793 /*
794 * Tap off here if there is a bpf listener.
795 */
796 BPF_MTAP(ifp, m0);
797
798 m_freem(m0);
799
800 /*
801 * Loop back to the top to possibly buffer more packets
802 */
803 goto outloop;
804 }
805
806 /*
807 * Ethernet interface receiver interrupt.
808 */
809 static __inline void
ed_rint(struct ed_softc * sc)810 ed_rint(struct ed_softc *sc)
811 {
812 struct ifnet *ifp = sc->ifp;
813 u_char boundry;
814 u_short len;
815 struct ed_ring packet_hdr;
816 bus_size_t packet_ptr;
817
818 ED_ASSERT_LOCKED(sc);
819
820 /*
821 * Set NIC to page 1 registers to get 'current' pointer
822 */
823 ed_nic_barrier(sc, ED_P0_CR, 1,
824 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
825 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
826 ed_nic_barrier(sc, ED_P0_CR, 1,
827 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
828
829 /*
830 * 'sc->next_packet' is the logical beginning of the ring-buffer -
831 * i.e. it points to where new data has been buffered. The 'CURR'
832 * (current) register points to the logical end of the ring-buffer -
833 * i.e. it points to where additional new data will be added. We loop
834 * here until the logical beginning equals the logical end (or in
835 * other words, until the ring-buffer is empty).
836 */
837 while (sc->next_packet != ed_nic_inb(sc, ED_P1_CURR)) {
838
839 /* get pointer to this buffer's header structure */
840 packet_ptr = sc->mem_ring +
841 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE;
842
843 /*
844 * The byte count includes a 4 byte header that was added by
845 * the NIC.
846 */
847 sc->readmem(sc, packet_ptr, (char *) &packet_hdr,
848 sizeof(packet_hdr));
849 len = packet_hdr.count;
850 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring)) ||
851 len < (ETHER_MIN_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring))) {
852 /*
853 * Length is a wild value. There's a good chance that
854 * this was caused by the NIC being old and buggy.
855 * The bug is that the length low byte is duplicated
856 * in the high byte. Try to recalculate the length
857 * based on the pointer to the next packet. Also,
858 * need ot preserve offset into page.
859 *
860 * NOTE: sc->next_packet is pointing at the current
861 * packet.
862 */
863 len &= ED_PAGE_SIZE - 1;
864 if (packet_hdr.next_packet >= sc->next_packet)
865 len += (packet_hdr.next_packet -
866 sc->next_packet) * ED_PAGE_SIZE;
867 else
868 len +=
869 ((packet_hdr.next_packet - sc->rec_page_start) +
870 (sc->rec_page_stop - sc->next_packet)) * ED_PAGE_SIZE;
871 /*
872 * because buffers are aligned on 256-byte boundary,
873 * the length computed above is off by 256 in almost
874 * all cases. Fix it...
875 */
876 if (len & 0xff)
877 len -= 256;
878 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN
879 + sizeof(struct ed_ring)))
880 sc->mibdata.dot3StatsFrameTooLongs++;
881 }
882
883 /*
884 * Be fairly liberal about what we allow as a "reasonable"
885 * length so that a [crufty] packet will make it to BPF (and
886 * can thus be analyzed). Note that all that is really
887 * important is that we have a length that will fit into one
888 * mbuf cluster or less; the upper layer protocols can then
889 * figure out the length from their own length field(s). But
890 * make sure that we have at least a full ethernet header or
891 * we would be unable to call ether_input() later.
892 */
893 if ((len >= sizeof(struct ed_ring) + ETHER_HDR_LEN) &&
894 (len <= MCLBYTES) &&
895 (packet_hdr.next_packet >= sc->rec_page_start) &&
896 (packet_hdr.next_packet < sc->rec_page_stop)) {
897 /*
898 * Go get packet.
899 */
900 ed_get_packet(sc, packet_ptr + sizeof(struct ed_ring),
901 len - sizeof(struct ed_ring));
902 ifp->if_ipackets++;
903 } else {
904 /*
905 * Really BAD. The ring pointers are corrupted.
906 */
907 log(LOG_ERR,
908 "%s: NIC memory corrupt - invalid packet length %d\n",
909 ifp->if_xname, len);
910 ifp->if_ierrors++;
911 ed_reset(ifp);
912 return;
913 }
914
915 /*
916 * Update next packet pointer
917 */
918 sc->next_packet = packet_hdr.next_packet;
919
920 /*
921 * Update NIC boundry pointer - being careful to keep it one
922 * buffer behind. (as recommended by NS databook)
923 */
924 boundry = sc->next_packet - 1;
925 if (boundry < sc->rec_page_start)
926 boundry = sc->rec_page_stop - 1;
927
928 /*
929 * Set NIC to page 0 registers to update boundry register
930 */
931 ed_nic_barrier(sc, ED_P0_CR, 1,
932 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
933 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
934 ed_nic_barrier(sc, ED_P0_CR, 1,
935 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
936 ed_nic_outb(sc, ED_P0_BNRY, boundry);
937
938 /*
939 * Set NIC to page 1 registers before looping to top (prepare
940 * to get 'CURR' current pointer)
941 */
942 ed_nic_barrier(sc, ED_P0_CR, 1,
943 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
944 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
945 ed_nic_barrier(sc, ED_P0_CR, 1,
946 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
947 }
948 }
949
950 /*
951 * Ethernet interface interrupt processor
952 */
953 void
edintr(void * arg)954 edintr(void *arg)
955 {
956 struct ed_softc *sc = (struct ed_softc*) arg;
957 struct ifnet *ifp = sc->ifp;
958 u_char isr;
959 int count;
960
961 ED_LOCK(sc);
962 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
963 ED_UNLOCK(sc);
964 return;
965 }
966 /*
967 * Set NIC to page 0 registers
968 */
969 ed_nic_barrier(sc, ED_P0_CR, 1,
970 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
971 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
972 ed_nic_barrier(sc, ED_P0_CR, 1,
973 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
974
975 /*
976 * loop until there are no more new interrupts. When the card goes
977 * away, the hardware will read back 0xff. Looking at the interrupts,
978 * it would appear that 0xff is impossible, or at least extremely
979 * unlikely.
980 */
981 while ((isr = ed_nic_inb(sc, ED_P0_ISR)) != 0 && isr != 0xff) {
982
983 /*
984 * reset all the bits that we are 'acknowledging' by writing a
985 * '1' to each bit position that was set (writing a '1'
986 * *clears* the bit)
987 */
988 ed_nic_outb(sc, ED_P0_ISR, isr);
989
990 /*
991 * The AX88190 and AX88190A has problems acking an interrupt
992 * and having them clear. This interferes with top-level loop
993 * here. Wait for all the bits to clear.
994 *
995 * We limit this to 5000 iterations. At 1us per inb/outb,
996 * this translates to about 15ms, which should be plenty of
997 * time, and also gives protection in the card eject case.
998 */
999 if (sc->chip_type == ED_CHIP_TYPE_AX88190) {
1000 count = 5000; /* 15ms */
1001 while (count-- && (ed_nic_inb(sc, ED_P0_ISR) & isr)) {
1002 ed_nic_outb(sc, ED_P0_ISR,0);
1003 ed_nic_outb(sc, ED_P0_ISR,isr);
1004 }
1005 if (count == 0)
1006 break;
1007 }
1008
1009 /*
1010 * Handle transmitter interrupts. Handle these first because
1011 * the receiver will reset the board under some conditions.
1012 */
1013 if (isr & (ED_ISR_PTX | ED_ISR_TXE)) {
1014 u_char collisions = ed_nic_inb(sc, ED_P0_NCR) & 0x0f;
1015
1016 /*
1017 * Check for transmit error. If a TX completed with an
1018 * error, we end up throwing the packet away. Really
1019 * the only error that is possible is excessive
1020 * collisions, and in this case it is best to allow
1021 * the automatic mechanisms of TCP to backoff the
1022 * flow. Of course, with UDP we're screwed, but this
1023 * is expected when a network is heavily loaded.
1024 */
1025 (void) ed_nic_inb(sc, ED_P0_TSR);
1026 if (isr & ED_ISR_TXE) {
1027 u_char tsr;
1028
1029 /*
1030 * Excessive collisions (16)
1031 */
1032 tsr = ed_nic_inb(sc, ED_P0_TSR);
1033 if ((tsr & ED_TSR_ABT)
1034 && (collisions == 0)) {
1035
1036 /*
1037 * When collisions total 16, the
1038 * P0_NCR will indicate 0, and the
1039 * TSR_ABT is set.
1040 */
1041 collisions = 16;
1042 sc->mibdata.dot3StatsExcessiveCollisions++;
1043 sc->mibdata.dot3StatsCollFrequencies[15]++;
1044 }
1045 if (tsr & ED_TSR_OWC)
1046 sc->mibdata.dot3StatsLateCollisions++;
1047 if (tsr & ED_TSR_CDH)
1048 sc->mibdata.dot3StatsSQETestErrors++;
1049 if (tsr & ED_TSR_CRS)
1050 sc->mibdata.dot3StatsCarrierSenseErrors++;
1051 if (tsr & ED_TSR_FU)
1052 sc->mibdata.dot3StatsInternalMacTransmitErrors++;
1053
1054 /*
1055 * update output errors counter
1056 */
1057 ifp->if_oerrors++;
1058 } else {
1059
1060 /*
1061 * Update total number of successfully
1062 * transmitted packets.
1063 */
1064 ifp->if_opackets++;
1065 }
1066
1067 /*
1068 * reset tx busy and output active flags
1069 */
1070 sc->xmit_busy = 0;
1071 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1072
1073 /*
1074 * clear watchdog timer
1075 */
1076 sc->tx_timer = 0;
1077
1078 /*
1079 * Add in total number of collisions on last
1080 * transmission.
1081 */
1082 ifp->if_collisions += collisions;
1083 switch(collisions) {
1084 case 0:
1085 case 16:
1086 break;
1087 case 1:
1088 sc->mibdata.dot3StatsSingleCollisionFrames++;
1089 sc->mibdata.dot3StatsCollFrequencies[0]++;
1090 break;
1091 default:
1092 sc->mibdata.dot3StatsMultipleCollisionFrames++;
1093 sc->mibdata.
1094 dot3StatsCollFrequencies[collisions-1]
1095 ++;
1096 break;
1097 }
1098
1099 /*
1100 * Decrement buffer in-use count if not zero (can only
1101 * be zero if a transmitter interrupt occured while
1102 * not actually transmitting). If data is ready to
1103 * transmit, start it transmitting, otherwise defer
1104 * until after handling receiver
1105 */
1106 if (sc->txb_inuse && --sc->txb_inuse)
1107 ed_xmit(sc);
1108 }
1109
1110 /*
1111 * Handle receiver interrupts
1112 */
1113 if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) {
1114
1115 /*
1116 * Overwrite warning. In order to make sure that a
1117 * lockup of the local DMA hasn't occurred, we reset
1118 * and re-init the NIC. The NSC manual suggests only a
1119 * partial reset/re-init is necessary - but some chips
1120 * seem to want more. The DMA lockup has been seen
1121 * only with early rev chips - Methinks this bug was
1122 * fixed in later revs. -DG
1123 */
1124 if (isr & ED_ISR_OVW) {
1125 ifp->if_ierrors++;
1126 #ifdef DIAGNOSTIC
1127 log(LOG_WARNING,
1128 "%s: warning - receiver ring buffer overrun\n",
1129 ifp->if_xname);
1130 #endif
1131
1132 /*
1133 * Stop/reset/re-init NIC
1134 */
1135 ed_reset(ifp);
1136 } else {
1137
1138 /*
1139 * Receiver Error. One or more of: CRC error,
1140 * frame alignment error FIFO overrun, or
1141 * missed packet.
1142 */
1143 if (isr & ED_ISR_RXE) {
1144 u_char rsr;
1145 rsr = ed_nic_inb(sc, ED_P0_RSR);
1146 if (rsr & ED_RSR_CRC)
1147 sc->mibdata.dot3StatsFCSErrors++;
1148 if (rsr & ED_RSR_FAE)
1149 sc->mibdata.dot3StatsAlignmentErrors++;
1150 if (rsr & ED_RSR_FO)
1151 sc->mibdata.dot3StatsInternalMacReceiveErrors++;
1152 ifp->if_ierrors++;
1153 #ifdef ED_DEBUG
1154 if_printf(ifp, "receive error %x\n",
1155 ed_nic_inb(sc, ED_P0_RSR));
1156 #endif
1157 }
1158
1159 /*
1160 * Go get the packet(s) XXX - Doing this on an
1161 * error is dubious because there shouldn't be
1162 * any data to get (we've configured the
1163 * interface to not accept packets with
1164 * errors).
1165 */
1166
1167 /*
1168 * Enable 16bit access to shared memory first
1169 * on WD/SMC boards.
1170 */
1171 ed_enable_16bit_access(sc);
1172 ed_rint(sc);
1173 ed_disable_16bit_access(sc);
1174 }
1175 }
1176
1177 /*
1178 * If it looks like the transmitter can take more data,
1179 * attempt to start output on the interface. This is done
1180 * after handling the receiver to give the receiver priority.
1181 */
1182 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0)
1183 ed_start_locked(ifp);
1184
1185 /*
1186 * return NIC CR to standard state: page 0, remote DMA
1187 * complete, start (toggling the TXP bit off, even if was just
1188 * set in the transmit routine, is *okay* - it is 'edge'
1189 * triggered from low to high)
1190 */
1191 ed_nic_barrier(sc, ED_P0_CR, 1,
1192 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
1193 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
1194 ed_nic_barrier(sc, ED_P0_CR, 1,
1195 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
1196
1197 /*
1198 * If the Network Talley Counters overflow, read them to reset
1199 * them. It appears that old 8390's won't clear the ISR flag
1200 * otherwise - resulting in an infinite loop.
1201 */
1202 if (isr & ED_ISR_CNT) {
1203 (void) ed_nic_inb(sc, ED_P0_CNTR0);
1204 (void) ed_nic_inb(sc, ED_P0_CNTR1);
1205 (void) ed_nic_inb(sc, ED_P0_CNTR2);
1206 }
1207 }
1208 ED_UNLOCK(sc);
1209 }
1210
1211 /*
1212 * Process an ioctl request.
1213 */
1214 static int
ed_ioctl(struct ifnet * ifp,u_long command,caddr_t data)1215 ed_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1216 {
1217 struct ed_softc *sc = ifp->if_softc;
1218 struct ifreq *ifr = (struct ifreq *)data;
1219 int error = 0;
1220
1221 switch (command) {
1222 case SIOCSIFFLAGS:
1223 /*
1224 * If the interface is marked up and stopped, then start it.
1225 * If we're up and already running, then it may be a mediachg.
1226 * If it is marked down and running, then stop it.
1227 */
1228 ED_LOCK(sc);
1229 if (ifp->if_flags & IFF_UP) {
1230 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1231 ed_init_locked(sc);
1232 else if (sc->sc_mediachg)
1233 sc->sc_mediachg(sc);
1234 } else {
1235 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1236 ed_stop(sc);
1237 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1238 }
1239 }
1240
1241 /*
1242 * Promiscuous flag may have changed, so reprogram the RCR.
1243 */
1244 ed_setrcr(sc);
1245
1246 ED_UNLOCK(sc);
1247 break;
1248
1249 case SIOCADDMULTI:
1250 case SIOCDELMULTI:
1251 /*
1252 * Multicast list has changed; set the hardware filter
1253 * accordingly.
1254 */
1255 ED_LOCK(sc);
1256 ed_setrcr(sc);
1257 ED_UNLOCK(sc);
1258 error = 0;
1259 break;
1260
1261 case SIOCGIFMEDIA:
1262 case SIOCSIFMEDIA:
1263 if (sc->sc_media_ioctl == NULL) {
1264 error = EINVAL;
1265 break;
1266 }
1267 sc->sc_media_ioctl(sc, ifr, command);
1268 break;
1269
1270 default:
1271 error = ether_ioctl(ifp, command, data);
1272 break;
1273 }
1274 return (error);
1275 }
1276
1277 /*
1278 * Given a source and destination address, copy 'amount' of a packet from
1279 * the ring buffer into a linear destination buffer. Takes into account
1280 * ring-wrap.
1281 */
1282 static __inline void
ed_ring_copy(struct ed_softc * sc,bus_size_t src,char * dst,u_short amount)1283 ed_ring_copy(struct ed_softc *sc, bus_size_t src, char *dst, u_short amount)
1284 {
1285 u_short tmp_amount;
1286
1287 /* does copy wrap to lower addr in ring buffer? */
1288 if (src + amount > sc->mem_end) {
1289 tmp_amount = sc->mem_end - src;
1290 /* copy amount up to end of NIC memory */
1291 sc->readmem(sc, src, dst, tmp_amount);
1292 amount -= tmp_amount;
1293 src = sc->mem_ring;
1294 dst += tmp_amount;
1295 }
1296 sc->readmem(sc, src, dst, amount);
1297 }
1298
1299 /*
1300 * Retreive packet from shared memory and send to the next level up via
1301 * ether_input().
1302 */
1303 static void
ed_get_packet(struct ed_softc * sc,bus_size_t buf,u_short len)1304 ed_get_packet(struct ed_softc *sc, bus_size_t buf, u_short len)
1305 {
1306 struct ifnet *ifp = sc->ifp;
1307 struct ether_header *eh;
1308 struct mbuf *m;
1309
1310 /* Allocate a header mbuf */
1311 MGETHDR(m, M_NOWAIT, MT_DATA);
1312 if (m == NULL)
1313 return;
1314 m->m_pkthdr.rcvif = ifp;
1315 m->m_pkthdr.len = m->m_len = len;
1316
1317 /*
1318 * We always put the received packet in a single buffer -
1319 * either with just an mbuf header or in a cluster attached
1320 * to the header. The +2 is to compensate for the alignment
1321 * fixup below.
1322 */
1323 if ((len + 2) > MHLEN) {
1324 /* Attach an mbuf cluster */
1325 MCLGET(m, M_NOWAIT);
1326
1327 /* Insist on getting a cluster */
1328 if ((m->m_flags & M_EXT) == 0) {
1329 m_freem(m);
1330 return;
1331 }
1332 }
1333
1334 /*
1335 * The +2 is to longword align the start of the real packet.
1336 * This is important for NFS.
1337 */
1338 m->m_data += 2;
1339 eh = mtod(m, struct ether_header *);
1340
1341 /*
1342 * Get packet, including link layer address, from interface.
1343 */
1344 ed_ring_copy(sc, buf, (char *)eh, len);
1345
1346 m->m_pkthdr.len = m->m_len = len;
1347
1348 ED_UNLOCK(sc);
1349 (*ifp->if_input)(ifp, m);
1350 ED_LOCK(sc);
1351 }
1352
1353 /*
1354 * Supporting routines
1355 */
1356
1357 /*
1358 * Given a NIC memory source address and a host memory destination
1359 * address, copy 'amount' from NIC to host using shared memory.
1360 * The 'amount' is rounded up to a word - okay as long as mbufs
1361 * are word sized. That's what the +1 is below.
1362 * This routine accesses things as 16 bit quantities.
1363 */
1364 void
ed_shmem_readmem16(struct ed_softc * sc,bus_size_t src,uint8_t * dst,uint16_t amount)1365 ed_shmem_readmem16(struct ed_softc *sc, bus_size_t src, uint8_t *dst,
1366 uint16_t amount)
1367 {
1368 bus_space_read_region_2(sc->mem_bst, sc->mem_bsh, src, (uint16_t *)dst,
1369 (amount + 1) / 2);
1370 }
1371
1372 /*
1373 * Given a NIC memory source address and a host memory destination
1374 * address, copy 'amount' from NIC to host using shared memory.
1375 * This routine accesses things as 8 bit quantities.
1376 */
1377 void
ed_shmem_readmem8(struct ed_softc * sc,bus_size_t src,uint8_t * dst,uint16_t amount)1378 ed_shmem_readmem8(struct ed_softc *sc, bus_size_t src, uint8_t *dst,
1379 uint16_t amount)
1380 {
1381 bus_space_read_region_1(sc->mem_bst, sc->mem_bsh, src, dst, amount);
1382 }
1383
1384 /*
1385 * Given a NIC memory source address and a host memory destination
1386 * address, copy 'amount' from NIC to host using Programmed I/O.
1387 * The 'amount' is rounded up to a word - okay as long as mbufs
1388 * are word sized.
1389 * This routine is currently Novell-specific.
1390 */
1391 void
ed_pio_readmem(struct ed_softc * sc,bus_size_t src,uint8_t * dst,uint16_t amount)1392 ed_pio_readmem(struct ed_softc *sc, bus_size_t src, uint8_t *dst,
1393 uint16_t amount)
1394 {
1395 /* Regular Novell cards */
1396 /* select page 0 registers */
1397 ed_nic_barrier(sc, ED_P0_CR, 1,
1398 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
1399 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
1400 ed_nic_barrier(sc, ED_P0_CR, 1,
1401 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
1402
1403 /* round up to a word */
1404 if (amount & 1)
1405 ++amount;
1406
1407 /* set up DMA byte count */
1408 ed_nic_outb(sc, ED_P0_RBCR0, amount);
1409 ed_nic_outb(sc, ED_P0_RBCR1, amount >> 8);
1410
1411 /* set up source address in NIC mem */
1412 ed_nic_outb(sc, ED_P0_RSAR0, src);
1413 ed_nic_outb(sc, ED_P0_RSAR1, src >> 8);
1414
1415 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD0 | ED_CR_STA);
1416
1417 if (sc->isa16bit)
1418 ed_asic_insw(sc, ED_NOVELL_DATA, dst, amount / 2);
1419 else
1420 ed_asic_insb(sc, ED_NOVELL_DATA, dst, amount);
1421 }
1422
1423 /*
1424 * Stripped down routine for writing a linear buffer to NIC memory.
1425 * Only used in the probe routine to test the memory. 'len' must
1426 * be even.
1427 */
1428 void
ed_pio_writemem(struct ed_softc * sc,uint8_t * src,uint16_t dst,uint16_t len)1429 ed_pio_writemem(struct ed_softc *sc, uint8_t *src, uint16_t dst, uint16_t len)
1430 {
1431 int maxwait = 200; /* about 240us */
1432
1433 /* select page 0 registers */
1434 ed_nic_barrier(sc, ED_P0_CR, 1,
1435 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
1436 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
1437 ed_nic_barrier(sc, ED_P0_CR, 1,
1438 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
1439
1440 /* reset remote DMA complete flag */
1441 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
1442
1443 /* set up DMA byte count */
1444 ed_nic_outb(sc, ED_P0_RBCR0, len);
1445 ed_nic_outb(sc, ED_P0_RBCR1, len >> 8);
1446
1447 /* set up destination address in NIC mem */
1448 ed_nic_outb(sc, ED_P0_RSAR0, dst);
1449 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8);
1450
1451 /* set remote DMA write */
1452 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
1453
1454 if (sc->isa16bit)
1455 ed_asic_outsw(sc, ED_NOVELL_DATA, src, len / 2);
1456 else
1457 ed_asic_outsb(sc, ED_NOVELL_DATA, src, len);
1458
1459 /*
1460 * Wait for remote DMA complete. This is necessary because on the
1461 * transmit side, data is handled internally by the NIC in bursts and
1462 * we can't start another remote DMA until this one completes. Not
1463 * waiting causes really bad things to happen - like the NIC
1464 * irrecoverably jamming the ISA bus.
1465 */
1466 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) &&
1467 --maxwait)
1468 continue;
1469 }
1470
1471 /*
1472 * Write an mbuf chain to the destination NIC memory address using
1473 * programmed I/O.
1474 */
1475 u_short
ed_pio_write_mbufs(struct ed_softc * sc,struct mbuf * m,bus_size_t dst)1476 ed_pio_write_mbufs(struct ed_softc *sc, struct mbuf *m, bus_size_t dst)
1477 {
1478 struct ifnet *ifp = sc->ifp;
1479 unsigned short total_len, dma_len;
1480 struct mbuf *mp;
1481 int maxwait = 200; /* about 240us */
1482
1483 ED_ASSERT_LOCKED(sc);
1484
1485 /* Regular Novell cards */
1486 /* First, count up the total number of bytes to copy */
1487 for (total_len = 0, mp = m; mp; mp = mp->m_next)
1488 total_len += mp->m_len;
1489
1490 dma_len = total_len;
1491 if (sc->isa16bit && (dma_len & 1))
1492 dma_len++;
1493
1494 /* select page 0 registers */
1495 ed_nic_barrier(sc, ED_P0_CR, 1,
1496 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
1497 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
1498 ed_nic_barrier(sc, ED_P0_CR, 1,
1499 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
1500
1501 /* reset remote DMA complete flag */
1502 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
1503
1504 /* set up DMA byte count */
1505 ed_nic_outb(sc, ED_P0_RBCR0, dma_len);
1506 ed_nic_outb(sc, ED_P0_RBCR1, dma_len >> 8);
1507
1508 /* set up destination address in NIC mem */
1509 ed_nic_outb(sc, ED_P0_RSAR0, dst);
1510 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8);
1511
1512 /* set remote DMA write */
1513 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
1514
1515 /*
1516 * Transfer the mbuf chain to the NIC memory.
1517 * 16-bit cards require that data be transferred as words, and only words.
1518 * So that case requires some extra code to patch over odd-length mbufs.
1519 */
1520
1521 if (!sc->isa16bit) {
1522 /* NE1000s are easy */
1523 while (m) {
1524 if (m->m_len)
1525 ed_asic_outsb(sc, ED_NOVELL_DATA,
1526 m->m_data, m->m_len);
1527 m = m->m_next;
1528 }
1529 } else {
1530 /* NE2000s are a pain */
1531 uint8_t *data;
1532 int len, wantbyte;
1533 union {
1534 uint16_t w;
1535 uint8_t b[2];
1536 } saveword;
1537
1538 wantbyte = 0;
1539
1540 while (m) {
1541 len = m->m_len;
1542 if (len) {
1543 data = mtod(m, caddr_t);
1544 /* finish the last word */
1545 if (wantbyte) {
1546 saveword.b[1] = *data;
1547 ed_asic_outw(sc, ED_NOVELL_DATA,
1548 saveword.w);
1549 data++;
1550 len--;
1551 wantbyte = 0;
1552 }
1553 /* output contiguous words */
1554 if (len > 1) {
1555 ed_asic_outsw(sc, ED_NOVELL_DATA,
1556 data, len >> 1);
1557 data += len & ~1;
1558 len &= 1;
1559 }
1560 /* save last byte, if necessary */
1561 if (len == 1) {
1562 saveword.b[0] = *data;
1563 wantbyte = 1;
1564 }
1565 }
1566 m = m->m_next;
1567 }
1568 /* spit last byte */
1569 if (wantbyte)
1570 ed_asic_outw(sc, ED_NOVELL_DATA, saveword.w);
1571 }
1572
1573 /*
1574 * Wait for remote DMA complete. This is necessary because on the
1575 * transmit side, data is handled internally by the NIC in bursts and
1576 * we can't start another remote DMA until this one completes. Not
1577 * waiting causes really bad things to happen - like the NIC
1578 * irrecoverably jamming the ISA bus.
1579 */
1580 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) &&
1581 --maxwait)
1582 continue;
1583
1584 if (!maxwait) {
1585 log(LOG_WARNING, "%s: remote transmit DMA failed to complete\n",
1586 ifp->if_xname);
1587 ed_reset(ifp);
1588 return(0);
1589 }
1590 return (total_len);
1591 }
1592
1593 static void
ed_setrcr(struct ed_softc * sc)1594 ed_setrcr(struct ed_softc *sc)
1595 {
1596 struct ifnet *ifp = sc->ifp;
1597 int i;
1598 u_char reg1;
1599
1600 ED_ASSERT_LOCKED(sc);
1601
1602 /* Bit 6 in AX88190 RCR register must be set. */
1603 if (sc->chip_type == ED_CHIP_TYPE_AX88190 ||
1604 sc->chip_type == ED_CHIP_TYPE_AX88790)
1605 reg1 = ED_RCR_INTT;
1606 else
1607 reg1 = 0x00;
1608
1609 /* set page 1 registers */
1610 ed_nic_barrier(sc, ED_P0_CR, 1,
1611 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
1612 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
1613 ed_nic_barrier(sc, ED_P0_CR, 1,
1614 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
1615
1616 if (ifp->if_flags & IFF_PROMISC) {
1617
1618 /*
1619 * Reconfigure the multicast filter.
1620 */
1621 for (i = 0; i < 8; i++)
1622 ed_nic_outb(sc, ED_P1_MAR(i), 0xff);
1623
1624 /*
1625 * And turn on promiscuous mode. Also enable reception of
1626 * runts and packets with CRC & alignment errors.
1627 */
1628 /* Set page 0 registers */
1629 ed_nic_barrier(sc, ED_P0_CR, 1,
1630 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
1631 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
1632 ed_nic_barrier(sc, ED_P0_CR, 1,
1633 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
1634
1635 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_PRO | ED_RCR_AM |
1636 ED_RCR_AB | ED_RCR_AR | ED_RCR_SEP | reg1);
1637 } else {
1638 /* set up multicast addresses and filter modes */
1639 if (ifp->if_flags & IFF_MULTICAST) {
1640 uint32_t mcaf[2];
1641
1642 if (ifp->if_flags & IFF_ALLMULTI) {
1643 mcaf[0] = 0xffffffff;
1644 mcaf[1] = 0xffffffff;
1645 } else
1646 ed_ds_getmcaf(sc, mcaf);
1647
1648 /*
1649 * Set multicast filter on chip.
1650 */
1651 for (i = 0; i < 8; i++)
1652 ed_nic_outb(sc, ED_P1_MAR(i), ((u_char *) mcaf)[i]);
1653
1654 /* Set page 0 registers */
1655 ed_nic_barrier(sc, ED_P0_CR, 1,
1656 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
1657 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
1658 ed_nic_barrier(sc, ED_P0_CR, 1,
1659 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
1660
1661 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AM | ED_RCR_AB | reg1);
1662 } else {
1663
1664 /*
1665 * Initialize multicast address hashing registers to
1666 * not accept multicasts.
1667 */
1668 for (i = 0; i < 8; ++i)
1669 ed_nic_outb(sc, ED_P1_MAR(i), 0x00);
1670
1671 /* Set page 0 registers */
1672 ed_nic_barrier(sc, ED_P0_CR, 1,
1673 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
1674 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
1675
1676 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AB | reg1);
1677 }
1678 }
1679
1680 /*
1681 * Start interface.
1682 */
1683 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
1684 }
1685
1686 /*
1687 * Compute the multicast address filter from the
1688 * list of multicast addresses we need to listen to.
1689 */
1690 static void
ed_ds_getmcaf(struct ed_softc * sc,uint32_t * mcaf)1691 ed_ds_getmcaf(struct ed_softc *sc, uint32_t *mcaf)
1692 {
1693 uint32_t index;
1694 u_char *af = (u_char *) mcaf;
1695 struct ifmultiaddr *ifma;
1696
1697 mcaf[0] = 0;
1698 mcaf[1] = 0;
1699
1700 if_maddr_rlock(sc->ifp);
1701 TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) {
1702 if (ifma->ifma_addr->sa_family != AF_LINK)
1703 continue;
1704 index = ether_crc32_be(LLADDR((struct sockaddr_dl *)
1705 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
1706 af[index >> 3] |= 1 << (index & 7);
1707 }
1708 if_maddr_runlock(sc->ifp);
1709 }
1710
1711 int
ed_isa_mem_ok(device_t dev,u_long pmem,u_int memsize)1712 ed_isa_mem_ok(device_t dev, u_long pmem, u_int memsize)
1713 {
1714 if (pmem < 0xa0000 || pmem + memsize > 0x1000000) {
1715 device_printf(dev, "Invalid ISA memory address range "
1716 "configured: 0x%lx - 0x%lx\n", pmem, pmem + memsize);
1717 return (ENXIO);
1718 }
1719 return (0);
1720 }
1721
1722 int
ed_clear_memory(device_t dev)1723 ed_clear_memory(device_t dev)
1724 {
1725 struct ed_softc *sc = device_get_softc(dev);
1726 bus_size_t i;
1727
1728 bus_space_set_region_1(sc->mem_bst, sc->mem_bsh, sc->mem_start,
1729 0, sc->mem_size);
1730
1731 for (i = 0; i < sc->mem_size; i++) {
1732 if (bus_space_read_1(sc->mem_bst, sc->mem_bsh,
1733 sc->mem_start + i)) {
1734 device_printf(dev, "failed to clear shared memory at "
1735 "0x%jx - check configuration\n",
1736 (uintmax_t)rman_get_start(sc->mem_res) + i);
1737 return (ENXIO);
1738 }
1739 }
1740 return (0);
1741 }
1742
1743 u_short
ed_shmem_write_mbufs(struct ed_softc * sc,struct mbuf * m,bus_size_t dst)1744 ed_shmem_write_mbufs(struct ed_softc *sc, struct mbuf *m, bus_size_t dst)
1745 {
1746 u_short len;
1747
1748 /*
1749 * Special case setup for 16 bit boards...
1750 */
1751 if (sc->isa16bit) {
1752 switch (sc->vendor) {
1753 #ifdef ED_3C503
1754 /*
1755 * For 16bit 3Com boards (which have 16k of
1756 * memory), we have the xmit buffers in a
1757 * different page of memory ('page 0') - so
1758 * change pages.
1759 */
1760 case ED_VENDOR_3COM:
1761 ed_asic_outb(sc, ED_3COM_GACFR, ED_3COM_GACFR_RSEL);
1762 break;
1763 #endif
1764 /*
1765 * Enable 16bit access to shared memory on
1766 * WD/SMC boards.
1767 *
1768 * XXX - same as ed_enable_16bit_access()
1769 */
1770 case ED_VENDOR_WD_SMC:
1771 ed_asic_outb(sc, ED_WD_LAAR,
1772 sc->wd_laar_proto | ED_WD_LAAR_M16EN);
1773 if (sc->chip_type == ED_CHIP_TYPE_WD790)
1774 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB);
1775 break;
1776 }
1777 }
1778 for (len = 0; m != NULL; m = m->m_next) {
1779 if (m->m_len == 0)
1780 continue;
1781 if (sc->isa16bit) {
1782 if (m->m_len > 1)
1783 bus_space_write_region_2(sc->mem_bst,
1784 sc->mem_bsh, dst,
1785 mtod(m, uint16_t *), m->m_len / 2);
1786 if ((m->m_len & 1) != 0)
1787 bus_space_write_1(sc->mem_bst, sc->mem_bsh,
1788 dst + m->m_len - 1,
1789 *(mtod(m, uint8_t *) + m->m_len - 1));
1790 } else
1791 bus_space_write_region_1(sc->mem_bst,
1792 sc->mem_bsh, dst,
1793 mtod(m, uint8_t *), m->m_len);
1794 dst += m->m_len;
1795 len += m->m_len;
1796 }
1797
1798 /*
1799 * Restore previous shared memory access
1800 */
1801 if (sc->isa16bit) {
1802 switch (sc->vendor) {
1803 #ifdef ED_3C503
1804 case ED_VENDOR_3COM:
1805 ed_asic_outb(sc, ED_3COM_GACFR,
1806 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0);
1807 break;
1808 #endif
1809 case ED_VENDOR_WD_SMC:
1810 /* XXX - same as ed_disable_16bit_access() */
1811 if (sc->chip_type == ED_CHIP_TYPE_WD790)
1812 ed_asic_outb(sc, ED_WD_MSR, 0x00);
1813 ed_asic_outb(sc, ED_WD_LAAR,
1814 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
1815 break;
1816 }
1817 }
1818 return (len);
1819 }
1820
1821 /*
1822 * Generic ifmedia support. By default, the DP8390-based cards don't know
1823 * what their network attachment really is, or even if it is valid (except
1824 * upon successful transmission of a packet). To play nicer with dhclient, as
1825 * well as to fit in with a framework where some cards can provde more
1826 * detailed information, make sure that we use this as a fallback.
1827 */
1828 static int
ed_gen_ifmedia_ioctl(struct ed_softc * sc,struct ifreq * ifr,u_long command)1829 ed_gen_ifmedia_ioctl(struct ed_softc *sc, struct ifreq *ifr, u_long command)
1830 {
1831 return (ifmedia_ioctl(sc->ifp, ifr, &sc->ifmedia, command));
1832 }
1833
1834 static int
ed_gen_ifmedia_upd(struct ifnet * ifp)1835 ed_gen_ifmedia_upd(struct ifnet *ifp)
1836 {
1837 return 0;
1838 }
1839
1840 static void
ed_gen_ifmedia_sts(struct ifnet * ifp,struct ifmediareq * ifmr)1841 ed_gen_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1842 {
1843 ifmr->ifm_active = IFM_ETHER | IFM_AUTO;
1844 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE;
1845 }
1846
1847 void
ed_gen_ifmedia_init(struct ed_softc * sc)1848 ed_gen_ifmedia_init(struct ed_softc *sc)
1849 {
1850 sc->sc_media_ioctl = &ed_gen_ifmedia_ioctl;
1851 ifmedia_init(&sc->ifmedia, 0, ed_gen_ifmedia_upd, ed_gen_ifmedia_sts);
1852 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0, 0);
1853 ifmedia_set(&sc->ifmedia, IFM_ETHER | IFM_AUTO);
1854 }
1855