1 /*-
2 * Copyright (c) 1995, David Greenman
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
30
31 /*
32 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet
33 * adapters. By David Greenman, 29-April-1993
34 *
35 * Currently supports the Western Digital/SMC 8003 and 8013 series,
36 * the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000,
37 * and a variety of similar clones.
38 *
39 */
40
41 #include "opt_ed.h"
42
43 #include <sys/param.h>
44 #include <sys/systm.h>
45 #include <sys/sockio.h>
46 #include <sys/mbuf.h>
47 #include <sys/kernel.h>
48 #include <sys/socket.h>
49 #include <sys/sysctl.h>
50 #include <sys/syslog.h>
51
52 #include <sys/bus.h>
53
54 #include <machine/bus.h>
55 #include <sys/rman.h>
56 #include <machine/resource.h>
57
58 #include <net/ethernet.h>
59 #include <net/if.h>
60 #include <net/if_var.h>
61 #include <net/if_arp.h>
62 #include <net/if_dl.h>
63 #include <net/if_mib.h>
64 #include <net/if_media.h>
65 #include <net/if_types.h>
66
67 #include <net/bpf.h>
68
69 #include <dev/ed/if_edreg.h>
70 #include <dev/ed/if_edvar.h>
71 #include <sys/kdb.h>
72
73 devclass_t ed_devclass;
74
75 static void ed_init(void *);
76 static void ed_init_locked(struct ed_softc *);
77 static int ed_ioctl(struct ifnet *, u_long, caddr_t);
78 static void ed_start(struct ifnet *);
79 static void ed_start_locked(struct ifnet *);
80 static void ed_reset(struct ifnet *);
81 static void ed_tick(void *);
82 static void ed_watchdog(struct ed_softc *);
83
84 static void ed_ds_getmcaf(struct ed_softc *, uint32_t *);
85
86 static void ed_get_packet(struct ed_softc *, bus_size_t, u_short);
87 static void ed_stop_hw(struct ed_softc *sc);
88
89 static __inline void ed_rint(struct ed_softc *);
90 static __inline void ed_xmit(struct ed_softc *);
91 static __inline void ed_ring_copy(struct ed_softc *, bus_size_t, char *,
92 u_short);
93
94 static void ed_setrcr(struct ed_softc *);
95
96 /*
97 * Generic probe routine for testing for the existance of a DS8390.
98 * Must be called after the NIC has just been reset. This routine
99 * works by looking at certain register values that are guaranteed
100 * to be initialized a certain way after power-up or reset. Seems
101 * not to currently work on the 83C690.
102 *
103 * Specifically:
104 *
105 * Register reset bits set bits
106 * Command Register (CR) TXP, STA RD2, STP
107 * Interrupt Status (ISR) RST
108 * Interrupt Mask (IMR) All bits
109 * Data Control (DCR) LAS
110 * Transmit Config. (TCR) LB1, LB0
111 *
112 * We only look at the CR and ISR registers, however, because looking at
113 * the others would require changing register pages (which would be
114 * intrusive if this isn't an 8390).
115 *
116 * Return 1 if 8390 was found, 0 if not.
117 */
118
119 int
ed_probe_generic8390(struct ed_softc * sc)120 ed_probe_generic8390(struct ed_softc *sc)
121 {
122 if ((ed_nic_inb(sc, ED_P0_CR) &
123 (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) !=
124 (ED_CR_RD2 | ED_CR_STP))
125 return (0);
126 if ((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST)
127 return (0);
128
129 return (1);
130 }
131
132 void
ed_disable_16bit_access(struct ed_softc * sc)133 ed_disable_16bit_access(struct ed_softc *sc)
134 {
135 /*
136 * Disable 16 bit access to shared memory
137 */
138 if (sc->isa16bit && sc->vendor == ED_VENDOR_WD_SMC) {
139 if (sc->chip_type == ED_CHIP_TYPE_WD790)
140 ed_asic_outb(sc, ED_WD_MSR, 0x00);
141 ed_asic_outb(sc, ED_WD_LAAR,
142 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
143 }
144 }
145
146 void
ed_enable_16bit_access(struct ed_softc * sc)147 ed_enable_16bit_access(struct ed_softc *sc)
148 {
149 if (sc->isa16bit && sc->vendor == ED_VENDOR_WD_SMC) {
150 ed_asic_outb(sc, ED_WD_LAAR,
151 sc->wd_laar_proto | ED_WD_LAAR_M16EN);
152 if (sc->chip_type == ED_CHIP_TYPE_WD790)
153 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB);
154 }
155 }
156
157 /*
158 * Allocate a port resource with the given resource id.
159 */
160 int
ed_alloc_port(device_t dev,int rid,int size)161 ed_alloc_port(device_t dev, int rid, int size)
162 {
163 struct ed_softc *sc = device_get_softc(dev);
164 struct resource *res;
165
166 res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
167 0ul, ~0ul, size, RF_ACTIVE);
168 if (res) {
169 sc->port_res = res;
170 sc->port_used = size;
171 sc->port_bst = rman_get_bustag(res);
172 sc->port_bsh = rman_get_bushandle(res);
173 return (0);
174 }
175 return (ENOENT);
176 }
177
178 /*
179 * Allocate a memory resource with the given resource id.
180 */
181 int
ed_alloc_memory(device_t dev,int rid,int size)182 ed_alloc_memory(device_t dev, int rid, int size)
183 {
184 struct ed_softc *sc = device_get_softc(dev);
185 struct resource *res;
186
187 res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
188 0ul, ~0ul, size, RF_ACTIVE);
189 if (res) {
190 sc->mem_res = res;
191 sc->mem_used = size;
192 sc->mem_bst = rman_get_bustag(res);
193 sc->mem_bsh = rman_get_bushandle(res);
194 return (0);
195 }
196 return (ENOENT);
197 }
198
199 /*
200 * Allocate an irq resource with the given resource id.
201 */
202 int
ed_alloc_irq(device_t dev,int rid,int flags)203 ed_alloc_irq(device_t dev, int rid, int flags)
204 {
205 struct ed_softc *sc = device_get_softc(dev);
206 struct resource *res;
207
208 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE | flags);
209 if (res) {
210 sc->irq_res = res;
211 return (0);
212 }
213 return (ENOENT);
214 }
215
216 /*
217 * Release all resources
218 */
219 void
ed_release_resources(device_t dev)220 ed_release_resources(device_t dev)
221 {
222 struct ed_softc *sc = device_get_softc(dev);
223
224 if (sc->port_res)
225 bus_free_resource(dev, SYS_RES_IOPORT, sc->port_res);
226 if (sc->port_res2)
227 bus_free_resource(dev, SYS_RES_IOPORT, sc->port_res2);
228 if (sc->mem_res)
229 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res);
230 if (sc->irq_res)
231 bus_free_resource(dev, SYS_RES_IRQ, sc->irq_res);
232 sc->port_res = 0;
233 sc->port_res2 = 0;
234 sc->mem_res = 0;
235 sc->irq_res = 0;
236 if (sc->ifp)
237 if_free(sc->ifp);
238 }
239
240 /*
241 * Install interface into kernel networking data structures
242 */
243 int
ed_attach(device_t dev)244 ed_attach(device_t dev)
245 {
246 struct ed_softc *sc = device_get_softc(dev);
247 struct ifnet *ifp;
248
249 sc->dev = dev;
250 ED_LOCK_INIT(sc);
251 ifp = sc->ifp = if_alloc(IFT_ETHER);
252 if (ifp == NULL) {
253 device_printf(dev, "can not if_alloc()\n");
254 ED_LOCK_DESTROY(sc);
255 return (ENOSPC);
256 }
257
258 if (sc->readmem == NULL) {
259 if (sc->mem_shared) {
260 if (sc->isa16bit)
261 sc->readmem = ed_shmem_readmem16;
262 else
263 sc->readmem = ed_shmem_readmem8;
264 } else {
265 sc->readmem = ed_pio_readmem;
266 }
267 }
268 if (sc->sc_write_mbufs == NULL) {
269 device_printf(dev, "No write mbufs routine set\n");
270 return (ENXIO);
271 }
272
273 callout_init_mtx(&sc->tick_ch, ED_MUTEX(sc), 0);
274 /*
275 * Set interface to stopped condition (reset)
276 */
277 ed_stop_hw(sc);
278
279 /*
280 * Initialize ifnet structure
281 */
282 ifp->if_softc = sc;
283 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
284 ifp->if_start = ed_start;
285 ifp->if_ioctl = ed_ioctl;
286 ifp->if_init = ed_init;
287 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
288 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
289 IFQ_SET_READY(&ifp->if_snd);
290 ifp->if_linkmib = &sc->mibdata;
291 ifp->if_linkmiblen = sizeof sc->mibdata;
292 /*
293 * XXX - should do a better job.
294 */
295 if (sc->chip_type == ED_CHIP_TYPE_WD790)
296 sc->mibdata.dot3StatsEtherChipSet =
297 DOT3CHIPSET(dot3VendorWesternDigital,
298 dot3ChipSetWesternDigital83C790);
299 else
300 sc->mibdata.dot3StatsEtherChipSet =
301 DOT3CHIPSET(dot3VendorNational,
302 dot3ChipSetNational8390);
303 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS;
304
305 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
306 /*
307 * Set default state for LINK2 flag (used to disable the
308 * tranceiver for AUI operation), based on config option.
309 * We only set this flag before we attach the device, so there's
310 * no race. It is convenient to allow users to turn this off
311 * by default in the kernel config, but given our more advanced
312 * boot time configuration options, this might no longer be needed.
313 */
314 if (device_get_flags(dev) & ED_FLAGS_DISABLE_TRANCEIVER)
315 ifp->if_flags |= IFF_LINK2;
316
317 /*
318 * Attach the interface
319 */
320 ether_ifattach(ifp, sc->enaddr);
321 /* device attach does transition from UNCONFIGURED to IDLE state */
322
323 sc->tx_mem = sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE;
324 sc->rx_mem = (sc->rec_page_stop - sc->rec_page_start) * ED_PAGE_SIZE;
325 SYSCTL_ADD_STRING(device_get_sysctl_ctx(dev),
326 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
327 0, "type", CTLFLAG_RD, sc->type_str, 0,
328 "Type of chip in card");
329 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
330 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
331 1, "TxMem", CTLFLAG_RD, &sc->tx_mem, 0,
332 "Memory set aside for transmitting packets");
333 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
334 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
335 2, "RxMem", CTLFLAG_RD, &sc->rx_mem, 0,
336 "Memory set aside for receiving packets");
337 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
338 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
339 3, "Mem", CTLFLAG_RD, &sc->mem_size, 0,
340 "Total Card Memory");
341 if (bootverbose) {
342 if (sc->type_str && (*sc->type_str != 0))
343 device_printf(dev, "type %s ", sc->type_str);
344 else
345 device_printf(dev, "type unknown (0x%x) ", sc->type);
346
347 #ifdef ED_HPP
348 if (sc->vendor == ED_VENDOR_HP)
349 printf("(%s %s IO)",
350 (sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS) ?
351 "16-bit" : "32-bit",
352 sc->hpp_mem_start ? "memory mapped" : "regular");
353 else
354 #endif
355 printf("%s", sc->isa16bit ? "(16 bit)" : "(8 bit)");
356
357 #if defined(ED_HPP) || defined(ED_3C503)
358 printf("%s", (((sc->vendor == ED_VENDOR_3COM) ||
359 (sc->vendor == ED_VENDOR_HP)) &&
360 (ifp->if_flags & IFF_LINK2)) ?
361 " tranceiver disabled" : "");
362 #endif
363 printf("\n");
364 }
365 return (0);
366 }
367
368 /*
369 * Detach the driver from the hardware and other systems in the kernel.
370 */
371 int
ed_detach(device_t dev)372 ed_detach(device_t dev)
373 {
374 struct ed_softc *sc = device_get_softc(dev);
375 struct ifnet *ifp = sc->ifp;
376
377 if (mtx_initialized(ED_MUTEX(sc)))
378 ED_ASSERT_UNLOCKED(sc);
379 if (ifp) {
380 ED_LOCK(sc);
381 if (bus_child_present(dev))
382 ed_stop(sc);
383 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
384 ED_UNLOCK(sc);
385 ether_ifdetach(ifp);
386 callout_drain(&sc->tick_ch);
387 }
388 if (sc->irq_res != NULL && sc->irq_handle)
389 bus_teardown_intr(dev, sc->irq_res, sc->irq_handle);
390 ed_release_resources(dev);
391 if (sc->miibus)
392 device_delete_child(dev, sc->miibus);
393 if (mtx_initialized(ED_MUTEX(sc)))
394 ED_LOCK_DESTROY(sc);
395 bus_generic_detach(dev);
396 return (0);
397 }
398
399 /*
400 * Reset interface.
401 */
402 static void
ed_reset(struct ifnet * ifp)403 ed_reset(struct ifnet *ifp)
404 {
405 struct ed_softc *sc = ifp->if_softc;
406
407 ED_ASSERT_LOCKED(sc);
408 /*
409 * Stop interface and re-initialize.
410 */
411 ed_stop(sc);
412 ed_init_locked(sc);
413 }
414
415 static void
ed_stop_hw(struct ed_softc * sc)416 ed_stop_hw(struct ed_softc *sc)
417 {
418 int n = 5000;
419
420 /*
421 * Stop everything on the interface, and select page 0 registers.
422 */
423 ed_nic_barrier(sc, ED_P0_CR, 1,
424 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
425 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
426 ed_nic_barrier(sc, ED_P0_CR, 1,
427 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
428
429 /*
430 * Wait for interface to enter stopped state, but limit # of checks to
431 * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but
432 * just in case it's an old one.
433 *
434 * The AX88x90 chips don't seem to implement this behavor. The
435 * datasheets say it is only turned on when the chip enters a RESET
436 * state and is silent about behavior for the stopped state we just
437 * entered.
438 */
439 if (sc->chip_type == ED_CHIP_TYPE_AX88190 ||
440 sc->chip_type == ED_CHIP_TYPE_AX88790)
441 return;
442 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) == 0) && --n)
443 continue;
444 if (n <= 0)
445 device_printf(sc->dev, "ed_stop_hw RST never set\n");
446 }
447
448 /*
449 * Take interface offline.
450 */
451 void
ed_stop(struct ed_softc * sc)452 ed_stop(struct ed_softc *sc)
453 {
454 ED_ASSERT_LOCKED(sc);
455 callout_stop(&sc->tick_ch);
456 ed_stop_hw(sc);
457 }
458
459 /*
460 * Periodic timer used to drive the watchdog and attachment-specific
461 * tick handler.
462 */
463 static void
ed_tick(void * arg)464 ed_tick(void *arg)
465 {
466 struct ed_softc *sc;
467
468 sc = arg;
469 ED_ASSERT_LOCKED(sc);
470 if (sc->sc_tick)
471 sc->sc_tick(sc);
472 if (sc->tx_timer != 0 && --sc->tx_timer == 0)
473 ed_watchdog(sc);
474 callout_reset(&sc->tick_ch, hz, ed_tick, sc);
475 }
476
477 /*
478 * Device timeout/watchdog routine. Entered if the device neglects to
479 * generate an interrupt after a transmit has been started on it.
480 */
481 static void
ed_watchdog(struct ed_softc * sc)482 ed_watchdog(struct ed_softc *sc)
483 {
484 struct ifnet *ifp;
485
486 ifp = sc->ifp;
487 log(LOG_ERR, "%s: device timeout\n", ifp->if_xname);
488 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
489
490 ed_reset(ifp);
491 }
492
493 /*
494 * Initialize device.
495 */
496 static void
ed_init(void * xsc)497 ed_init(void *xsc)
498 {
499 struct ed_softc *sc = xsc;
500
501 ED_ASSERT_UNLOCKED(sc);
502 ED_LOCK(sc);
503 ed_init_locked(sc);
504 ED_UNLOCK(sc);
505 }
506
507 static void
ed_init_locked(struct ed_softc * sc)508 ed_init_locked(struct ed_softc *sc)
509 {
510 struct ifnet *ifp = sc->ifp;
511 int i;
512
513 ED_ASSERT_LOCKED(sc);
514
515 /*
516 * Initialize the NIC in the exact order outlined in the NS manual.
517 * This init procedure is "mandatory"...don't change what or when
518 * things happen.
519 */
520
521 /* reset transmitter flags */
522 sc->xmit_busy = 0;
523 sc->tx_timer = 0;
524
525 sc->txb_inuse = 0;
526 sc->txb_new = 0;
527 sc->txb_next_tx = 0;
528
529 /* This variable is used below - don't move this assignment */
530 sc->next_packet = sc->rec_page_start + 1;
531
532 /*
533 * Set interface for page 0, Remote DMA complete, Stopped
534 */
535 ed_nic_barrier(sc, ED_P0_CR, 1,
536 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
537 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
538 ed_nic_barrier(sc, ED_P0_CR, 1,
539 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
540
541 if (sc->isa16bit)
542 /*
543 * Set FIFO threshold to 8, No auto-init Remote DMA, byte
544 * order=80x86, word-wide DMA xfers,
545 */
546 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS);
547 else
548 /*
549 * Same as above, but byte-wide DMA xfers
550 */
551 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
552
553 /*
554 * Clear Remote Byte Count Registers
555 */
556 ed_nic_outb(sc, ED_P0_RBCR0, 0);
557 ed_nic_outb(sc, ED_P0_RBCR1, 0);
558
559 /*
560 * For the moment, don't store incoming packets in memory.
561 */
562 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_MON);
563
564 /*
565 * Place NIC in internal loopback mode
566 */
567 ed_nic_outb(sc, ED_P0_TCR, ED_TCR_LB0);
568
569 /*
570 * Initialize transmit/receive (ring-buffer) Page Start
571 */
572 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start);
573 ed_nic_outb(sc, ED_P0_PSTART, sc->rec_page_start);
574 /* Set lower bits of byte addressable framing to 0 */
575 if (sc->chip_type == ED_CHIP_TYPE_WD790)
576 ed_nic_outb(sc, 0x09, 0);
577
578 /*
579 * Initialize Receiver (ring-buffer) Page Stop and Boundry
580 */
581 ed_nic_outb(sc, ED_P0_PSTOP, sc->rec_page_stop);
582 ed_nic_outb(sc, ED_P0_BNRY, sc->rec_page_start);
583
584 /*
585 * Clear all interrupts. A '1' in each bit position clears the
586 * corresponding flag.
587 */
588 ed_nic_outb(sc, ED_P0_ISR, 0xff);
589
590 /*
591 * Enable the following interrupts: receive/transmit complete,
592 * receive/transmit error, and Receiver OverWrite.
593 *
594 * Counter overflow and Remote DMA complete are *not* enabled.
595 */
596 ed_nic_outb(sc, ED_P0_IMR,
597 ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE);
598
599 /*
600 * Program Command Register for page 1
601 */
602 ed_nic_barrier(sc, ED_P0_CR, 1,
603 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
604 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
605 ed_nic_barrier(sc, ED_P0_CR, 1,
606 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
607
608 /*
609 * Copy out our station address
610 */
611 for (i = 0; i < ETHER_ADDR_LEN; ++i)
612 ed_nic_outb(sc, ED_P1_PAR(i), IF_LLADDR(sc->ifp)[i]);
613
614 /*
615 * Set Current Page pointer to next_packet (initialized above)
616 */
617 ed_nic_outb(sc, ED_P1_CURR, sc->next_packet);
618
619 /*
620 * Program Receiver Configuration Register and multicast filter. CR is
621 * set to page 0 on return.
622 */
623 ed_setrcr(sc);
624
625 /*
626 * Take interface out of loopback
627 */
628 ed_nic_outb(sc, ED_P0_TCR, 0);
629
630 if (sc->sc_mediachg)
631 sc->sc_mediachg(sc);
632
633 /*
634 * Set 'running' flag, and clear output active flag.
635 */
636 ifp->if_drv_flags |= IFF_DRV_RUNNING;
637 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
638
639 /*
640 * ...and attempt to start output
641 */
642 ed_start_locked(ifp);
643
644 callout_reset(&sc->tick_ch, hz, ed_tick, sc);
645 }
646
647 /*
648 * This routine actually starts the transmission on the interface
649 */
650 static __inline void
ed_xmit(struct ed_softc * sc)651 ed_xmit(struct ed_softc *sc)
652 {
653 unsigned short len;
654
655 len = sc->txb_len[sc->txb_next_tx];
656
657 /*
658 * Set NIC for page 0 register access
659 */
660 ed_nic_barrier(sc, ED_P0_CR, 1,
661 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
662 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
663 ed_nic_barrier(sc, ED_P0_CR, 1,
664 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
665
666 /*
667 * Set TX buffer start page
668 */
669 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start +
670 sc->txb_next_tx * ED_TXBUF_SIZE);
671
672 /*
673 * Set TX length
674 */
675 ed_nic_outb(sc, ED_P0_TBCR0, len);
676 ed_nic_outb(sc, ED_P0_TBCR1, len >> 8);
677
678 /*
679 * Set page 0, Remote DMA complete, Transmit Packet, and *Start*
680 */
681 ed_nic_barrier(sc, ED_P0_CR, 1,
682 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
683 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA);
684 ed_nic_barrier(sc, ED_P0_CR, 1,
685 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
686 sc->xmit_busy = 1;
687
688 /*
689 * Point to next transmit buffer slot and wrap if necessary.
690 */
691 sc->txb_next_tx++;
692 if (sc->txb_next_tx == sc->txb_cnt)
693 sc->txb_next_tx = 0;
694
695 /*
696 * Set a timer just in case we never hear from the board again
697 */
698 sc->tx_timer = 2;
699 }
700
701 /*
702 * Start output on interface.
703 * We make two assumptions here:
704 * 1) that the current priority is set to splimp _before_ this code
705 * is called *and* is returned to the appropriate priority after
706 * return
707 * 2) that the IFF_DRV_OACTIVE flag is checked before this code is called
708 * (i.e. that the output part of the interface is idle)
709 */
710 static void
ed_start(struct ifnet * ifp)711 ed_start(struct ifnet *ifp)
712 {
713 struct ed_softc *sc = ifp->if_softc;
714
715 ED_ASSERT_UNLOCKED(sc);
716 ED_LOCK(sc);
717 ed_start_locked(ifp);
718 ED_UNLOCK(sc);
719 }
720
721 static void
ed_start_locked(struct ifnet * ifp)722 ed_start_locked(struct ifnet *ifp)
723 {
724 struct ed_softc *sc = ifp->if_softc;
725 struct mbuf *m0, *m;
726 bus_size_t buffer;
727 int len;
728
729 ED_ASSERT_LOCKED(sc);
730 outloop:
731
732 /*
733 * First, see if there are buffered packets and an idle transmitter -
734 * should never happen at this point.
735 */
736 if (sc->txb_inuse && (sc->xmit_busy == 0)) {
737 printf("ed: packets buffered, but transmitter idle\n");
738 ed_xmit(sc);
739 }
740
741 /*
742 * See if there is room to put another packet in the buffer.
743 */
744 if (sc->txb_inuse == sc->txb_cnt) {
745
746 /*
747 * No room. Indicate this to the outside world and exit.
748 */
749 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
750 return;
751 }
752 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
753 if (m == 0) {
754
755 /*
756 * We are using the !OACTIVE flag to indicate to the outside
757 * world that we can accept an additional packet rather than
758 * that the transmitter is _actually_ active. Indeed, the
759 * transmitter may be active, but if we haven't filled all the
760 * buffers with data then we still want to accept more.
761 */
762 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
763 return;
764 }
765
766 /*
767 * Copy the mbuf chain into the transmit buffer
768 */
769 m0 = m;
770
771 /* txb_new points to next open buffer slot */
772 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE);
773
774 len = sc->sc_write_mbufs(sc, m, buffer);
775 if (len == 0) {
776 m_freem(m0);
777 goto outloop;
778 }
779
780 sc->txb_len[sc->txb_new] = max(len, (ETHER_MIN_LEN-ETHER_CRC_LEN));
781
782 sc->txb_inuse++;
783
784 /*
785 * Point to next buffer slot and wrap if necessary.
786 */
787 sc->txb_new++;
788 if (sc->txb_new == sc->txb_cnt)
789 sc->txb_new = 0;
790
791 if (sc->xmit_busy == 0)
792 ed_xmit(sc);
793
794 /*
795 * Tap off here if there is a bpf listener.
796 */
797 BPF_MTAP(ifp, m0);
798
799 m_freem(m0);
800
801 /*
802 * Loop back to the top to possibly buffer more packets
803 */
804 goto outloop;
805 }
806
807 /*
808 * Ethernet interface receiver interrupt.
809 */
810 static __inline void
ed_rint(struct ed_softc * sc)811 ed_rint(struct ed_softc *sc)
812 {
813 struct ifnet *ifp = sc->ifp;
814 u_char boundry;
815 u_short len;
816 struct ed_ring packet_hdr;
817 bus_size_t packet_ptr;
818
819 ED_ASSERT_LOCKED(sc);
820
821 /*
822 * Set NIC to page 1 registers to get 'current' pointer
823 */
824 ed_nic_barrier(sc, ED_P0_CR, 1,
825 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
826 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
827 ed_nic_barrier(sc, ED_P0_CR, 1,
828 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
829
830 /*
831 * 'sc->next_packet' is the logical beginning of the ring-buffer -
832 * i.e. it points to where new data has been buffered. The 'CURR'
833 * (current) register points to the logical end of the ring-buffer -
834 * i.e. it points to where additional new data will be added. We loop
835 * here until the logical beginning equals the logical end (or in
836 * other words, until the ring-buffer is empty).
837 */
838 while (sc->next_packet != ed_nic_inb(sc, ED_P1_CURR)) {
839
840 /* get pointer to this buffer's header structure */
841 packet_ptr = sc->mem_ring +
842 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE;
843
844 /*
845 * The byte count includes a 4 byte header that was added by
846 * the NIC.
847 */
848 sc->readmem(sc, packet_ptr, (char *) &packet_hdr,
849 sizeof(packet_hdr));
850 len = packet_hdr.count;
851 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring)) ||
852 len < (ETHER_MIN_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring))) {
853 /*
854 * Length is a wild value. There's a good chance that
855 * this was caused by the NIC being old and buggy.
856 * The bug is that the length low byte is duplicated
857 * in the high byte. Try to recalculate the length
858 * based on the pointer to the next packet. Also,
859 * need ot preserve offset into page.
860 *
861 * NOTE: sc->next_packet is pointing at the current
862 * packet.
863 */
864 len &= ED_PAGE_SIZE - 1;
865 if (packet_hdr.next_packet >= sc->next_packet)
866 len += (packet_hdr.next_packet -
867 sc->next_packet) * ED_PAGE_SIZE;
868 else
869 len +=
870 ((packet_hdr.next_packet - sc->rec_page_start) +
871 (sc->rec_page_stop - sc->next_packet)) * ED_PAGE_SIZE;
872 /*
873 * because buffers are aligned on 256-byte boundary,
874 * the length computed above is off by 256 in almost
875 * all cases. Fix it...
876 */
877 if (len & 0xff)
878 len -= 256;
879 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN
880 + sizeof(struct ed_ring)))
881 sc->mibdata.dot3StatsFrameTooLongs++;
882 }
883
884 /*
885 * Be fairly liberal about what we allow as a "reasonable"
886 * length so that a [crufty] packet will make it to BPF (and
887 * can thus be analyzed). Note that all that is really
888 * important is that we have a length that will fit into one
889 * mbuf cluster or less; the upper layer protocols can then
890 * figure out the length from their own length field(s). But
891 * make sure that we have at least a full ethernet header or
892 * we would be unable to call ether_input() later.
893 */
894 if ((len >= sizeof(struct ed_ring) + ETHER_HDR_LEN) &&
895 (len <= MCLBYTES) &&
896 (packet_hdr.next_packet >= sc->rec_page_start) &&
897 (packet_hdr.next_packet < sc->rec_page_stop)) {
898 /*
899 * Go get packet.
900 */
901 ed_get_packet(sc, packet_ptr + sizeof(struct ed_ring),
902 len - sizeof(struct ed_ring));
903 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
904 } else {
905 /*
906 * Really BAD. The ring pointers are corrupted.
907 */
908 log(LOG_ERR,
909 "%s: NIC memory corrupt - invalid packet length %d\n",
910 ifp->if_xname, len);
911 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
912 ed_reset(ifp);
913 return;
914 }
915
916 /*
917 * Update next packet pointer
918 */
919 sc->next_packet = packet_hdr.next_packet;
920
921 /*
922 * Update NIC boundry pointer - being careful to keep it one
923 * buffer behind. (as recommended by NS databook)
924 */
925 boundry = sc->next_packet - 1;
926 if (boundry < sc->rec_page_start)
927 boundry = sc->rec_page_stop - 1;
928
929 /*
930 * Set NIC to page 0 registers to update boundry register
931 */
932 ed_nic_barrier(sc, ED_P0_CR, 1,
933 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
934 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
935 ed_nic_barrier(sc, ED_P0_CR, 1,
936 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
937 ed_nic_outb(sc, ED_P0_BNRY, boundry);
938
939 /*
940 * Set NIC to page 1 registers before looping to top (prepare
941 * to get 'CURR' current pointer)
942 */
943 ed_nic_barrier(sc, ED_P0_CR, 1,
944 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
945 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
946 ed_nic_barrier(sc, ED_P0_CR, 1,
947 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
948 }
949 }
950
951 /*
952 * Ethernet interface interrupt processor
953 */
954 void
edintr(void * arg)955 edintr(void *arg)
956 {
957 struct ed_softc *sc = (struct ed_softc*) arg;
958 struct ifnet *ifp = sc->ifp;
959 u_char isr;
960 int count;
961
962 ED_LOCK(sc);
963 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
964 ED_UNLOCK(sc);
965 return;
966 }
967 /*
968 * Set NIC to page 0 registers
969 */
970 ed_nic_barrier(sc, ED_P0_CR, 1,
971 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
972 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
973 ed_nic_barrier(sc, ED_P0_CR, 1,
974 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
975
976 /*
977 * loop until there are no more new interrupts. When the card goes
978 * away, the hardware will read back 0xff. Looking at the interrupts,
979 * it would appear that 0xff is impossible as ED_ISR_RST is normally
980 * clear. ED_ISR_RDC is also normally clear and only set while
981 * we're transferring memory to the card and we're holding the
982 * ED_LOCK (so we can't get into here).
983 */
984 while ((isr = ed_nic_inb(sc, ED_P0_ISR)) != 0 && isr != 0xff) {
985
986 /*
987 * reset all the bits that we are 'acknowledging' by writing a
988 * '1' to each bit position that was set (writing a '1'
989 * *clears* the bit)
990 */
991 ed_nic_outb(sc, ED_P0_ISR, isr);
992
993 /*
994 * The AX88190 and AX88190A has problems acking an interrupt
995 * and having them clear. This interferes with top-level loop
996 * here. Wait for all the bits to clear.
997 *
998 * We limit this to 5000 iterations. At 1us per inb/outb,
999 * this translates to about 15ms, which should be plenty of
1000 * time, and also gives protection in the card eject case.
1001 */
1002 if (sc->chip_type == ED_CHIP_TYPE_AX88190) {
1003 count = 5000; /* 15ms */
1004 while (count-- && (ed_nic_inb(sc, ED_P0_ISR) & isr)) {
1005 ed_nic_outb(sc, ED_P0_ISR,0);
1006 ed_nic_outb(sc, ED_P0_ISR,isr);
1007 }
1008 if (count == 0)
1009 break;
1010 }
1011
1012 /*
1013 * Handle transmitter interrupts. Handle these first because
1014 * the receiver will reset the board under some conditions.
1015 */
1016 if (isr & (ED_ISR_PTX | ED_ISR_TXE)) {
1017 u_char collisions = ed_nic_inb(sc, ED_P0_NCR) & 0x0f;
1018
1019 /*
1020 * Check for transmit error. If a TX completed with an
1021 * error, we end up throwing the packet away. Really
1022 * the only error that is possible is excessive
1023 * collisions, and in this case it is best to allow
1024 * the automatic mechanisms of TCP to backoff the
1025 * flow. Of course, with UDP we're screwed, but this
1026 * is expected when a network is heavily loaded.
1027 */
1028 (void) ed_nic_inb(sc, ED_P0_TSR);
1029 if (isr & ED_ISR_TXE) {
1030 u_char tsr;
1031
1032 /*
1033 * Excessive collisions (16)
1034 */
1035 tsr = ed_nic_inb(sc, ED_P0_TSR);
1036 if ((tsr & ED_TSR_ABT)
1037 && (collisions == 0)) {
1038
1039 /*
1040 * When collisions total 16, the
1041 * P0_NCR will indicate 0, and the
1042 * TSR_ABT is set.
1043 */
1044 collisions = 16;
1045 sc->mibdata.dot3StatsExcessiveCollisions++;
1046 sc->mibdata.dot3StatsCollFrequencies[15]++;
1047 }
1048 if (tsr & ED_TSR_OWC)
1049 sc->mibdata.dot3StatsLateCollisions++;
1050 if (tsr & ED_TSR_CDH)
1051 sc->mibdata.dot3StatsSQETestErrors++;
1052 if (tsr & ED_TSR_CRS)
1053 sc->mibdata.dot3StatsCarrierSenseErrors++;
1054 if (tsr & ED_TSR_FU)
1055 sc->mibdata.dot3StatsInternalMacTransmitErrors++;
1056
1057 /*
1058 * update output errors counter
1059 */
1060 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1061 } else {
1062
1063 /*
1064 * Update total number of successfully
1065 * transmitted packets.
1066 */
1067 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1068 }
1069
1070 /*
1071 * reset tx busy and output active flags
1072 */
1073 sc->xmit_busy = 0;
1074 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1075
1076 /*
1077 * clear watchdog timer
1078 */
1079 sc->tx_timer = 0;
1080
1081 /*
1082 * Add in total number of collisions on last
1083 * transmission.
1084 */
1085 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, collisions);
1086 switch(collisions) {
1087 case 0:
1088 case 16:
1089 break;
1090 case 1:
1091 sc->mibdata.dot3StatsSingleCollisionFrames++;
1092 sc->mibdata.dot3StatsCollFrequencies[0]++;
1093 break;
1094 default:
1095 sc->mibdata.dot3StatsMultipleCollisionFrames++;
1096 sc->mibdata.
1097 dot3StatsCollFrequencies[collisions-1]
1098 ++;
1099 break;
1100 }
1101
1102 /*
1103 * Decrement buffer in-use count if not zero (can only
1104 * be zero if a transmitter interrupt occured while
1105 * not actually transmitting). If data is ready to
1106 * transmit, start it transmitting, otherwise defer
1107 * until after handling receiver
1108 */
1109 if (sc->txb_inuse && --sc->txb_inuse)
1110 ed_xmit(sc);
1111 }
1112
1113 /*
1114 * Handle receiver interrupts
1115 */
1116 if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) {
1117
1118 /*
1119 * Overwrite warning. In order to make sure that a
1120 * lockup of the local DMA hasn't occurred, we reset
1121 * and re-init the NIC. The NSC manual suggests only a
1122 * partial reset/re-init is necessary - but some chips
1123 * seem to want more. The DMA lockup has been seen
1124 * only with early rev chips - Methinks this bug was
1125 * fixed in later revs. -DG
1126 */
1127 if (isr & ED_ISR_OVW) {
1128 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1129 #ifdef DIAGNOSTIC
1130 log(LOG_WARNING,
1131 "%s: warning - receiver ring buffer overrun\n",
1132 ifp->if_xname);
1133 #endif
1134
1135 /*
1136 * Stop/reset/re-init NIC
1137 */
1138 ed_reset(ifp);
1139 } else {
1140
1141 /*
1142 * Receiver Error. One or more of: CRC error,
1143 * frame alignment error FIFO overrun, or
1144 * missed packet.
1145 */
1146 if (isr & ED_ISR_RXE) {
1147 u_char rsr;
1148 rsr = ed_nic_inb(sc, ED_P0_RSR);
1149 if (rsr & ED_RSR_CRC)
1150 sc->mibdata.dot3StatsFCSErrors++;
1151 if (rsr & ED_RSR_FAE)
1152 sc->mibdata.dot3StatsAlignmentErrors++;
1153 if (rsr & ED_RSR_FO)
1154 sc->mibdata.dot3StatsInternalMacReceiveErrors++;
1155 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1156 #ifdef ED_DEBUG
1157 if_printf(ifp, "receive error %x\n",
1158 ed_nic_inb(sc, ED_P0_RSR));
1159 #endif
1160 }
1161
1162 /*
1163 * Go get the packet(s) XXX - Doing this on an
1164 * error is dubious because there shouldn't be
1165 * any data to get (we've configured the
1166 * interface to not accept packets with
1167 * errors).
1168 */
1169
1170 /*
1171 * Enable 16bit access to shared memory first
1172 * on WD/SMC boards.
1173 */
1174 ed_enable_16bit_access(sc);
1175 ed_rint(sc);
1176 ed_disable_16bit_access(sc);
1177 }
1178 }
1179
1180 /*
1181 * If it looks like the transmitter can take more data,
1182 * attempt to start output on the interface. This is done
1183 * after handling the receiver to give the receiver priority.
1184 */
1185 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0)
1186 ed_start_locked(ifp);
1187
1188 /*
1189 * return NIC CR to standard state: page 0, remote DMA
1190 * complete, start (toggling the TXP bit off, even if was just
1191 * set in the transmit routine, is *okay* - it is 'edge'
1192 * triggered from low to high)
1193 */
1194 ed_nic_barrier(sc, ED_P0_CR, 1,
1195 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
1196 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
1197 ed_nic_barrier(sc, ED_P0_CR, 1,
1198 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
1199
1200 /*
1201 * If the Network Talley Counters overflow, read them to reset
1202 * them. It appears that old 8390's won't clear the ISR flag
1203 * otherwise - resulting in an infinite loop.
1204 */
1205 if (isr & ED_ISR_CNT) {
1206 (void) ed_nic_inb(sc, ED_P0_CNTR0);
1207 (void) ed_nic_inb(sc, ED_P0_CNTR1);
1208 (void) ed_nic_inb(sc, ED_P0_CNTR2);
1209 }
1210 }
1211 ED_UNLOCK(sc);
1212 }
1213
1214 /*
1215 * Process an ioctl request.
1216 */
1217 static int
ed_ioctl(struct ifnet * ifp,u_long command,caddr_t data)1218 ed_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1219 {
1220 struct ed_softc *sc = ifp->if_softc;
1221 struct ifreq *ifr = (struct ifreq *)data;
1222 int error = 0;
1223
1224 switch (command) {
1225 case SIOCSIFFLAGS:
1226 /*
1227 * If the interface is marked up and stopped, then start it.
1228 * If we're up and already running, then it may be a mediachg.
1229 * If it is marked down and running, then stop it.
1230 */
1231 ED_LOCK(sc);
1232 if (ifp->if_flags & IFF_UP) {
1233 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1234 ed_init_locked(sc);
1235 else if (sc->sc_mediachg)
1236 sc->sc_mediachg(sc);
1237 } else {
1238 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1239 ed_stop(sc);
1240 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1241 }
1242 }
1243
1244 /*
1245 * Promiscuous flag may have changed, so reprogram the RCR.
1246 */
1247 ed_setrcr(sc);
1248
1249 ED_UNLOCK(sc);
1250 break;
1251
1252 case SIOCADDMULTI:
1253 case SIOCDELMULTI:
1254 /*
1255 * Multicast list has changed; set the hardware filter
1256 * accordingly.
1257 */
1258 ED_LOCK(sc);
1259 ed_setrcr(sc);
1260 ED_UNLOCK(sc);
1261 error = 0;
1262 break;
1263
1264 case SIOCGIFMEDIA:
1265 case SIOCSIFMEDIA:
1266 if (sc->sc_media_ioctl == NULL) {
1267 error = EINVAL;
1268 break;
1269 }
1270 sc->sc_media_ioctl(sc, ifr, command);
1271 break;
1272
1273 default:
1274 error = ether_ioctl(ifp, command, data);
1275 break;
1276 }
1277 return (error);
1278 }
1279
1280 /*
1281 * Given a source and destination address, copy 'amount' of a packet from
1282 * the ring buffer into a linear destination buffer. Takes into account
1283 * ring-wrap.
1284 */
1285 static __inline void
ed_ring_copy(struct ed_softc * sc,bus_size_t src,char * dst,u_short amount)1286 ed_ring_copy(struct ed_softc *sc, bus_size_t src, char *dst, u_short amount)
1287 {
1288 u_short tmp_amount;
1289
1290 /* does copy wrap to lower addr in ring buffer? */
1291 if (src + amount > sc->mem_end) {
1292 tmp_amount = sc->mem_end - src;
1293 /* copy amount up to end of NIC memory */
1294 sc->readmem(sc, src, dst, tmp_amount);
1295 amount -= tmp_amount;
1296 src = sc->mem_ring;
1297 dst += tmp_amount;
1298 }
1299 sc->readmem(sc, src, dst, amount);
1300 }
1301
1302 /*
1303 * Retreive packet from shared memory and send to the next level up via
1304 * ether_input().
1305 */
1306 static void
ed_get_packet(struct ed_softc * sc,bus_size_t buf,u_short len)1307 ed_get_packet(struct ed_softc *sc, bus_size_t buf, u_short len)
1308 {
1309 struct ifnet *ifp = sc->ifp;
1310 struct ether_header *eh;
1311 struct mbuf *m;
1312
1313 /* Allocate a header mbuf */
1314 MGETHDR(m, M_NOWAIT, MT_DATA);
1315 if (m == NULL)
1316 return;
1317 m->m_pkthdr.rcvif = ifp;
1318 m->m_pkthdr.len = m->m_len = len;
1319
1320 /*
1321 * We always put the received packet in a single buffer -
1322 * either with just an mbuf header or in a cluster attached
1323 * to the header. The +2 is to compensate for the alignment
1324 * fixup below.
1325 */
1326 if ((len + 2) > MHLEN) {
1327 /* Attach an mbuf cluster */
1328 if (!(MCLGET(m, M_NOWAIT))) {
1329 m_freem(m);
1330 return;
1331 }
1332 }
1333
1334 /*
1335 * The +2 is to longword align the start of the real packet.
1336 * This is important for NFS.
1337 */
1338 m->m_data += 2;
1339 eh = mtod(m, struct ether_header *);
1340
1341 /*
1342 * Get packet, including link layer address, from interface.
1343 */
1344 ed_ring_copy(sc, buf, (char *)eh, len);
1345
1346 m->m_pkthdr.len = m->m_len = len;
1347
1348 ED_UNLOCK(sc);
1349 (*ifp->if_input)(ifp, m);
1350 ED_LOCK(sc);
1351 }
1352
1353 /*
1354 * Supporting routines
1355 */
1356
1357 /*
1358 * Given a NIC memory source address and a host memory destination
1359 * address, copy 'amount' from NIC to host using shared memory.
1360 * The 'amount' is rounded up to a word - okay as long as mbufs
1361 * are word sized. That's what the +1 is below.
1362 * This routine accesses things as 16 bit quantities.
1363 */
1364 void
ed_shmem_readmem16(struct ed_softc * sc,bus_size_t src,uint8_t * dst,uint16_t amount)1365 ed_shmem_readmem16(struct ed_softc *sc, bus_size_t src, uint8_t *dst,
1366 uint16_t amount)
1367 {
1368 bus_space_read_region_2(sc->mem_bst, sc->mem_bsh, src, (uint16_t *)dst,
1369 (amount + 1) / 2);
1370 }
1371
1372 /*
1373 * Given a NIC memory source address and a host memory destination
1374 * address, copy 'amount' from NIC to host using shared memory.
1375 * This routine accesses things as 8 bit quantities.
1376 */
1377 void
ed_shmem_readmem8(struct ed_softc * sc,bus_size_t src,uint8_t * dst,uint16_t amount)1378 ed_shmem_readmem8(struct ed_softc *sc, bus_size_t src, uint8_t *dst,
1379 uint16_t amount)
1380 {
1381 bus_space_read_region_1(sc->mem_bst, sc->mem_bsh, src, dst, amount);
1382 }
1383
1384 /*
1385 * Given a NIC memory source address and a host memory destination
1386 * address, copy 'amount' from NIC to host using Programmed I/O.
1387 * The 'amount' is rounded up to a word - okay as long as mbufs
1388 * are word sized.
1389 * This routine is currently Novell-specific.
1390 */
1391 void
ed_pio_readmem(struct ed_softc * sc,bus_size_t src,uint8_t * dst,uint16_t amount)1392 ed_pio_readmem(struct ed_softc *sc, bus_size_t src, uint8_t *dst,
1393 uint16_t amount)
1394 {
1395 /* Regular Novell cards */
1396 /* select page 0 registers */
1397 ed_nic_barrier(sc, ED_P0_CR, 1,
1398 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
1399 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
1400 ed_nic_barrier(sc, ED_P0_CR, 1,
1401 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
1402
1403 /* round up to a word */
1404 if (amount & 1)
1405 ++amount;
1406
1407 /* set up DMA byte count */
1408 ed_nic_outb(sc, ED_P0_RBCR0, amount);
1409 ed_nic_outb(sc, ED_P0_RBCR1, amount >> 8);
1410
1411 /* set up source address in NIC mem */
1412 ed_nic_outb(sc, ED_P0_RSAR0, src);
1413 ed_nic_outb(sc, ED_P0_RSAR1, src >> 8);
1414
1415 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD0 | ED_CR_STA);
1416
1417 if (sc->isa16bit)
1418 ed_asic_insw(sc, ED_NOVELL_DATA, dst, amount / 2);
1419 else
1420 ed_asic_insb(sc, ED_NOVELL_DATA, dst, amount);
1421 }
1422
1423 /*
1424 * Stripped down routine for writing a linear buffer to NIC memory.
1425 * Only used in the probe routine to test the memory. 'len' must
1426 * be even.
1427 */
1428 void
ed_pio_writemem(struct ed_softc * sc,uint8_t * src,uint16_t dst,uint16_t len)1429 ed_pio_writemem(struct ed_softc *sc, uint8_t *src, uint16_t dst, uint16_t len)
1430 {
1431 int maxwait = 200; /* about 240us */
1432
1433 /* select page 0 registers */
1434 ed_nic_barrier(sc, ED_P0_CR, 1,
1435 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
1436 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
1437 ed_nic_barrier(sc, ED_P0_CR, 1,
1438 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
1439
1440 /* reset remote DMA complete flag */
1441 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
1442
1443 /* set up DMA byte count */
1444 ed_nic_outb(sc, ED_P0_RBCR0, len);
1445 ed_nic_outb(sc, ED_P0_RBCR1, len >> 8);
1446
1447 /* set up destination address in NIC mem */
1448 ed_nic_outb(sc, ED_P0_RSAR0, dst);
1449 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8);
1450
1451 /* set remote DMA write */
1452 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
1453
1454 if (sc->isa16bit)
1455 ed_asic_outsw(sc, ED_NOVELL_DATA, src, len / 2);
1456 else
1457 ed_asic_outsb(sc, ED_NOVELL_DATA, src, len);
1458
1459 /*
1460 * Wait for remote DMA complete. This is necessary because on the
1461 * transmit side, data is handled internally by the NIC in bursts and
1462 * we can't start another remote DMA until this one completes. Not
1463 * waiting causes really bad things to happen - like the NIC
1464 * irrecoverably jamming the ISA bus.
1465 */
1466 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) &&
1467 --maxwait)
1468 continue;
1469 }
1470
1471 /*
1472 * Write an mbuf chain to the destination NIC memory address using
1473 * programmed I/O.
1474 */
1475 u_short
ed_pio_write_mbufs(struct ed_softc * sc,struct mbuf * m,bus_size_t dst)1476 ed_pio_write_mbufs(struct ed_softc *sc, struct mbuf *m, bus_size_t dst)
1477 {
1478 struct ifnet *ifp = sc->ifp;
1479 unsigned short total_len, dma_len;
1480 struct mbuf *mp;
1481 int maxwait = 200; /* about 240us */
1482
1483 ED_ASSERT_LOCKED(sc);
1484
1485 /* Regular Novell cards */
1486 /* First, count up the total number of bytes to copy */
1487 for (total_len = 0, mp = m; mp; mp = mp->m_next)
1488 total_len += mp->m_len;
1489
1490 dma_len = total_len;
1491 if (sc->isa16bit && (dma_len & 1))
1492 dma_len++;
1493
1494 /* select page 0 registers */
1495 ed_nic_barrier(sc, ED_P0_CR, 1,
1496 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
1497 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
1498 ed_nic_barrier(sc, ED_P0_CR, 1,
1499 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
1500
1501 /* reset remote DMA complete flag */
1502 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
1503
1504 /* set up DMA byte count */
1505 ed_nic_outb(sc, ED_P0_RBCR0, dma_len);
1506 ed_nic_outb(sc, ED_P0_RBCR1, dma_len >> 8);
1507
1508 /* set up destination address in NIC mem */
1509 ed_nic_outb(sc, ED_P0_RSAR0, dst);
1510 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8);
1511
1512 /* set remote DMA write */
1513 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
1514
1515 /*
1516 * Transfer the mbuf chain to the NIC memory.
1517 * 16-bit cards require that data be transferred as words, and only words.
1518 * So that case requires some extra code to patch over odd-length mbufs.
1519 */
1520
1521 if (!sc->isa16bit) {
1522 /* NE1000s are easy */
1523 while (m) {
1524 if (m->m_len)
1525 ed_asic_outsb(sc, ED_NOVELL_DATA,
1526 m->m_data, m->m_len);
1527 m = m->m_next;
1528 }
1529 } else {
1530 /* NE2000s are a pain */
1531 uint8_t *data;
1532 int len, wantbyte;
1533 union {
1534 uint16_t w;
1535 uint8_t b[2];
1536 } saveword;
1537
1538 wantbyte = 0;
1539
1540 while (m) {
1541 len = m->m_len;
1542 if (len) {
1543 data = mtod(m, caddr_t);
1544 /* finish the last word */
1545 if (wantbyte) {
1546 saveword.b[1] = *data;
1547 ed_asic_outw(sc, ED_NOVELL_DATA,
1548 saveword.w);
1549 data++;
1550 len--;
1551 wantbyte = 0;
1552 }
1553 /* output contiguous words */
1554 if (len > 1) {
1555 ed_asic_outsw(sc, ED_NOVELL_DATA,
1556 data, len >> 1);
1557 data += len & ~1;
1558 len &= 1;
1559 }
1560 /* save last byte, if necessary */
1561 if (len == 1) {
1562 saveword.b[0] = *data;
1563 wantbyte = 1;
1564 }
1565 }
1566 m = m->m_next;
1567 }
1568 /* spit last byte */
1569 if (wantbyte)
1570 ed_asic_outw(sc, ED_NOVELL_DATA, saveword.w);
1571 }
1572
1573 /*
1574 * Wait for remote DMA complete. This is necessary because on the
1575 * transmit side, data is handled internally by the NIC in bursts and
1576 * we can't start another remote DMA until this one completes. Not
1577 * waiting causes really bad things to happen - like the NIC
1578 * irrecoverably jamming the ISA bus.
1579 */
1580 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) &&
1581 --maxwait)
1582 continue;
1583
1584 if (!maxwait) {
1585 log(LOG_WARNING, "%s: remote transmit DMA failed to complete\n",
1586 ifp->if_xname);
1587 ed_reset(ifp);
1588 return(0);
1589 }
1590 return (total_len);
1591 }
1592
1593 static void
ed_setrcr(struct ed_softc * sc)1594 ed_setrcr(struct ed_softc *sc)
1595 {
1596 struct ifnet *ifp = sc->ifp;
1597 int i;
1598 u_char reg1;
1599
1600 ED_ASSERT_LOCKED(sc);
1601
1602 /* Bit 6 in AX88190 RCR register must be set. */
1603 if (sc->chip_type == ED_CHIP_TYPE_AX88190 ||
1604 sc->chip_type == ED_CHIP_TYPE_AX88790)
1605 reg1 = ED_RCR_INTT;
1606 else
1607 reg1 = 0x00;
1608
1609 /* set page 1 registers */
1610 ed_nic_barrier(sc, ED_P0_CR, 1,
1611 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
1612 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
1613 ed_nic_barrier(sc, ED_P0_CR, 1,
1614 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
1615
1616 if (ifp->if_flags & IFF_PROMISC) {
1617
1618 /*
1619 * Reconfigure the multicast filter.
1620 */
1621 for (i = 0; i < 8; i++)
1622 ed_nic_outb(sc, ED_P1_MAR(i), 0xff);
1623
1624 /*
1625 * And turn on promiscuous mode. Also enable reception of
1626 * runts and packets with CRC & alignment errors.
1627 */
1628 /* Set page 0 registers */
1629 ed_nic_barrier(sc, ED_P0_CR, 1,
1630 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
1631 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
1632 ed_nic_barrier(sc, ED_P0_CR, 1,
1633 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
1634
1635 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_PRO | ED_RCR_AM |
1636 ED_RCR_AB | ED_RCR_AR | ED_RCR_SEP | reg1);
1637 } else {
1638 /* set up multicast addresses and filter modes */
1639 if (ifp->if_flags & IFF_MULTICAST) {
1640 uint32_t mcaf[2];
1641
1642 if (ifp->if_flags & IFF_ALLMULTI) {
1643 mcaf[0] = 0xffffffff;
1644 mcaf[1] = 0xffffffff;
1645 } else
1646 ed_ds_getmcaf(sc, mcaf);
1647
1648 /*
1649 * Set multicast filter on chip.
1650 */
1651 for (i = 0; i < 8; i++)
1652 ed_nic_outb(sc, ED_P1_MAR(i), ((u_char *) mcaf)[i]);
1653
1654 /* Set page 0 registers */
1655 ed_nic_barrier(sc, ED_P0_CR, 1,
1656 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
1657 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
1658 ed_nic_barrier(sc, ED_P0_CR, 1,
1659 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
1660
1661 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AM | ED_RCR_AB | reg1);
1662 } else {
1663
1664 /*
1665 * Initialize multicast address hashing registers to
1666 * not accept multicasts.
1667 */
1668 for (i = 0; i < 8; ++i)
1669 ed_nic_outb(sc, ED_P1_MAR(i), 0x00);
1670
1671 /* Set page 0 registers */
1672 ed_nic_barrier(sc, ED_P0_CR, 1,
1673 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
1674 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
1675
1676 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AB | reg1);
1677 }
1678 }
1679
1680 /*
1681 * Start interface.
1682 */
1683 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
1684 }
1685
1686 /*
1687 * Compute the multicast address filter from the
1688 * list of multicast addresses we need to listen to.
1689 */
1690 static void
ed_ds_getmcaf(struct ed_softc * sc,uint32_t * mcaf)1691 ed_ds_getmcaf(struct ed_softc *sc, uint32_t *mcaf)
1692 {
1693 uint32_t index;
1694 u_char *af = (u_char *) mcaf;
1695 struct ifmultiaddr *ifma;
1696
1697 mcaf[0] = 0;
1698 mcaf[1] = 0;
1699
1700 if_maddr_rlock(sc->ifp);
1701 TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) {
1702 if (ifma->ifma_addr->sa_family != AF_LINK)
1703 continue;
1704 index = ether_crc32_be(LLADDR((struct sockaddr_dl *)
1705 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
1706 af[index >> 3] |= 1 << (index & 7);
1707 }
1708 if_maddr_runlock(sc->ifp);
1709 }
1710
1711 int
ed_isa_mem_ok(device_t dev,u_long pmem,u_int memsize)1712 ed_isa_mem_ok(device_t dev, u_long pmem, u_int memsize)
1713 {
1714 if (pmem < 0xa0000 || pmem + memsize > 0x1000000) {
1715 device_printf(dev, "Invalid ISA memory address range "
1716 "configured: 0x%lx - 0x%lx\n", pmem, pmem + memsize);
1717 return (ENXIO);
1718 }
1719 return (0);
1720 }
1721
1722 int
ed_clear_memory(device_t dev)1723 ed_clear_memory(device_t dev)
1724 {
1725 struct ed_softc *sc = device_get_softc(dev);
1726 bus_size_t i;
1727
1728 bus_space_set_region_1(sc->mem_bst, sc->mem_bsh, sc->mem_start,
1729 0, sc->mem_size);
1730
1731 for (i = 0; i < sc->mem_size; i++) {
1732 if (bus_space_read_1(sc->mem_bst, sc->mem_bsh,
1733 sc->mem_start + i)) {
1734 device_printf(dev, "failed to clear shared memory at "
1735 "0x%jx - check configuration\n",
1736 (uintmax_t)rman_get_start(sc->mem_res) + i);
1737 return (ENXIO);
1738 }
1739 }
1740 return (0);
1741 }
1742
1743 u_short
ed_shmem_write_mbufs(struct ed_softc * sc,struct mbuf * m,bus_size_t dst)1744 ed_shmem_write_mbufs(struct ed_softc *sc, struct mbuf *m, bus_size_t dst)
1745 {
1746 u_short len;
1747
1748 /*
1749 * Special case setup for 16 bit boards...
1750 */
1751 if (sc->isa16bit) {
1752 switch (sc->vendor) {
1753 #ifdef ED_3C503
1754 /*
1755 * For 16bit 3Com boards (which have 16k of
1756 * memory), we have the xmit buffers in a
1757 * different page of memory ('page 0') - so
1758 * change pages.
1759 */
1760 case ED_VENDOR_3COM:
1761 ed_asic_outb(sc, ED_3COM_GACFR, ED_3COM_GACFR_RSEL);
1762 break;
1763 #endif
1764 /*
1765 * Enable 16bit access to shared memory on
1766 * WD/SMC boards.
1767 *
1768 * XXX - same as ed_enable_16bit_access()
1769 */
1770 case ED_VENDOR_WD_SMC:
1771 ed_asic_outb(sc, ED_WD_LAAR,
1772 sc->wd_laar_proto | ED_WD_LAAR_M16EN);
1773 if (sc->chip_type == ED_CHIP_TYPE_WD790)
1774 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB);
1775 break;
1776 }
1777 }
1778 for (len = 0; m != NULL; m = m->m_next) {
1779 if (m->m_len == 0)
1780 continue;
1781 if (sc->isa16bit) {
1782 if (m->m_len > 1)
1783 bus_space_write_region_2(sc->mem_bst,
1784 sc->mem_bsh, dst,
1785 mtod(m, uint16_t *), m->m_len / 2);
1786 if ((m->m_len & 1) != 0)
1787 bus_space_write_1(sc->mem_bst, sc->mem_bsh,
1788 dst + m->m_len - 1,
1789 *(mtod(m, uint8_t *) + m->m_len - 1));
1790 } else
1791 bus_space_write_region_1(sc->mem_bst,
1792 sc->mem_bsh, dst,
1793 mtod(m, uint8_t *), m->m_len);
1794 dst += m->m_len;
1795 len += m->m_len;
1796 }
1797
1798 /*
1799 * Restore previous shared memory access
1800 */
1801 if (sc->isa16bit) {
1802 switch (sc->vendor) {
1803 #ifdef ED_3C503
1804 case ED_VENDOR_3COM:
1805 ed_asic_outb(sc, ED_3COM_GACFR,
1806 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0);
1807 break;
1808 #endif
1809 case ED_VENDOR_WD_SMC:
1810 /* XXX - same as ed_disable_16bit_access() */
1811 if (sc->chip_type == ED_CHIP_TYPE_WD790)
1812 ed_asic_outb(sc, ED_WD_MSR, 0x00);
1813 ed_asic_outb(sc, ED_WD_LAAR,
1814 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
1815 break;
1816 }
1817 }
1818 return (len);
1819 }
1820
1821 /*
1822 * Generic ifmedia support. By default, the DP8390-based cards don't know
1823 * what their network attachment really is, or even if it is valid (except
1824 * upon successful transmission of a packet). To play nicer with dhclient, as
1825 * well as to fit in with a framework where some cards can provde more
1826 * detailed information, make sure that we use this as a fallback.
1827 */
1828 static int
ed_gen_ifmedia_ioctl(struct ed_softc * sc,struct ifreq * ifr,u_long command)1829 ed_gen_ifmedia_ioctl(struct ed_softc *sc, struct ifreq *ifr, u_long command)
1830 {
1831 return (ifmedia_ioctl(sc->ifp, ifr, &sc->ifmedia, command));
1832 }
1833
1834 static int
ed_gen_ifmedia_upd(struct ifnet * ifp)1835 ed_gen_ifmedia_upd(struct ifnet *ifp)
1836 {
1837 return 0;
1838 }
1839
1840 static void
ed_gen_ifmedia_sts(struct ifnet * ifp,struct ifmediareq * ifmr)1841 ed_gen_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1842 {
1843 ifmr->ifm_active = IFM_ETHER | IFM_AUTO;
1844 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE;
1845 }
1846
1847 void
ed_gen_ifmedia_init(struct ed_softc * sc)1848 ed_gen_ifmedia_init(struct ed_softc *sc)
1849 {
1850 sc->sc_media_ioctl = &ed_gen_ifmedia_ioctl;
1851 ifmedia_init(&sc->ifmedia, 0, ed_gen_ifmedia_upd, ed_gen_ifmedia_sts);
1852 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0, 0);
1853 ifmedia_set(&sc->ifmedia, IFM_ETHER | IFM_AUTO);
1854 }
1855