1 /*-
2 * Copyright (c) 2014-2019 Ruslan Bukin <br@bsdpad.com>
3 * All rights reserved.
4 *
5 * This software was developed by SRI International and the University of
6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
7 * ("CTSRD"), as part of the DARPA CRASH research programme.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31 /*
32 * Synopsys DesignWare Mobile Storage Host Controller
33 * Chapter 14, Altera Cyclone V Device Handbook (CV-5V2 2014.07.22)
34 */
35
36 #include <sys/cdefs.h>
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/conf.h>
40 #include <sys/bus.h>
41 #include <sys/kernel.h>
42 #include <sys/lock.h>
43 #include <sys/module.h>
44 #include <sys/malloc.h>
45 #include <sys/mutex.h>
46 #include <sys/proc.h>
47 #include <sys/rman.h>
48 #include <sys/queue.h>
49 #include <sys/taskqueue.h>
50
51 #include <dev/mmc/bridge.h>
52 #include <dev/mmc/mmcbrvar.h>
53 #include <dev/mmc/mmc_fdt_helpers.h>
54
55 #include <dev/fdt/fdt_common.h>
56 #include <dev/ofw/openfirm.h>
57 #include <dev/ofw/ofw_bus.h>
58 #include <dev/ofw/ofw_bus_subr.h>
59
60 #include <machine/bus.h>
61 #include <machine/cpu.h>
62 #include <machine/intr.h>
63
64 #include <dev/extres/clk/clk.h>
65
66 #include <dev/mmc/host/dwmmc_reg.h>
67 #include <dev/mmc/host/dwmmc_var.h>
68
69 #include "opt_mmccam.h"
70
71 #ifdef MMCCAM
72 #include <cam/cam.h>
73 #include <cam/cam_ccb.h>
74 #include <cam/cam_debug.h>
75 #include <cam/cam_sim.h>
76 #include <cam/cam_xpt_sim.h>
77
78 #include "mmc_sim_if.h"
79 #endif
80
81 #include "mmcbr_if.h"
82
83 #ifdef DEBUG
84 #define dprintf(fmt, args...) printf(fmt, ##args)
85 #else
86 #define dprintf(x, arg...)
87 #endif
88
89 #define READ4(_sc, _reg) \
90 bus_read_4((_sc)->res[0], _reg)
91 #define WRITE4(_sc, _reg, _val) \
92 bus_write_4((_sc)->res[0], _reg, _val)
93
94 #define DIV_ROUND_UP(n, d) howmany(n, d)
95
96 #define DWMMC_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
97 #define DWMMC_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
98 #define DWMMC_LOCK_INIT(_sc) \
99 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \
100 "dwmmc", MTX_DEF)
101 #define DWMMC_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
102 #define DWMMC_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED);
103 #define DWMMC_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED);
104
105 #define PENDING_CMD 0x01
106 #define PENDING_STOP 0x02
107 #define CARD_INIT_DONE 0x04
108
109 #define DWMMC_DATA_ERR_FLAGS (SDMMC_INTMASK_DRT | SDMMC_INTMASK_DCRC \
110 |SDMMC_INTMASK_SBE | SDMMC_INTMASK_EBE)
111 #define DWMMC_CMD_ERR_FLAGS (SDMMC_INTMASK_RTO | SDMMC_INTMASK_RCRC \
112 |SDMMC_INTMASK_RE)
113 #define DWMMC_ERR_FLAGS (DWMMC_DATA_ERR_FLAGS | DWMMC_CMD_ERR_FLAGS \
114 |SDMMC_INTMASK_HLE)
115
116 #define DES0_DIC (1 << 1) /* Disable Interrupt on Completion */
117 #define DES0_LD (1 << 2) /* Last Descriptor */
118 #define DES0_FS (1 << 3) /* First Descriptor */
119 #define DES0_CH (1 << 4) /* second address CHained */
120 #define DES0_ER (1 << 5) /* End of Ring */
121 #define DES0_CES (1 << 30) /* Card Error Summary */
122 #define DES0_OWN (1 << 31) /* OWN */
123
124 #define DES1_BS1_MASK 0x1fff
125
126 struct idmac_desc {
127 uint32_t des0; /* control */
128 uint32_t des1; /* bufsize */
129 uint32_t des2; /* buf1 phys addr */
130 uint32_t des3; /* buf2 phys addr or next descr */
131 };
132
133 #define IDMAC_DESC_SEGS (PAGE_SIZE / (sizeof(struct idmac_desc)))
134 #define IDMAC_DESC_SIZE (sizeof(struct idmac_desc) * IDMAC_DESC_SEGS)
135 #define DEF_MSIZE 0x2 /* Burst size of multiple transaction */
136 /*
137 * Size field in DMA descriptor is 13 bits long (up to 4095 bytes),
138 * but must be a multiple of the data bus size.Additionally, we must ensure
139 * that bus_dmamap_load() doesn't additionally fragments buffer (because it
140 * is processed with page size granularity). Thus limit fragment size to half
141 * of page.
142 * XXX switch descriptor format to array and use second buffer pointer for
143 * second half of page
144 */
145 #define IDMAC_MAX_SIZE 2048
146 /*
147 * Busdma may bounce buffers, so we must reserve 2 descriptors
148 * (on start and on end) for bounced fragments.
149 */
150 #define DWMMC_MAX_DATA (IDMAC_MAX_SIZE * (IDMAC_DESC_SEGS - 2)) / MMC_SECTOR_SIZE
151
152 static void dwmmc_next_operation(struct dwmmc_softc *);
153 static int dwmmc_setup_bus(struct dwmmc_softc *, int);
154 static int dma_done(struct dwmmc_softc *, struct mmc_command *);
155 static int dma_stop(struct dwmmc_softc *);
156 static void pio_read(struct dwmmc_softc *, struct mmc_command *);
157 static void pio_write(struct dwmmc_softc *, struct mmc_command *);
158 static void dwmmc_handle_card_present(struct dwmmc_softc *sc, bool is_present);
159
160 static struct resource_spec dwmmc_spec[] = {
161 { SYS_RES_MEMORY, 0, RF_ACTIVE },
162 { SYS_RES_IRQ, 0, RF_ACTIVE },
163 { -1, 0 }
164 };
165
166 #define HWTYPE_MASK (0x0000ffff)
167 #define HWFLAG_MASK (0xffff << 16)
168
169 static void
dwmmc_get1paddr(void * arg,bus_dma_segment_t * segs,int nsegs,int error)170 dwmmc_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
171 {
172
173 if (nsegs != 1)
174 panic("%s: nsegs != 1 (%d)\n", __func__, nsegs);
175 if (error != 0)
176 panic("%s: error != 0 (%d)\n", __func__, error);
177
178 *(bus_addr_t *)arg = segs[0].ds_addr;
179 }
180
181 static void
dwmmc_ring_setup(void * arg,bus_dma_segment_t * segs,int nsegs,int error)182 dwmmc_ring_setup(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
183 {
184 struct dwmmc_softc *sc;
185 int idx;
186
187 sc = arg;
188 dprintf("nsegs %d seg0len %lu\n", nsegs, segs[0].ds_len);
189 if (error != 0)
190 panic("%s: error != 0 (%d)\n", __func__, error);
191
192 for (idx = 0; idx < nsegs; idx++) {
193 sc->desc_ring[idx].des0 = DES0_DIC | DES0_CH;
194 sc->desc_ring[idx].des1 = segs[idx].ds_len & DES1_BS1_MASK;
195 sc->desc_ring[idx].des2 = segs[idx].ds_addr;
196
197 if (idx == 0)
198 sc->desc_ring[idx].des0 |= DES0_FS;
199
200 if (idx == (nsegs - 1)) {
201 sc->desc_ring[idx].des0 &= ~(DES0_DIC | DES0_CH);
202 sc->desc_ring[idx].des0 |= DES0_LD;
203 }
204 wmb();
205 sc->desc_ring[idx].des0 |= DES0_OWN;
206 }
207 }
208
209 static int
dwmmc_ctrl_reset(struct dwmmc_softc * sc,int reset_bits)210 dwmmc_ctrl_reset(struct dwmmc_softc *sc, int reset_bits)
211 {
212 int reg;
213 int i;
214
215 reg = READ4(sc, SDMMC_CTRL);
216 reg |= (reset_bits);
217 WRITE4(sc, SDMMC_CTRL, reg);
218
219 /* Wait reset done */
220 for (i = 0; i < 100; i++) {
221 if (!(READ4(sc, SDMMC_CTRL) & reset_bits))
222 return (0);
223 DELAY(10);
224 }
225
226 device_printf(sc->dev, "Reset failed\n");
227
228 return (1);
229 }
230
231 static int
dma_setup(struct dwmmc_softc * sc)232 dma_setup(struct dwmmc_softc *sc)
233 {
234 int error;
235 int nidx;
236 int idx;
237
238 /*
239 * Set up TX descriptor ring, descriptors, and dma maps.
240 */
241 error = bus_dma_tag_create(
242 bus_get_dma_tag(sc->dev), /* Parent tag. */
243 4096, 0, /* alignment, boundary */
244 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
245 BUS_SPACE_MAXADDR, /* highaddr */
246 NULL, NULL, /* filter, filterarg */
247 IDMAC_DESC_SIZE, 1, /* maxsize, nsegments */
248 IDMAC_DESC_SIZE, /* maxsegsize */
249 0, /* flags */
250 NULL, NULL, /* lockfunc, lockarg */
251 &sc->desc_tag);
252 if (error != 0) {
253 device_printf(sc->dev,
254 "could not create ring DMA tag.\n");
255 return (1);
256 }
257
258 error = bus_dmamem_alloc(sc->desc_tag, (void**)&sc->desc_ring,
259 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO,
260 &sc->desc_map);
261 if (error != 0) {
262 device_printf(sc->dev,
263 "could not allocate descriptor ring.\n");
264 return (1);
265 }
266
267 error = bus_dmamap_load(sc->desc_tag, sc->desc_map,
268 sc->desc_ring, IDMAC_DESC_SIZE, dwmmc_get1paddr,
269 &sc->desc_ring_paddr, 0);
270 if (error != 0) {
271 device_printf(sc->dev,
272 "could not load descriptor ring map.\n");
273 return (1);
274 }
275
276 for (idx = 0; idx < IDMAC_DESC_SEGS; idx++) {
277 sc->desc_ring[idx].des0 = DES0_CH;
278 sc->desc_ring[idx].des1 = 0;
279 nidx = (idx + 1) % IDMAC_DESC_SEGS;
280 sc->desc_ring[idx].des3 = sc->desc_ring_paddr + \
281 (nidx * sizeof(struct idmac_desc));
282 }
283 sc->desc_ring[idx - 1].des3 = sc->desc_ring_paddr;
284 sc->desc_ring[idx - 1].des0 |= DES0_ER;
285
286 error = bus_dma_tag_create(
287 bus_get_dma_tag(sc->dev), /* Parent tag. */
288 8, 0, /* alignment, boundary */
289 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
290 BUS_SPACE_MAXADDR, /* highaddr */
291 NULL, NULL, /* filter, filterarg */
292 IDMAC_MAX_SIZE * IDMAC_DESC_SEGS, /* maxsize */
293 IDMAC_DESC_SEGS, /* nsegments */
294 IDMAC_MAX_SIZE, /* maxsegsize */
295 0, /* flags */
296 NULL, NULL, /* lockfunc, lockarg */
297 &sc->buf_tag);
298 if (error != 0) {
299 device_printf(sc->dev,
300 "could not create ring DMA tag.\n");
301 return (1);
302 }
303
304 error = bus_dmamap_create(sc->buf_tag, 0,
305 &sc->buf_map);
306 if (error != 0) {
307 device_printf(sc->dev,
308 "could not create TX buffer DMA map.\n");
309 return (1);
310 }
311
312 return (0);
313 }
314
315 static void
dwmmc_cmd_done(struct dwmmc_softc * sc)316 dwmmc_cmd_done(struct dwmmc_softc *sc)
317 {
318 struct mmc_command *cmd;
319 #ifdef MMCCAM
320 union ccb *ccb;
321 #endif
322
323 #ifdef MMCCAM
324 ccb = sc->ccb;
325 if (ccb == NULL)
326 return;
327 cmd = &ccb->mmcio.cmd;
328 #else
329 cmd = sc->curcmd;
330 #endif
331 if (cmd == NULL)
332 return;
333
334 if (cmd->flags & MMC_RSP_PRESENT) {
335 if (cmd->flags & MMC_RSP_136) {
336 cmd->resp[3] = READ4(sc, SDMMC_RESP0);
337 cmd->resp[2] = READ4(sc, SDMMC_RESP1);
338 cmd->resp[1] = READ4(sc, SDMMC_RESP2);
339 cmd->resp[0] = READ4(sc, SDMMC_RESP3);
340 } else {
341 cmd->resp[3] = 0;
342 cmd->resp[2] = 0;
343 cmd->resp[1] = 0;
344 cmd->resp[0] = READ4(sc, SDMMC_RESP0);
345 }
346 }
347 }
348
349 static void
dwmmc_tasklet(struct dwmmc_softc * sc)350 dwmmc_tasklet(struct dwmmc_softc *sc)
351 {
352 struct mmc_command *cmd;
353
354 cmd = sc->curcmd;
355 if (cmd == NULL)
356 return;
357
358 if (!sc->cmd_done)
359 return;
360
361 if (cmd->error != MMC_ERR_NONE || !cmd->data) {
362 dwmmc_next_operation(sc);
363 } else if (cmd->data && sc->dto_rcvd) {
364 if ((cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK ||
365 cmd->opcode == MMC_READ_MULTIPLE_BLOCK) &&
366 sc->use_auto_stop) {
367 if (sc->acd_rcvd)
368 dwmmc_next_operation(sc);
369 } else {
370 dwmmc_next_operation(sc);
371 }
372 }
373 }
374
375 static void
dwmmc_intr(void * arg)376 dwmmc_intr(void *arg)
377 {
378 struct mmc_command *cmd;
379 struct dwmmc_softc *sc;
380 uint32_t reg;
381
382 sc = arg;
383
384 DWMMC_LOCK(sc);
385
386 cmd = sc->curcmd;
387
388 /* First handle SDMMC controller interrupts */
389 reg = READ4(sc, SDMMC_MINTSTS);
390 if (reg) {
391 dprintf("%s 0x%08x\n", __func__, reg);
392
393 if (reg & DWMMC_CMD_ERR_FLAGS) {
394 dprintf("cmd err 0x%08x cmd 0x%08x\n",
395 reg, cmd->opcode);
396 cmd->error = MMC_ERR_TIMEOUT;
397 }
398
399 if (reg & DWMMC_DATA_ERR_FLAGS) {
400 dprintf("data err 0x%08x cmd 0x%08x\n",
401 reg, cmd->opcode);
402 cmd->error = MMC_ERR_FAILED;
403 if (!sc->use_pio) {
404 dma_done(sc, cmd);
405 dma_stop(sc);
406 }
407 }
408
409 if (reg & SDMMC_INTMASK_CMD_DONE) {
410 dwmmc_cmd_done(sc);
411 sc->cmd_done = 1;
412 }
413
414 if (reg & SDMMC_INTMASK_ACD)
415 sc->acd_rcvd = 1;
416
417 if (reg & SDMMC_INTMASK_DTO)
418 sc->dto_rcvd = 1;
419
420 if (reg & SDMMC_INTMASK_CD) {
421 dwmmc_handle_card_present(sc,
422 READ4(sc, SDMMC_CDETECT) == 0 ? true : false);
423 }
424 }
425
426 /* Ack interrupts */
427 WRITE4(sc, SDMMC_RINTSTS, reg);
428
429 if (sc->use_pio) {
430 if (reg & (SDMMC_INTMASK_RXDR|SDMMC_INTMASK_DTO)) {
431 pio_read(sc, cmd);
432 }
433 if (reg & (SDMMC_INTMASK_TXDR|SDMMC_INTMASK_DTO)) {
434 pio_write(sc, cmd);
435 }
436 } else {
437 /* Now handle DMA interrupts */
438 reg = READ4(sc, SDMMC_IDSTS);
439 if (reg) {
440 dprintf("dma intr 0x%08x\n", reg);
441 if (reg & (SDMMC_IDINTEN_TI | SDMMC_IDINTEN_RI)) {
442 WRITE4(sc, SDMMC_IDSTS, (SDMMC_IDINTEN_TI |
443 SDMMC_IDINTEN_RI));
444 WRITE4(sc, SDMMC_IDSTS, SDMMC_IDINTEN_NI);
445 dma_done(sc, cmd);
446 }
447 }
448 }
449
450 dwmmc_tasklet(sc);
451
452 DWMMC_UNLOCK(sc);
453 }
454
455 static void
dwmmc_handle_card_present(struct dwmmc_softc * sc,bool is_present)456 dwmmc_handle_card_present(struct dwmmc_softc *sc, bool is_present)
457 {
458 bool was_present;
459
460 if (dumping || SCHEDULER_STOPPED())
461 return;
462
463 was_present = sc->child != NULL;
464
465 if (!was_present && is_present) {
466 taskqueue_enqueue_timeout(taskqueue_bus,
467 &sc->card_delayed_task, -(hz / 2));
468 } else if (was_present && !is_present) {
469 taskqueue_enqueue(taskqueue_bus, &sc->card_task);
470 }
471 }
472
473 static void
dwmmc_card_task(void * arg,int pending __unused)474 dwmmc_card_task(void *arg, int pending __unused)
475 {
476 struct dwmmc_softc *sc = arg;
477
478 #ifdef MMCCAM
479 mmc_cam_sim_discover(&sc->mmc_sim);
480 #else
481 bus_topo_lock();
482 if (READ4(sc, SDMMC_CDETECT) == 0 ||
483 (sc->mmc_helper.props & MMC_PROP_BROKEN_CD)) {
484 if (sc->child == NULL) {
485 if (bootverbose)
486 device_printf(sc->dev, "Card inserted\n");
487
488 sc->child = device_add_child(sc->dev, "mmc", -1);
489 if (sc->child) {
490 device_set_ivars(sc->child, sc);
491 (void)device_probe_and_attach(sc->child);
492 }
493 }
494 } else {
495 /* Card isn't present, detach if necessary */
496 if (sc->child != NULL) {
497 if (bootverbose)
498 device_printf(sc->dev, "Card removed\n");
499
500 device_delete_child(sc->dev, sc->child);
501 sc->child = NULL;
502 }
503 }
504 bus_topo_unlock();
505 #endif /* MMCCAM */
506 }
507
508 static int
parse_fdt(struct dwmmc_softc * sc)509 parse_fdt(struct dwmmc_softc *sc)
510 {
511 pcell_t dts_value[3];
512 phandle_t node;
513 uint32_t bus_hz = 0;
514 int len;
515 int error;
516
517 if ((node = ofw_bus_get_node(sc->dev)) == -1)
518 return (ENXIO);
519
520 /* Set some defaults for freq and supported mode */
521 sc->host.f_min = 400000;
522 sc->host.f_max = 200000000;
523 sc->host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340;
524 sc->host.caps = MMC_CAP_HSPEED | MMC_CAP_SIGNALING_330;
525 mmc_fdt_parse(sc->dev, node, &sc->mmc_helper, &sc->host);
526
527 /* fifo-depth */
528 if ((len = OF_getproplen(node, "fifo-depth")) > 0) {
529 OF_getencprop(node, "fifo-depth", dts_value, len);
530 sc->fifo_depth = dts_value[0];
531 }
532
533 /* num-slots (Deprecated) */
534 sc->num_slots = 1;
535 if ((len = OF_getproplen(node, "num-slots")) > 0) {
536 device_printf(sc->dev, "num-slots property is deprecated\n");
537 OF_getencprop(node, "num-slots", dts_value, len);
538 sc->num_slots = dts_value[0];
539 }
540
541 /* clock-frequency */
542 if ((len = OF_getproplen(node, "clock-frequency")) > 0) {
543 OF_getencprop(node, "clock-frequency", dts_value, len);
544 bus_hz = dts_value[0];
545 }
546
547 /* IP block reset is optional */
548 error = hwreset_get_by_ofw_name(sc->dev, 0, "reset", &sc->hwreset);
549 if (error != 0 &&
550 error != ENOENT &&
551 error != ENODEV) {
552 device_printf(sc->dev, "Cannot get reset\n");
553 goto fail;
554 }
555
556 /* vmmc regulator is optional */
557 error = regulator_get_by_ofw_property(sc->dev, 0, "vmmc-supply",
558 &sc->vmmc);
559 if (error != 0 &&
560 error != ENOENT &&
561 error != ENODEV) {
562 device_printf(sc->dev, "Cannot get regulator 'vmmc-supply'\n");
563 goto fail;
564 }
565
566 /* vqmmc regulator is optional */
567 error = regulator_get_by_ofw_property(sc->dev, 0, "vqmmc-supply",
568 &sc->vqmmc);
569 if (error != 0 &&
570 error != ENOENT &&
571 error != ENODEV) {
572 device_printf(sc->dev, "Cannot get regulator 'vqmmc-supply'\n");
573 goto fail;
574 }
575
576 /* Assert reset first */
577 if (sc->hwreset != NULL) {
578 error = hwreset_assert(sc->hwreset);
579 if (error != 0) {
580 device_printf(sc->dev, "Cannot assert reset\n");
581 goto fail;
582 }
583 }
584
585 /* BIU (Bus Interface Unit clock) is optional */
586 error = clk_get_by_ofw_name(sc->dev, 0, "biu", &sc->biu);
587 if (error != 0 &&
588 error != ENOENT &&
589 error != ENODEV) {
590 device_printf(sc->dev, "Cannot get 'biu' clock\n");
591 goto fail;
592 }
593
594 if (sc->biu) {
595 error = clk_enable(sc->biu);
596 if (error != 0) {
597 device_printf(sc->dev, "cannot enable biu clock\n");
598 goto fail;
599 }
600 }
601
602 /*
603 * CIU (Controller Interface Unit clock) is mandatory
604 * if no clock-frequency property is given
605 */
606 error = clk_get_by_ofw_name(sc->dev, 0, "ciu", &sc->ciu);
607 if (error != 0 &&
608 error != ENOENT &&
609 error != ENODEV) {
610 device_printf(sc->dev, "Cannot get 'ciu' clock\n");
611 goto fail;
612 }
613
614 if (sc->ciu) {
615 if (bus_hz != 0) {
616 error = clk_set_freq(sc->ciu, bus_hz, 0);
617 if (error != 0)
618 device_printf(sc->dev,
619 "cannot set ciu clock to %u\n", bus_hz);
620 }
621 error = clk_enable(sc->ciu);
622 if (error != 0) {
623 device_printf(sc->dev, "cannot enable ciu clock\n");
624 goto fail;
625 }
626 clk_get_freq(sc->ciu, &sc->bus_hz);
627 }
628
629 /* Enable regulators */
630 if (sc->vmmc != NULL) {
631 error = regulator_enable(sc->vmmc);
632 if (error != 0) {
633 device_printf(sc->dev, "Cannot enable vmmc regulator\n");
634 goto fail;
635 }
636 }
637 if (sc->vqmmc != NULL) {
638 error = regulator_enable(sc->vqmmc);
639 if (error != 0) {
640 device_printf(sc->dev, "Cannot enable vqmmc regulator\n");
641 goto fail;
642 }
643 }
644
645 /* Take dwmmc out of reset */
646 if (sc->hwreset != NULL) {
647 error = hwreset_deassert(sc->hwreset);
648 if (error != 0) {
649 device_printf(sc->dev, "Cannot deassert reset\n");
650 goto fail;
651 }
652 }
653
654 if (sc->bus_hz == 0) {
655 device_printf(sc->dev, "No bus speed provided\n");
656 goto fail;
657 }
658
659 return (0);
660
661 fail:
662 return (ENXIO);
663 }
664
665 int
dwmmc_attach(device_t dev)666 dwmmc_attach(device_t dev)
667 {
668 struct dwmmc_softc *sc;
669 int error;
670
671 sc = device_get_softc(dev);
672
673 sc->dev = dev;
674
675 /* Why not to use Auto Stop? It save a hundred of irq per second */
676 sc->use_auto_stop = 1;
677
678 error = parse_fdt(sc);
679 if (error != 0) {
680 device_printf(dev, "Can't get FDT property.\n");
681 return (ENXIO);
682 }
683
684 DWMMC_LOCK_INIT(sc);
685
686 if (bus_alloc_resources(dev, dwmmc_spec, sc->res)) {
687 device_printf(dev, "could not allocate resources\n");
688 return (ENXIO);
689 }
690
691 /* Setup interrupt handler. */
692 error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_NET | INTR_MPSAFE,
693 NULL, dwmmc_intr, sc, &sc->intr_cookie);
694 if (error != 0) {
695 device_printf(dev, "could not setup interrupt handler.\n");
696 return (ENXIO);
697 }
698
699 device_printf(dev, "Hardware version ID is %04x\n",
700 READ4(sc, SDMMC_VERID) & 0xffff);
701
702 /* Reset all */
703 if (dwmmc_ctrl_reset(sc, (SDMMC_CTRL_RESET |
704 SDMMC_CTRL_FIFO_RESET |
705 SDMMC_CTRL_DMA_RESET)))
706 return (ENXIO);
707
708 dwmmc_setup_bus(sc, sc->host.f_min);
709
710 if (sc->fifo_depth == 0) {
711 sc->fifo_depth = 1 +
712 ((READ4(sc, SDMMC_FIFOTH) >> SDMMC_FIFOTH_RXWMARK_S) & 0xfff);
713 device_printf(dev, "No fifo-depth, using FIFOTH %x\n",
714 sc->fifo_depth);
715 }
716
717 if (!sc->use_pio) {
718 dma_stop(sc);
719 if (dma_setup(sc))
720 return (ENXIO);
721
722 /* Install desc base */
723 WRITE4(sc, SDMMC_DBADDR, sc->desc_ring_paddr);
724
725 /* Enable DMA interrupts */
726 WRITE4(sc, SDMMC_IDSTS, SDMMC_IDINTEN_MASK);
727 WRITE4(sc, SDMMC_IDINTEN, (SDMMC_IDINTEN_NI |
728 SDMMC_IDINTEN_RI |
729 SDMMC_IDINTEN_TI));
730 }
731
732 /* Clear and disable interrups for a while */
733 WRITE4(sc, SDMMC_RINTSTS, 0xffffffff);
734 WRITE4(sc, SDMMC_INTMASK, 0);
735
736 /* Maximum timeout */
737 WRITE4(sc, SDMMC_TMOUT, 0xffffffff);
738
739 /* Enable interrupts */
740 WRITE4(sc, SDMMC_RINTSTS, 0xffffffff);
741 WRITE4(sc, SDMMC_INTMASK, (SDMMC_INTMASK_CMD_DONE |
742 SDMMC_INTMASK_DTO |
743 SDMMC_INTMASK_ACD |
744 SDMMC_INTMASK_TXDR |
745 SDMMC_INTMASK_RXDR |
746 DWMMC_ERR_FLAGS |
747 SDMMC_INTMASK_CD));
748 WRITE4(sc, SDMMC_CTRL, SDMMC_CTRL_INT_ENABLE);
749
750 TASK_INIT(&sc->card_task, 0, dwmmc_card_task, sc);
751 TIMEOUT_TASK_INIT(taskqueue_bus, &sc->card_delayed_task, 0,
752 dwmmc_card_task, sc);
753
754 #ifdef MMCCAM
755 sc->ccb = NULL;
756 if (mmc_cam_sim_alloc(dev, "dw_mmc", &sc->mmc_sim) != 0) {
757 device_printf(dev, "cannot alloc cam sim\n");
758 dwmmc_detach(dev);
759 return (ENXIO);
760 }
761 #endif
762 /*
763 * Schedule a card detection as we won't get an interrupt
764 * if the card is inserted when we attach
765 */
766 dwmmc_card_task(sc, 0);
767 return (0);
768 }
769
770 int
dwmmc_detach(device_t dev)771 dwmmc_detach(device_t dev)
772 {
773 struct dwmmc_softc *sc;
774 int ret;
775
776 sc = device_get_softc(dev);
777
778 ret = device_delete_children(dev);
779 if (ret != 0)
780 return (ret);
781
782 taskqueue_drain(taskqueue_bus, &sc->card_task);
783 taskqueue_drain_timeout(taskqueue_bus, &sc->card_delayed_task);
784
785 if (sc->intr_cookie != NULL) {
786 ret = bus_teardown_intr(dev, sc->res[1], sc->intr_cookie);
787 if (ret != 0)
788 return (ret);
789 }
790 bus_release_resources(dev, dwmmc_spec, sc->res);
791
792 DWMMC_LOCK_DESTROY(sc);
793
794 if (sc->hwreset != NULL && hwreset_deassert(sc->hwreset) != 0)
795 device_printf(sc->dev, "cannot deassert reset\n");
796 if (sc->biu != NULL && clk_disable(sc->biu) != 0)
797 device_printf(sc->dev, "cannot disable biu clock\n");
798 if (sc->ciu != NULL && clk_disable(sc->ciu) != 0)
799 device_printf(sc->dev, "cannot disable ciu clock\n");
800
801 if (sc->vmmc && regulator_disable(sc->vmmc) != 0)
802 device_printf(sc->dev, "Cannot disable vmmc regulator\n");
803 if (sc->vqmmc && regulator_disable(sc->vqmmc) != 0)
804 device_printf(sc->dev, "Cannot disable vqmmc regulator\n");
805
806 #ifdef MMCCAM
807 mmc_cam_sim_free(&sc->mmc_sim);
808 #endif
809
810 return (0);
811 }
812
813 static int
dwmmc_setup_bus(struct dwmmc_softc * sc,int freq)814 dwmmc_setup_bus(struct dwmmc_softc *sc, int freq)
815 {
816 int tout;
817 int div;
818
819 if (freq == 0) {
820 WRITE4(sc, SDMMC_CLKENA, 0);
821 WRITE4(sc, SDMMC_CMD, (SDMMC_CMD_WAIT_PRVDATA |
822 SDMMC_CMD_UPD_CLK_ONLY | SDMMC_CMD_START));
823
824 tout = 1000;
825 do {
826 if (tout-- < 0) {
827 device_printf(sc->dev, "Failed update clk\n");
828 return (1);
829 }
830 } while (READ4(sc, SDMMC_CMD) & SDMMC_CMD_START);
831
832 return (0);
833 }
834
835 WRITE4(sc, SDMMC_CLKENA, 0);
836 WRITE4(sc, SDMMC_CLKSRC, 0);
837
838 div = (sc->bus_hz != freq) ? DIV_ROUND_UP(sc->bus_hz, 2 * freq) : 0;
839
840 WRITE4(sc, SDMMC_CLKDIV, div);
841 WRITE4(sc, SDMMC_CMD, (SDMMC_CMD_WAIT_PRVDATA |
842 SDMMC_CMD_UPD_CLK_ONLY | SDMMC_CMD_START));
843
844 tout = 1000;
845 do {
846 if (tout-- < 0) {
847 device_printf(sc->dev, "Failed to update clk\n");
848 return (1);
849 }
850 } while (READ4(sc, SDMMC_CMD) & SDMMC_CMD_START);
851
852 WRITE4(sc, SDMMC_CLKENA, (SDMMC_CLKENA_CCLK_EN | SDMMC_CLKENA_LP));
853 WRITE4(sc, SDMMC_CMD, SDMMC_CMD_WAIT_PRVDATA |
854 SDMMC_CMD_UPD_CLK_ONLY | SDMMC_CMD_START);
855
856 tout = 1000;
857 do {
858 if (tout-- < 0) {
859 device_printf(sc->dev, "Failed to enable clk\n");
860 return (1);
861 }
862 } while (READ4(sc, SDMMC_CMD) & SDMMC_CMD_START);
863
864 return (0);
865 }
866
867 static int
dwmmc_update_ios(device_t brdev,device_t reqdev)868 dwmmc_update_ios(device_t brdev, device_t reqdev)
869 {
870 struct dwmmc_softc *sc;
871 struct mmc_ios *ios;
872 uint32_t reg;
873 int ret = 0;
874
875 sc = device_get_softc(brdev);
876 ios = &sc->host.ios;
877
878 dprintf("Setting up clk %u bus_width %d, timing: %d\n",
879 ios->clock, ios->bus_width, ios->timing);
880
881 switch (ios->power_mode) {
882 case power_on:
883 break;
884 case power_off:
885 WRITE4(sc, SDMMC_PWREN, 0);
886 break;
887 case power_up:
888 WRITE4(sc, SDMMC_PWREN, 1);
889 break;
890 }
891
892 mmc_fdt_set_power(&sc->mmc_helper, ios->power_mode);
893
894 if (ios->bus_width == bus_width_8)
895 WRITE4(sc, SDMMC_CTYPE, SDMMC_CTYPE_8BIT);
896 else if (ios->bus_width == bus_width_4)
897 WRITE4(sc, SDMMC_CTYPE, SDMMC_CTYPE_4BIT);
898 else
899 WRITE4(sc, SDMMC_CTYPE, 0);
900
901 if ((sc->hwtype & HWTYPE_MASK) == HWTYPE_EXYNOS) {
902 /* XXX: take care about DDR or SDR use here */
903 WRITE4(sc, SDMMC_CLKSEL, sc->sdr_timing);
904 }
905
906 /* Set DDR mode */
907 reg = READ4(sc, SDMMC_UHS_REG);
908 if (ios->timing == bus_timing_uhs_ddr50 ||
909 ios->timing == bus_timing_mmc_ddr52 ||
910 ios->timing == bus_timing_mmc_hs400)
911 reg |= (SDMMC_UHS_REG_DDR);
912 else
913 reg &= ~(SDMMC_UHS_REG_DDR);
914 WRITE4(sc, SDMMC_UHS_REG, reg);
915
916 if (sc->update_ios)
917 ret = sc->update_ios(sc, ios);
918
919 dwmmc_setup_bus(sc, ios->clock);
920
921 return (ret);
922 }
923
924 static int
dma_done(struct dwmmc_softc * sc,struct mmc_command * cmd)925 dma_done(struct dwmmc_softc *sc, struct mmc_command *cmd)
926 {
927 struct mmc_data *data;
928
929 data = cmd->data;
930
931 if (data->flags & MMC_DATA_WRITE)
932 bus_dmamap_sync(sc->buf_tag, sc->buf_map,
933 BUS_DMASYNC_POSTWRITE);
934 else
935 bus_dmamap_sync(sc->buf_tag, sc->buf_map,
936 BUS_DMASYNC_POSTREAD);
937
938 bus_dmamap_sync(sc->desc_tag, sc->desc_map,
939 BUS_DMASYNC_POSTWRITE);
940
941 bus_dmamap_unload(sc->buf_tag, sc->buf_map);
942
943 return (0);
944 }
945
946 static int
dma_stop(struct dwmmc_softc * sc)947 dma_stop(struct dwmmc_softc *sc)
948 {
949 int reg;
950
951 reg = READ4(sc, SDMMC_CTRL);
952 reg &= ~(SDMMC_CTRL_USE_IDMAC);
953 reg |= (SDMMC_CTRL_DMA_RESET);
954 WRITE4(sc, SDMMC_CTRL, reg);
955
956 reg = READ4(sc, SDMMC_BMOD);
957 reg &= ~(SDMMC_BMOD_DE | SDMMC_BMOD_FB);
958 reg |= (SDMMC_BMOD_SWR);
959 WRITE4(sc, SDMMC_BMOD, reg);
960
961 return (0);
962 }
963
964 static int
dma_prepare(struct dwmmc_softc * sc,struct mmc_command * cmd)965 dma_prepare(struct dwmmc_softc *sc, struct mmc_command *cmd)
966 {
967 struct mmc_data *data;
968 int err;
969 int reg;
970
971 data = cmd->data;
972
973 reg = READ4(sc, SDMMC_INTMASK);
974 reg &= ~(SDMMC_INTMASK_TXDR | SDMMC_INTMASK_RXDR);
975 WRITE4(sc, SDMMC_INTMASK, reg);
976 dprintf("%s: bus_dmamap_load size: %zu\n", __func__, data->len);
977 err = bus_dmamap_load(sc->buf_tag, sc->buf_map,
978 data->data, data->len, dwmmc_ring_setup,
979 sc, BUS_DMA_NOWAIT);
980 if (err != 0)
981 panic("dmamap_load failed\n");
982
983 /* Ensure the device can see the desc */
984 bus_dmamap_sync(sc->desc_tag, sc->desc_map,
985 BUS_DMASYNC_PREWRITE);
986
987 if (data->flags & MMC_DATA_WRITE)
988 bus_dmamap_sync(sc->buf_tag, sc->buf_map,
989 BUS_DMASYNC_PREWRITE);
990 else
991 bus_dmamap_sync(sc->buf_tag, sc->buf_map,
992 BUS_DMASYNC_PREREAD);
993
994 reg = (DEF_MSIZE << SDMMC_FIFOTH_MSIZE_S);
995 reg |= ((sc->fifo_depth / 2) - 1) << SDMMC_FIFOTH_RXWMARK_S;
996 reg |= (sc->fifo_depth / 2) << SDMMC_FIFOTH_TXWMARK_S;
997
998 WRITE4(sc, SDMMC_FIFOTH, reg);
999 wmb();
1000
1001 reg = READ4(sc, SDMMC_CTRL);
1002 reg |= (SDMMC_CTRL_USE_IDMAC | SDMMC_CTRL_DMA_ENABLE);
1003 WRITE4(sc, SDMMC_CTRL, reg);
1004 wmb();
1005
1006 reg = READ4(sc, SDMMC_BMOD);
1007 reg |= (SDMMC_BMOD_DE | SDMMC_BMOD_FB);
1008 WRITE4(sc, SDMMC_BMOD, reg);
1009
1010 /* Start */
1011 WRITE4(sc, SDMMC_PLDMND, 1);
1012
1013 return (0);
1014 }
1015
1016 static int
pio_prepare(struct dwmmc_softc * sc,struct mmc_command * cmd)1017 pio_prepare(struct dwmmc_softc *sc, struct mmc_command *cmd)
1018 {
1019 struct mmc_data *data;
1020 int reg;
1021
1022 data = cmd->data;
1023 data->xfer_len = 0;
1024
1025 reg = (DEF_MSIZE << SDMMC_FIFOTH_MSIZE_S);
1026 reg |= ((sc->fifo_depth / 2) - 1) << SDMMC_FIFOTH_RXWMARK_S;
1027 reg |= (sc->fifo_depth / 2) << SDMMC_FIFOTH_TXWMARK_S;
1028
1029 WRITE4(sc, SDMMC_FIFOTH, reg);
1030 wmb();
1031
1032 return (0);
1033 }
1034
1035 static void
pio_read(struct dwmmc_softc * sc,struct mmc_command * cmd)1036 pio_read(struct dwmmc_softc *sc, struct mmc_command *cmd)
1037 {
1038 struct mmc_data *data;
1039 uint32_t *p, status;
1040
1041 if (cmd == NULL || cmd->data == NULL)
1042 return;
1043
1044 data = cmd->data;
1045 if ((data->flags & MMC_DATA_READ) == 0)
1046 return;
1047
1048 KASSERT((data->xfer_len & 3) == 0, ("xfer_len not aligned"));
1049 p = (uint32_t *)data->data + (data->xfer_len >> 2);
1050
1051 while (data->xfer_len < data->len) {
1052 status = READ4(sc, SDMMC_STATUS);
1053 if (status & SDMMC_STATUS_FIFO_EMPTY)
1054 break;
1055 *p++ = READ4(sc, SDMMC_DATA);
1056 data->xfer_len += 4;
1057 }
1058
1059 WRITE4(sc, SDMMC_RINTSTS, SDMMC_INTMASK_RXDR);
1060 }
1061
1062 static void
pio_write(struct dwmmc_softc * sc,struct mmc_command * cmd)1063 pio_write(struct dwmmc_softc *sc, struct mmc_command *cmd)
1064 {
1065 struct mmc_data *data;
1066 uint32_t *p, status;
1067
1068 if (cmd == NULL || cmd->data == NULL)
1069 return;
1070
1071 data = cmd->data;
1072 if ((data->flags & MMC_DATA_WRITE) == 0)
1073 return;
1074
1075 KASSERT((data->xfer_len & 3) == 0, ("xfer_len not aligned"));
1076 p = (uint32_t *)data->data + (data->xfer_len >> 2);
1077
1078 while (data->xfer_len < data->len) {
1079 status = READ4(sc, SDMMC_STATUS);
1080 if (status & SDMMC_STATUS_FIFO_FULL)
1081 break;
1082 WRITE4(sc, SDMMC_DATA, *p++);
1083 data->xfer_len += 4;
1084 }
1085
1086 WRITE4(sc, SDMMC_RINTSTS, SDMMC_INTMASK_TXDR);
1087 }
1088
1089 static void
dwmmc_start_cmd(struct dwmmc_softc * sc,struct mmc_command * cmd)1090 dwmmc_start_cmd(struct dwmmc_softc *sc, struct mmc_command *cmd)
1091 {
1092 struct mmc_data *data;
1093 uint32_t blksz;
1094 uint32_t cmdr;
1095
1096 dprintf("%s\n", __func__);
1097 sc->curcmd = cmd;
1098 data = cmd->data;
1099
1100 #ifndef MMCCAM
1101 /* XXX Upper layers don't always set this */
1102 cmd->mrq = sc->req;
1103 #endif
1104 /* Begin setting up command register. */
1105
1106 cmdr = cmd->opcode;
1107
1108 dprintf("cmd->opcode 0x%08x\n", cmd->opcode);
1109
1110 if (cmd->opcode == MMC_STOP_TRANSMISSION ||
1111 cmd->opcode == MMC_GO_IDLE_STATE ||
1112 cmd->opcode == MMC_GO_INACTIVE_STATE)
1113 cmdr |= SDMMC_CMD_STOP_ABORT;
1114 else if (cmd->opcode != MMC_SEND_STATUS && data)
1115 cmdr |= SDMMC_CMD_WAIT_PRVDATA;
1116
1117 /* Set up response handling. */
1118 if (MMC_RSP(cmd->flags) != MMC_RSP_NONE) {
1119 cmdr |= SDMMC_CMD_RESP_EXP;
1120 if (cmd->flags & MMC_RSP_136)
1121 cmdr |= SDMMC_CMD_RESP_LONG;
1122 }
1123
1124 if (cmd->flags & MMC_RSP_CRC)
1125 cmdr |= SDMMC_CMD_RESP_CRC;
1126
1127 /*
1128 * XXX: Not all platforms want this.
1129 */
1130 cmdr |= SDMMC_CMD_USE_HOLD_REG;
1131
1132 if ((sc->flags & CARD_INIT_DONE) == 0) {
1133 sc->flags |= (CARD_INIT_DONE);
1134 cmdr |= SDMMC_CMD_SEND_INIT;
1135 }
1136
1137 if (data) {
1138 if ((cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK ||
1139 cmd->opcode == MMC_READ_MULTIPLE_BLOCK) &&
1140 sc->use_auto_stop)
1141 cmdr |= SDMMC_CMD_SEND_ASTOP;
1142
1143 cmdr |= SDMMC_CMD_DATA_EXP;
1144 if (data->flags & MMC_DATA_STREAM)
1145 cmdr |= SDMMC_CMD_MODE_STREAM;
1146 if (data->flags & MMC_DATA_WRITE)
1147 cmdr |= SDMMC_CMD_DATA_WRITE;
1148
1149 WRITE4(sc, SDMMC_TMOUT, 0xffffffff);
1150 #ifdef MMCCAM
1151 if (cmd->data->flags & MMC_DATA_BLOCK_SIZE) {
1152 WRITE4(sc, SDMMC_BLKSIZ, cmd->data->block_size);
1153 WRITE4(sc, SDMMC_BYTCNT, cmd->data->len);
1154 } else
1155 #endif
1156 {
1157 WRITE4(sc, SDMMC_BYTCNT, data->len);
1158 blksz = (data->len < MMC_SECTOR_SIZE) ? \
1159 data->len : MMC_SECTOR_SIZE;
1160 WRITE4(sc, SDMMC_BLKSIZ, blksz);
1161 }
1162
1163 if (sc->use_pio) {
1164 pio_prepare(sc, cmd);
1165 } else {
1166 dma_prepare(sc, cmd);
1167 }
1168 wmb();
1169 }
1170
1171 dprintf("cmdr 0x%08x\n", cmdr);
1172
1173 WRITE4(sc, SDMMC_CMDARG, cmd->arg);
1174 wmb();
1175 WRITE4(sc, SDMMC_CMD, cmdr | SDMMC_CMD_START);
1176 };
1177
1178 static void
dwmmc_next_operation(struct dwmmc_softc * sc)1179 dwmmc_next_operation(struct dwmmc_softc *sc)
1180 {
1181 struct mmc_command *cmd;
1182 dprintf("%s\n", __func__);
1183 #ifdef MMCCAM
1184 union ccb *ccb;
1185
1186 ccb = sc->ccb;
1187 if (ccb == NULL)
1188 return;
1189 cmd = &ccb->mmcio.cmd;
1190 #else
1191 struct mmc_request *req;
1192
1193 req = sc->req;
1194 if (req == NULL)
1195 return;
1196 cmd = req->cmd;
1197 #endif
1198
1199 sc->acd_rcvd = 0;
1200 sc->dto_rcvd = 0;
1201 sc->cmd_done = 0;
1202
1203 /*
1204 * XXX: Wait until card is still busy.
1205 * We do need this to prevent data timeouts,
1206 * mostly caused by multi-block write command
1207 * followed by single-read.
1208 */
1209 while(READ4(sc, SDMMC_STATUS) & (SDMMC_STATUS_DATA_BUSY))
1210 continue;
1211
1212 if (sc->flags & PENDING_CMD) {
1213 sc->flags &= ~PENDING_CMD;
1214 dwmmc_start_cmd(sc, cmd);
1215 return;
1216 } else if (sc->flags & PENDING_STOP && !sc->use_auto_stop) {
1217 sc->flags &= ~PENDING_STOP;
1218 /// XXX: What to do with this?
1219 //dwmmc_start_cmd(sc, req->stop);
1220 return;
1221 }
1222
1223 #ifdef MMCCAM
1224 sc->ccb = NULL;
1225 sc->curcmd = NULL;
1226 ccb->ccb_h.status =
1227 (ccb->mmcio.cmd.error == 0 ? CAM_REQ_CMP : CAM_REQ_CMP_ERR);
1228 xpt_done(ccb);
1229 #else
1230 sc->req = NULL;
1231 sc->curcmd = NULL;
1232 req->done(req);
1233 #endif
1234 }
1235
1236 static int
dwmmc_request(device_t brdev,device_t reqdev,struct mmc_request * req)1237 dwmmc_request(device_t brdev, device_t reqdev, struct mmc_request *req)
1238 {
1239 struct dwmmc_softc *sc;
1240
1241 sc = device_get_softc(brdev);
1242
1243 dprintf("%s\n", __func__);
1244
1245 DWMMC_LOCK(sc);
1246
1247 #ifdef MMCCAM
1248 sc->flags |= PENDING_CMD;
1249 #else
1250 if (sc->req != NULL) {
1251 DWMMC_UNLOCK(sc);
1252 return (EBUSY);
1253 }
1254
1255 sc->req = req;
1256 sc->flags |= PENDING_CMD;
1257 if (sc->req->stop)
1258 sc->flags |= PENDING_STOP;
1259 #endif
1260 dwmmc_next_operation(sc);
1261
1262 DWMMC_UNLOCK(sc);
1263 return (0);
1264 }
1265
1266 #ifndef MMCCAM
1267 static int
dwmmc_get_ro(device_t brdev,device_t reqdev)1268 dwmmc_get_ro(device_t brdev, device_t reqdev)
1269 {
1270
1271 dprintf("%s\n", __func__);
1272
1273 return (0);
1274 }
1275
1276 static int
dwmmc_acquire_host(device_t brdev,device_t reqdev)1277 dwmmc_acquire_host(device_t brdev, device_t reqdev)
1278 {
1279 struct dwmmc_softc *sc;
1280
1281 sc = device_get_softc(brdev);
1282
1283 DWMMC_LOCK(sc);
1284 while (sc->bus_busy)
1285 msleep(sc, &sc->sc_mtx, PZERO, "dwmmcah", hz / 5);
1286 sc->bus_busy++;
1287 DWMMC_UNLOCK(sc);
1288 return (0);
1289 }
1290
1291 static int
dwmmc_release_host(device_t brdev,device_t reqdev)1292 dwmmc_release_host(device_t brdev, device_t reqdev)
1293 {
1294 struct dwmmc_softc *sc;
1295
1296 sc = device_get_softc(brdev);
1297
1298 DWMMC_LOCK(sc);
1299 sc->bus_busy--;
1300 wakeup(sc);
1301 DWMMC_UNLOCK(sc);
1302 return (0);
1303 }
1304 #endif /* !MMCCAM */
1305
1306 static int
dwmmc_read_ivar(device_t bus,device_t child,int which,uintptr_t * result)1307 dwmmc_read_ivar(device_t bus, device_t child, int which, uintptr_t *result)
1308 {
1309 struct dwmmc_softc *sc;
1310
1311 sc = device_get_softc(bus);
1312
1313 switch (which) {
1314 default:
1315 return (EINVAL);
1316 case MMCBR_IVAR_BUS_MODE:
1317 *(int *)result = sc->host.ios.bus_mode;
1318 break;
1319 case MMCBR_IVAR_BUS_WIDTH:
1320 *(int *)result = sc->host.ios.bus_width;
1321 break;
1322 case MMCBR_IVAR_CHIP_SELECT:
1323 *(int *)result = sc->host.ios.chip_select;
1324 break;
1325 case MMCBR_IVAR_CLOCK:
1326 *(int *)result = sc->host.ios.clock;
1327 break;
1328 case MMCBR_IVAR_F_MIN:
1329 *(int *)result = sc->host.f_min;
1330 break;
1331 case MMCBR_IVAR_F_MAX:
1332 *(int *)result = sc->host.f_max;
1333 break;
1334 case MMCBR_IVAR_HOST_OCR:
1335 *(int *)result = sc->host.host_ocr;
1336 break;
1337 case MMCBR_IVAR_MODE:
1338 *(int *)result = sc->host.mode;
1339 break;
1340 case MMCBR_IVAR_OCR:
1341 *(int *)result = sc->host.ocr;
1342 break;
1343 case MMCBR_IVAR_POWER_MODE:
1344 *(int *)result = sc->host.ios.power_mode;
1345 break;
1346 case MMCBR_IVAR_VDD:
1347 *(int *)result = sc->host.ios.vdd;
1348 break;
1349 case MMCBR_IVAR_VCCQ:
1350 *(int *)result = sc->host.ios.vccq;
1351 break;
1352 case MMCBR_IVAR_CAPS:
1353 *(int *)result = sc->host.caps;
1354 break;
1355 case MMCBR_IVAR_MAX_DATA:
1356 *(int *)result = DWMMC_MAX_DATA;
1357 break;
1358 case MMCBR_IVAR_TIMING:
1359 *(int *)result = sc->host.ios.timing;
1360 break;
1361 }
1362 return (0);
1363 }
1364
1365 static int
dwmmc_write_ivar(device_t bus,device_t child,int which,uintptr_t value)1366 dwmmc_write_ivar(device_t bus, device_t child, int which, uintptr_t value)
1367 {
1368 struct dwmmc_softc *sc;
1369
1370 sc = device_get_softc(bus);
1371
1372 switch (which) {
1373 default:
1374 return (EINVAL);
1375 case MMCBR_IVAR_BUS_MODE:
1376 sc->host.ios.bus_mode = value;
1377 break;
1378 case MMCBR_IVAR_BUS_WIDTH:
1379 sc->host.ios.bus_width = value;
1380 break;
1381 case MMCBR_IVAR_CHIP_SELECT:
1382 sc->host.ios.chip_select = value;
1383 break;
1384 case MMCBR_IVAR_CLOCK:
1385 sc->host.ios.clock = value;
1386 break;
1387 case MMCBR_IVAR_MODE:
1388 sc->host.mode = value;
1389 break;
1390 case MMCBR_IVAR_OCR:
1391 sc->host.ocr = value;
1392 break;
1393 case MMCBR_IVAR_POWER_MODE:
1394 sc->host.ios.power_mode = value;
1395 break;
1396 case MMCBR_IVAR_VDD:
1397 sc->host.ios.vdd = value;
1398 break;
1399 case MMCBR_IVAR_TIMING:
1400 sc->host.ios.timing = value;
1401 break;
1402 case MMCBR_IVAR_VCCQ:
1403 sc->host.ios.vccq = value;
1404 break;
1405 /* These are read-only */
1406 case MMCBR_IVAR_CAPS:
1407 case MMCBR_IVAR_HOST_OCR:
1408 case MMCBR_IVAR_F_MIN:
1409 case MMCBR_IVAR_F_MAX:
1410 case MMCBR_IVAR_MAX_DATA:
1411 return (EINVAL);
1412 }
1413 return (0);
1414 }
1415
1416 #ifdef MMCCAM
1417 /* Note: this function likely belongs to the specific driver impl */
1418 static int
dwmmc_switch_vccq(device_t dev,device_t child)1419 dwmmc_switch_vccq(device_t dev, device_t child)
1420 {
1421 device_printf(dev, "This is a default impl of switch_vccq() that always fails\n");
1422 return EINVAL;
1423 }
1424
1425 static int
dwmmc_get_tran_settings(device_t dev,struct ccb_trans_settings_mmc * cts)1426 dwmmc_get_tran_settings(device_t dev, struct ccb_trans_settings_mmc *cts)
1427 {
1428 struct dwmmc_softc *sc;
1429
1430 sc = device_get_softc(dev);
1431
1432 cts->host_ocr = sc->host.host_ocr;
1433 cts->host_f_min = sc->host.f_min;
1434 cts->host_f_max = sc->host.f_max;
1435 cts->host_caps = sc->host.caps;
1436 cts->host_max_data = DWMMC_MAX_DATA;
1437 memcpy(&cts->ios, &sc->host.ios, sizeof(struct mmc_ios));
1438
1439 return (0);
1440 }
1441
1442 static int
dwmmc_set_tran_settings(device_t dev,struct ccb_trans_settings_mmc * cts)1443 dwmmc_set_tran_settings(device_t dev, struct ccb_trans_settings_mmc *cts)
1444 {
1445 struct dwmmc_softc *sc;
1446 struct mmc_ios *ios;
1447 struct mmc_ios *new_ios;
1448 int res;
1449
1450 sc = device_get_softc(dev);
1451 ios = &sc->host.ios;
1452
1453 new_ios = &cts->ios;
1454
1455 /* Update only requested fields */
1456 if (cts->ios_valid & MMC_CLK) {
1457 ios->clock = new_ios->clock;
1458 if (bootverbose)
1459 device_printf(sc->dev, "Clock => %d\n", ios->clock);
1460 }
1461 if (cts->ios_valid & MMC_VDD) {
1462 ios->vdd = new_ios->vdd;
1463 if (bootverbose)
1464 device_printf(sc->dev, "VDD => %d\n", ios->vdd);
1465 }
1466 if (cts->ios_valid & MMC_CS) {
1467 ios->chip_select = new_ios->chip_select;
1468 if (bootverbose)
1469 device_printf(sc->dev, "CS => %d\n", ios->chip_select);
1470 }
1471 if (cts->ios_valid & MMC_BW) {
1472 ios->bus_width = new_ios->bus_width;
1473 if (bootverbose)
1474 device_printf(sc->dev, "Bus width => %d\n", ios->bus_width);
1475 }
1476 if (cts->ios_valid & MMC_PM) {
1477 ios->power_mode = new_ios->power_mode;
1478 if (bootverbose)
1479 device_printf(sc->dev, "Power mode => %d\n", ios->power_mode);
1480 }
1481 if (cts->ios_valid & MMC_BT) {
1482 ios->timing = new_ios->timing;
1483 if (bootverbose)
1484 device_printf(sc->dev, "Timing => %d\n", ios->timing);
1485 }
1486 if (cts->ios_valid & MMC_BM) {
1487 ios->bus_mode = new_ios->bus_mode;
1488 if (bootverbose)
1489 device_printf(sc->dev, "Bus mode => %d\n", ios->bus_mode);
1490 }
1491 if (cts->ios_valid & MMC_VCCQ) {
1492 ios->vccq = new_ios->vccq;
1493 if (bootverbose)
1494 device_printf(sc->dev, "VCCQ => %d\n", ios->vccq);
1495 res = dwmmc_switch_vccq(sc->dev, NULL);
1496 device_printf(sc->dev, "VCCQ switch result: %d\n", res);
1497 }
1498
1499 return (dwmmc_update_ios(sc->dev, NULL));
1500 }
1501
1502 static int
dwmmc_cam_request(device_t dev,union ccb * ccb)1503 dwmmc_cam_request(device_t dev, union ccb *ccb)
1504 {
1505 struct dwmmc_softc *sc;
1506 struct ccb_mmcio *mmcio;
1507
1508 sc = device_get_softc(dev);
1509 mmcio = &ccb->mmcio;
1510
1511 DWMMC_LOCK(sc);
1512
1513 #ifdef DEBUG
1514 if (__predict_false(bootverbose)) {
1515 device_printf(sc->dev, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n",
1516 mmcio->cmd.opcode, mmcio->cmd.arg, mmcio->cmd.flags,
1517 mmcio->cmd.data != NULL ? (unsigned int) mmcio->cmd.data->len : 0,
1518 mmcio->cmd.data != NULL ? mmcio->cmd.data->flags: 0);
1519 }
1520 #endif
1521 if (mmcio->cmd.data != NULL) {
1522 if (mmcio->cmd.data->len == 0 || mmcio->cmd.data->flags == 0)
1523 panic("data->len = %d, data->flags = %d -- something is b0rked",
1524 (int)mmcio->cmd.data->len, mmcio->cmd.data->flags);
1525 }
1526 if (sc->ccb != NULL) {
1527 device_printf(sc->dev, "Controller still has an active command\n");
1528 return (EBUSY);
1529 }
1530 sc->ccb = ccb;
1531 DWMMC_UNLOCK(sc);
1532 dwmmc_request(sc->dev, NULL, NULL);
1533
1534 return (0);
1535 }
1536
1537 static void
dwmmc_cam_poll(device_t dev)1538 dwmmc_cam_poll(device_t dev)
1539 {
1540 struct dwmmc_softc *sc;
1541
1542 sc = device_get_softc(dev);
1543 dwmmc_intr(sc);
1544 }
1545 #endif /* MMCCAM */
1546
1547 static device_method_t dwmmc_methods[] = {
1548 /* Bus interface */
1549 DEVMETHOD(bus_read_ivar, dwmmc_read_ivar),
1550 DEVMETHOD(bus_write_ivar, dwmmc_write_ivar),
1551
1552 #ifndef MMCCAM
1553 /* mmcbr_if */
1554 DEVMETHOD(mmcbr_update_ios, dwmmc_update_ios),
1555 DEVMETHOD(mmcbr_request, dwmmc_request),
1556 DEVMETHOD(mmcbr_get_ro, dwmmc_get_ro),
1557 DEVMETHOD(mmcbr_acquire_host, dwmmc_acquire_host),
1558 DEVMETHOD(mmcbr_release_host, dwmmc_release_host),
1559 #endif
1560
1561 #ifdef MMCCAM
1562 /* MMCCAM interface */
1563 DEVMETHOD(mmc_sim_get_tran_settings, dwmmc_get_tran_settings),
1564 DEVMETHOD(mmc_sim_set_tran_settings, dwmmc_set_tran_settings),
1565 DEVMETHOD(mmc_sim_cam_request, dwmmc_cam_request),
1566 DEVMETHOD(mmc_sim_cam_poll, dwmmc_cam_poll),
1567
1568 DEVMETHOD(bus_add_child, bus_generic_add_child),
1569 #endif
1570
1571 DEVMETHOD_END
1572 };
1573
1574 DEFINE_CLASS_0(dwmmc, dwmmc_driver, dwmmc_methods,
1575 sizeof(struct dwmmc_softc));
1576