1 /*
2 * Copyright © 2009 Keith Packard
3 *
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
13 *
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THIS SOFTWARE.
21 */
22
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/delay.h>
26 #include <linux/init.h>
27 #include <linux/errno.h>
28 #include <linux/sched.h>
29 #include <linux/i2c.h>
30 #include <linux/seq_file.h>
31 #include <drm/drm_dp_helper.h>
32 #include <drm/drmP.h>
33
34 #include "drm_crtc_helper_internal.h"
35
36 /**
37 * DOC: dp helpers
38 *
39 * These functions contain some common logic and helpers at various abstraction
40 * levels to deal with Display Port sink devices and related things like DP aux
41 * channel transfers, EDID reading over DP aux channels, decoding certain DPCD
42 * blocks, ...
43 */
44
45 /* Helpers for DP link training */
dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE],int r)46 static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r)
47 {
48 return link_status[r - DP_LANE0_1_STATUS];
49 }
50
dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE],int lane)51 static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE],
52 int lane)
53 {
54 int i = DP_LANE0_1_STATUS + (lane >> 1);
55 int s = (lane & 1) * 4;
56 u8 l = dp_link_status(link_status, i);
57 return (l >> s) & 0xf;
58 }
59
drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],int lane_count)60 bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
61 int lane_count)
62 {
63 u8 lane_align;
64 u8 lane_status;
65 int lane;
66
67 lane_align = dp_link_status(link_status,
68 DP_LANE_ALIGN_STATUS_UPDATED);
69 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
70 return false;
71 for (lane = 0; lane < lane_count; lane++) {
72 lane_status = dp_get_lane_status(link_status, lane);
73 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
74 return false;
75 }
76 return true;
77 }
78 EXPORT_SYMBOL(drm_dp_channel_eq_ok);
79
drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],int lane_count)80 bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
81 int lane_count)
82 {
83 int lane;
84 u8 lane_status;
85
86 for (lane = 0; lane < lane_count; lane++) {
87 lane_status = dp_get_lane_status(link_status, lane);
88 if ((lane_status & DP_LANE_CR_DONE) == 0)
89 return false;
90 }
91 return true;
92 }
93 EXPORT_SYMBOL(drm_dp_clock_recovery_ok);
94
drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],int lane)95 u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
96 int lane)
97 {
98 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
99 int s = ((lane & 1) ?
100 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
101 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
102 u8 l = dp_link_status(link_status, i);
103
104 return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
105 }
106 EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage);
107
drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],int lane)108 u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
109 int lane)
110 {
111 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
112 int s = ((lane & 1) ?
113 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
114 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
115 u8 l = dp_link_status(link_status, i);
116
117 return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
118 }
119 EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);
120
drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])121 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
122 if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
123 udelay(100);
124 else
125 mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
126 }
127 EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
128
drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])129 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
130 if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
131 udelay(400);
132 else
133 mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
134 }
135 EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
136
drm_dp_link_rate_to_bw_code(int link_rate)137 u8 drm_dp_link_rate_to_bw_code(int link_rate)
138 {
139 switch (link_rate) {
140 default:
141 WARN(1, "unknown DP link rate %d, using %x\n", link_rate,
142 DP_LINK_BW_1_62);
143 case 162000:
144 return DP_LINK_BW_1_62;
145 case 270000:
146 return DP_LINK_BW_2_7;
147 case 540000:
148 return DP_LINK_BW_5_4;
149 }
150 }
151 EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code);
152
drm_dp_bw_code_to_link_rate(u8 link_bw)153 int drm_dp_bw_code_to_link_rate(u8 link_bw)
154 {
155 switch (link_bw) {
156 default:
157 WARN(1, "unknown DP link BW code %x, using 162000\n", link_bw);
158 case DP_LINK_BW_1_62:
159 return 162000;
160 case DP_LINK_BW_2_7:
161 return 270000;
162 case DP_LINK_BW_5_4:
163 return 540000;
164 }
165 }
166 EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate);
167
168 #define AUX_RETRY_INTERVAL 500 /* us */
169
170 /**
171 * DOC: dp helpers
172 *
173 * The DisplayPort AUX channel is an abstraction to allow generic, driver-
174 * independent access to AUX functionality. Drivers can take advantage of
175 * this by filling in the fields of the drm_dp_aux structure.
176 *
177 * Transactions are described using a hardware-independent drm_dp_aux_msg
178 * structure, which is passed into a driver's .transfer() implementation.
179 * Both native and I2C-over-AUX transactions are supported.
180 */
181
drm_dp_dpcd_access(struct drm_dp_aux * aux,u8 request,unsigned int offset,void * buffer,size_t size)182 static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request,
183 unsigned int offset, void *buffer, size_t size)
184 {
185 struct drm_dp_aux_msg msg;
186 unsigned int retry, native_reply;
187 int err = 0, ret = 0;
188
189 memset(&msg, 0, sizeof(msg));
190 msg.address = offset;
191 msg.request = request;
192 msg.buffer = buffer;
193 msg.size = size;
194
195 mutex_lock(&aux->hw_mutex);
196
197 /*
198 * The specification doesn't give any recommendation on how often to
199 * retry native transactions. We used to retry 7 times like for
200 * aux i2c transactions but real world devices this wasn't
201 * sufficient, bump to 32 which makes Dell 4k monitors happier.
202 */
203 for (retry = 0; retry < 32; retry++) {
204 if (ret != 0 && ret != -ETIMEDOUT) {
205 usleep_range(AUX_RETRY_INTERVAL,
206 AUX_RETRY_INTERVAL + 100);
207 }
208
209 ret = aux->transfer(aux, &msg);
210
211 if (ret >= 0) {
212 native_reply = msg.reply & DP_AUX_NATIVE_REPLY_MASK;
213 if (native_reply == DP_AUX_NATIVE_REPLY_ACK) {
214 if (ret == size)
215 goto unlock;
216
217 ret = -EPROTO;
218 } else
219 ret = -EIO;
220 }
221
222 /*
223 * We want the error we return to be the error we received on
224 * the first transaction, since we may get a different error the
225 * next time we retry
226 */
227 if (!err)
228 err = ret;
229 }
230
231 DRM_DEBUG_KMS("Too many retries, giving up. First error: %d\n", err);
232 ret = err;
233
234 unlock:
235 mutex_unlock(&aux->hw_mutex);
236 return ret;
237 }
238
239 /**
240 * drm_dp_dpcd_read() - read a series of bytes from the DPCD
241 * @aux: DisplayPort AUX channel
242 * @offset: address of the (first) register to read
243 * @buffer: buffer to store the register values
244 * @size: number of bytes in @buffer
245 *
246 * Returns the number of bytes transferred on success, or a negative error
247 * code on failure. -EIO is returned if the request was NAKed by the sink or
248 * if the retry count was exceeded. If not all bytes were transferred, this
249 * function returns -EPROTO. Errors from the underlying AUX channel transfer
250 * function, with the exception of -EBUSY (which causes the transaction to
251 * be retried), are propagated to the caller.
252 */
drm_dp_dpcd_read(struct drm_dp_aux * aux,unsigned int offset,void * buffer,size_t size)253 ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
254 void *buffer, size_t size)
255 {
256 int ret;
257
258 /*
259 * HP ZR24w corrupts the first DPCD access after entering power save
260 * mode. Eg. on a read, the entire buffer will be filled with the same
261 * byte. Do a throw away read to avoid corrupting anything we care
262 * about. Afterwards things will work correctly until the monitor
263 * gets woken up and subsequently re-enters power save mode.
264 *
265 * The user pressing any button on the monitor is enough to wake it
266 * up, so there is no particularly good place to do the workaround.
267 * We just have to do it before any DPCD access and hope that the
268 * monitor doesn't power down exactly after the throw away read.
269 */
270 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, DP_DPCD_REV, buffer,
271 1);
272 if (ret != 1)
273 return ret;
274
275 return drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset, buffer,
276 size);
277 }
278 EXPORT_SYMBOL(drm_dp_dpcd_read);
279
280 /**
281 * drm_dp_dpcd_write() - write a series of bytes to the DPCD
282 * @aux: DisplayPort AUX channel
283 * @offset: address of the (first) register to write
284 * @buffer: buffer containing the values to write
285 * @size: number of bytes in @buffer
286 *
287 * Returns the number of bytes transferred on success, or a negative error
288 * code on failure. -EIO is returned if the request was NAKed by the sink or
289 * if the retry count was exceeded. If not all bytes were transferred, this
290 * function returns -EPROTO. Errors from the underlying AUX channel transfer
291 * function, with the exception of -EBUSY (which causes the transaction to
292 * be retried), are propagated to the caller.
293 */
drm_dp_dpcd_write(struct drm_dp_aux * aux,unsigned int offset,void * buffer,size_t size)294 ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
295 void *buffer, size_t size)
296 {
297 return drm_dp_dpcd_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer,
298 size);
299 }
300 EXPORT_SYMBOL(drm_dp_dpcd_write);
301
302 /**
303 * drm_dp_dpcd_read_link_status() - read DPCD link status (bytes 0x202-0x207)
304 * @aux: DisplayPort AUX channel
305 * @status: buffer to store the link status in (must be at least 6 bytes)
306 *
307 * Returns the number of bytes transferred on success or a negative error
308 * code on failure.
309 */
drm_dp_dpcd_read_link_status(struct drm_dp_aux * aux,u8 status[DP_LINK_STATUS_SIZE])310 int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
311 u8 status[DP_LINK_STATUS_SIZE])
312 {
313 return drm_dp_dpcd_read(aux, DP_LANE0_1_STATUS, status,
314 DP_LINK_STATUS_SIZE);
315 }
316 EXPORT_SYMBOL(drm_dp_dpcd_read_link_status);
317
318 /**
319 * drm_dp_link_probe() - probe a DisplayPort link for capabilities
320 * @aux: DisplayPort AUX channel
321 * @link: pointer to structure in which to return link capabilities
322 *
323 * The structure filled in by this function can usually be passed directly
324 * into drm_dp_link_power_up() and drm_dp_link_configure() to power up and
325 * configure the link based on the link's capabilities.
326 *
327 * Returns 0 on success or a negative error code on failure.
328 */
drm_dp_link_probe(struct drm_dp_aux * aux,struct drm_dp_link * link)329 int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link)
330 {
331 u8 values[3];
332 int err;
333
334 memset(link, 0, sizeof(*link));
335
336 err = drm_dp_dpcd_read(aux, DP_DPCD_REV, values, sizeof(values));
337 if (err < 0)
338 return err;
339
340 link->revision = values[0];
341 link->rate = drm_dp_bw_code_to_link_rate(values[1]);
342 link->num_lanes = values[2] & DP_MAX_LANE_COUNT_MASK;
343
344 if (values[2] & DP_ENHANCED_FRAME_CAP)
345 link->capabilities |= DP_LINK_CAP_ENHANCED_FRAMING;
346
347 return 0;
348 }
349 EXPORT_SYMBOL(drm_dp_link_probe);
350
351 /**
352 * drm_dp_link_power_up() - power up a DisplayPort link
353 * @aux: DisplayPort AUX channel
354 * @link: pointer to a structure containing the link configuration
355 *
356 * Returns 0 on success or a negative error code on failure.
357 */
drm_dp_link_power_up(struct drm_dp_aux * aux,struct drm_dp_link * link)358 int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link)
359 {
360 u8 value;
361 int err;
362
363 /* DP_SET_POWER register is only available on DPCD v1.1 and later */
364 if (link->revision < 0x11)
365 return 0;
366
367 err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value);
368 if (err < 0)
369 return err;
370
371 value &= ~DP_SET_POWER_MASK;
372 value |= DP_SET_POWER_D0;
373
374 err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value);
375 if (err < 0)
376 return err;
377
378 /*
379 * According to the DP 1.1 specification, a "Sink Device must exit the
380 * power saving state within 1 ms" (Section 2.5.3.1, Table 5-52, "Sink
381 * Control Field" (register 0x600).
382 */
383 usleep_range(1000, 2000);
384
385 return 0;
386 }
387 EXPORT_SYMBOL(drm_dp_link_power_up);
388
389 /**
390 * drm_dp_link_power_down() - power down a DisplayPort link
391 * @aux: DisplayPort AUX channel
392 * @link: pointer to a structure containing the link configuration
393 *
394 * Returns 0 on success or a negative error code on failure.
395 */
drm_dp_link_power_down(struct drm_dp_aux * aux,struct drm_dp_link * link)396 int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link)
397 {
398 u8 value;
399 int err;
400
401 /* DP_SET_POWER register is only available on DPCD v1.1 and later */
402 if (link->revision < 0x11)
403 return 0;
404
405 err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value);
406 if (err < 0)
407 return err;
408
409 value &= ~DP_SET_POWER_MASK;
410 value |= DP_SET_POWER_D3;
411
412 err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value);
413 if (err < 0)
414 return err;
415
416 return 0;
417 }
418 EXPORT_SYMBOL(drm_dp_link_power_down);
419
420 /**
421 * drm_dp_link_configure() - configure a DisplayPort link
422 * @aux: DisplayPort AUX channel
423 * @link: pointer to a structure containing the link configuration
424 *
425 * Returns 0 on success or a negative error code on failure.
426 */
drm_dp_link_configure(struct drm_dp_aux * aux,struct drm_dp_link * link)427 int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link)
428 {
429 u8 values[2];
430 int err;
431
432 values[0] = drm_dp_link_rate_to_bw_code(link->rate);
433 values[1] = link->num_lanes;
434
435 if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
436 values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
437
438 err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values));
439 if (err < 0)
440 return err;
441
442 return 0;
443 }
444 EXPORT_SYMBOL(drm_dp_link_configure);
445
446 /**
447 * drm_dp_downstream_max_clock() - extract branch device max
448 * pixel rate for legacy VGA
449 * converter or max TMDS clock
450 * rate for others
451 * @dpcd: DisplayPort configuration data
452 * @port_cap: port capabilities
453 *
454 * Returns max clock in kHz on success or 0 if max clock not defined
455 */
drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],const u8 port_cap[4])456 int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
457 const u8 port_cap[4])
458 {
459 int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
460 bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
461 DP_DETAILED_CAP_INFO_AVAILABLE;
462
463 if (!detailed_cap_info)
464 return 0;
465
466 switch (type) {
467 case DP_DS_PORT_TYPE_VGA:
468 return port_cap[1] * 8 * 1000;
469 case DP_DS_PORT_TYPE_DVI:
470 case DP_DS_PORT_TYPE_HDMI:
471 case DP_DS_PORT_TYPE_DP_DUALMODE:
472 return port_cap[1] * 2500;
473 default:
474 return 0;
475 }
476 }
477 EXPORT_SYMBOL(drm_dp_downstream_max_clock);
478
479 /**
480 * drm_dp_downstream_max_bpc() - extract branch device max
481 * bits per component
482 * @dpcd: DisplayPort configuration data
483 * @port_cap: port capabilities
484 *
485 * Returns max bpc on success or 0 if max bpc not defined
486 */
drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],const u8 port_cap[4])487 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
488 const u8 port_cap[4])
489 {
490 int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
491 bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
492 DP_DETAILED_CAP_INFO_AVAILABLE;
493 int bpc;
494
495 if (!detailed_cap_info)
496 return 0;
497
498 switch (type) {
499 case DP_DS_PORT_TYPE_VGA:
500 case DP_DS_PORT_TYPE_DVI:
501 case DP_DS_PORT_TYPE_HDMI:
502 case DP_DS_PORT_TYPE_DP_DUALMODE:
503 bpc = port_cap[2] & DP_DS_MAX_BPC_MASK;
504
505 switch (bpc) {
506 case DP_DS_8BPC:
507 return 8;
508 case DP_DS_10BPC:
509 return 10;
510 case DP_DS_12BPC:
511 return 12;
512 case DP_DS_16BPC:
513 return 16;
514 }
515 default:
516 return 0;
517 }
518 }
519 EXPORT_SYMBOL(drm_dp_downstream_max_bpc);
520
521 /**
522 * drm_dp_downstream_id() - identify branch device
523 * @aux: DisplayPort AUX channel
524 * @id: DisplayPort branch device id
525 *
526 * Returns branch device id on success or NULL on failure
527 */
drm_dp_downstream_id(struct drm_dp_aux * aux,char id[6])528 int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6])
529 {
530 return drm_dp_dpcd_read(aux, DP_BRANCH_ID, id, 6);
531 }
532 EXPORT_SYMBOL(drm_dp_downstream_id);
533
534 /**
535 * drm_dp_downstream_debug() - debug DP branch devices
536 * @m: pointer for debugfs file
537 * @dpcd: DisplayPort configuration data
538 * @port_cap: port capabilities
539 * @aux: DisplayPort AUX channel
540 *
541 */
drm_dp_downstream_debug(struct seq_file * m,const u8 dpcd[DP_RECEIVER_CAP_SIZE],const u8 port_cap[4],struct drm_dp_aux * aux)542 void drm_dp_downstream_debug(struct seq_file *m,
543 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
544 const u8 port_cap[4], struct drm_dp_aux *aux)
545 {
546 bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
547 DP_DETAILED_CAP_INFO_AVAILABLE;
548 int clk;
549 int bpc;
550 char id[7];
551 int len;
552 uint8_t rev[2];
553 int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
554 bool branch_device = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
555 DP_DWN_STRM_PORT_PRESENT;
556
557 seq_printf(m, "\tDP branch device present: %s\n",
558 branch_device ? "yes" : "no");
559
560 if (!branch_device)
561 return;
562
563 switch (type) {
564 case DP_DS_PORT_TYPE_DP:
565 seq_puts(m, "\t\tType: DisplayPort\n");
566 break;
567 case DP_DS_PORT_TYPE_VGA:
568 seq_puts(m, "\t\tType: VGA\n");
569 break;
570 case DP_DS_PORT_TYPE_DVI:
571 seq_puts(m, "\t\tType: DVI\n");
572 break;
573 case DP_DS_PORT_TYPE_HDMI:
574 seq_puts(m, "\t\tType: HDMI\n");
575 break;
576 case DP_DS_PORT_TYPE_NON_EDID:
577 seq_puts(m, "\t\tType: others without EDID support\n");
578 break;
579 case DP_DS_PORT_TYPE_DP_DUALMODE:
580 seq_puts(m, "\t\tType: DP++\n");
581 break;
582 case DP_DS_PORT_TYPE_WIRELESS:
583 seq_puts(m, "\t\tType: Wireless\n");
584 break;
585 default:
586 seq_puts(m, "\t\tType: N/A\n");
587 }
588
589 memset(id, 0, sizeof(id));
590 drm_dp_downstream_id(aux, id);
591 seq_printf(m, "\t\tID: %s\n", id);
592
593 len = drm_dp_dpcd_read(aux, DP_BRANCH_HW_REV, &rev[0], 1);
594 if (len > 0)
595 seq_printf(m, "\t\tHW: %d.%d\n",
596 (rev[0] & 0xf0) >> 4, rev[0] & 0xf);
597
598 len = drm_dp_dpcd_read(aux, DP_BRANCH_SW_REV, rev, 2);
599 if (len > 0)
600 seq_printf(m, "\t\tSW: %d.%d\n", rev[0], rev[1]);
601
602 if (detailed_cap_info) {
603 clk = drm_dp_downstream_max_clock(dpcd, port_cap);
604
605 if (clk > 0) {
606 if (type == DP_DS_PORT_TYPE_VGA)
607 seq_printf(m, "\t\tMax dot clock: %d kHz\n", clk);
608 else
609 seq_printf(m, "\t\tMax TMDS clock: %d kHz\n", clk);
610 }
611
612 bpc = drm_dp_downstream_max_bpc(dpcd, port_cap);
613
614 if (bpc > 0)
615 seq_printf(m, "\t\tMax bpc: %d\n", bpc);
616 }
617 }
618 EXPORT_SYMBOL(drm_dp_downstream_debug);
619
620 /*
621 * I2C-over-AUX implementation
622 */
623
drm_dp_i2c_functionality(struct i2c_adapter * adapter)624 static u32 drm_dp_i2c_functionality(struct i2c_adapter *adapter)
625 {
626 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
627 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
628 I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
629 I2C_FUNC_10BIT_ADDR;
630 }
631
drm_dp_i2c_msg_write_status_update(struct drm_dp_aux_msg * msg)632 static void drm_dp_i2c_msg_write_status_update(struct drm_dp_aux_msg *msg)
633 {
634 /*
635 * In case of i2c defer or short i2c ack reply to a write,
636 * we need to switch to WRITE_STATUS_UPDATE to drain the
637 * rest of the message
638 */
639 if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE) {
640 msg->request &= DP_AUX_I2C_MOT;
641 msg->request |= DP_AUX_I2C_WRITE_STATUS_UPDATE;
642 }
643 }
644
645 #define AUX_PRECHARGE_LEN 10 /* 10 to 16 */
646 #define AUX_SYNC_LEN (16 + 4) /* preamble + AUX_SYNC_END */
647 #define AUX_STOP_LEN 4
648 #define AUX_CMD_LEN 4
649 #define AUX_ADDRESS_LEN 20
650 #define AUX_REPLY_PAD_LEN 4
651 #define AUX_LENGTH_LEN 8
652
653 /*
654 * Calculate the duration of the AUX request/reply in usec. Gives the
655 * "best" case estimate, ie. successful while as short as possible.
656 */
drm_dp_aux_req_duration(const struct drm_dp_aux_msg * msg)657 static int drm_dp_aux_req_duration(const struct drm_dp_aux_msg *msg)
658 {
659 int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN +
660 AUX_CMD_LEN + AUX_ADDRESS_LEN + AUX_LENGTH_LEN;
661
662 if ((msg->request & DP_AUX_I2C_READ) == 0)
663 len += msg->size * 8;
664
665 return len;
666 }
667
drm_dp_aux_reply_duration(const struct drm_dp_aux_msg * msg)668 static int drm_dp_aux_reply_duration(const struct drm_dp_aux_msg *msg)
669 {
670 int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN +
671 AUX_CMD_LEN + AUX_REPLY_PAD_LEN;
672
673 /*
674 * For read we expect what was asked. For writes there will
675 * be 0 or 1 data bytes. Assume 0 for the "best" case.
676 */
677 if (msg->request & DP_AUX_I2C_READ)
678 len += msg->size * 8;
679
680 return len;
681 }
682
683 #define I2C_START_LEN 1
684 #define I2C_STOP_LEN 1
685 #define I2C_ADDR_LEN 9 /* ADDRESS + R/W + ACK/NACK */
686 #define I2C_DATA_LEN 9 /* DATA + ACK/NACK */
687
688 /*
689 * Calculate the length of the i2c transfer in usec, assuming
690 * the i2c bus speed is as specified. Gives the the "worst"
691 * case estimate, ie. successful while as long as possible.
692 * Doesn't account the the "MOT" bit, and instead assumes each
693 * message includes a START, ADDRESS and STOP. Neither does it
694 * account for additional random variables such as clock stretching.
695 */
drm_dp_i2c_msg_duration(const struct drm_dp_aux_msg * msg,int i2c_speed_khz)696 static int drm_dp_i2c_msg_duration(const struct drm_dp_aux_msg *msg,
697 int i2c_speed_khz)
698 {
699 /* AUX bitrate is 1MHz, i2c bitrate as specified */
700 return DIV_ROUND_UP((I2C_START_LEN + I2C_ADDR_LEN +
701 msg->size * I2C_DATA_LEN +
702 I2C_STOP_LEN) * 1000, i2c_speed_khz);
703 }
704
705 /*
706 * Deterine how many retries should be attempted to successfully transfer
707 * the specified message, based on the estimated durations of the
708 * i2c and AUX transfers.
709 */
drm_dp_i2c_retry_count(const struct drm_dp_aux_msg * msg,int i2c_speed_khz)710 static int drm_dp_i2c_retry_count(const struct drm_dp_aux_msg *msg,
711 int i2c_speed_khz)
712 {
713 int aux_time_us = drm_dp_aux_req_duration(msg) +
714 drm_dp_aux_reply_duration(msg);
715 int i2c_time_us = drm_dp_i2c_msg_duration(msg, i2c_speed_khz);
716
717 return DIV_ROUND_UP(i2c_time_us, aux_time_us + AUX_RETRY_INTERVAL);
718 }
719
720 /*
721 * FIXME currently assumes 10 kHz as some real world devices seem
722 * to require it. We should query/set the speed via DPCD if supported.
723 */
724 static int dp_aux_i2c_speed_khz __read_mostly = 10;
725 module_param_unsafe(dp_aux_i2c_speed_khz, int, 0644);
726 MODULE_PARM_DESC(dp_aux_i2c_speed_khz,
727 "Assumed speed of the i2c bus in kHz, (1-400, default 10)");
728
729 /*
730 * Transfer a single I2C-over-AUX message and handle various error conditions,
731 * retrying the transaction as appropriate. It is assumed that the
732 * &drm_dp_aux.transfer function does not modify anything in the msg other than the
733 * reply field.
734 *
735 * Returns bytes transferred on success, or a negative error code on failure.
736 */
drm_dp_i2c_do_msg(struct drm_dp_aux * aux,struct drm_dp_aux_msg * msg)737 static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
738 {
739 unsigned int retry, defer_i2c;
740 int ret;
741 /*
742 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device
743 * is required to retry at least seven times upon receiving AUX_DEFER
744 * before giving up the AUX transaction.
745 *
746 * We also try to account for the i2c bus speed.
747 */
748 int max_retries = max(7, drm_dp_i2c_retry_count(msg, dp_aux_i2c_speed_khz));
749
750 for (retry = 0, defer_i2c = 0; retry < (max_retries + defer_i2c); retry++) {
751 ret = aux->transfer(aux, msg);
752 if (ret < 0) {
753 if (ret == -EBUSY)
754 continue;
755
756 /*
757 * While timeouts can be errors, they're usually normal
758 * behavior (for instance, when a driver tries to
759 * communicate with a non-existant DisplayPort device).
760 * Avoid spamming the kernel log with timeout errors.
761 */
762 if (ret == -ETIMEDOUT)
763 DRM_DEBUG_KMS_RATELIMITED("transaction timed out\n");
764 else
765 DRM_DEBUG_KMS("transaction failed: %d\n", ret);
766
767 return ret;
768 }
769
770
771 switch (msg->reply & DP_AUX_NATIVE_REPLY_MASK) {
772 case DP_AUX_NATIVE_REPLY_ACK:
773 /*
774 * For I2C-over-AUX transactions this isn't enough, we
775 * need to check for the I2C ACK reply.
776 */
777 break;
778
779 case DP_AUX_NATIVE_REPLY_NACK:
780 DRM_DEBUG_KMS("native nack (result=%d, size=%zu)\n", ret, msg->size);
781 return -EREMOTEIO;
782
783 case DP_AUX_NATIVE_REPLY_DEFER:
784 DRM_DEBUG_KMS("native defer\n");
785 /*
786 * We could check for I2C bit rate capabilities and if
787 * available adjust this interval. We could also be
788 * more careful with DP-to-legacy adapters where a
789 * long legacy cable may force very low I2C bit rates.
790 *
791 * For now just defer for long enough to hopefully be
792 * safe for all use-cases.
793 */
794 usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100);
795 continue;
796
797 default:
798 DRM_ERROR("invalid native reply %#04x\n", msg->reply);
799 return -EREMOTEIO;
800 }
801
802 switch (msg->reply & DP_AUX_I2C_REPLY_MASK) {
803 case DP_AUX_I2C_REPLY_ACK:
804 /*
805 * Both native ACK and I2C ACK replies received. We
806 * can assume the transfer was successful.
807 */
808 if (ret != msg->size)
809 drm_dp_i2c_msg_write_status_update(msg);
810 return ret;
811
812 case DP_AUX_I2C_REPLY_NACK:
813 DRM_DEBUG_KMS("I2C nack (result=%d, size=%zu\n", ret, msg->size);
814 aux->i2c_nack_count++;
815 return -EREMOTEIO;
816
817 case DP_AUX_I2C_REPLY_DEFER:
818 DRM_DEBUG_KMS("I2C defer\n");
819 /* DP Compliance Test 4.2.2.5 Requirement:
820 * Must have at least 7 retries for I2C defers on the
821 * transaction to pass this test
822 */
823 aux->i2c_defer_count++;
824 if (defer_i2c < 7)
825 defer_i2c++;
826 usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100);
827 drm_dp_i2c_msg_write_status_update(msg);
828
829 continue;
830
831 default:
832 DRM_ERROR("invalid I2C reply %#04x\n", msg->reply);
833 return -EREMOTEIO;
834 }
835 }
836
837 DRM_DEBUG_KMS("too many retries, giving up\n");
838 return -EREMOTEIO;
839 }
840
drm_dp_i2c_msg_set_request(struct drm_dp_aux_msg * msg,const struct i2c_msg * i2c_msg)841 static void drm_dp_i2c_msg_set_request(struct drm_dp_aux_msg *msg,
842 const struct i2c_msg *i2c_msg)
843 {
844 msg->request = (i2c_msg->flags & I2C_M_RD) ?
845 DP_AUX_I2C_READ : DP_AUX_I2C_WRITE;
846 msg->request |= DP_AUX_I2C_MOT;
847 }
848
849 /*
850 * Keep retrying drm_dp_i2c_do_msg until all data has been transferred.
851 *
852 * Returns an error code on failure, or a recommended transfer size on success.
853 */
drm_dp_i2c_drain_msg(struct drm_dp_aux * aux,struct drm_dp_aux_msg * orig_msg)854 static int drm_dp_i2c_drain_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *orig_msg)
855 {
856 int err, ret = orig_msg->size;
857 struct drm_dp_aux_msg msg = *orig_msg;
858
859 while (msg.size > 0) {
860 err = drm_dp_i2c_do_msg(aux, &msg);
861 if (err <= 0)
862 return err == 0 ? -EPROTO : err;
863
864 if (err < msg.size && err < ret) {
865 DRM_DEBUG_KMS("Partial I2C reply: requested %zu bytes got %d bytes\n",
866 msg.size, err);
867 ret = err;
868 }
869
870 msg.size -= err;
871 msg.buffer += err;
872 }
873
874 return ret;
875 }
876
877 /*
878 * Bizlink designed DP->DVI-D Dual Link adapters require the I2C over AUX
879 * packets to be as large as possible. If not, the I2C transactions never
880 * succeed. Hence the default is maximum.
881 */
882 static int dp_aux_i2c_transfer_size __read_mostly = DP_AUX_MAX_PAYLOAD_BYTES;
883 module_param_unsafe(dp_aux_i2c_transfer_size, int, 0644);
884 MODULE_PARM_DESC(dp_aux_i2c_transfer_size,
885 "Number of bytes to transfer in a single I2C over DP AUX CH message, (1-16, default 16)");
886
drm_dp_i2c_xfer(struct i2c_adapter * adapter,struct i2c_msg * msgs,int num)887 static int drm_dp_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs,
888 int num)
889 {
890 struct drm_dp_aux *aux = adapter->algo_data;
891 unsigned int i, j;
892 unsigned transfer_size;
893 struct drm_dp_aux_msg msg;
894 int err = 0;
895
896 dp_aux_i2c_transfer_size = clamp(dp_aux_i2c_transfer_size, 1, DP_AUX_MAX_PAYLOAD_BYTES);
897
898 memset(&msg, 0, sizeof(msg));
899
900 for (i = 0; i < num; i++) {
901 msg.address = msgs[i].addr;
902 drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
903 /* Send a bare address packet to start the transaction.
904 * Zero sized messages specify an address only (bare
905 * address) transaction.
906 */
907 msg.buffer = NULL;
908 msg.size = 0;
909 err = drm_dp_i2c_do_msg(aux, &msg);
910
911 /*
912 * Reset msg.request in case in case it got
913 * changed into a WRITE_STATUS_UPDATE.
914 */
915 drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
916
917 if (err < 0)
918 break;
919 /* We want each transaction to be as large as possible, but
920 * we'll go to smaller sizes if the hardware gives us a
921 * short reply.
922 */
923 transfer_size = dp_aux_i2c_transfer_size;
924 for (j = 0; j < msgs[i].len; j += msg.size) {
925 msg.buffer = msgs[i].buf + j;
926 msg.size = min(transfer_size, msgs[i].len - j);
927
928 err = drm_dp_i2c_drain_msg(aux, &msg);
929
930 /*
931 * Reset msg.request in case in case it got
932 * changed into a WRITE_STATUS_UPDATE.
933 */
934 drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
935
936 if (err < 0)
937 break;
938 transfer_size = err;
939 }
940 if (err < 0)
941 break;
942 }
943 if (err >= 0)
944 err = num;
945 /* Send a bare address packet to close out the transaction.
946 * Zero sized messages specify an address only (bare
947 * address) transaction.
948 */
949 msg.request &= ~DP_AUX_I2C_MOT;
950 msg.buffer = NULL;
951 msg.size = 0;
952 (void)drm_dp_i2c_do_msg(aux, &msg);
953
954 return err;
955 }
956
957 static const struct i2c_algorithm drm_dp_i2c_algo = {
958 .functionality = drm_dp_i2c_functionality,
959 .master_xfer = drm_dp_i2c_xfer,
960 };
961
i2c_to_aux(struct i2c_adapter * i2c)962 static struct drm_dp_aux *i2c_to_aux(struct i2c_adapter *i2c)
963 {
964 return container_of(i2c, struct drm_dp_aux, ddc);
965 }
966
lock_bus(struct i2c_adapter * i2c,unsigned int flags)967 static void lock_bus(struct i2c_adapter *i2c, unsigned int flags)
968 {
969 mutex_lock(&i2c_to_aux(i2c)->hw_mutex);
970 }
971
trylock_bus(struct i2c_adapter * i2c,unsigned int flags)972 static int trylock_bus(struct i2c_adapter *i2c, unsigned int flags)
973 {
974 return mutex_trylock(&i2c_to_aux(i2c)->hw_mutex);
975 }
976
unlock_bus(struct i2c_adapter * i2c,unsigned int flags)977 static void unlock_bus(struct i2c_adapter *i2c, unsigned int flags)
978 {
979 mutex_unlock(&i2c_to_aux(i2c)->hw_mutex);
980 }
981
982 static const struct i2c_lock_operations drm_dp_i2c_lock_ops = {
983 .lock_bus = lock_bus,
984 .trylock_bus = trylock_bus,
985 .unlock_bus = unlock_bus,
986 };
987
drm_dp_aux_get_crc(struct drm_dp_aux * aux,u8 * crc)988 static int drm_dp_aux_get_crc(struct drm_dp_aux *aux, u8 *crc)
989 {
990 u8 buf, count;
991 int ret;
992
993 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
994 if (ret < 0)
995 return ret;
996
997 WARN_ON(!(buf & DP_TEST_SINK_START));
998
999 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK_MISC, &buf);
1000 if (ret < 0)
1001 return ret;
1002
1003 count = buf & DP_TEST_COUNT_MASK;
1004 if (count == aux->crc_count)
1005 return -EAGAIN; /* No CRC yet */
1006
1007 aux->crc_count = count;
1008
1009 /*
1010 * At DP_TEST_CRC_R_CR, there's 6 bytes containing CRC data, 2 bytes
1011 * per component (RGB or CrYCb).
1012 */
1013 ret = drm_dp_dpcd_read(aux, DP_TEST_CRC_R_CR, crc, 6);
1014 if (ret < 0)
1015 return ret;
1016
1017 return 0;
1018 }
1019
drm_dp_aux_crc_work(struct work_struct * work)1020 static void drm_dp_aux_crc_work(struct work_struct *work)
1021 {
1022 struct drm_dp_aux *aux = container_of(work, struct drm_dp_aux,
1023 crc_work);
1024 struct drm_crtc *crtc;
1025 u8 crc_bytes[6];
1026 uint32_t crcs[3];
1027 int ret;
1028
1029 if (WARN_ON(!aux->crtc))
1030 return;
1031
1032 crtc = aux->crtc;
1033 while (crtc->crc.opened) {
1034 drm_crtc_wait_one_vblank(crtc);
1035 if (!crtc->crc.opened)
1036 break;
1037
1038 ret = drm_dp_aux_get_crc(aux, crc_bytes);
1039 if (ret == -EAGAIN) {
1040 usleep_range(1000, 2000);
1041 ret = drm_dp_aux_get_crc(aux, crc_bytes);
1042 }
1043
1044 if (ret == -EAGAIN) {
1045 DRM_DEBUG_KMS("Get CRC failed after retrying: %d\n",
1046 ret);
1047 continue;
1048 } else if (ret) {
1049 DRM_DEBUG_KMS("Failed to get a CRC: %d\n", ret);
1050 continue;
1051 }
1052
1053 crcs[0] = crc_bytes[0] | crc_bytes[1] << 8;
1054 crcs[1] = crc_bytes[2] | crc_bytes[3] << 8;
1055 crcs[2] = crc_bytes[4] | crc_bytes[5] << 8;
1056 drm_crtc_add_crc_entry(crtc, false, 0, crcs);
1057 }
1058 }
1059
1060 /**
1061 * drm_dp_aux_init() - minimally initialise an aux channel
1062 * @aux: DisplayPort AUX channel
1063 *
1064 * If you need to use the drm_dp_aux's i2c adapter prior to registering it
1065 * with the outside world, call drm_dp_aux_init() first. You must still
1066 * call drm_dp_aux_register() once the connector has been registered to
1067 * allow userspace access to the auxiliary DP channel.
1068 */
drm_dp_aux_init(struct drm_dp_aux * aux)1069 void drm_dp_aux_init(struct drm_dp_aux *aux)
1070 {
1071 lockinit(&aux->hw_mutex, "ahwm", 0, LK_CANRECURSE);
1072 INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work);
1073
1074 aux->ddc.algo = &drm_dp_i2c_algo;
1075 aux->ddc.algo_data = aux;
1076 aux->ddc.retries = 3;
1077
1078 aux->ddc.lock_ops = &drm_dp_i2c_lock_ops;
1079 }
1080 EXPORT_SYMBOL(drm_dp_aux_init);
1081
1082 /**
1083 * drm_dp_aux_register() - initialise and register aux channel
1084 * @aux: DisplayPort AUX channel
1085 *
1086 * Automatically calls drm_dp_aux_init() if this hasn't been done yet.
1087 *
1088 * Returns 0 on success or a negative error code on failure.
1089 */
drm_dp_aux_register(struct drm_dp_aux * aux)1090 int drm_dp_aux_register(struct drm_dp_aux *aux)
1091 {
1092 int ret;
1093
1094 if (!aux->ddc.algo)
1095 drm_dp_aux_init(aux);
1096
1097 #if 0
1098 aux->ddc.class = I2C_CLASS_DDC;
1099 aux->ddc.owner = THIS_MODULE;
1100 #endif
1101 aux->ddc.dev.parent = aux->dev;
1102 #if 0
1103 aux->ddc.dev.of_node = aux->dev->of_node;
1104 #endif
1105
1106 strlcpy(aux->ddc.name, aux->name ? aux->name : dev_name(aux->dev),
1107 sizeof(aux->ddc.name));
1108
1109 ret = drm_dp_aux_register_devnode(aux);
1110 if (ret)
1111 return ret;
1112
1113 ret = i2c_add_adapter(&aux->ddc);
1114 if (ret) {
1115 drm_dp_aux_unregister_devnode(aux);
1116 return ret;
1117 }
1118
1119 return 0;
1120 }
1121 EXPORT_SYMBOL(drm_dp_aux_register);
1122
1123 /**
1124 * drm_dp_aux_unregister() - unregister an AUX adapter
1125 * @aux: DisplayPort AUX channel
1126 */
drm_dp_aux_unregister(struct drm_dp_aux * aux)1127 void drm_dp_aux_unregister(struct drm_dp_aux *aux)
1128 {
1129 drm_dp_aux_unregister_devnode(aux);
1130 i2c_del_adapter(&aux->ddc);
1131 }
1132 EXPORT_SYMBOL(drm_dp_aux_unregister);
1133
1134 #define PSR_SETUP_TIME(x) [DP_PSR_SETUP_TIME_ ## x >> DP_PSR_SETUP_TIME_SHIFT] = (x)
1135
1136 /**
1137 * drm_dp_psr_setup_time() - PSR setup in time usec
1138 * @psr_cap: PSR capabilities from DPCD
1139 *
1140 * Returns:
1141 * PSR setup time for the panel in microseconds, negative
1142 * error code on failure.
1143 */
drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE])1144 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE])
1145 {
1146 static const u16 psr_setup_time_us[] = {
1147 PSR_SETUP_TIME(330),
1148 PSR_SETUP_TIME(275),
1149 PSR_SETUP_TIME(165),
1150 PSR_SETUP_TIME(110),
1151 PSR_SETUP_TIME(55),
1152 PSR_SETUP_TIME(0),
1153 };
1154 int i;
1155
1156 i = (psr_cap[1] & DP_PSR_SETUP_TIME_MASK) >> DP_PSR_SETUP_TIME_SHIFT;
1157 if (i >= ARRAY_SIZE(psr_setup_time_us))
1158 return -EINVAL;
1159
1160 return psr_setup_time_us[i];
1161 }
1162 EXPORT_SYMBOL(drm_dp_psr_setup_time);
1163
1164 #undef PSR_SETUP_TIME
1165
1166 /**
1167 * drm_dp_start_crc() - start capture of frame CRCs
1168 * @aux: DisplayPort AUX channel
1169 * @crtc: CRTC displaying the frames whose CRCs are to be captured
1170 *
1171 * Returns 0 on success or a negative error code on failure.
1172 */
drm_dp_start_crc(struct drm_dp_aux * aux,struct drm_crtc * crtc)1173 int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc)
1174 {
1175 u8 buf;
1176 int ret;
1177
1178 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
1179 if (ret < 0)
1180 return ret;
1181
1182 ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf | DP_TEST_SINK_START);
1183 if (ret < 0)
1184 return ret;
1185
1186 aux->crc_count = 0;
1187 aux->crtc = crtc;
1188 schedule_work(&aux->crc_work);
1189
1190 return 0;
1191 }
1192 EXPORT_SYMBOL(drm_dp_start_crc);
1193
1194 /**
1195 * drm_dp_stop_crc() - stop capture of frame CRCs
1196 * @aux: DisplayPort AUX channel
1197 *
1198 * Returns 0 on success or a negative error code on failure.
1199 */
drm_dp_stop_crc(struct drm_dp_aux * aux)1200 int drm_dp_stop_crc(struct drm_dp_aux *aux)
1201 {
1202 u8 buf;
1203 int ret;
1204
1205 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
1206 if (ret < 0)
1207 return ret;
1208
1209 ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf & ~DP_TEST_SINK_START);
1210 if (ret < 0)
1211 return ret;
1212
1213 flush_work(&aux->crc_work);
1214 aux->crtc = NULL;
1215
1216 return 0;
1217 }
1218 EXPORT_SYMBOL(drm_dp_stop_crc);
1219
1220 struct dpcd_quirk {
1221 u8 oui[3];
1222 bool is_branch;
1223 u32 quirks;
1224 };
1225
1226 #define OUI(first, second, third) { (first), (second), (third) }
1227
1228 static const struct dpcd_quirk dpcd_quirk_list[] = {
1229 /* Analogix 7737 needs reduced M and N at HBR2 link rates */
1230 { OUI(0x00, 0x22, 0xb9), true, BIT(DP_DPCD_QUIRK_LIMITED_M_N) },
1231 };
1232
1233 #undef OUI
1234
1235 /*
1236 * Get a bit mask of DPCD quirks for the sink/branch device identified by
1237 * ident. The quirk data is shared but it's up to the drivers to act on the
1238 * data.
1239 *
1240 * For now, only the OUI (first three bytes) is used, but this may be extended
1241 * to device identification string and hardware/firmware revisions later.
1242 */
1243 static u32
drm_dp_get_quirks(const struct drm_dp_dpcd_ident * ident,bool is_branch)1244 drm_dp_get_quirks(const struct drm_dp_dpcd_ident *ident, bool is_branch)
1245 {
1246 const struct dpcd_quirk *quirk;
1247 u32 quirks = 0;
1248 int i;
1249
1250 for (i = 0; i < ARRAY_SIZE(dpcd_quirk_list); i++) {
1251 quirk = &dpcd_quirk_list[i];
1252
1253 if (quirk->is_branch != is_branch)
1254 continue;
1255
1256 if (memcmp(quirk->oui, ident->oui, sizeof(ident->oui)) != 0)
1257 continue;
1258
1259 quirks |= quirk->quirks;
1260 }
1261
1262 return quirks;
1263 }
1264
1265 /**
1266 * drm_dp_read_desc - read sink/branch descriptor from DPCD
1267 * @aux: DisplayPort AUX channel
1268 * @desc: Device decriptor to fill from DPCD
1269 * @is_branch: true for branch devices, false for sink devices
1270 *
1271 * Read DPCD 0x400 (sink) or 0x500 (branch) into @desc. Also debug log the
1272 * identification.
1273 *
1274 * Returns 0 on success or a negative error code on failure.
1275 */
drm_dp_read_desc(struct drm_dp_aux * aux,struct drm_dp_desc * desc,bool is_branch)1276 int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
1277 bool is_branch)
1278 {
1279 struct drm_dp_dpcd_ident *ident = &desc->ident;
1280 unsigned int offset = is_branch ? DP_BRANCH_OUI : DP_SINK_OUI;
1281 int ret, dev_id_len;
1282
1283 ret = drm_dp_dpcd_read(aux, offset, ident, sizeof(*ident));
1284 if (ret < 0)
1285 return ret;
1286
1287 desc->quirks = drm_dp_get_quirks(ident, is_branch);
1288
1289 dev_id_len = strnlen(ident->device_id, sizeof(ident->device_id));
1290
1291 DRM_DEBUG_KMS("DP %s: OUI %*phD dev-ID %*pE HW-rev %d.%d SW-rev %d.%d quirks 0x%04x\n",
1292 is_branch ? "branch" : "sink",
1293 (int)sizeof(ident->oui), ident->oui,
1294 dev_id_len, ident->device_id,
1295 ident->hw_rev >> 4, ident->hw_rev & 0xf,
1296 ident->sw_major_rev, ident->sw_minor_rev,
1297 desc->quirks);
1298
1299 return 0;
1300 }
1301 EXPORT_SYMBOL(drm_dp_read_desc);
1302