1 /*- 2 * Copyright (c) 2002 Adaptec Inc. 3 * All rights reserved. 4 * 5 * Written by: David Jeffery 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: src/sys/dev/ips/ips.h,v 1.10 2004/05/30 20:08:34 phk Exp $ 29 */ 30 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/module.h> 36 #include <sys/bus.h> 37 #include <sys/conf.h> 38 #include <sys/types.h> 39 #include <sys/thread.h> 40 #include <sys/queue.h> 41 #include <sys/buf.h> 42 #include <sys/malloc.h> 43 #include <sys/time.h> 44 #include <sys/lock.h> 45 #include <sys/rman.h> 46 #include <sys/buf2.h> 47 #include <sys/thread2.h> 48 49 #include <bus/pci/pcireg.h> 50 #include <bus/pci/pcivar.h> 51 52 MALLOC_DECLARE(M_IPSBUF); 53 54 /* 55 * IPS CONSTANTS 56 */ 57 #define IPS_VENDOR_ID 0x1014 58 #define IPS_VENDOR_ID_ADAPTEC 0x9005 59 #define IPS_MORPHEUS_DEVICE_ID 0x01BD 60 #define IPS_COPPERHEAD_DEVICE_ID 0x002E 61 #define IPS_MARCO_DEVICE_ID 0x0250 62 #define IPS_CSL 0xff 63 #define IPS_POCL 0x30 64 65 /* amounts of memory to allocate for certain commands */ 66 #define IPS_ADAPTER_INFO_LEN (sizeof(ips_adapter_info_t)) 67 #define IPS_DRIVE_INFO_LEN (sizeof(ips_drive_info_t)) 68 #define IPS_COMMAND_LEN 24 69 #define IPS_MAX_SG_LEN (sizeof(ips_sg_element_t) * IPS_MAX_SG_ELEMENTS) 70 #define IPS_NVRAM_PAGE_SIZE 128 71 /* various flags */ 72 #define IPS_STATIC_FLAG 1 73 74 /* states for the card to be in */ 75 #define IPS_DEV_OPEN 0x01 76 #define IPS_TIMEOUT 0x02 /* command time out, need reset */ 77 #define IPS_OFFLINE 0x04 /* can't reset card/card failure */ 78 #define IPS_STATIC_BUSY 0x08 /* static command slot in use */ 79 80 /* max number of commands set to something low for now */ 81 #define IPS_MAX_CMD_NUM 128 82 #define IPS_MAX_NUM_DRIVES 8 83 #define IPS_MAX_SG_ELEMENTS 32 84 #define IPS_MAX_IOBUF_SIZE (64 * 1024) 85 #define IPS_BLKSIZE 512 86 87 /* logical drive states */ 88 89 #define IPS_LD_OFFLINE 0x02 90 #define IPS_LD_OKAY 0x03 91 #define IPS_LD_DEGRADED 0x04 92 #define IPS_LD_FREE 0x00 93 #define IPS_LD_SYS 0x06 94 #define IPS_LD_CRS 0x24 95 96 /* register offsets */ 97 #define MORPHEUS_REG_OMR0 0x0018 /* Outbound Msg. Reg. 0 */ 98 #define MORPHEUS_REG_OMR1 0x001C /* Outbound Msg. Reg. 1 */ 99 #define MORPHEUS_REG_IDR 0x0020 /* Inbound Doorbell Reg. */ 100 #define MORPHEUS_REG_IISR 0x0024 /* Inbound IRQ Status Reg. */ 101 #define MORPHEUS_REG_IIMR 0x0028 /* Inbound IRQ Mask Reg. */ 102 #define MORPHEUS_REG_OISR 0x0030 /* Outbound IRQ Status Reg. */ 103 #define MORPHEUS_REG_OIMR 0x0034 /* Outbound IRQ Status Reg. */ 104 #define MORPHEUS_REG_IQPR 0x0040 /* Inbound Queue Port Reg. */ 105 #define MORPHEUS_REG_OQPR 0x0044 /* Outbound Queue Port Reg. */ 106 107 #define COPPER_REG_SCPR 0x05 /* Subsystem Ctrl. Port Reg. */ 108 #define COPPER_REG_ISPR 0x06 /* IRQ Status Port Reg. */ 109 #define COPPER_REG_CBSP 0x07 /* ? Reg. */ 110 #define COPPER_REG_HISR 0x08 /* Host IRQ Status Reg. */ 111 #define COPPER_REG_CCSAR 0x10 /* Cmd. Channel Sys Addr Reg.*/ 112 #define COPPER_REG_CCCR 0x14 /* Cmd. Channel Ctrl. Reg. */ 113 #define COPPER_REG_SQHR 0x20 /* Status Queue Head Reg. */ 114 #define COPPER_REG_SQTR 0x24 /* Status Queue Tail Reg. */ 115 #define COPPER_REG_SQER 0x28 /* Status Queue End Reg. */ 116 #define COPPER_REG_SQSR 0x2C /* Status Queue Start Reg. */ 117 118 /* bit definitions */ 119 #define MORPHEUS_BIT_POST1 0x01 120 #define MORPHEUS_BIT_POST2 0x02 121 #define MORPHEUS_BIT_CMD_IRQ 0x08 122 123 #define COPPER_CMD_START 0x101A 124 #define COPPER_SEM_BIT 0x08 125 #define COPPER_EI_BIT 0x80 126 #define COPPER_EBM_BIT 0x02 127 #define COPPER_RESET_BIT 0x80 128 #define COPPER_GHI_BIT 0x04 129 #define COPPER_SCE_BIT 0x01 130 #define COPPER_OP_BIT 0x01 131 #define COPPER_ILE_BIT 0x10 132 133 /* status defines */ 134 #define IPS_POST1_OK 0x8000 135 #define IPS_POST2_OK 0x000f 136 137 /* command op codes */ 138 #define IPS_READ_CMD 0x02 139 #define IPS_WRITE_CMD 0x03 140 #define IPS_ADAPTER_INFO_CMD 0x05 141 #define IPS_CACHE_FLUSH_CMD 0x0A 142 #define IPS_REBUILD_STATUS_CMD 0x0C 143 #define IPS_ERROR_TABLE_CMD 0x17 144 #define IPS_DRIVE_INFO_CMD 0x19 145 #define IPS_SUBSYS_PARAM_CMD 0x40 146 #define IPS_CONFIG_SYNC_CMD 0x58 147 #define IPS_SG_READ_CMD 0x82 148 #define IPS_SG_WRITE_CMD 0x83 149 #define IPS_RW_NVRAM_CMD 0xBC 150 #define IPS_FFDC_CMD 0xD7 151 152 /* error information returned by the adapter */ 153 #define IPS_MIN_ERROR 0x02 154 #define IPS_ERROR_STATUS 0x13000200 /* ahh, magic numbers */ 155 156 #define IPS_OS_FREEBSD 8 157 #define IPS_VERSION_MAJOR "0.90" 158 #define IPS_VERSION_MINOR ".10" 159 160 /* Adapter Types */ 161 #define IPS_ADAPTER_COPPERHEAD 0x01 162 #define IPS_ADAPTER_COPPERHEAD2 0x02 163 #define IPS_ADAPTER_COPPERHEADOB1 0x03 164 #define IPS_ADAPTER_COPPERHEADOB2 0x04 165 #define IPS_ADAPTER_CLARINET 0x05 166 #define IPS_ADAPTER_CLARINETLITE 0x06 167 #define IPS_ADAPTER_TROMBONE 0x07 168 #define IPS_ADAPTER_MORPHEUS 0x08 169 #define IPS_ADAPTER_MORPHEUSLITE 0x09 170 #define IPS_ADAPTER_NEO 0x0A 171 #define IPS_ADAPTER_NEOLITE 0x0B 172 #define IPS_ADAPTER_SARASOTA2 0x0C 173 #define IPS_ADAPTER_SARASOTA1 0x0D 174 #define IPS_ADAPTER_MARCO 0x0E 175 #define IPS_ADAPTER_SEBRING 0x0F 176 #define IPS_ADAPTER_7T 0x10 177 #define IPS_ADAPTER_7K 0x11 178 #define IPS_ADAPTER_7M 0x12 179 #define IPS_ADAPTER_MAX_T IPS_ADAPTER_7M 180 181 /* values for ffdc_settime (from gmtime) */ 182 #define IPS_SECSPERMIN 60 183 #define IPS_MINSPERHOUR 60 184 #define IPS_HOURSPERDAY 24 185 #define IPS_DAYSPERWEEK 7 186 #define IPS_DAYSPERNYEAR 365 187 #define IPS_DAYSPERLYEAR 366 188 #define IPS_SECSPERHOUR (IPS_SECSPERMIN * IPS_MINSPERHOUR) 189 #define IPS_SECSPERDAY ((long) IPS_SECSPERHOUR * IPS_HOURSPERDAY) 190 #define IPS_MONSPERYEAR 12 191 #define IPS_EPOCH_YEAR 1970 192 #define IPS_LEAPS_THRU_END_OF(y) ((y) / 4 - (y) / 100 + (y) / 400) 193 #define ips_isleap(y) (((y) % 4) == 0 && (((y) % 100) != 0 || ((y) % 400) == 0)) 194 195 196 /* 197 * for compatibility 198 */ 199 /* struct buf to struct bio changes */ 200 201 #define d_maxsize si_iosize_max 202 203 #if defined(PCIR_MAPS) && !defined(PCIR_BARS) 204 # define PCIR_BAR(x) (PCIR_BARS + (x) * 4) 205 # define PCIR_BARS PCIR_MAPS 206 #endif 207 208 209 /* 210 * IPS MACROS 211 */ 212 213 #define ips_read_1(sc,offset) bus_space_read_1(sc->bustag, sc->bushandle, offset) 214 #define ips_read_2(sc,offset) bus_space_read_2(sc->bustag, sc->bushandle, offset) 215 #define ips_read_4(sc,offset) bus_space_read_4(sc->bustag, sc->bushandle, offset) 216 217 #define ips_write_1(sc,offset,value) bus_space_write_1(sc->bustag, sc->bushandle, offset, value) 218 #define ips_write_2(sc,offset,value) bus_space_write_2(sc->bustag, sc->bushandle, offset, value) 219 #define ips_write_4(sc,offset,value) bus_space_write_4(sc->bustag, sc->bushandle, offset, value) 220 221 #define ips_read_request(iobuf) ((bio)->bio_buf->b_cmd == BUF_CMD_READ) 222 223 #define COMMAND_ERROR(status) (((status)->fields.basic_status & 0x0f) >= IPS_MIN_ERROR) 224 225 #ifndef IPS_DEBUG 226 #define DEVICE_PRINTF(x...) 227 #define PRINTF(x...) 228 #else 229 #define DEVICE_PRINTF(level,x...) if(IPS_DEBUG >= level)device_printf(x) 230 #define PRINTF(level,x...) if(IPS_DEBUG >= level)kprintf(x) 231 #endif 232 233 /* 234 * IPS STRUCTS 235 */ 236 struct ips_softc; 237 238 typedef struct { 239 u_int8_t command; 240 u_int8_t id; 241 u_int8_t drivenum; 242 u_int8_t reserve2; 243 u_int32_t lba; 244 u_int32_t buffaddr; 245 u_int32_t reserve3; 246 } __attribute__ ((packed)) ips_generic_cmd; 247 248 typedef struct { 249 u_int8_t command; 250 u_int8_t id; 251 u_int8_t drivenum; 252 u_int8_t segnum; 253 u_int32_t lba; 254 u_int32_t buffaddr; 255 u_int16_t length; 256 u_int16_t reserve1; 257 } __attribute__ ((packed)) ips_io_cmd; 258 259 typedef struct { 260 u_int8_t command; 261 u_int8_t id; 262 u_int8_t pagenum; 263 u_int8_t rw; 264 u_int32_t reserve1; 265 u_int32_t buffaddr; 266 u_int32_t reserve3; 267 } __attribute__ ((packed)) ips_rw_nvram_cmd; 268 269 typedef struct { 270 u_int8_t command; 271 u_int8_t id; 272 u_int8_t drivenum; 273 u_int8_t reserve1; 274 u_int32_t reserve2; 275 u_int32_t buffaddr; 276 u_int32_t reserve3; 277 } __attribute__ ((packed)) ips_drive_cmd; 278 279 typedef struct { 280 u_int8_t command; 281 u_int8_t id; 282 u_int8_t reserve1; 283 u_int8_t commandtype; 284 u_int32_t reserve2; 285 u_int32_t buffaddr; 286 u_int32_t reserve3; 287 } __attribute__((packed)) ips_adapter_info_cmd; 288 289 typedef struct { 290 u_int8_t command; 291 u_int8_t id; 292 u_int8_t reset_count; 293 u_int8_t reset_type; 294 u_int8_t second; 295 u_int8_t minute; 296 u_int8_t hour; 297 u_int8_t day; 298 u_int8_t reserve1[4]; 299 u_int8_t month; 300 u_int8_t yearH; 301 u_int8_t yearL; 302 u_int8_t reserve2; 303 } __attribute__((packed)) ips_adapter_ffdc_cmd; 304 305 typedef union{ 306 ips_generic_cmd generic_cmd; 307 ips_drive_cmd drive_cmd; 308 ips_adapter_info_cmd adapter_info_cmd; 309 } ips_cmd_buff_t; 310 311 typedef struct { 312 u_int32_t signature; 313 u_int8_t reserved; 314 u_int8_t adapter_slot; 315 u_int16_t adapter_type; 316 u_int8_t bios_high[4]; 317 u_int8_t bios_low[4]; 318 u_int16_t reserve2; 319 u_int8_t reserve3; 320 u_int8_t operating_system; 321 u_int8_t driver_high[4]; 322 u_int8_t driver_low[4]; 323 u_int8_t reserve4[100]; 324 } __attribute__((packed)) ips_nvram_page5; 325 326 typedef struct { 327 u_int32_t addr; 328 u_int32_t len; 329 } ips_sg_element_t; 330 331 typedef struct { 332 u_int8_t drivenum; 333 u_int8_t merge_id; 334 u_int8_t raid_lvl; 335 u_int8_t state; 336 u_int32_t sector_count; 337 } __attribute__((packed)) ips_drive_t; 338 339 typedef struct { 340 u_int8_t drivecount; 341 u_int8_t reserve1; 342 u_int16_t reserve2; 343 ips_drive_t drives[IPS_MAX_NUM_DRIVES]; 344 } __attribute__((packed)) ips_drive_info_t; 345 346 typedef struct { 347 u_int8_t drivecount; 348 u_int8_t miscflags; 349 u_int8_t SLTflags; 350 u_int8_t BSTflags; 351 u_int8_t pwr_chg_count; 352 u_int8_t wrong_addr_count; 353 u_int8_t unident_count; 354 u_int8_t nvram_dev_chg_count; 355 u_int8_t codeblock_version[8]; 356 u_int8_t bootblock_version[8]; 357 u_int32_t drive_sector_count[IPS_MAX_NUM_DRIVES]; 358 u_int8_t max_concurrent_cmds; 359 u_int8_t max_phys_devices; 360 u_int16_t flash_prog_count; 361 u_int8_t defunct_disks; 362 u_int8_t rebuildflags; 363 u_int8_t offline_drivecount; 364 u_int8_t critical_drivecount; 365 u_int16_t config_update_count; 366 u_int8_t blockedflags; 367 u_int8_t psdn_error; 368 u_int16_t addr_dead_disk[4*16]; /* ugly, max # channels * max # scsi devices per channel */ 369 } __attribute__((packed)) ips_adapter_info_t; 370 371 typedef struct { 372 u_int32_t status[IPS_MAX_CMD_NUM]; 373 u_int32_t base_phys_addr; 374 int nextstatus; 375 bus_dma_tag_t dmatag; 376 bus_dmamap_t dmamap; 377 } ips_copper_queue_t; 378 379 typedef union { 380 struct { 381 u_int8_t reserved; 382 u_int8_t command_id; 383 u_int8_t basic_status; 384 u_int8_t extended_status; 385 } fields; 386 volatile u_int32_t value; 387 } ips_cmd_status_t; 388 389 /* used to keep track of current commands to the card */ 390 typedef struct ips_command { 391 u_int8_t command_number; 392 u_int8_t id; 393 u_int8_t timeout; 394 struct ips_softc *sc; 395 bus_dmamap_t command_dmamap; 396 void *command_buffer; 397 u_int32_t command_phys_addr; /*WARNING! must be changed if 64bit addressing ever used*/ 398 bus_dma_tag_t data_dmatag; 399 bus_dmamap_t data_dmamap; 400 /* members below are zero'd when handed out */ 401 ips_cmd_status_t status; 402 SLIST_ENTRY(ips_command) next; 403 void *data_buffer; 404 void *arg; 405 void (*callback)(struct ips_command *command); 406 int completed; 407 } ips_command_t; 408 409 typedef struct ips_wait_list { 410 STAILQ_ENTRY(ips_wait_list) next; 411 void *data; 412 int (* callback)(ips_command_t *command); 413 } ips_wait_list_t; 414 415 typedef struct ips_softc { 416 struct resource *iores; 417 struct resource *irqres; 418 struct intr_config_hook ips_ich; 419 int configured; 420 int state; 421 int iotype; 422 int rid; 423 int irqrid; 424 void *irqcookie; 425 bus_space_tag_t bustag; 426 bus_space_handle_t bushandle; 427 bus_dma_tag_t adapter_dmatag; 428 bus_dma_tag_t command_dmatag; 429 bus_dma_tag_t sg_dmatag; 430 device_t dev; 431 struct callout timer; 432 u_int16_t adapter_type; 433 ips_adapter_info_t adapter_info; 434 device_t diskdev[IPS_MAX_NUM_DRIVES]; 435 ips_drive_t drives[IPS_MAX_NUM_DRIVES]; 436 u_int8_t drivecount; 437 u_int16_t ffdc_resetcount; 438 struct timeval ffdc_resettime; 439 u_int8_t next_drive; 440 u_int8_t max_cmds; 441 volatile u_int8_t used_commands; 442 ips_command_t *commandarray; 443 ips_command_t *staticcmd; 444 SLIST_HEAD(command_list, ips_command) free_cmd_list; 445 int (*ips_adapter_reinit)(struct ips_softc *sc, 446 int force); 447 void (*ips_adapter_intr)(void *sc); 448 void (*ips_issue_cmd)(ips_command_t *command); 449 void (*ips_poll_cmd)(ips_command_t *command); 450 ips_copper_queue_t *copper_queue; 451 452 struct lock queue_lock; 453 struct bio_queue_head bio_queue; 454 } ips_softc_t; 455 456 /* function defines from ips_ioctl.c */ 457 extern int ips_ioctl_request(ips_softc_t *sc, u_long ioctl_cmd, caddr_t addr, 458 int32_t flags); 459 /* function defines from ips_disk.c */ 460 extern void ipsd_finish(struct bio *iobuf); 461 462 /* function defines from ips_commands.c */ 463 extern int ips_flush_cache(ips_softc_t *sc); 464 extern void ips_start_io_request(ips_softc_t *sc); 465 extern int ips_get_drive_info(ips_softc_t *sc); 466 extern int ips_get_adapter_info(ips_softc_t *sc); 467 extern int ips_ffdc_reset(ips_softc_t *sc); 468 extern int ips_update_nvram(ips_softc_t *sc); 469 extern int ips_clear_adapter(ips_softc_t *sc); 470 471 /* function defines from ips.c */ 472 extern int ips_get_free_cmd(ips_softc_t *sc, ips_command_t **command, 473 unsigned long flags); 474 extern void ips_insert_free_cmd(ips_softc_t *sc, ips_command_t *command); 475 extern int ips_adapter_init(ips_softc_t *sc); 476 extern int ips_morpheus_reinit(ips_softc_t *sc, int force); 477 extern int ips_adapter_free(ips_softc_t *sc); 478 extern void ips_morpheus_intr(void *sc); 479 extern void ips_issue_morpheus_cmd(ips_command_t *command); 480 extern void ips_morpheus_poll(ips_command_t *command); 481 extern int ips_copperhead_reinit(ips_softc_t *sc, int force); 482 extern void ips_copperhead_intr(void *sc); 483 extern void ips_issue_copperhead_cmd(ips_command_t *command); 484 extern void ips_copperhead_poll(ips_command_t *command); 485 int ips_timed_wait(ips_command_t *, const char *, int); 486