1 /* $NetBSD: dmac.c,v 1.12 2014/03/31 11:25:49 martin Exp $ */
2
3 /*-
4 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by UCHIYAMA Yasushi.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include <sys/cdefs.h>
33 __KERNEL_RCSID(0, "$NetBSD: dmac.c,v 1.12 2014/03/31 11:25:49 martin Exp $");
34
35 #include "debug_playstation2.h"
36
37 #include <sys/param.h>
38 #include <sys/systm.h>
39
40 #include <mips/cache.h>
41
42 #include <playstation2/ee/eevar.h>
43 #include <playstation2/ee/dmacvar.h>
44 #include <playstation2/ee/dmacreg.h>
45 #include <playstation2/ee/gsvar.h> /* debug monitor */
46
47 #include <playstation2/playstation2/interrupt.h>
48
49 #ifdef DEBUG
50 #define LEGAL_CHANNEL(x) ((x) >= 0 && (x) <= 15)
51 #define STATIC
52 #else
53 #define STATIC static
54 #endif
55
56 #define _DMAC_NINTR 10
57
58 STATIC vaddr_t __dmac_channel_base[_DMAC_NINTR] = {
59 D0_REGBASE,
60 D1_REGBASE,
61 D2_REGBASE,
62 D3_REGBASE,
63 D4_REGBASE,
64 D5_REGBASE,
65 D6_REGBASE,
66 D7_REGBASE,
67 D8_REGBASE,
68 D9_REGBASE
69 };
70
71 u_int32_t __dmac_enabled_channel;
72
73 STATIC int __dmac_initialized;
74 STATIC struct _ipl_dispatcher __dmac_dispatcher[_DMAC_NINTR];
75 STATIC struct _ipl_holder __dmac_ipl_holder[_IPL_N];
76 STATIC SLIST_HEAD(, _ipl_dispatcher) __dmac_dispatcher_head =
77 SLIST_HEAD_INITIALIZER(__dmac_dispatcher_head);
78
79 void
dmac_init(void)80 dmac_init(void)
81 {
82 int i;
83
84 if (__dmac_initialized++)
85 return;
86
87 /* disable DMAC */
88 _reg_write_4(D_ENABLEW_REG, D_ENABLE_SUSPEND);
89
90 /* disable all interrupt */
91 for (i = 0; i < _DMAC_NINTR; i++)
92 dmac_intr_disable(i);
93
94 for (i = 0; i < _IPL_N; i++)
95 __dmac_ipl_holder[i].mask = 0xffffffff;
96
97 if (_reg_read_4(D_STAT_REG) & D_STAT_SIM)
98 _reg_write_4(D_STAT_REG, D_STAT_SIM);
99 if (_reg_read_4(D_STAT_REG) & D_STAT_MEIM)
100 _reg_write_4(D_STAT_REG, D_STAT_MEIM);
101
102 /* clear all status */
103 _reg_write_4(D_STAT_REG, _reg_read_4(D_STAT_REG) & D_STAT_CIS_MASK);
104
105 /* enable DMAC */
106 _reg_write_4(D_ENABLEW_REG, 0);
107 _reg_write_4(D_CTRL_REG, D_CTRL_DMAE);
108 }
109
110 /*
111 * Interrupt
112 */
113 int
dmac_intr(u_int32_t mask)114 dmac_intr(u_int32_t mask)
115 {
116 struct _ipl_dispatcher *dispatcher;
117 u_int32_t r, dispatch, pending;
118
119 r = _reg_read_4(D_STAT_REG);
120 mask = D_STAT_CIM(mask);
121 dispatch = r & ~mask & __dmac_enabled_channel;
122 pending = r & mask & __dmac_enabled_channel;
123 #if 0
124 __gsfb_print(2,
125 "DMAC stat=%08x, mask=%08x, pend=%08x, disp=%08x enable=%08x\n",
126 r, mask, pending, dispatch, __dmac_enabled_channel);
127 #endif
128 if (dispatch == 0)
129 return (pending == 0 ? 1 : 0);
130
131 /* clear interrupt */
132 _reg_write_4(D_STAT_REG, dispatch);
133
134 /* dispatch interrupt handler */
135 SLIST_FOREACH(dispatcher, &__dmac_dispatcher_head, link) {
136 if (dispatcher->bit & dispatch) {
137 KDASSERT(dispatcher->func);
138 (*dispatcher->func)(dispatcher->arg);
139 dispatch &= ~dispatcher->bit;
140 }
141 }
142
143 /* disable spurious interrupt source */
144 if (dispatch) {
145 int i, bit;
146 for (i = 0, bit = 1; i < _DMAC_NINTR; i++, bit <<= 1) {
147 if (bit & dispatch) {
148 dmac_intr_disable(i);
149 printf("%s: spurious interrupt %d disabled.\n",
150 __func__, i);
151 }
152 }
153 }
154
155
156 return (pending == 0 ? 1 : 0);
157 }
158
159 void
dmac_intr_enable(enum dmac_channel ch)160 dmac_intr_enable(enum dmac_channel ch)
161 {
162 u_int32_t mask;
163
164 KDASSERT(LEGAL_CHANNEL(ch));
165
166 mask = D_STAT_CIM_BIT(ch);
167 _reg_write_4(D_STAT_REG, (_reg_read_4(D_STAT_REG) & mask) ^ mask);
168 }
169
170 void
dmac_intr_disable(enum dmac_channel ch)171 dmac_intr_disable(enum dmac_channel ch)
172 {
173 KDASSERT(LEGAL_CHANNEL(ch));
174
175 _reg_write_4(D_STAT_REG, _reg_read_4(D_STAT_REG) & D_STAT_CIM_BIT(ch));
176 }
177
178 void
dmac_update_mask(u_int32_t mask)179 dmac_update_mask(u_int32_t mask)
180 {
181 u_int32_t cur_mask;
182
183 mask = D_STAT_CIM(mask);
184 cur_mask = _reg_read_4(D_STAT_REG);
185
186 _reg_write_4(D_STAT_REG, ((cur_mask ^ ~mask) | (cur_mask & mask)) &
187 D_STAT_CIM(__dmac_enabled_channel));
188 }
189
190 void *
dmac_intr_establish(enum dmac_channel ch,int ipl,int (* func)(void *),void * arg)191 dmac_intr_establish(enum dmac_channel ch, int ipl, int (*func)(void *),
192 void *arg)
193 {
194 struct _ipl_dispatcher *dispatcher = &__dmac_dispatcher[ch];
195 struct _ipl_dispatcher *d;
196 int i, s;
197
198 KDASSERT(dispatcher->func == NULL);
199
200 s = _intr_suspend();
201 dispatcher->func = func;
202 dispatcher->arg = arg;
203 dispatcher->ipl = ipl;
204 dispatcher->channel = ch;
205 dispatcher->bit = D_STAT_CIS_BIT(ch);
206
207 for (i = 0; i < _IPL_N; i++) {
208 if (i < ipl)
209 __dmac_ipl_holder[i].mask &= ~D_STAT_CIM_BIT(ch);
210 else
211 __dmac_ipl_holder[i].mask |= D_STAT_CIM_BIT(ch);
212 }
213
214 /* insert queue IPL order */
215 if (SLIST_EMPTY(&__dmac_dispatcher_head)) {
216 SLIST_INSERT_HEAD(&__dmac_dispatcher_head, dispatcher, link);
217 } else {
218 SLIST_FOREACH(d, &__dmac_dispatcher_head, link) {
219 if (SLIST_NEXT(d, link) == 0 ||
220 SLIST_NEXT(d, link)->ipl < ipl) {
221 SLIST_INSERT_AFTER(d, dispatcher, link);
222 break;
223 }
224 }
225 }
226
227 md_ipl_register(IPL_DMAC, __dmac_ipl_holder);
228
229 dmac_intr_enable(ch);
230 __dmac_enabled_channel |= D_STAT_CIS_BIT(ch);
231
232 _intr_resume(s);
233
234 return ((void *)ch);
235 }
236
237 void
dmac_intr_disestablish(void * handle)238 dmac_intr_disestablish(void *handle)
239 {
240 int ch = (int)(handle);
241 struct _ipl_dispatcher *dispatcher = &__dmac_dispatcher[ch];
242 int i, s;
243
244 s = _intr_suspend();
245
246 dmac_intr_disable(ch);
247 dispatcher->func = NULL;
248
249 SLIST_REMOVE(&__dmac_dispatcher_head, dispatcher,
250 _ipl_dispatcher, link);
251
252 for (i = 0; i < _IPL_N; i++)
253 __dmac_ipl_holder[i].mask |= D_STAT_CIM_BIT(ch);
254
255 md_ipl_register(IPL_DMAC, __dmac_ipl_holder);
256 __dmac_enabled_channel &= ~D_STAT_CIS_BIT(ch);
257
258 _intr_resume(s);
259 }
260
261 /*
262 * Start/Stop
263 */
264 void
dmac_start_channel(enum dmac_channel ch)265 dmac_start_channel(enum dmac_channel ch)
266 {
267 bus_addr_t chcr = D_CHCR_REG(__dmac_channel_base[ch]);
268 u_int32_t r;
269 int s;
270
271 /* suspend all channels */
272 s = _intr_suspend();
273 r = _reg_read_4(D_ENABLER_REG);
274 _reg_write_4(D_ENABLEW_REG, r | D_ENABLE_SUSPEND);
275
276 /* access CHCR */
277 _reg_write_4(chcr, (_reg_read_4(chcr) | D_CHCR_STR));
278
279 /* start all channels */
280 _reg_write_4(D_ENABLEW_REG, r & ~D_ENABLE_SUSPEND);
281 _intr_resume(s);
282 }
283
284 void
dmac_stop_channel(enum dmac_channel ch)285 dmac_stop_channel(enum dmac_channel ch)
286 {
287 bus_addr_t chcr = D_CHCR_REG(__dmac_channel_base[ch]);
288 u_int32_t r;
289 int s;
290
291 /* suspend all channels */
292 s = _intr_suspend();
293 r = _reg_read_4(D_ENABLER_REG);
294 _reg_write_4(D_ENABLEW_REG, r | D_ENABLE_SUSPEND);
295
296 /* access CHCR */
297 _reg_write_4(chcr, (_reg_read_4(chcr) & ~D_CHCR_STR));
298
299 /* resume all chanells */
300 _reg_write_4(D_ENABLEW_REG, r);
301 _intr_resume(s);
302 }
303
304 void
dmac_sync_buffer(void)305 dmac_sync_buffer(void)
306 {
307
308 mips_dcache_wbinv_all();
309 __asm volatile("sync.l");
310 }
311
312 /*
313 * Polling
314 * DMAC status connected to CPCOND[0].
315 */
316 void
dmac_cpc_set(enum dmac_channel ch)317 dmac_cpc_set(enum dmac_channel ch)
318 {
319 u_int32_t r;
320
321 r = _reg_read_4(D_PCR_REG);
322 KDASSERT((D_PCR_CPC(r) & ~D_PCR_CPC_BIT(ch)) == 0);
323
324 /* clear interrupt status */
325 _reg_write_4(D_STAT_REG, D_STAT_CIS_BIT(ch));
326
327 _reg_write_4(D_PCR_REG, r | D_PCR_CPC_BIT(ch));
328 }
329
330 void
dmac_cpc_clear(enum dmac_channel ch)331 dmac_cpc_clear(enum dmac_channel ch)
332 {
333
334 _reg_write_4(D_PCR_REG, _reg_read_4(D_PCR_REG) & ~D_PCR_CPC_BIT(ch))
335 }
336
337 void
dmac_cpc_poll(void)338 dmac_cpc_poll(void)
339 {
340 __asm volatile(
341 ".set noreorder;"
342 "1: nop;"
343 "nop;"
344 "nop;"
345 "nop;"
346 "nop;"
347 "bc0f 1b;"
348 " nop;"
349 ".set reorder");
350 }
351
352 /* not recommended. use dmac_cpc_poll as possible */
353 void
dmac_bus_poll(enum dmac_channel ch)354 dmac_bus_poll(enum dmac_channel ch)
355 {
356 bus_addr_t chcr = D_CHCR_REG(__dmac_channel_base[ch]);
357
358 while (_reg_read_4(chcr) & D_CHCR_STR)
359 ;
360 }
361
362 /*
363 * Misc
364 */
365 void
dmac_chcr_write(enum dmac_channel ch,u_int32_t v)366 dmac_chcr_write(enum dmac_channel ch, u_int32_t v)
367 {
368 u_int32_t r;
369 int s;
370
371 /* suspend all channels */
372 s = _intr_suspend();
373 r = _reg_read_4(D_ENABLER_REG);
374 _reg_write_4(D_ENABLEW_REG, r | D_ENABLE_SUSPEND);
375
376 /* write CHCR reg */
377 _reg_write_4(D_CHCR_REG(__dmac_channel_base[ch]), v);
378
379 /* resume all chanells */
380 _reg_write_4(D_ENABLEW_REG, r);
381 _intr_resume(s);
382 }
383
384