1 /* Search an insn for pseudo regs that must be in hard regs and are not.
2 Copyright (C) 1987-2022 Free Software Foundation, Inc.
3
4 This file is part of GCC.
5
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
10
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
19
20 /* This file contains subroutines used only from the file reload1.cc.
21 It knows how to scan one insn for operands and values
22 that need to be copied into registers to make valid code.
23 It also finds other operands and values which are valid
24 but for which equivalent values in registers exist and
25 ought to be used instead.
26
27 Before processing the first insn of the function, call `init_reload'.
28 init_reload actually has to be called earlier anyway.
29
30 To scan an insn, call `find_reloads'. This does two things:
31 1. sets up tables describing which values must be reloaded
32 for this insn, and what kind of hard regs they must be reloaded into;
33 2. optionally record the locations where those values appear in
34 the data, so they can be replaced properly later.
35 This is done only if the second arg to `find_reloads' is nonzero.
36
37 The third arg to `find_reloads' specifies the number of levels
38 of indirect addressing supported by the machine. If it is zero,
39 indirect addressing is not valid. If it is one, (MEM (REG n))
40 is valid even if (REG n) did not get a hard register; if it is two,
41 (MEM (MEM (REG n))) is also valid even if (REG n) did not get a
42 hard register, and similarly for higher values.
43
44 Then you must choose the hard regs to reload those pseudo regs into,
45 and generate appropriate load insns before this insn and perhaps
46 also store insns after this insn. Set up the array `reload_reg_rtx'
47 to contain the REG rtx's for the registers you used. In some
48 cases `find_reloads' will return a nonzero value in `reload_reg_rtx'
49 for certain reloads. Then that tells you which register to use,
50 so you do not need to allocate one. But you still do need to add extra
51 instructions to copy the value into and out of that register.
52
53 Finally you must call `subst_reloads' to substitute the reload reg rtx's
54 into the locations already recorded.
55
56 NOTE SIDE EFFECTS:
57
58 find_reloads can alter the operands of the instruction it is called on.
59
60 1. Two operands of any sort may be interchanged, if they are in a
61 commutative instruction.
62 This happens only if find_reloads thinks the instruction will compile
63 better that way.
64
65 2. Pseudo-registers that are equivalent to constants are replaced
66 with those constants if they are not in hard registers.
67
68 1 happens every time find_reloads is called.
69 2 happens only when REPLACE is 1, which is only when
70 actually doing the reloads, not when just counting them.
71
72 Using a reload register for several reloads in one insn:
73
74 When an insn has reloads, it is considered as having three parts:
75 the input reloads, the insn itself after reloading, and the output reloads.
76 Reloads of values used in memory addresses are often needed for only one part.
77
78 When this is so, reload_when_needed records which part needs the reload.
79 Two reloads for different parts of the insn can share the same reload
80 register.
81
82 When a reload is used for addresses in multiple parts, or when it is
83 an ordinary operand, it is classified as RELOAD_OTHER, and cannot share
84 a register with any other reload. */
85
86 #define REG_OK_STRICT
87
88 /* We do not enable this with CHECKING_P, since it is awfully slow. */
89 #undef DEBUG_RELOAD
90
91 #include "config.h"
92 #include "system.h"
93 #include "coretypes.h"
94 #include "backend.h"
95 #include "target.h"
96 #include "rtl.h"
97 #include "tree.h"
98 #include "df.h"
99 #include "memmodel.h"
100 #include "tm_p.h"
101 #include "optabs.h"
102 #include "regs.h"
103 #include "ira.h"
104 #include "recog.h"
105 #include "rtl-error.h"
106 #include "reload.h"
107 #include "addresses.h"
108 #include "function-abi.h"
109
110 /* True if X is a constant that can be forced into the constant pool.
111 MODE is the mode of the operand, or VOIDmode if not known. */
112 #define CONST_POOL_OK_P(MODE, X) \
113 ((MODE) != VOIDmode \
114 && CONSTANT_P (X) \
115 && GET_CODE (X) != HIGH \
116 && !targetm.cannot_force_const_mem (MODE, X))
117
118 /* True if C is a non-empty register class that has too few registers
119 to be safely used as a reload target class. */
120
121 static inline bool
small_register_class_p(reg_class_t rclass)122 small_register_class_p (reg_class_t rclass)
123 {
124 return (reg_class_size [(int) rclass] == 1
125 || (reg_class_size [(int) rclass] >= 1
126 && targetm.class_likely_spilled_p (rclass)));
127 }
128
129
130 /* All reloads of the current insn are recorded here. See reload.h for
131 comments. */
132 int n_reloads;
133 struct reload rld[MAX_RELOADS];
134
135 /* All the "earlyclobber" operands of the current insn
136 are recorded here. */
137 int n_earlyclobbers;
138 rtx reload_earlyclobbers[MAX_RECOG_OPERANDS];
139
140 int reload_n_operands;
141
142 /* Replacing reloads.
143
144 If `replace_reloads' is nonzero, then as each reload is recorded
145 an entry is made for it in the table `replacements'.
146 Then later `subst_reloads' can look through that table and
147 perform all the replacements needed. */
148
149 /* Nonzero means record the places to replace. */
150 static int replace_reloads;
151
152 /* Each replacement is recorded with a structure like this. */
153 struct replacement
154 {
155 rtx *where; /* Location to store in */
156 int what; /* which reload this is for */
157 machine_mode mode; /* mode it must have */
158 };
159
160 static struct replacement replacements[MAX_RECOG_OPERANDS * ((MAX_REGS_PER_ADDRESS * 2) + 1)];
161
162 /* Number of replacements currently recorded. */
163 static int n_replacements;
164
165 /* Used to track what is modified by an operand. */
166 struct decomposition
167 {
168 int reg_flag; /* Nonzero if referencing a register. */
169 int safe; /* Nonzero if this can't conflict with anything. */
170 rtx base; /* Base address for MEM. */
171 poly_int64_pod start; /* Starting offset or register number. */
172 poly_int64_pod end; /* Ending offset or register number. */
173 };
174
175 /* Save MEMs needed to copy from one class of registers to another. One MEM
176 is used per mode, but normally only one or two modes are ever used.
177
178 We keep two versions, before and after register elimination. The one
179 after register elimination is record separately for each operand. This
180 is done in case the address is not valid to be sure that we separately
181 reload each. */
182
183 static rtx secondary_memlocs[NUM_MACHINE_MODES];
184 static rtx secondary_memlocs_elim[NUM_MACHINE_MODES][MAX_RECOG_OPERANDS];
185 static int secondary_memlocs_elim_used = 0;
186
187 /* The instruction we are doing reloads for;
188 so we can test whether a register dies in it. */
189 static rtx_insn *this_insn;
190
191 /* Nonzero if this instruction is a user-specified asm with operands. */
192 static int this_insn_is_asm;
193
194 /* If hard_regs_live_known is nonzero,
195 we can tell which hard regs are currently live,
196 at least enough to succeed in choosing dummy reloads. */
197 static int hard_regs_live_known;
198
199 /* Indexed by hard reg number,
200 element is nonnegative if hard reg has been spilled.
201 This vector is passed to `find_reloads' as an argument
202 and is not changed here. */
203 static short *static_reload_reg_p;
204
205 /* Set to 1 in subst_reg_equivs if it changes anything. */
206 static int subst_reg_equivs_changed;
207
208 /* On return from push_reload, holds the reload-number for the OUT
209 operand, which can be different for that from the input operand. */
210 static int output_reloadnum;
211
212 /* Compare two RTX's. */
213 #define MATCHES(x, y) \
214 (x == y || (x != 0 && (REG_P (x) \
215 ? REG_P (y) && REGNO (x) == REGNO (y) \
216 : rtx_equal_p (x, y) && ! side_effects_p (x))))
217
218 /* Indicates if two reloads purposes are for similar enough things that we
219 can merge their reloads. */
220 #define MERGABLE_RELOADS(when1, when2, op1, op2) \
221 ((when1) == RELOAD_OTHER || (when2) == RELOAD_OTHER \
222 || ((when1) == (when2) && (op1) == (op2)) \
223 || ((when1) == RELOAD_FOR_INPUT && (when2) == RELOAD_FOR_INPUT) \
224 || ((when1) == RELOAD_FOR_OPERAND_ADDRESS \
225 && (when2) == RELOAD_FOR_OPERAND_ADDRESS) \
226 || ((when1) == RELOAD_FOR_OTHER_ADDRESS \
227 && (when2) == RELOAD_FOR_OTHER_ADDRESS))
228
229 /* Nonzero if these two reload purposes produce RELOAD_OTHER when merged. */
230 #define MERGE_TO_OTHER(when1, when2, op1, op2) \
231 ((when1) != (when2) \
232 || ! ((op1) == (op2) \
233 || (when1) == RELOAD_FOR_INPUT \
234 || (when1) == RELOAD_FOR_OPERAND_ADDRESS \
235 || (when1) == RELOAD_FOR_OTHER_ADDRESS))
236
237 /* If we are going to reload an address, compute the reload type to
238 use. */
239 #define ADDR_TYPE(type) \
240 ((type) == RELOAD_FOR_INPUT_ADDRESS \
241 ? RELOAD_FOR_INPADDR_ADDRESS \
242 : ((type) == RELOAD_FOR_OUTPUT_ADDRESS \
243 ? RELOAD_FOR_OUTADDR_ADDRESS \
244 : (type)))
245
246 static int push_secondary_reload (int, rtx, int, int, enum reg_class,
247 machine_mode, enum reload_type,
248 enum insn_code *, secondary_reload_info *);
249 static enum reg_class find_valid_class (machine_mode, machine_mode,
250 int, unsigned int);
251 static void push_replacement (rtx *, int, machine_mode);
252 static void dup_replacements (rtx *, rtx *);
253 static void combine_reloads (void);
254 static int find_reusable_reload (rtx *, rtx, enum reg_class,
255 enum reload_type, int, int);
256 static rtx find_dummy_reload (rtx, rtx, rtx *, rtx *, machine_mode,
257 machine_mode, reg_class_t, int, int);
258 static int hard_reg_set_here_p (unsigned int, unsigned int, rtx);
259 static struct decomposition decompose (rtx);
260 static int immune_p (rtx, rtx, struct decomposition);
261 static bool alternative_allows_const_pool_ref (rtx, const char *, int);
262 static rtx find_reloads_toplev (rtx, int, enum reload_type, int, int,
263 rtx_insn *, int *);
264 static rtx make_memloc (rtx, int);
265 static bool maybe_memory_address_addr_space_p (machine_mode, rtx,
266 addr_space_t, rtx *);
267 static int find_reloads_address (machine_mode, rtx *, rtx, rtx *,
268 int, enum reload_type, int, rtx_insn *);
269 static rtx subst_reg_equivs (rtx, rtx_insn *);
270 static rtx subst_indexed_address (rtx);
271 static void update_auto_inc_notes (rtx_insn *, int, int);
272 static int find_reloads_address_1 (machine_mode, addr_space_t, rtx, int,
273 enum rtx_code, enum rtx_code, rtx *,
274 int, enum reload_type,int, rtx_insn *);
275 static void find_reloads_address_part (rtx, rtx *, enum reg_class,
276 machine_mode, int,
277 enum reload_type, int);
278 static rtx find_reloads_subreg_address (rtx, int, enum reload_type,
279 int, rtx_insn *, int *);
280 static void copy_replacements_1 (rtx *, rtx *, int);
281 static poly_int64 find_inc_amount (rtx, rtx);
282 static int refers_to_mem_for_reload_p (rtx);
283 static int refers_to_regno_for_reload_p (unsigned int, unsigned int,
284 rtx, rtx *);
285
286 /* Add NEW to reg_equiv_alt_mem_list[REGNO] if it's not present in the
287 list yet. */
288
289 static void
push_reg_equiv_alt_mem(int regno,rtx mem)290 push_reg_equiv_alt_mem (int regno, rtx mem)
291 {
292 rtx it;
293
294 for (it = reg_equiv_alt_mem_list (regno); it; it = XEXP (it, 1))
295 if (rtx_equal_p (XEXP (it, 0), mem))
296 return;
297
298 reg_equiv_alt_mem_list (regno)
299 = alloc_EXPR_LIST (REG_EQUIV, mem,
300 reg_equiv_alt_mem_list (regno));
301 }
302
303 /* Determine if any secondary reloads are needed for loading (if IN_P is
304 nonzero) or storing (if IN_P is zero) X to or from a reload register of
305 register class RELOAD_CLASS in mode RELOAD_MODE. If secondary reloads
306 are needed, push them.
307
308 Return the reload number of the secondary reload we made, or -1 if
309 we didn't need one. *PICODE is set to the insn_code to use if we do
310 need a secondary reload. */
311
312 static int
push_secondary_reload(int in_p,rtx x,int opnum,int optional,enum reg_class reload_class,machine_mode reload_mode,enum reload_type type,enum insn_code * picode,secondary_reload_info * prev_sri)313 push_secondary_reload (int in_p, rtx x, int opnum, int optional,
314 enum reg_class reload_class,
315 machine_mode reload_mode, enum reload_type type,
316 enum insn_code *picode, secondary_reload_info *prev_sri)
317 {
318 enum reg_class rclass = NO_REGS;
319 enum reg_class scratch_class;
320 machine_mode mode = reload_mode;
321 enum insn_code icode = CODE_FOR_nothing;
322 enum insn_code t_icode = CODE_FOR_nothing;
323 enum reload_type secondary_type;
324 int s_reload, t_reload = -1;
325 const char *scratch_constraint;
326 secondary_reload_info sri;
327
328 if (type == RELOAD_FOR_INPUT_ADDRESS
329 || type == RELOAD_FOR_OUTPUT_ADDRESS
330 || type == RELOAD_FOR_INPADDR_ADDRESS
331 || type == RELOAD_FOR_OUTADDR_ADDRESS)
332 secondary_type = type;
333 else
334 secondary_type = in_p ? RELOAD_FOR_INPUT_ADDRESS : RELOAD_FOR_OUTPUT_ADDRESS;
335
336 *picode = CODE_FOR_nothing;
337
338 /* If X is a paradoxical SUBREG, use the inner value to determine both the
339 mode and object being reloaded. */
340 if (paradoxical_subreg_p (x))
341 {
342 x = SUBREG_REG (x);
343 reload_mode = GET_MODE (x);
344 }
345
346 /* If X is a pseudo-register that has an equivalent MEM (actually, if it
347 is still a pseudo-register by now, it *must* have an equivalent MEM
348 but we don't want to assume that), use that equivalent when seeing if
349 a secondary reload is needed since whether or not a reload is needed
350 might be sensitive to the form of the MEM. */
351
352 if (REG_P (x) && REGNO (x) >= FIRST_PSEUDO_REGISTER
353 && reg_equiv_mem (REGNO (x)))
354 x = reg_equiv_mem (REGNO (x));
355
356 sri.icode = CODE_FOR_nothing;
357 sri.prev_sri = prev_sri;
358 rclass = (enum reg_class) targetm.secondary_reload (in_p, x, reload_class,
359 reload_mode, &sri);
360 icode = (enum insn_code) sri.icode;
361
362 /* If we don't need any secondary registers, done. */
363 if (rclass == NO_REGS && icode == CODE_FOR_nothing)
364 return -1;
365
366 if (rclass != NO_REGS)
367 t_reload = push_secondary_reload (in_p, x, opnum, optional, rclass,
368 reload_mode, type, &t_icode, &sri);
369
370 /* If we will be using an insn, the secondary reload is for a
371 scratch register. */
372
373 if (icode != CODE_FOR_nothing)
374 {
375 /* If IN_P is nonzero, the reload register will be the output in
376 operand 0. If IN_P is zero, the reload register will be the input
377 in operand 1. Outputs should have an initial "=", which we must
378 skip. */
379
380 /* ??? It would be useful to be able to handle only two, or more than
381 three, operands, but for now we can only handle the case of having
382 exactly three: output, input and one temp/scratch. */
383 gcc_assert (insn_data[(int) icode].n_operands == 3);
384
385 /* ??? We currently have no way to represent a reload that needs
386 an icode to reload from an intermediate tertiary reload register.
387 We should probably have a new field in struct reload to tag a
388 chain of scratch operand reloads onto. */
389 gcc_assert (rclass == NO_REGS);
390
391 scratch_constraint = insn_data[(int) icode].operand[2].constraint;
392 gcc_assert (*scratch_constraint == '=');
393 scratch_constraint++;
394 if (*scratch_constraint == '&')
395 scratch_constraint++;
396 scratch_class = (reg_class_for_constraint
397 (lookup_constraint (scratch_constraint)));
398
399 rclass = scratch_class;
400 mode = insn_data[(int) icode].operand[2].mode;
401 }
402
403 /* This case isn't valid, so fail. Reload is allowed to use the same
404 register for RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT reloads, but
405 in the case of a secondary register, we actually need two different
406 registers for correct code. We fail here to prevent the possibility of
407 silently generating incorrect code later.
408
409 The convention is that secondary input reloads are valid only if the
410 secondary_class is different from class. If you have such a case, you
411 cannot use secondary reloads, you must work around the problem some
412 other way.
413
414 Allow this when a reload_in/out pattern is being used. I.e. assume
415 that the generated code handles this case. */
416
417 gcc_assert (!in_p || rclass != reload_class || icode != CODE_FOR_nothing
418 || t_icode != CODE_FOR_nothing);
419
420 /* See if we can reuse an existing secondary reload. */
421 for (s_reload = 0; s_reload < n_reloads; s_reload++)
422 if (rld[s_reload].secondary_p
423 && (reg_class_subset_p (rclass, rld[s_reload].rclass)
424 || reg_class_subset_p (rld[s_reload].rclass, rclass))
425 && ((in_p && rld[s_reload].inmode == mode)
426 || (! in_p && rld[s_reload].outmode == mode))
427 && ((in_p && rld[s_reload].secondary_in_reload == t_reload)
428 || (! in_p && rld[s_reload].secondary_out_reload == t_reload))
429 && ((in_p && rld[s_reload].secondary_in_icode == t_icode)
430 || (! in_p && rld[s_reload].secondary_out_icode == t_icode))
431 && (small_register_class_p (rclass)
432 || targetm.small_register_classes_for_mode_p (VOIDmode))
433 && MERGABLE_RELOADS (secondary_type, rld[s_reload].when_needed,
434 opnum, rld[s_reload].opnum))
435 {
436 if (in_p)
437 rld[s_reload].inmode = mode;
438 if (! in_p)
439 rld[s_reload].outmode = mode;
440
441 if (reg_class_subset_p (rclass, rld[s_reload].rclass))
442 rld[s_reload].rclass = rclass;
443
444 rld[s_reload].opnum = MIN (rld[s_reload].opnum, opnum);
445 rld[s_reload].optional &= optional;
446 rld[s_reload].secondary_p = 1;
447 if (MERGE_TO_OTHER (secondary_type, rld[s_reload].when_needed,
448 opnum, rld[s_reload].opnum))
449 rld[s_reload].when_needed = RELOAD_OTHER;
450
451 break;
452 }
453
454 if (s_reload == n_reloads)
455 {
456 /* If we need a memory location to copy between the two reload regs,
457 set it up now. Note that we do the input case before making
458 the reload and the output case after. This is due to the
459 way reloads are output. */
460
461 if (in_p && icode == CODE_FOR_nothing
462 && targetm.secondary_memory_needed (mode, rclass, reload_class))
463 {
464 get_secondary_mem (x, reload_mode, opnum, type);
465
466 /* We may have just added new reloads. Make sure we add
467 the new reload at the end. */
468 s_reload = n_reloads;
469 }
470
471 /* We need to make a new secondary reload for this register class. */
472 rld[s_reload].in = rld[s_reload].out = 0;
473 rld[s_reload].rclass = rclass;
474
475 rld[s_reload].inmode = in_p ? mode : VOIDmode;
476 rld[s_reload].outmode = ! in_p ? mode : VOIDmode;
477 rld[s_reload].reg_rtx = 0;
478 rld[s_reload].optional = optional;
479 rld[s_reload].inc = 0;
480 /* Maybe we could combine these, but it seems too tricky. */
481 rld[s_reload].nocombine = 1;
482 rld[s_reload].in_reg = 0;
483 rld[s_reload].out_reg = 0;
484 rld[s_reload].opnum = opnum;
485 rld[s_reload].when_needed = secondary_type;
486 rld[s_reload].secondary_in_reload = in_p ? t_reload : -1;
487 rld[s_reload].secondary_out_reload = ! in_p ? t_reload : -1;
488 rld[s_reload].secondary_in_icode = in_p ? t_icode : CODE_FOR_nothing;
489 rld[s_reload].secondary_out_icode
490 = ! in_p ? t_icode : CODE_FOR_nothing;
491 rld[s_reload].secondary_p = 1;
492
493 n_reloads++;
494
495 if (! in_p && icode == CODE_FOR_nothing
496 && targetm.secondary_memory_needed (mode, reload_class, rclass))
497 get_secondary_mem (x, mode, opnum, type);
498 }
499
500 *picode = icode;
501 return s_reload;
502 }
503
504 /* If a secondary reload is needed, return its class. If both an intermediate
505 register and a scratch register is needed, we return the class of the
506 intermediate register. */
507 reg_class_t
secondary_reload_class(bool in_p,reg_class_t rclass,machine_mode mode,rtx x)508 secondary_reload_class (bool in_p, reg_class_t rclass, machine_mode mode,
509 rtx x)
510 {
511 enum insn_code icode;
512 secondary_reload_info sri;
513
514 sri.icode = CODE_FOR_nothing;
515 sri.prev_sri = NULL;
516 rclass
517 = (enum reg_class) targetm.secondary_reload (in_p, x, rclass, mode, &sri);
518 icode = (enum insn_code) sri.icode;
519
520 /* If there are no secondary reloads at all, we return NO_REGS.
521 If an intermediate register is needed, we return its class. */
522 if (icode == CODE_FOR_nothing || rclass != NO_REGS)
523 return rclass;
524
525 /* No intermediate register is needed, but we have a special reload
526 pattern, which we assume for now needs a scratch register. */
527 return scratch_reload_class (icode);
528 }
529
530 /* ICODE is the insn_code of a reload pattern. Check that it has exactly
531 three operands, verify that operand 2 is an output operand, and return
532 its register class.
533 ??? We'd like to be able to handle any pattern with at least 2 operands,
534 for zero or more scratch registers, but that needs more infrastructure. */
535 enum reg_class
scratch_reload_class(enum insn_code icode)536 scratch_reload_class (enum insn_code icode)
537 {
538 const char *scratch_constraint;
539 enum reg_class rclass;
540
541 gcc_assert (insn_data[(int) icode].n_operands == 3);
542 scratch_constraint = insn_data[(int) icode].operand[2].constraint;
543 gcc_assert (*scratch_constraint == '=');
544 scratch_constraint++;
545 if (*scratch_constraint == '&')
546 scratch_constraint++;
547 rclass = reg_class_for_constraint (lookup_constraint (scratch_constraint));
548 gcc_assert (rclass != NO_REGS);
549 return rclass;
550 }
551
552 /* Return a memory location that will be used to copy X in mode MODE.
553 If we haven't already made a location for this mode in this insn,
554 call find_reloads_address on the location being returned. */
555
556 rtx
get_secondary_mem(rtx x ATTRIBUTE_UNUSED,machine_mode mode,int opnum,enum reload_type type)557 get_secondary_mem (rtx x ATTRIBUTE_UNUSED, machine_mode mode,
558 int opnum, enum reload_type type)
559 {
560 rtx loc;
561 int mem_valid;
562
563 /* By default, if MODE is narrower than a word, widen it to a word.
564 This is required because most machines that require these memory
565 locations do not support short load and stores from all registers
566 (e.g., FP registers). */
567
568 mode = targetm.secondary_memory_needed_mode (mode);
569
570 /* If we already have made a MEM for this operand in MODE, return it. */
571 if (secondary_memlocs_elim[(int) mode][opnum] != 0)
572 return secondary_memlocs_elim[(int) mode][opnum];
573
574 /* If this is the first time we've tried to get a MEM for this mode,
575 allocate a new one. `something_changed' in reload will get set
576 by noticing that the frame size has changed. */
577
578 if (secondary_memlocs[(int) mode] == 0)
579 {
580 #ifdef SECONDARY_MEMORY_NEEDED_RTX
581 secondary_memlocs[(int) mode] = SECONDARY_MEMORY_NEEDED_RTX (mode);
582 #else
583 secondary_memlocs[(int) mode]
584 = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
585 #endif
586 }
587
588 /* Get a version of the address doing any eliminations needed. If that
589 didn't give us a new MEM, make a new one if it isn't valid. */
590
591 loc = eliminate_regs (secondary_memlocs[(int) mode], VOIDmode, NULL_RTX);
592 mem_valid = strict_memory_address_addr_space_p (mode, XEXP (loc, 0),
593 MEM_ADDR_SPACE (loc));
594
595 if (! mem_valid && loc == secondary_memlocs[(int) mode])
596 loc = copy_rtx (loc);
597
598 /* The only time the call below will do anything is if the stack
599 offset is too large. In that case IND_LEVELS doesn't matter, so we
600 can just pass a zero. Adjust the type to be the address of the
601 corresponding object. If the address was valid, save the eliminated
602 address. If it wasn't valid, we need to make a reload each time, so
603 don't save it. */
604
605 if (! mem_valid)
606 {
607 type = (type == RELOAD_FOR_INPUT ? RELOAD_FOR_INPUT_ADDRESS
608 : type == RELOAD_FOR_OUTPUT ? RELOAD_FOR_OUTPUT_ADDRESS
609 : RELOAD_OTHER);
610
611 find_reloads_address (mode, &loc, XEXP (loc, 0), &XEXP (loc, 0),
612 opnum, type, 0, 0);
613 }
614
615 secondary_memlocs_elim[(int) mode][opnum] = loc;
616 if (secondary_memlocs_elim_used <= (int)mode)
617 secondary_memlocs_elim_used = (int)mode + 1;
618 return loc;
619 }
620
621 /* Clear any secondary memory locations we've made. */
622
623 void
clear_secondary_mem(void)624 clear_secondary_mem (void)
625 {
626 memset (secondary_memlocs, 0, sizeof secondary_memlocs);
627 }
628
629
630 /* Find the largest class which has at least one register valid in
631 mode INNER, and which for every such register, that register number
632 plus N is also valid in OUTER (if in range) and is cheap to move
633 into REGNO. Such a class must exist. */
634
635 static enum reg_class
find_valid_class(machine_mode outer ATTRIBUTE_UNUSED,machine_mode inner ATTRIBUTE_UNUSED,int n,unsigned int dest_regno ATTRIBUTE_UNUSED)636 find_valid_class (machine_mode outer ATTRIBUTE_UNUSED,
637 machine_mode inner ATTRIBUTE_UNUSED, int n,
638 unsigned int dest_regno ATTRIBUTE_UNUSED)
639 {
640 int best_cost = -1;
641 int rclass;
642 int regno;
643 enum reg_class best_class = NO_REGS;
644 enum reg_class dest_class ATTRIBUTE_UNUSED = REGNO_REG_CLASS (dest_regno);
645 unsigned int best_size = 0;
646 int cost;
647
648 for (rclass = 1; rclass < N_REG_CLASSES; rclass++)
649 {
650 int bad = 0;
651 int good = 0;
652 for (regno = 0; regno < FIRST_PSEUDO_REGISTER - n && ! bad; regno++)
653 if (TEST_HARD_REG_BIT (reg_class_contents[rclass], regno))
654 {
655 if (targetm.hard_regno_mode_ok (regno, inner))
656 {
657 good = 1;
658 if (TEST_HARD_REG_BIT (reg_class_contents[rclass], regno + n)
659 && !targetm.hard_regno_mode_ok (regno + n, outer))
660 bad = 1;
661 }
662 }
663
664 if (bad || !good)
665 continue;
666 cost = register_move_cost (outer, (enum reg_class) rclass, dest_class);
667
668 if ((reg_class_size[rclass] > best_size
669 && (best_cost < 0 || best_cost >= cost))
670 || best_cost > cost)
671 {
672 best_class = (enum reg_class) rclass;
673 best_size = reg_class_size[rclass];
674 best_cost = register_move_cost (outer, (enum reg_class) rclass,
675 dest_class);
676 }
677 }
678
679 gcc_assert (best_size != 0);
680
681 return best_class;
682 }
683
684 /* We are trying to reload a subreg of something that is not a register.
685 Find the largest class which contains only registers valid in
686 mode MODE. OUTER is the mode of the subreg, DEST_CLASS the class in
687 which we would eventually like to obtain the object. */
688
689 static enum reg_class
find_valid_class_1(machine_mode outer ATTRIBUTE_UNUSED,machine_mode mode ATTRIBUTE_UNUSED,enum reg_class dest_class ATTRIBUTE_UNUSED)690 find_valid_class_1 (machine_mode outer ATTRIBUTE_UNUSED,
691 machine_mode mode ATTRIBUTE_UNUSED,
692 enum reg_class dest_class ATTRIBUTE_UNUSED)
693 {
694 int best_cost = -1;
695 int rclass;
696 int regno;
697 enum reg_class best_class = NO_REGS;
698 unsigned int best_size = 0;
699 int cost;
700
701 for (rclass = 1; rclass < N_REG_CLASSES; rclass++)
702 {
703 unsigned int computed_rclass_size = 0;
704
705 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
706 {
707 if (in_hard_reg_set_p (reg_class_contents[rclass], mode, regno)
708 && targetm.hard_regno_mode_ok (regno, mode))
709 computed_rclass_size++;
710 }
711
712 cost = register_move_cost (outer, (enum reg_class) rclass, dest_class);
713
714 if ((computed_rclass_size > best_size
715 && (best_cost < 0 || best_cost >= cost))
716 || best_cost > cost)
717 {
718 best_class = (enum reg_class) rclass;
719 best_size = computed_rclass_size;
720 best_cost = register_move_cost (outer, (enum reg_class) rclass,
721 dest_class);
722 }
723 }
724
725 gcc_assert (best_size != 0);
726
727 #ifdef LIMIT_RELOAD_CLASS
728 best_class = LIMIT_RELOAD_CLASS (mode, best_class);
729 #endif
730 return best_class;
731 }
732
733 /* Return the number of a previously made reload that can be combined with
734 a new one, or n_reloads if none of the existing reloads can be used.
735 OUT, RCLASS, TYPE and OPNUM are the same arguments as passed to
736 push_reload, they determine the kind of the new reload that we try to
737 combine. P_IN points to the corresponding value of IN, which can be
738 modified by this function.
739 DONT_SHARE is nonzero if we can't share any input-only reload for IN. */
740
741 static int
find_reusable_reload(rtx * p_in,rtx out,enum reg_class rclass,enum reload_type type,int opnum,int dont_share)742 find_reusable_reload (rtx *p_in, rtx out, enum reg_class rclass,
743 enum reload_type type, int opnum, int dont_share)
744 {
745 rtx in = *p_in;
746 int i;
747 /* We can't merge two reloads if the output of either one is
748 earlyclobbered. */
749
750 if (earlyclobber_operand_p (out))
751 return n_reloads;
752
753 /* We can use an existing reload if the class is right
754 and at least one of IN and OUT is a match
755 and the other is at worst neutral.
756 (A zero compared against anything is neutral.)
757
758 For targets with small register classes, don't use existing reloads
759 unless they are for the same thing since that can cause us to need
760 more reload registers than we otherwise would. */
761
762 for (i = 0; i < n_reloads; i++)
763 if ((reg_class_subset_p (rclass, rld[i].rclass)
764 || reg_class_subset_p (rld[i].rclass, rclass))
765 /* If the existing reload has a register, it must fit our class. */
766 && (rld[i].reg_rtx == 0
767 || TEST_HARD_REG_BIT (reg_class_contents[(int) rclass],
768 true_regnum (rld[i].reg_rtx)))
769 && ((in != 0 && MATCHES (rld[i].in, in) && ! dont_share
770 && (out == 0 || rld[i].out == 0 || MATCHES (rld[i].out, out)))
771 || (out != 0 && MATCHES (rld[i].out, out)
772 && (in == 0 || rld[i].in == 0 || MATCHES (rld[i].in, in))))
773 && (rld[i].out == 0 || ! earlyclobber_operand_p (rld[i].out))
774 && (small_register_class_p (rclass)
775 || targetm.small_register_classes_for_mode_p (VOIDmode))
776 && MERGABLE_RELOADS (type, rld[i].when_needed, opnum, rld[i].opnum))
777 return i;
778
779 /* Reloading a plain reg for input can match a reload to postincrement
780 that reg, since the postincrement's value is the right value.
781 Likewise, it can match a preincrement reload, since we regard
782 the preincrementation as happening before any ref in this insn
783 to that register. */
784 for (i = 0; i < n_reloads; i++)
785 if ((reg_class_subset_p (rclass, rld[i].rclass)
786 || reg_class_subset_p (rld[i].rclass, rclass))
787 /* If the existing reload has a register, it must fit our
788 class. */
789 && (rld[i].reg_rtx == 0
790 || TEST_HARD_REG_BIT (reg_class_contents[(int) rclass],
791 true_regnum (rld[i].reg_rtx)))
792 && out == 0 && rld[i].out == 0 && rld[i].in != 0
793 && ((REG_P (in)
794 && GET_RTX_CLASS (GET_CODE (rld[i].in)) == RTX_AUTOINC
795 && MATCHES (XEXP (rld[i].in, 0), in))
796 || (REG_P (rld[i].in)
797 && GET_RTX_CLASS (GET_CODE (in)) == RTX_AUTOINC
798 && MATCHES (XEXP (in, 0), rld[i].in)))
799 && (rld[i].out == 0 || ! earlyclobber_operand_p (rld[i].out))
800 && (small_register_class_p (rclass)
801 || targetm.small_register_classes_for_mode_p (VOIDmode))
802 && MERGABLE_RELOADS (type, rld[i].when_needed,
803 opnum, rld[i].opnum))
804 {
805 /* Make sure reload_in ultimately has the increment,
806 not the plain register. */
807 if (REG_P (in))
808 *p_in = rld[i].in;
809 return i;
810 }
811 return n_reloads;
812 }
813
814 /* Return true if:
815
816 (a) (subreg:OUTER_MODE REG ...) represents a word or subword subreg
817 of a multiword value; and
818
819 (b) the number of *words* in REG does not match the number of *registers*
820 in REG. */
821
822 static bool
complex_word_subreg_p(machine_mode outer_mode,rtx reg)823 complex_word_subreg_p (machine_mode outer_mode, rtx reg)
824 {
825 machine_mode inner_mode = GET_MODE (reg);
826 poly_uint64 reg_words = REG_NREGS (reg) * UNITS_PER_WORD;
827 return (known_le (GET_MODE_SIZE (outer_mode), UNITS_PER_WORD)
828 && maybe_gt (GET_MODE_SIZE (inner_mode), UNITS_PER_WORD)
829 && !known_equal_after_align_up (GET_MODE_SIZE (inner_mode),
830 reg_words, UNITS_PER_WORD));
831 }
832
833 /* Return true if X is a SUBREG that will need reloading of its SUBREG_REG
834 expression. MODE is the mode that X will be used in. OUTPUT is true if
835 the function is invoked for the output part of an enclosing reload. */
836
837 static bool
reload_inner_reg_of_subreg(rtx x,machine_mode mode,bool output)838 reload_inner_reg_of_subreg (rtx x, machine_mode mode, bool output)
839 {
840 rtx inner;
841 int regno;
842
843 /* Only SUBREGs are problematical. */
844 if (GET_CODE (x) != SUBREG)
845 return false;
846
847 inner = SUBREG_REG (x);
848
849 /* If INNER is a constant or PLUS, then INNER will need reloading. */
850 if (CONSTANT_P (inner) || GET_CODE (inner) == PLUS)
851 return true;
852
853 /* If INNER is not a register, then INNER will not need reloading. */
854 if (!REG_P (inner))
855 return false;
856
857 regno = REGNO (inner);
858
859 /* If INNER is not a hard register, then INNER will not need reloading
860 unless it's a mode dependent memory reference. */
861 if (regno >= FIRST_PSEUDO_REGISTER)
862 return !output
863 && reg_equiv_mem (regno) != 0
864 && mode_dependent_address_p (XEXP (reg_equiv_mem (regno), 0),
865 MEM_ADDR_SPACE (reg_equiv_mem (regno)));
866
867 /* If INNER is not ok for MODE, then INNER will need reloading. */
868 if (!targetm.hard_regno_mode_ok (subreg_regno (x), mode))
869 return true;
870
871 /* If this is for an output, and the outer part is a word or smaller,
872 INNER is larger than a word and the number of registers in INNER is
873 not the same as the number of words in INNER, then INNER will need
874 reloading (with an in-out reload). */
875 return output && complex_word_subreg_p (mode, inner);
876 }
877
878 /* Return nonzero if IN can be reloaded into REGNO with mode MODE without
879 requiring an extra reload register. The caller has already found that
880 IN contains some reference to REGNO, so check that we can produce the
881 new value in a single step. E.g. if we have
882 (set (reg r13) (plus (reg r13) (const int 1))), and there is an
883 instruction that adds one to a register, this should succeed.
884 However, if we have something like
885 (set (reg r13) (plus (reg r13) (const int 999))), and the constant 999
886 needs to be loaded into a register first, we need a separate reload
887 register.
888 Such PLUS reloads are generated by find_reload_address_part.
889 The out-of-range PLUS expressions are usually introduced in the instruction
890 patterns by register elimination and substituting pseudos without a home
891 by their function-invariant equivalences. */
892 static int
can_reload_into(rtx in,int regno,machine_mode mode)893 can_reload_into (rtx in, int regno, machine_mode mode)
894 {
895 rtx dst;
896 rtx_insn *test_insn;
897 int r = 0;
898 struct recog_data_d save_recog_data;
899
900 /* For matching constraints, we often get notional input reloads where
901 we want to use the original register as the reload register. I.e.
902 technically this is a non-optional input-output reload, but IN is
903 already a valid register, and has been chosen as the reload register.
904 Speed this up, since it trivially works. */
905 if (REG_P (in))
906 return 1;
907
908 /* To test MEMs properly, we'd have to take into account all the reloads
909 that are already scheduled, which can become quite complicated.
910 And since we've already handled address reloads for this MEM, it
911 should always succeed anyway. */
912 if (MEM_P (in))
913 return 1;
914
915 /* If we can make a simple SET insn that does the job, everything should
916 be fine. */
917 dst = gen_rtx_REG (mode, regno);
918 test_insn = make_insn_raw (gen_rtx_SET (dst, in));
919 save_recog_data = recog_data;
920 if (recog_memoized (test_insn) >= 0)
921 {
922 extract_insn (test_insn);
923 r = constrain_operands (1, get_enabled_alternatives (test_insn));
924 }
925 recog_data = save_recog_data;
926 return r;
927 }
928
929 /* Record one reload that needs to be performed.
930 IN is an rtx saying where the data are to be found before this instruction.
931 OUT says where they must be stored after the instruction.
932 (IN is zero for data not read, and OUT is zero for data not written.)
933 INLOC and OUTLOC point to the places in the instructions where
934 IN and OUT were found.
935 If IN and OUT are both nonzero, it means the same register must be used
936 to reload both IN and OUT.
937
938 RCLASS is a register class required for the reloaded data.
939 INMODE is the machine mode that the instruction requires
940 for the reg that replaces IN and OUTMODE is likewise for OUT.
941
942 If IN is zero, then OUT's location and mode should be passed as
943 INLOC and INMODE.
944
945 STRICT_LOW is the 1 if there is a containing STRICT_LOW_PART rtx.
946
947 OPTIONAL nonzero means this reload does not need to be performed:
948 it can be discarded if that is more convenient.
949
950 OPNUM and TYPE say what the purpose of this reload is.
951
952 The return value is the reload-number for this reload.
953
954 If both IN and OUT are nonzero, in some rare cases we might
955 want to make two separate reloads. (Actually we never do this now.)
956 Therefore, the reload-number for OUT is stored in
957 output_reloadnum when we return; the return value applies to IN.
958 Usually (presently always), when IN and OUT are nonzero,
959 the two reload-numbers are equal, but the caller should be careful to
960 distinguish them. */
961
962 int
push_reload(rtx in,rtx out,rtx * inloc,rtx * outloc,enum reg_class rclass,machine_mode inmode,machine_mode outmode,int strict_low,int optional,int opnum,enum reload_type type)963 push_reload (rtx in, rtx out, rtx *inloc, rtx *outloc,
964 enum reg_class rclass, machine_mode inmode,
965 machine_mode outmode, int strict_low, int optional,
966 int opnum, enum reload_type type)
967 {
968 int i;
969 int dont_share = 0;
970 int dont_remove_subreg = 0;
971 #ifdef LIMIT_RELOAD_CLASS
972 rtx *in_subreg_loc = 0, *out_subreg_loc = 0;
973 #endif
974 int secondary_in_reload = -1, secondary_out_reload = -1;
975 enum insn_code secondary_in_icode = CODE_FOR_nothing;
976 enum insn_code secondary_out_icode = CODE_FOR_nothing;
977 enum reg_class subreg_in_class ATTRIBUTE_UNUSED;
978 subreg_in_class = NO_REGS;
979
980 /* INMODE and/or OUTMODE could be VOIDmode if no mode
981 has been specified for the operand. In that case,
982 use the operand's mode as the mode to reload. */
983 if (inmode == VOIDmode && in != 0)
984 inmode = GET_MODE (in);
985 if (outmode == VOIDmode && out != 0)
986 outmode = GET_MODE (out);
987
988 /* If find_reloads and friends until now missed to replace a pseudo
989 with a constant of reg_equiv_constant something went wrong
990 beforehand.
991 Note that it can't simply be done here if we missed it earlier
992 since the constant might need to be pushed into the literal pool
993 and the resulting memref would probably need further
994 reloading. */
995 if (in != 0 && REG_P (in))
996 {
997 int regno = REGNO (in);
998
999 gcc_assert (regno < FIRST_PSEUDO_REGISTER
1000 || reg_renumber[regno] >= 0
1001 || reg_equiv_constant (regno) == NULL_RTX);
1002 }
1003
1004 /* reg_equiv_constant only contains constants which are obviously
1005 not appropriate as destination. So if we would need to replace
1006 the destination pseudo with a constant we are in real
1007 trouble. */
1008 if (out != 0 && REG_P (out))
1009 {
1010 int regno = REGNO (out);
1011
1012 gcc_assert (regno < FIRST_PSEUDO_REGISTER
1013 || reg_renumber[regno] >= 0
1014 || reg_equiv_constant (regno) == NULL_RTX);
1015 }
1016
1017 /* If we have a read-write operand with an address side-effect,
1018 change either IN or OUT so the side-effect happens only once. */
1019 if (in != 0 && out != 0 && MEM_P (in) && rtx_equal_p (in, out))
1020 switch (GET_CODE (XEXP (in, 0)))
1021 {
1022 case POST_INC: case POST_DEC: case POST_MODIFY:
1023 in = replace_equiv_address_nv (in, XEXP (XEXP (in, 0), 0));
1024 break;
1025
1026 case PRE_INC: case PRE_DEC: case PRE_MODIFY:
1027 out = replace_equiv_address_nv (out, XEXP (XEXP (out, 0), 0));
1028 break;
1029
1030 default:
1031 break;
1032 }
1033
1034 /* If we are reloading a (SUBREG constant ...), really reload just the
1035 inside expression in its own mode. Similarly for (SUBREG (PLUS ...)).
1036 If we have (SUBREG:M1 (MEM:M2 ...) ...) (or an inner REG that is still
1037 a pseudo and hence will become a MEM) with M1 wider than M2 and the
1038 register is a pseudo, also reload the inside expression.
1039 For machines that extend byte loads, do this for any SUBREG of a pseudo
1040 where both M1 and M2 are a word or smaller, M1 is wider than M2, and
1041 M2 is an integral mode that gets extended when loaded.
1042 Similar issue for (SUBREG:M1 (REG:M2 ...) ...) for a hard register R
1043 where either M1 is not valid for R or M2 is wider than a word but we
1044 only need one register to store an M2-sized quantity in R.
1045 (However, if OUT is nonzero, we need to reload the reg *and*
1046 the subreg, so do nothing here, and let following statement handle it.)
1047
1048 Note that the case of (SUBREG (CONST_INT...)...) is handled elsewhere;
1049 we can't handle it here because CONST_INT does not indicate a mode.
1050
1051 Similarly, we must reload the inside expression if we have a
1052 STRICT_LOW_PART (presumably, in == out in this case).
1053
1054 Also reload the inner expression if it does not require a secondary
1055 reload but the SUBREG does.
1056
1057 Also reload the inner expression if it is a register that is in
1058 the class whose registers cannot be referenced in a different size
1059 and M1 is not the same size as M2. If subreg_lowpart_p is false, we
1060 cannot reload just the inside since we might end up with the wrong
1061 register class. But if it is inside a STRICT_LOW_PART, we have
1062 no choice, so we hope we do get the right register class there.
1063
1064 Finally, reload the inner expression if it is a pseudo that will
1065 become a MEM and the MEM has a mode-dependent address, as in that
1066 case we obviously cannot change the mode of the MEM to that of the
1067 containing SUBREG as that would change the interpretation of the
1068 address. */
1069
1070 scalar_int_mode inner_mode;
1071 if (in != 0 && GET_CODE (in) == SUBREG
1072 && targetm.can_change_mode_class (GET_MODE (SUBREG_REG (in)),
1073 inmode, rclass)
1074 && contains_allocatable_reg_of_mode[rclass][GET_MODE (SUBREG_REG (in))]
1075 && (strict_low
1076 || (subreg_lowpart_p (in)
1077 && (CONSTANT_P (SUBREG_REG (in))
1078 || GET_CODE (SUBREG_REG (in)) == PLUS
1079 || (((REG_P (SUBREG_REG (in))
1080 && REGNO (SUBREG_REG (in)) >= FIRST_PSEUDO_REGISTER)
1081 || MEM_P (SUBREG_REG (in)))
1082 && (paradoxical_subreg_p (inmode,
1083 GET_MODE (SUBREG_REG (in)))
1084 || (known_le (GET_MODE_SIZE (inmode), UNITS_PER_WORD)
1085 && is_a <scalar_int_mode> (GET_MODE (SUBREG_REG
1086 (in)),
1087 &inner_mode)
1088 && GET_MODE_SIZE (inner_mode) <= UNITS_PER_WORD
1089 && paradoxical_subreg_p (inmode, inner_mode)
1090 && LOAD_EXTEND_OP (inner_mode) != UNKNOWN)
1091 || (WORD_REGISTER_OPERATIONS
1092 && partial_subreg_p (inmode,
1093 GET_MODE (SUBREG_REG (in)))
1094 && (known_equal_after_align_down
1095 (GET_MODE_SIZE (inmode) - 1,
1096 GET_MODE_SIZE (GET_MODE (SUBREG_REG
1097 (in))) - 1,
1098 UNITS_PER_WORD)))))
1099 || (REG_P (SUBREG_REG (in))
1100 && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER
1101 /* The case where out is nonzero
1102 is handled differently in the following statement. */
1103 && (out == 0 || subreg_lowpart_p (in))
1104 && (complex_word_subreg_p (inmode, SUBREG_REG (in))
1105 || !targetm.hard_regno_mode_ok (subreg_regno (in),
1106 inmode)))
1107 || (secondary_reload_class (1, rclass, inmode, in) != NO_REGS
1108 && (secondary_reload_class (1, rclass,
1109 GET_MODE (SUBREG_REG (in)),
1110 SUBREG_REG (in))
1111 == NO_REGS))
1112 || (REG_P (SUBREG_REG (in))
1113 && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER
1114 && !REG_CAN_CHANGE_MODE_P (REGNO (SUBREG_REG (in)),
1115 GET_MODE (SUBREG_REG (in)),
1116 inmode))))
1117 || (REG_P (SUBREG_REG (in))
1118 && REGNO (SUBREG_REG (in)) >= FIRST_PSEUDO_REGISTER
1119 && reg_equiv_mem (REGNO (SUBREG_REG (in)))
1120 && (mode_dependent_address_p
1121 (XEXP (reg_equiv_mem (REGNO (SUBREG_REG (in))), 0),
1122 MEM_ADDR_SPACE (reg_equiv_mem (REGNO (SUBREG_REG (in)))))))))
1123 {
1124 #ifdef LIMIT_RELOAD_CLASS
1125 in_subreg_loc = inloc;
1126 #endif
1127 inloc = &SUBREG_REG (in);
1128 in = *inloc;
1129
1130 if (!WORD_REGISTER_OPERATIONS
1131 && LOAD_EXTEND_OP (GET_MODE (in)) == UNKNOWN
1132 && MEM_P (in))
1133 /* This is supposed to happen only for paradoxical subregs made by
1134 combine.cc. (SUBREG (MEM)) isn't supposed to occur other ways. */
1135 gcc_assert (known_le (GET_MODE_SIZE (GET_MODE (in)),
1136 GET_MODE_SIZE (inmode)));
1137
1138 inmode = GET_MODE (in);
1139 }
1140
1141 /* Similar issue for (SUBREG:M1 (REG:M2 ...) ...) for a hard register R
1142 where M1 is not valid for R if it was not handled by the code above.
1143
1144 Similar issue for (SUBREG constant ...) if it was not handled by the
1145 code above. This can happen if SUBREG_BYTE != 0.
1146
1147 However, we must reload the inner reg *as well as* the subreg in
1148 that case. */
1149
1150 if (in != 0 && reload_inner_reg_of_subreg (in, inmode, false))
1151 {
1152 if (REG_P (SUBREG_REG (in)) && HARD_REGISTER_P (SUBREG_REG (in)))
1153 subreg_in_class
1154 = find_valid_class (inmode, GET_MODE (SUBREG_REG (in)),
1155 subreg_regno_offset (REGNO (SUBREG_REG (in)),
1156 GET_MODE (SUBREG_REG (in)),
1157 SUBREG_BYTE (in),
1158 GET_MODE (in)),
1159 REGNO (SUBREG_REG (in)));
1160 #if 1 // XXXMRG
1161 else if (REG_P (SUBREG_REG (in))
1162 || GET_CODE (SUBREG_REG (in)) == SYMBOL_REF)
1163 #else
1164 else if (CONSTANT_P (SUBREG_REG (in))
1165 || GET_CODE (SUBREG_REG (in)) == PLUS)
1166 #endif
1167 subreg_in_class = find_valid_class_1 (inmode,
1168 GET_MODE (SUBREG_REG (in)),
1169 rclass);
1170
1171 /* This relies on the fact that emit_reload_insns outputs the
1172 instructions for input reloads of type RELOAD_OTHER in the same
1173 order as the reloads. Thus if the outer reload is also of type
1174 RELOAD_OTHER, we are guaranteed that this inner reload will be
1175 output before the outer reload. */
1176 push_reload (SUBREG_REG (in), NULL_RTX, &SUBREG_REG (in), (rtx *) 0,
1177 subreg_in_class, VOIDmode, VOIDmode, 0, 0, opnum, type);
1178 dont_remove_subreg = 1;
1179 }
1180
1181 /* Similarly for paradoxical and problematical SUBREGs on the output.
1182 Note that there is no reason we need worry about the previous value
1183 of SUBREG_REG (out); even if wider than out, storing in a subreg is
1184 entitled to clobber it all (except in the case of a word mode subreg
1185 or of a STRICT_LOW_PART, in that latter case the constraint should
1186 label it input-output.) */
1187 if (out != 0 && GET_CODE (out) == SUBREG
1188 && (subreg_lowpart_p (out) || strict_low)
1189 && targetm.can_change_mode_class (GET_MODE (SUBREG_REG (out)),
1190 outmode, rclass)
1191 && contains_allocatable_reg_of_mode[rclass][GET_MODE (SUBREG_REG (out))]
1192 && (CONSTANT_P (SUBREG_REG (out))
1193 || strict_low
1194 || (((REG_P (SUBREG_REG (out))
1195 && REGNO (SUBREG_REG (out)) >= FIRST_PSEUDO_REGISTER)
1196 || MEM_P (SUBREG_REG (out)))
1197 && (paradoxical_subreg_p (outmode, GET_MODE (SUBREG_REG (out)))
1198 || (WORD_REGISTER_OPERATIONS
1199 && partial_subreg_p (outmode, GET_MODE (SUBREG_REG (out)))
1200 && (known_equal_after_align_down
1201 (GET_MODE_SIZE (outmode) - 1,
1202 GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))) - 1,
1203 UNITS_PER_WORD)))))
1204 || (REG_P (SUBREG_REG (out))
1205 && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER
1206 /* The case of a word mode subreg
1207 is handled differently in the following statement. */
1208 && ! (known_le (GET_MODE_SIZE (outmode), UNITS_PER_WORD)
1209 && maybe_gt (GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))),
1210 UNITS_PER_WORD))
1211 && !targetm.hard_regno_mode_ok (subreg_regno (out), outmode))
1212 || (secondary_reload_class (0, rclass, outmode, out) != NO_REGS
1213 && (secondary_reload_class (0, rclass, GET_MODE (SUBREG_REG (out)),
1214 SUBREG_REG (out))
1215 == NO_REGS))
1216 || (REG_P (SUBREG_REG (out))
1217 && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER
1218 && !REG_CAN_CHANGE_MODE_P (REGNO (SUBREG_REG (out)),
1219 GET_MODE (SUBREG_REG (out)),
1220 outmode))))
1221 {
1222 #ifdef LIMIT_RELOAD_CLASS
1223 out_subreg_loc = outloc;
1224 #endif
1225 outloc = &SUBREG_REG (out);
1226 out = *outloc;
1227 gcc_assert (WORD_REGISTER_OPERATIONS || !MEM_P (out)
1228 || known_le (GET_MODE_SIZE (GET_MODE (out)),
1229 GET_MODE_SIZE (outmode)));
1230 outmode = GET_MODE (out);
1231 }
1232
1233 /* Similar issue for (SUBREG:M1 (REG:M2 ...) ...) for a hard register R
1234 where either M1 is not valid for R or M2 is wider than a word but we
1235 only need one register to store an M2-sized quantity in R.
1236
1237 However, we must reload the inner reg *as well as* the subreg in
1238 that case and the inner reg is an in-out reload. */
1239
1240 if (out != 0 && reload_inner_reg_of_subreg (out, outmode, true))
1241 {
1242 enum reg_class in_out_class
1243 = find_valid_class (outmode, GET_MODE (SUBREG_REG (out)),
1244 subreg_regno_offset (REGNO (SUBREG_REG (out)),
1245 GET_MODE (SUBREG_REG (out)),
1246 SUBREG_BYTE (out),
1247 GET_MODE (out)),
1248 REGNO (SUBREG_REG (out)));
1249
1250 /* This relies on the fact that emit_reload_insns outputs the
1251 instructions for output reloads of type RELOAD_OTHER in reverse
1252 order of the reloads. Thus if the outer reload is also of type
1253 RELOAD_OTHER, we are guaranteed that this inner reload will be
1254 output after the outer reload. */
1255 push_reload (SUBREG_REG (out), SUBREG_REG (out), &SUBREG_REG (out),
1256 &SUBREG_REG (out), in_out_class, VOIDmode, VOIDmode,
1257 0, 0, opnum, RELOAD_OTHER);
1258 dont_remove_subreg = 1;
1259 }
1260
1261 /* If IN appears in OUT, we can't share any input-only reload for IN. */
1262 if (in != 0 && out != 0 && MEM_P (out)
1263 && (REG_P (in) || MEM_P (in) || GET_CODE (in) == PLUS)
1264 && reg_overlap_mentioned_for_reload_p (in, XEXP (out, 0)))
1265 dont_share = 1;
1266
1267 /* If IN is a SUBREG of a hard register, make a new REG. This
1268 simplifies some of the cases below. */
1269
1270 if (in != 0 && GET_CODE (in) == SUBREG && REG_P (SUBREG_REG (in))
1271 && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER
1272 && ! dont_remove_subreg)
1273 in = gen_rtx_REG (GET_MODE (in), subreg_regno (in));
1274
1275 /* Similarly for OUT. */
1276 if (out != 0 && GET_CODE (out) == SUBREG
1277 && REG_P (SUBREG_REG (out))
1278 && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER
1279 && ! dont_remove_subreg)
1280 out = gen_rtx_REG (GET_MODE (out), subreg_regno (out));
1281
1282 /* Narrow down the class of register wanted if that is
1283 desirable on this machine for efficiency. */
1284 {
1285 reg_class_t preferred_class = rclass;
1286
1287 if (in != 0)
1288 preferred_class = targetm.preferred_reload_class (in, rclass);
1289
1290 /* Output reloads may need analogous treatment, different in detail. */
1291 if (out != 0)
1292 preferred_class
1293 = targetm.preferred_output_reload_class (out, preferred_class);
1294
1295 /* Discard what the target said if we cannot do it. */
1296 if (preferred_class != NO_REGS
1297 || (optional && type == RELOAD_FOR_OUTPUT))
1298 rclass = (enum reg_class) preferred_class;
1299 }
1300
1301 /* Make sure we use a class that can handle the actual pseudo
1302 inside any subreg. For example, on the 386, QImode regs
1303 can appear within SImode subregs. Although GENERAL_REGS
1304 can handle SImode, QImode needs a smaller class. */
1305 #ifdef LIMIT_RELOAD_CLASS
1306 if (in_subreg_loc)
1307 rclass = LIMIT_RELOAD_CLASS (inmode, rclass);
1308 else if (in != 0 && GET_CODE (in) == SUBREG)
1309 rclass = LIMIT_RELOAD_CLASS (GET_MODE (SUBREG_REG (in)), rclass);
1310
1311 if (out_subreg_loc)
1312 rclass = LIMIT_RELOAD_CLASS (outmode, rclass);
1313 if (out != 0 && GET_CODE (out) == SUBREG)
1314 rclass = LIMIT_RELOAD_CLASS (GET_MODE (SUBREG_REG (out)), rclass);
1315 #endif
1316
1317 /* Verify that this class is at least possible for the mode that
1318 is specified. */
1319 if (this_insn_is_asm)
1320 {
1321 machine_mode mode;
1322 if (paradoxical_subreg_p (inmode, outmode))
1323 mode = inmode;
1324 else
1325 mode = outmode;
1326 if (mode == VOIDmode)
1327 {
1328 error_for_asm (this_insn, "cannot reload integer constant "
1329 "operand in %<asm%>");
1330 mode = word_mode;
1331 if (in != 0)
1332 inmode = word_mode;
1333 if (out != 0)
1334 outmode = word_mode;
1335 }
1336 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1337 if (targetm.hard_regno_mode_ok (i, mode)
1338 && in_hard_reg_set_p (reg_class_contents[(int) rclass], mode, i))
1339 break;
1340 if (i == FIRST_PSEUDO_REGISTER)
1341 {
1342 error_for_asm (this_insn, "impossible register constraint "
1343 "in %<asm%>");
1344 /* Avoid further trouble with this insn. */
1345 PATTERN (this_insn) = gen_rtx_USE (VOIDmode, const0_rtx);
1346 /* We used to continue here setting class to ALL_REGS, but it triggers
1347 sanity check on i386 for:
1348 void foo(long double d)
1349 {
1350 asm("" :: "a" (d));
1351 }
1352 Returning zero here ought to be safe as we take care in
1353 find_reloads to not process the reloads when instruction was
1354 replaced by USE. */
1355
1356 return 0;
1357 }
1358 }
1359
1360 /* Optional output reloads are always OK even if we have no register class,
1361 since the function of these reloads is only to have spill_reg_store etc.
1362 set, so that the storing insn can be deleted later. */
1363 gcc_assert (rclass != NO_REGS
1364 || (optional != 0 && type == RELOAD_FOR_OUTPUT));
1365
1366 i = find_reusable_reload (&in, out, rclass, type, opnum, dont_share);
1367
1368 if (i == n_reloads)
1369 {
1370 /* See if we need a secondary reload register to move between CLASS
1371 and IN or CLASS and OUT. Get the icode and push any required reloads
1372 needed for each of them if so. */
1373
1374 if (in != 0)
1375 secondary_in_reload
1376 = push_secondary_reload (1, in, opnum, optional, rclass, inmode, type,
1377 &secondary_in_icode, NULL);
1378 if (out != 0 && GET_CODE (out) != SCRATCH)
1379 secondary_out_reload
1380 = push_secondary_reload (0, out, opnum, optional, rclass, outmode,
1381 type, &secondary_out_icode, NULL);
1382
1383 /* We found no existing reload suitable for re-use.
1384 So add an additional reload. */
1385
1386 if (subreg_in_class == NO_REGS
1387 && in != 0
1388 && (REG_P (in)
1389 || (GET_CODE (in) == SUBREG && REG_P (SUBREG_REG (in))))
1390 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER)
1391 subreg_in_class = REGNO_REG_CLASS (reg_or_subregno (in));
1392 /* If a memory location is needed for the copy, make one. */
1393 if (subreg_in_class != NO_REGS
1394 && targetm.secondary_memory_needed (inmode, subreg_in_class, rclass))
1395 get_secondary_mem (in, inmode, opnum, type);
1396
1397 i = n_reloads;
1398 rld[i].in = in;
1399 rld[i].out = out;
1400 rld[i].rclass = rclass;
1401 rld[i].inmode = inmode;
1402 rld[i].outmode = outmode;
1403 rld[i].reg_rtx = 0;
1404 rld[i].optional = optional;
1405 rld[i].inc = 0;
1406 rld[i].nocombine = 0;
1407 rld[i].in_reg = inloc ? *inloc : 0;
1408 rld[i].out_reg = outloc ? *outloc : 0;
1409 rld[i].opnum = opnum;
1410 rld[i].when_needed = type;
1411 rld[i].secondary_in_reload = secondary_in_reload;
1412 rld[i].secondary_out_reload = secondary_out_reload;
1413 rld[i].secondary_in_icode = secondary_in_icode;
1414 rld[i].secondary_out_icode = secondary_out_icode;
1415 rld[i].secondary_p = 0;
1416
1417 n_reloads++;
1418
1419 if (out != 0
1420 && (REG_P (out)
1421 || (GET_CODE (out) == SUBREG && REG_P (SUBREG_REG (out))))
1422 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
1423 && (targetm.secondary_memory_needed
1424 (outmode, rclass, REGNO_REG_CLASS (reg_or_subregno (out)))))
1425 get_secondary_mem (out, outmode, opnum, type);
1426 }
1427 else
1428 {
1429 /* We are reusing an existing reload,
1430 but we may have additional information for it.
1431 For example, we may now have both IN and OUT
1432 while the old one may have just one of them. */
1433
1434 /* The modes can be different. If they are, we want to reload in
1435 the larger mode, so that the value is valid for both modes. */
1436 if (inmode != VOIDmode
1437 && partial_subreg_p (rld[i].inmode, inmode))
1438 rld[i].inmode = inmode;
1439 if (outmode != VOIDmode
1440 && partial_subreg_p (rld[i].outmode, outmode))
1441 rld[i].outmode = outmode;
1442 if (in != 0)
1443 {
1444 rtx in_reg = inloc ? *inloc : 0;
1445 /* If we merge reloads for two distinct rtl expressions that
1446 are identical in content, there might be duplicate address
1447 reloads. Remove the extra set now, so that if we later find
1448 that we can inherit this reload, we can get rid of the
1449 address reloads altogether.
1450
1451 Do not do this if both reloads are optional since the result
1452 would be an optional reload which could potentially leave
1453 unresolved address replacements.
1454
1455 It is not sufficient to call transfer_replacements since
1456 choose_reload_regs will remove the replacements for address
1457 reloads of inherited reloads which results in the same
1458 problem. */
1459 if (rld[i].in != in && rtx_equal_p (in, rld[i].in)
1460 && ! (rld[i].optional && optional))
1461 {
1462 /* We must keep the address reload with the lower operand
1463 number alive. */
1464 if (opnum > rld[i].opnum)
1465 {
1466 remove_address_replacements (in);
1467 in = rld[i].in;
1468 in_reg = rld[i].in_reg;
1469 }
1470 else
1471 remove_address_replacements (rld[i].in);
1472 }
1473 /* When emitting reloads we don't necessarily look at the in-
1474 and outmode, but also directly at the operands (in and out).
1475 So we can't simply overwrite them with whatever we have found
1476 for this (to-be-merged) reload, we have to "merge" that too.
1477 Reusing another reload already verified that we deal with the
1478 same operands, just possibly in different modes. So we
1479 overwrite the operands only when the new mode is larger.
1480 See also PR33613. */
1481 if (!rld[i].in
1482 || partial_subreg_p (GET_MODE (rld[i].in), GET_MODE (in)))
1483 rld[i].in = in;
1484 if (!rld[i].in_reg
1485 || (in_reg
1486 && partial_subreg_p (GET_MODE (rld[i].in_reg),
1487 GET_MODE (in_reg))))
1488 rld[i].in_reg = in_reg;
1489 }
1490 if (out != 0)
1491 {
1492 if (!rld[i].out
1493 || (out
1494 && partial_subreg_p (GET_MODE (rld[i].out),
1495 GET_MODE (out))))
1496 rld[i].out = out;
1497 if (outloc
1498 && (!rld[i].out_reg
1499 || partial_subreg_p (GET_MODE (rld[i].out_reg),
1500 GET_MODE (*outloc))))
1501 rld[i].out_reg = *outloc;
1502 }
1503 if (reg_class_subset_p (rclass, rld[i].rclass))
1504 rld[i].rclass = rclass;
1505 rld[i].optional &= optional;
1506 if (MERGE_TO_OTHER (type, rld[i].when_needed,
1507 opnum, rld[i].opnum))
1508 rld[i].when_needed = RELOAD_OTHER;
1509 rld[i].opnum = MIN (rld[i].opnum, opnum);
1510 }
1511
1512 /* If the ostensible rtx being reloaded differs from the rtx found
1513 in the location to substitute, this reload is not safe to combine
1514 because we cannot reliably tell whether it appears in the insn. */
1515
1516 if (in != 0 && in != *inloc)
1517 rld[i].nocombine = 1;
1518
1519 /* If we will replace IN and OUT with the reload-reg,
1520 record where they are located so that substitution need
1521 not do a tree walk. */
1522
1523 if (replace_reloads)
1524 {
1525 if (inloc != 0)
1526 {
1527 struct replacement *r = &replacements[n_replacements++];
1528 r->what = i;
1529 r->where = inloc;
1530 r->mode = inmode;
1531 }
1532 if (outloc != 0 && outloc != inloc)
1533 {
1534 struct replacement *r = &replacements[n_replacements++];
1535 r->what = i;
1536 r->where = outloc;
1537 r->mode = outmode;
1538 }
1539 }
1540
1541 /* If this reload is just being introduced and it has both
1542 an incoming quantity and an outgoing quantity that are
1543 supposed to be made to match, see if either one of the two
1544 can serve as the place to reload into.
1545
1546 If one of them is acceptable, set rld[i].reg_rtx
1547 to that one. */
1548
1549 if (in != 0 && out != 0 && in != out && rld[i].reg_rtx == 0)
1550 {
1551 rld[i].reg_rtx = find_dummy_reload (in, out, inloc, outloc,
1552 inmode, outmode,
1553 rld[i].rclass, i,
1554 earlyclobber_operand_p (out));
1555
1556 /* If the outgoing register already contains the same value
1557 as the incoming one, we can dispense with loading it.
1558 The easiest way to tell the caller that is to give a phony
1559 value for the incoming operand (same as outgoing one). */
1560 if (rld[i].reg_rtx == out
1561 && (REG_P (in) || CONSTANT_P (in))
1562 && find_equiv_reg (in, this_insn, NO_REGS, REGNO (out),
1563 static_reload_reg_p, i, inmode) != 0)
1564 rld[i].in = out;
1565 }
1566
1567 /* If this is an input reload and the operand contains a register that
1568 dies in this insn and is used nowhere else, see if it is the right class
1569 to be used for this reload. Use it if so. (This occurs most commonly
1570 in the case of paradoxical SUBREGs and in-out reloads). We cannot do
1571 this if it is also an output reload that mentions the register unless
1572 the output is a SUBREG that clobbers an entire register.
1573
1574 Note that the operand might be one of the spill regs, if it is a
1575 pseudo reg and we are in a block where spilling has not taken place.
1576 But if there is no spilling in this block, that is OK.
1577 An explicitly used hard reg cannot be a spill reg. */
1578
1579 if (rld[i].reg_rtx == 0 && in != 0 && hard_regs_live_known)
1580 {
1581 rtx note;
1582 int regno;
1583 machine_mode rel_mode = inmode;
1584
1585 if (out && partial_subreg_p (rel_mode, outmode))
1586 rel_mode = outmode;
1587
1588 for (note = REG_NOTES (this_insn); note; note = XEXP (note, 1))
1589 if (REG_NOTE_KIND (note) == REG_DEAD
1590 && REG_P (XEXP (note, 0))
1591 && (regno = REGNO (XEXP (note, 0))) < FIRST_PSEUDO_REGISTER
1592 && reg_mentioned_p (XEXP (note, 0), in)
1593 /* Check that a former pseudo is valid; see find_dummy_reload. */
1594 && (ORIGINAL_REGNO (XEXP (note, 0)) < FIRST_PSEUDO_REGISTER
1595 || (! bitmap_bit_p (DF_LR_OUT (ENTRY_BLOCK_PTR_FOR_FN (cfun)),
1596 ORIGINAL_REGNO (XEXP (note, 0)))
1597 && REG_NREGS (XEXP (note, 0)) == 1))
1598 && ! refers_to_regno_for_reload_p (regno,
1599 end_hard_regno (rel_mode,
1600 regno),
1601 PATTERN (this_insn), inloc)
1602 && ! find_reg_fusage (this_insn, USE, XEXP (note, 0))
1603 /* If this is also an output reload, IN cannot be used as
1604 the reload register if it is set in this insn unless IN
1605 is also OUT. */
1606 && (out == 0 || in == out
1607 || ! hard_reg_set_here_p (regno,
1608 end_hard_regno (rel_mode, regno),
1609 PATTERN (this_insn)))
1610 /* ??? Why is this code so different from the previous?
1611 Is there any simple coherent way to describe the two together?
1612 What's going on here. */
1613 && (in != out
1614 || (GET_CODE (in) == SUBREG
1615 && (known_equal_after_align_up
1616 (GET_MODE_SIZE (GET_MODE (in)),
1617 GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))),
1618 UNITS_PER_WORD))))
1619 /* Make sure the operand fits in the reg that dies. */
1620 && known_le (GET_MODE_SIZE (rel_mode),
1621 GET_MODE_SIZE (GET_MODE (XEXP (note, 0))))
1622 && targetm.hard_regno_mode_ok (regno, inmode)
1623 && targetm.hard_regno_mode_ok (regno, outmode))
1624 {
1625 unsigned int offs;
1626 unsigned int nregs = MAX (hard_regno_nregs (regno, inmode),
1627 hard_regno_nregs (regno, outmode));
1628
1629 for (offs = 0; offs < nregs; offs++)
1630 if (fixed_regs[regno + offs]
1631 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rclass],
1632 regno + offs))
1633 break;
1634
1635 if (offs == nregs
1636 && (! (refers_to_regno_for_reload_p
1637 (regno, end_hard_regno (inmode, regno), in, (rtx *) 0))
1638 || can_reload_into (in, regno, inmode)))
1639 {
1640 rld[i].reg_rtx = gen_rtx_REG (rel_mode, regno);
1641 break;
1642 }
1643 }
1644 }
1645
1646 if (out)
1647 output_reloadnum = i;
1648
1649 return i;
1650 }
1651
1652 /* Record an additional place we must replace a value
1653 for which we have already recorded a reload.
1654 RELOADNUM is the value returned by push_reload
1655 when the reload was recorded.
1656 This is used in insn patterns that use match_dup. */
1657
1658 static void
push_replacement(rtx * loc,int reloadnum,machine_mode mode)1659 push_replacement (rtx *loc, int reloadnum, machine_mode mode)
1660 {
1661 if (replace_reloads)
1662 {
1663 struct replacement *r = &replacements[n_replacements++];
1664 r->what = reloadnum;
1665 r->where = loc;
1666 r->mode = mode;
1667 }
1668 }
1669
1670 /* Duplicate any replacement we have recorded to apply at
1671 location ORIG_LOC to also be performed at DUP_LOC.
1672 This is used in insn patterns that use match_dup. */
1673
1674 static void
dup_replacements(rtx * dup_loc,rtx * orig_loc)1675 dup_replacements (rtx *dup_loc, rtx *orig_loc)
1676 {
1677 int i, n = n_replacements;
1678
1679 for (i = 0; i < n; i++)
1680 {
1681 struct replacement *r = &replacements[i];
1682 if (r->where == orig_loc)
1683 push_replacement (dup_loc, r->what, r->mode);
1684 }
1685 }
1686
1687 /* Transfer all replacements that used to be in reload FROM to be in
1688 reload TO. */
1689
1690 void
transfer_replacements(int to,int from)1691 transfer_replacements (int to, int from)
1692 {
1693 int i;
1694
1695 for (i = 0; i < n_replacements; i++)
1696 if (replacements[i].what == from)
1697 replacements[i].what = to;
1698 }
1699
1700 /* IN_RTX is the value loaded by a reload that we now decided to inherit,
1701 or a subpart of it. If we have any replacements registered for IN_RTX,
1702 cancel the reloads that were supposed to load them.
1703 Return nonzero if we canceled any reloads. */
1704 int
remove_address_replacements(rtx in_rtx)1705 remove_address_replacements (rtx in_rtx)
1706 {
1707 int i, j;
1708 char reload_flags[MAX_RELOADS];
1709 int something_changed = 0;
1710
1711 memset (reload_flags, 0, sizeof reload_flags);
1712 for (i = 0, j = 0; i < n_replacements; i++)
1713 {
1714 if (loc_mentioned_in_p (replacements[i].where, in_rtx))
1715 reload_flags[replacements[i].what] |= 1;
1716 else
1717 {
1718 replacements[j++] = replacements[i];
1719 reload_flags[replacements[i].what] |= 2;
1720 }
1721 }
1722 /* Note that the following store must be done before the recursive calls. */
1723 n_replacements = j;
1724
1725 for (i = n_reloads - 1; i >= 0; i--)
1726 {
1727 if (reload_flags[i] == 1)
1728 {
1729 deallocate_reload_reg (i);
1730 remove_address_replacements (rld[i].in);
1731 rld[i].in = 0;
1732 something_changed = 1;
1733 }
1734 }
1735 return something_changed;
1736 }
1737
1738 /* If there is only one output reload, and it is not for an earlyclobber
1739 operand, try to combine it with a (logically unrelated) input reload
1740 to reduce the number of reload registers needed.
1741
1742 This is safe if the input reload does not appear in
1743 the value being output-reloaded, because this implies
1744 it is not needed any more once the original insn completes.
1745
1746 If that doesn't work, see we can use any of the registers that
1747 die in this insn as a reload register. We can if it is of the right
1748 class and does not appear in the value being output-reloaded. */
1749
1750 static void
combine_reloads(void)1751 combine_reloads (void)
1752 {
1753 int i, regno;
1754 int output_reload = -1;
1755 int secondary_out = -1;
1756 rtx note;
1757
1758 /* Find the output reload; return unless there is exactly one
1759 and that one is mandatory. */
1760
1761 for (i = 0; i < n_reloads; i++)
1762 if (rld[i].out != 0)
1763 {
1764 if (output_reload >= 0)
1765 return;
1766 output_reload = i;
1767 }
1768
1769 if (output_reload < 0 || rld[output_reload].optional)
1770 return;
1771
1772 /* An input-output reload isn't combinable. */
1773
1774 if (rld[output_reload].in != 0)
1775 return;
1776
1777 /* If this reload is for an earlyclobber operand, we can't do anything. */
1778 if (earlyclobber_operand_p (rld[output_reload].out))
1779 return;
1780
1781 /* If there is a reload for part of the address of this operand, we would
1782 need to change it to RELOAD_FOR_OTHER_ADDRESS. But that would extend
1783 its life to the point where doing this combine would not lower the
1784 number of spill registers needed. */
1785 for (i = 0; i < n_reloads; i++)
1786 if ((rld[i].when_needed == RELOAD_FOR_OUTPUT_ADDRESS
1787 || rld[i].when_needed == RELOAD_FOR_OUTADDR_ADDRESS)
1788 && rld[i].opnum == rld[output_reload].opnum)
1789 return;
1790
1791 /* Check each input reload; can we combine it? */
1792
1793 for (i = 0; i < n_reloads; i++)
1794 if (rld[i].in && ! rld[i].optional && ! rld[i].nocombine
1795 /* Life span of this reload must not extend past main insn. */
1796 && rld[i].when_needed != RELOAD_FOR_OUTPUT_ADDRESS
1797 && rld[i].when_needed != RELOAD_FOR_OUTADDR_ADDRESS
1798 && rld[i].when_needed != RELOAD_OTHER
1799 && (ira_reg_class_max_nregs [(int)rld[i].rclass][(int) rld[i].inmode]
1800 == ira_reg_class_max_nregs [(int) rld[output_reload].rclass]
1801 [(int) rld[output_reload].outmode])
1802 && known_eq (rld[i].inc, 0)
1803 && rld[i].reg_rtx == 0
1804 /* Don't combine two reloads with different secondary
1805 memory locations. */
1806 && (secondary_memlocs_elim[(int) rld[output_reload].outmode][rld[i].opnum] == 0
1807 || secondary_memlocs_elim[(int) rld[output_reload].outmode][rld[output_reload].opnum] == 0
1808 || rtx_equal_p (secondary_memlocs_elim[(int) rld[output_reload].outmode][rld[i].opnum],
1809 secondary_memlocs_elim[(int) rld[output_reload].outmode][rld[output_reload].opnum]))
1810 && (targetm.small_register_classes_for_mode_p (VOIDmode)
1811 ? (rld[i].rclass == rld[output_reload].rclass)
1812 : (reg_class_subset_p (rld[i].rclass,
1813 rld[output_reload].rclass)
1814 || reg_class_subset_p (rld[output_reload].rclass,
1815 rld[i].rclass)))
1816 && (MATCHES (rld[i].in, rld[output_reload].out)
1817 /* Args reversed because the first arg seems to be
1818 the one that we imagine being modified
1819 while the second is the one that might be affected. */
1820 || (! reg_overlap_mentioned_for_reload_p (rld[output_reload].out,
1821 rld[i].in)
1822 /* However, if the input is a register that appears inside
1823 the output, then we also can't share.
1824 Imagine (set (mem (reg 69)) (plus (reg 69) ...)).
1825 If the same reload reg is used for both reg 69 and the
1826 result to be stored in memory, then that result
1827 will clobber the address of the memory ref. */
1828 && ! (REG_P (rld[i].in)
1829 && reg_overlap_mentioned_for_reload_p (rld[i].in,
1830 rld[output_reload].out))))
1831 && ! reload_inner_reg_of_subreg (rld[i].in, rld[i].inmode,
1832 rld[i].when_needed != RELOAD_FOR_INPUT)
1833 && (reg_class_size[(int) rld[i].rclass]
1834 || targetm.small_register_classes_for_mode_p (VOIDmode))
1835 /* We will allow making things slightly worse by combining an
1836 input and an output, but no worse than that. */
1837 && (rld[i].when_needed == RELOAD_FOR_INPUT
1838 || rld[i].when_needed == RELOAD_FOR_OUTPUT))
1839 {
1840 int j;
1841
1842 /* We have found a reload to combine with! */
1843 rld[i].out = rld[output_reload].out;
1844 rld[i].out_reg = rld[output_reload].out_reg;
1845 rld[i].outmode = rld[output_reload].outmode;
1846 /* Mark the old output reload as inoperative. */
1847 rld[output_reload].out = 0;
1848 /* The combined reload is needed for the entire insn. */
1849 rld[i].when_needed = RELOAD_OTHER;
1850 /* If the output reload had a secondary reload, copy it. */
1851 if (rld[output_reload].secondary_out_reload != -1)
1852 {
1853 rld[i].secondary_out_reload
1854 = rld[output_reload].secondary_out_reload;
1855 rld[i].secondary_out_icode
1856 = rld[output_reload].secondary_out_icode;
1857 }
1858
1859 /* Copy any secondary MEM. */
1860 if (secondary_memlocs_elim[(int) rld[output_reload].outmode][rld[output_reload].opnum] != 0)
1861 secondary_memlocs_elim[(int) rld[output_reload].outmode][rld[i].opnum]
1862 = secondary_memlocs_elim[(int) rld[output_reload].outmode][rld[output_reload].opnum];
1863 /* If required, minimize the register class. */
1864 if (reg_class_subset_p (rld[output_reload].rclass,
1865 rld[i].rclass))
1866 rld[i].rclass = rld[output_reload].rclass;
1867
1868 /* Transfer all replacements from the old reload to the combined. */
1869 for (j = 0; j < n_replacements; j++)
1870 if (replacements[j].what == output_reload)
1871 replacements[j].what = i;
1872
1873 return;
1874 }
1875
1876 /* If this insn has only one operand that is modified or written (assumed
1877 to be the first), it must be the one corresponding to this reload. It
1878 is safe to use anything that dies in this insn for that output provided
1879 that it does not occur in the output (we already know it isn't an
1880 earlyclobber. If this is an asm insn, give up. */
1881
1882 if (INSN_CODE (this_insn) == -1)
1883 return;
1884
1885 for (i = 1; i < insn_data[INSN_CODE (this_insn)].n_operands; i++)
1886 if (insn_data[INSN_CODE (this_insn)].operand[i].constraint[0] == '='
1887 || insn_data[INSN_CODE (this_insn)].operand[i].constraint[0] == '+')
1888 return;
1889
1890 /* See if some hard register that dies in this insn and is not used in
1891 the output is the right class. Only works if the register we pick
1892 up can fully hold our output reload. */
1893 for (note = REG_NOTES (this_insn); note; note = XEXP (note, 1))
1894 if (REG_NOTE_KIND (note) == REG_DEAD
1895 && REG_P (XEXP (note, 0))
1896 && !reg_overlap_mentioned_for_reload_p (XEXP (note, 0),
1897 rld[output_reload].out)
1898 && (regno = REGNO (XEXP (note, 0))) < FIRST_PSEUDO_REGISTER
1899 && targetm.hard_regno_mode_ok (regno, rld[output_reload].outmode)
1900 && TEST_HARD_REG_BIT (reg_class_contents[(int) rld[output_reload].rclass],
1901 regno)
1902 && (hard_regno_nregs (regno, rld[output_reload].outmode)
1903 <= REG_NREGS (XEXP (note, 0)))
1904 /* Ensure that a secondary or tertiary reload for this output
1905 won't want this register. */
1906 && ((secondary_out = rld[output_reload].secondary_out_reload) == -1
1907 || (!(TEST_HARD_REG_BIT
1908 (reg_class_contents[(int) rld[secondary_out].rclass], regno))
1909 && ((secondary_out = rld[secondary_out].secondary_out_reload) == -1
1910 || !(TEST_HARD_REG_BIT
1911 (reg_class_contents[(int) rld[secondary_out].rclass],
1912 regno)))))
1913 && !fixed_regs[regno]
1914 /* Check that a former pseudo is valid; see find_dummy_reload. */
1915 && (ORIGINAL_REGNO (XEXP (note, 0)) < FIRST_PSEUDO_REGISTER
1916 || (!bitmap_bit_p (DF_LR_OUT (ENTRY_BLOCK_PTR_FOR_FN (cfun)),
1917 ORIGINAL_REGNO (XEXP (note, 0)))
1918 && REG_NREGS (XEXP (note, 0)) == 1)))
1919 {
1920 rld[output_reload].reg_rtx
1921 = gen_rtx_REG (rld[output_reload].outmode, regno);
1922 return;
1923 }
1924 }
1925
1926 /* Try to find a reload register for an in-out reload (expressions IN and OUT).
1927 See if one of IN and OUT is a register that may be used;
1928 this is desirable since a spill-register won't be needed.
1929 If so, return the register rtx that proves acceptable.
1930
1931 INLOC and OUTLOC are locations where IN and OUT appear in the insn.
1932 RCLASS is the register class required for the reload.
1933
1934 If FOR_REAL is >= 0, it is the number of the reload,
1935 and in some cases when it can be discovered that OUT doesn't need
1936 to be computed, clear out rld[FOR_REAL].out.
1937
1938 If FOR_REAL is -1, this should not be done, because this call
1939 is just to see if a register can be found, not to find and install it.
1940
1941 EARLYCLOBBER is nonzero if OUT is an earlyclobber operand. This
1942 puts an additional constraint on being able to use IN for OUT since
1943 IN must not appear elsewhere in the insn (it is assumed that IN itself
1944 is safe from the earlyclobber). */
1945
1946 static rtx
find_dummy_reload(rtx real_in,rtx real_out,rtx * inloc,rtx * outloc,machine_mode inmode,machine_mode outmode,reg_class_t rclass,int for_real,int earlyclobber)1947 find_dummy_reload (rtx real_in, rtx real_out, rtx *inloc, rtx *outloc,
1948 machine_mode inmode, machine_mode outmode,
1949 reg_class_t rclass, int for_real, int earlyclobber)
1950 {
1951 rtx in = real_in;
1952 rtx out = real_out;
1953 int in_offset = 0;
1954 int out_offset = 0;
1955 rtx value = 0;
1956
1957 /* If operands exceed a word, we can't use either of them
1958 unless they have the same size. */
1959 if (maybe_ne (GET_MODE_SIZE (outmode), GET_MODE_SIZE (inmode))
1960 && (maybe_gt (GET_MODE_SIZE (outmode), UNITS_PER_WORD)
1961 || maybe_gt (GET_MODE_SIZE (inmode), UNITS_PER_WORD)))
1962 return 0;
1963
1964 /* Note that {in,out}_offset are needed only when 'in' or 'out'
1965 respectively refers to a hard register. */
1966
1967 /* Find the inside of any subregs. */
1968 while (GET_CODE (out) == SUBREG)
1969 {
1970 if (REG_P (SUBREG_REG (out))
1971 && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER)
1972 out_offset += subreg_regno_offset (REGNO (SUBREG_REG (out)),
1973 GET_MODE (SUBREG_REG (out)),
1974 SUBREG_BYTE (out),
1975 GET_MODE (out));
1976 out = SUBREG_REG (out);
1977 }
1978 while (GET_CODE (in) == SUBREG)
1979 {
1980 if (REG_P (SUBREG_REG (in))
1981 && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER)
1982 in_offset += subreg_regno_offset (REGNO (SUBREG_REG (in)),
1983 GET_MODE (SUBREG_REG (in)),
1984 SUBREG_BYTE (in),
1985 GET_MODE (in));
1986 in = SUBREG_REG (in);
1987 }
1988
1989 /* Narrow down the reg class, the same way push_reload will;
1990 otherwise we might find a dummy now, but push_reload won't. */
1991 {
1992 reg_class_t preferred_class = targetm.preferred_reload_class (in, rclass);
1993 if (preferred_class != NO_REGS)
1994 rclass = (enum reg_class) preferred_class;
1995 }
1996
1997 /* See if OUT will do. */
1998 if (REG_P (out)
1999 && REGNO (out) < FIRST_PSEUDO_REGISTER)
2000 {
2001 unsigned int regno = REGNO (out) + out_offset;
2002 unsigned int nwords = hard_regno_nregs (regno, outmode);
2003 rtx saved_rtx;
2004
2005 /* When we consider whether the insn uses OUT,
2006 ignore references within IN. They don't prevent us
2007 from copying IN into OUT, because those refs would
2008 move into the insn that reloads IN.
2009
2010 However, we only ignore IN in its role as this reload.
2011 If the insn uses IN elsewhere and it contains OUT,
2012 that counts. We can't be sure it's the "same" operand
2013 so it might not go through this reload.
2014
2015 We also need to avoid using OUT if it, or part of it, is a
2016 fixed register. Modifying such registers, even transiently,
2017 may have undefined effects on the machine, such as modifying
2018 the stack pointer. */
2019 saved_rtx = *inloc;
2020 *inloc = const0_rtx;
2021
2022 if (regno < FIRST_PSEUDO_REGISTER
2023 && targetm.hard_regno_mode_ok (regno, outmode)
2024 && ! refers_to_regno_for_reload_p (regno, regno + nwords,
2025 PATTERN (this_insn), outloc))
2026 {
2027 unsigned int i;
2028
2029 for (i = 0; i < nwords; i++)
2030 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) rclass],
2031 regno + i)
2032 || fixed_regs[regno + i])
2033 break;
2034
2035 if (i == nwords)
2036 {
2037 if (REG_P (real_out))
2038 value = real_out;
2039 else
2040 value = gen_rtx_REG (outmode, regno);
2041 }
2042 }
2043
2044 *inloc = saved_rtx;
2045 }
2046
2047 /* Consider using IN if OUT was not acceptable
2048 or if OUT dies in this insn (like the quotient in a divmod insn).
2049 We can't use IN unless it is dies in this insn,
2050 which means we must know accurately which hard regs are live.
2051 Also, the result can't go in IN if IN is used within OUT,
2052 or if OUT is an earlyclobber and IN appears elsewhere in the insn. */
2053 if (hard_regs_live_known
2054 && REG_P (in)
2055 && REGNO (in) < FIRST_PSEUDO_REGISTER
2056 && (value == 0
2057 || find_reg_note (this_insn, REG_UNUSED, real_out))
2058 && find_reg_note (this_insn, REG_DEAD, real_in)
2059 && !fixed_regs[REGNO (in)]
2060 && targetm.hard_regno_mode_ok (REGNO (in),
2061 /* The only case where out and real_out
2062 might have different modes is where
2063 real_out is a subreg, and in that
2064 case, out has a real mode. */
2065 (GET_MODE (out) != VOIDmode
2066 ? GET_MODE (out) : outmode))
2067 && (ORIGINAL_REGNO (in) < FIRST_PSEUDO_REGISTER
2068 /* However only do this if we can be sure that this input
2069 operand doesn't correspond with an uninitialized pseudo.
2070 global can assign some hardreg to it that is the same as
2071 the one assigned to a different, also live pseudo (as it
2072 can ignore the conflict). We must never introduce writes
2073 to such hardregs, as they would clobber the other live
2074 pseudo. See PR 20973. */
2075 || (!bitmap_bit_p (DF_LR_OUT (ENTRY_BLOCK_PTR_FOR_FN (cfun)),
2076 ORIGINAL_REGNO (in))
2077 /* Similarly, only do this if we can be sure that the death
2078 note is still valid. global can assign some hardreg to
2079 the pseudo referenced in the note and simultaneously a
2080 subword of this hardreg to a different, also live pseudo,
2081 because only another subword of the hardreg is actually
2082 used in the insn. This cannot happen if the pseudo has
2083 been assigned exactly one hardreg. See PR 33732. */
2084 && REG_NREGS (in) == 1)))
2085 {
2086 unsigned int regno = REGNO (in) + in_offset;
2087 unsigned int nwords = hard_regno_nregs (regno, inmode);
2088
2089 if (! refers_to_regno_for_reload_p (regno, regno + nwords, out, (rtx*) 0)
2090 && ! hard_reg_set_here_p (regno, regno + nwords,
2091 PATTERN (this_insn))
2092 && (! earlyclobber
2093 || ! refers_to_regno_for_reload_p (regno, regno + nwords,
2094 PATTERN (this_insn), inloc)))
2095 {
2096 unsigned int i;
2097
2098 for (i = 0; i < nwords; i++)
2099 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) rclass],
2100 regno + i))
2101 break;
2102
2103 if (i == nwords)
2104 {
2105 /* If we were going to use OUT as the reload reg
2106 and changed our mind, it means OUT is a dummy that
2107 dies here. So don't bother copying value to it. */
2108 if (for_real >= 0 && value == real_out)
2109 rld[for_real].out = 0;
2110 if (REG_P (real_in))
2111 value = real_in;
2112 else
2113 value = gen_rtx_REG (inmode, regno);
2114 }
2115 }
2116 }
2117
2118 return value;
2119 }
2120
2121 /* This page contains subroutines used mainly for determining
2122 whether the IN or an OUT of a reload can serve as the
2123 reload register. */
2124
2125 /* Return 1 if X is an operand of an insn that is being earlyclobbered. */
2126
2127 int
earlyclobber_operand_p(rtx x)2128 earlyclobber_operand_p (rtx x)
2129 {
2130 int i;
2131
2132 for (i = 0; i < n_earlyclobbers; i++)
2133 if (reload_earlyclobbers[i] == x)
2134 return 1;
2135
2136 return 0;
2137 }
2138
2139 /* Return 1 if expression X alters a hard reg in the range
2140 from BEG_REGNO (inclusive) to END_REGNO (exclusive),
2141 either explicitly or in the guise of a pseudo-reg allocated to REGNO.
2142 X should be the body of an instruction. */
2143
2144 static int
hard_reg_set_here_p(unsigned int beg_regno,unsigned int end_regno,rtx x)2145 hard_reg_set_here_p (unsigned int beg_regno, unsigned int end_regno, rtx x)
2146 {
2147 if (GET_CODE (x) == SET || GET_CODE (x) == CLOBBER)
2148 {
2149 rtx op0 = SET_DEST (x);
2150
2151 while (GET_CODE (op0) == SUBREG)
2152 op0 = SUBREG_REG (op0);
2153 if (REG_P (op0))
2154 {
2155 unsigned int r = REGNO (op0);
2156
2157 /* See if this reg overlaps range under consideration. */
2158 if (r < end_regno
2159 && end_hard_regno (GET_MODE (op0), r) > beg_regno)
2160 return 1;
2161 }
2162 }
2163 else if (GET_CODE (x) == PARALLEL)
2164 {
2165 int i = XVECLEN (x, 0) - 1;
2166
2167 for (; i >= 0; i--)
2168 if (hard_reg_set_here_p (beg_regno, end_regno, XVECEXP (x, 0, i)))
2169 return 1;
2170 }
2171
2172 return 0;
2173 }
2174
2175 /* Return true if ADDR is a valid memory address for mode MODE
2176 in address space AS, and check that each pseudo reg has the
2177 proper kind of hard reg. */
2178
2179 bool
strict_memory_address_addr_space_p(machine_mode mode ATTRIBUTE_UNUSED,rtx addr,addr_space_t as)2180 strict_memory_address_addr_space_p (machine_mode mode ATTRIBUTE_UNUSED,
2181 rtx addr, addr_space_t as)
2182 {
2183 #ifdef GO_IF_LEGITIMATE_ADDRESS
2184 gcc_assert (ADDR_SPACE_GENERIC_P (as));
2185 GO_IF_LEGITIMATE_ADDRESS (mode, addr, win);
2186 return false;
2187
2188 win:
2189 return true;
2190 #else
2191 return targetm.addr_space.legitimate_address_p (mode, addr, 1, as);
2192 #endif
2193 }
2194
2195 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
2196 if they are the same hard reg, and has special hacks for
2197 autoincrement and autodecrement.
2198 This is specifically intended for find_reloads to use
2199 in determining whether two operands match.
2200 X is the operand whose number is the lower of the two.
2201
2202 The value is 2 if Y contains a pre-increment that matches
2203 a non-incrementing address in X. */
2204
2205 /* ??? To be completely correct, we should arrange to pass
2206 for X the output operand and for Y the input operand.
2207 For now, we assume that the output operand has the lower number
2208 because that is natural in (SET output (... input ...)). */
2209
2210 int
operands_match_p(rtx x,rtx y)2211 operands_match_p (rtx x, rtx y)
2212 {
2213 int i;
2214 RTX_CODE code = GET_CODE (x);
2215 const char *fmt;
2216 int success_2;
2217
2218 if (x == y)
2219 return 1;
2220 if ((code == REG || (code == SUBREG && REG_P (SUBREG_REG (x))))
2221 && (REG_P (y) || (GET_CODE (y) == SUBREG
2222 && REG_P (SUBREG_REG (y)))))
2223 {
2224 int j;
2225
2226 if (code == SUBREG)
2227 {
2228 i = REGNO (SUBREG_REG (x));
2229 if (i >= FIRST_PSEUDO_REGISTER)
2230 goto slow;
2231 i += subreg_regno_offset (REGNO (SUBREG_REG (x)),
2232 GET_MODE (SUBREG_REG (x)),
2233 SUBREG_BYTE (x),
2234 GET_MODE (x));
2235 }
2236 else
2237 i = REGNO (x);
2238
2239 if (GET_CODE (y) == SUBREG)
2240 {
2241 j = REGNO (SUBREG_REG (y));
2242 if (j >= FIRST_PSEUDO_REGISTER)
2243 goto slow;
2244 j += subreg_regno_offset (REGNO (SUBREG_REG (y)),
2245 GET_MODE (SUBREG_REG (y)),
2246 SUBREG_BYTE (y),
2247 GET_MODE (y));
2248 }
2249 else
2250 j = REGNO (y);
2251
2252 /* On a REG_WORDS_BIG_ENDIAN machine, point to the last register of a
2253 multiple hard register group of scalar integer registers, so that
2254 for example (reg:DI 0) and (reg:SI 1) will be considered the same
2255 register. */
2256 scalar_int_mode xmode;
2257 if (REG_WORDS_BIG_ENDIAN
2258 && is_a <scalar_int_mode> (GET_MODE (x), &xmode)
2259 && GET_MODE_SIZE (xmode) > UNITS_PER_WORD
2260 && i < FIRST_PSEUDO_REGISTER)
2261 i += hard_regno_nregs (i, xmode) - 1;
2262 scalar_int_mode ymode;
2263 if (REG_WORDS_BIG_ENDIAN
2264 && is_a <scalar_int_mode> (GET_MODE (y), &ymode)
2265 && GET_MODE_SIZE (ymode) > UNITS_PER_WORD
2266 && j < FIRST_PSEUDO_REGISTER)
2267 j += hard_regno_nregs (j, ymode) - 1;
2268
2269 return i == j;
2270 }
2271 /* If two operands must match, because they are really a single
2272 operand of an assembler insn, then two postincrements are invalid
2273 because the assembler insn would increment only once.
2274 On the other hand, a postincrement matches ordinary indexing
2275 if the postincrement is the output operand. */
2276 if (code == POST_DEC || code == POST_INC || code == POST_MODIFY)
2277 return operands_match_p (XEXP (x, 0), y);
2278 /* Two preincrements are invalid
2279 because the assembler insn would increment only once.
2280 On the other hand, a preincrement matches ordinary indexing
2281 if the preincrement is the input operand.
2282 In this case, return 2, since some callers need to do special
2283 things when this happens. */
2284 if (GET_CODE (y) == PRE_DEC || GET_CODE (y) == PRE_INC
2285 || GET_CODE (y) == PRE_MODIFY)
2286 return operands_match_p (x, XEXP (y, 0)) ? 2 : 0;
2287
2288 slow:
2289
2290 /* Now we have disposed of all the cases in which different rtx codes
2291 can match. */
2292 if (code != GET_CODE (y))
2293 return 0;
2294
2295 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
2296 if (GET_MODE (x) != GET_MODE (y))
2297 return 0;
2298
2299 /* MEMs referring to different address space are not equivalent. */
2300 if (code == MEM && MEM_ADDR_SPACE (x) != MEM_ADDR_SPACE (y))
2301 return 0;
2302
2303 switch (code)
2304 {
2305 CASE_CONST_UNIQUE:
2306 return 0;
2307
2308 case CONST_VECTOR:
2309 if (!same_vector_encodings_p (x, y))
2310 return false;
2311 break;
2312
2313 case LABEL_REF:
2314 return label_ref_label (x) == label_ref_label (y);
2315 case SYMBOL_REF:
2316 return XSTR (x, 0) == XSTR (y, 0);
2317
2318 default:
2319 break;
2320 }
2321
2322 /* Compare the elements. If any pair of corresponding elements
2323 fail to match, return 0 for the whole things. */
2324
2325 success_2 = 0;
2326 fmt = GET_RTX_FORMAT (code);
2327 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2328 {
2329 int val, j;
2330 switch (fmt[i])
2331 {
2332 case 'w':
2333 if (XWINT (x, i) != XWINT (y, i))
2334 return 0;
2335 break;
2336
2337 case 'i':
2338 if (XINT (x, i) != XINT (y, i))
2339 return 0;
2340 break;
2341
2342 case 'p':
2343 if (maybe_ne (SUBREG_BYTE (x), SUBREG_BYTE (y)))
2344 return 0;
2345 break;
2346
2347 case 'e':
2348 val = operands_match_p (XEXP (x, i), XEXP (y, i));
2349 if (val == 0)
2350 return 0;
2351 /* If any subexpression returns 2,
2352 we should return 2 if we are successful. */
2353 if (val == 2)
2354 success_2 = 1;
2355 break;
2356
2357 case '0':
2358 break;
2359
2360 case 'E':
2361 if (XVECLEN (x, i) != XVECLEN (y, i))
2362 return 0;
2363 for (j = XVECLEN (x, i) - 1; j >= 0; --j)
2364 {
2365 val = operands_match_p (XVECEXP (x, i, j), XVECEXP (y, i, j));
2366 if (val == 0)
2367 return 0;
2368 if (val == 2)
2369 success_2 = 1;
2370 }
2371 break;
2372
2373 /* It is believed that rtx's at this level will never
2374 contain anything but integers and other rtx's,
2375 except for within LABEL_REFs and SYMBOL_REFs. */
2376 default:
2377 gcc_unreachable ();
2378 }
2379 }
2380 return 1 + success_2;
2381 }
2382
2383 /* Describe the range of registers or memory referenced by X.
2384 If X is a register, set REG_FLAG and put the first register
2385 number into START and the last plus one into END.
2386 If X is a memory reference, put a base address into BASE
2387 and a range of integer offsets into START and END.
2388 If X is pushing on the stack, we can assume it causes no trouble,
2389 so we set the SAFE field. */
2390
2391 static struct decomposition
decompose(rtx x)2392 decompose (rtx x)
2393 {
2394 struct decomposition val;
2395 int all_const = 0, regno;
2396
2397 memset (&val, 0, sizeof (val));
2398
2399 switch (GET_CODE (x))
2400 {
2401 case MEM:
2402 {
2403 rtx base = NULL_RTX, offset = 0;
2404 rtx addr = XEXP (x, 0);
2405
2406 if (GET_CODE (addr) == PRE_DEC || GET_CODE (addr) == PRE_INC
2407 || GET_CODE (addr) == POST_DEC || GET_CODE (addr) == POST_INC)
2408 {
2409 val.base = XEXP (addr, 0);
2410 val.start = -GET_MODE_SIZE (GET_MODE (x));
2411 val.end = GET_MODE_SIZE (GET_MODE (x));
2412 val.safe = REGNO (val.base) == STACK_POINTER_REGNUM;
2413 return val;
2414 }
2415
2416 if (GET_CODE (addr) == PRE_MODIFY || GET_CODE (addr) == POST_MODIFY)
2417 {
2418 if (GET_CODE (XEXP (addr, 1)) == PLUS
2419 && XEXP (addr, 0) == XEXP (XEXP (addr, 1), 0)
2420 && CONSTANT_P (XEXP (XEXP (addr, 1), 1)))
2421 {
2422 val.base = XEXP (addr, 0);
2423 val.start = -INTVAL (XEXP (XEXP (addr, 1), 1));
2424 val.end = INTVAL (XEXP (XEXP (addr, 1), 1));
2425 val.safe = REGNO (val.base) == STACK_POINTER_REGNUM;
2426 return val;
2427 }
2428 }
2429
2430 if (GET_CODE (addr) == CONST)
2431 {
2432 addr = XEXP (addr, 0);
2433 all_const = 1;
2434 }
2435 if (GET_CODE (addr) == PLUS)
2436 {
2437 if (CONSTANT_P (XEXP (addr, 0)))
2438 {
2439 base = XEXP (addr, 1);
2440 offset = XEXP (addr, 0);
2441 }
2442 else if (CONSTANT_P (XEXP (addr, 1)))
2443 {
2444 base = XEXP (addr, 0);
2445 offset = XEXP (addr, 1);
2446 }
2447 }
2448
2449 if (offset == 0)
2450 {
2451 base = addr;
2452 offset = const0_rtx;
2453 }
2454 if (GET_CODE (offset) == CONST)
2455 offset = XEXP (offset, 0);
2456 if (GET_CODE (offset) == PLUS)
2457 {
2458 if (CONST_INT_P (XEXP (offset, 0)))
2459 {
2460 base = gen_rtx_PLUS (GET_MODE (base), base, XEXP (offset, 1));
2461 offset = XEXP (offset, 0);
2462 }
2463 else if (CONST_INT_P (XEXP (offset, 1)))
2464 {
2465 base = gen_rtx_PLUS (GET_MODE (base), base, XEXP (offset, 0));
2466 offset = XEXP (offset, 1);
2467 }
2468 else
2469 {
2470 base = gen_rtx_PLUS (GET_MODE (base), base, offset);
2471 offset = const0_rtx;
2472 }
2473 }
2474 else if (!CONST_INT_P (offset))
2475 {
2476 base = gen_rtx_PLUS (GET_MODE (base), base, offset);
2477 offset = const0_rtx;
2478 }
2479
2480 if (all_const && GET_CODE (base) == PLUS)
2481 base = gen_rtx_CONST (GET_MODE (base), base);
2482
2483 gcc_assert (CONST_INT_P (offset));
2484
2485 val.start = INTVAL (offset);
2486 val.end = val.start + GET_MODE_SIZE (GET_MODE (x));
2487 val.base = base;
2488 }
2489 break;
2490
2491 case REG:
2492 val.reg_flag = 1;
2493 regno = true_regnum (x);
2494 if (regno < 0 || regno >= FIRST_PSEUDO_REGISTER)
2495 {
2496 /* A pseudo with no hard reg. */
2497 val.start = REGNO (x);
2498 val.end = val.start + 1;
2499 }
2500 else
2501 {
2502 /* A hard reg. */
2503 val.start = regno;
2504 val.end = end_hard_regno (GET_MODE (x), regno);
2505 }
2506 break;
2507
2508 case SUBREG:
2509 if (!REG_P (SUBREG_REG (x)))
2510 /* This could be more precise, but it's good enough. */
2511 return decompose (SUBREG_REG (x));
2512 regno = true_regnum (x);
2513 if (regno < 0 || regno >= FIRST_PSEUDO_REGISTER)
2514 return decompose (SUBREG_REG (x));
2515
2516 /* A hard reg. */
2517 val.reg_flag = 1;
2518 val.start = regno;
2519 val.end = regno + subreg_nregs (x);
2520 break;
2521
2522 case SCRATCH:
2523 /* This hasn't been assigned yet, so it can't conflict yet. */
2524 val.safe = 1;
2525 break;
2526
2527 default:
2528 gcc_assert (CONSTANT_P (x));
2529 val.safe = 1;
2530 break;
2531 }
2532 return val;
2533 }
2534
2535 /* Return 1 if altering Y will not modify the value of X.
2536 Y is also described by YDATA, which should be decompose (Y). */
2537
2538 static int
immune_p(rtx x,rtx y,struct decomposition ydata)2539 immune_p (rtx x, rtx y, struct decomposition ydata)
2540 {
2541 struct decomposition xdata;
2542
2543 if (ydata.reg_flag)
2544 /* In this case the decomposition structure contains register
2545 numbers rather than byte offsets. */
2546 return !refers_to_regno_for_reload_p (ydata.start.to_constant (),
2547 ydata.end.to_constant (),
2548 x, (rtx *) 0);
2549 if (ydata.safe)
2550 return 1;
2551
2552 gcc_assert (MEM_P (y));
2553 /* If Y is memory and X is not, Y can't affect X. */
2554 if (!MEM_P (x))
2555 return 1;
2556
2557 xdata = decompose (x);
2558
2559 if (! rtx_equal_p (xdata.base, ydata.base))
2560 {
2561 /* If bases are distinct symbolic constants, there is no overlap. */
2562 if (CONSTANT_P (xdata.base) && CONSTANT_P (ydata.base))
2563 return 1;
2564 /* Constants and stack slots never overlap. */
2565 if (CONSTANT_P (xdata.base)
2566 && (ydata.base == frame_pointer_rtx
2567 || ydata.base == hard_frame_pointer_rtx
2568 || ydata.base == stack_pointer_rtx))
2569 return 1;
2570 if (CONSTANT_P (ydata.base)
2571 && (xdata.base == frame_pointer_rtx
2572 || xdata.base == hard_frame_pointer_rtx
2573 || xdata.base == stack_pointer_rtx))
2574 return 1;
2575 /* If either base is variable, we don't know anything. */
2576 return 0;
2577 }
2578
2579 return known_ge (xdata.start, ydata.end) || known_ge (ydata.start, xdata.end);
2580 }
2581
2582 /* Similar, but calls decompose. */
2583
2584 int
safe_from_earlyclobber(rtx op,rtx clobber)2585 safe_from_earlyclobber (rtx op, rtx clobber)
2586 {
2587 struct decomposition early_data;
2588
2589 early_data = decompose (clobber);
2590 return immune_p (op, clobber, early_data);
2591 }
2592
2593 /* Main entry point of this file: search the body of INSN
2594 for values that need reloading and record them with push_reload.
2595 REPLACE nonzero means record also where the values occur
2596 so that subst_reloads can be used.
2597
2598 IND_LEVELS says how many levels of indirection are supported by this
2599 machine; a value of zero means that a memory reference is not a valid
2600 memory address.
2601
2602 LIVE_KNOWN says we have valid information about which hard
2603 regs are live at each point in the program; this is true when
2604 we are called from global_alloc but false when stupid register
2605 allocation has been done.
2606
2607 RELOAD_REG_P if nonzero is a vector indexed by hard reg number
2608 which is nonnegative if the reg has been commandeered for reloading into.
2609 It is copied into STATIC_RELOAD_REG_P and referenced from there
2610 by various subroutines.
2611
2612 Return TRUE if some operands need to be changed, because of swapping
2613 commutative operands, reg_equiv_address substitution, or whatever. */
2614
2615 int
find_reloads(rtx_insn * insn,int replace,int ind_levels,int live_known,short * reload_reg_p)2616 find_reloads (rtx_insn *insn, int replace, int ind_levels, int live_known,
2617 short *reload_reg_p)
2618 {
2619 int insn_code_number;
2620 int i, j;
2621 int noperands;
2622 /* These start out as the constraints for the insn
2623 and they are chewed up as we consider alternatives. */
2624 const char *constraints[MAX_RECOG_OPERANDS];
2625 /* These are the preferred classes for an operand, or NO_REGS if it isn't
2626 a register. */
2627 enum reg_class preferred_class[MAX_RECOG_OPERANDS];
2628 char pref_or_nothing[MAX_RECOG_OPERANDS];
2629 /* Nonzero for a MEM operand whose entire address needs a reload.
2630 May be -1 to indicate the entire address may or may not need a reload. */
2631 int address_reloaded[MAX_RECOG_OPERANDS];
2632 /* Nonzero for an address operand that needs to be completely reloaded.
2633 May be -1 to indicate the entire operand may or may not need a reload. */
2634 int address_operand_reloaded[MAX_RECOG_OPERANDS];
2635 /* Value of enum reload_type to use for operand. */
2636 enum reload_type operand_type[MAX_RECOG_OPERANDS];
2637 /* Value of enum reload_type to use within address of operand. */
2638 enum reload_type address_type[MAX_RECOG_OPERANDS];
2639 /* Save the usage of each operand. */
2640 enum reload_usage { RELOAD_READ, RELOAD_READ_WRITE, RELOAD_WRITE } modified[MAX_RECOG_OPERANDS];
2641 int no_input_reloads = 0, no_output_reloads = 0;
2642 int n_alternatives;
2643 reg_class_t this_alternative[MAX_RECOG_OPERANDS];
2644 char this_alternative_match_win[MAX_RECOG_OPERANDS];
2645 char this_alternative_win[MAX_RECOG_OPERANDS];
2646 char this_alternative_offmemok[MAX_RECOG_OPERANDS];
2647 char this_alternative_earlyclobber[MAX_RECOG_OPERANDS];
2648 int this_alternative_matches[MAX_RECOG_OPERANDS];
2649 reg_class_t goal_alternative[MAX_RECOG_OPERANDS];
2650 int this_alternative_number;
2651 int goal_alternative_number = 0;
2652 int operand_reloadnum[MAX_RECOG_OPERANDS];
2653 int goal_alternative_matches[MAX_RECOG_OPERANDS];
2654 int goal_alternative_matched[MAX_RECOG_OPERANDS];
2655 char goal_alternative_match_win[MAX_RECOG_OPERANDS];
2656 char goal_alternative_win[MAX_RECOG_OPERANDS];
2657 char goal_alternative_offmemok[MAX_RECOG_OPERANDS];
2658 char goal_alternative_earlyclobber[MAX_RECOG_OPERANDS];
2659 int goal_alternative_swapped;
2660 int best;
2661 int commutative;
2662 char operands_match[MAX_RECOG_OPERANDS][MAX_RECOG_OPERANDS];
2663 rtx substed_operand[MAX_RECOG_OPERANDS];
2664 rtx body = PATTERN (insn);
2665 rtx set = single_set (insn);
2666 int goal_earlyclobber = 0, this_earlyclobber;
2667 machine_mode operand_mode[MAX_RECOG_OPERANDS];
2668 int retval = 0;
2669
2670 this_insn = insn;
2671 n_reloads = 0;
2672 n_replacements = 0;
2673 n_earlyclobbers = 0;
2674 replace_reloads = replace;
2675 hard_regs_live_known = live_known;
2676 static_reload_reg_p = reload_reg_p;
2677
2678 if (JUMP_P (insn) && INSN_CODE (insn) < 0)
2679 {
2680 extract_insn (insn);
2681 for (i = 0; i < recog_data.n_operands; i++)
2682 if (recog_data.operand_type[i] != OP_IN)
2683 break;
2684 if (i < recog_data.n_operands)
2685 {
2686 error_for_asm (insn,
2687 "the target does not support %<asm goto%> "
2688 "with outputs in %<asm%>");
2689 ira_nullify_asm_goto (insn);
2690 return 0;
2691 }
2692 }
2693
2694 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output reloads. */
2695 if (JUMP_P (insn) || CALL_P (insn))
2696 no_output_reloads = 1;
2697
2698 /* The eliminated forms of any secondary memory locations are per-insn, so
2699 clear them out here. */
2700
2701 if (secondary_memlocs_elim_used)
2702 {
2703 memset (secondary_memlocs_elim, 0,
2704 sizeof (secondary_memlocs_elim[0]) * secondary_memlocs_elim_used);
2705 secondary_memlocs_elim_used = 0;
2706 }
2707
2708 /* Dispose quickly of (set (reg..) (reg..)) if both have hard regs and it
2709 is cheap to move between them. If it is not, there may not be an insn
2710 to do the copy, so we may need a reload. */
2711 if (GET_CODE (body) == SET
2712 && REG_P (SET_DEST (body))
2713 && REGNO (SET_DEST (body)) < FIRST_PSEUDO_REGISTER
2714 && REG_P (SET_SRC (body))
2715 && REGNO (SET_SRC (body)) < FIRST_PSEUDO_REGISTER
2716 && register_move_cost (GET_MODE (SET_SRC (body)),
2717 REGNO_REG_CLASS (REGNO (SET_SRC (body))),
2718 REGNO_REG_CLASS (REGNO (SET_DEST (body)))) == 2)
2719 return 0;
2720
2721 extract_insn (insn);
2722
2723 noperands = reload_n_operands = recog_data.n_operands;
2724 n_alternatives = recog_data.n_alternatives;
2725
2726 /* Just return "no reloads" if insn has no operands with constraints. */
2727 if (noperands == 0 || n_alternatives == 0)
2728 return 0;
2729
2730 insn_code_number = INSN_CODE (insn);
2731 this_insn_is_asm = insn_code_number < 0;
2732
2733 memcpy (operand_mode, recog_data.operand_mode,
2734 noperands * sizeof (machine_mode));
2735 memcpy (constraints, recog_data.constraints,
2736 noperands * sizeof (const char *));
2737
2738 commutative = -1;
2739
2740 /* If we will need to know, later, whether some pair of operands
2741 are the same, we must compare them now and save the result.
2742 Reloading the base and index registers will clobber them
2743 and afterward they will fail to match. */
2744
2745 for (i = 0; i < noperands; i++)
2746 {
2747 const char *p;
2748 int c;
2749 char *end;
2750
2751 substed_operand[i] = recog_data.operand[i];
2752 p = constraints[i];
2753
2754 modified[i] = RELOAD_READ;
2755
2756 /* Scan this operand's constraint to see if it is an output operand,
2757 an in-out operand, is commutative, or should match another. */
2758
2759 while ((c = *p))
2760 {
2761 p += CONSTRAINT_LEN (c, p);
2762 switch (c)
2763 {
2764 case '=':
2765 modified[i] = RELOAD_WRITE;
2766 break;
2767 case '+':
2768 modified[i] = RELOAD_READ_WRITE;
2769 break;
2770 case '%':
2771 {
2772 /* The last operand should not be marked commutative. */
2773 gcc_assert (i != noperands - 1);
2774
2775 /* We currently only support one commutative pair of
2776 operands. Some existing asm code currently uses more
2777 than one pair. Previously, that would usually work,
2778 but sometimes it would crash the compiler. We
2779 continue supporting that case as well as we can by
2780 silently ignoring all but the first pair. In the
2781 future we may handle it correctly. */
2782 if (commutative < 0)
2783 commutative = i;
2784 else
2785 gcc_assert (this_insn_is_asm);
2786 }
2787 break;
2788 /* Use of ISDIGIT is tempting here, but it may get expensive because
2789 of locale support we don't want. */
2790 case '0': case '1': case '2': case '3': case '4':
2791 case '5': case '6': case '7': case '8': case '9':
2792 {
2793 c = strtoul (p - 1, &end, 10);
2794 p = end;
2795
2796 operands_match[c][i]
2797 = operands_match_p (recog_data.operand[c],
2798 recog_data.operand[i]);
2799
2800 /* An operand may not match itself. */
2801 gcc_assert (c != i);
2802
2803 /* If C can be commuted with C+1, and C might need to match I,
2804 then C+1 might also need to match I. */
2805 if (commutative >= 0)
2806 {
2807 if (c == commutative || c == commutative + 1)
2808 {
2809 int other = c + (c == commutative ? 1 : -1);
2810 operands_match[other][i]
2811 = operands_match_p (recog_data.operand[other],
2812 recog_data.operand[i]);
2813 }
2814 if (i == commutative || i == commutative + 1)
2815 {
2816 int other = i + (i == commutative ? 1 : -1);
2817 operands_match[c][other]
2818 = operands_match_p (recog_data.operand[c],
2819 recog_data.operand[other]);
2820 }
2821 /* Note that C is supposed to be less than I.
2822 No need to consider altering both C and I because in
2823 that case we would alter one into the other. */
2824 }
2825 }
2826 }
2827 }
2828 }
2829
2830 /* Examine each operand that is a memory reference or memory address
2831 and reload parts of the addresses into index registers.
2832 Also here any references to pseudo regs that didn't get hard regs
2833 but are equivalent to constants get replaced in the insn itself
2834 with those constants. Nobody will ever see them again.
2835
2836 Finally, set up the preferred classes of each operand. */
2837
2838 for (i = 0; i < noperands; i++)
2839 {
2840 RTX_CODE code = GET_CODE (recog_data.operand[i]);
2841
2842 address_reloaded[i] = 0;
2843 address_operand_reloaded[i] = 0;
2844 operand_type[i] = (modified[i] == RELOAD_READ ? RELOAD_FOR_INPUT
2845 : modified[i] == RELOAD_WRITE ? RELOAD_FOR_OUTPUT
2846 : RELOAD_OTHER);
2847 address_type[i]
2848 = (modified[i] == RELOAD_READ ? RELOAD_FOR_INPUT_ADDRESS
2849 : modified[i] == RELOAD_WRITE ? RELOAD_FOR_OUTPUT_ADDRESS
2850 : RELOAD_OTHER);
2851
2852 if (*constraints[i] == 0)
2853 /* Ignore things like match_operator operands. */
2854 ;
2855 else if (insn_extra_address_constraint
2856 (lookup_constraint (constraints[i])))
2857 {
2858 address_operand_reloaded[i]
2859 = find_reloads_address (recog_data.operand_mode[i], (rtx*) 0,
2860 recog_data.operand[i],
2861 recog_data.operand_loc[i],
2862 i, operand_type[i], ind_levels, insn);
2863
2864 /* If we now have a simple operand where we used to have a
2865 PLUS or MULT or ASHIFT, re-recognize and try again. */
2866 if ((OBJECT_P (*recog_data.operand_loc[i])
2867 || GET_CODE (*recog_data.operand_loc[i]) == SUBREG)
2868 && (GET_CODE (recog_data.operand[i]) == MULT
2869 || GET_CODE (recog_data.operand[i]) == ASHIFT
2870 || GET_CODE (recog_data.operand[i]) == PLUS))
2871 {
2872 INSN_CODE (insn) = -1;
2873 retval = find_reloads (insn, replace, ind_levels, live_known,
2874 reload_reg_p);
2875 return retval;
2876 }
2877
2878 recog_data.operand[i] = *recog_data.operand_loc[i];
2879 substed_operand[i] = recog_data.operand[i];
2880
2881 /* Address operands are reloaded in their existing mode,
2882 no matter what is specified in the machine description. */
2883 operand_mode[i] = GET_MODE (recog_data.operand[i]);
2884
2885 /* If the address is a single CONST_INT pick address mode
2886 instead otherwise we will later not know in which mode
2887 the reload should be performed. */
2888 if (operand_mode[i] == VOIDmode)
2889 operand_mode[i] = Pmode;
2890
2891 }
2892 else if (code == MEM)
2893 {
2894 address_reloaded[i]
2895 = find_reloads_address (GET_MODE (recog_data.operand[i]),
2896 recog_data.operand_loc[i],
2897 XEXP (recog_data.operand[i], 0),
2898 &XEXP (recog_data.operand[i], 0),
2899 i, address_type[i], ind_levels, insn);
2900 recog_data.operand[i] = *recog_data.operand_loc[i];
2901 substed_operand[i] = recog_data.operand[i];
2902 }
2903 else if (code == SUBREG)
2904 {
2905 rtx reg = SUBREG_REG (recog_data.operand[i]);
2906 rtx op
2907 = find_reloads_toplev (recog_data.operand[i], i, address_type[i],
2908 ind_levels,
2909 set != 0
2910 && &SET_DEST (set) == recog_data.operand_loc[i],
2911 insn,
2912 &address_reloaded[i]);
2913
2914 /* If we made a MEM to load (a part of) the stackslot of a pseudo
2915 that didn't get a hard register, emit a USE with a REG_EQUAL
2916 note in front so that we might inherit a previous, possibly
2917 wider reload. */
2918
2919 if (replace
2920 && MEM_P (op)
2921 && REG_P (reg)
2922 && known_ge (GET_MODE_SIZE (GET_MODE (reg)),
2923 GET_MODE_SIZE (GET_MODE (op)))
2924 && reg_equiv_constant (REGNO (reg)) == 0)
2925 set_unique_reg_note (emit_insn_before (gen_rtx_USE (VOIDmode, reg),
2926 insn),
2927 REG_EQUAL, reg_equiv_memory_loc (REGNO (reg)));
2928
2929 substed_operand[i] = recog_data.operand[i] = op;
2930 }
2931 else if (code == PLUS || GET_RTX_CLASS (code) == RTX_UNARY)
2932 /* We can get a PLUS as an "operand" as a result of register
2933 elimination. See eliminate_regs and gen_reload. We handle
2934 a unary operator by reloading the operand. */
2935 substed_operand[i] = recog_data.operand[i]
2936 = find_reloads_toplev (recog_data.operand[i], i, address_type[i],
2937 ind_levels, 0, insn,
2938 &address_reloaded[i]);
2939 else if (code == REG)
2940 {
2941 /* This is equivalent to calling find_reloads_toplev.
2942 The code is duplicated for speed.
2943 When we find a pseudo always equivalent to a constant,
2944 we replace it by the constant. We must be sure, however,
2945 that we don't try to replace it in the insn in which it
2946 is being set. */
2947 int regno = REGNO (recog_data.operand[i]);
2948 if (reg_equiv_constant (regno) != 0
2949 && (set == 0 || &SET_DEST (set) != recog_data.operand_loc[i]))
2950 {
2951 /* Record the existing mode so that the check if constants are
2952 allowed will work when operand_mode isn't specified. */
2953
2954 if (operand_mode[i] == VOIDmode)
2955 operand_mode[i] = GET_MODE (recog_data.operand[i]);
2956
2957 substed_operand[i] = recog_data.operand[i]
2958 = reg_equiv_constant (regno);
2959 }
2960 if (reg_equiv_memory_loc (regno) != 0
2961 && (reg_equiv_address (regno) != 0 || num_not_at_initial_offset))
2962 /* We need not give a valid is_set_dest argument since the case
2963 of a constant equivalence was checked above. */
2964 substed_operand[i] = recog_data.operand[i]
2965 = find_reloads_toplev (recog_data.operand[i], i, address_type[i],
2966 ind_levels, 0, insn,
2967 &address_reloaded[i]);
2968 }
2969 /* If the operand is still a register (we didn't replace it with an
2970 equivalent), get the preferred class to reload it into. */
2971 code = GET_CODE (recog_data.operand[i]);
2972 preferred_class[i]
2973 = ((code == REG && REGNO (recog_data.operand[i])
2974 >= FIRST_PSEUDO_REGISTER)
2975 ? reg_preferred_class (REGNO (recog_data.operand[i]))
2976 : NO_REGS);
2977 pref_or_nothing[i]
2978 = (code == REG
2979 && REGNO (recog_data.operand[i]) >= FIRST_PSEUDO_REGISTER
2980 && reg_alternate_class (REGNO (recog_data.operand[i])) == NO_REGS);
2981 }
2982
2983 /* If this is simply a copy from operand 1 to operand 0, merge the
2984 preferred classes for the operands. */
2985 if (set != 0 && noperands >= 2 && recog_data.operand[0] == SET_DEST (set)
2986 && recog_data.operand[1] == SET_SRC (set))
2987 {
2988 preferred_class[0] = preferred_class[1]
2989 = reg_class_subunion[(int) preferred_class[0]][(int) preferred_class[1]];
2990 pref_or_nothing[0] |= pref_or_nothing[1];
2991 pref_or_nothing[1] |= pref_or_nothing[0];
2992 }
2993
2994 /* Now see what we need for pseudo-regs that didn't get hard regs
2995 or got the wrong kind of hard reg. For this, we must consider
2996 all the operands together against the register constraints. */
2997
2998 best = MAX_RECOG_OPERANDS * 2 + 600;
2999
3000 goal_alternative_swapped = 0;
3001
3002 /* The constraints are made of several alternatives.
3003 Each operand's constraint looks like foo,bar,... with commas
3004 separating the alternatives. The first alternatives for all
3005 operands go together, the second alternatives go together, etc.
3006
3007 First loop over alternatives. */
3008
3009 alternative_mask enabled = get_enabled_alternatives (insn);
3010 for (this_alternative_number = 0;
3011 this_alternative_number < n_alternatives;
3012 this_alternative_number++)
3013 {
3014 int swapped;
3015
3016 if (!TEST_BIT (enabled, this_alternative_number))
3017 {
3018 int i;
3019
3020 for (i = 0; i < recog_data.n_operands; i++)
3021 constraints[i] = skip_alternative (constraints[i]);
3022
3023 continue;
3024 }
3025
3026 /* If insn is commutative (it's safe to exchange a certain pair
3027 of operands) then we need to try each alternative twice, the
3028 second time matching those two operands as if we had
3029 exchanged them. To do this, really exchange them in
3030 operands. */
3031 for (swapped = 0; swapped < (commutative >= 0 ? 2 : 1); swapped++)
3032 {
3033 /* Loop over operands for one constraint alternative. */
3034 /* LOSERS counts those that don't fit this alternative
3035 and would require loading. */
3036 int losers = 0;
3037 /* BAD is set to 1 if it some operand can't fit this alternative
3038 even after reloading. */
3039 int bad = 0;
3040 /* REJECT is a count of how undesirable this alternative says it is
3041 if any reloading is required. If the alternative matches exactly
3042 then REJECT is ignored, but otherwise it gets this much
3043 counted against it in addition to the reloading needed. Each
3044 ? counts three times here since we want the disparaging caused by
3045 a bad register class to only count 1/3 as much. */
3046 int reject = 0;
3047
3048 if (swapped)
3049 {
3050 recog_data.operand[commutative] = substed_operand[commutative + 1];
3051 recog_data.operand[commutative + 1] = substed_operand[commutative];
3052 /* Swap the duplicates too. */
3053 for (i = 0; i < recog_data.n_dups; i++)
3054 if (recog_data.dup_num[i] == commutative
3055 || recog_data.dup_num[i] == commutative + 1)
3056 *recog_data.dup_loc[i]
3057 = recog_data.operand[(int) recog_data.dup_num[i]];
3058
3059 std::swap (preferred_class[commutative],
3060 preferred_class[commutative + 1]);
3061 std::swap (pref_or_nothing[commutative],
3062 pref_or_nothing[commutative + 1]);
3063 std::swap (address_reloaded[commutative],
3064 address_reloaded[commutative + 1]);
3065 }
3066
3067 this_earlyclobber = 0;
3068
3069 for (i = 0; i < noperands; i++)
3070 {
3071 const char *p = constraints[i];
3072 char *end;
3073 int len;
3074 int win = 0;
3075 int did_match = 0;
3076 /* 0 => this operand can be reloaded somehow for this alternative. */
3077 int badop = 1;
3078 /* 0 => this operand can be reloaded if the alternative allows regs. */
3079 int winreg = 0;
3080 int c;
3081 int m;
3082 rtx operand = recog_data.operand[i];
3083 int offset = 0;
3084 /* Nonzero means this is a MEM that must be reloaded into a reg
3085 regardless of what the constraint says. */
3086 int force_reload = 0;
3087 int offmemok = 0;
3088 /* Nonzero if a constant forced into memory would be OK for this
3089 operand. */
3090 int constmemok = 0;
3091 int earlyclobber = 0;
3092 enum constraint_num cn;
3093 enum reg_class cl;
3094
3095 /* If the predicate accepts a unary operator, it means that
3096 we need to reload the operand, but do not do this for
3097 match_operator and friends. */
3098 if (UNARY_P (operand) && *p != 0)
3099 operand = XEXP (operand, 0);
3100
3101 /* If the operand is a SUBREG, extract
3102 the REG or MEM (or maybe even a constant) within.
3103 (Constants can occur as a result of reg_equiv_constant.) */
3104
3105 while (GET_CODE (operand) == SUBREG)
3106 {
3107 /* Offset only matters when operand is a REG and
3108 it is a hard reg. This is because it is passed
3109 to reg_fits_class_p if it is a REG and all pseudos
3110 return 0 from that function. */
3111 if (REG_P (SUBREG_REG (operand))
3112 && REGNO (SUBREG_REG (operand)) < FIRST_PSEUDO_REGISTER)
3113 {
3114 if (simplify_subreg_regno (REGNO (SUBREG_REG (operand)),
3115 GET_MODE (SUBREG_REG (operand)),
3116 SUBREG_BYTE (operand),
3117 GET_MODE (operand)) < 0)
3118 force_reload = 1;
3119 offset += subreg_regno_offset (REGNO (SUBREG_REG (operand)),
3120 GET_MODE (SUBREG_REG (operand)),
3121 SUBREG_BYTE (operand),
3122 GET_MODE (operand));
3123 }
3124 operand = SUBREG_REG (operand);
3125 /* Force reload if this is a constant or PLUS or if there may
3126 be a problem accessing OPERAND in the outer mode. */
3127 scalar_int_mode inner_mode;
3128 if (CONSTANT_P (operand)
3129 || GET_CODE (operand) == PLUS
3130 /* We must force a reload of paradoxical SUBREGs
3131 of a MEM because the alignment of the inner value
3132 may not be enough to do the outer reference. On
3133 big-endian machines, it may also reference outside
3134 the object.
3135
3136 On machines that extend byte operations and we have a
3137 SUBREG where both the inner and outer modes are no wider
3138 than a word and the inner mode is narrower, is integral,
3139 and gets extended when loaded from memory, combine.cc has
3140 made assumptions about the behavior of the machine in such
3141 register access. If the data is, in fact, in memory we
3142 must always load using the size assumed to be in the
3143 register and let the insn do the different-sized
3144 accesses.
3145
3146 This is doubly true if WORD_REGISTER_OPERATIONS. In
3147 this case eliminate_regs has left non-paradoxical
3148 subregs for push_reload to see. Make sure it does
3149 by forcing the reload.
3150
3151 ??? When is it right at this stage to have a subreg
3152 of a mem that is _not_ to be handled specially? IMO
3153 those should have been reduced to just a mem. */
3154 || ((MEM_P (operand)
3155 || (REG_P (operand)
3156 && REGNO (operand) >= FIRST_PSEUDO_REGISTER))
3157 && (WORD_REGISTER_OPERATIONS
3158 || (((maybe_lt
3159 (GET_MODE_BITSIZE (GET_MODE (operand)),
3160 BIGGEST_ALIGNMENT))
3161 && (paradoxical_subreg_p
3162 (operand_mode[i], GET_MODE (operand)))))
3163 || BYTES_BIG_ENDIAN
3164 || (known_le (GET_MODE_SIZE (operand_mode[i]),
3165 UNITS_PER_WORD)
3166 && (is_a <scalar_int_mode>
3167 (GET_MODE (operand), &inner_mode))
3168 && (GET_MODE_SIZE (inner_mode)
3169 <= UNITS_PER_WORD)
3170 && paradoxical_subreg_p (operand_mode[i],
3171 inner_mode)
3172 && LOAD_EXTEND_OP (inner_mode) != UNKNOWN)))
3173 /* We must force a reload of a SUBREG's inner expression
3174 if it is a pseudo that will become a MEM and the MEM
3175 has a mode-dependent address, as in that case we
3176 obviously cannot change the mode of the MEM to that
3177 of the containing SUBREG as that would change the
3178 interpretation of the address. */
3179 || (REG_P (operand)
3180 && REGNO (operand) >= FIRST_PSEUDO_REGISTER
3181 && reg_equiv_mem (REGNO (operand))
3182 && (mode_dependent_address_p
3183 (XEXP (reg_equiv_mem (REGNO (operand)), 0),
3184 (MEM_ADDR_SPACE
3185 (reg_equiv_mem (REGNO (operand)))))))
3186 )
3187 force_reload = 1;
3188 }
3189
3190 this_alternative[i] = NO_REGS;
3191 this_alternative_win[i] = 0;
3192 this_alternative_match_win[i] = 0;
3193 this_alternative_offmemok[i] = 0;
3194 this_alternative_earlyclobber[i] = 0;
3195 this_alternative_matches[i] = -1;
3196
3197 /* An empty constraint or empty alternative
3198 allows anything which matched the pattern. */
3199 if (*p == 0 || *p == ',')
3200 win = 1, badop = 0;
3201
3202 /* Scan this alternative's specs for this operand;
3203 set WIN if the operand fits any letter in this alternative.
3204 Otherwise, clear BADOP if this operand could
3205 fit some letter after reloads,
3206 or set WINREG if this operand could fit after reloads
3207 provided the constraint allows some registers. */
3208
3209 do
3210 switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c)
3211 {
3212 case '\0':
3213 len = 0;
3214 break;
3215 case ',':
3216 c = '\0';
3217 break;
3218
3219 case '?':
3220 reject += 6;
3221 break;
3222
3223 case '!':
3224 reject = 600;
3225 break;
3226
3227 case '#':
3228 /* Ignore rest of this alternative as far as
3229 reloading is concerned. */
3230 do
3231 p++;
3232 while (*p && *p != ',');
3233 len = 0;
3234 break;
3235
3236 case '0': case '1': case '2': case '3': case '4':
3237 case '5': case '6': case '7': case '8': case '9':
3238 m = strtoul (p, &end, 10);
3239 p = end;
3240 len = 0;
3241
3242 this_alternative_matches[i] = m;
3243 /* We are supposed to match a previous operand.
3244 If we do, we win if that one did.
3245 If we do not, count both of the operands as losers.
3246 (This is too conservative, since most of the time
3247 only a single reload insn will be needed to make
3248 the two operands win. As a result, this alternative
3249 may be rejected when it is actually desirable.) */
3250 if ((swapped && (m != commutative || i != commutative + 1))
3251 /* If we are matching as if two operands were swapped,
3252 also pretend that operands_match had been computed
3253 with swapped.
3254 But if I is the second of those and C is the first,
3255 don't exchange them, because operands_match is valid
3256 only on one side of its diagonal. */
3257 ? (operands_match
3258 [(m == commutative || m == commutative + 1)
3259 ? 2 * commutative + 1 - m : m]
3260 [(i == commutative || i == commutative + 1)
3261 ? 2 * commutative + 1 - i : i])
3262 : operands_match[m][i])
3263 {
3264 /* If we are matching a non-offsettable address where an
3265 offsettable address was expected, then we must reject
3266 this combination, because we can't reload it. */
3267 if (this_alternative_offmemok[m]
3268 && MEM_P (recog_data.operand[m])
3269 && this_alternative[m] == NO_REGS
3270 && ! this_alternative_win[m])
3271 bad = 1;
3272
3273 did_match = this_alternative_win[m];
3274 }
3275 else
3276 {
3277 /* Operands don't match. */
3278 rtx value;
3279 int loc1, loc2;
3280 /* Retroactively mark the operand we had to match
3281 as a loser, if it wasn't already. */
3282 if (this_alternative_win[m])
3283 losers++;
3284 this_alternative_win[m] = 0;
3285 if (this_alternative[m] == NO_REGS)
3286 bad = 1;
3287 /* But count the pair only once in the total badness of
3288 this alternative, if the pair can be a dummy reload.
3289 The pointers in operand_loc are not swapped; swap
3290 them by hand if necessary. */
3291 if (swapped && i == commutative)
3292 loc1 = commutative + 1;
3293 else if (swapped && i == commutative + 1)
3294 loc1 = commutative;
3295 else
3296 loc1 = i;
3297 if (swapped && m == commutative)
3298 loc2 = commutative + 1;
3299 else if (swapped && m == commutative + 1)
3300 loc2 = commutative;
3301 else
3302 loc2 = m;
3303 value
3304 = find_dummy_reload (recog_data.operand[i],
3305 recog_data.operand[m],
3306 recog_data.operand_loc[loc1],
3307 recog_data.operand_loc[loc2],
3308 operand_mode[i], operand_mode[m],
3309 this_alternative[m], -1,
3310 this_alternative_earlyclobber[m]);
3311
3312 if (value != 0)
3313 losers--;
3314 }
3315 /* This can be fixed with reloads if the operand
3316 we are supposed to match can be fixed with reloads. */
3317 badop = 0;
3318 this_alternative[i] = this_alternative[m];
3319
3320 /* If we have to reload this operand and some previous
3321 operand also had to match the same thing as this
3322 operand, we don't know how to do that. So reject this
3323 alternative. */
3324 if (! did_match || force_reload)
3325 for (j = 0; j < i; j++)
3326 if (this_alternative_matches[j]
3327 == this_alternative_matches[i])
3328 {
3329 badop = 1;
3330 break;
3331 }
3332 break;
3333
3334 case 'p':
3335 /* All necessary reloads for an address_operand
3336 were handled in find_reloads_address. */
3337 this_alternative[i]
3338 = base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
3339 ADDRESS, SCRATCH);
3340 win = 1;
3341 badop = 0;
3342 break;
3343
3344 case TARGET_MEM_CONSTRAINT:
3345 if (force_reload)
3346 break;
3347 if (MEM_P (operand)
3348 || (REG_P (operand)
3349 && REGNO (operand) >= FIRST_PSEUDO_REGISTER
3350 && reg_renumber[REGNO (operand)] < 0))
3351 win = 1;
3352 if (CONST_POOL_OK_P (operand_mode[i], operand))
3353 badop = 0;
3354 constmemok = 1;
3355 break;
3356
3357 case '<':
3358 if (MEM_P (operand)
3359 && ! address_reloaded[i]
3360 && (GET_CODE (XEXP (operand, 0)) == PRE_DEC
3361 || GET_CODE (XEXP (operand, 0)) == POST_DEC))
3362 win = 1;
3363 break;
3364
3365 case '>':
3366 if (MEM_P (operand)
3367 && ! address_reloaded[i]
3368 && (GET_CODE (XEXP (operand, 0)) == PRE_INC
3369 || GET_CODE (XEXP (operand, 0)) == POST_INC))
3370 win = 1;
3371 break;
3372
3373 /* Memory operand whose address is not offsettable. */
3374 case 'V':
3375 if (force_reload)
3376 break;
3377 if (MEM_P (operand)
3378 && ! (ind_levels ? offsettable_memref_p (operand)
3379 : offsettable_nonstrict_memref_p (operand))
3380 /* Certain mem addresses will become offsettable
3381 after they themselves are reloaded. This is important;
3382 we don't want our own handling of unoffsettables
3383 to override the handling of reg_equiv_address. */
3384 && !(REG_P (XEXP (operand, 0))
3385 && (ind_levels == 0
3386 || reg_equiv_address (REGNO (XEXP (operand, 0))) != 0)))
3387 win = 1;
3388 break;
3389
3390 /* Memory operand whose address is offsettable. */
3391 case 'o':
3392 if (force_reload)
3393 break;
3394 if ((MEM_P (operand)
3395 /* If IND_LEVELS, find_reloads_address won't reload a
3396 pseudo that didn't get a hard reg, so we have to
3397 reject that case. */
3398 && ((ind_levels ? offsettable_memref_p (operand)
3399 : offsettable_nonstrict_memref_p (operand))
3400 /* A reloaded address is offsettable because it is now
3401 just a simple register indirect. */
3402 || address_reloaded[i] == 1))
3403 || (REG_P (operand)
3404 && REGNO (operand) >= FIRST_PSEUDO_REGISTER
3405 && reg_renumber[REGNO (operand)] < 0
3406 /* If reg_equiv_address is nonzero, we will be
3407 loading it into a register; hence it will be
3408 offsettable, but we cannot say that reg_equiv_mem
3409 is offsettable without checking. */
3410 && ((reg_equiv_mem (REGNO (operand)) != 0
3411 && offsettable_memref_p (reg_equiv_mem (REGNO (operand))))
3412 || (reg_equiv_address (REGNO (operand)) != 0))))
3413 win = 1;
3414 if (CONST_POOL_OK_P (operand_mode[i], operand)
3415 || MEM_P (operand))
3416 badop = 0;
3417 constmemok = 1;
3418 offmemok = 1;
3419 break;
3420
3421 case '&':
3422 /* Output operand that is stored before the need for the
3423 input operands (and their index registers) is over. */
3424 earlyclobber = 1, this_earlyclobber = 1;
3425 break;
3426
3427 case 'X':
3428 force_reload = 0;
3429 win = 1;
3430 break;
3431
3432 case 'g':
3433 if (! force_reload
3434 /* A PLUS is never a valid operand, but reload can make
3435 it from a register when eliminating registers. */
3436 && GET_CODE (operand) != PLUS
3437 /* A SCRATCH is not a valid operand. */
3438 && GET_CODE (operand) != SCRATCH
3439 && (! CONSTANT_P (operand)
3440 || ! flag_pic
3441 || LEGITIMATE_PIC_OPERAND_P (operand))
3442 && (GENERAL_REGS == ALL_REGS
3443 || !REG_P (operand)
3444 || (REGNO (operand) >= FIRST_PSEUDO_REGISTER
3445 && reg_renumber[REGNO (operand)] < 0)))
3446 win = 1;
3447 cl = GENERAL_REGS;
3448 goto reg;
3449
3450 default:
3451 cn = lookup_constraint (p);
3452 switch (get_constraint_type (cn))
3453 {
3454 case CT_REGISTER:
3455 cl = reg_class_for_constraint (cn);
3456 if (cl != NO_REGS)
3457 goto reg;
3458 break;
3459
3460 case CT_CONST_INT:
3461 if (CONST_INT_P (operand)
3462 && (insn_const_int_ok_for_constraint
3463 (INTVAL (operand), cn)))
3464 win = true;
3465 break;
3466
3467 case CT_MEMORY:
3468 case CT_RELAXED_MEMORY:
3469 if (force_reload)
3470 break;
3471 if (constraint_satisfied_p (operand, cn))
3472 win = 1;
3473 /* If the address was already reloaded,
3474 we win as well. */
3475 else if (MEM_P (operand) && address_reloaded[i] == 1)
3476 win = 1;
3477 /* Likewise if the address will be reloaded because
3478 reg_equiv_address is nonzero. For reg_equiv_mem
3479 we have to check. */
3480 else if (REG_P (operand)
3481 && REGNO (operand) >= FIRST_PSEUDO_REGISTER
3482 && reg_renumber[REGNO (operand)] < 0
3483 && ((reg_equiv_mem (REGNO (operand)) != 0
3484 && (constraint_satisfied_p
3485 (reg_equiv_mem (REGNO (operand)),
3486 cn)))
3487 || (reg_equiv_address (REGNO (operand))
3488 != 0)))
3489 win = 1;
3490
3491 /* If we didn't already win, we can reload
3492 constants via force_const_mem, and other
3493 MEMs by reloading the address like for 'o'. */
3494 if (CONST_POOL_OK_P (operand_mode[i], operand)
3495 || MEM_P (operand))
3496 badop = 0;
3497 constmemok = 1;
3498 offmemok = 1;
3499 break;
3500
3501 case CT_SPECIAL_MEMORY:
3502 if (force_reload)
3503 break;
3504 if (constraint_satisfied_p (operand, cn))
3505 win = 1;
3506 /* Likewise if the address will be reloaded because
3507 reg_equiv_address is nonzero. For reg_equiv_mem
3508 we have to check. */
3509 else if (REG_P (operand)
3510 && REGNO (operand) >= FIRST_PSEUDO_REGISTER
3511 && reg_renumber[REGNO (operand)] < 0
3512 && reg_equiv_mem (REGNO (operand)) != 0
3513 && (constraint_satisfied_p
3514 (reg_equiv_mem (REGNO (operand)), cn)))
3515 win = 1;
3516 break;
3517
3518 case CT_ADDRESS:
3519 if (constraint_satisfied_p (operand, cn))
3520 win = 1;
3521
3522 /* If we didn't already win, we can reload
3523 the address into a base register. */
3524 this_alternative[i]
3525 = base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
3526 ADDRESS, SCRATCH);
3527 badop = 0;
3528 break;
3529
3530 case CT_FIXED_FORM:
3531 if (constraint_satisfied_p (operand, cn))
3532 win = 1;
3533 break;
3534 }
3535 break;
3536
3537 reg:
3538 this_alternative[i]
3539 = reg_class_subunion[this_alternative[i]][cl];
3540 if (GET_MODE (operand) == BLKmode)
3541 break;
3542 winreg = 1;
3543 if (REG_P (operand)
3544 && reg_fits_class_p (operand, this_alternative[i],
3545 offset, GET_MODE (recog_data.operand[i])))
3546 win = 1;
3547 break;
3548 }
3549 while ((p += len), c);
3550
3551 if (swapped == (commutative >= 0 ? 1 : 0))
3552 constraints[i] = p;
3553
3554 /* If this operand could be handled with a reg,
3555 and some reg is allowed, then this operand can be handled. */
3556 if (winreg && this_alternative[i] != NO_REGS
3557 && (win || !class_only_fixed_regs[this_alternative[i]]))
3558 badop = 0;
3559
3560 /* Record which operands fit this alternative. */
3561 this_alternative_earlyclobber[i] = earlyclobber;
3562 if (win && ! force_reload)
3563 this_alternative_win[i] = 1;
3564 else if (did_match && ! force_reload)
3565 this_alternative_match_win[i] = 1;
3566 else
3567 {
3568 int const_to_mem = 0;
3569
3570 this_alternative_offmemok[i] = offmemok;
3571 losers++;
3572 if (badop)
3573 bad = 1;
3574 /* Alternative loses if it has no regs for a reg operand. */
3575 if (REG_P (operand)
3576 && this_alternative[i] == NO_REGS
3577 && this_alternative_matches[i] < 0)
3578 bad = 1;
3579
3580 /* If this is a constant that is reloaded into the desired
3581 class by copying it to memory first, count that as another
3582 reload. This is consistent with other code and is
3583 required to avoid choosing another alternative when
3584 the constant is moved into memory by this function on
3585 an early reload pass. Note that the test here is
3586 precisely the same as in the code below that calls
3587 force_const_mem. */
3588 if (CONST_POOL_OK_P (operand_mode[i], operand)
3589 && ((targetm.preferred_reload_class (operand,
3590 this_alternative[i])
3591 == NO_REGS)
3592 || no_input_reloads))
3593 {
3594 const_to_mem = 1;
3595 if (this_alternative[i] != NO_REGS)
3596 losers++;
3597 }
3598
3599 /* Alternative loses if it requires a type of reload not
3600 permitted for this insn. We can always reload SCRATCH
3601 and objects with a REG_UNUSED note. */
3602 if (GET_CODE (operand) != SCRATCH
3603 && modified[i] != RELOAD_READ && no_output_reloads
3604 && ! find_reg_note (insn, REG_UNUSED, operand))
3605 bad = 1;
3606 else if (modified[i] != RELOAD_WRITE && no_input_reloads
3607 && ! const_to_mem)
3608 bad = 1;
3609
3610 /* If we can't reload this value at all, reject this
3611 alternative. Note that we could also lose due to
3612 LIMIT_RELOAD_CLASS, but we don't check that
3613 here. */
3614
3615 if (! CONSTANT_P (operand) && this_alternative[i] != NO_REGS)
3616 {
3617 if (targetm.preferred_reload_class (operand,
3618 this_alternative[i])
3619 == NO_REGS)
3620 reject = 600;
3621
3622 if (operand_type[i] == RELOAD_FOR_OUTPUT
3623 && (targetm.preferred_output_reload_class (operand,
3624 this_alternative[i])
3625 == NO_REGS))
3626 reject = 600;
3627 }
3628
3629 /* We prefer to reload pseudos over reloading other things,
3630 since such reloads may be able to be eliminated later.
3631 If we are reloading a SCRATCH, we won't be generating any
3632 insns, just using a register, so it is also preferred.
3633 So bump REJECT in other cases. Don't do this in the
3634 case where we are forcing a constant into memory and
3635 it will then win since we don't want to have a different
3636 alternative match then. */
3637 if (! (REG_P (operand)
3638 && REGNO (operand) >= FIRST_PSEUDO_REGISTER)
3639 && GET_CODE (operand) != SCRATCH
3640 && ! (const_to_mem && constmemok))
3641 reject += 2;
3642
3643 /* Input reloads can be inherited more often than output
3644 reloads can be removed, so penalize output reloads. */
3645 if (operand_type[i] != RELOAD_FOR_INPUT
3646 && GET_CODE (operand) != SCRATCH)
3647 reject++;
3648 }
3649
3650 /* If this operand is a pseudo register that didn't get
3651 a hard reg and this alternative accepts some
3652 register, see if the class that we want is a subset
3653 of the preferred class for this register. If not,
3654 but it intersects that class, we'd like to use the
3655 intersection, but the best we can do is to use the
3656 preferred class, if it is instead a subset of the
3657 class we want in this alternative. If we can't use
3658 it, show that usage of this alternative should be
3659 discouraged; it will be discouraged more still if the
3660 register is `preferred or nothing'. We do this
3661 because it increases the chance of reusing our spill
3662 register in a later insn and avoiding a pair of
3663 memory stores and loads.
3664
3665 Don't bother with this if this alternative will
3666 accept this operand.
3667
3668 Don't do this for a multiword operand, since it is
3669 only a small win and has the risk of requiring more
3670 spill registers, which could cause a large loss.
3671
3672 Don't do this if the preferred class has only one
3673 register because we might otherwise exhaust the
3674 class. */
3675
3676 if (! win && ! did_match
3677 && this_alternative[i] != NO_REGS
3678 && known_le (GET_MODE_SIZE (operand_mode[i]), UNITS_PER_WORD)
3679 && reg_class_size [(int) preferred_class[i]] > 0
3680 && ! small_register_class_p (preferred_class[i]))
3681 {
3682 if (! reg_class_subset_p (this_alternative[i],
3683 preferred_class[i]))
3684 {
3685 /* Since we don't have a way of forming a register
3686 class for the intersection, we just do
3687 something special if the preferred class is a
3688 subset of the class we have; that's the most
3689 common case anyway. */
3690 if (reg_class_subset_p (preferred_class[i],
3691 this_alternative[i]))
3692 this_alternative[i] = preferred_class[i];
3693 else
3694 reject += (2 + 2 * pref_or_nothing[i]);
3695 }
3696 }
3697 }
3698
3699 /* Now see if any output operands that are marked "earlyclobber"
3700 in this alternative conflict with any input operands
3701 or any memory addresses. */
3702
3703 for (i = 0; i < noperands; i++)
3704 if (this_alternative_earlyclobber[i]
3705 && (this_alternative_win[i] || this_alternative_match_win[i]))
3706 {
3707 struct decomposition early_data;
3708
3709 early_data = decompose (recog_data.operand[i]);
3710
3711 gcc_assert (modified[i] != RELOAD_READ);
3712
3713 if (this_alternative[i] == NO_REGS)
3714 {
3715 this_alternative_earlyclobber[i] = 0;
3716 gcc_assert (this_insn_is_asm);
3717 error_for_asm (this_insn,
3718 "%<&%> constraint used with no register class");
3719 }
3720
3721 for (j = 0; j < noperands; j++)
3722 /* Is this an input operand or a memory ref? */
3723 if ((MEM_P (recog_data.operand[j])
3724 || modified[j] != RELOAD_WRITE)
3725 && j != i
3726 /* Ignore things like match_operator operands. */
3727 && !recog_data.is_operator[j]
3728 /* Don't count an input operand that is constrained to match
3729 the early clobber operand. */
3730 && ! (this_alternative_matches[j] == i
3731 && rtx_equal_p (recog_data.operand[i],
3732 recog_data.operand[j]))
3733 /* Is it altered by storing the earlyclobber operand? */
3734 && !immune_p (recog_data.operand[j], recog_data.operand[i],
3735 early_data))
3736 {
3737 /* If the output is in a non-empty few-regs class,
3738 it's costly to reload it, so reload the input instead. */
3739 if (small_register_class_p (this_alternative[i])
3740 && (REG_P (recog_data.operand[j])
3741 || GET_CODE (recog_data.operand[j]) == SUBREG))
3742 {
3743 losers++;
3744 this_alternative_win[j] = 0;
3745 this_alternative_match_win[j] = 0;
3746 }
3747 else
3748 break;
3749 }
3750 /* If an earlyclobber operand conflicts with something,
3751 it must be reloaded, so request this and count the cost. */
3752 if (j != noperands)
3753 {
3754 losers++;
3755 this_alternative_win[i] = 0;
3756 this_alternative_match_win[j] = 0;
3757 for (j = 0; j < noperands; j++)
3758 if (this_alternative_matches[j] == i
3759 && this_alternative_match_win[j])
3760 {
3761 this_alternative_win[j] = 0;
3762 this_alternative_match_win[j] = 0;
3763 losers++;
3764 }
3765 }
3766 }
3767
3768 /* If one alternative accepts all the operands, no reload required,
3769 choose that alternative; don't consider the remaining ones. */
3770 if (losers == 0)
3771 {
3772 /* Unswap these so that they are never swapped at `finish'. */
3773 if (swapped)
3774 {
3775 recog_data.operand[commutative] = substed_operand[commutative];
3776 recog_data.operand[commutative + 1]
3777 = substed_operand[commutative + 1];
3778 }
3779 for (i = 0; i < noperands; i++)
3780 {
3781 goal_alternative_win[i] = this_alternative_win[i];
3782 goal_alternative_match_win[i] = this_alternative_match_win[i];
3783 goal_alternative[i] = this_alternative[i];
3784 goal_alternative_offmemok[i] = this_alternative_offmemok[i];
3785 goal_alternative_matches[i] = this_alternative_matches[i];
3786 goal_alternative_earlyclobber[i]
3787 = this_alternative_earlyclobber[i];
3788 }
3789 goal_alternative_number = this_alternative_number;
3790 goal_alternative_swapped = swapped;
3791 goal_earlyclobber = this_earlyclobber;
3792 goto finish;
3793 }
3794
3795 /* REJECT, set by the ! and ? constraint characters and when a register
3796 would be reloaded into a non-preferred class, discourages the use of
3797 this alternative for a reload goal. REJECT is incremented by six
3798 for each ? and two for each non-preferred class. */
3799 losers = losers * 6 + reject;
3800
3801 /* If this alternative can be made to work by reloading,
3802 and it needs less reloading than the others checked so far,
3803 record it as the chosen goal for reloading. */
3804 if (! bad)
3805 {
3806 if (best > losers)
3807 {
3808 for (i = 0; i < noperands; i++)
3809 {
3810 goal_alternative[i] = this_alternative[i];
3811 goal_alternative_win[i] = this_alternative_win[i];
3812 goal_alternative_match_win[i]
3813 = this_alternative_match_win[i];
3814 goal_alternative_offmemok[i]
3815 = this_alternative_offmemok[i];
3816 goal_alternative_matches[i] = this_alternative_matches[i];
3817 goal_alternative_earlyclobber[i]
3818 = this_alternative_earlyclobber[i];
3819 }
3820 goal_alternative_swapped = swapped;
3821 best = losers;
3822 goal_alternative_number = this_alternative_number;
3823 goal_earlyclobber = this_earlyclobber;
3824 }
3825 }
3826
3827 if (swapped)
3828 {
3829 /* If the commutative operands have been swapped, swap
3830 them back in order to check the next alternative. */
3831 recog_data.operand[commutative] = substed_operand[commutative];
3832 recog_data.operand[commutative + 1] = substed_operand[commutative + 1];
3833 /* Unswap the duplicates too. */
3834 for (i = 0; i < recog_data.n_dups; i++)
3835 if (recog_data.dup_num[i] == commutative
3836 || recog_data.dup_num[i] == commutative + 1)
3837 *recog_data.dup_loc[i]
3838 = recog_data.operand[(int) recog_data.dup_num[i]];
3839
3840 /* Unswap the operand related information as well. */
3841 std::swap (preferred_class[commutative],
3842 preferred_class[commutative + 1]);
3843 std::swap (pref_or_nothing[commutative],
3844 pref_or_nothing[commutative + 1]);
3845 std::swap (address_reloaded[commutative],
3846 address_reloaded[commutative + 1]);
3847 }
3848 }
3849 }
3850
3851 /* The operands don't meet the constraints.
3852 goal_alternative describes the alternative
3853 that we could reach by reloading the fewest operands.
3854 Reload so as to fit it. */
3855
3856 if (best == MAX_RECOG_OPERANDS * 2 + 600)
3857 {
3858 /* No alternative works with reloads?? */
3859 if (insn_code_number >= 0)
3860 fatal_insn ("unable to generate reloads for:", insn);
3861 error_for_asm (insn, "inconsistent operand constraints in an %<asm%>");
3862 /* Avoid further trouble with this insn. */
3863 PATTERN (insn) = gen_rtx_USE (VOIDmode, const0_rtx);
3864 n_reloads = 0;
3865 return 0;
3866 }
3867
3868 /* Jump to `finish' from above if all operands are valid already.
3869 In that case, goal_alternative_win is all 1. */
3870 finish:
3871
3872 /* Right now, for any pair of operands I and J that are required to match,
3873 with I < J,
3874 goal_alternative_matches[J] is I.
3875 Set up goal_alternative_matched as the inverse function:
3876 goal_alternative_matched[I] = J. */
3877
3878 for (i = 0; i < noperands; i++)
3879 goal_alternative_matched[i] = -1;
3880
3881 for (i = 0; i < noperands; i++)
3882 if (! goal_alternative_win[i]
3883 && goal_alternative_matches[i] >= 0)
3884 goal_alternative_matched[goal_alternative_matches[i]] = i;
3885
3886 for (i = 0; i < noperands; i++)
3887 goal_alternative_win[i] |= goal_alternative_match_win[i];
3888
3889 /* If the best alternative is with operands 1 and 2 swapped,
3890 consider them swapped before reporting the reloads. Update the
3891 operand numbers of any reloads already pushed. */
3892
3893 if (goal_alternative_swapped)
3894 {
3895 std::swap (substed_operand[commutative],
3896 substed_operand[commutative + 1]);
3897 std::swap (recog_data.operand[commutative],
3898 recog_data.operand[commutative + 1]);
3899 std::swap (*recog_data.operand_loc[commutative],
3900 *recog_data.operand_loc[commutative + 1]);
3901
3902 for (i = 0; i < recog_data.n_dups; i++)
3903 if (recog_data.dup_num[i] == commutative
3904 || recog_data.dup_num[i] == commutative + 1)
3905 *recog_data.dup_loc[i]
3906 = recog_data.operand[(int) recog_data.dup_num[i]];
3907
3908 for (i = 0; i < n_reloads; i++)
3909 {
3910 if (rld[i].opnum == commutative)
3911 rld[i].opnum = commutative + 1;
3912 else if (rld[i].opnum == commutative + 1)
3913 rld[i].opnum = commutative;
3914 }
3915 }
3916
3917 for (i = 0; i < noperands; i++)
3918 {
3919 operand_reloadnum[i] = -1;
3920
3921 /* If this is an earlyclobber operand, we need to widen the scope.
3922 The reload must remain valid from the start of the insn being
3923 reloaded until after the operand is stored into its destination.
3924 We approximate this with RELOAD_OTHER even though we know that we
3925 do not conflict with RELOAD_FOR_INPUT_ADDRESS reloads.
3926
3927 One special case that is worth checking is when we have an
3928 output that is earlyclobber but isn't used past the insn (typically
3929 a SCRATCH). In this case, we only need have the reload live
3930 through the insn itself, but not for any of our input or output
3931 reloads.
3932 But we must not accidentally narrow the scope of an existing
3933 RELOAD_OTHER reload - leave these alone.
3934
3935 In any case, anything needed to address this operand can remain
3936 however they were previously categorized. */
3937
3938 if (goal_alternative_earlyclobber[i] && operand_type[i] != RELOAD_OTHER)
3939 operand_type[i]
3940 = (find_reg_note (insn, REG_UNUSED, recog_data.operand[i])
3941 ? RELOAD_FOR_INSN : RELOAD_OTHER);
3942 }
3943
3944 /* Any constants that aren't allowed and can't be reloaded
3945 into registers are here changed into memory references. */
3946 for (i = 0; i < noperands; i++)
3947 if (! goal_alternative_win[i])
3948 {
3949 rtx op = recog_data.operand[i];
3950 rtx subreg = NULL_RTX;
3951 rtx plus = NULL_RTX;
3952 machine_mode mode = operand_mode[i];
3953
3954 /* Reloads of SUBREGs of CONSTANT RTXs are handled later in
3955 push_reload so we have to let them pass here. */
3956 if (GET_CODE (op) == SUBREG)
3957 {
3958 subreg = op;
3959 op = SUBREG_REG (op);
3960 mode = GET_MODE (op);
3961 }
3962
3963 if (GET_CODE (op) == PLUS)
3964 {
3965 plus = op;
3966 op = XEXP (op, 1);
3967 }
3968
3969 if (CONST_POOL_OK_P (mode, op)
3970 && ((targetm.preferred_reload_class (op, goal_alternative[i])
3971 == NO_REGS)
3972 || no_input_reloads))
3973 {
3974 int this_address_reloaded;
3975 rtx tem = force_const_mem (mode, op);
3976
3977 /* If we stripped a SUBREG or a PLUS above add it back. */
3978 if (plus != NULL_RTX)
3979 tem = gen_rtx_PLUS (mode, XEXP (plus, 0), tem);
3980
3981 if (subreg != NULL_RTX)
3982 tem = gen_rtx_SUBREG (operand_mode[i], tem, SUBREG_BYTE (subreg));
3983
3984 this_address_reloaded = 0;
3985 substed_operand[i] = recog_data.operand[i]
3986 = find_reloads_toplev (tem, i, address_type[i], ind_levels,
3987 0, insn, &this_address_reloaded);
3988
3989 /* If the alternative accepts constant pool refs directly
3990 there will be no reload needed at all. */
3991 if (plus == NULL_RTX
3992 && subreg == NULL_RTX
3993 && alternative_allows_const_pool_ref (this_address_reloaded != 1
3994 ? substed_operand[i]
3995 : NULL,
3996 recog_data.constraints[i],
3997 goal_alternative_number))
3998 goal_alternative_win[i] = 1;
3999 }
4000 }
4001
4002 /* Record the values of the earlyclobber operands for the caller. */
4003 if (goal_earlyclobber)
4004 for (i = 0; i < noperands; i++)
4005 if (goal_alternative_earlyclobber[i])
4006 reload_earlyclobbers[n_earlyclobbers++] = recog_data.operand[i];
4007
4008 /* Now record reloads for all the operands that need them. */
4009 for (i = 0; i < noperands; i++)
4010 if (! goal_alternative_win[i])
4011 {
4012 /* Operands that match previous ones have already been handled. */
4013 if (goal_alternative_matches[i] >= 0)
4014 ;
4015 /* Handle an operand with a nonoffsettable address
4016 appearing where an offsettable address will do
4017 by reloading the address into a base register.
4018
4019 ??? We can also do this when the operand is a register and
4020 reg_equiv_mem is not offsettable, but this is a bit tricky,
4021 so we don't bother with it. It may not be worth doing. */
4022 else if (goal_alternative_matched[i] == -1
4023 && goal_alternative_offmemok[i]
4024 && MEM_P (recog_data.operand[i]))
4025 {
4026 /* If the address to be reloaded is a VOIDmode constant,
4027 use the default address mode as mode of the reload register,
4028 as would have been done by find_reloads_address. */
4029 addr_space_t as = MEM_ADDR_SPACE (recog_data.operand[i]);
4030 machine_mode address_mode;
4031
4032 address_mode = get_address_mode (recog_data.operand[i]);
4033 operand_reloadnum[i]
4034 = push_reload (XEXP (recog_data.operand[i], 0), NULL_RTX,
4035 &XEXP (recog_data.operand[i], 0), (rtx*) 0,
4036 base_reg_class (VOIDmode, as, MEM, SCRATCH),
4037 address_mode,
4038 VOIDmode, 0, 0, i, RELOAD_OTHER);
4039 rld[operand_reloadnum[i]].inc
4040 = GET_MODE_SIZE (GET_MODE (recog_data.operand[i]));
4041
4042 /* If this operand is an output, we will have made any
4043 reloads for its address as RELOAD_FOR_OUTPUT_ADDRESS, but
4044 now we are treating part of the operand as an input, so
4045 we must change these to RELOAD_FOR_OTHER_ADDRESS. */
4046
4047 if (modified[i] == RELOAD_WRITE)
4048 {
4049 for (j = 0; j < n_reloads; j++)
4050 {
4051 if (rld[j].opnum == i)
4052 {
4053 if (rld[j].when_needed == RELOAD_FOR_OUTPUT_ADDRESS)
4054 rld[j].when_needed = RELOAD_FOR_OTHER_ADDRESS;
4055 else if (rld[j].when_needed
4056 == RELOAD_FOR_OUTADDR_ADDRESS)
4057 rld[j].when_needed = RELOAD_FOR_OTHER_ADDRESS;
4058 }
4059 }
4060 }
4061 }
4062 else if (goal_alternative_matched[i] == -1)
4063 {
4064 operand_reloadnum[i]
4065 = push_reload ((modified[i] != RELOAD_WRITE
4066 ? recog_data.operand[i] : 0),
4067 (modified[i] != RELOAD_READ
4068 ? recog_data.operand[i] : 0),
4069 (modified[i] != RELOAD_WRITE
4070 ? recog_data.operand_loc[i] : 0),
4071 (modified[i] != RELOAD_READ
4072 ? recog_data.operand_loc[i] : 0),
4073 (enum reg_class) goal_alternative[i],
4074 (modified[i] == RELOAD_WRITE
4075 ? VOIDmode : operand_mode[i]),
4076 (modified[i] == RELOAD_READ
4077 ? VOIDmode : operand_mode[i]),
4078 (insn_code_number < 0 ? 0
4079 : insn_data[insn_code_number].operand[i].strict_low),
4080 0, i, operand_type[i]);
4081 }
4082 /* In a matching pair of operands, one must be input only
4083 and the other must be output only.
4084 Pass the input operand as IN and the other as OUT. */
4085 else if (modified[i] == RELOAD_READ
4086 && modified[goal_alternative_matched[i]] == RELOAD_WRITE)
4087 {
4088 operand_reloadnum[i]
4089 = push_reload (recog_data.operand[i],
4090 recog_data.operand[goal_alternative_matched[i]],
4091 recog_data.operand_loc[i],
4092 recog_data.operand_loc[goal_alternative_matched[i]],
4093 (enum reg_class) goal_alternative[i],
4094 operand_mode[i],
4095 operand_mode[goal_alternative_matched[i]],
4096 0, 0, i, RELOAD_OTHER);
4097 operand_reloadnum[goal_alternative_matched[i]] = output_reloadnum;
4098 }
4099 else if (modified[i] == RELOAD_WRITE
4100 && modified[goal_alternative_matched[i]] == RELOAD_READ)
4101 {
4102 operand_reloadnum[goal_alternative_matched[i]]
4103 = push_reload (recog_data.operand[goal_alternative_matched[i]],
4104 recog_data.operand[i],
4105 recog_data.operand_loc[goal_alternative_matched[i]],
4106 recog_data.operand_loc[i],
4107 (enum reg_class) goal_alternative[i],
4108 operand_mode[goal_alternative_matched[i]],
4109 operand_mode[i],
4110 0, 0, i, RELOAD_OTHER);
4111 operand_reloadnum[i] = output_reloadnum;
4112 }
4113 else
4114 {
4115 gcc_assert (insn_code_number < 0);
4116 error_for_asm (insn, "inconsistent operand constraints "
4117 "in an %<asm%>");
4118 /* Avoid further trouble with this insn. */
4119 PATTERN (insn) = gen_rtx_USE (VOIDmode, const0_rtx);
4120 n_reloads = 0;
4121 return 0;
4122 }
4123 }
4124 else if (goal_alternative_matched[i] < 0
4125 && goal_alternative_matches[i] < 0
4126 && address_operand_reloaded[i] != 1
4127 && optimize)
4128 {
4129 /* For each non-matching operand that's a MEM or a pseudo-register
4130 that didn't get a hard register, make an optional reload.
4131 This may get done even if the insn needs no reloads otherwise. */
4132
4133 rtx operand = recog_data.operand[i];
4134
4135 while (GET_CODE (operand) == SUBREG)
4136 operand = SUBREG_REG (operand);
4137 if ((MEM_P (operand)
4138 || (REG_P (operand)
4139 && REGNO (operand) >= FIRST_PSEUDO_REGISTER))
4140 /* If this is only for an output, the optional reload would not
4141 actually cause us to use a register now, just note that
4142 something is stored here. */
4143 && (goal_alternative[i] != NO_REGS
4144 || modified[i] == RELOAD_WRITE)
4145 && ! no_input_reloads
4146 /* An optional output reload might allow to delete INSN later.
4147 We mustn't make in-out reloads on insns that are not permitted
4148 output reloads.
4149 If this is an asm, we can't delete it; we must not even call
4150 push_reload for an optional output reload in this case,
4151 because we can't be sure that the constraint allows a register,
4152 and push_reload verifies the constraints for asms. */
4153 && (modified[i] == RELOAD_READ
4154 || (! no_output_reloads && ! this_insn_is_asm)))
4155 operand_reloadnum[i]
4156 = push_reload ((modified[i] != RELOAD_WRITE
4157 ? recog_data.operand[i] : 0),
4158 (modified[i] != RELOAD_READ
4159 ? recog_data.operand[i] : 0),
4160 (modified[i] != RELOAD_WRITE
4161 ? recog_data.operand_loc[i] : 0),
4162 (modified[i] != RELOAD_READ
4163 ? recog_data.operand_loc[i] : 0),
4164 (enum reg_class) goal_alternative[i],
4165 (modified[i] == RELOAD_WRITE
4166 ? VOIDmode : operand_mode[i]),
4167 (modified[i] == RELOAD_READ
4168 ? VOIDmode : operand_mode[i]),
4169 (insn_code_number < 0 ? 0
4170 : insn_data[insn_code_number].operand[i].strict_low),
4171 1, i, operand_type[i]);
4172 /* If a memory reference remains (either as a MEM or a pseudo that
4173 did not get a hard register), yet we can't make an optional
4174 reload, check if this is actually a pseudo register reference;
4175 we then need to emit a USE and/or a CLOBBER so that reload
4176 inheritance will do the right thing. */
4177 else if (replace
4178 && (MEM_P (operand)
4179 || (REG_P (operand)
4180 && REGNO (operand) >= FIRST_PSEUDO_REGISTER
4181 && reg_renumber [REGNO (operand)] < 0)))
4182 {
4183 operand = *recog_data.operand_loc[i];
4184
4185 while (GET_CODE (operand) == SUBREG)
4186 operand = SUBREG_REG (operand);
4187 if (REG_P (operand))
4188 {
4189 if (modified[i] != RELOAD_WRITE)
4190 /* We mark the USE with QImode so that we recognize
4191 it as one that can be safely deleted at the end
4192 of reload. */
4193 PUT_MODE (emit_insn_before (gen_rtx_USE (VOIDmode, operand),
4194 insn), QImode);
4195 if (modified[i] != RELOAD_READ)
4196 emit_insn_after (gen_clobber (operand), insn);
4197 }
4198 }
4199 }
4200 else if (goal_alternative_matches[i] >= 0
4201 && goal_alternative_win[goal_alternative_matches[i]]
4202 && modified[i] == RELOAD_READ
4203 && modified[goal_alternative_matches[i]] == RELOAD_WRITE
4204 && ! no_input_reloads && ! no_output_reloads
4205 && optimize)
4206 {
4207 /* Similarly, make an optional reload for a pair of matching
4208 objects that are in MEM or a pseudo that didn't get a hard reg. */
4209
4210 rtx operand = recog_data.operand[i];
4211
4212 while (GET_CODE (operand) == SUBREG)
4213 operand = SUBREG_REG (operand);
4214 if ((MEM_P (operand)
4215 || (REG_P (operand)
4216 && REGNO (operand) >= FIRST_PSEUDO_REGISTER))
4217 && (goal_alternative[goal_alternative_matches[i]] != NO_REGS))
4218 operand_reloadnum[i] = operand_reloadnum[goal_alternative_matches[i]]
4219 = push_reload (recog_data.operand[goal_alternative_matches[i]],
4220 recog_data.operand[i],
4221 recog_data.operand_loc[goal_alternative_matches[i]],
4222 recog_data.operand_loc[i],
4223 (enum reg_class) goal_alternative[goal_alternative_matches[i]],
4224 operand_mode[goal_alternative_matches[i]],
4225 operand_mode[i],
4226 0, 1, goal_alternative_matches[i], RELOAD_OTHER);
4227 }
4228
4229 /* Perform whatever substitutions on the operands we are supposed
4230 to make due to commutativity or replacement of registers
4231 with equivalent constants or memory slots. */
4232
4233 for (i = 0; i < noperands; i++)
4234 {
4235 /* We only do this on the last pass through reload, because it is
4236 possible for some data (like reg_equiv_address) to be changed during
4237 later passes. Moreover, we lose the opportunity to get a useful
4238 reload_{in,out}_reg when we do these replacements. */
4239
4240 if (replace)
4241 {
4242 rtx substitution = substed_operand[i];
4243
4244 *recog_data.operand_loc[i] = substitution;
4245
4246 /* If we're replacing an operand with a LABEL_REF, we need to
4247 make sure that there's a REG_LABEL_OPERAND note attached to
4248 this instruction. */
4249 if (GET_CODE (substitution) == LABEL_REF
4250 && !find_reg_note (insn, REG_LABEL_OPERAND,
4251 label_ref_label (substitution))
4252 /* For a JUMP_P, if it was a branch target it must have
4253 already been recorded as such. */
4254 && (!JUMP_P (insn)
4255 || !label_is_jump_target_p (label_ref_label (substitution),
4256 insn)))
4257 {
4258 add_reg_note (insn, REG_LABEL_OPERAND,
4259 label_ref_label (substitution));
4260 if (LABEL_P (label_ref_label (substitution)))
4261 ++LABEL_NUSES (label_ref_label (substitution));
4262 }
4263
4264 }
4265 else
4266 retval |= (substed_operand[i] != *recog_data.operand_loc[i]);
4267 }
4268
4269 /* If this insn pattern contains any MATCH_DUP's, make sure that
4270 they will be substituted if the operands they match are substituted.
4271 Also do now any substitutions we already did on the operands.
4272
4273 Don't do this if we aren't making replacements because we might be
4274 propagating things allocated by frame pointer elimination into places
4275 it doesn't expect. */
4276
4277 if (insn_code_number >= 0 && replace)
4278 for (i = insn_data[insn_code_number].n_dups - 1; i >= 0; i--)
4279 {
4280 int opno = recog_data.dup_num[i];
4281 *recog_data.dup_loc[i] = *recog_data.operand_loc[opno];
4282 dup_replacements (recog_data.dup_loc[i], recog_data.operand_loc[opno]);
4283 }
4284
4285 #if 0
4286 /* This loses because reloading of prior insns can invalidate the equivalence
4287 (or at least find_equiv_reg isn't smart enough to find it any more),
4288 causing this insn to need more reload regs than it needed before.
4289 It may be too late to make the reload regs available.
4290 Now this optimization is done safely in choose_reload_regs. */
4291
4292 /* For each reload of a reg into some other class of reg,
4293 search for an existing equivalent reg (same value now) in the right class.
4294 We can use it as long as we don't need to change its contents. */
4295 for (i = 0; i < n_reloads; i++)
4296 if (rld[i].reg_rtx == 0
4297 && rld[i].in != 0
4298 && REG_P (rld[i].in)
4299 && rld[i].out == 0)
4300 {
4301 rld[i].reg_rtx
4302 = find_equiv_reg (rld[i].in, insn, rld[i].rclass, -1,
4303 static_reload_reg_p, 0, rld[i].inmode);
4304 /* Prevent generation of insn to load the value
4305 because the one we found already has the value. */
4306 if (rld[i].reg_rtx)
4307 rld[i].in = rld[i].reg_rtx;
4308 }
4309 #endif
4310
4311 /* If we detected error and replaced asm instruction by USE, forget about the
4312 reloads. */
4313 if (GET_CODE (PATTERN (insn)) == USE
4314 && CONST_INT_P (XEXP (PATTERN (insn), 0)))
4315 n_reloads = 0;
4316
4317 /* Perhaps an output reload can be combined with another
4318 to reduce needs by one. */
4319 if (!goal_earlyclobber)
4320 combine_reloads ();
4321
4322 /* If we have a pair of reloads for parts of an address, they are reloading
4323 the same object, the operands themselves were not reloaded, and they
4324 are for two operands that are supposed to match, merge the reloads and
4325 change the type of the surviving reload to RELOAD_FOR_OPERAND_ADDRESS. */
4326
4327 for (i = 0; i < n_reloads; i++)
4328 {
4329 int k;
4330
4331 for (j = i + 1; j < n_reloads; j++)
4332 if ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS
4333 || rld[i].when_needed == RELOAD_FOR_OUTPUT_ADDRESS
4334 || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS
4335 || rld[i].when_needed == RELOAD_FOR_OUTADDR_ADDRESS)
4336 && (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
4337 || rld[j].when_needed == RELOAD_FOR_OUTPUT_ADDRESS
4338 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS
4339 || rld[j].when_needed == RELOAD_FOR_OUTADDR_ADDRESS)
4340 && rtx_equal_p (rld[i].in, rld[j].in)
4341 && (operand_reloadnum[rld[i].opnum] < 0
4342 || rld[operand_reloadnum[rld[i].opnum]].optional)
4343 && (operand_reloadnum[rld[j].opnum] < 0
4344 || rld[operand_reloadnum[rld[j].opnum]].optional)
4345 && (goal_alternative_matches[rld[i].opnum] == rld[j].opnum
4346 || (goal_alternative_matches[rld[j].opnum]
4347 == rld[i].opnum)))
4348 {
4349 for (k = 0; k < n_replacements; k++)
4350 if (replacements[k].what == j)
4351 replacements[k].what = i;
4352
4353 if (rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS
4354 || rld[i].when_needed == RELOAD_FOR_OUTADDR_ADDRESS)
4355 rld[i].when_needed = RELOAD_FOR_OPADDR_ADDR;
4356 else
4357 rld[i].when_needed = RELOAD_FOR_OPERAND_ADDRESS;
4358 rld[j].in = 0;
4359 }
4360 }
4361
4362 /* Scan all the reloads and update their type.
4363 If a reload is for the address of an operand and we didn't reload
4364 that operand, change the type. Similarly, change the operand number
4365 of a reload when two operands match. If a reload is optional, treat it
4366 as though the operand isn't reloaded.
4367
4368 ??? This latter case is somewhat odd because if we do the optional
4369 reload, it means the object is hanging around. Thus we need only
4370 do the address reload if the optional reload was NOT done.
4371
4372 Change secondary reloads to be the address type of their operand, not
4373 the normal type.
4374
4375 If an operand's reload is now RELOAD_OTHER, change any
4376 RELOAD_FOR_INPUT_ADDRESS reloads of that operand to
4377 RELOAD_FOR_OTHER_ADDRESS. */
4378
4379 for (i = 0; i < n_reloads; i++)
4380 {
4381 if (rld[i].secondary_p
4382 && rld[i].when_needed == operand_type[rld[i].opnum])
4383 rld[i].when_needed = address_type[rld[i].opnum];
4384
4385 if ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS
4386 || rld[i].when_needed == RELOAD_FOR_OUTPUT_ADDRESS
4387 || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS
4388 || rld[i].when_needed == RELOAD_FOR_OUTADDR_ADDRESS)
4389 && (operand_reloadnum[rld[i].opnum] < 0
4390 || rld[operand_reloadnum[rld[i].opnum]].optional))
4391 {
4392 /* If we have a secondary reload to go along with this reload,
4393 change its type to RELOAD_FOR_OPADDR_ADDR. */
4394
4395 if ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS
4396 || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
4397 && rld[i].secondary_in_reload != -1)
4398 {
4399 int secondary_in_reload = rld[i].secondary_in_reload;
4400
4401 rld[secondary_in_reload].when_needed = RELOAD_FOR_OPADDR_ADDR;
4402
4403 /* If there's a tertiary reload we have to change it also. */
4404 if (secondary_in_reload > 0
4405 && rld[secondary_in_reload].secondary_in_reload != -1)
4406 rld[rld[secondary_in_reload].secondary_in_reload].when_needed
4407 = RELOAD_FOR_OPADDR_ADDR;
4408 }
4409
4410 if ((rld[i].when_needed == RELOAD_FOR_OUTPUT_ADDRESS
4411 || rld[i].when_needed == RELOAD_FOR_OUTADDR_ADDRESS)
4412 && rld[i].secondary_out_reload != -1)
4413 {
4414 int secondary_out_reload = rld[i].secondary_out_reload;
4415
4416 rld[secondary_out_reload].when_needed = RELOAD_FOR_OPADDR_ADDR;
4417
4418 /* If there's a tertiary reload we have to change it also. */
4419 if (secondary_out_reload
4420 && rld[secondary_out_reload].secondary_out_reload != -1)
4421 rld[rld[secondary_out_reload].secondary_out_reload].when_needed
4422 = RELOAD_FOR_OPADDR_ADDR;
4423 }
4424
4425 if (rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS
4426 || rld[i].when_needed == RELOAD_FOR_OUTADDR_ADDRESS)
4427 rld[i].when_needed = RELOAD_FOR_OPADDR_ADDR;
4428 else
4429 rld[i].when_needed = RELOAD_FOR_OPERAND_ADDRESS;
4430 }
4431
4432 if ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS
4433 || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
4434 && operand_reloadnum[rld[i].opnum] >= 0
4435 && (rld[operand_reloadnum[rld[i].opnum]].when_needed
4436 == RELOAD_OTHER))
4437 rld[i].when_needed = RELOAD_FOR_OTHER_ADDRESS;
4438
4439 if (goal_alternative_matches[rld[i].opnum] >= 0)
4440 rld[i].opnum = goal_alternative_matches[rld[i].opnum];
4441 }
4442
4443 /* Scan all the reloads, and check for RELOAD_FOR_OPERAND_ADDRESS reloads.
4444 If we have more than one, then convert all RELOAD_FOR_OPADDR_ADDR
4445 reloads to RELOAD_FOR_OPERAND_ADDRESS reloads.
4446
4447 choose_reload_regs assumes that RELOAD_FOR_OPADDR_ADDR reloads never
4448 conflict with RELOAD_FOR_OPERAND_ADDRESS reloads. This is true for a
4449 single pair of RELOAD_FOR_OPADDR_ADDR/RELOAD_FOR_OPERAND_ADDRESS reloads.
4450 However, if there is more than one RELOAD_FOR_OPERAND_ADDRESS reload,
4451 then a RELOAD_FOR_OPADDR_ADDR reload conflicts with all
4452 RELOAD_FOR_OPERAND_ADDRESS reloads other than the one that uses it.
4453 This is complicated by the fact that a single operand can have more
4454 than one RELOAD_FOR_OPERAND_ADDRESS reload. It is very difficult to fix
4455 choose_reload_regs without affecting code quality, and cases that
4456 actually fail are extremely rare, so it turns out to be better to fix
4457 the problem here by not generating cases that choose_reload_regs will
4458 fail for. */
4459 /* There is a similar problem with RELOAD_FOR_INPUT_ADDRESS /
4460 RELOAD_FOR_OUTPUT_ADDRESS when there is more than one of a kind for
4461 a single operand.
4462 We can reduce the register pressure by exploiting that a
4463 RELOAD_FOR_X_ADDR_ADDR that precedes all RELOAD_FOR_X_ADDRESS reloads
4464 does not conflict with any of them, if it is only used for the first of
4465 the RELOAD_FOR_X_ADDRESS reloads. */
4466 {
4467 int first_op_addr_num = -2;
4468 int first_inpaddr_num[MAX_RECOG_OPERANDS];
4469 int first_outpaddr_num[MAX_RECOG_OPERANDS];
4470 int need_change = 0;
4471 /* We use last_op_addr_reload and the contents of the above arrays
4472 first as flags - -2 means no instance encountered, -1 means exactly
4473 one instance encountered.
4474 If more than one instance has been encountered, we store the reload
4475 number of the first reload of the kind in question; reload numbers
4476 are known to be non-negative. */
4477 for (i = 0; i < noperands; i++)
4478 first_inpaddr_num[i] = first_outpaddr_num[i] = -2;
4479 for (i = n_reloads - 1; i >= 0; i--)
4480 {
4481 switch (rld[i].when_needed)
4482 {
4483 case RELOAD_FOR_OPERAND_ADDRESS:
4484 if (++first_op_addr_num >= 0)
4485 {
4486 first_op_addr_num = i;
4487 need_change = 1;
4488 }
4489 break;
4490 case RELOAD_FOR_INPUT_ADDRESS:
4491 if (++first_inpaddr_num[rld[i].opnum] >= 0)
4492 {
4493 first_inpaddr_num[rld[i].opnum] = i;
4494 need_change = 1;
4495 }
4496 break;
4497 case RELOAD_FOR_OUTPUT_ADDRESS:
4498 if (++first_outpaddr_num[rld[i].opnum] >= 0)
4499 {
4500 first_outpaddr_num[rld[i].opnum] = i;
4501 need_change = 1;
4502 }
4503 break;
4504 default:
4505 break;
4506 }
4507 }
4508
4509 if (need_change)
4510 {
4511 for (i = 0; i < n_reloads; i++)
4512 {
4513 int first_num;
4514 enum reload_type type;
4515
4516 switch (rld[i].when_needed)
4517 {
4518 case RELOAD_FOR_OPADDR_ADDR:
4519 first_num = first_op_addr_num;
4520 type = RELOAD_FOR_OPERAND_ADDRESS;
4521 break;
4522 case RELOAD_FOR_INPADDR_ADDRESS:
4523 first_num = first_inpaddr_num[rld[i].opnum];
4524 type = RELOAD_FOR_INPUT_ADDRESS;
4525 break;
4526 case RELOAD_FOR_OUTADDR_ADDRESS:
4527 first_num = first_outpaddr_num[rld[i].opnum];
4528 type = RELOAD_FOR_OUTPUT_ADDRESS;
4529 break;
4530 default:
4531 continue;
4532 }
4533 if (first_num < 0)
4534 continue;
4535 else if (i > first_num)
4536 rld[i].when_needed = type;
4537 else
4538 {
4539 /* Check if the only TYPE reload that uses reload I is
4540 reload FIRST_NUM. */
4541 for (j = n_reloads - 1; j > first_num; j--)
4542 {
4543 if (rld[j].when_needed == type
4544 && (rld[i].secondary_p
4545 ? rld[j].secondary_in_reload == i
4546 : reg_mentioned_p (rld[i].in, rld[j].in)))
4547 {
4548 rld[i].when_needed = type;
4549 break;
4550 }
4551 }
4552 }
4553 }
4554 }
4555 }
4556
4557 #ifdef NB_FIX_VAX_BACKEND
4558 /*
4559 * Scan the reloads again looking for a case where there is
4560 * precisely one RELOAD_FOR_OPERAND_ADDRESS reload and one
4561 * RELOAD_FOR_OPADDR_ADDR reload BUT they are for different
4562 * operands. choose_reload_regs assumes that the
4563 * RELOAD_FOR_OPADDR_ADDR and RELOAD_FOR_OPERAND_ADDRESS reloads are
4564 * a pair operating on the same operand and will choose the same
4565 * register for both, which is not what is wanted.
4566 */
4567 {
4568 int need_change = 0;
4569 int n_operand_address_reloads = 0,
4570 n_opaddr_addr_reloads = 0;
4571 int reloadnum_for_operand_address_reload = -1,
4572 reloadnum_for_opaddr_addr_reload = -1;
4573
4574 for (i = 0; i < n_reloads; i++)
4575 {
4576 switch (rld[i].when_needed)
4577 {
4578 case RELOAD_FOR_OPADDR_ADDR:
4579 n_opaddr_addr_reloads++;
4580 reloadnum_for_opaddr_addr_reload = i;
4581 break;
4582 case RELOAD_FOR_OPERAND_ADDRESS:
4583 n_operand_address_reloads++;
4584 reloadnum_for_operand_address_reload = i;
4585 break;
4586 default:
4587 break;
4588 }
4589 }
4590 need_change =
4591 (n_operand_address_reloads == 1
4592 && n_opaddr_addr_reloads == 1
4593 && rld[reloadnum_for_opaddr_addr_reload].opnum
4594 != rld[reloadnum_for_operand_address_reload].opnum);
4595
4596 if (need_change)
4597 {
4598 rld[reloadnum_for_opaddr_addr_reload].when_needed
4599 = RELOAD_FOR_OPERAND_ADDRESS;
4600 }
4601 }
4602 #endif
4603
4604 /* See if we have any reloads that are now allowed to be merged
4605 because we've changed when the reload is needed to
4606 RELOAD_FOR_OPERAND_ADDRESS or RELOAD_FOR_OTHER_ADDRESS. Only
4607 check for the most common cases. */
4608
4609 for (i = 0; i < n_reloads; i++)
4610 if (rld[i].in != 0 && rld[i].out == 0
4611 && (rld[i].when_needed == RELOAD_FOR_OPERAND_ADDRESS
4612 || rld[i].when_needed == RELOAD_FOR_OPADDR_ADDR
4613 || rld[i].when_needed == RELOAD_FOR_OTHER_ADDRESS))
4614 for (j = 0; j < n_reloads; j++)
4615 if (i != j && rld[j].in != 0 && rld[j].out == 0
4616 && rld[j].when_needed == rld[i].when_needed
4617 && MATCHES (rld[i].in, rld[j].in)
4618 && rld[i].rclass == rld[j].rclass
4619 && !rld[i].nocombine && !rld[j].nocombine
4620 && rld[i].reg_rtx == rld[j].reg_rtx)
4621 {
4622 rld[i].opnum = MIN (rld[i].opnum, rld[j].opnum);
4623 transfer_replacements (i, j);
4624 rld[j].in = 0;
4625 }
4626
4627 /* Compute reload_mode and reload_nregs. */
4628 for (i = 0; i < n_reloads; i++)
4629 {
4630 rld[i].mode = rld[i].inmode;
4631 if (rld[i].mode == VOIDmode
4632 || partial_subreg_p (rld[i].mode, rld[i].outmode))
4633 rld[i].mode = rld[i].outmode;
4634
4635 rld[i].nregs = ira_reg_class_max_nregs [rld[i].rclass][rld[i].mode];
4636 }
4637
4638 /* Special case a simple move with an input reload and a
4639 destination of a hard reg, if the hard reg is ok, use it. */
4640 for (i = 0; i < n_reloads; i++)
4641 if (rld[i].when_needed == RELOAD_FOR_INPUT
4642 && GET_CODE (PATTERN (insn)) == SET
4643 && REG_P (SET_DEST (PATTERN (insn)))
4644 && (SET_SRC (PATTERN (insn)) == rld[i].in
4645 || SET_SRC (PATTERN (insn)) == rld[i].in_reg)
4646 && !elimination_target_reg_p (SET_DEST (PATTERN (insn))))
4647 {
4648 rtx dest = SET_DEST (PATTERN (insn));
4649 unsigned int regno = REGNO (dest);
4650
4651 if (regno < FIRST_PSEUDO_REGISTER
4652 && TEST_HARD_REG_BIT (reg_class_contents[rld[i].rclass], regno)
4653 && targetm.hard_regno_mode_ok (regno, rld[i].mode))
4654 {
4655 int nr = hard_regno_nregs (regno, rld[i].mode);
4656 int ok = 1, nri;
4657
4658 for (nri = 1; nri < nr; nri ++)
4659 if (! TEST_HARD_REG_BIT (reg_class_contents[rld[i].rclass], regno + nri))
4660 {
4661 ok = 0;
4662 break;
4663 }
4664
4665 if (ok)
4666 rld[i].reg_rtx = dest;
4667 }
4668 }
4669
4670 return retval;
4671 }
4672
4673 /* Return true if alternative number ALTNUM in constraint-string
4674 CONSTRAINT is guaranteed to accept a reloaded constant-pool reference.
4675 MEM gives the reference if its address hasn't been fully reloaded,
4676 otherwise it is NULL. */
4677
4678 static bool
alternative_allows_const_pool_ref(rtx mem ATTRIBUTE_UNUSED,const char * constraint,int altnum)4679 alternative_allows_const_pool_ref (rtx mem ATTRIBUTE_UNUSED,
4680 const char *constraint, int altnum)
4681 {
4682 int c;
4683
4684 /* Skip alternatives before the one requested. */
4685 while (altnum > 0)
4686 {
4687 while (*constraint++ != ',')
4688 ;
4689 altnum--;
4690 }
4691 /* Scan the requested alternative for TARGET_MEM_CONSTRAINT or 'o'.
4692 If one of them is present, this alternative accepts the result of
4693 passing a constant-pool reference through find_reloads_toplev.
4694
4695 The same is true of extra memory constraints if the address
4696 was reloaded into a register. However, the target may elect
4697 to disallow the original constant address, forcing it to be
4698 reloaded into a register instead. */
4699 for (; (c = *constraint) && c != ',' && c != '#';
4700 constraint += CONSTRAINT_LEN (c, constraint))
4701 {
4702 enum constraint_num cn = lookup_constraint (constraint);
4703 if (insn_extra_memory_constraint (cn)
4704 && (mem == NULL || constraint_satisfied_p (mem, cn)))
4705 return true;
4706 }
4707 return false;
4708 }
4709
4710 /* Scan X for memory references and scan the addresses for reloading.
4711 Also checks for references to "constant" regs that we want to eliminate
4712 and replaces them with the values they stand for.
4713 We may alter X destructively if it contains a reference to such.
4714 If X is just a constant reg, we return the equivalent value
4715 instead of X.
4716
4717 IND_LEVELS says how many levels of indirect addressing this machine
4718 supports.
4719
4720 OPNUM and TYPE identify the purpose of the reload.
4721
4722 IS_SET_DEST is true if X is the destination of a SET, which is not
4723 appropriate to be replaced by a constant.
4724
4725 INSN, if nonzero, is the insn in which we do the reload. It is used
4726 to determine if we may generate output reloads, and where to put USEs
4727 for pseudos that we have to replace with stack slots.
4728
4729 ADDRESS_RELOADED. If nonzero, is a pointer to where we put the
4730 result of find_reloads_address. */
4731
4732 static rtx
find_reloads_toplev(rtx x,int opnum,enum reload_type type,int ind_levels,int is_set_dest,rtx_insn * insn,int * address_reloaded)4733 find_reloads_toplev (rtx x, int opnum, enum reload_type type,
4734 int ind_levels, int is_set_dest, rtx_insn *insn,
4735 int *address_reloaded)
4736 {
4737 RTX_CODE code = GET_CODE (x);
4738
4739 const char *fmt = GET_RTX_FORMAT (code);
4740 int i;
4741 int copied;
4742
4743 if (code == REG)
4744 {
4745 /* This code is duplicated for speed in find_reloads. */
4746 int regno = REGNO (x);
4747 if (reg_equiv_constant (regno) != 0 && !is_set_dest)
4748 x = reg_equiv_constant (regno);
4749 #if 0
4750 /* This creates (subreg (mem...)) which would cause an unnecessary
4751 reload of the mem. */
4752 else if (reg_equiv_mem (regno) != 0)
4753 x = reg_equiv_mem (regno);
4754 #endif
4755 else if (reg_equiv_memory_loc (regno)
4756 && (reg_equiv_address (regno) != 0 || num_not_at_initial_offset))
4757 {
4758 rtx mem = make_memloc (x, regno);
4759 if (reg_equiv_address (regno)
4760 || ! rtx_equal_p (mem, reg_equiv_mem (regno)))
4761 {
4762 /* If this is not a toplevel operand, find_reloads doesn't see
4763 this substitution. We have to emit a USE of the pseudo so
4764 that delete_output_reload can see it. */
4765 if (replace_reloads && recog_data.operand[opnum] != x)
4766 /* We mark the USE with QImode so that we recognize it
4767 as one that can be safely deleted at the end of
4768 reload. */
4769 PUT_MODE (emit_insn_before (gen_rtx_USE (VOIDmode, x), insn),
4770 QImode);
4771 x = mem;
4772 i = find_reloads_address (GET_MODE (x), &x, XEXP (x, 0), &XEXP (x, 0),
4773 opnum, type, ind_levels, insn);
4774 if (!rtx_equal_p (x, mem))
4775 push_reg_equiv_alt_mem (regno, x);
4776 if (address_reloaded)
4777 *address_reloaded = i;
4778 }
4779 }
4780 return x;
4781 }
4782 if (code == MEM)
4783 {
4784 rtx tem = x;
4785
4786 i = find_reloads_address (GET_MODE (x), &tem, XEXP (x, 0), &XEXP (x, 0),
4787 opnum, type, ind_levels, insn);
4788 if (address_reloaded)
4789 *address_reloaded = i;
4790
4791 return tem;
4792 }
4793
4794 if (code == SUBREG && REG_P (SUBREG_REG (x)))
4795 {
4796 /* Check for SUBREG containing a REG that's equivalent to a
4797 constant. If the constant has a known value, truncate it
4798 right now. Similarly if we are extracting a single-word of a
4799 multi-word constant. If the constant is symbolic, allow it
4800 to be substituted normally. push_reload will strip the
4801 subreg later. The constant must not be VOIDmode, because we
4802 will lose the mode of the register (this should never happen
4803 because one of the cases above should handle it). */
4804
4805 int regno = REGNO (SUBREG_REG (x));
4806 rtx tem;
4807
4808 if (regno >= FIRST_PSEUDO_REGISTER
4809 && reg_renumber[regno] < 0
4810 && reg_equiv_constant (regno) != 0)
4811 {
4812 tem =
4813 simplify_gen_subreg (GET_MODE (x), reg_equiv_constant (regno),
4814 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
4815 gcc_assert (tem);
4816 if (CONSTANT_P (tem)
4817 && !targetm.legitimate_constant_p (GET_MODE (x), tem))
4818 {
4819 tem = force_const_mem (GET_MODE (x), tem);
4820 i = find_reloads_address (GET_MODE (tem), &tem, XEXP (tem, 0),
4821 &XEXP (tem, 0), opnum, type,
4822 ind_levels, insn);
4823 if (address_reloaded)
4824 *address_reloaded = i;
4825 }
4826 return tem;
4827 }
4828
4829 /* If the subreg contains a reg that will be converted to a mem,
4830 attempt to convert the whole subreg to a (narrower or wider)
4831 memory reference instead. If this succeeds, we're done --
4832 otherwise fall through to check whether the inner reg still
4833 needs address reloads anyway. */
4834
4835 if (regno >= FIRST_PSEUDO_REGISTER
4836 && reg_equiv_memory_loc (regno) != 0)
4837 {
4838 tem = find_reloads_subreg_address (x, opnum, type, ind_levels,
4839 insn, address_reloaded);
4840 if (tem)
4841 return tem;
4842 }
4843 }
4844
4845 for (copied = 0, i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4846 {
4847 if (fmt[i] == 'e')
4848 {
4849 rtx new_part = find_reloads_toplev (XEXP (x, i), opnum, type,
4850 ind_levels, is_set_dest, insn,
4851 address_reloaded);
4852 /* If we have replaced a reg with it's equivalent memory loc -
4853 that can still be handled here e.g. if it's in a paradoxical
4854 subreg - we must make the change in a copy, rather than using
4855 a destructive change. This way, find_reloads can still elect
4856 not to do the change. */
4857 if (new_part != XEXP (x, i) && ! CONSTANT_P (new_part) && ! copied)
4858 {
4859 x = shallow_copy_rtx (x);
4860 copied = 1;
4861 }
4862 XEXP (x, i) = new_part;
4863 }
4864 }
4865 return x;
4866 }
4867
4868 /* Return a mem ref for the memory equivalent of reg REGNO.
4869 This mem ref is not shared with anything. */
4870
4871 static rtx
make_memloc(rtx ad,int regno)4872 make_memloc (rtx ad, int regno)
4873 {
4874 /* We must rerun eliminate_regs, in case the elimination
4875 offsets have changed. */
4876 rtx tem
4877 = XEXP (eliminate_regs (reg_equiv_memory_loc (regno), VOIDmode, NULL_RTX),
4878 0);
4879
4880 /* If TEM might contain a pseudo, we must copy it to avoid
4881 modifying it when we do the substitution for the reload. */
4882 if (rtx_varies_p (tem, 0))
4883 tem = copy_rtx (tem);
4884
4885 tem = replace_equiv_address_nv (reg_equiv_memory_loc (regno), tem);
4886 tem = adjust_address_nv (tem, GET_MODE (ad), 0);
4887
4888 /* Copy the result if it's still the same as the equivalence, to avoid
4889 modifying it when we do the substitution for the reload. */
4890 if (tem == reg_equiv_memory_loc (regno))
4891 tem = copy_rtx (tem);
4892 return tem;
4893 }
4894
4895 /* Returns true if AD could be turned into a valid memory reference
4896 to mode MODE in address space AS by reloading the part pointed to
4897 by PART into a register. */
4898
4899 static bool
maybe_memory_address_addr_space_p(machine_mode mode,rtx ad,addr_space_t as,rtx * part)4900 maybe_memory_address_addr_space_p (machine_mode mode, rtx ad,
4901 addr_space_t as, rtx *part)
4902 {
4903 bool retv;
4904 rtx tem = *part;
4905 rtx reg = gen_rtx_REG (GET_MODE (tem), max_reg_num ());
4906
4907 *part = reg;
4908 retv = memory_address_addr_space_p (mode, ad, as);
4909 *part = tem;
4910
4911 return retv;
4912 }
4913
4914 /* Record all reloads needed for handling memory address AD
4915 which appears in *LOC in a memory reference to mode MODE
4916 which itself is found in location *MEMREFLOC.
4917 Note that we take shortcuts assuming that no multi-reg machine mode
4918 occurs as part of an address.
4919
4920 OPNUM and TYPE specify the purpose of this reload.
4921
4922 IND_LEVELS says how many levels of indirect addressing this machine
4923 supports.
4924
4925 INSN, if nonzero, is the insn in which we do the reload. It is used
4926 to determine if we may generate output reloads, and where to put USEs
4927 for pseudos that we have to replace with stack slots.
4928
4929 Value is one if this address is reloaded or replaced as a whole; it is
4930 zero if the top level of this address was not reloaded or replaced, and
4931 it is -1 if it may or may not have been reloaded or replaced.
4932
4933 Note that there is no verification that the address will be valid after
4934 this routine does its work. Instead, we rely on the fact that the address
4935 was valid when reload started. So we need only undo things that reload
4936 could have broken. These are wrong register types, pseudos not allocated
4937 to a hard register, and frame pointer elimination. */
4938
4939 static int
find_reloads_address(machine_mode mode,rtx * memrefloc,rtx ad,rtx * loc,int opnum,enum reload_type type,int ind_levels,rtx_insn * insn)4940 find_reloads_address (machine_mode mode, rtx *memrefloc, rtx ad,
4941 rtx *loc, int opnum, enum reload_type type,
4942 int ind_levels, rtx_insn *insn)
4943 {
4944 addr_space_t as = memrefloc? MEM_ADDR_SPACE (*memrefloc)
4945 : ADDR_SPACE_GENERIC;
4946 int regno;
4947 int removed_and = 0;
4948 int op_index;
4949 rtx tem;
4950
4951 /* If the address is a register, see if it is a legitimate address and
4952 reload if not. We first handle the cases where we need not reload
4953 or where we must reload in a non-standard way. */
4954
4955 if (REG_P (ad))
4956 {
4957 regno = REGNO (ad);
4958
4959 if (reg_equiv_constant (regno) != 0)
4960 {
4961 find_reloads_address_part (reg_equiv_constant (regno), loc,
4962 base_reg_class (mode, as, MEM, SCRATCH),
4963 GET_MODE (ad), opnum, type, ind_levels);
4964 return 1;
4965 }
4966
4967 tem = reg_equiv_memory_loc (regno);
4968 if (tem != 0)
4969 {
4970 if (reg_equiv_address (regno) != 0 || num_not_at_initial_offset)
4971 {
4972 tem = make_memloc (ad, regno);
4973 if (! strict_memory_address_addr_space_p (GET_MODE (tem),
4974 XEXP (tem, 0),
4975 MEM_ADDR_SPACE (tem)))
4976 {
4977 rtx orig = tem;
4978
4979 find_reloads_address (GET_MODE (tem), &tem, XEXP (tem, 0),
4980 &XEXP (tem, 0), opnum,
4981 ADDR_TYPE (type), ind_levels, insn);
4982 if (!rtx_equal_p (tem, orig))
4983 push_reg_equiv_alt_mem (regno, tem);
4984 }
4985 /* We can avoid a reload if the register's equivalent memory
4986 expression is valid as an indirect memory address.
4987 But not all addresses are valid in a mem used as an indirect
4988 address: only reg or reg+constant. */
4989
4990 if (ind_levels > 0
4991 && strict_memory_address_addr_space_p (mode, tem, as)
4992 && (REG_P (XEXP (tem, 0))
4993 || (GET_CODE (XEXP (tem, 0)) == PLUS
4994 && REG_P (XEXP (XEXP (tem, 0), 0))
4995 && CONSTANT_P (XEXP (XEXP (tem, 0), 1)))))
4996 {
4997 /* TEM is not the same as what we'll be replacing the
4998 pseudo with after reload, put a USE in front of INSN
4999 in the final reload pass. */
5000 if (replace_reloads
5001 && num_not_at_initial_offset
5002 && ! rtx_equal_p (tem, reg_equiv_mem (regno)))
5003 {
5004 *loc = tem;
5005 /* We mark the USE with QImode so that we
5006 recognize it as one that can be safely
5007 deleted at the end of reload. */
5008 PUT_MODE (emit_insn_before (gen_rtx_USE (VOIDmode, ad),
5009 insn), QImode);
5010
5011 /* This doesn't really count as replacing the address
5012 as a whole, since it is still a memory access. */
5013 }
5014 return 0;
5015 }
5016 ad = tem;
5017 }
5018 }
5019
5020 /* The only remaining case where we can avoid a reload is if this is a
5021 hard register that is valid as a base register and which is not the
5022 subject of a CLOBBER in this insn. */
5023
5024 else if (regno < FIRST_PSEUDO_REGISTER
5025 && regno_ok_for_base_p (regno, mode, as, MEM, SCRATCH)
5026 && ! regno_clobbered_p (regno, this_insn, mode, 0))
5027 return 0;
5028
5029 /* If we do not have one of the cases above, we must do the reload. */
5030 push_reload (ad, NULL_RTX, loc, (rtx*) 0,
5031 base_reg_class (mode, as, MEM, SCRATCH),
5032 GET_MODE (ad), VOIDmode, 0, 0, opnum, type);
5033 return 1;
5034 }
5035
5036 if (strict_memory_address_addr_space_p (mode, ad, as))
5037 {
5038 /* The address appears valid, so reloads are not needed.
5039 But the address may contain an eliminable register.
5040 This can happen because a machine with indirect addressing
5041 may consider a pseudo register by itself a valid address even when
5042 it has failed to get a hard reg.
5043 So do a tree-walk to find and eliminate all such regs. */
5044
5045 /* But first quickly dispose of a common case. */
5046 if (GET_CODE (ad) == PLUS
5047 && CONST_INT_P (XEXP (ad, 1))
5048 && REG_P (XEXP (ad, 0))
5049 && reg_equiv_constant (REGNO (XEXP (ad, 0))) == 0)
5050 return 0;
5051
5052 subst_reg_equivs_changed = 0;
5053 *loc = subst_reg_equivs (ad, insn);
5054
5055 if (! subst_reg_equivs_changed)
5056 return 0;
5057
5058 /* Check result for validity after substitution. */
5059 if (strict_memory_address_addr_space_p (mode, ad, as))
5060 return 0;
5061 }
5062
5063 #ifdef LEGITIMIZE_RELOAD_ADDRESS
5064 do
5065 {
5066 if (memrefloc && ADDR_SPACE_GENERIC_P (as))
5067 {
5068 LEGITIMIZE_RELOAD_ADDRESS (ad, GET_MODE (*memrefloc), opnum, type,
5069 ind_levels, win);
5070 }
5071 break;
5072 win:
5073 *memrefloc = copy_rtx (*memrefloc);
5074 XEXP (*memrefloc, 0) = ad;
5075 move_replacements (&ad, &XEXP (*memrefloc, 0));
5076 return -1;
5077 }
5078 while (0);
5079 #endif
5080
5081 /* The address is not valid. We have to figure out why. First see if
5082 we have an outer AND and remove it if so. Then analyze what's inside. */
5083
5084 if (GET_CODE (ad) == AND)
5085 {
5086 removed_and = 1;
5087 loc = &XEXP (ad, 0);
5088 ad = *loc;
5089 }
5090
5091 /* One possibility for why the address is invalid is that it is itself
5092 a MEM. This can happen when the frame pointer is being eliminated, a
5093 pseudo is not allocated to a hard register, and the offset between the
5094 frame and stack pointers is not its initial value. In that case the
5095 pseudo will have been replaced by a MEM referring to the
5096 stack pointer. */
5097 if (MEM_P (ad))
5098 {
5099 /* First ensure that the address in this MEM is valid. Then, unless
5100 indirect addresses are valid, reload the MEM into a register. */
5101 tem = ad;
5102 find_reloads_address (GET_MODE (ad), &tem, XEXP (ad, 0), &XEXP (ad, 0),
5103 opnum, ADDR_TYPE (type),
5104 ind_levels == 0 ? 0 : ind_levels - 1, insn);
5105
5106 /* If tem was changed, then we must create a new memory reference to
5107 hold it and store it back into memrefloc. */
5108 if (tem != ad && memrefloc)
5109 {
5110 *memrefloc = copy_rtx (*memrefloc);
5111 copy_replacements (tem, XEXP (*memrefloc, 0));
5112 loc = &XEXP (*memrefloc, 0);
5113 if (removed_and)
5114 loc = &XEXP (*loc, 0);
5115 }
5116
5117 /* Check similar cases as for indirect addresses as above except
5118 that we can allow pseudos and a MEM since they should have been
5119 taken care of above. */
5120
5121 if (ind_levels == 0
5122 || (GET_CODE (XEXP (tem, 0)) == SYMBOL_REF && ! indirect_symref_ok)
5123 || MEM_P (XEXP (tem, 0))
5124 || ! (REG_P (XEXP (tem, 0))
5125 || (GET_CODE (XEXP (tem, 0)) == PLUS
5126 && REG_P (XEXP (XEXP (tem, 0), 0))
5127 && CONST_INT_P (XEXP (XEXP (tem, 0), 1)))))
5128 {
5129 /* Must use TEM here, not AD, since it is the one that will
5130 have any subexpressions reloaded, if needed. */
5131 push_reload (tem, NULL_RTX, loc, (rtx*) 0,
5132 base_reg_class (mode, as, MEM, SCRATCH), GET_MODE (tem),
5133 VOIDmode, 0,
5134 0, opnum, type);
5135 return ! removed_and;
5136 }
5137 else
5138 return 0;
5139 }
5140
5141 /* If we have address of a stack slot but it's not valid because the
5142 displacement is too large, compute the sum in a register.
5143 Handle all base registers here, not just fp/ap/sp, because on some
5144 targets (namely SH) we can also get too large displacements from
5145 big-endian corrections. */
5146 else if (GET_CODE (ad) == PLUS
5147 && REG_P (XEXP (ad, 0))
5148 && REGNO (XEXP (ad, 0)) < FIRST_PSEUDO_REGISTER
5149 && CONST_INT_P (XEXP (ad, 1))
5150 && (regno_ok_for_base_p (REGNO (XEXP (ad, 0)), mode, as, PLUS,
5151 CONST_INT)
5152 /* Similarly, if we were to reload the base register and the
5153 mem+offset address is still invalid, then we want to reload
5154 the whole address, not just the base register. */
5155 || ! maybe_memory_address_addr_space_p
5156 (mode, ad, as, &(XEXP (ad, 0)))))
5157
5158 {
5159 /* Unshare the MEM rtx so we can safely alter it. */
5160 if (memrefloc)
5161 {
5162 *memrefloc = copy_rtx (*memrefloc);
5163 loc = &XEXP (*memrefloc, 0);
5164 if (removed_and)
5165 loc = &XEXP (*loc, 0);
5166 }
5167
5168 if (double_reg_address_ok[mode]
5169 && regno_ok_for_base_p (REGNO (XEXP (ad, 0)), mode, as,
5170 PLUS, CONST_INT))
5171 {
5172 /* Unshare the sum as well. */
5173 *loc = ad = copy_rtx (ad);
5174
5175 /* Reload the displacement into an index reg.
5176 We assume the frame pointer or arg pointer is a base reg. */
5177 find_reloads_address_part (XEXP (ad, 1), &XEXP (ad, 1),
5178 INDEX_REG_CLASS, GET_MODE (ad), opnum,
5179 type, ind_levels);
5180 return 0;
5181 }
5182 else
5183 {
5184 /* If the sum of two regs is not necessarily valid,
5185 reload the sum into a base reg.
5186 That will at least work. */
5187 find_reloads_address_part (ad, loc,
5188 base_reg_class (mode, as, MEM, SCRATCH),
5189 GET_MODE (ad), opnum, type, ind_levels);
5190 }
5191 return ! removed_and;
5192 }
5193
5194 /* If we have an indexed stack slot, there are three possible reasons why
5195 it might be invalid: The index might need to be reloaded, the address
5196 might have been made by frame pointer elimination and hence have a
5197 constant out of range, or both reasons might apply.
5198
5199 We can easily check for an index needing reload, but even if that is the
5200 case, we might also have an invalid constant. To avoid making the
5201 conservative assumption and requiring two reloads, we see if this address
5202 is valid when not interpreted strictly. If it is, the only problem is
5203 that the index needs a reload and find_reloads_address_1 will take care
5204 of it.
5205
5206 Handle all base registers here, not just fp/ap/sp, because on some
5207 targets (namely SPARC) we can also get invalid addresses from preventive
5208 subreg big-endian corrections made by find_reloads_toplev. We
5209 can also get expressions involving LO_SUM (rather than PLUS) from
5210 find_reloads_subreg_address.
5211
5212 If we decide to do something, it must be that `double_reg_address_ok'
5213 is true. We generate a reload of the base register + constant and
5214 rework the sum so that the reload register will be added to the index.
5215 This is safe because we know the address isn't shared.
5216
5217 We check for the base register as both the first and second operand of
5218 the innermost PLUS and/or LO_SUM. */
5219
5220 for (op_index = 0; op_index < 2; ++op_index)
5221 {
5222 rtx operand, addend;
5223 enum rtx_code inner_code;
5224
5225 if (GET_CODE (ad) != PLUS)
5226 continue;
5227
5228 inner_code = GET_CODE (XEXP (ad, 0));
5229 if (!(GET_CODE (ad) == PLUS
5230 && CONST_INT_P (XEXP (ad, 1))
5231 && (inner_code == PLUS || inner_code == LO_SUM)))
5232 continue;
5233
5234 operand = XEXP (XEXP (ad, 0), op_index);
5235 if (!REG_P (operand) || REGNO (operand) >= FIRST_PSEUDO_REGISTER)
5236 continue;
5237
5238 addend = XEXP (XEXP (ad, 0), 1 - op_index);
5239
5240 if ((regno_ok_for_base_p (REGNO (operand), mode, as, inner_code,
5241 GET_CODE (addend))
5242 || operand == frame_pointer_rtx
5243 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
5244 && operand == hard_frame_pointer_rtx)
5245 || (FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
5246 && operand == arg_pointer_rtx)
5247 || operand == stack_pointer_rtx)
5248 && ! maybe_memory_address_addr_space_p
5249 (mode, ad, as, &XEXP (XEXP (ad, 0), 1 - op_index)))
5250 {
5251 rtx offset_reg;
5252 enum reg_class cls;
5253
5254 offset_reg = plus_constant (GET_MODE (ad), operand,
5255 INTVAL (XEXP (ad, 1)));
5256
5257 /* Form the adjusted address. */
5258 if (GET_CODE (XEXP (ad, 0)) == PLUS)
5259 ad = gen_rtx_PLUS (GET_MODE (ad),
5260 op_index == 0 ? offset_reg : addend,
5261 op_index == 0 ? addend : offset_reg);
5262 else
5263 ad = gen_rtx_LO_SUM (GET_MODE (ad),
5264 op_index == 0 ? offset_reg : addend,
5265 op_index == 0 ? addend : offset_reg);
5266 *loc = ad;
5267
5268 cls = base_reg_class (mode, as, MEM, GET_CODE (addend));
5269 find_reloads_address_part (XEXP (ad, op_index),
5270 &XEXP (ad, op_index), cls,
5271 GET_MODE (ad), opnum, type, ind_levels);
5272 find_reloads_address_1 (mode, as,
5273 XEXP (ad, 1 - op_index), 1, GET_CODE (ad),
5274 GET_CODE (XEXP (ad, op_index)),
5275 &XEXP (ad, 1 - op_index), opnum,
5276 type, 0, insn);
5277
5278 return 0;
5279 }
5280 }
5281
5282 /* See if address becomes valid when an eliminable register
5283 in a sum is replaced. */
5284
5285 tem = ad;
5286 if (GET_CODE (ad) == PLUS)
5287 tem = subst_indexed_address (ad);
5288 if (tem != ad && strict_memory_address_addr_space_p (mode, tem, as))
5289 {
5290 /* Ok, we win that way. Replace any additional eliminable
5291 registers. */
5292
5293 subst_reg_equivs_changed = 0;
5294 tem = subst_reg_equivs (tem, insn);
5295
5296 /* Make sure that didn't make the address invalid again. */
5297
5298 if (! subst_reg_equivs_changed
5299 || strict_memory_address_addr_space_p (mode, tem, as))
5300 {
5301 *loc = tem;
5302 return 0;
5303 }
5304 }
5305
5306 /* If constants aren't valid addresses, reload the constant address
5307 into a register. */
5308 if (CONSTANT_P (ad) && ! strict_memory_address_addr_space_p (mode, ad, as))
5309 {
5310 machine_mode address_mode = GET_MODE (ad);
5311 if (address_mode == VOIDmode)
5312 address_mode = targetm.addr_space.address_mode (as);
5313
5314 /* If AD is an address in the constant pool, the MEM rtx may be shared.
5315 Unshare it so we can safely alter it. */
5316 if (memrefloc && GET_CODE (ad) == SYMBOL_REF
5317 && CONSTANT_POOL_ADDRESS_P (ad))
5318 {
5319 *memrefloc = copy_rtx (*memrefloc);
5320 loc = &XEXP (*memrefloc, 0);
5321 if (removed_and)
5322 loc = &XEXP (*loc, 0);
5323 }
5324
5325 find_reloads_address_part (ad, loc,
5326 base_reg_class (mode, as, MEM, SCRATCH),
5327 address_mode, opnum, type, ind_levels);
5328 return ! removed_and;
5329 }
5330
5331 return find_reloads_address_1 (mode, as, ad, 0, MEM, SCRATCH, loc,
5332 opnum, type, ind_levels, insn);
5333 }
5334
5335 /* Find all pseudo regs appearing in AD
5336 that are eliminable in favor of equivalent values
5337 and do not have hard regs; replace them by their equivalents.
5338 INSN, if nonzero, is the insn in which we do the reload. We put USEs in
5339 front of it for pseudos that we have to replace with stack slots. */
5340
5341 static rtx
subst_reg_equivs(rtx ad,rtx_insn * insn)5342 subst_reg_equivs (rtx ad, rtx_insn *insn)
5343 {
5344 RTX_CODE code = GET_CODE (ad);
5345 int i;
5346 const char *fmt;
5347
5348 switch (code)
5349 {
5350 case HIGH:
5351 case CONST:
5352 CASE_CONST_ANY:
5353 case SYMBOL_REF:
5354 case LABEL_REF:
5355 case PC:
5356 return ad;
5357
5358 case REG:
5359 {
5360 int regno = REGNO (ad);
5361
5362 if (reg_equiv_constant (regno) != 0)
5363 {
5364 subst_reg_equivs_changed = 1;
5365 return reg_equiv_constant (regno);
5366 }
5367 if (reg_equiv_memory_loc (regno) && num_not_at_initial_offset)
5368 {
5369 rtx mem = make_memloc (ad, regno);
5370 if (! rtx_equal_p (mem, reg_equiv_mem (regno)))
5371 {
5372 subst_reg_equivs_changed = 1;
5373 /* We mark the USE with QImode so that we recognize it
5374 as one that can be safely deleted at the end of
5375 reload. */
5376 PUT_MODE (emit_insn_before (gen_rtx_USE (VOIDmode, ad), insn),
5377 QImode);
5378 return mem;
5379 }
5380 }
5381 }
5382 return ad;
5383
5384 case PLUS:
5385 /* Quickly dispose of a common case. */
5386 if (XEXP (ad, 0) == frame_pointer_rtx
5387 && CONST_INT_P (XEXP (ad, 1)))
5388 return ad;
5389 break;
5390
5391 default:
5392 break;
5393 }
5394
5395 fmt = GET_RTX_FORMAT (code);
5396 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5397 if (fmt[i] == 'e')
5398 XEXP (ad, i) = subst_reg_equivs (XEXP (ad, i), insn);
5399 return ad;
5400 }
5401
5402 /* Compute the sum of X and Y, making canonicalizations assumed in an
5403 address, namely: sum constant integers, surround the sum of two
5404 constants with a CONST, put the constant as the second operand, and
5405 group the constant on the outermost sum.
5406
5407 This routine assumes both inputs are already in canonical form. */
5408
5409 rtx
form_sum(machine_mode mode,rtx x,rtx y)5410 form_sum (machine_mode mode, rtx x, rtx y)
5411 {
5412 rtx tem;
5413
5414 gcc_assert (GET_MODE (x) == mode || GET_MODE (x) == VOIDmode);
5415 gcc_assert (GET_MODE (y) == mode || GET_MODE (y) == VOIDmode);
5416
5417 if (CONST_INT_P (x))
5418 return plus_constant (mode, y, INTVAL (x));
5419 else if (CONST_INT_P (y))
5420 return plus_constant (mode, x, INTVAL (y));
5421 else if (CONSTANT_P (x))
5422 tem = x, x = y, y = tem;
5423
5424 if (GET_CODE (x) == PLUS && CONSTANT_P (XEXP (x, 1)))
5425 return form_sum (mode, XEXP (x, 0), form_sum (mode, XEXP (x, 1), y));
5426
5427 /* Note that if the operands of Y are specified in the opposite
5428 order in the recursive calls below, infinite recursion will occur. */
5429 if (GET_CODE (y) == PLUS && CONSTANT_P (XEXP (y, 1)))
5430 return form_sum (mode, form_sum (mode, x, XEXP (y, 0)), XEXP (y, 1));
5431
5432 /* If both constant, encapsulate sum. Otherwise, just form sum. A
5433 constant will have been placed second. */
5434 if (CONSTANT_P (x) && CONSTANT_P (y))
5435 {
5436 if (GET_CODE (x) == CONST)
5437 x = XEXP (x, 0);
5438 if (GET_CODE (y) == CONST)
5439 y = XEXP (y, 0);
5440
5441 return gen_rtx_CONST (VOIDmode, gen_rtx_PLUS (mode, x, y));
5442 }
5443
5444 return gen_rtx_PLUS (mode, x, y);
5445 }
5446
5447 /* If ADDR is a sum containing a pseudo register that should be
5448 replaced with a constant (from reg_equiv_constant),
5449 return the result of doing so, and also apply the associative
5450 law so that the result is more likely to be a valid address.
5451 (But it is not guaranteed to be one.)
5452
5453 Note that at most one register is replaced, even if more are
5454 replaceable. Also, we try to put the result into a canonical form
5455 so it is more likely to be a valid address.
5456
5457 In all other cases, return ADDR. */
5458
5459 static rtx
subst_indexed_address(rtx addr)5460 subst_indexed_address (rtx addr)
5461 {
5462 rtx op0 = 0, op1 = 0, op2 = 0;
5463 rtx tem;
5464 int regno;
5465
5466 if (GET_CODE (addr) == PLUS)
5467 {
5468 /* Try to find a register to replace. */
5469 op0 = XEXP (addr, 0), op1 = XEXP (addr, 1), op2 = 0;
5470 if (REG_P (op0)
5471 && (regno = REGNO (op0)) >= FIRST_PSEUDO_REGISTER
5472 && reg_renumber[regno] < 0
5473 && reg_equiv_constant (regno) != 0)
5474 op0 = reg_equiv_constant (regno);
5475 else if (REG_P (op1)
5476 && (regno = REGNO (op1)) >= FIRST_PSEUDO_REGISTER
5477 && reg_renumber[regno] < 0
5478 && reg_equiv_constant (regno) != 0)
5479 op1 = reg_equiv_constant (regno);
5480 else if (GET_CODE (op0) == PLUS
5481 && (tem = subst_indexed_address (op0)) != op0)
5482 op0 = tem;
5483 else if (GET_CODE (op1) == PLUS
5484 && (tem = subst_indexed_address (op1)) != op1)
5485 op1 = tem;
5486 else
5487 return addr;
5488
5489 /* Pick out up to three things to add. */
5490 if (GET_CODE (op1) == PLUS)
5491 op2 = XEXP (op1, 1), op1 = XEXP (op1, 0);
5492 else if (GET_CODE (op0) == PLUS)
5493 op2 = op1, op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5494
5495 /* Compute the sum. */
5496 if (op2 != 0)
5497 op1 = form_sum (GET_MODE (addr), op1, op2);
5498 if (op1 != 0)
5499 op0 = form_sum (GET_MODE (addr), op0, op1);
5500
5501 return op0;
5502 }
5503 return addr;
5504 }
5505
5506 /* Update the REG_INC notes for an insn. It updates all REG_INC
5507 notes for the instruction which refer to REGNO the to refer
5508 to the reload number.
5509
5510 INSN is the insn for which any REG_INC notes need updating.
5511
5512 REGNO is the register number which has been reloaded.
5513
5514 RELOADNUM is the reload number. */
5515
5516 static void
update_auto_inc_notes(rtx_insn * insn ATTRIBUTE_UNUSED,int regno ATTRIBUTE_UNUSED,int reloadnum ATTRIBUTE_UNUSED)5517 update_auto_inc_notes (rtx_insn *insn ATTRIBUTE_UNUSED, int regno ATTRIBUTE_UNUSED,
5518 int reloadnum ATTRIBUTE_UNUSED)
5519 {
5520 if (!AUTO_INC_DEC)
5521 return;
5522
5523 for (rtx link = REG_NOTES (insn); link; link = XEXP (link, 1))
5524 if (REG_NOTE_KIND (link) == REG_INC
5525 && (int) REGNO (XEXP (link, 0)) == regno)
5526 push_replacement (&XEXP (link, 0), reloadnum, VOIDmode);
5527 }
5528
5529 /* Record the pseudo registers we must reload into hard registers in a
5530 subexpression of a would-be memory address, X referring to a value
5531 in mode MODE. (This function is not called if the address we find
5532 is strictly valid.)
5533
5534 CONTEXT = 1 means we are considering regs as index regs,
5535 = 0 means we are considering them as base regs.
5536 OUTER_CODE is the code of the enclosing RTX, typically a MEM, a PLUS,
5537 or an autoinc code.
5538 If CONTEXT == 0 and OUTER_CODE is a PLUS or LO_SUM, then INDEX_CODE
5539 is the code of the index part of the address. Otherwise, pass SCRATCH
5540 for this argument.
5541 OPNUM and TYPE specify the purpose of any reloads made.
5542
5543 IND_LEVELS says how many levels of indirect addressing are
5544 supported at this point in the address.
5545
5546 INSN, if nonzero, is the insn in which we do the reload. It is used
5547 to determine if we may generate output reloads.
5548
5549 We return nonzero if X, as a whole, is reloaded or replaced. */
5550
5551 /* Note that we take shortcuts assuming that no multi-reg machine mode
5552 occurs as part of an address.
5553 Also, this is not fully machine-customizable; it works for machines
5554 such as VAXen and 68000's and 32000's, but other possible machines
5555 could have addressing modes that this does not handle right.
5556 If you add push_reload calls here, you need to make sure gen_reload
5557 handles those cases gracefully. */
5558
5559 static int
find_reloads_address_1(machine_mode mode,addr_space_t as,rtx x,int context,enum rtx_code outer_code,enum rtx_code index_code,rtx * loc,int opnum,enum reload_type type,int ind_levels,rtx_insn * insn)5560 find_reloads_address_1 (machine_mode mode, addr_space_t as,
5561 rtx x, int context,
5562 enum rtx_code outer_code, enum rtx_code index_code,
5563 rtx *loc, int opnum, enum reload_type type,
5564 int ind_levels, rtx_insn *insn)
5565 {
5566 #define REG_OK_FOR_CONTEXT(CONTEXT, REGNO, MODE, AS, OUTER, INDEX) \
5567 ((CONTEXT) == 0 \
5568 ? regno_ok_for_base_p (REGNO, MODE, AS, OUTER, INDEX) \
5569 : REGNO_OK_FOR_INDEX_P (REGNO))
5570
5571 enum reg_class context_reg_class;
5572 RTX_CODE code = GET_CODE (x);
5573 bool reloaded_inner_of_autoinc = false;
5574
5575 if (context == 1)
5576 context_reg_class = INDEX_REG_CLASS;
5577 else
5578 context_reg_class = base_reg_class (mode, as, outer_code, index_code);
5579
5580 switch (code)
5581 {
5582 case PLUS:
5583 {
5584 rtx orig_op0 = XEXP (x, 0);
5585 rtx orig_op1 = XEXP (x, 1);
5586 RTX_CODE code0 = GET_CODE (orig_op0);
5587 RTX_CODE code1 = GET_CODE (orig_op1);
5588 rtx op0 = orig_op0;
5589 rtx op1 = orig_op1;
5590
5591 if (GET_CODE (op0) == SUBREG)
5592 {
5593 op0 = SUBREG_REG (op0);
5594 code0 = GET_CODE (op0);
5595 if (code0 == REG && REGNO (op0) < FIRST_PSEUDO_REGISTER)
5596 op0 = gen_rtx_REG (word_mode,
5597 (REGNO (op0) +
5598 subreg_regno_offset (REGNO (SUBREG_REG (orig_op0)),
5599 GET_MODE (SUBREG_REG (orig_op0)),
5600 SUBREG_BYTE (orig_op0),
5601 GET_MODE (orig_op0))));
5602 }
5603
5604 if (GET_CODE (op1) == SUBREG)
5605 {
5606 op1 = SUBREG_REG (op1);
5607 code1 = GET_CODE (op1);
5608 if (code1 == REG && REGNO (op1) < FIRST_PSEUDO_REGISTER)
5609 /* ??? Why is this given op1's mode and above for
5610 ??? op0 SUBREGs we use word_mode? */
5611 op1 = gen_rtx_REG (GET_MODE (op1),
5612 (REGNO (op1) +
5613 subreg_regno_offset (REGNO (SUBREG_REG (orig_op1)),
5614 GET_MODE (SUBREG_REG (orig_op1)),
5615 SUBREG_BYTE (orig_op1),
5616 GET_MODE (orig_op1))));
5617 }
5618 /* Plus in the index register may be created only as a result of
5619 register rematerialization for expression like &localvar*4. Reload it.
5620 It may be possible to combine the displacement on the outer level,
5621 but it is probably not worthwhile to do so. */
5622 if (context == 1)
5623 {
5624 find_reloads_address (GET_MODE (x), loc, XEXP (x, 0), &XEXP (x, 0),
5625 opnum, ADDR_TYPE (type), ind_levels, insn);
5626 push_reload (*loc, NULL_RTX, loc, (rtx*) 0,
5627 context_reg_class,
5628 GET_MODE (x), VOIDmode, 0, 0, opnum, type);
5629 return 1;
5630 }
5631
5632 if (code0 == MULT || code0 == ASHIFT
5633 || code0 == SIGN_EXTEND || code0 == TRUNCATE
5634 || code0 == ZERO_EXTEND || code1 == MEM)
5635 {
5636 find_reloads_address_1 (mode, as, orig_op0, 1, PLUS, SCRATCH,
5637 &XEXP (x, 0), opnum, type, ind_levels,
5638 insn);
5639 find_reloads_address_1 (mode, as, orig_op1, 0, PLUS, code0,
5640 &XEXP (x, 1), opnum, type, ind_levels,
5641 insn);
5642 }
5643
5644 else if (code1 == MULT || code1 == ASHIFT
5645 || code1 == SIGN_EXTEND || code1 == TRUNCATE
5646 || code1 == ZERO_EXTEND || code0 == MEM)
5647 {
5648 find_reloads_address_1 (mode, as, orig_op0, 0, PLUS, code1,
5649 &XEXP (x, 0), opnum, type, ind_levels,
5650 insn);
5651 find_reloads_address_1 (mode, as, orig_op1, 1, PLUS, SCRATCH,
5652 &XEXP (x, 1), opnum, type, ind_levels,
5653 insn);
5654 }
5655
5656 else if (code0 == CONST_INT || code0 == CONST
5657 || code0 == SYMBOL_REF || code0 == LABEL_REF)
5658 find_reloads_address_1 (mode, as, orig_op1, 0, PLUS, code0,
5659 &XEXP (x, 1), opnum, type, ind_levels,
5660 insn);
5661
5662 else if (code1 == CONST_INT || code1 == CONST
5663 || code1 == SYMBOL_REF || code1 == LABEL_REF)
5664 find_reloads_address_1 (mode, as, orig_op0, 0, PLUS, code1,
5665 &XEXP (x, 0), opnum, type, ind_levels,
5666 insn);
5667
5668 else if (code0 == REG && code1 == REG)
5669 {
5670 if (REGNO_OK_FOR_INDEX_P (REGNO (op1))
5671 && regno_ok_for_base_p (REGNO (op0), mode, as, PLUS, REG))
5672 return 0;
5673 else if (REGNO_OK_FOR_INDEX_P (REGNO (op0))
5674 && regno_ok_for_base_p (REGNO (op1), mode, as, PLUS, REG))
5675 return 0;
5676 else if (regno_ok_for_base_p (REGNO (op0), mode, as, PLUS, REG))
5677 find_reloads_address_1 (mode, as, orig_op1, 1, PLUS, SCRATCH,
5678 &XEXP (x, 1), opnum, type, ind_levels,
5679 insn);
5680 else if (REGNO_OK_FOR_INDEX_P (REGNO (op1)))
5681 find_reloads_address_1 (mode, as, orig_op0, 0, PLUS, REG,
5682 &XEXP (x, 0), opnum, type, ind_levels,
5683 insn);
5684 else if (regno_ok_for_base_p (REGNO (op1), mode, as, PLUS, REG))
5685 find_reloads_address_1 (mode, as, orig_op0, 1, PLUS, SCRATCH,
5686 &XEXP (x, 0), opnum, type, ind_levels,
5687 insn);
5688 else if (REGNO_OK_FOR_INDEX_P (REGNO (op0)))
5689 find_reloads_address_1 (mode, as, orig_op1, 0, PLUS, REG,
5690 &XEXP (x, 1), opnum, type, ind_levels,
5691 insn);
5692 else
5693 {
5694 find_reloads_address_1 (mode, as, orig_op0, 0, PLUS, REG,
5695 &XEXP (x, 0), opnum, type, ind_levels,
5696 insn);
5697 find_reloads_address_1 (mode, as, orig_op1, 1, PLUS, SCRATCH,
5698 &XEXP (x, 1), opnum, type, ind_levels,
5699 insn);
5700 }
5701 }
5702
5703 else if (code0 == REG)
5704 {
5705 find_reloads_address_1 (mode, as, orig_op0, 1, PLUS, SCRATCH,
5706 &XEXP (x, 0), opnum, type, ind_levels,
5707 insn);
5708 find_reloads_address_1 (mode, as, orig_op1, 0, PLUS, REG,
5709 &XEXP (x, 1), opnum, type, ind_levels,
5710 insn);
5711 }
5712
5713 else if (code1 == REG)
5714 {
5715 find_reloads_address_1 (mode, as, orig_op1, 1, PLUS, SCRATCH,
5716 &XEXP (x, 1), opnum, type, ind_levels,
5717 insn);
5718 find_reloads_address_1 (mode, as, orig_op0, 0, PLUS, REG,
5719 &XEXP (x, 0), opnum, type, ind_levels,
5720 insn);
5721 }
5722 }
5723
5724 return 0;
5725
5726 case POST_MODIFY:
5727 case PRE_MODIFY:
5728 {
5729 rtx op0 = XEXP (x, 0);
5730 rtx op1 = XEXP (x, 1);
5731 enum rtx_code index_code;
5732 int regno;
5733 int reloadnum;
5734
5735 if (GET_CODE (op1) != PLUS && GET_CODE (op1) != MINUS)
5736 return 0;
5737
5738 /* Currently, we only support {PRE,POST}_MODIFY constructs
5739 where a base register is {inc,dec}remented by the contents
5740 of another register or by a constant value. Thus, these
5741 operands must match. */
5742 gcc_assert (op0 == XEXP (op1, 0));
5743
5744 /* Require index register (or constant). Let's just handle the
5745 register case in the meantime... If the target allows
5746 auto-modify by a constant then we could try replacing a pseudo
5747 register with its equivalent constant where applicable.
5748
5749 We also handle the case where the register was eliminated
5750 resulting in a PLUS subexpression.
5751
5752 If we later decide to reload the whole PRE_MODIFY or
5753 POST_MODIFY, inc_for_reload might clobber the reload register
5754 before reading the index. The index register might therefore
5755 need to live longer than a TYPE reload normally would, so be
5756 conservative and class it as RELOAD_OTHER. */
5757 if ((REG_P (XEXP (op1, 1))
5758 && !REGNO_OK_FOR_INDEX_P (REGNO (XEXP (op1, 1))))
5759 || GET_CODE (XEXP (op1, 1)) == PLUS)
5760 find_reloads_address_1 (mode, as, XEXP (op1, 1), 1, code, SCRATCH,
5761 &XEXP (op1, 1), opnum, RELOAD_OTHER,
5762 ind_levels, insn);
5763
5764 gcc_assert (REG_P (XEXP (op1, 0)));
5765
5766 regno = REGNO (XEXP (op1, 0));
5767 index_code = GET_CODE (XEXP (op1, 1));
5768
5769 /* A register that is incremented cannot be constant! */
5770 gcc_assert (regno < FIRST_PSEUDO_REGISTER
5771 || reg_equiv_constant (regno) == 0);
5772
5773 /* Handle a register that is equivalent to a memory location
5774 which cannot be addressed directly. */
5775 if (reg_equiv_memory_loc (regno) != 0
5776 && (reg_equiv_address (regno) != 0
5777 || num_not_at_initial_offset))
5778 {
5779 rtx tem = make_memloc (XEXP (x, 0), regno);
5780
5781 if (reg_equiv_address (regno)
5782 || ! rtx_equal_p (tem, reg_equiv_mem (regno)))
5783 {
5784 rtx orig = tem;
5785
5786 /* First reload the memory location's address.
5787 We can't use ADDR_TYPE (type) here, because we need to
5788 write back the value after reading it, hence we actually
5789 need two registers. */
5790 find_reloads_address (GET_MODE (tem), &tem, XEXP (tem, 0),
5791 &XEXP (tem, 0), opnum,
5792 RELOAD_OTHER,
5793 ind_levels, insn);
5794
5795 if (!rtx_equal_p (tem, orig))
5796 push_reg_equiv_alt_mem (regno, tem);
5797
5798 /* Then reload the memory location into a base
5799 register. */
5800 reloadnum = push_reload (tem, tem, &XEXP (x, 0),
5801 &XEXP (op1, 0),
5802 base_reg_class (mode, as,
5803 code, index_code),
5804 GET_MODE (x), GET_MODE (x), 0,
5805 0, opnum, RELOAD_OTHER);
5806
5807 update_auto_inc_notes (this_insn, regno, reloadnum);
5808 return 0;
5809 }
5810 }
5811
5812 if (reg_renumber[regno] >= 0)
5813 regno = reg_renumber[regno];
5814
5815 /* We require a base register here... */
5816 if (!regno_ok_for_base_p (regno, GET_MODE (x), as, code, index_code))
5817 {
5818 reloadnum = push_reload (XEXP (op1, 0), XEXP (x, 0),
5819 &XEXP (op1, 0), &XEXP (x, 0),
5820 base_reg_class (mode, as,
5821 code, index_code),
5822 GET_MODE (x), GET_MODE (x), 0, 0,
5823 opnum, RELOAD_OTHER);
5824
5825 update_auto_inc_notes (this_insn, regno, reloadnum);
5826 return 0;
5827 }
5828 }
5829 return 0;
5830
5831 case POST_INC:
5832 case POST_DEC:
5833 case PRE_INC:
5834 case PRE_DEC:
5835 if (REG_P (XEXP (x, 0)))
5836 {
5837 int regno = REGNO (XEXP (x, 0));
5838 int value = 0;
5839 rtx x_orig = x;
5840
5841 /* A register that is incremented cannot be constant! */
5842 gcc_assert (regno < FIRST_PSEUDO_REGISTER
5843 || reg_equiv_constant (regno) == 0);
5844
5845 /* Handle a register that is equivalent to a memory location
5846 which cannot be addressed directly. */
5847 if (reg_equiv_memory_loc (regno) != 0
5848 && (reg_equiv_address (regno) != 0 || num_not_at_initial_offset))
5849 {
5850 rtx tem = make_memloc (XEXP (x, 0), regno);
5851 if (reg_equiv_address (regno)
5852 || ! rtx_equal_p (tem, reg_equiv_mem (regno)))
5853 {
5854 rtx orig = tem;
5855
5856 /* First reload the memory location's address.
5857 We can't use ADDR_TYPE (type) here, because we need to
5858 write back the value after reading it, hence we actually
5859 need two registers. */
5860 find_reloads_address (GET_MODE (tem), &tem, XEXP (tem, 0),
5861 &XEXP (tem, 0), opnum, type,
5862 ind_levels, insn);
5863 reloaded_inner_of_autoinc = true;
5864 if (!rtx_equal_p (tem, orig))
5865 push_reg_equiv_alt_mem (regno, tem);
5866 /* Put this inside a new increment-expression. */
5867 x = gen_rtx_fmt_e (GET_CODE (x), GET_MODE (x), tem);
5868 /* Proceed to reload that, as if it contained a register. */
5869 }
5870 }
5871
5872 /* If we have a hard register that is ok in this incdec context,
5873 don't make a reload. If the register isn't nice enough for
5874 autoincdec, we can reload it. But, if an autoincrement of a
5875 register that we here verified as playing nice, still outside
5876 isn't "valid", it must be that no autoincrement is "valid".
5877 If that is true and something made an autoincrement anyway,
5878 this must be a special context where one is allowed.
5879 (For example, a "push" instruction.)
5880 We can't improve this address, so leave it alone. */
5881
5882 /* Otherwise, reload the autoincrement into a suitable hard reg
5883 and record how much to increment by. */
5884
5885 if (reg_renumber[regno] >= 0)
5886 regno = reg_renumber[regno];
5887 if (regno >= FIRST_PSEUDO_REGISTER
5888 || !REG_OK_FOR_CONTEXT (context, regno, mode, as, code,
5889 index_code))
5890 {
5891 int reloadnum;
5892
5893 /* If we can output the register afterwards, do so, this
5894 saves the extra update.
5895 We can do so if we have an INSN - i.e. no JUMP_INSN nor
5896 CALL_INSN.
5897 But don't do this if we cannot directly address the
5898 memory location, since this will make it harder to
5899 reuse address reloads, and increases register pressure.
5900 Also don't do this if we can probably update x directly. */
5901 rtx equiv = (MEM_P (XEXP (x, 0))
5902 ? XEXP (x, 0)
5903 : reg_equiv_mem (regno));
5904 enum insn_code icode = optab_handler (add_optab, GET_MODE (x));
5905 if (insn && NONJUMP_INSN_P (insn)
5906 && (regno < FIRST_PSEUDO_REGISTER
5907 || (equiv
5908 && memory_operand (equiv, GET_MODE (equiv))
5909 && ! (icode != CODE_FOR_nothing
5910 && insn_operand_matches (icode, 0, equiv)
5911 && insn_operand_matches (icode, 1, equiv))))
5912 /* Using RELOAD_OTHER means we emit this and the reload we
5913 made earlier in the wrong order. */
5914 && !reloaded_inner_of_autoinc)
5915 {
5916 /* We use the original pseudo for loc, so that
5917 emit_reload_insns() knows which pseudo this
5918 reload refers to and updates the pseudo rtx, not
5919 its equivalent memory location, as well as the
5920 corresponding entry in reg_last_reload_reg. */
5921 loc = &XEXP (x_orig, 0);
5922 x = XEXP (x, 0);
5923 reloadnum
5924 = push_reload (x, x, loc, loc,
5925 context_reg_class,
5926 GET_MODE (x), GET_MODE (x), 0, 0,
5927 opnum, RELOAD_OTHER);
5928 }
5929 else
5930 {
5931 reloadnum
5932 = push_reload (x, x, loc, (rtx*) 0,
5933 context_reg_class,
5934 GET_MODE (x), GET_MODE (x), 0, 0,
5935 opnum, type);
5936 rld[reloadnum].inc
5937 = find_inc_amount (PATTERN (this_insn), XEXP (x_orig, 0));
5938
5939 value = 1;
5940 }
5941
5942 update_auto_inc_notes (this_insn, REGNO (XEXP (x_orig, 0)),
5943 reloadnum);
5944 }
5945 return value;
5946 }
5947 return 0;
5948
5949 case TRUNCATE:
5950 case SIGN_EXTEND:
5951 case ZERO_EXTEND:
5952 /* Look for parts to reload in the inner expression and reload them
5953 too, in addition to this operation. Reloading all inner parts in
5954 addition to this one shouldn't be necessary, but at this point,
5955 we don't know if we can possibly omit any part that *can* be
5956 reloaded. Targets that are better off reloading just either part
5957 (or perhaps even a different part of an outer expression), should
5958 define LEGITIMIZE_RELOAD_ADDRESS. */
5959 find_reloads_address_1 (GET_MODE (XEXP (x, 0)), as, XEXP (x, 0),
5960 context, code, SCRATCH, &XEXP (x, 0), opnum,
5961 type, ind_levels, insn);
5962 push_reload (x, NULL_RTX, loc, (rtx*) 0,
5963 context_reg_class,
5964 GET_MODE (x), VOIDmode, 0, 0, opnum, type);
5965 return 1;
5966
5967 case MEM:
5968 /* This is probably the result of a substitution, by eliminate_regs, of
5969 an equivalent address for a pseudo that was not allocated to a hard
5970 register. Verify that the specified address is valid and reload it
5971 into a register.
5972
5973 Since we know we are going to reload this item, don't decrement for
5974 the indirection level.
5975
5976 Note that this is actually conservative: it would be slightly more
5977 efficient to use the value of SPILL_INDIRECT_LEVELS from
5978 reload1.cc here. */
5979
5980 find_reloads_address (GET_MODE (x), loc, XEXP (x, 0), &XEXP (x, 0),
5981 opnum, ADDR_TYPE (type), ind_levels, insn);
5982 push_reload (*loc, NULL_RTX, loc, (rtx*) 0,
5983 context_reg_class,
5984 GET_MODE (x), VOIDmode, 0, 0, opnum, type);
5985 return 1;
5986
5987 case REG:
5988 {
5989 int regno = REGNO (x);
5990
5991 if (reg_equiv_constant (regno) != 0)
5992 {
5993 find_reloads_address_part (reg_equiv_constant (regno), loc,
5994 context_reg_class,
5995 GET_MODE (x), opnum, type, ind_levels);
5996 return 1;
5997 }
5998
5999 #if 0 /* This might screw code in reload1.cc to delete prior output-reload
6000 that feeds this insn. */
6001 if (reg_equiv_mem (regno) != 0)
6002 {
6003 push_reload (reg_equiv_mem (regno), NULL_RTX, loc, (rtx*) 0,
6004 context_reg_class,
6005 GET_MODE (x), VOIDmode, 0, 0, opnum, type);
6006 return 1;
6007 }
6008 #endif
6009
6010 if (reg_equiv_memory_loc (regno)
6011 && (reg_equiv_address (regno) != 0 || num_not_at_initial_offset))
6012 {
6013 rtx tem = make_memloc (x, regno);
6014 if (reg_equiv_address (regno) != 0
6015 || ! rtx_equal_p (tem, reg_equiv_mem (regno)))
6016 {
6017 x = tem;
6018 find_reloads_address (GET_MODE (x), &x, XEXP (x, 0),
6019 &XEXP (x, 0), opnum, ADDR_TYPE (type),
6020 ind_levels, insn);
6021 if (!rtx_equal_p (x, tem))
6022 push_reg_equiv_alt_mem (regno, x);
6023 }
6024 }
6025
6026 if (reg_renumber[regno] >= 0)
6027 regno = reg_renumber[regno];
6028
6029 if (regno >= FIRST_PSEUDO_REGISTER
6030 || !REG_OK_FOR_CONTEXT (context, regno, mode, as, outer_code,
6031 index_code))
6032 {
6033 push_reload (x, NULL_RTX, loc, (rtx*) 0,
6034 context_reg_class,
6035 GET_MODE (x), VOIDmode, 0, 0, opnum, type);
6036 return 1;
6037 }
6038
6039 /* If a register appearing in an address is the subject of a CLOBBER
6040 in this insn, reload it into some other register to be safe.
6041 The CLOBBER is supposed to make the register unavailable
6042 from before this insn to after it. */
6043 if (regno_clobbered_p (regno, this_insn, GET_MODE (x), 0))
6044 {
6045 push_reload (x, NULL_RTX, loc, (rtx*) 0,
6046 context_reg_class,
6047 GET_MODE (x), VOIDmode, 0, 0, opnum, type);
6048 return 1;
6049 }
6050 }
6051 return 0;
6052
6053 case SUBREG:
6054 if (REG_P (SUBREG_REG (x)))
6055 {
6056 /* If this is a SUBREG of a hard register and the resulting register
6057 is of the wrong class, reload the whole SUBREG. This avoids
6058 needless copies if SUBREG_REG is multi-word. */
6059 if (REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER)
6060 {
6061 int regno ATTRIBUTE_UNUSED = subreg_regno (x);
6062
6063 if (!REG_OK_FOR_CONTEXT (context, regno, mode, as, outer_code,
6064 index_code))
6065 {
6066 push_reload (x, NULL_RTX, loc, (rtx*) 0,
6067 context_reg_class,
6068 GET_MODE (x), VOIDmode, 0, 0, opnum, type);
6069 return 1;
6070 }
6071 }
6072 /* If this is a SUBREG of a pseudo-register, and the pseudo-register
6073 is larger than the class size, then reload the whole SUBREG. */
6074 else
6075 {
6076 enum reg_class rclass = context_reg_class;
6077 if (ira_reg_class_max_nregs [rclass][GET_MODE (SUBREG_REG (x))]
6078 > reg_class_size[(int) rclass])
6079 {
6080 /* If the inner register will be replaced by a memory
6081 reference, we can do this only if we can replace the
6082 whole subreg by a (narrower) memory reference. If
6083 this is not possible, fall through and reload just
6084 the inner register (including address reloads). */
6085 if (reg_equiv_memory_loc (REGNO (SUBREG_REG (x))) != 0)
6086 {
6087 rtx tem = find_reloads_subreg_address (x, opnum,
6088 ADDR_TYPE (type),
6089 ind_levels, insn,
6090 NULL);
6091 if (tem)
6092 {
6093 push_reload (tem, NULL_RTX, loc, (rtx*) 0, rclass,
6094 GET_MODE (tem), VOIDmode, 0, 0,
6095 opnum, type);
6096 return 1;
6097 }
6098 }
6099 else
6100 {
6101 push_reload (x, NULL_RTX, loc, (rtx*) 0, rclass,
6102 GET_MODE (x), VOIDmode, 0, 0, opnum, type);
6103 return 1;
6104 }
6105 }
6106 }
6107 }
6108 break;
6109
6110 default:
6111 break;
6112 }
6113
6114 {
6115 const char *fmt = GET_RTX_FORMAT (code);
6116 int i;
6117
6118 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6119 {
6120 if (fmt[i] == 'e')
6121 /* Pass SCRATCH for INDEX_CODE, since CODE can never be a PLUS once
6122 we get here. */
6123 find_reloads_address_1 (mode, as, XEXP (x, i), context,
6124 code, SCRATCH, &XEXP (x, i),
6125 opnum, type, ind_levels, insn);
6126 }
6127 }
6128
6129 #undef REG_OK_FOR_CONTEXT
6130 return 0;
6131 }
6132
6133 /* X, which is found at *LOC, is a part of an address that needs to be
6134 reloaded into a register of class RCLASS. If X is a constant, or if
6135 X is a PLUS that contains a constant, check that the constant is a
6136 legitimate operand and that we are supposed to be able to load
6137 it into the register.
6138
6139 If not, force the constant into memory and reload the MEM instead.
6140
6141 MODE is the mode to use, in case X is an integer constant.
6142
6143 OPNUM and TYPE describe the purpose of any reloads made.
6144
6145 IND_LEVELS says how many levels of indirect addressing this machine
6146 supports. */
6147
6148 static void
find_reloads_address_part(rtx x,rtx * loc,enum reg_class rclass,machine_mode mode,int opnum,enum reload_type type,int ind_levels)6149 find_reloads_address_part (rtx x, rtx *loc, enum reg_class rclass,
6150 machine_mode mode, int opnum,
6151 enum reload_type type, int ind_levels)
6152 {
6153 if (CONSTANT_P (x)
6154 && (!targetm.legitimate_constant_p (mode, x)
6155 || targetm.preferred_reload_class (x, rclass) == NO_REGS))
6156 {
6157 x = force_const_mem (mode, x);
6158 find_reloads_address (mode, &x, XEXP (x, 0), &XEXP (x, 0),
6159 opnum, type, ind_levels, 0);
6160 }
6161
6162 else if (GET_CODE (x) == PLUS
6163 && CONSTANT_P (XEXP (x, 1))
6164 && (!targetm.legitimate_constant_p (GET_MODE (x), XEXP (x, 1))
6165 || targetm.preferred_reload_class (XEXP (x, 1), rclass)
6166 == NO_REGS))
6167 {
6168 rtx tem;
6169
6170 tem = force_const_mem (GET_MODE (x), XEXP (x, 1));
6171 x = gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0), tem);
6172 find_reloads_address (mode, &XEXP (x, 1), XEXP (tem, 0), &XEXP (tem, 0),
6173 opnum, type, ind_levels, 0);
6174 }
6175
6176 push_reload (x, NULL_RTX, loc, (rtx*) 0, rclass,
6177 mode, VOIDmode, 0, 0, opnum, type);
6178 }
6179
6180 /* X, a subreg of a pseudo, is a part of an address that needs to be
6181 reloaded, and the pseusdo is equivalent to a memory location.
6182
6183 Attempt to replace the whole subreg by a (possibly narrower or wider)
6184 memory reference. If this is possible, return this new memory
6185 reference, and push all required address reloads. Otherwise,
6186 return NULL.
6187
6188 OPNUM and TYPE identify the purpose of the reload.
6189
6190 IND_LEVELS says how many levels of indirect addressing are
6191 supported at this point in the address.
6192
6193 INSN, if nonzero, is the insn in which we do the reload. It is used
6194 to determine where to put USEs for pseudos that we have to replace with
6195 stack slots. */
6196
6197 static rtx
find_reloads_subreg_address(rtx x,int opnum,enum reload_type type,int ind_levels,rtx_insn * insn,int * address_reloaded)6198 find_reloads_subreg_address (rtx x, int opnum, enum reload_type type,
6199 int ind_levels, rtx_insn *insn,
6200 int *address_reloaded)
6201 {
6202 machine_mode outer_mode = GET_MODE (x);
6203 machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
6204 int regno = REGNO (SUBREG_REG (x));
6205 int reloaded = 0;
6206 rtx tem, orig;
6207 poly_int64 offset;
6208
6209 gcc_assert (reg_equiv_memory_loc (regno) != 0);
6210
6211 /* We cannot replace the subreg with a modified memory reference if:
6212
6213 - we have a paradoxical subreg that implicitly acts as a zero or
6214 sign extension operation due to LOAD_EXTEND_OP;
6215
6216 - we have a subreg that is implicitly supposed to act on the full
6217 register due to WORD_REGISTER_OPERATIONS (see also eliminate_regs);
6218
6219 - the address of the equivalent memory location is mode-dependent; or
6220
6221 - we have a paradoxical subreg and the resulting memory is not
6222 sufficiently aligned to allow access in the wider mode.
6223
6224 In addition, we choose not to perform the replacement for *any*
6225 paradoxical subreg, even if it were possible in principle. This
6226 is to avoid generating wider memory references than necessary.
6227
6228 This corresponds to how previous versions of reload used to handle
6229 paradoxical subregs where no address reload was required. */
6230
6231 if (paradoxical_subreg_p (x))
6232 return NULL;
6233
6234 if (WORD_REGISTER_OPERATIONS
6235 && partial_subreg_p (outer_mode, inner_mode)
6236 && known_equal_after_align_down (GET_MODE_SIZE (outer_mode) - 1,
6237 GET_MODE_SIZE (inner_mode) - 1,
6238 UNITS_PER_WORD))
6239 return NULL;
6240
6241 /* Since we don't attempt to handle paradoxical subregs, we can just
6242 call into simplify_subreg, which will handle all remaining checks
6243 for us. */
6244 orig = make_memloc (SUBREG_REG (x), regno);
6245 offset = SUBREG_BYTE (x);
6246 tem = simplify_subreg (outer_mode, orig, inner_mode, offset);
6247 if (!tem || !MEM_P (tem))
6248 return NULL;
6249
6250 /* Now push all required address reloads, if any. */
6251 reloaded = find_reloads_address (GET_MODE (tem), &tem,
6252 XEXP (tem, 0), &XEXP (tem, 0),
6253 opnum, type, ind_levels, insn);
6254 /* ??? Do we need to handle nonzero offsets somehow? */
6255 if (known_eq (offset, 0) && !rtx_equal_p (tem, orig))
6256 push_reg_equiv_alt_mem (regno, tem);
6257
6258 /* For some processors an address may be valid in the original mode but
6259 not in a smaller mode. For example, ARM accepts a scaled index register
6260 in SImode but not in HImode. Note that this is only a problem if the
6261 address in reg_equiv_mem is already invalid in the new mode; other
6262 cases would be fixed by find_reloads_address as usual.
6263
6264 ??? We attempt to handle such cases here by doing an additional reload
6265 of the full address after the usual processing by find_reloads_address.
6266 Note that this may not work in the general case, but it seems to cover
6267 the cases where this situation currently occurs. A more general fix
6268 might be to reload the *value* instead of the address, but this would
6269 not be expected by the callers of this routine as-is.
6270
6271 If find_reloads_address already completed replaced the address, there
6272 is nothing further to do. */
6273 if (reloaded == 0
6274 && reg_equiv_mem (regno) != 0
6275 && !strict_memory_address_addr_space_p
6276 (GET_MODE (x), XEXP (reg_equiv_mem (regno), 0),
6277 MEM_ADDR_SPACE (reg_equiv_mem (regno))))
6278 {
6279 push_reload (XEXP (tem, 0), NULL_RTX, &XEXP (tem, 0), (rtx*) 0,
6280 base_reg_class (GET_MODE (tem), MEM_ADDR_SPACE (tem),
6281 MEM, SCRATCH),
6282 GET_MODE (XEXP (tem, 0)), VOIDmode, 0, 0, opnum, type);
6283 reloaded = 1;
6284 }
6285
6286 /* If this is not a toplevel operand, find_reloads doesn't see this
6287 substitution. We have to emit a USE of the pseudo so that
6288 delete_output_reload can see it. */
6289 if (replace_reloads && recog_data.operand[opnum] != x)
6290 /* We mark the USE with QImode so that we recognize it as one that
6291 can be safely deleted at the end of reload. */
6292 PUT_MODE (emit_insn_before (gen_rtx_USE (VOIDmode, SUBREG_REG (x)), insn),
6293 QImode);
6294
6295 if (address_reloaded)
6296 *address_reloaded = reloaded;
6297
6298 return tem;
6299 }
6300
6301 /* Substitute into the current INSN the registers into which we have reloaded
6302 the things that need reloading. The array `replacements'
6303 contains the locations of all pointers that must be changed
6304 and says what to replace them with.
6305
6306 Return the rtx that X translates into; usually X, but modified. */
6307
6308 void
subst_reloads(rtx_insn * insn)6309 subst_reloads (rtx_insn *insn)
6310 {
6311 int i;
6312
6313 for (i = 0; i < n_replacements; i++)
6314 {
6315 struct replacement *r = &replacements[i];
6316 rtx reloadreg = rld[r->what].reg_rtx;
6317 if (reloadreg)
6318 {
6319 #ifdef DEBUG_RELOAD
6320 /* This checking takes a very long time on some platforms
6321 causing the gcc.c-torture/compile/limits-fnargs.c test
6322 to time out during testing. See PR 31850.
6323
6324 Internal consistency test. Check that we don't modify
6325 anything in the equivalence arrays. Whenever something from
6326 those arrays needs to be reloaded, it must be unshared before
6327 being substituted into; the equivalence must not be modified.
6328 Otherwise, if the equivalence is used after that, it will
6329 have been modified, and the thing substituted (probably a
6330 register) is likely overwritten and not a usable equivalence. */
6331 int check_regno;
6332
6333 for (check_regno = 0; check_regno < max_regno; check_regno++)
6334 {
6335 #define CHECK_MODF(ARRAY) \
6336 gcc_assert (!(*reg_equivs)[check_regno].ARRAY \
6337 || !loc_mentioned_in_p (r->where, \
6338 (*reg_equivs)[check_regno].ARRAY))
6339
6340 CHECK_MODF (constant);
6341 CHECK_MODF (memory_loc);
6342 CHECK_MODF (address);
6343 CHECK_MODF (mem);
6344 #undef CHECK_MODF
6345 }
6346 #endif /* DEBUG_RELOAD */
6347
6348 /* If we're replacing a LABEL_REF with a register, there must
6349 already be an indication (to e.g. flow) which label this
6350 register refers to. */
6351 gcc_assert (GET_CODE (*r->where) != LABEL_REF
6352 || !JUMP_P (insn)
6353 || find_reg_note (insn,
6354 REG_LABEL_OPERAND,
6355 XEXP (*r->where, 0))
6356 || label_is_jump_target_p (XEXP (*r->where, 0), insn));
6357
6358 /* Encapsulate RELOADREG so its machine mode matches what
6359 used to be there. Note that gen_lowpart_common will
6360 do the wrong thing if RELOADREG is multi-word. RELOADREG
6361 will always be a REG here. */
6362 if (GET_MODE (reloadreg) != r->mode && r->mode != VOIDmode)
6363 reloadreg = reload_adjust_reg_for_mode (reloadreg, r->mode);
6364
6365 *r->where = reloadreg;
6366 }
6367 /* If reload got no reg and isn't optional, something's wrong. */
6368 else
6369 gcc_assert (rld[r->what].optional);
6370 }
6371 }
6372
6373 /* Make a copy of any replacements being done into X and move those
6374 copies to locations in Y, a copy of X. */
6375
6376 void
copy_replacements(rtx x,rtx y)6377 copy_replacements (rtx x, rtx y)
6378 {
6379 copy_replacements_1 (&x, &y, n_replacements);
6380 }
6381
6382 static void
copy_replacements_1(rtx * px,rtx * py,int orig_replacements)6383 copy_replacements_1 (rtx *px, rtx *py, int orig_replacements)
6384 {
6385 int i, j;
6386 rtx x, y;
6387 struct replacement *r;
6388 enum rtx_code code;
6389 const char *fmt;
6390
6391 for (j = 0; j < orig_replacements; j++)
6392 if (replacements[j].where == px)
6393 {
6394 r = &replacements[n_replacements++];
6395 r->where = py;
6396 r->what = replacements[j].what;
6397 r->mode = replacements[j].mode;
6398 }
6399
6400 x = *px;
6401 y = *py;
6402 code = GET_CODE (x);
6403 fmt = GET_RTX_FORMAT (code);
6404
6405 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6406 {
6407 if (fmt[i] == 'e')
6408 copy_replacements_1 (&XEXP (x, i), &XEXP (y, i), orig_replacements);
6409 else if (fmt[i] == 'E')
6410 for (j = XVECLEN (x, i); --j >= 0; )
6411 copy_replacements_1 (&XVECEXP (x, i, j), &XVECEXP (y, i, j),
6412 orig_replacements);
6413 }
6414 }
6415
6416 /* Change any replacements being done to *X to be done to *Y. */
6417
6418 void
move_replacements(rtx * x,rtx * y)6419 move_replacements (rtx *x, rtx *y)
6420 {
6421 int i;
6422
6423 for (i = 0; i < n_replacements; i++)
6424 if (replacements[i].where == x)
6425 replacements[i].where = y;
6426 }
6427
6428 /* If LOC was scheduled to be replaced by something, return the replacement.
6429 Otherwise, return *LOC. */
6430
6431 rtx
find_replacement(rtx * loc)6432 find_replacement (rtx *loc)
6433 {
6434 struct replacement *r;
6435
6436 for (r = &replacements[0]; r < &replacements[n_replacements]; r++)
6437 {
6438 rtx reloadreg = rld[r->what].reg_rtx;
6439
6440 if (reloadreg && r->where == loc)
6441 {
6442 if (r->mode != VOIDmode && GET_MODE (reloadreg) != r->mode)
6443 reloadreg = reload_adjust_reg_for_mode (reloadreg, r->mode);
6444
6445 return reloadreg;
6446 }
6447 else if (reloadreg && GET_CODE (*loc) == SUBREG
6448 && r->where == &SUBREG_REG (*loc))
6449 {
6450 if (r->mode != VOIDmode && GET_MODE (reloadreg) != r->mode)
6451 reloadreg = reload_adjust_reg_for_mode (reloadreg, r->mode);
6452
6453 return simplify_gen_subreg (GET_MODE (*loc), reloadreg,
6454 GET_MODE (SUBREG_REG (*loc)),
6455 SUBREG_BYTE (*loc));
6456 }
6457 }
6458
6459 /* If *LOC is a PLUS, MINUS, or MULT, see if a replacement is scheduled for
6460 what's inside and make a new rtl if so. */
6461 if (GET_CODE (*loc) == PLUS || GET_CODE (*loc) == MINUS
6462 || GET_CODE (*loc) == MULT)
6463 {
6464 rtx x = find_replacement (&XEXP (*loc, 0));
6465 rtx y = find_replacement (&XEXP (*loc, 1));
6466
6467 if (x != XEXP (*loc, 0) || y != XEXP (*loc, 1))
6468 return gen_rtx_fmt_ee (GET_CODE (*loc), GET_MODE (*loc), x, y);
6469 }
6470
6471 return *loc;
6472 }
6473
6474 /* Return nonzero if register in range [REGNO, ENDREGNO)
6475 appears either explicitly or implicitly in X
6476 other than being stored into (except for earlyclobber operands).
6477
6478 References contained within the substructure at LOC do not count.
6479 LOC may be zero, meaning don't ignore anything.
6480
6481 This is similar to refers_to_regno_p in rtlanal.cc except that we
6482 look at equivalences for pseudos that didn't get hard registers. */
6483
6484 static int
refers_to_regno_for_reload_p(unsigned int regno,unsigned int endregno,rtx x,rtx * loc)6485 refers_to_regno_for_reload_p (unsigned int regno, unsigned int endregno,
6486 rtx x, rtx *loc)
6487 {
6488 int i;
6489 unsigned int r;
6490 RTX_CODE code;
6491 const char *fmt;
6492
6493 if (x == 0)
6494 return 0;
6495
6496 repeat:
6497 code = GET_CODE (x);
6498
6499 switch (code)
6500 {
6501 case REG:
6502 r = REGNO (x);
6503
6504 /* If this is a pseudo, a hard register must not have been allocated.
6505 X must therefore either be a constant or be in memory. */
6506 if (r >= FIRST_PSEUDO_REGISTER)
6507 {
6508 if (reg_equiv_memory_loc (r))
6509 return refers_to_regno_for_reload_p (regno, endregno,
6510 reg_equiv_memory_loc (r),
6511 (rtx*) 0);
6512
6513 gcc_assert (reg_equiv_constant (r) || reg_equiv_invariant (r));
6514 return 0;
6515 }
6516
6517 return endregno > r && regno < END_REGNO (x);
6518
6519 case SUBREG:
6520 /* If this is a SUBREG of a hard reg, we can see exactly which
6521 registers are being modified. Otherwise, handle normally. */
6522 if (REG_P (SUBREG_REG (x))
6523 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER)
6524 {
6525 unsigned int inner_regno = subreg_regno (x);
6526 unsigned int inner_endregno
6527 = inner_regno + (inner_regno < FIRST_PSEUDO_REGISTER
6528 ? subreg_nregs (x) : 1);
6529
6530 return endregno > inner_regno && regno < inner_endregno;
6531 }
6532 break;
6533
6534 case CLOBBER:
6535 case SET:
6536 if (&SET_DEST (x) != loc
6537 /* Note setting a SUBREG counts as referring to the REG it is in for
6538 a pseudo but not for hard registers since we can
6539 treat each word individually. */
6540 && ((GET_CODE (SET_DEST (x)) == SUBREG
6541 && loc != &SUBREG_REG (SET_DEST (x))
6542 && REG_P (SUBREG_REG (SET_DEST (x)))
6543 && REGNO (SUBREG_REG (SET_DEST (x))) >= FIRST_PSEUDO_REGISTER
6544 && refers_to_regno_for_reload_p (regno, endregno,
6545 SUBREG_REG (SET_DEST (x)),
6546 loc))
6547 /* If the output is an earlyclobber operand, this is
6548 a conflict. */
6549 || ((!REG_P (SET_DEST (x))
6550 || earlyclobber_operand_p (SET_DEST (x)))
6551 && refers_to_regno_for_reload_p (regno, endregno,
6552 SET_DEST (x), loc))))
6553 return 1;
6554
6555 if (code == CLOBBER || loc == &SET_SRC (x))
6556 return 0;
6557 x = SET_SRC (x);
6558 goto repeat;
6559
6560 default:
6561 break;
6562 }
6563
6564 /* X does not match, so try its subexpressions. */
6565
6566 fmt = GET_RTX_FORMAT (code);
6567 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6568 {
6569 if (fmt[i] == 'e' && loc != &XEXP (x, i))
6570 {
6571 if (i == 0)
6572 {
6573 x = XEXP (x, 0);
6574 goto repeat;
6575 }
6576 else
6577 if (refers_to_regno_for_reload_p (regno, endregno,
6578 XEXP (x, i), loc))
6579 return 1;
6580 }
6581 else if (fmt[i] == 'E')
6582 {
6583 int j;
6584 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6585 if (loc != &XVECEXP (x, i, j)
6586 && refers_to_regno_for_reload_p (regno, endregno,
6587 XVECEXP (x, i, j), loc))
6588 return 1;
6589 }
6590 }
6591 return 0;
6592 }
6593
6594 /* Nonzero if modifying X will affect IN. If X is a register or a SUBREG,
6595 we check if any register number in X conflicts with the relevant register
6596 numbers. If X is a constant, return 0. If X is a MEM, return 1 iff IN
6597 contains a MEM (we don't bother checking for memory addresses that can't
6598 conflict because we expect this to be a rare case.
6599
6600 This function is similar to reg_overlap_mentioned_p in rtlanal.cc except
6601 that we look at equivalences for pseudos that didn't get hard registers. */
6602
6603 int
reg_overlap_mentioned_for_reload_p(rtx x,rtx in)6604 reg_overlap_mentioned_for_reload_p (rtx x, rtx in)
6605 {
6606 int regno, endregno;
6607
6608 /* Overly conservative. */
6609 if (GET_CODE (x) == STRICT_LOW_PART
6610 || GET_RTX_CLASS (GET_CODE (x)) == RTX_AUTOINC)
6611 x = XEXP (x, 0);
6612
6613 /* If either argument is a constant, then modifying X cannot affect IN. */
6614 if (CONSTANT_P (x) || CONSTANT_P (in))
6615 return 0;
6616 else if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
6617 return refers_to_mem_for_reload_p (in);
6618 else if (GET_CODE (x) == SUBREG)
6619 {
6620 regno = REGNO (SUBREG_REG (x));
6621 if (regno < FIRST_PSEUDO_REGISTER)
6622 regno += subreg_regno_offset (REGNO (SUBREG_REG (x)),
6623 GET_MODE (SUBREG_REG (x)),
6624 SUBREG_BYTE (x),
6625 GET_MODE (x));
6626 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
6627 ? subreg_nregs (x) : 1);
6628
6629 return refers_to_regno_for_reload_p (regno, endregno, in, (rtx*) 0);
6630 }
6631 else if (REG_P (x))
6632 {
6633 regno = REGNO (x);
6634
6635 /* If this is a pseudo, it must not have been assigned a hard register.
6636 Therefore, it must either be in memory or be a constant. */
6637
6638 if (regno >= FIRST_PSEUDO_REGISTER)
6639 {
6640 if (reg_equiv_memory_loc (regno))
6641 return refers_to_mem_for_reload_p (in);
6642 gcc_assert (reg_equiv_constant (regno));
6643 return 0;
6644 }
6645
6646 endregno = END_REGNO (x);
6647
6648 return refers_to_regno_for_reload_p (regno, endregno, in, (rtx*) 0);
6649 }
6650 else if (MEM_P (x))
6651 return refers_to_mem_for_reload_p (in);
6652 else if (GET_CODE (x) == SCRATCH || GET_CODE (x) == PC)
6653 return reg_mentioned_p (x, in);
6654 else
6655 {
6656 gcc_assert (GET_CODE (x) == PLUS);
6657
6658 /* We actually want to know if X is mentioned somewhere inside IN.
6659 We must not say that (plus (sp) (const_int 124)) is in
6660 (plus (sp) (const_int 64)), since that can lead to incorrect reload
6661 allocation when spuriously changing a RELOAD_FOR_OUTPUT_ADDRESS
6662 into a RELOAD_OTHER on behalf of another RELOAD_OTHER. */
6663 while (MEM_P (in))
6664 in = XEXP (in, 0);
6665 if (REG_P (in))
6666 return 0;
6667 else if (GET_CODE (in) == PLUS)
6668 return (rtx_equal_p (x, in)
6669 || reg_overlap_mentioned_for_reload_p (x, XEXP (in, 0))
6670 || reg_overlap_mentioned_for_reload_p (x, XEXP (in, 1)));
6671 else
6672 return (reg_overlap_mentioned_for_reload_p (XEXP (x, 0), in)
6673 || reg_overlap_mentioned_for_reload_p (XEXP (x, 1), in));
6674 }
6675 }
6676
6677 /* Return nonzero if anything in X contains a MEM. Look also for pseudo
6678 registers. */
6679
6680 static int
refers_to_mem_for_reload_p(rtx x)6681 refers_to_mem_for_reload_p (rtx x)
6682 {
6683 const char *fmt;
6684 int i;
6685
6686 if (MEM_P (x))
6687 return 1;
6688
6689 if (REG_P (x))
6690 return (REGNO (x) >= FIRST_PSEUDO_REGISTER
6691 && reg_equiv_memory_loc (REGNO (x)));
6692
6693 fmt = GET_RTX_FORMAT (GET_CODE (x));
6694 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
6695 if (fmt[i] == 'e'
6696 && (MEM_P (XEXP (x, i))
6697 || refers_to_mem_for_reload_p (XEXP (x, i))))
6698 return 1;
6699
6700 return 0;
6701 }
6702
6703 /* Check the insns before INSN to see if there is a suitable register
6704 containing the same value as GOAL.
6705 If OTHER is -1, look for a register in class RCLASS.
6706 Otherwise, just see if register number OTHER shares GOAL's value.
6707
6708 Return an rtx for the register found, or zero if none is found.
6709
6710 If RELOAD_REG_P is (short *)1,
6711 we reject any hard reg that appears in reload_reg_rtx
6712 because such a hard reg is also needed coming into this insn.
6713
6714 If RELOAD_REG_P is any other nonzero value,
6715 it is a vector indexed by hard reg number
6716 and we reject any hard reg whose element in the vector is nonnegative
6717 as well as any that appears in reload_reg_rtx.
6718
6719 If GOAL is zero, then GOALREG is a register number; we look
6720 for an equivalent for that register.
6721
6722 MODE is the machine mode of the value we want an equivalence for.
6723 If GOAL is nonzero and not VOIDmode, then it must have mode MODE.
6724
6725 This function is used by jump.cc as well as in the reload pass.
6726
6727 If GOAL is the sum of the stack pointer and a constant, we treat it
6728 as if it were a constant except that sp is required to be unchanging. */
6729
6730 rtx
find_equiv_reg(rtx goal,rtx_insn * insn,enum reg_class rclass,int other,short * reload_reg_p,int goalreg,machine_mode mode)6731 find_equiv_reg (rtx goal, rtx_insn *insn, enum reg_class rclass, int other,
6732 short *reload_reg_p, int goalreg, machine_mode mode)
6733 {
6734 rtx_insn *p = insn;
6735 rtx goaltry, valtry, value;
6736 rtx_insn *where;
6737 rtx pat;
6738 int regno = -1;
6739 int valueno;
6740 int goal_mem = 0;
6741 int goal_const = 0;
6742 int goal_mem_addr_varies = 0;
6743 int need_stable_sp = 0;
6744 int nregs;
6745 int valuenregs;
6746 int num = 0;
6747
6748 if (goal == 0)
6749 regno = goalreg;
6750 else if (REG_P (goal))
6751 regno = REGNO (goal);
6752 else if (MEM_P (goal))
6753 {
6754 enum rtx_code code = GET_CODE (XEXP (goal, 0));
6755 if (MEM_VOLATILE_P (goal))
6756 return 0;
6757 if (flag_float_store && SCALAR_FLOAT_MODE_P (GET_MODE (goal)))
6758 return 0;
6759 /* An address with side effects must be reexecuted. */
6760 switch (code)
6761 {
6762 case POST_INC:
6763 case PRE_INC:
6764 case POST_DEC:
6765 case PRE_DEC:
6766 case POST_MODIFY:
6767 case PRE_MODIFY:
6768 return 0;
6769 default:
6770 break;
6771 }
6772 goal_mem = 1;
6773 }
6774 else if (CONSTANT_P (goal))
6775 goal_const = 1;
6776 else if (GET_CODE (goal) == PLUS
6777 && XEXP (goal, 0) == stack_pointer_rtx
6778 && CONSTANT_P (XEXP (goal, 1)))
6779 goal_const = need_stable_sp = 1;
6780 else if (GET_CODE (goal) == PLUS
6781 && XEXP (goal, 0) == frame_pointer_rtx
6782 && CONSTANT_P (XEXP (goal, 1)))
6783 goal_const = 1;
6784 else
6785 return 0;
6786
6787 num = 0;
6788 /* Scan insns back from INSN, looking for one that copies
6789 a value into or out of GOAL.
6790 Stop and give up if we reach a label. */
6791
6792 while (1)
6793 {
6794 p = PREV_INSN (p);
6795 if (p && DEBUG_INSN_P (p))
6796 continue;
6797 num++;
6798 if (p == 0 || LABEL_P (p)
6799 || num > param_max_reload_search_insns)
6800 return 0;
6801
6802 /* Don't reuse register contents from before a setjmp-type
6803 function call; on the second return (from the longjmp) it
6804 might have been clobbered by a later reuse. It doesn't
6805 seem worthwhile to actually go and see if it is actually
6806 reused even if that information would be readily available;
6807 just don't reuse it across the setjmp call. */
6808 if (CALL_P (p) && find_reg_note (p, REG_SETJMP, NULL_RTX))
6809 return 0;
6810
6811 if (NONJUMP_INSN_P (p)
6812 /* If we don't want spill regs ... */
6813 && (! (reload_reg_p != 0
6814 && reload_reg_p != (short *) HOST_WIDE_INT_1)
6815 /* ... then ignore insns introduced by reload; they aren't
6816 useful and can cause results in reload_as_needed to be
6817 different from what they were when calculating the need for
6818 spills. If we notice an input-reload insn here, we will
6819 reject it below, but it might hide a usable equivalent.
6820 That makes bad code. It may even fail: perhaps no reg was
6821 spilled for this insn because it was assumed we would find
6822 that equivalent. */
6823 || INSN_UID (p) < reload_first_uid))
6824 {
6825 rtx tem;
6826 pat = single_set (p);
6827
6828 /* First check for something that sets some reg equal to GOAL. */
6829 if (pat != 0
6830 && ((regno >= 0
6831 && true_regnum (SET_SRC (pat)) == regno
6832 && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0)
6833 ||
6834 (regno >= 0
6835 && true_regnum (SET_DEST (pat)) == regno
6836 && (valueno = true_regnum (valtry = SET_SRC (pat))) >= 0)
6837 ||
6838 (goal_const && rtx_equal_p (SET_SRC (pat), goal)
6839 /* When looking for stack pointer + const,
6840 make sure we don't use a stack adjust. */
6841 && !reg_overlap_mentioned_for_reload_p (SET_DEST (pat), goal)
6842 && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0)
6843 || (goal_mem
6844 && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0
6845 && rtx_renumbered_equal_p (goal, SET_SRC (pat)))
6846 || (goal_mem
6847 && (valueno = true_regnum (valtry = SET_SRC (pat))) >= 0
6848 && rtx_renumbered_equal_p (goal, SET_DEST (pat)))
6849 /* If we are looking for a constant,
6850 and something equivalent to that constant was copied
6851 into a reg, we can use that reg. */
6852 || (goal_const && REG_NOTES (p) != 0
6853 && (tem = find_reg_note (p, REG_EQUIV, NULL_RTX))
6854 && ((rtx_equal_p (XEXP (tem, 0), goal)
6855 && (valueno
6856 = true_regnum (valtry = SET_DEST (pat))) >= 0)
6857 || (REG_P (SET_DEST (pat))
6858 && CONST_DOUBLE_AS_FLOAT_P (XEXP (tem, 0))
6859 && SCALAR_FLOAT_MODE_P (GET_MODE (XEXP (tem, 0)))
6860 && CONST_INT_P (goal)
6861 && (goaltry = operand_subword (XEXP (tem, 0), 0,
6862 0, VOIDmode)) != 0
6863 && rtx_equal_p (goal, goaltry)
6864 && (valtry
6865 = operand_subword (SET_DEST (pat), 0, 0,
6866 VOIDmode))
6867 && (valueno = true_regnum (valtry)) >= 0)))
6868 || (goal_const && (tem = find_reg_note (p, REG_EQUIV,
6869 NULL_RTX))
6870 && REG_P (SET_DEST (pat))
6871 && CONST_DOUBLE_AS_FLOAT_P (XEXP (tem, 0))
6872 && SCALAR_FLOAT_MODE_P (GET_MODE (XEXP (tem, 0)))
6873 && CONST_INT_P (goal)
6874 && (goaltry = operand_subword (XEXP (tem, 0), 1, 0,
6875 VOIDmode)) != 0
6876 && rtx_equal_p (goal, goaltry)
6877 && (valtry
6878 = operand_subword (SET_DEST (pat), 1, 0, VOIDmode))
6879 && (valueno = true_regnum (valtry)) >= 0)))
6880 {
6881 if (other >= 0)
6882 {
6883 if (valueno != other)
6884 continue;
6885 }
6886 else if ((unsigned) valueno >= FIRST_PSEUDO_REGISTER)
6887 continue;
6888 else if (!in_hard_reg_set_p (reg_class_contents[(int) rclass],
6889 mode, valueno))
6890 continue;
6891 value = valtry;
6892 where = p;
6893 break;
6894 }
6895 }
6896 }
6897
6898 /* We found a previous insn copying GOAL into a suitable other reg VALUE
6899 (or copying VALUE into GOAL, if GOAL is also a register).
6900 Now verify that VALUE is really valid. */
6901
6902 /* VALUENO is the register number of VALUE; a hard register. */
6903
6904 /* Don't try to re-use something that is killed in this insn. We want
6905 to be able to trust REG_UNUSED notes. */
6906 if (REG_NOTES (where) != 0 && find_reg_note (where, REG_UNUSED, value))
6907 return 0;
6908
6909 /* If we propose to get the value from the stack pointer or if GOAL is
6910 a MEM based on the stack pointer, we need a stable SP. */
6911 if (valueno == STACK_POINTER_REGNUM || regno == STACK_POINTER_REGNUM
6912 || (goal_mem && reg_overlap_mentioned_for_reload_p (stack_pointer_rtx,
6913 goal)))
6914 need_stable_sp = 1;
6915
6916 /* Reject VALUE if the copy-insn moved the wrong sort of datum. */
6917 if (GET_MODE (value) != mode)
6918 return 0;
6919
6920 /* Reject VALUE if it was loaded from GOAL
6921 and is also a register that appears in the address of GOAL. */
6922
6923 if (goal_mem && value == SET_DEST (single_set (where))
6924 && refers_to_regno_for_reload_p (valueno, end_hard_regno (mode, valueno),
6925 goal, (rtx*) 0))
6926 return 0;
6927
6928 /* Reject registers that overlap GOAL. */
6929
6930 if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER)
6931 nregs = hard_regno_nregs (regno, mode);
6932 else
6933 nregs = 1;
6934 valuenregs = hard_regno_nregs (valueno, mode);
6935
6936 if (!goal_mem && !goal_const
6937 && regno + nregs > valueno && regno < valueno + valuenregs)
6938 return 0;
6939
6940 /* Reject VALUE if it is one of the regs reserved for reloads.
6941 Reload1 knows how to reuse them anyway, and it would get
6942 confused if we allocated one without its knowledge.
6943 (Now that insns introduced by reload are ignored above,
6944 this case shouldn't happen, but I'm not positive.) */
6945
6946 if (reload_reg_p != 0 && reload_reg_p != (short *) HOST_WIDE_INT_1)
6947 {
6948 int i;
6949 for (i = 0; i < valuenregs; ++i)
6950 if (reload_reg_p[valueno + i] >= 0)
6951 return 0;
6952 }
6953
6954 /* Reject VALUE if it is a register being used for an input reload
6955 even if it is not one of those reserved. */
6956
6957 if (reload_reg_p != 0)
6958 {
6959 int i;
6960 for (i = 0; i < n_reloads; i++)
6961 if (rld[i].reg_rtx != 0
6962 && rld[i].in
6963 && (int) REGNO (rld[i].reg_rtx) < valueno + valuenregs
6964 && (int) END_REGNO (rld[i].reg_rtx) > valueno)
6965 return 0;
6966 }
6967
6968 if (goal_mem)
6969 /* We must treat frame pointer as varying here,
6970 since it can vary--in a nonlocal goto as generated by expand_goto. */
6971 goal_mem_addr_varies = !CONSTANT_ADDRESS_P (XEXP (goal, 0));
6972
6973 /* Now verify that the values of GOAL and VALUE remain unaltered
6974 until INSN is reached. */
6975
6976 p = insn;
6977 while (1)
6978 {
6979 p = PREV_INSN (p);
6980 if (p == where)
6981 return value;
6982
6983 /* Don't trust the conversion past a function call
6984 if either of the two is in a call-clobbered register, or memory. */
6985 if (CALL_P (p))
6986 {
6987 if (goal_mem || need_stable_sp)
6988 return 0;
6989
6990 function_abi callee_abi = insn_callee_abi (p);
6991 if (regno >= 0
6992 && regno < FIRST_PSEUDO_REGISTER
6993 && callee_abi.clobbers_reg_p (mode, regno))
6994 return 0;
6995
6996 if (valueno >= 0
6997 && valueno < FIRST_PSEUDO_REGISTER
6998 && callee_abi.clobbers_reg_p (mode, valueno))
6999 return 0;
7000 }
7001
7002 if (INSN_P (p))
7003 {
7004 pat = PATTERN (p);
7005
7006 /* Watch out for unspec_volatile, and volatile asms. */
7007 if (volatile_insn_p (pat))
7008 return 0;
7009
7010 /* If this insn P stores in either GOAL or VALUE, return 0.
7011 If GOAL is a memory ref and this insn writes memory, return 0.
7012 If GOAL is a memory ref and its address is not constant,
7013 and this insn P changes a register used in GOAL, return 0. */
7014
7015 if (GET_CODE (pat) == COND_EXEC)
7016 pat = COND_EXEC_CODE (pat);
7017 if (GET_CODE (pat) == SET || GET_CODE (pat) == CLOBBER)
7018 {
7019 rtx dest = SET_DEST (pat);
7020 while (GET_CODE (dest) == SUBREG
7021 || GET_CODE (dest) == ZERO_EXTRACT
7022 || GET_CODE (dest) == STRICT_LOW_PART)
7023 dest = XEXP (dest, 0);
7024 if (REG_P (dest))
7025 {
7026 int xregno = REGNO (dest);
7027 int end_xregno = END_REGNO (dest);
7028 if (xregno < regno + nregs && end_xregno > regno)
7029 return 0;
7030 if (xregno < valueno + valuenregs
7031 && end_xregno > valueno)
7032 return 0;
7033 if (goal_mem_addr_varies
7034 && reg_overlap_mentioned_for_reload_p (dest, goal))
7035 return 0;
7036 if (xregno == STACK_POINTER_REGNUM && need_stable_sp)
7037 return 0;
7038 }
7039 else if (goal_mem && MEM_P (dest)
7040 && ! push_operand (dest, GET_MODE (dest)))
7041 return 0;
7042 else if (MEM_P (dest) && regno >= FIRST_PSEUDO_REGISTER
7043 && reg_equiv_memory_loc (regno) != 0)
7044 return 0;
7045 else if (need_stable_sp && push_operand (dest, GET_MODE (dest)))
7046 return 0;
7047 }
7048 else if (GET_CODE (pat) == PARALLEL)
7049 {
7050 int i;
7051 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
7052 {
7053 rtx v1 = XVECEXP (pat, 0, i);
7054 if (GET_CODE (v1) == COND_EXEC)
7055 v1 = COND_EXEC_CODE (v1);
7056 if (GET_CODE (v1) == SET || GET_CODE (v1) == CLOBBER)
7057 {
7058 rtx dest = SET_DEST (v1);
7059 while (GET_CODE (dest) == SUBREG
7060 || GET_CODE (dest) == ZERO_EXTRACT
7061 || GET_CODE (dest) == STRICT_LOW_PART)
7062 dest = XEXP (dest, 0);
7063 if (REG_P (dest))
7064 {
7065 int xregno = REGNO (dest);
7066 int end_xregno = END_REGNO (dest);
7067 if (xregno < regno + nregs
7068 && end_xregno > regno)
7069 return 0;
7070 if (xregno < valueno + valuenregs
7071 && end_xregno > valueno)
7072 return 0;
7073 if (goal_mem_addr_varies
7074 && reg_overlap_mentioned_for_reload_p (dest,
7075 goal))
7076 return 0;
7077 if (xregno == STACK_POINTER_REGNUM && need_stable_sp)
7078 return 0;
7079 }
7080 else if (goal_mem && MEM_P (dest)
7081 && ! push_operand (dest, GET_MODE (dest)))
7082 return 0;
7083 else if (MEM_P (dest) && regno >= FIRST_PSEUDO_REGISTER
7084 && reg_equiv_memory_loc (regno) != 0)
7085 return 0;
7086 else if (need_stable_sp
7087 && push_operand (dest, GET_MODE (dest)))
7088 return 0;
7089 }
7090 }
7091 }
7092
7093 if (CALL_P (p) && CALL_INSN_FUNCTION_USAGE (p))
7094 {
7095 rtx link;
7096
7097 for (link = CALL_INSN_FUNCTION_USAGE (p); XEXP (link, 1) != 0;
7098 link = XEXP (link, 1))
7099 {
7100 pat = XEXP (link, 0);
7101 if (GET_CODE (pat) == CLOBBER)
7102 {
7103 rtx dest = SET_DEST (pat);
7104
7105 if (REG_P (dest))
7106 {
7107 int xregno = REGNO (dest);
7108 int end_xregno = END_REGNO (dest);
7109
7110 if (xregno < regno + nregs
7111 && end_xregno > regno)
7112 return 0;
7113 else if (xregno < valueno + valuenregs
7114 && end_xregno > valueno)
7115 return 0;
7116 else if (goal_mem_addr_varies
7117 && reg_overlap_mentioned_for_reload_p (dest,
7118 goal))
7119 return 0;
7120 }
7121
7122 else if (goal_mem && MEM_P (dest)
7123 && ! push_operand (dest, GET_MODE (dest)))
7124 return 0;
7125 else if (need_stable_sp
7126 && push_operand (dest, GET_MODE (dest)))
7127 return 0;
7128 }
7129 }
7130 }
7131
7132 #if AUTO_INC_DEC
7133 /* If this insn auto-increments or auto-decrements
7134 either regno or valueno, return 0 now.
7135 If GOAL is a memory ref and its address is not constant,
7136 and this insn P increments a register used in GOAL, return 0. */
7137 {
7138 rtx link;
7139
7140 for (link = REG_NOTES (p); link; link = XEXP (link, 1))
7141 if (REG_NOTE_KIND (link) == REG_INC
7142 && REG_P (XEXP (link, 0)))
7143 {
7144 int incno = REGNO (XEXP (link, 0));
7145 if (incno < regno + nregs && incno >= regno)
7146 return 0;
7147 if (incno < valueno + valuenregs && incno >= valueno)
7148 return 0;
7149 if (goal_mem_addr_varies
7150 && reg_overlap_mentioned_for_reload_p (XEXP (link, 0),
7151 goal))
7152 return 0;
7153 }
7154 }
7155 #endif
7156 }
7157 }
7158 }
7159
7160 /* Find a place where INCED appears in an increment or decrement operator
7161 within X, and return the amount INCED is incremented or decremented by.
7162 The value is always positive. */
7163
7164 static poly_int64
find_inc_amount(rtx x,rtx inced)7165 find_inc_amount (rtx x, rtx inced)
7166 {
7167 enum rtx_code code = GET_CODE (x);
7168 const char *fmt;
7169 int i;
7170
7171 if (code == MEM)
7172 {
7173 rtx addr = XEXP (x, 0);
7174 if ((GET_CODE (addr) == PRE_DEC
7175 || GET_CODE (addr) == POST_DEC
7176 || GET_CODE (addr) == PRE_INC
7177 || GET_CODE (addr) == POST_INC)
7178 && XEXP (addr, 0) == inced)
7179 return GET_MODE_SIZE (GET_MODE (x));
7180 else if ((GET_CODE (addr) == PRE_MODIFY
7181 || GET_CODE (addr) == POST_MODIFY)
7182 && GET_CODE (XEXP (addr, 1)) == PLUS
7183 && XEXP (addr, 0) == XEXP (XEXP (addr, 1), 0)
7184 && XEXP (addr, 0) == inced
7185 && CONST_INT_P (XEXP (XEXP (addr, 1), 1)))
7186 {
7187 i = INTVAL (XEXP (XEXP (addr, 1), 1));
7188 return i < 0 ? -i : i;
7189 }
7190 }
7191
7192 fmt = GET_RTX_FORMAT (code);
7193 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7194 {
7195 if (fmt[i] == 'e')
7196 {
7197 poly_int64 tem = find_inc_amount (XEXP (x, i), inced);
7198 if (maybe_ne (tem, 0))
7199 return tem;
7200 }
7201 if (fmt[i] == 'E')
7202 {
7203 int j;
7204 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7205 {
7206 poly_int64 tem = find_inc_amount (XVECEXP (x, i, j), inced);
7207 if (maybe_ne (tem, 0))
7208 return tem;
7209 }
7210 }
7211 }
7212
7213 return 0;
7214 }
7215
7216 /* Return 1 if registers from REGNO to ENDREGNO are the subjects of a
7217 REG_INC note in insn INSN. REGNO must refer to a hard register. */
7218
7219 static int
reg_inc_found_and_valid_p(unsigned int regno,unsigned int endregno,rtx insn)7220 reg_inc_found_and_valid_p (unsigned int regno, unsigned int endregno,
7221 rtx insn)
7222 {
7223 rtx link;
7224
7225 if (!AUTO_INC_DEC)
7226 return 0;
7227
7228 gcc_assert (insn);
7229
7230 if (! INSN_P (insn))
7231 return 0;
7232
7233 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
7234 if (REG_NOTE_KIND (link) == REG_INC)
7235 {
7236 unsigned int test = (int) REGNO (XEXP (link, 0));
7237 if (test >= regno && test < endregno)
7238 return 1;
7239 }
7240 return 0;
7241 }
7242
7243 /* Return 1 if register REGNO is the subject of a clobber in insn INSN.
7244 If SETS is 1, also consider SETs. If SETS is 2, enable checking
7245 REG_INC. REGNO must refer to a hard register. */
7246
7247 int
regno_clobbered_p(unsigned int regno,rtx_insn * insn,machine_mode mode,int sets)7248 regno_clobbered_p (unsigned int regno, rtx_insn *insn, machine_mode mode,
7249 int sets)
7250 {
7251 /* regno must be a hard register. */
7252 gcc_assert (regno < FIRST_PSEUDO_REGISTER);
7253
7254 unsigned int endregno = end_hard_regno (mode, regno);
7255
7256 if ((GET_CODE (PATTERN (insn)) == CLOBBER
7257 || (sets == 1 && GET_CODE (PATTERN (insn)) == SET))
7258 && REG_P (XEXP (PATTERN (insn), 0)))
7259 {
7260 unsigned int test = REGNO (XEXP (PATTERN (insn), 0));
7261
7262 return test >= regno && test < endregno;
7263 }
7264
7265 if (sets == 2 && reg_inc_found_and_valid_p (regno, endregno, insn))
7266 return 1;
7267
7268 if (GET_CODE (PATTERN (insn)) == PARALLEL)
7269 {
7270 int i = XVECLEN (PATTERN (insn), 0) - 1;
7271
7272 for (; i >= 0; i--)
7273 {
7274 rtx elt = XVECEXP (PATTERN (insn), 0, i);
7275 if ((GET_CODE (elt) == CLOBBER
7276 || (sets == 1 && GET_CODE (elt) == SET))
7277 && REG_P (XEXP (elt, 0)))
7278 {
7279 unsigned int test = REGNO (XEXP (elt, 0));
7280
7281 if (test >= regno && test < endregno)
7282 return 1;
7283 }
7284 if (sets == 2
7285 && reg_inc_found_and_valid_p (regno, endregno, elt))
7286 return 1;
7287 }
7288 }
7289
7290 return 0;
7291 }
7292
7293 /* Find the low part, with mode MODE, of a hard regno RELOADREG. */
7294 rtx
reload_adjust_reg_for_mode(rtx reloadreg,machine_mode mode)7295 reload_adjust_reg_for_mode (rtx reloadreg, machine_mode mode)
7296 {
7297 int regno;
7298
7299 if (GET_MODE (reloadreg) == mode)
7300 return reloadreg;
7301
7302 regno = REGNO (reloadreg);
7303
7304 if (REG_WORDS_BIG_ENDIAN)
7305 regno += ((int) REG_NREGS (reloadreg)
7306 - (int) hard_regno_nregs (regno, mode));
7307
7308 return gen_rtx_REG (mode, regno);
7309 }
7310
7311 static const char *const reload_when_needed_name[] =
7312 {
7313 "RELOAD_FOR_INPUT",
7314 "RELOAD_FOR_OUTPUT",
7315 "RELOAD_FOR_INSN",
7316 "RELOAD_FOR_INPUT_ADDRESS",
7317 "RELOAD_FOR_INPADDR_ADDRESS",
7318 "RELOAD_FOR_OUTPUT_ADDRESS",
7319 "RELOAD_FOR_OUTADDR_ADDRESS",
7320 "RELOAD_FOR_OPERAND_ADDRESS",
7321 "RELOAD_FOR_OPADDR_ADDR",
7322 "RELOAD_OTHER",
7323 "RELOAD_FOR_OTHER_ADDRESS"
7324 };
7325
7326 /* These functions are used to print the variables set by 'find_reloads' */
7327
7328 DEBUG_FUNCTION void
debug_reload_to_stream(FILE * f)7329 debug_reload_to_stream (FILE *f)
7330 {
7331 int r;
7332 const char *prefix;
7333
7334 if (! f)
7335 f = stderr;
7336 for (r = 0; r < n_reloads; r++)
7337 {
7338 fprintf (f, "Reload %d: ", r);
7339
7340 if (rld[r].in != 0)
7341 {
7342 fprintf (f, "reload_in (%s) = ",
7343 GET_MODE_NAME (rld[r].inmode));
7344 print_inline_rtx (f, rld[r].in, 24);
7345 fprintf (f, "\n\t");
7346 }
7347
7348 if (rld[r].out != 0)
7349 {
7350 fprintf (f, "reload_out (%s) = ",
7351 GET_MODE_NAME (rld[r].outmode));
7352 print_inline_rtx (f, rld[r].out, 24);
7353 fprintf (f, "\n\t");
7354 }
7355
7356 fprintf (f, "%s, ", reg_class_names[(int) rld[r].rclass]);
7357
7358 fprintf (f, "%s (opnum = %d)",
7359 reload_when_needed_name[(int) rld[r].when_needed],
7360 rld[r].opnum);
7361
7362 if (rld[r].optional)
7363 fprintf (f, ", optional");
7364
7365 if (rld[r].nongroup)
7366 fprintf (f, ", nongroup");
7367
7368 if (maybe_ne (rld[r].inc, 0))
7369 {
7370 fprintf (f, ", inc by ");
7371 print_dec (rld[r].inc, f, SIGNED);
7372 }
7373
7374 if (rld[r].nocombine)
7375 fprintf (f, ", can't combine");
7376
7377 if (rld[r].secondary_p)
7378 fprintf (f, ", secondary_reload_p");
7379
7380 if (rld[r].in_reg != 0)
7381 {
7382 fprintf (f, "\n\treload_in_reg: ");
7383 print_inline_rtx (f, rld[r].in_reg, 24);
7384 }
7385
7386 if (rld[r].out_reg != 0)
7387 {
7388 fprintf (f, "\n\treload_out_reg: ");
7389 print_inline_rtx (f, rld[r].out_reg, 24);
7390 }
7391
7392 if (rld[r].reg_rtx != 0)
7393 {
7394 fprintf (f, "\n\treload_reg_rtx: ");
7395 print_inline_rtx (f, rld[r].reg_rtx, 24);
7396 }
7397
7398 prefix = "\n\t";
7399 if (rld[r].secondary_in_reload != -1)
7400 {
7401 fprintf (f, "%ssecondary_in_reload = %d",
7402 prefix, rld[r].secondary_in_reload);
7403 prefix = ", ";
7404 }
7405
7406 if (rld[r].secondary_out_reload != -1)
7407 fprintf (f, "%ssecondary_out_reload = %d\n",
7408 prefix, rld[r].secondary_out_reload);
7409
7410 prefix = "\n\t";
7411 if (rld[r].secondary_in_icode != CODE_FOR_nothing)
7412 {
7413 fprintf (f, "%ssecondary_in_icode = %s", prefix,
7414 insn_data[rld[r].secondary_in_icode].name);
7415 prefix = ", ";
7416 }
7417
7418 if (rld[r].secondary_out_icode != CODE_FOR_nothing)
7419 fprintf (f, "%ssecondary_out_icode = %s", prefix,
7420 insn_data[rld[r].secondary_out_icode].name);
7421
7422 fprintf (f, "\n");
7423 }
7424 }
7425
7426 DEBUG_FUNCTION void
debug_reload(void)7427 debug_reload (void)
7428 {
7429 debug_reload_to_stream (stderr);
7430 }
7431