1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <linux/hdmi.h>
24 #include <drm/drmP.h>
25 #include "radeon.h"
26 #include "radeon_audio.h"
27 #include "sid.h"
28
29 #define DCE8_DCCG_AUDIO_DTO1_PHASE 0x05b8
30 #define DCE8_DCCG_AUDIO_DTO1_MODULE 0x05bc
31
32 u32 dce6_endpoint_rreg(struct radeon_device *rdev,
33 u32 block_offset, u32 reg);
34 void dce6_endpoint_wreg(struct radeon_device *rdev,
35 u32 block_offset, u32 reg, u32 v);
36 void dce6_afmt_select_pin(struct drm_encoder *encoder);
37 void dce6_afmt_write_latency_fields(struct drm_encoder *encoder,
38 struct drm_connector *connector, struct drm_display_mode *mode);
39 void dce6_afmt_write_speaker_allocation(struct drm_encoder *encoder);
40 void dce6_afmt_write_sad_regs(struct drm_encoder *encoder,
41 struct cea_sad *sads, int sad_count);
42 void dce6_audio_fini(struct radeon_device *rdev);
43
dce6_endpoint_rreg(struct radeon_device * rdev,u32 block_offset,u32 reg)44 u32 dce6_endpoint_rreg(struct radeon_device *rdev,
45 u32 block_offset, u32 reg)
46 {
47 u32 r;
48
49 lockmgr(&rdev->end_idx_lock, LK_EXCLUSIVE);
50 WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
51 r = RREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset);
52 lockmgr(&rdev->end_idx_lock, LK_RELEASE);
53
54 return r;
55 }
56
dce6_endpoint_wreg(struct radeon_device * rdev,u32 block_offset,u32 reg,u32 v)57 void dce6_endpoint_wreg(struct radeon_device *rdev,
58 u32 block_offset, u32 reg, u32 v)
59 {
60 lockmgr(&rdev->end_idx_lock, LK_EXCLUSIVE);
61 if (ASIC_IS_DCE8(rdev))
62 WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
63 else
64 WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset,
65 AZ_ENDPOINT_REG_WRITE_EN | AZ_ENDPOINT_REG_INDEX(reg));
66 WREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset, v);
67 lockmgr(&rdev->end_idx_lock, LK_RELEASE);
68 }
69
dce6_afmt_get_connected_pins(struct radeon_device * rdev)70 static void dce6_afmt_get_connected_pins(struct radeon_device *rdev)
71 {
72 int i;
73 u32 offset, tmp;
74
75 for (i = 0; i < rdev->audio.num_pins; i++) {
76 offset = rdev->audio.pin[i].offset;
77 tmp = RREG32_ENDPOINT(offset,
78 AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
79 if (((tmp & PORT_CONNECTIVITY_MASK) >> PORT_CONNECTIVITY_SHIFT) == 1)
80 rdev->audio.pin[i].connected = false;
81 else
82 rdev->audio.pin[i].connected = true;
83 }
84 }
85
dce6_audio_get_pin(struct radeon_device * rdev)86 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev)
87 {
88 struct drm_encoder *encoder;
89 struct radeon_encoder *radeon_encoder;
90 struct radeon_encoder_atom_dig *dig;
91 struct r600_audio_pin *pin = NULL;
92 int i, pin_count;
93
94 dce6_afmt_get_connected_pins(rdev);
95
96 for (i = 0; i < rdev->audio.num_pins; i++) {
97 if (rdev->audio.pin[i].connected) {
98 pin = &rdev->audio.pin[i];
99 pin_count = 0;
100
101 list_for_each_entry(encoder, &rdev->ddev->mode_config.encoder_list, head) {
102 if (radeon_encoder_is_digital(encoder)) {
103 radeon_encoder = to_radeon_encoder(encoder);
104 dig = radeon_encoder->enc_priv;
105 if (dig->pin == pin)
106 pin_count++;
107 }
108 }
109
110 if (pin_count == 0)
111 return pin;
112 }
113 }
114 if (!pin)
115 DRM_ERROR("No connected audio pins found!\n");
116 return pin;
117 }
118
dce6_afmt_select_pin(struct drm_encoder * encoder)119 void dce6_afmt_select_pin(struct drm_encoder *encoder)
120 {
121 struct radeon_device *rdev = encoder->dev->dev_private;
122 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
123 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
124
125 if (!dig || !dig->afmt || !dig->pin)
126 return;
127
128 WREG32(AFMT_AUDIO_SRC_CONTROL + dig->afmt->offset,
129 AFMT_AUDIO_SRC_SELECT(dig->pin->id));
130 }
131
dce6_afmt_write_latency_fields(struct drm_encoder * encoder,struct drm_connector * connector,struct drm_display_mode * mode)132 void dce6_afmt_write_latency_fields(struct drm_encoder *encoder,
133 struct drm_connector *connector,
134 struct drm_display_mode *mode)
135 {
136 struct radeon_device *rdev = encoder->dev->dev_private;
137 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
138 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
139 u32 tmp = 0;
140
141 if (!dig || !dig->afmt || !dig->pin)
142 return;
143
144 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
145 if (connector->latency_present[1])
146 tmp = VIDEO_LIPSYNC(connector->video_latency[1]) |
147 AUDIO_LIPSYNC(connector->audio_latency[1]);
148 else
149 tmp = VIDEO_LIPSYNC(0) | AUDIO_LIPSYNC(0);
150 } else {
151 if (connector->latency_present[0])
152 tmp = VIDEO_LIPSYNC(connector->video_latency[0]) |
153 AUDIO_LIPSYNC(connector->audio_latency[0]);
154 else
155 tmp = VIDEO_LIPSYNC(0) | AUDIO_LIPSYNC(0);
156 }
157 WREG32_ENDPOINT(dig->pin->offset,
158 AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
159 }
160
161 void dce6_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder,
162 u8 *sadb, int sad_count);
dce6_afmt_hdmi_write_speaker_allocation(struct drm_encoder * encoder,u8 * sadb,int sad_count)163 void dce6_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder,
164 u8 *sadb, int sad_count)
165 {
166 struct radeon_device *rdev = encoder->dev->dev_private;
167 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
168 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
169 u32 tmp;
170
171 if (!dig || !dig->afmt || !dig->pin)
172 return;
173
174 /* program the speaker allocation */
175 tmp = RREG32_ENDPOINT(dig->pin->offset,
176 AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
177 tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);
178 /* set HDMI mode */
179 tmp |= HDMI_CONNECTION;
180 if (sad_count)
181 tmp |= SPEAKER_ALLOCATION(sadb[0]);
182 else
183 tmp |= SPEAKER_ALLOCATION(5); /* stereo */
184 WREG32_ENDPOINT(dig->pin->offset,
185 AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
186 }
187
188 void dce6_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder,
189 u8 *sadb, int sad_count);
dce6_afmt_dp_write_speaker_allocation(struct drm_encoder * encoder,u8 * sadb,int sad_count)190 void dce6_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder,
191 u8 *sadb, int sad_count)
192 {
193 struct radeon_device *rdev = encoder->dev->dev_private;
194 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
195 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
196 u32 tmp;
197
198 if (!dig || !dig->afmt || !dig->pin)
199 return;
200
201 /* program the speaker allocation */
202 tmp = RREG32_ENDPOINT(dig->pin->offset,
203 AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
204 tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK);
205 /* set DP mode */
206 tmp |= DP_CONNECTION;
207 if (sad_count)
208 tmp |= SPEAKER_ALLOCATION(sadb[0]);
209 else
210 tmp |= SPEAKER_ALLOCATION(5); /* stereo */
211 WREG32_ENDPOINT(dig->pin->offset,
212 AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
213 }
214
dce6_afmt_write_sad_regs(struct drm_encoder * encoder,struct cea_sad * sads,int sad_count)215 void dce6_afmt_write_sad_regs(struct drm_encoder *encoder,
216 struct cea_sad *sads, int sad_count)
217 {
218 int i;
219 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
220 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
221 struct radeon_device *rdev = encoder->dev->dev_private;
222 static const u16 eld_reg_to_type[][2] = {
223 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
224 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
225 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
226 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
227 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
228 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
229 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
230 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
231 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
232 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
233 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
234 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
235 };
236
237 if (!dig || !dig->afmt || !dig->pin)
238 return;
239
240 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
241 u32 value = 0;
242 u8 stereo_freqs = 0;
243 int max_channels = -1;
244 int j;
245
246 for (j = 0; j < sad_count; j++) {
247 struct cea_sad *sad = &sads[j];
248
249 if (sad->format == eld_reg_to_type[i][1]) {
250 if (sad->channels > max_channels) {
251 value = MAX_CHANNELS(sad->channels) |
252 DESCRIPTOR_BYTE_2(sad->byte2) |
253 SUPPORTED_FREQUENCIES(sad->freq);
254 max_channels = sad->channels;
255 }
256
257 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
258 stereo_freqs |= sad->freq;
259 else
260 break;
261 }
262 }
263
264 value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs);
265
266 WREG32_ENDPOINT(dig->pin->offset, eld_reg_to_type[i][0], value);
267 }
268 }
269
dce6_audio_enable(struct radeon_device * rdev,struct r600_audio_pin * pin,u8 enable_mask)270 void dce6_audio_enable(struct radeon_device *rdev,
271 struct r600_audio_pin *pin,
272 u8 enable_mask)
273 {
274 if (!pin)
275 return;
276
277 WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
278 enable_mask ? AUDIO_ENABLED : 0);
279 }
280
281 void dce6_hdmi_audio_set_dto(struct radeon_device *rdev,
282 struct radeon_crtc *crtc, unsigned int clock);
dce6_hdmi_audio_set_dto(struct radeon_device * rdev,struct radeon_crtc * crtc,unsigned int clock)283 void dce6_hdmi_audio_set_dto(struct radeon_device *rdev,
284 struct radeon_crtc *crtc, unsigned int clock)
285 {
286 /* Two dtos; generally use dto0 for HDMI */
287 u32 value = 0;
288
289 if (crtc)
290 value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);
291
292 WREG32(DCCG_AUDIO_DTO_SOURCE, value);
293
294 /* Express [24MHz / target pixel clock] as an exact rational
295 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
296 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
297 */
298 WREG32(DCCG_AUDIO_DTO0_PHASE, 24000);
299 WREG32(DCCG_AUDIO_DTO0_MODULE, clock);
300 }
301
302 void dce6_dp_audio_set_dto(struct radeon_device *rdev,
303 struct radeon_crtc *crtc, unsigned int clock);
dce6_dp_audio_set_dto(struct radeon_device * rdev,struct radeon_crtc * crtc,unsigned int clock)304 void dce6_dp_audio_set_dto(struct radeon_device *rdev,
305 struct radeon_crtc *crtc, unsigned int clock)
306 {
307 /* Two dtos; generally use dto1 for DP */
308 u32 value = 0;
309 value |= DCCG_AUDIO_DTO_SEL;
310
311 if (crtc)
312 value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);
313
314 WREG32(DCCG_AUDIO_DTO_SOURCE, value);
315
316 /* Express [24MHz / target pixel clock] as an exact rational
317 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
318 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
319 */
320 if (ASIC_IS_DCE8(rdev)) {
321 unsigned int div = (RREG32(DENTIST_DISPCLK_CNTL) &
322 DENTIST_DPREFCLK_WDIVIDER_MASK) >>
323 DENTIST_DPREFCLK_WDIVIDER_SHIFT;
324 div = radeon_audio_decode_dfs_div(div);
325
326 if (div)
327 clock = clock * 100 / div;
328
329 WREG32(DCE8_DCCG_AUDIO_DTO1_PHASE, 24000);
330 WREG32(DCE8_DCCG_AUDIO_DTO1_MODULE, clock);
331 } else {
332 WREG32(DCCG_AUDIO_DTO1_PHASE, 24000);
333 WREG32(DCCG_AUDIO_DTO1_MODULE, clock);
334 }
335 }
336