1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27 #include "basics/conversion.h"
28
29 #include "dce_opp.h"
30
31 #include "reg_helper.h"
32
33 #define REG(reg)\
34 (opp110->regs->reg)
35
36 #undef FN
37 #define FN(reg_name, field_name) \
38 opp110->opp_shift->field_name, opp110->opp_mask->field_name
39
40 #define CTX \
41 opp110->base.ctx
42
43 enum {
44 MAX_PWL_ENTRY = 128,
45 MAX_REGIONS_NUMBER = 16
46 };
47
48 enum {
49 MAX_LUT_ENTRY = 256,
50 MAX_NUMBER_OF_ENTRIES = 256
51 };
52
53
54 enum {
55 OUTPUT_CSC_MATRIX_SIZE = 12
56 };
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77
78
79 /*
80 *****************************************************************************
81 * Function: regamma_config_regions_and_segments
82 *
83 * build regamma curve by using predefined hw points
84 * uses interface parameters ,like EDID coeff.
85 *
86 * @param : parameters interface parameters
87 * @return void
88 *
89 * @note
90 *
91 * @see
92 *
93 *****************************************************************************
94 */
95
96
97
98 /**
99 * set_truncation
100 * 1) set truncation depth: 0 for 18 bpp or 1 for 24 bpp
101 * 2) enable truncation
102 * 3) HW remove 12bit FMT support for DCE11 power saving reason.
103 */
set_truncation(struct dce110_opp * opp110,const struct bit_depth_reduction_params * params)104 static void set_truncation(
105 struct dce110_opp *opp110,
106 const struct bit_depth_reduction_params *params)
107 {
108 /*Disable truncation*/
109 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
110 FMT_TRUNCATE_EN, 0,
111 FMT_TRUNCATE_DEPTH, 0,
112 FMT_TRUNCATE_MODE, 0);
113
114
115 if (params->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
116 /* 8bpc trunc on YCbCr422*/
117 if (params->flags.TRUNCATE_DEPTH == 1)
118 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
119 FMT_TRUNCATE_EN, 1,
120 FMT_TRUNCATE_DEPTH, 1,
121 FMT_TRUNCATE_MODE, 0);
122 else if (params->flags.TRUNCATE_DEPTH == 2)
123 /* 10bpc trunc on YCbCr422*/
124 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
125 FMT_TRUNCATE_EN, 1,
126 FMT_TRUNCATE_DEPTH, 2,
127 FMT_TRUNCATE_MODE, 0);
128 return;
129 }
130 /* on other format-to do */
131 if (params->flags.TRUNCATE_ENABLED == 0)
132 return;
133 /*Set truncation depth and Enable truncation*/
134 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
135 FMT_TRUNCATE_EN, 1,
136 FMT_TRUNCATE_DEPTH,
137 params->flags.TRUNCATE_DEPTH,
138 FMT_TRUNCATE_MODE,
139 params->flags.TRUNCATE_MODE);
140 }
141
142
143 /**
144 * set_spatial_dither
145 * 1) set spatial dithering mode: pattern of seed
146 * 2) set spatial dithering depth: 0 for 18bpp or 1 for 24bpp
147 * 3) set random seed
148 * 4) set random mode
149 * lfsr is reset every frame or not reset
150 * RGB dithering method
151 * 0: RGB data are all dithered with x^28+x^3+1
152 * 1: R data is dithered with x^28+x^3+1
153 * G data is dithered with x^28+X^9+1
154 * B data is dithered with x^28+x^13+1
155 * enable high pass filter or not
156 * 5) enable spatical dithering
157 */
set_spatial_dither(struct dce110_opp * opp110,const struct bit_depth_reduction_params * params)158 static void set_spatial_dither(
159 struct dce110_opp *opp110,
160 const struct bit_depth_reduction_params *params)
161 {
162 /*Disable spatial (random) dithering*/
163 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
164 FMT_SPATIAL_DITHER_EN, 0,
165 FMT_SPATIAL_DITHER_DEPTH, 0,
166 FMT_SPATIAL_DITHER_MODE, 0);
167
168 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
169 FMT_HIGHPASS_RANDOM_ENABLE, 0,
170 FMT_FRAME_RANDOM_ENABLE, 0,
171 FMT_RGB_RANDOM_ENABLE, 0);
172
173 REG_UPDATE(FMT_BIT_DEPTH_CONTROL,
174 FMT_TEMPORAL_DITHER_EN, 0);
175
176 /* no 10bpc on DCE11*/
177 if (params->flags.SPATIAL_DITHER_ENABLED == 0 ||
178 params->flags.SPATIAL_DITHER_DEPTH == 2)
179 return;
180
181 /* only use FRAME_COUNTER_MAX if frameRandom == 1*/
182
183 if (opp110->opp_mask->FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX &&
184 opp110->opp_mask->FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP) {
185 if (params->flags.FRAME_RANDOM == 1) {
186 if (params->flags.SPATIAL_DITHER_DEPTH == 0 ||
187 params->flags.SPATIAL_DITHER_DEPTH == 1) {
188 REG_UPDATE_2(FMT_CONTROL,
189 FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, 15,
190 FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, 2);
191 } else if (params->flags.SPATIAL_DITHER_DEPTH == 2) {
192 REG_UPDATE_2(FMT_CONTROL,
193 FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, 3,
194 FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, 1);
195 } else
196 return;
197 } else {
198 REG_UPDATE_2(FMT_CONTROL,
199 FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, 0,
200 FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, 0);
201 }
202 }
203 /* Set seed for random values for
204 * spatial dithering for R,G,B channels
205 */
206 REG_UPDATE(FMT_DITHER_RAND_R_SEED,
207 FMT_RAND_R_SEED, params->r_seed_value);
208
209 REG_UPDATE(FMT_DITHER_RAND_G_SEED,
210 FMT_RAND_G_SEED, params->g_seed_value);
211
212 REG_UPDATE(FMT_DITHER_RAND_B_SEED,
213 FMT_RAND_B_SEED, params->b_seed_value);
214
215 /* FMT_OFFSET_R_Cr 31:16 0x0 Setting the zero
216 * offset for the R/Cr channel, lower 4LSB
217 * is forced to zeros. Typically set to 0
218 * RGB and 0x80000 YCbCr.
219 */
220 /* FMT_OFFSET_G_Y 31:16 0x0 Setting the zero
221 * offset for the G/Y channel, lower 4LSB is
222 * forced to zeros. Typically set to 0 RGB
223 * and 0x80000 YCbCr.
224 */
225 /* FMT_OFFSET_B_Cb 31:16 0x0 Setting the zero
226 * offset for the B/Cb channel, lower 4LSB is
227 * forced to zeros. Typically set to 0 RGB and
228 * 0x80000 YCbCr.
229 */
230
231 /* Disable High pass filter
232 * Reset only at startup
233 * Set RGB data dithered with x^28+x^3+1
234 */
235 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
236 FMT_HIGHPASS_RANDOM_ENABLE, params->flags.HIGHPASS_RANDOM,
237 FMT_FRAME_RANDOM_ENABLE, params->flags.FRAME_RANDOM,
238 FMT_RGB_RANDOM_ENABLE, params->flags.RGB_RANDOM);
239
240 /* Set spatial dithering bit depth
241 * Set spatial dithering mode
242 * (default is Seed patterrn AAAA...)
243 * Enable spatial dithering
244 */
245 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
246 FMT_SPATIAL_DITHER_DEPTH, params->flags.SPATIAL_DITHER_DEPTH,
247 FMT_SPATIAL_DITHER_MODE, params->flags.SPATIAL_DITHER_MODE,
248 FMT_SPATIAL_DITHER_EN, 1);
249 }
250
251 /**
252 * SetTemporalDither (Frame Modulation)
253 * 1) set temporal dither depth
254 * 2) select pattern: from hard-coded pattern or programmable pattern
255 * 3) select optimized strips for BGR or RGB LCD sub-pixel
256 * 4) set s matrix
257 * 5) set t matrix
258 * 6) set grey level for 0.25, 0.5, 0.75
259 * 7) enable temporal dithering
260 */
261
set_temporal_dither(struct dce110_opp * opp110,const struct bit_depth_reduction_params * params)262 static void set_temporal_dither(
263 struct dce110_opp *opp110,
264 const struct bit_depth_reduction_params *params)
265 {
266 /*Disable temporal (frame modulation) dithering first*/
267 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
268 FMT_TEMPORAL_DITHER_EN, 0,
269 FMT_TEMPORAL_DITHER_RESET, 0,
270 FMT_TEMPORAL_DITHER_OFFSET, 0);
271
272 REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL,
273 FMT_TEMPORAL_DITHER_DEPTH, 0,
274 FMT_TEMPORAL_LEVEL, 0);
275
276 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
277 FMT_25FRC_SEL, 0,
278 FMT_50FRC_SEL, 0,
279 FMT_75FRC_SEL, 0);
280
281 /* no 10bpc dither on DCE11*/
282 if (params->flags.FRAME_MODULATION_ENABLED == 0 ||
283 params->flags.FRAME_MODULATION_DEPTH == 2)
284 return;
285
286 /* Set temporal dithering depth*/
287 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
288 FMT_TEMPORAL_DITHER_DEPTH, params->flags.FRAME_MODULATION_DEPTH,
289 FMT_TEMPORAL_DITHER_RESET, 0,
290 FMT_TEMPORAL_DITHER_OFFSET, 0);
291
292 /*Select legacy pattern based on FRC and Temporal level*/
293 if (REG(FMT_TEMPORAL_DITHER_PATTERN_CONTROL)) {
294 REG_WRITE(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, 0);
295 /*Set s matrix*/
296 REG_WRITE(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, 0);
297 /*Set t matrix*/
298 REG_WRITE(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, 0);
299 }
300
301 /*Select patterns for 0.25, 0.5 and 0.75 grey level*/
302 REG_UPDATE(FMT_BIT_DEPTH_CONTROL,
303 FMT_TEMPORAL_LEVEL, params->flags.TEMPORAL_LEVEL);
304
305 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
306 FMT_25FRC_SEL, params->flags.FRC25,
307 FMT_50FRC_SEL, params->flags.FRC50,
308 FMT_75FRC_SEL, params->flags.FRC75);
309
310 /*Enable bit reduction by temporal (frame modulation) dithering*/
311 REG_UPDATE(FMT_BIT_DEPTH_CONTROL,
312 FMT_TEMPORAL_DITHER_EN, 1);
313 }
314
315 /**
316 * Set Clamping
317 * 1) Set clamping format based on bpc - 0 for 6bpc (No clamping)
318 * 1 for 8 bpc
319 * 2 for 10 bpc
320 * 3 for 12 bpc
321 * 7 for programable
322 * 2) Enable clamp if Limited range requested
323 */
dce110_opp_set_clamping(struct dce110_opp * opp110,const struct clamping_and_pixel_encoding_params * params)324 void dce110_opp_set_clamping(
325 struct dce110_opp *opp110,
326 const struct clamping_and_pixel_encoding_params *params)
327 {
328 REG_SET_2(FMT_CLAMP_CNTL, 0,
329 FMT_CLAMP_DATA_EN, 0,
330 FMT_CLAMP_COLOR_FORMAT, 0);
331
332 switch (params->clamping_level) {
333 case CLAMPING_FULL_RANGE:
334 break;
335 case CLAMPING_LIMITED_RANGE_8BPC:
336 REG_SET_2(FMT_CLAMP_CNTL, 0,
337 FMT_CLAMP_DATA_EN, 1,
338 FMT_CLAMP_COLOR_FORMAT, 1);
339 break;
340 case CLAMPING_LIMITED_RANGE_10BPC:
341 REG_SET_2(FMT_CLAMP_CNTL, 0,
342 FMT_CLAMP_DATA_EN, 1,
343 FMT_CLAMP_COLOR_FORMAT, 2);
344 break;
345 case CLAMPING_LIMITED_RANGE_12BPC:
346 REG_SET_2(FMT_CLAMP_CNTL, 0,
347 FMT_CLAMP_DATA_EN, 1,
348 FMT_CLAMP_COLOR_FORMAT, 3);
349 break;
350 case CLAMPING_LIMITED_RANGE_PROGRAMMABLE:
351 /*Set clamp control*/
352 REG_SET_2(FMT_CLAMP_CNTL, 0,
353 FMT_CLAMP_DATA_EN, 1,
354 FMT_CLAMP_COLOR_FORMAT, 7);
355
356 /*set the defaults*/
357 REG_SET_2(FMT_CLAMP_COMPONENT_R, 0,
358 FMT_CLAMP_LOWER_R, 0x10,
359 FMT_CLAMP_UPPER_R, 0xFEF);
360
361 REG_SET_2(FMT_CLAMP_COMPONENT_G, 0,
362 FMT_CLAMP_LOWER_G, 0x10,
363 FMT_CLAMP_UPPER_G, 0xFEF);
364
365 REG_SET_2(FMT_CLAMP_COMPONENT_B, 0,
366 FMT_CLAMP_LOWER_B, 0x10,
367 FMT_CLAMP_UPPER_B, 0xFEF);
368 break;
369 default:
370 break;
371 }
372 }
373
374 /**
375 * set_pixel_encoding
376 *
377 * Set Pixel Encoding
378 * 0: RGB 4:4:4 or YCbCr 4:4:4 or YOnly
379 * 1: YCbCr 4:2:2
380 */
set_pixel_encoding(struct dce110_opp * opp110,const struct clamping_and_pixel_encoding_params * params)381 static void set_pixel_encoding(
382 struct dce110_opp *opp110,
383 const struct clamping_and_pixel_encoding_params *params)
384 {
385 if (opp110->opp_mask->FMT_CBCR_BIT_REDUCTION_BYPASS)
386 REG_UPDATE_3(FMT_CONTROL,
387 FMT_PIXEL_ENCODING, 0,
388 FMT_SUBSAMPLING_MODE, 0,
389 FMT_CBCR_BIT_REDUCTION_BYPASS, 0);
390 else
391 REG_UPDATE_2(FMT_CONTROL,
392 FMT_PIXEL_ENCODING, 0,
393 FMT_SUBSAMPLING_MODE, 0);
394
395 if (params->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
396 REG_UPDATE_2(FMT_CONTROL,
397 FMT_PIXEL_ENCODING, 1,
398 FMT_SUBSAMPLING_ORDER, 0);
399 }
400 if (params->pixel_encoding == PIXEL_ENCODING_YCBCR420) {
401 REG_UPDATE_3(FMT_CONTROL,
402 FMT_PIXEL_ENCODING, 2,
403 FMT_SUBSAMPLING_MODE, 2,
404 FMT_CBCR_BIT_REDUCTION_BYPASS, 1);
405 }
406
407 }
408
dce110_opp_program_bit_depth_reduction(struct output_pixel_processor * opp,const struct bit_depth_reduction_params * params)409 void dce110_opp_program_bit_depth_reduction(
410 struct output_pixel_processor *opp,
411 const struct bit_depth_reduction_params *params)
412 {
413 struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
414
415 set_truncation(opp110, params);
416 set_spatial_dither(opp110, params);
417 set_temporal_dither(opp110, params);
418 }
419
dce110_opp_program_clamping_and_pixel_encoding(struct output_pixel_processor * opp,const struct clamping_and_pixel_encoding_params * params)420 void dce110_opp_program_clamping_and_pixel_encoding(
421 struct output_pixel_processor *opp,
422 const struct clamping_and_pixel_encoding_params *params)
423 {
424 struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
425
426 dce110_opp_set_clamping(opp110, params);
427 set_pixel_encoding(opp110, params);
428 }
429
program_formatter_420_memory(struct output_pixel_processor * opp)430 static void program_formatter_420_memory(struct output_pixel_processor *opp)
431 {
432 struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
433 uint32_t fmt_mem_cntl_value;
434
435 /* Program source select*/
436 /* Use HW default source select for FMT_MEMORYx_CONTROL */
437 /* Use that value for FMT_SRC_SELECT as well*/
438 REG_GET(CONTROL,
439 FMT420_MEM0_SOURCE_SEL, &fmt_mem_cntl_value);
440
441 REG_UPDATE(FMT_CONTROL,
442 FMT_SRC_SELECT, fmt_mem_cntl_value);
443
444 /* Turn on the memory */
445 REG_UPDATE(CONTROL,
446 FMT420_MEM0_PWR_FORCE, 0);
447 }
448
dce110_opp_set_dyn_expansion(struct output_pixel_processor * opp,enum dc_color_space color_sp,enum dc_color_depth color_dpth,enum signal_type signal)449 void dce110_opp_set_dyn_expansion(
450 struct output_pixel_processor *opp,
451 enum dc_color_space color_sp,
452 enum dc_color_depth color_dpth,
453 enum signal_type signal)
454 {
455 struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
456
457 REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL,
458 FMT_DYNAMIC_EXP_EN, 0,
459 FMT_DYNAMIC_EXP_MODE, 0);
460
461 /*00 - 10-bit -> 12-bit dynamic expansion*/
462 /*01 - 8-bit -> 12-bit dynamic expansion*/
463 if (signal == SIGNAL_TYPE_HDMI_TYPE_A ||
464 signal == SIGNAL_TYPE_DISPLAY_PORT ||
465 signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
466 switch (color_dpth) {
467 case COLOR_DEPTH_888:
468 REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL,
469 FMT_DYNAMIC_EXP_EN, 1,
470 FMT_DYNAMIC_EXP_MODE, 1);
471 break;
472 case COLOR_DEPTH_101010:
473 REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL,
474 FMT_DYNAMIC_EXP_EN, 1,
475 FMT_DYNAMIC_EXP_MODE, 0);
476 break;
477 case COLOR_DEPTH_121212:
478 REG_UPDATE_2(
479 FMT_DYNAMIC_EXP_CNTL,
480 FMT_DYNAMIC_EXP_EN, 1,/*otherwise last two bits are zero*/
481 FMT_DYNAMIC_EXP_MODE, 0);
482 break;
483 default:
484 break;
485 }
486 }
487 }
488
program_formatter_reset_dig_resync_fifo(struct output_pixel_processor * opp)489 static void program_formatter_reset_dig_resync_fifo(struct output_pixel_processor *opp)
490 {
491 struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
492
493 /* clear previous phase lock status*/
494 REG_UPDATE(FMT_CONTROL,
495 FMT_420_PIXEL_PHASE_LOCKED_CLEAR, 1);
496
497 /* poll until FMT_420_PIXEL_PHASE_LOCKED become 1*/
498 REG_WAIT(FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED, 1, 10, 10);
499
500 }
501
dce110_opp_program_fmt(struct output_pixel_processor * opp,struct bit_depth_reduction_params * fmt_bit_depth,struct clamping_and_pixel_encoding_params * clamping)502 void dce110_opp_program_fmt(
503 struct output_pixel_processor *opp,
504 struct bit_depth_reduction_params *fmt_bit_depth,
505 struct clamping_and_pixel_encoding_params *clamping)
506 {
507 /* dithering is affected by <CrtcSourceSelect>, hence should be
508 * programmed afterwards */
509
510 if (clamping->pixel_encoding == PIXEL_ENCODING_YCBCR420)
511 program_formatter_420_memory(opp);
512
513 dce110_opp_program_bit_depth_reduction(
514 opp,
515 fmt_bit_depth);
516
517 dce110_opp_program_clamping_and_pixel_encoding(
518 opp,
519 clamping);
520
521 if (clamping->pixel_encoding == PIXEL_ENCODING_YCBCR420)
522 program_formatter_reset_dig_resync_fifo(opp);
523
524 return;
525 }
526
527
528
529
530
531 /*****************************************/
532 /* Constructor, Destructor */
533 /*****************************************/
534
535 static const struct opp_funcs funcs = {
536 .opp_set_dyn_expansion = dce110_opp_set_dyn_expansion,
537 .opp_destroy = dce110_opp_destroy,
538 .opp_program_fmt = dce110_opp_program_fmt,
539 .opp_program_bit_depth_reduction = dce110_opp_program_bit_depth_reduction
540 };
541
dce110_opp_construct(struct dce110_opp * opp110,struct dc_context * ctx,uint32_t inst,const struct dce_opp_registers * regs,const struct dce_opp_shift * opp_shift,const struct dce_opp_mask * opp_mask)542 void dce110_opp_construct(struct dce110_opp *opp110,
543 struct dc_context *ctx,
544 uint32_t inst,
545 const struct dce_opp_registers *regs,
546 const struct dce_opp_shift *opp_shift,
547 const struct dce_opp_mask *opp_mask)
548 {
549 opp110->base.funcs = &funcs;
550
551 opp110->base.ctx = ctx;
552
553 opp110->base.inst = inst;
554
555 opp110->regs = regs;
556 opp110->opp_shift = opp_shift;
557 opp110->opp_mask = opp_mask;
558 }
559
dce110_opp_destroy(struct output_pixel_processor ** opp)560 void dce110_opp_destroy(struct output_pixel_processor **opp)
561 {
562 if (*opp)
563 kfree(FROM_DCE11_OPP(*opp));
564 *opp = NULL;
565 }
566
567