1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "reg_helper.h"
27
28 #include "core_types.h"
29 #include "link_encoder.h"
30 #include "dce_link_encoder.h"
31 #include "stream_encoder.h"
32 #include "i2caux_interface.h"
33 #include "dc_bios_types.h"
34
35 #include "gpio_service_interface.h"
36
37 #include "dce/dce_11_0_d.h"
38 #include "dce/dce_11_0_sh_mask.h"
39 #include "dce/dce_11_0_enum.h"
40
41 #ifndef DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE__SHIFT
42 #define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE__SHIFT 0xa
43 #endif
44
45 #ifndef DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK
46 #define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK 0x00000400L
47 #endif
48
49 #ifndef HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK
50 #define HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L
51 #endif
52
53 #ifndef HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT
54 #define HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c
55 #endif
56
57 #define CTX \
58 enc110->base.ctx
59 #define DC_LOGGER \
60 enc110->base.ctx->logger
61
62 #define REG(reg)\
63 (enc110->link_regs->reg)
64
65 #define AUX_REG(reg)\
66 (enc110->aux_regs->reg)
67
68 #define HPD_REG(reg)\
69 (enc110->hpd_regs->reg)
70
71 #define DEFAULT_AUX_MAX_DATA_SIZE 16
72 #define AUX_MAX_DEFER_WRITE_RETRY 20
73 /*
74 * @brief
75 * Trigger Source Select
76 * ASIC-dependent, actual values for register programming
77 */
78 #define DCE110_DIG_FE_SOURCE_SELECT_INVALID 0x0
79 #define DCE110_DIG_FE_SOURCE_SELECT_DIGA 0x1
80 #define DCE110_DIG_FE_SOURCE_SELECT_DIGB 0x2
81 #define DCE110_DIG_FE_SOURCE_SELECT_DIGC 0x4
82 #define DCE110_DIG_FE_SOURCE_SELECT_DIGD 0x08
83 #define DCE110_DIG_FE_SOURCE_SELECT_DIGE 0x10
84 #define DCE110_DIG_FE_SOURCE_SELECT_DIGF 0x20
85 #define DCE110_DIG_FE_SOURCE_SELECT_DIGG 0x40
86
87 enum {
88 DP_MST_UPDATE_MAX_RETRY = 50
89 };
90
91 #define DIG_REG(reg)\
92 (reg + enc110->offsets.dig)
93
94 #define DP_REG(reg)\
95 (reg + enc110->offsets.dp)
96
97 static const struct link_encoder_funcs dce110_lnk_enc_funcs = {
98 .validate_output_with_stream =
99 dce110_link_encoder_validate_output_with_stream,
100 .hw_init = dce110_link_encoder_hw_init,
101 .setup = dce110_link_encoder_setup,
102 .enable_tmds_output = dce110_link_encoder_enable_tmds_output,
103 .enable_dp_output = dce110_link_encoder_enable_dp_output,
104 .enable_dp_mst_output = dce110_link_encoder_enable_dp_mst_output,
105 .disable_output = dce110_link_encoder_disable_output,
106 .dp_set_lane_settings = dce110_link_encoder_dp_set_lane_settings,
107 .dp_set_phy_pattern = dce110_link_encoder_dp_set_phy_pattern,
108 .update_mst_stream_allocation_table =
109 dce110_link_encoder_update_mst_stream_allocation_table,
110 .psr_program_dp_dphy_fast_training =
111 dce110_psr_program_dp_dphy_fast_training,
112 .psr_program_secondary_packet = dce110_psr_program_secondary_packet,
113 .connect_dig_be_to_fe = dce110_link_encoder_connect_dig_be_to_fe,
114 .enable_hpd = dce110_link_encoder_enable_hpd,
115 .disable_hpd = dce110_link_encoder_disable_hpd,
116 .is_dig_enabled = dce110_is_dig_enabled,
117 .destroy = dce110_link_encoder_destroy
118 };
119
link_transmitter_control(struct dce110_link_encoder * enc110,struct bp_transmitter_control * cntl)120 static enum bp_result link_transmitter_control(
121 struct dce110_link_encoder *enc110,
122 struct bp_transmitter_control *cntl)
123 {
124 enum bp_result result;
125 struct dc_bios *bp = enc110->base.ctx->dc_bios;
126
127 result = bp->funcs->transmitter_control(bp, cntl);
128
129 return result;
130 }
131
enable_phy_bypass_mode(struct dce110_link_encoder * enc110,bool enable)132 static void enable_phy_bypass_mode(
133 struct dce110_link_encoder *enc110,
134 bool enable)
135 {
136 /* This register resides in DP back end block;
137 * transmitter is used for the offset */
138
139 REG_UPDATE(DP_DPHY_CNTL, DPHY_BYPASS, enable);
140
141 }
142
disable_prbs_symbols(struct dce110_link_encoder * enc110,bool disable)143 static void disable_prbs_symbols(
144 struct dce110_link_encoder *enc110,
145 bool disable)
146 {
147 /* This register resides in DP back end block;
148 * transmitter is used for the offset */
149
150 REG_UPDATE_4(DP_DPHY_CNTL,
151 DPHY_ATEST_SEL_LANE0, disable,
152 DPHY_ATEST_SEL_LANE1, disable,
153 DPHY_ATEST_SEL_LANE2, disable,
154 DPHY_ATEST_SEL_LANE3, disable);
155 }
156
disable_prbs_mode(struct dce110_link_encoder * enc110)157 static void disable_prbs_mode(
158 struct dce110_link_encoder *enc110)
159 {
160 REG_UPDATE(DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, 0);
161 }
162
program_pattern_symbols(struct dce110_link_encoder * enc110,uint16_t pattern_symbols[8])163 static void program_pattern_symbols(
164 struct dce110_link_encoder *enc110,
165 uint16_t pattern_symbols[8])
166 {
167 /* This register resides in DP back end block;
168 * transmitter is used for the offset */
169
170 REG_SET_3(DP_DPHY_SYM0, 0,
171 DPHY_SYM1, pattern_symbols[0],
172 DPHY_SYM2, pattern_symbols[1],
173 DPHY_SYM3, pattern_symbols[2]);
174
175 /* This register resides in DP back end block;
176 * transmitter is used for the offset */
177
178 REG_SET_3(DP_DPHY_SYM1, 0,
179 DPHY_SYM4, pattern_symbols[3],
180 DPHY_SYM5, pattern_symbols[4],
181 DPHY_SYM6, pattern_symbols[5]);
182
183 /* This register resides in DP back end block;
184 * transmitter is used for the offset */
185
186 REG_SET_2(DP_DPHY_SYM2, 0,
187 DPHY_SYM7, pattern_symbols[6],
188 DPHY_SYM8, pattern_symbols[7]);
189 }
190
set_dp_phy_pattern_d102(struct dce110_link_encoder * enc110)191 static void set_dp_phy_pattern_d102(
192 struct dce110_link_encoder *enc110)
193 {
194 /* Disable PHY Bypass mode to setup the test pattern */
195 enable_phy_bypass_mode(enc110, false);
196
197 /* For 10-bit PRBS or debug symbols
198 * please use the following sequence: */
199
200 /* Enable debug symbols on the lanes */
201
202 disable_prbs_symbols(enc110, true);
203
204 /* Disable PRBS mode */
205 disable_prbs_mode(enc110);
206
207 /* Program debug symbols to be output */
208 {
209 uint16_t pattern_symbols[8] = {
210 0x2AA, 0x2AA, 0x2AA, 0x2AA,
211 0x2AA, 0x2AA, 0x2AA, 0x2AA
212 };
213
214 program_pattern_symbols(enc110, pattern_symbols);
215 }
216
217 /* Enable phy bypass mode to enable the test pattern */
218
219 enable_phy_bypass_mode(enc110, true);
220 }
221
set_link_training_complete(struct dce110_link_encoder * enc110,bool complete)222 static void set_link_training_complete(
223 struct dce110_link_encoder *enc110,
224 bool complete)
225 {
226 /* This register resides in DP back end block;
227 * transmitter is used for the offset */
228
229 REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, complete);
230
231 }
232
dce110_link_encoder_set_dp_phy_pattern_training_pattern(struct link_encoder * enc,uint32_t index)233 void dce110_link_encoder_set_dp_phy_pattern_training_pattern(
234 struct link_encoder *enc,
235 uint32_t index)
236 {
237 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
238 /* Write Training Pattern */
239
240 REG_WRITE(DP_DPHY_TRAINING_PATTERN_SEL, index);
241
242 /* Set HW Register Training Complete to false */
243
244 set_link_training_complete(enc110, false);
245
246 /* Disable PHY Bypass mode to output Training Pattern */
247
248 enable_phy_bypass_mode(enc110, false);
249
250 /* Disable PRBS mode */
251 disable_prbs_mode(enc110);
252 }
253
setup_panel_mode(struct dce110_link_encoder * enc110,enum dp_panel_mode panel_mode)254 static void setup_panel_mode(
255 struct dce110_link_encoder *enc110,
256 enum dp_panel_mode panel_mode)
257 {
258 uint32_t value;
259 struct dc_context *ctx = enc110->base.ctx;
260
261 /* if psp set panel mode, dal should be program it */
262 if (ctx->dc->caps.psp_setup_panel_mode)
263 return;
264
265 ASSERT(REG(DP_DPHY_INTERNAL_CTRL));
266 value = REG_READ(DP_DPHY_INTERNAL_CTRL);
267
268 switch (panel_mode) {
269 case DP_PANEL_MODE_EDP:
270 value = 0x1;
271 break;
272 case DP_PANEL_MODE_SPECIAL:
273 value = 0x11;
274 break;
275 default:
276 value = 0x0;
277 break;
278 }
279
280 REG_WRITE(DP_DPHY_INTERNAL_CTRL, value);
281 }
282
set_dp_phy_pattern_symbol_error(struct dce110_link_encoder * enc110)283 static void set_dp_phy_pattern_symbol_error(
284 struct dce110_link_encoder *enc110)
285 {
286 /* Disable PHY Bypass mode to setup the test pattern */
287 enable_phy_bypass_mode(enc110, false);
288
289 /* program correct panel mode*/
290 setup_panel_mode(enc110, DP_PANEL_MODE_DEFAULT);
291
292 /* A PRBS23 pattern is used for most DP electrical measurements. */
293
294 /* Enable PRBS symbols on the lanes */
295 disable_prbs_symbols(enc110, false);
296
297 /* For PRBS23 Set bit DPHY_PRBS_SEL=1 and Set bit DPHY_PRBS_EN=1 */
298 REG_UPDATE_2(DP_DPHY_PRBS_CNTL,
299 DPHY_PRBS_SEL, 1,
300 DPHY_PRBS_EN, 1);
301
302 /* Enable phy bypass mode to enable the test pattern */
303 enable_phy_bypass_mode(enc110, true);
304 }
305
set_dp_phy_pattern_prbs7(struct dce110_link_encoder * enc110)306 static void set_dp_phy_pattern_prbs7(
307 struct dce110_link_encoder *enc110)
308 {
309 /* Disable PHY Bypass mode to setup the test pattern */
310 enable_phy_bypass_mode(enc110, false);
311
312 /* A PRBS7 pattern is used for most DP electrical measurements. */
313
314 /* Enable PRBS symbols on the lanes */
315 disable_prbs_symbols(enc110, false);
316
317 /* For PRBS7 Set bit DPHY_PRBS_SEL=0 and Set bit DPHY_PRBS_EN=1 */
318 REG_UPDATE_2(DP_DPHY_PRBS_CNTL,
319 DPHY_PRBS_SEL, 0,
320 DPHY_PRBS_EN, 1);
321
322 /* Enable phy bypass mode to enable the test pattern */
323 enable_phy_bypass_mode(enc110, true);
324 }
325
set_dp_phy_pattern_80bit_custom(struct dce110_link_encoder * enc110,const uint8_t * pattern)326 static void set_dp_phy_pattern_80bit_custom(
327 struct dce110_link_encoder *enc110,
328 const uint8_t *pattern)
329 {
330 /* Disable PHY Bypass mode to setup the test pattern */
331 enable_phy_bypass_mode(enc110, false);
332
333 /* Enable debug symbols on the lanes */
334
335 disable_prbs_symbols(enc110, true);
336
337 /* Enable PHY bypass mode to enable the test pattern */
338 /* TODO is it really needed ? */
339
340 enable_phy_bypass_mode(enc110, true);
341
342 /* Program 80 bit custom pattern */
343 {
344 uint16_t pattern_symbols[8];
345
346 pattern_symbols[0] =
347 ((pattern[1] & 0x03) << 8) | pattern[0];
348 pattern_symbols[1] =
349 ((pattern[2] & 0x0f) << 6) | ((pattern[1] >> 2) & 0x3f);
350 pattern_symbols[2] =
351 ((pattern[3] & 0x3f) << 4) | ((pattern[2] >> 4) & 0x0f);
352 pattern_symbols[3] =
353 (pattern[4] << 2) | ((pattern[3] >> 6) & 0x03);
354 pattern_symbols[4] =
355 ((pattern[6] & 0x03) << 8) | pattern[5];
356 pattern_symbols[5] =
357 ((pattern[7] & 0x0f) << 6) | ((pattern[6] >> 2) & 0x3f);
358 pattern_symbols[6] =
359 ((pattern[8] & 0x3f) << 4) | ((pattern[7] >> 4) & 0x0f);
360 pattern_symbols[7] =
361 (pattern[9] << 2) | ((pattern[8] >> 6) & 0x03);
362
363 program_pattern_symbols(enc110, pattern_symbols);
364 }
365
366 /* Enable phy bypass mode to enable the test pattern */
367
368 enable_phy_bypass_mode(enc110, true);
369 }
370
set_dp_phy_pattern_hbr2_compliance_cp2520_2(struct dce110_link_encoder * enc110,unsigned int cp2520_pattern)371 static void set_dp_phy_pattern_hbr2_compliance_cp2520_2(
372 struct dce110_link_encoder *enc110,
373 unsigned int cp2520_pattern)
374 {
375
376 /* previously there is a register DP_HBR2_EYE_PATTERN
377 * that is enabled to get the pattern.
378 * But it does not work with the latest spec change,
379 * so we are programming the following registers manually.
380 *
381 * The following settings have been confirmed
382 * by Nick Chorney and Sandra Liu */
383
384 /* Disable PHY Bypass mode to setup the test pattern */
385
386 enable_phy_bypass_mode(enc110, false);
387
388 /* Setup DIG encoder in DP SST mode */
389 enc110->base.funcs->setup(&enc110->base, SIGNAL_TYPE_DISPLAY_PORT);
390
391 /* ensure normal panel mode. */
392 setup_panel_mode(enc110, DP_PANEL_MODE_DEFAULT);
393
394 /* no vbid after BS (SR)
395 * DP_LINK_FRAMING_CNTL changed history Sandra Liu
396 * 11000260 / 11000104 / 110000FC */
397 REG_UPDATE_3(DP_LINK_FRAMING_CNTL,
398 DP_IDLE_BS_INTERVAL, 0xFC,
399 DP_VBID_DISABLE, 1,
400 DP_VID_ENHANCED_FRAME_MODE, 1);
401
402 /* swap every BS with SR */
403 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0);
404
405 /* select cp2520 patterns */
406 if (REG(DP_DPHY_HBR2_PATTERN_CONTROL))
407 REG_UPDATE(DP_DPHY_HBR2_PATTERN_CONTROL,
408 DP_DPHY_HBR2_PATTERN_CONTROL, cp2520_pattern);
409 else
410 /* pre-DCE11 can only generate CP2520 pattern 2 */
411 ASSERT(cp2520_pattern == 2);
412
413 /* set link training complete */
414 set_link_training_complete(enc110, true);
415
416 /* disable video stream */
417 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
418
419 /* Disable PHY Bypass mode to setup the test pattern */
420 enable_phy_bypass_mode(enc110, false);
421 }
422
set_dp_phy_pattern_passthrough_mode(struct dce110_link_encoder * enc110,enum dp_panel_mode panel_mode)423 static void set_dp_phy_pattern_passthrough_mode(
424 struct dce110_link_encoder *enc110,
425 enum dp_panel_mode panel_mode)
426 {
427 /* program correct panel mode */
428 setup_panel_mode(enc110, panel_mode);
429
430 /* restore LINK_FRAMING_CNTL and DPHY_SCRAMBLER_BS_COUNT
431 * in case we were doing HBR2 compliance pattern before
432 */
433 REG_UPDATE_3(DP_LINK_FRAMING_CNTL,
434 DP_IDLE_BS_INTERVAL, 0x2000,
435 DP_VBID_DISABLE, 0,
436 DP_VID_ENHANCED_FRAME_MODE, 1);
437
438 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0x1FF);
439
440 /* set link training complete */
441 set_link_training_complete(enc110, true);
442
443 /* Disable PHY Bypass mode to setup the test pattern */
444 enable_phy_bypass_mode(enc110, false);
445
446 /* Disable PRBS mode */
447 disable_prbs_mode(enc110);
448 }
449
450 /* return value is bit-vector */
get_frontend_source(enum engine_id engine)451 static uint8_t get_frontend_source(
452 enum engine_id engine)
453 {
454 switch (engine) {
455 case ENGINE_ID_DIGA:
456 return DCE110_DIG_FE_SOURCE_SELECT_DIGA;
457 case ENGINE_ID_DIGB:
458 return DCE110_DIG_FE_SOURCE_SELECT_DIGB;
459 case ENGINE_ID_DIGC:
460 return DCE110_DIG_FE_SOURCE_SELECT_DIGC;
461 case ENGINE_ID_DIGD:
462 return DCE110_DIG_FE_SOURCE_SELECT_DIGD;
463 case ENGINE_ID_DIGE:
464 return DCE110_DIG_FE_SOURCE_SELECT_DIGE;
465 case ENGINE_ID_DIGF:
466 return DCE110_DIG_FE_SOURCE_SELECT_DIGF;
467 case ENGINE_ID_DIGG:
468 return DCE110_DIG_FE_SOURCE_SELECT_DIGG;
469 default:
470 ASSERT_CRITICAL(false);
471 return DCE110_DIG_FE_SOURCE_SELECT_INVALID;
472 }
473 }
474
configure_encoder(struct dce110_link_encoder * enc110,const struct dc_link_settings * link_settings)475 static void configure_encoder(
476 struct dce110_link_encoder *enc110,
477 const struct dc_link_settings *link_settings)
478 {
479 /* set number of lanes */
480
481 REG_SET(DP_CONFIG, 0,
482 DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE);
483
484 /* setup scrambler */
485 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, 1);
486 }
487
aux_initialize(struct dce110_link_encoder * enc110)488 static void aux_initialize(
489 struct dce110_link_encoder *enc110)
490 {
491 struct dc_context *ctx = enc110->base.ctx;
492 enum hpd_source_id hpd_source = enc110->base.hpd_source;
493 uint32_t addr = AUX_REG(AUX_CONTROL);
494 uint32_t value = dm_read_reg(ctx, addr);
495
496 set_reg_field_value(value, hpd_source, AUX_CONTROL, AUX_HPD_SEL);
497 set_reg_field_value(value, 0, AUX_CONTROL, AUX_LS_READ_EN);
498 dm_write_reg(ctx, addr, value);
499
500 addr = AUX_REG(AUX_DPHY_RX_CONTROL0);
501 value = dm_read_reg(ctx, addr);
502
503 /* 1/4 window (the maximum allowed) */
504 set_reg_field_value(value, 1,
505 AUX_DPHY_RX_CONTROL0, AUX_RX_RECEIVE_WINDOW);
506 dm_write_reg(ctx, addr, value);
507
508 }
509
dce110_psr_program_dp_dphy_fast_training(struct link_encoder * enc,bool exit_link_training_required)510 void dce110_psr_program_dp_dphy_fast_training(struct link_encoder *enc,
511 bool exit_link_training_required)
512 {
513 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
514
515 if (exit_link_training_required)
516 REG_UPDATE(DP_DPHY_FAST_TRAINING,
517 DPHY_RX_FAST_TRAINING_CAPABLE, 1);
518 else {
519 REG_UPDATE(DP_DPHY_FAST_TRAINING,
520 DPHY_RX_FAST_TRAINING_CAPABLE, 0);
521 /*In DCE 11, we are able to pre-program a Force SR register
522 * to be able to trigger SR symbol after 5 idle patterns
523 * transmitted. Upon PSR Exit, DMCU can trigger
524 * DPHY_LOAD_BS_COUNT_START = 1. Upon writing 1 to
525 * DPHY_LOAD_BS_COUNT_START and the internal counter
526 * reaches DPHY_LOAD_BS_COUNT, the next BS symbol will be
527 * replaced by SR symbol once.
528 */
529
530 REG_UPDATE(DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, 0x5);
531 }
532 }
533
dce110_psr_program_secondary_packet(struct link_encoder * enc,unsigned int sdp_transmit_line_num_deadline)534 void dce110_psr_program_secondary_packet(struct link_encoder *enc,
535 unsigned int sdp_transmit_line_num_deadline)
536 {
537 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
538
539 REG_UPDATE_2(DP_SEC_CNTL1,
540 DP_SEC_GSP0_LINE_NUM, sdp_transmit_line_num_deadline,
541 DP_SEC_GSP0_PRIORITY, 1);
542 }
543
dce110_is_dig_enabled(struct link_encoder * enc)544 bool dce110_is_dig_enabled(struct link_encoder *enc)
545 {
546 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
547 uint32_t value;
548
549 REG_GET(DIG_BE_EN_CNTL, DIG_ENABLE, &value);
550 return value;
551 }
552
link_encoder_disable(struct dce110_link_encoder * enc110)553 static void link_encoder_disable(struct dce110_link_encoder *enc110)
554 {
555 /* reset training pattern */
556 REG_SET(DP_DPHY_TRAINING_PATTERN_SEL, 0,
557 DPHY_TRAINING_PATTERN_SEL, 0);
558
559 /* reset training complete */
560 REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, 0);
561
562 /* reset panel mode */
563 setup_panel_mode(enc110, DP_PANEL_MODE_DEFAULT);
564 }
565
hpd_initialize(struct dce110_link_encoder * enc110)566 static void hpd_initialize(
567 struct dce110_link_encoder *enc110)
568 {
569 /* Associate HPD with DIG_BE */
570 enum hpd_source_id hpd_source = enc110->base.hpd_source;
571
572 REG_UPDATE(DIG_BE_CNTL, DIG_HPD_SELECT, hpd_source);
573 }
574
dce110_link_encoder_validate_dvi_output(const struct dce110_link_encoder * enc110,enum signal_type connector_signal,enum signal_type signal,const struct dc_crtc_timing * crtc_timing)575 bool dce110_link_encoder_validate_dvi_output(
576 const struct dce110_link_encoder *enc110,
577 enum signal_type connector_signal,
578 enum signal_type signal,
579 const struct dc_crtc_timing *crtc_timing)
580 {
581 uint32_t max_pixel_clock = TMDS_MAX_PIXEL_CLOCK;
582
583 if (signal == SIGNAL_TYPE_DVI_DUAL_LINK)
584 max_pixel_clock *= 2;
585
586 /* This handles the case of HDMI downgrade to DVI we don't want to
587 * we don't want to cap the pixel clock if the DDI is not DVI.
588 */
589 if (connector_signal != SIGNAL_TYPE_DVI_DUAL_LINK &&
590 connector_signal != SIGNAL_TYPE_DVI_SINGLE_LINK)
591 max_pixel_clock = enc110->base.features.max_hdmi_pixel_clock;
592
593 /* DVI only support RGB pixel encoding */
594 if (crtc_timing->pixel_encoding != PIXEL_ENCODING_RGB)
595 return false;
596
597 /*connect DVI via adpater's HDMI connector*/
598 if ((connector_signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
599 connector_signal == SIGNAL_TYPE_HDMI_TYPE_A) &&
600 signal != SIGNAL_TYPE_HDMI_TYPE_A &&
601 crtc_timing->pix_clk_khz > TMDS_MAX_PIXEL_CLOCK)
602 return false;
603 if (crtc_timing->pix_clk_khz < TMDS_MIN_PIXEL_CLOCK)
604 return false;
605
606 if (crtc_timing->pix_clk_khz > max_pixel_clock)
607 return false;
608
609 /* DVI supports 6/8bpp single-link and 10/16bpp dual-link */
610 switch (crtc_timing->display_color_depth) {
611 case COLOR_DEPTH_666:
612 case COLOR_DEPTH_888:
613 break;
614 case COLOR_DEPTH_101010:
615 case COLOR_DEPTH_161616:
616 if (signal != SIGNAL_TYPE_DVI_DUAL_LINK)
617 return false;
618 break;
619 default:
620 return false;
621 }
622
623 return true;
624 }
625
dce110_link_encoder_validate_hdmi_output(const struct dce110_link_encoder * enc110,const struct dc_crtc_timing * crtc_timing,int adjusted_pix_clk_khz)626 static bool dce110_link_encoder_validate_hdmi_output(
627 const struct dce110_link_encoder *enc110,
628 const struct dc_crtc_timing *crtc_timing,
629 int adjusted_pix_clk_khz)
630 {
631 enum dc_color_depth max_deep_color =
632 enc110->base.features.max_hdmi_deep_color;
633
634 if (max_deep_color < crtc_timing->display_color_depth)
635 return false;
636
637 if (crtc_timing->display_color_depth < COLOR_DEPTH_888)
638 return false;
639 if (adjusted_pix_clk_khz < TMDS_MIN_PIXEL_CLOCK)
640 return false;
641
642 if ((adjusted_pix_clk_khz == 0) ||
643 (adjusted_pix_clk_khz > enc110->base.features.max_hdmi_pixel_clock))
644 return false;
645
646 /* DCE11 HW does not support 420 */
647 if (!enc110->base.features.ycbcr420_supported &&
648 crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
649 return false;
650
651 if (!enc110->base.features.flags.bits.HDMI_6GB_EN &&
652 adjusted_pix_clk_khz >= 300000)
653 return false;
654 if (enc110->base.ctx->dc->debug.hdmi20_disable &&
655 crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
656 return false;
657 return true;
658 }
659
dce110_link_encoder_validate_dp_output(const struct dce110_link_encoder * enc110,const struct dc_crtc_timing * crtc_timing)660 bool dce110_link_encoder_validate_dp_output(
661 const struct dce110_link_encoder *enc110,
662 const struct dc_crtc_timing *crtc_timing)
663 {
664 /* default RGB only */
665 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB)
666 return true;
667
668 if (enc110->base.features.flags.bits.IS_YCBCR_CAPABLE)
669 return true;
670
671 /* for DCE 8.x or later DP Y-only feature,
672 * we need ASIC cap + FeatureSupportDPYonly, not support 666 */
673 if (crtc_timing->flags.Y_ONLY &&
674 enc110->base.features.flags.bits.IS_YCBCR_CAPABLE &&
675 crtc_timing->display_color_depth != COLOR_DEPTH_666)
676 return true;
677
678 return false;
679 }
680
dce110_link_encoder_construct(struct dce110_link_encoder * enc110,const struct encoder_init_data * init_data,const struct encoder_feature_support * enc_features,const struct dce110_link_enc_registers * link_regs,const struct dce110_link_enc_aux_registers * aux_regs,const struct dce110_link_enc_hpd_registers * hpd_regs)681 void dce110_link_encoder_construct(
682 struct dce110_link_encoder *enc110,
683 const struct encoder_init_data *init_data,
684 const struct encoder_feature_support *enc_features,
685 const struct dce110_link_enc_registers *link_regs,
686 const struct dce110_link_enc_aux_registers *aux_regs,
687 const struct dce110_link_enc_hpd_registers *hpd_regs)
688 {
689 struct bp_encoder_cap_info bp_cap_info = {0};
690 const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
691 enum bp_result result = BP_RESULT_OK;
692
693 enc110->base.funcs = &dce110_lnk_enc_funcs;
694 enc110->base.ctx = init_data->ctx;
695 enc110->base.id = init_data->encoder;
696
697 enc110->base.hpd_source = init_data->hpd_source;
698 enc110->base.connector = init_data->connector;
699
700 enc110->base.preferred_engine = ENGINE_ID_UNKNOWN;
701
702 enc110->base.features = *enc_features;
703
704 enc110->base.transmitter = init_data->transmitter;
705
706 /* set the flag to indicate whether driver poll the I2C data pin
707 * while doing the DP sink detect
708 */
709
710 /* if (dal_adapter_service_is_feature_supported(as,
711 FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
712 enc110->base.features.flags.bits.
713 DP_SINK_DETECT_POLL_DATA_PIN = true;*/
714
715 enc110->base.output_signals =
716 SIGNAL_TYPE_DVI_SINGLE_LINK |
717 SIGNAL_TYPE_DVI_DUAL_LINK |
718 SIGNAL_TYPE_LVDS |
719 SIGNAL_TYPE_DISPLAY_PORT |
720 SIGNAL_TYPE_DISPLAY_PORT_MST |
721 SIGNAL_TYPE_EDP |
722 SIGNAL_TYPE_HDMI_TYPE_A;
723
724 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
725 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
726 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
727 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
728 * Prefer DIG assignment is decided by board design.
729 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
730 * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
731 * By this, adding DIGG should not hurt DCE 8.0.
732 * This will let DCE 8.1 share DCE 8.0 as much as possible
733 */
734
735 enc110->link_regs = link_regs;
736 enc110->aux_regs = aux_regs;
737 enc110->hpd_regs = hpd_regs;
738
739 switch (enc110->base.transmitter) {
740 case TRANSMITTER_UNIPHY_A:
741 enc110->base.preferred_engine = ENGINE_ID_DIGA;
742 break;
743 case TRANSMITTER_UNIPHY_B:
744 enc110->base.preferred_engine = ENGINE_ID_DIGB;
745 break;
746 case TRANSMITTER_UNIPHY_C:
747 enc110->base.preferred_engine = ENGINE_ID_DIGC;
748 break;
749 case TRANSMITTER_UNIPHY_D:
750 enc110->base.preferred_engine = ENGINE_ID_DIGD;
751 break;
752 case TRANSMITTER_UNIPHY_E:
753 enc110->base.preferred_engine = ENGINE_ID_DIGE;
754 break;
755 case TRANSMITTER_UNIPHY_F:
756 enc110->base.preferred_engine = ENGINE_ID_DIGF;
757 break;
758 case TRANSMITTER_UNIPHY_G:
759 enc110->base.preferred_engine = ENGINE_ID_DIGG;
760 break;
761 default:
762 ASSERT_CRITICAL(false);
763 enc110->base.preferred_engine = ENGINE_ID_UNKNOWN;
764 }
765
766 /* default to one to mirror Windows behavior */
767 enc110->base.features.flags.bits.HDMI_6GB_EN = 1;
768
769 result = bp_funcs->get_encoder_cap_info(enc110->base.ctx->dc_bios,
770 enc110->base.id, &bp_cap_info);
771
772 /* Override features with DCE-specific values */
773 if (BP_RESULT_OK == result) {
774 enc110->base.features.flags.bits.IS_HBR2_CAPABLE =
775 bp_cap_info.DP_HBR2_EN;
776 enc110->base.features.flags.bits.IS_HBR3_CAPABLE =
777 bp_cap_info.DP_HBR3_EN;
778 enc110->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
779 } else {
780 DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
781 __func__,
782 result);
783 }
784 if (enc110->base.ctx->dc->debug.hdmi20_disable) {
785 enc110->base.features.flags.bits.HDMI_6GB_EN = 0;
786 }
787 }
788
dce110_link_encoder_validate_output_with_stream(struct link_encoder * enc,const struct dc_stream_state * stream)789 bool dce110_link_encoder_validate_output_with_stream(
790 struct link_encoder *enc,
791 const struct dc_stream_state *stream)
792 {
793 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
794 bool is_valid;
795
796 switch (stream->signal) {
797 case SIGNAL_TYPE_DVI_SINGLE_LINK:
798 case SIGNAL_TYPE_DVI_DUAL_LINK:
799 is_valid = dce110_link_encoder_validate_dvi_output(
800 enc110,
801 stream->sink->link->connector_signal,
802 stream->signal,
803 &stream->timing);
804 break;
805 case SIGNAL_TYPE_HDMI_TYPE_A:
806 is_valid = dce110_link_encoder_validate_hdmi_output(
807 enc110,
808 &stream->timing,
809 stream->phy_pix_clk);
810 break;
811 case SIGNAL_TYPE_DISPLAY_PORT:
812 case SIGNAL_TYPE_DISPLAY_PORT_MST:
813 is_valid = dce110_link_encoder_validate_dp_output(
814 enc110, &stream->timing);
815 break;
816 case SIGNAL_TYPE_EDP:
817 is_valid =
818 (stream->timing.
819 pixel_encoding == PIXEL_ENCODING_RGB) ? true : false;
820 break;
821 case SIGNAL_TYPE_VIRTUAL:
822 is_valid = true;
823 break;
824 default:
825 is_valid = false;
826 break;
827 }
828
829 return is_valid;
830 }
831
dce110_link_encoder_hw_init(struct link_encoder * enc)832 void dce110_link_encoder_hw_init(
833 struct link_encoder *enc)
834 {
835 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
836 struct bp_transmitter_control cntl = { 0 };
837 enum bp_result result;
838
839 cntl.action = TRANSMITTER_CONTROL_INIT;
840 cntl.engine_id = ENGINE_ID_UNKNOWN;
841 cntl.transmitter = enc110->base.transmitter;
842 cntl.connector_obj_id = enc110->base.connector;
843 cntl.lanes_number = LANE_COUNT_FOUR;
844 cntl.coherent = false;
845 cntl.hpd_sel = enc110->base.hpd_source;
846
847 if (enc110->base.connector.id == CONNECTOR_ID_EDP)
848 cntl.signal = SIGNAL_TYPE_EDP;
849
850 result = link_transmitter_control(enc110, &cntl);
851
852 if (result != BP_RESULT_OK) {
853 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
854 __func__);
855 BREAK_TO_DEBUGGER();
856 return;
857 }
858
859 if (enc110->base.connector.id == CONNECTOR_ID_LVDS) {
860 cntl.action = TRANSMITTER_CONTROL_BACKLIGHT_BRIGHTNESS;
861
862 result = link_transmitter_control(enc110, &cntl);
863
864 ASSERT(result == BP_RESULT_OK);
865
866 }
867 aux_initialize(enc110);
868
869 /* reinitialize HPD.
870 * hpd_initialize() will pass DIG_FE id to HW context.
871 * All other routine within HW context will use fe_engine_offset
872 * as DIG_FE id even caller pass DIG_FE id.
873 * So this routine must be called first. */
874 hpd_initialize(enc110);
875 }
876
dce110_link_encoder_destroy(struct link_encoder ** enc)877 void dce110_link_encoder_destroy(struct link_encoder **enc)
878 {
879 kfree(TO_DCE110_LINK_ENC(*enc));
880 *enc = NULL;
881 }
882
dce110_link_encoder_setup(struct link_encoder * enc,enum signal_type signal)883 void dce110_link_encoder_setup(
884 struct link_encoder *enc,
885 enum signal_type signal)
886 {
887 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
888
889 switch (signal) {
890 case SIGNAL_TYPE_EDP:
891 case SIGNAL_TYPE_DISPLAY_PORT:
892 /* DP SST */
893 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 0);
894 break;
895 case SIGNAL_TYPE_LVDS:
896 /* LVDS */
897 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 1);
898 break;
899 case SIGNAL_TYPE_DVI_SINGLE_LINK:
900 case SIGNAL_TYPE_DVI_DUAL_LINK:
901 /* TMDS-DVI */
902 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 2);
903 break;
904 case SIGNAL_TYPE_HDMI_TYPE_A:
905 /* TMDS-HDMI */
906 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 3);
907 break;
908 case SIGNAL_TYPE_DISPLAY_PORT_MST:
909 /* DP MST */
910 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 5);
911 break;
912 default:
913 ASSERT_CRITICAL(false);
914 /* invalid mode ! */
915 break;
916 }
917
918 }
919
920 /* TODO: still need depth or just pass in adjusted pixel clock? */
dce110_link_encoder_enable_tmds_output(struct link_encoder * enc,enum clock_source_id clock_source,enum dc_color_depth color_depth,enum signal_type signal,uint32_t pixel_clock)921 void dce110_link_encoder_enable_tmds_output(
922 struct link_encoder *enc,
923 enum clock_source_id clock_source,
924 enum dc_color_depth color_depth,
925 enum signal_type signal,
926 uint32_t pixel_clock)
927 {
928 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
929 struct bp_transmitter_control cntl = { 0 };
930 enum bp_result result;
931
932 /* Enable the PHY */
933 cntl.connector_obj_id = enc110->base.connector;
934 cntl.action = TRANSMITTER_CONTROL_ENABLE;
935 cntl.engine_id = enc->preferred_engine;
936 cntl.transmitter = enc110->base.transmitter;
937 cntl.pll_id = clock_source;
938 cntl.signal = signal;
939 if (cntl.signal == SIGNAL_TYPE_DVI_DUAL_LINK)
940 cntl.lanes_number = 8;
941 else
942 cntl.lanes_number = 4;
943
944 cntl.hpd_sel = enc110->base.hpd_source;
945
946 cntl.pixel_clock = pixel_clock;
947 cntl.color_depth = color_depth;
948
949 result = link_transmitter_control(enc110, &cntl);
950
951 if (result != BP_RESULT_OK) {
952 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
953 __func__);
954 BREAK_TO_DEBUGGER();
955 }
956 }
957
958 /* enables DP PHY output */
dce110_link_encoder_enable_dp_output(struct link_encoder * enc,const struct dc_link_settings * link_settings,enum clock_source_id clock_source)959 void dce110_link_encoder_enable_dp_output(
960 struct link_encoder *enc,
961 const struct dc_link_settings *link_settings,
962 enum clock_source_id clock_source)
963 {
964 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
965 struct bp_transmitter_control cntl = { 0 };
966 enum bp_result result;
967
968 /* Enable the PHY */
969
970 /* number_of_lanes is used for pixel clock adjust,
971 * but it's not passed to asic_control.
972 * We need to set number of lanes manually.
973 */
974 configure_encoder(enc110, link_settings);
975 cntl.connector_obj_id = enc110->base.connector;
976 cntl.action = TRANSMITTER_CONTROL_ENABLE;
977 cntl.engine_id = enc->preferred_engine;
978 cntl.transmitter = enc110->base.transmitter;
979 cntl.pll_id = clock_source;
980 cntl.signal = SIGNAL_TYPE_DISPLAY_PORT;
981 cntl.lanes_number = link_settings->lane_count;
982 cntl.hpd_sel = enc110->base.hpd_source;
983 cntl.pixel_clock = link_settings->link_rate
984 * LINK_RATE_REF_FREQ_IN_KHZ;
985 /* TODO: check if undefined works */
986 cntl.color_depth = COLOR_DEPTH_UNDEFINED;
987
988 result = link_transmitter_control(enc110, &cntl);
989
990 if (result != BP_RESULT_OK) {
991 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
992 __func__);
993 BREAK_TO_DEBUGGER();
994 }
995 }
996
997 /* enables DP PHY output in MST mode */
dce110_link_encoder_enable_dp_mst_output(struct link_encoder * enc,const struct dc_link_settings * link_settings,enum clock_source_id clock_source)998 void dce110_link_encoder_enable_dp_mst_output(
999 struct link_encoder *enc,
1000 const struct dc_link_settings *link_settings,
1001 enum clock_source_id clock_source)
1002 {
1003 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1004 struct bp_transmitter_control cntl = { 0 };
1005 enum bp_result result;
1006
1007 /* Enable the PHY */
1008
1009 /* number_of_lanes is used for pixel clock adjust,
1010 * but it's not passed to asic_control.
1011 * We need to set number of lanes manually.
1012 */
1013 configure_encoder(enc110, link_settings);
1014
1015 cntl.action = TRANSMITTER_CONTROL_ENABLE;
1016 cntl.engine_id = ENGINE_ID_UNKNOWN;
1017 cntl.transmitter = enc110->base.transmitter;
1018 cntl.pll_id = clock_source;
1019 cntl.signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
1020 cntl.lanes_number = link_settings->lane_count;
1021 cntl.hpd_sel = enc110->base.hpd_source;
1022 cntl.pixel_clock = link_settings->link_rate
1023 * LINK_RATE_REF_FREQ_IN_KHZ;
1024 /* TODO: check if undefined works */
1025 cntl.color_depth = COLOR_DEPTH_UNDEFINED;
1026
1027 result = link_transmitter_control(enc110, &cntl);
1028
1029 if (result != BP_RESULT_OK) {
1030 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
1031 __func__);
1032 BREAK_TO_DEBUGGER();
1033 }
1034 }
1035 /*
1036 * @brief
1037 * Disable transmitter and its encoder
1038 */
dce110_link_encoder_disable_output(struct link_encoder * enc,enum signal_type signal)1039 void dce110_link_encoder_disable_output(
1040 struct link_encoder *enc,
1041 enum signal_type signal)
1042 {
1043 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1044 struct bp_transmitter_control cntl = { 0 };
1045 enum bp_result result;
1046
1047 if (!dce110_is_dig_enabled(enc)) {
1048 /* OF_SKIP_POWER_DOWN_INACTIVE_ENCODER */
1049 return;
1050 }
1051 /* Power-down RX and disable GPU PHY should be paired.
1052 * Disabling PHY without powering down RX may cause
1053 * symbol lock loss, on which we will get DP Sink interrupt. */
1054
1055 /* There is a case for the DP active dongles
1056 * where we want to disable the PHY but keep RX powered,
1057 * for those we need to ignore DP Sink interrupt
1058 * by checking lane count that has been set
1059 * on the last do_enable_output(). */
1060
1061 /* disable transmitter */
1062 cntl.action = TRANSMITTER_CONTROL_DISABLE;
1063 cntl.transmitter = enc110->base.transmitter;
1064 cntl.hpd_sel = enc110->base.hpd_source;
1065 cntl.signal = signal;
1066 cntl.connector_obj_id = enc110->base.connector;
1067
1068 result = link_transmitter_control(enc110, &cntl);
1069
1070 if (result != BP_RESULT_OK) {
1071 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
1072 __func__);
1073 BREAK_TO_DEBUGGER();
1074 return;
1075 }
1076
1077 /* disable encoder */
1078 if (dc_is_dp_signal(signal))
1079 link_encoder_disable(enc110);
1080 }
1081
dce110_link_encoder_dp_set_lane_settings(struct link_encoder * enc,const struct link_training_settings * link_settings)1082 void dce110_link_encoder_dp_set_lane_settings(
1083 struct link_encoder *enc,
1084 const struct link_training_settings *link_settings)
1085 {
1086 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1087 union dpcd_training_lane_set training_lane_set = { { 0 } };
1088 int32_t lane = 0;
1089 struct bp_transmitter_control cntl = { 0 };
1090
1091 if (!link_settings) {
1092 BREAK_TO_DEBUGGER();
1093 return;
1094 }
1095
1096 cntl.action = TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS;
1097 cntl.transmitter = enc110->base.transmitter;
1098 cntl.connector_obj_id = enc110->base.connector;
1099 cntl.lanes_number = link_settings->link_settings.lane_count;
1100 cntl.hpd_sel = enc110->base.hpd_source;
1101 cntl.pixel_clock = link_settings->link_settings.link_rate *
1102 LINK_RATE_REF_FREQ_IN_KHZ;
1103
1104 for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) {
1105 /* translate lane settings */
1106
1107 training_lane_set.bits.VOLTAGE_SWING_SET =
1108 link_settings->lane_settings[lane].VOLTAGE_SWING;
1109 training_lane_set.bits.PRE_EMPHASIS_SET =
1110 link_settings->lane_settings[lane].PRE_EMPHASIS;
1111
1112 /* post cursor 2 setting only applies to HBR2 link rate */
1113 if (link_settings->link_settings.link_rate == LINK_RATE_HIGH2) {
1114 /* this is passed to VBIOS
1115 * to program post cursor 2 level */
1116
1117 training_lane_set.bits.POST_CURSOR2_SET =
1118 link_settings->lane_settings[lane].POST_CURSOR2;
1119 }
1120
1121 cntl.lane_select = lane;
1122 cntl.lane_settings = training_lane_set.raw;
1123
1124 /* call VBIOS table to set voltage swing and pre-emphasis */
1125 link_transmitter_control(enc110, &cntl);
1126 }
1127 }
1128
1129 /* set DP PHY test and training patterns */
dce110_link_encoder_dp_set_phy_pattern(struct link_encoder * enc,const struct encoder_set_dp_phy_pattern_param * param)1130 void dce110_link_encoder_dp_set_phy_pattern(
1131 struct link_encoder *enc,
1132 const struct encoder_set_dp_phy_pattern_param *param)
1133 {
1134 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1135
1136 switch (param->dp_phy_pattern) {
1137 case DP_TEST_PATTERN_TRAINING_PATTERN1:
1138 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 0);
1139 break;
1140 case DP_TEST_PATTERN_TRAINING_PATTERN2:
1141 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 1);
1142 break;
1143 case DP_TEST_PATTERN_TRAINING_PATTERN3:
1144 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 2);
1145 break;
1146 case DP_TEST_PATTERN_TRAINING_PATTERN4:
1147 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 3);
1148 break;
1149 case DP_TEST_PATTERN_D102:
1150 set_dp_phy_pattern_d102(enc110);
1151 break;
1152 case DP_TEST_PATTERN_SYMBOL_ERROR:
1153 set_dp_phy_pattern_symbol_error(enc110);
1154 break;
1155 case DP_TEST_PATTERN_PRBS7:
1156 set_dp_phy_pattern_prbs7(enc110);
1157 break;
1158 case DP_TEST_PATTERN_80BIT_CUSTOM:
1159 set_dp_phy_pattern_80bit_custom(
1160 enc110, param->custom_pattern);
1161 break;
1162 case DP_TEST_PATTERN_CP2520_1:
1163 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 1);
1164 break;
1165 case DP_TEST_PATTERN_CP2520_2:
1166 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 2);
1167 break;
1168 case DP_TEST_PATTERN_CP2520_3:
1169 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 3);
1170 break;
1171 case DP_TEST_PATTERN_VIDEO_MODE: {
1172 set_dp_phy_pattern_passthrough_mode(
1173 enc110, param->dp_panel_mode);
1174 break;
1175 }
1176
1177 default:
1178 /* invalid phy pattern */
1179 ASSERT_CRITICAL(false);
1180 break;
1181 }
1182 }
1183
fill_stream_allocation_row_info(const struct link_mst_stream_allocation * stream_allocation,uint32_t * src,uint32_t * slots)1184 static void fill_stream_allocation_row_info(
1185 const struct link_mst_stream_allocation *stream_allocation,
1186 uint32_t *src,
1187 uint32_t *slots)
1188 {
1189 const struct stream_encoder *stream_enc = stream_allocation->stream_enc;
1190
1191 if (stream_enc) {
1192 *src = stream_enc->id;
1193 *slots = stream_allocation->slot_count;
1194 } else {
1195 *src = 0;
1196 *slots = 0;
1197 }
1198 }
1199
1200 /* programs DP MST VC payload allocation */
dce110_link_encoder_update_mst_stream_allocation_table(struct link_encoder * enc,const struct link_mst_stream_allocation_table * table)1201 void dce110_link_encoder_update_mst_stream_allocation_table(
1202 struct link_encoder *enc,
1203 const struct link_mst_stream_allocation_table *table)
1204 {
1205 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1206 uint32_t value0 = 0;
1207 uint32_t value1 = 0;
1208 uint32_t value2 = 0;
1209 uint32_t slots = 0;
1210 uint32_t src = 0;
1211 uint32_t retries = 0;
1212
1213 /* For CZ, there are only 3 pipes. So Virtual channel is up 3.*/
1214
1215 /* --- Set MSE Stream Attribute -
1216 * Setup VC Payload Table on Tx Side,
1217 * Issue allocation change trigger
1218 * to commit payload on both tx and rx side */
1219
1220 /* we should clean-up table each time */
1221
1222 if (table->stream_count >= 1) {
1223 fill_stream_allocation_row_info(
1224 &table->stream_allocations[0],
1225 &src,
1226 &slots);
1227 } else {
1228 src = 0;
1229 slots = 0;
1230 }
1231
1232 REG_UPDATE_2(DP_MSE_SAT0,
1233 DP_MSE_SAT_SRC0, src,
1234 DP_MSE_SAT_SLOT_COUNT0, slots);
1235
1236 if (table->stream_count >= 2) {
1237 fill_stream_allocation_row_info(
1238 &table->stream_allocations[1],
1239 &src,
1240 &slots);
1241 } else {
1242 src = 0;
1243 slots = 0;
1244 }
1245
1246 REG_UPDATE_2(DP_MSE_SAT0,
1247 DP_MSE_SAT_SRC1, src,
1248 DP_MSE_SAT_SLOT_COUNT1, slots);
1249
1250 if (table->stream_count >= 3) {
1251 fill_stream_allocation_row_info(
1252 &table->stream_allocations[2],
1253 &src,
1254 &slots);
1255 } else {
1256 src = 0;
1257 slots = 0;
1258 }
1259
1260 REG_UPDATE_2(DP_MSE_SAT1,
1261 DP_MSE_SAT_SRC2, src,
1262 DP_MSE_SAT_SLOT_COUNT2, slots);
1263
1264 if (table->stream_count >= 4) {
1265 fill_stream_allocation_row_info(
1266 &table->stream_allocations[3],
1267 &src,
1268 &slots);
1269 } else {
1270 src = 0;
1271 slots = 0;
1272 }
1273
1274 REG_UPDATE_2(DP_MSE_SAT1,
1275 DP_MSE_SAT_SRC3, src,
1276 DP_MSE_SAT_SLOT_COUNT3, slots);
1277
1278 /* --- wait for transaction finish */
1279
1280 /* send allocation change trigger (ACT) ?
1281 * this step first sends the ACT,
1282 * then double buffers the SAT into the hardware
1283 * making the new allocation active on the DP MST mode link */
1284
1285
1286 /* DP_MSE_SAT_UPDATE:
1287 * 0 - No Action
1288 * 1 - Update SAT with trigger
1289 * 2 - Update SAT without trigger */
1290
1291 REG_UPDATE(DP_MSE_SAT_UPDATE,
1292 DP_MSE_SAT_UPDATE, 1);
1293
1294 /* wait for update to complete
1295 * (i.e. DP_MSE_SAT_UPDATE field is reset to 0)
1296 * then wait for the transmission
1297 * of at least 16 MTP headers on immediate local link.
1298 * i.e. DP_MSE_16_MTP_KEEPOUT field (read only) is reset to 0
1299 * a value of 1 indicates that DP MST mode
1300 * is in the 16 MTP keepout region after a VC has been added.
1301 * MST stream bandwidth (VC rate) can be configured
1302 * after this bit is cleared */
1303
1304 do {
1305 udelay(10);
1306
1307 value0 = REG_READ(DP_MSE_SAT_UPDATE);
1308
1309 REG_GET(DP_MSE_SAT_UPDATE,
1310 DP_MSE_SAT_UPDATE, &value1);
1311
1312 REG_GET(DP_MSE_SAT_UPDATE,
1313 DP_MSE_16_MTP_KEEPOUT, &value2);
1314
1315 /* bit field DP_MSE_SAT_UPDATE is set to 1 already */
1316 if (!value1 && !value2)
1317 break;
1318 ++retries;
1319 } while (retries < DP_MST_UPDATE_MAX_RETRY);
1320 }
1321
dce110_link_encoder_connect_dig_be_to_fe(struct link_encoder * enc,enum engine_id engine,bool connect)1322 void dce110_link_encoder_connect_dig_be_to_fe(
1323 struct link_encoder *enc,
1324 enum engine_id engine,
1325 bool connect)
1326 {
1327 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1328 uint32_t field;
1329
1330 if (engine != ENGINE_ID_UNKNOWN) {
1331
1332 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &field);
1333
1334 if (connect)
1335 field |= get_frontend_source(engine);
1336 else
1337 field &= ~get_frontend_source(engine);
1338
1339 REG_UPDATE(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, field);
1340 }
1341 }
1342
dce110_link_encoder_enable_hpd(struct link_encoder * enc)1343 void dce110_link_encoder_enable_hpd(struct link_encoder *enc)
1344 {
1345 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1346 struct dc_context *ctx = enc110->base.ctx;
1347 uint32_t addr = HPD_REG(DC_HPD_CONTROL);
1348 uint32_t hpd_enable = 0;
1349 uint32_t value = dm_read_reg(ctx, addr);
1350
1351 get_reg_field_value(hpd_enable, DC_HPD_CONTROL, DC_HPD_EN);
1352
1353 if (hpd_enable == 0)
1354 set_reg_field_value(value, 1, DC_HPD_CONTROL, DC_HPD_EN);
1355 }
1356
dce110_link_encoder_disable_hpd(struct link_encoder * enc)1357 void dce110_link_encoder_disable_hpd(struct link_encoder *enc)
1358 {
1359 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1360 struct dc_context *ctx = enc110->base.ctx;
1361 uint32_t addr = HPD_REG(DC_HPD_CONTROL);
1362 uint32_t value = dm_read_reg(ctx, addr);
1363
1364 set_reg_field_value(value, 0, DC_HPD_CONTROL, DC_HPD_EN);
1365 }
1366