1 /* $OpenBSD: tgavar.h,v 1.8 2002/07/04 00:34:28 miod Exp $ */ 2 /* $NetBSD: tgavar.h,v 1.8 2000/04/02 19:01:11 nathanw Exp $ */ 3 4 /* 5 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 6 * All rights reserved. 7 * 8 * Author: Chris G. Demetriou 9 * 10 * Permission to use, copy, modify and distribute this software and 11 * its documentation is hereby granted, provided that both the copyright 12 * notice and this permission notice appear in all copies of the 13 * software, derivative works or modified versions, and any portions 14 * thereof, and that both notices appear in supporting documentation. 15 * 16 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 17 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 18 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 19 * 20 * Carnegie Mellon requests users of this software to return to 21 * 22 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 23 * School of Computer Science 24 * Carnegie Mellon University 25 * Pittsburgh PA 15213-3890 26 * 27 * any improvements or extensions that they make and grant Carnegie the 28 * rights to redistribute these changes. 29 */ 30 31 #include <dev/ic/ramdac.h> 32 #include <dev/pci/tgareg.h> 33 #include <dev/wscons/wsconsio.h> 34 #include <dev/wscons/wscons_raster.h> 35 #include <dev/wscons/wsdisplayvar.h> 36 #include <dev/rasops/rasops.h> 37 38 struct tga_devconfig; 39 struct fbcmap; 40 struct fbcursor; 41 struct fbcurpos; 42 43 struct tga_conf { 44 char *tgac_name; /* name for this board type */ 45 46 struct ramdac_funcs *(*ramdac_funcs)(void); 47 48 int tgac_phys_depth; /* physical frame buffer depth */ 49 vsize_t tgac_cspace_size; /* core space size */ 50 vsize_t tgac_vvbr_units; /* what '1' in the VVBR means */ 51 52 int tgac_ndbuf; /* number of display buffers */ 53 vaddr_t tgac_dbuf[2]; /* display buffer offsets/addresses */ 54 vsize_t tgac_dbufsz[2]; /* display buffer sizes */ 55 56 int tgac_nbbuf; /* number of display buffers */ 57 vaddr_t tgac_bbuf[2]; /* back buffer offsets/addresses */ 58 vsize_t tgac_bbufsz[2]; /* back buffer sizes */ 59 }; 60 61 struct tga_devconfig { 62 bus_space_tag_t dc_memt; 63 bus_space_handle_t dc_memh; 64 65 pcitag_t dc_pcitag; /* PCI tag */ 66 bus_addr_t dc_pcipaddr; /* PCI phys addr. */ 67 68 bus_space_handle_t dc_regs; /* registers; XXX: need aliases */ 69 70 int dc_tga_type; /* the device type; see below */ 71 int dc_tga2; /* True if it is a TGA2 */ 72 const struct tga_conf *dc_tgaconf; /* device buffer configuration */ 73 74 struct ramdac_funcs 75 *dc_ramdac_funcs; /* The RAMDAC functions */ 76 struct ramdac_cookie 77 *dc_ramdac_cookie; /* the RAMDAC type; see above */ 78 79 vaddr_t dc_vaddr; /* memory space virtual base address */ 80 paddr_t dc_paddr; /* memory space physical base address */ 81 82 int dc_wid; /* width of frame buffer */ 83 int dc_ht; /* height of frame buffer */ 84 int dc_rowbytes; /* bytes in a FB scan line */ 85 86 vaddr_t dc_videobase; /* base of flat frame buffer */ 87 88 struct rasops_info dc_rinfo; /* raster display data */ 89 90 int dc_blanked; /* currently had video disabled */ 91 void *dc_ramdac_private; /* RAMDAC private storage */ 92 93 void (*dc_ramdac_intr)(void *); 94 int dc_intrenabled; /* can we depend on interrupts yet? */ 95 }; 96 97 struct tga_softc { 98 struct device sc_dev; 99 100 struct tga_devconfig *sc_dc; /* device configuration */ 101 void *sc_intr; /* interrupt handler info */ 102 u_int sc_mode; /* wscons mode used */ 103 /* XXX should record intr fns/arg */ 104 105 int nscreens; 106 }; 107 108 #define TGA_TYPE_T8_01 0 /* 8bpp, 1MB */ 109 #define TGA_TYPE_T8_02 1 /* 8bpp, 2MB */ 110 #define TGA_TYPE_T8_22 2 /* 8bpp, 4MB */ 111 #define TGA_TYPE_T8_44 3 /* 8bpp, 8MB */ 112 #define TGA_TYPE_T32_04 4 /* 32bpp, 4MB */ 113 #define TGA_TYPE_T32_08 5 /* 32bpp, 8MB */ 114 #define TGA_TYPE_T32_88 6 /* 32bpp, 16MB */ 115 #define TGA_TYPE_POWERSTORM_4D20 7 /* unknown */ 116 #define TGA_TYPE_UNKNOWN 8 /* unknown */ 117 118 #define DEVICE_IS_TGA(class, id) \ 119 (((PCI_VENDOR(id) == PCI_VENDOR_DEC && \ 120 PCI_PRODUCT(id) == PCI_PRODUCT_DEC_21030) || \ 121 PCI_PRODUCT(id) == PCI_PRODUCT_DEC_PBXGB) ? 10 : 0) 122 123 int tga_cnattach(bus_space_tag_t, bus_space_tag_t, pci_chipset_tag_t, 124 int, int, int); 125 126 int tga_identify(struct tga_devconfig *); 127 const struct tga_conf *tga_getconf(int); 128 129 int tga_builtin_set_cursor(struct tga_devconfig *, 130 struct wsdisplay_cursor *); 131 int tga_builtin_get_cursor(struct tga_devconfig *, 132 struct wsdisplay_cursor *); 133 int tga_builtin_set_curpos(struct tga_devconfig *, 134 struct wsdisplay_curpos *); 135 int tga_builtin_get_curpos(struct tga_devconfig *, 136 struct wsdisplay_curpos *); 137 int tga_builtin_get_curmax(struct tga_devconfig *, 138 struct wsdisplay_curpos *); 139 140 /* Read a TGA register */ 141 #define TGARREG(dc,reg) (bus_space_read_4((dc)->dc_memt, (dc)->dc_regs, \ 142 (reg) << 2)) 143 144 /* Write a TGA register */ 145 #define TGAWREG(dc,reg,val) bus_space_write_4((dc)->dc_memt, (dc)->dc_regs, \ 146 (reg) << 2, (val)) 147 148 /* Write a TGA register at an alternate aliased location */ 149 #define TGAWALREG(dc,reg,alias,val) bus_space_write_4( \ 150 (dc)->dc_memt, (dc)->dc_regs, \ 151 ((alias) * TGA_CREGS_ALIAS) + ((reg) << 2), \ 152 (val)) 153 154 /* Insert a write barrier */ 155 #define TGAREGWB(dc,reg, nregs) bus_space_barrier( \ 156 (dc)->dc_memt, (dc)->dc_regs, \ 157 ((reg) << 2), 4 * (nregs), BUS_SPACE_BARRIER_WRITE) 158 159 /* Insert a read barrier */ 160 #define TGAREGRB(dc,reg, nregs) bus_space_barrier( \ 161 (dc)->dc_memt, (dc)->dc_regs, \ 162 ((reg) << 2), 4 * (nregs), BUS_SPACE_BARRIER_READ) 163 164 /* Insert a read/write barrier */ 165 #define TGAREGRWB(dc,reg, nregs) bus_space_barrier( \ 166 (dc)->dc_memt, (dc)->dc_regs, \ 167 ((reg) << 2), 4 * (nregs), \ 168 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 169