1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 1999 Seigo Tanimura
5 * All rights reserved.
6 *
7 * Portions of this source are based on cwcealdr.cpp and dhwiface.cpp in
8 * cwcealdr1.zip, the sample sources by Crystal Semiconductor.
9 * Copyright (c) 1996-1998 Crystal Semiconductor Corp.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
31 */
32
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/bus.h>
37 #include <sys/malloc.h>
38 #include <sys/module.h>
39 #include <machine/resource.h>
40 #include <machine/bus.h>
41 #include <sys/rman.h>
42
43 #ifdef HAVE_KERNEL_OPTION_HEADERS
44 #include "opt_snd.h"
45 #endif
46
47 #include <dev/sound/pcm/sound.h>
48 #include <dev/sound/pci/csareg.h>
49 #include <dev/sound/pci/csavar.h>
50
51 #include <dev/pci/pcireg.h>
52 #include <dev/pci/pcivar.h>
53
54 #include <dev/sound/pci/cs461x_dsp.h>
55
56 /* This is the pci device id. */
57 #define CS4610_PCI_ID 0x60011013
58 #define CS4614_PCI_ID 0x60031013
59 #define CS4615_PCI_ID 0x60041013
60
61 /* Here is the parameter structure per a device. */
62 struct csa_softc {
63 device_t dev; /* device */
64 csa_res res; /* resources */
65
66 device_t pcm; /* pcm device */
67 driver_intr_t* pcmintr; /* pcm intr */
68 void *pcmintr_arg; /* pcm intr arg */
69 device_t midi; /* midi device */
70 driver_intr_t* midiintr; /* midi intr */
71 void *midiintr_arg; /* midi intr arg */
72 void *ih; /* cookie */
73
74 struct csa_card *card;
75 struct csa_bridgeinfo binfo; /* The state of this bridge. */
76 };
77
78 typedef struct csa_softc *sc_p;
79
80 static int csa_probe(device_t dev);
81 static int csa_attach(device_t dev);
82 static struct resource *csa_alloc_resource(device_t bus, device_t child, int type, int *rid,
83 rman_res_t start, rman_res_t end,
84 rman_res_t count, u_int flags);
85 static int csa_release_resource(device_t bus, device_t child, int type, int rid,
86 struct resource *r);
87 static int csa_setup_intr(device_t bus, device_t child,
88 struct resource *irq, int flags,
89 driver_filter_t *filter,
90 driver_intr_t *intr, void *arg, void **cookiep);
91 static int csa_teardown_intr(device_t bus, device_t child,
92 struct resource *irq, void *cookie);
93 static driver_intr_t csa_intr;
94 static int csa_initialize(sc_p scp);
95 static int csa_downloadimage(csa_res *resp);
96 static int csa_transferimage(csa_res *resp, u_int32_t *src, u_long dest, u_long len);
97
98 static void
amp_none(void)99 amp_none(void)
100 {
101 }
102
103 static void
amp_voyetra(void)104 amp_voyetra(void)
105 {
106 }
107
108 static int
clkrun_hack(int run)109 clkrun_hack(int run)
110 {
111 #ifdef __i386__
112 device_t child;
113 int port;
114 u_int16_t control;
115 bus_space_tag_t btag;
116
117 child = pci_find_device(0x8086, 0x7113);
118 if (child == NULL)
119 return (ENXIO);
120
121 port = (pci_read_config(child, 0x41, 1) << 8) + 0x10;
122 /* XXX */
123 btag = X86_BUS_SPACE_IO;
124
125 control = bus_space_read_2(btag, 0x0, port);
126 control &= ~0x2000;
127 control |= run? 0 : 0x2000;
128 bus_space_write_2(btag, 0x0, port, control);
129 #endif
130 return (0);
131 }
132
133 static struct csa_card cards_4610[] = {
134 {0, 0, "Unknown/invalid SSID (CS4610)", NULL, NULL, NULL, 0},
135 };
136
137 static struct csa_card cards_4614[] = {
138 {0x1489, 0x7001, "Genius Soundmaker 128 value", amp_none, NULL, NULL, 0},
139 {0x5053, 0x3357, "Turtle Beach Santa Cruz", amp_voyetra, NULL, NULL, 1},
140 {0x1071, 0x6003, "Mitac MI6020/21", amp_voyetra, NULL, NULL, 0},
141 {0x14AF, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0},
142 {0x1681, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0},
143 {0x1014, 0x0132, "Thinkpad 570", amp_none, NULL, NULL, 0},
144 {0x1014, 0x0153, "Thinkpad 600X/A20/T20", amp_none, NULL, clkrun_hack, 0},
145 {0x1014, 0x1010, "Thinkpad 600E (unsupported)", NULL, NULL, NULL, 0},
146 {0x153b, 0x1136, "Terratec SiXPack 5.1+", NULL, NULL, NULL, 0},
147 {0, 0, "Unknown/invalid SSID (CS4614)", NULL, NULL, NULL, 0},
148 };
149
150 static struct csa_card cards_4615[] = {
151 {0, 0, "Unknown/invalid SSID (CS4615)", NULL, NULL, NULL, 0},
152 };
153
154 static struct csa_card nocard = {0, 0, "unknown", NULL, NULL, NULL, 0};
155
156 struct card_type {
157 u_int32_t devid;
158 char *name;
159 struct csa_card *cards;
160 };
161
162 static struct card_type cards[] = {
163 {CS4610_PCI_ID, "CS4610/CS4611", cards_4610},
164 {CS4614_PCI_ID, "CS4280/CS4614/CS4622/CS4624/CS4630", cards_4614},
165 {CS4615_PCI_ID, "CS4615", cards_4615},
166 {0, NULL, NULL},
167 };
168
169 static struct card_type *
csa_findcard(device_t dev)170 csa_findcard(device_t dev)
171 {
172 int i;
173
174 i = 0;
175 while (cards[i].devid != 0) {
176 if (pci_get_devid(dev) == cards[i].devid)
177 return &cards[i];
178 i++;
179 }
180 return NULL;
181 }
182
183 struct csa_card *
csa_findsubcard(device_t dev)184 csa_findsubcard(device_t dev)
185 {
186 int i;
187 struct card_type *card;
188 struct csa_card *subcard;
189
190 card = csa_findcard(dev);
191 if (card == NULL)
192 return &nocard;
193 subcard = card->cards;
194 i = 0;
195 while (subcard[i].subvendor != 0) {
196 if (pci_get_subvendor(dev) == subcard[i].subvendor
197 && pci_get_subdevice(dev) == subcard[i].subdevice) {
198 return &subcard[i];
199 }
200 i++;
201 }
202 return &subcard[i];
203 }
204
205 static int
csa_probe(device_t dev)206 csa_probe(device_t dev)
207 {
208 struct card_type *card;
209
210 card = csa_findcard(dev);
211 if (card) {
212 device_set_desc(dev, card->name);
213 return BUS_PROBE_DEFAULT;
214 }
215 return ENXIO;
216 }
217
218 static int
csa_attach(device_t dev)219 csa_attach(device_t dev)
220 {
221 sc_p scp;
222 csa_res *resp;
223 struct sndcard_func *func;
224 int error = ENXIO;
225
226 scp = device_get_softc(dev);
227
228 /* Fill in the softc. */
229 bzero(scp, sizeof(*scp));
230 scp->dev = dev;
231
232 pci_enable_busmaster(dev);
233
234 /* Allocate the resources. */
235 resp = &scp->res;
236 scp->card = csa_findsubcard(dev);
237 scp->binfo.card = scp->card;
238 printf("csa: card is %s\n", scp->card->name);
239 resp->io_rid = PCIR_BAR(0);
240 resp->io = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
241 &resp->io_rid, RF_ACTIVE);
242 if (resp->io == NULL)
243 return (ENXIO);
244 resp->mem_rid = PCIR_BAR(1);
245 resp->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
246 &resp->mem_rid, RF_ACTIVE);
247 if (resp->mem == NULL)
248 goto err_io;
249 resp->irq_rid = 0;
250 resp->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
251 &resp->irq_rid, RF_ACTIVE | RF_SHAREABLE);
252 if (resp->irq == NULL)
253 goto err_mem;
254
255 /* Enable interrupt. */
256 if (snd_setup_intr(dev, resp->irq, 0, csa_intr, scp, &scp->ih))
257 goto err_intr;
258 #if 0
259 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0)
260 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
261 #endif
262
263 /* Initialize the chip. */
264 if (csa_initialize(scp))
265 goto err_teardown;
266
267 /* Reset the Processor. */
268 csa_resetdsp(resp);
269
270 /* Download the Processor Image to the processor. */
271 if (csa_downloadimage(resp))
272 goto err_teardown;
273
274 /* Attach the children. */
275
276 /* PCM Audio */
277 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_WAITOK | M_ZERO);
278 func->varinfo = &scp->binfo;
279 func->func = SCF_PCM;
280 scp->pcm = device_add_child(dev, "pcm", -1);
281 device_set_ivars(scp->pcm, func);
282
283 /* Midi Interface */
284 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_WAITOK | M_ZERO);
285 func->varinfo = &scp->binfo;
286 func->func = SCF_MIDI;
287 scp->midi = device_add_child(dev, "midi", -1);
288 device_set_ivars(scp->midi, func);
289
290 bus_generic_attach(dev);
291
292 return (0);
293
294 err_teardown:
295 bus_teardown_intr(dev, resp->irq, scp->ih);
296 err_intr:
297 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq);
298 err_mem:
299 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem);
300 err_io:
301 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io);
302 return (error);
303 }
304
305 static void
csa_child_deleted(device_t dev,device_t child)306 csa_child_deleted(device_t dev, device_t child)
307 {
308 free(device_get_ivars(child), M_DEVBUF);
309 }
310
311 static int
csa_detach(device_t dev)312 csa_detach(device_t dev)
313 {
314 csa_res *resp;
315 sc_p scp;
316 int err;
317
318 scp = device_get_softc(dev);
319 resp = &scp->res;
320
321 if (scp->midi != NULL) {
322 err = device_delete_child(dev, scp->midi);
323 if (err != 0)
324 return err;
325 scp->midi = NULL;
326 }
327
328 if (scp->pcm != NULL) {
329 err = device_delete_child(dev, scp->pcm);
330 if (err != 0)
331 return err;
332 scp->pcm = NULL;
333 }
334
335 bus_teardown_intr(dev, resp->irq, scp->ih);
336 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq);
337 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem);
338 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io);
339
340 return bus_generic_detach(dev);
341 }
342
343 static int
csa_resume(device_t dev)344 csa_resume(device_t dev)
345 {
346 csa_res *resp;
347 sc_p scp;
348
349 scp = device_get_softc(dev);
350 resp = &scp->res;
351
352 /* Initialize the chip. */
353 if (csa_initialize(scp))
354 return (ENXIO);
355
356 /* Reset the Processor. */
357 csa_resetdsp(resp);
358
359 /* Download the Processor Image to the processor. */
360 if (csa_downloadimage(resp))
361 return (ENXIO);
362
363 return (bus_generic_resume(dev));
364 }
365
366 static struct resource *
csa_alloc_resource(device_t bus,device_t child,int type,int * rid,rman_res_t start,rman_res_t end,rman_res_t count,u_int flags)367 csa_alloc_resource(device_t bus, device_t child, int type, int *rid,
368 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
369 {
370 sc_p scp;
371 csa_res *resp;
372 struct resource *res;
373
374 scp = device_get_softc(bus);
375 resp = &scp->res;
376 switch (type) {
377 case SYS_RES_IRQ:
378 if (*rid != 0)
379 return (NULL);
380 res = resp->irq;
381 break;
382 case SYS_RES_MEMORY:
383 switch (*rid) {
384 case PCIR_BAR(0):
385 res = resp->io;
386 break;
387 case PCIR_BAR(1):
388 res = resp->mem;
389 break;
390 default:
391 return (NULL);
392 }
393 break;
394 default:
395 return (NULL);
396 }
397
398 return res;
399 }
400
401 static int
csa_release_resource(device_t bus,device_t child,int type,int rid,struct resource * r)402 csa_release_resource(device_t bus, device_t child, int type, int rid,
403 struct resource *r)
404 {
405 return (0);
406 }
407
408 /*
409 * The following three functions deal with interrupt handling.
410 * An interrupt is primarily handled by the bridge driver.
411 * The bridge driver then determines the child devices to pass
412 * the interrupt. Certain information of the device can be read
413 * only once(eg the value of HISR). The bridge driver is responsible
414 * to pass such the information to the children.
415 */
416
417 static int
csa_setup_intr(device_t bus,device_t child,struct resource * irq,int flags,driver_filter_t * filter,driver_intr_t * intr,void * arg,void ** cookiep)418 csa_setup_intr(device_t bus, device_t child,
419 struct resource *irq, int flags,
420 driver_filter_t *filter,
421 driver_intr_t *intr, void *arg, void **cookiep)
422 {
423 sc_p scp;
424 csa_res *resp;
425 struct sndcard_func *func;
426
427 if (filter != NULL) {
428 printf("ata-csa.c: we cannot use a filter here\n");
429 return (EINVAL);
430 }
431 scp = device_get_softc(bus);
432 resp = &scp->res;
433
434 /*
435 * Look at the function code of the child to determine
436 * the appropriate handler for it.
437 */
438 func = device_get_ivars(child);
439 if (func == NULL || irq != resp->irq)
440 return (EINVAL);
441
442 switch (func->func) {
443 case SCF_PCM:
444 scp->pcmintr = intr;
445 scp->pcmintr_arg = arg;
446 break;
447
448 case SCF_MIDI:
449 scp->midiintr = intr;
450 scp->midiintr_arg = arg;
451 break;
452
453 default:
454 return (EINVAL);
455 }
456 *cookiep = scp;
457 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0)
458 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
459
460 return (0);
461 }
462
463 static int
csa_teardown_intr(device_t bus,device_t child,struct resource * irq,void * cookie)464 csa_teardown_intr(device_t bus, device_t child,
465 struct resource *irq, void *cookie)
466 {
467 sc_p scp;
468 csa_res *resp;
469 struct sndcard_func *func;
470
471 scp = device_get_softc(bus);
472 resp = &scp->res;
473
474 /*
475 * Look at the function code of the child to determine
476 * the appropriate handler for it.
477 */
478 func = device_get_ivars(child);
479 if (func == NULL || irq != resp->irq || cookie != scp)
480 return (EINVAL);
481
482 switch (func->func) {
483 case SCF_PCM:
484 scp->pcmintr = NULL;
485 scp->pcmintr_arg = NULL;
486 break;
487
488 case SCF_MIDI:
489 scp->midiintr = NULL;
490 scp->midiintr_arg = NULL;
491 break;
492
493 default:
494 return (EINVAL);
495 }
496
497 return (0);
498 }
499
500 /* The interrupt handler */
501 static void
csa_intr(void * arg)502 csa_intr(void *arg)
503 {
504 sc_p scp = arg;
505 csa_res *resp;
506 u_int32_t hisr;
507
508 resp = &scp->res;
509
510 /* Is this interrupt for us? */
511 hisr = csa_readio(resp, BA0_HISR);
512 if ((hisr & 0x7fffffff) == 0) {
513 /* Throw an eoi. */
514 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
515 return;
516 }
517
518 /*
519 * Pass the value of HISR via struct csa_bridgeinfo.
520 * The children get access through their ivars.
521 */
522 scp->binfo.hisr = hisr;
523
524 /* Invoke the handlers of the children. */
525 if ((hisr & (HISR_VC0 | HISR_VC1)) != 0 && scp->pcmintr != NULL) {
526 scp->pcmintr(scp->pcmintr_arg);
527 hisr &= ~(HISR_VC0 | HISR_VC1);
528 }
529 if ((hisr & HISR_MIDI) != 0 && scp->midiintr != NULL) {
530 scp->midiintr(scp->midiintr_arg);
531 hisr &= ~HISR_MIDI;
532 }
533
534 /* Throw an eoi. */
535 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
536 }
537
538 static int
csa_initialize(sc_p scp)539 csa_initialize(sc_p scp)
540 {
541 int i;
542 u_int32_t acsts, acisv;
543 csa_res *resp;
544
545 resp = &scp->res;
546
547 /*
548 * First, blast the clock control register to zero so that the PLL starts
549 * out in a known state, and blast the master serial port control register
550 * to zero so that the serial ports also start out in a known state.
551 */
552 csa_writeio(resp, BA0_CLKCR1, 0);
553 csa_writeio(resp, BA0_SERMC1, 0);
554
555 /*
556 * If we are in AC97 mode, then we must set the part to a host controlled
557 * AC-link. Otherwise, we won't be able to bring up the link.
558 */
559 #if 1
560 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_1_03); /* 1.03 codec */
561 #else
562 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_2_0); /* 2.0 codec */
563 #endif /* 1 */
564
565 /*
566 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
567 * spec) and then drive it high. This is done for non AC97 modes since
568 * there might be logic external to the CS461x that uses the ARST# line
569 * for a reset.
570 */
571 csa_writeio(resp, BA0_ACCTL, 1);
572 DELAY(50);
573 csa_writeio(resp, BA0_ACCTL, 0);
574 DELAY(50);
575 csa_writeio(resp, BA0_ACCTL, ACCTL_RSTN);
576
577 /*
578 * The first thing we do here is to enable sync generation. As soon
579 * as we start receiving bit clock, we'll start producing the SYNC
580 * signal.
581 */
582 csa_writeio(resp, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
583
584 /*
585 * Now wait for a short while to allow the AC97 part to start
586 * generating bit clock (so we don't try to start the PLL without an
587 * input clock).
588 */
589 DELAY(50000);
590
591 /*
592 * Set the serial port timing configuration, so that
593 * the clock control circuit gets its clock from the correct place.
594 */
595 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97);
596 DELAY(700000);
597
598 /*
599 * Write the selected clock control setup to the hardware. Do not turn on
600 * SWCE yet (if requested), so that the devices clocked by the output of
601 * PLL are not clocked until the PLL is stable.
602 */
603 csa_writeio(resp, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ);
604 csa_writeio(resp, BA0_PLLM, 0x3a);
605 csa_writeio(resp, BA0_CLKCR2, CLKCR2_PDIVS_8);
606
607 /*
608 * Power up the PLL.
609 */
610 csa_writeio(resp, BA0_CLKCR1, CLKCR1_PLLP);
611
612 /*
613 * Wait until the PLL has stabilized.
614 */
615 DELAY(5000);
616
617 /*
618 * Turn on clocking of the core so that we can setup the serial ports.
619 */
620 csa_writeio(resp, BA0_CLKCR1, csa_readio(resp, BA0_CLKCR1) | CLKCR1_SWCE);
621
622 /*
623 * Fill the serial port FIFOs with silence.
624 */
625 csa_clearserialfifos(resp);
626
627 /*
628 * Set the serial port FIFO pointer to the first sample in the FIFO.
629 */
630 #ifdef notdef
631 csa_writeio(resp, BA0_SERBSP, 0);
632 #endif /* notdef */
633
634 /*
635 * Write the serial port configuration to the part. The master
636 * enable bit is not set until all other values have been written.
637 */
638 csa_writeio(resp, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN);
639 csa_writeio(resp, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN);
640 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE);
641
642 /*
643 * Wait for the codec ready signal from the AC97 codec.
644 */
645 acsts = 0;
646 for (i = 0 ; i < 1000 ; i++) {
647 /*
648 * First, lets wait a short while to let things settle out a bit,
649 * and to prevent retrying the read too quickly.
650 */
651 DELAY(125);
652
653 /*
654 * Read the AC97 status register to see if we've seen a CODEC READY
655 * signal from the AC97 codec.
656 */
657 acsts = csa_readio(resp, BA0_ACSTS);
658 if ((acsts & ACSTS_CRDY) != 0)
659 break;
660 }
661
662 /*
663 * Make sure we sampled CODEC READY.
664 */
665 if ((acsts & ACSTS_CRDY) == 0)
666 return (ENXIO);
667
668 /*
669 * Assert the vaid frame signal so that we can start sending commands
670 * to the AC97 codec.
671 */
672 csa_writeio(resp, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
673
674 /*
675 * Wait until we've sampled input slots 3 and 4 as valid, meaning that
676 * the codec is pumping ADC data across the AC-link.
677 */
678 acisv = 0;
679 for (i = 0 ; i < 2000 ; i++) {
680 /*
681 * First, lets wait a short while to let things settle out a bit,
682 * and to prevent retrying the read too quickly.
683 */
684 #ifdef notdef
685 DELAY(10000000L); /* clw */
686 #else
687 DELAY(1000);
688 #endif /* notdef */
689 /*
690 * Read the input slot valid register and see if input slots 3 and
691 * 4 are valid yet.
692 */
693 acisv = csa_readio(resp, BA0_ACISV);
694 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4))
695 break;
696 }
697 /*
698 * Make sure we sampled valid input slots 3 and 4. If not, then return
699 * an error.
700 */
701 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) != (ACISV_ISV3 | ACISV_ISV4))
702 return (ENXIO);
703
704 /*
705 * Now, assert valid frame and the slot 3 and 4 valid bits. This will
706 * commense the transfer of digital audio data to the AC97 codec.
707 */
708 csa_writeio(resp, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4);
709
710 /*
711 * Power down the DAC and ADC. We will power them up (if) when we need
712 * them.
713 */
714 #ifdef notdef
715 csa_writeio(resp, BA0_AC97_POWERDOWN, 0x300);
716 #endif /* notdef */
717
718 /*
719 * Turn off the Processor by turning off the software clock enable flag in
720 * the clock control register.
721 */
722 #ifdef notdef
723 clkcr1 = csa_readio(resp, BA0_CLKCR1) & ~CLKCR1_SWCE;
724 csa_writeio(resp, BA0_CLKCR1, clkcr1);
725 #endif /* notdef */
726
727 /*
728 * Enable interrupts on the part.
729 */
730 #if 0
731 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
732 #endif /* notdef */
733
734 return (0);
735 }
736
737 void
csa_clearserialfifos(csa_res * resp)738 csa_clearserialfifos(csa_res *resp)
739 {
740 int i, j, pwr;
741 u_int8_t clkcr1, serbst;
742
743 /*
744 * See if the devices are powered down. If so, we must power them up first
745 * or they will not respond.
746 */
747 pwr = 1;
748 clkcr1 = csa_readio(resp, BA0_CLKCR1);
749 if ((clkcr1 & CLKCR1_SWCE) == 0) {
750 csa_writeio(resp, BA0_CLKCR1, clkcr1 | CLKCR1_SWCE);
751 pwr = 0;
752 }
753
754 /*
755 * We want to clear out the serial port FIFOs so we don't end up playing
756 * whatever random garbage happens to be in them. We fill the sample FIFOs
757 * with zero (silence).
758 */
759 csa_writeio(resp, BA0_SERBWP, 0);
760
761 /* Fill all 256 sample FIFO locations. */
762 serbst = 0;
763 for (i = 0 ; i < 256 ; i++) {
764 /* Make sure the previous FIFO write operation has completed. */
765 for (j = 0 ; j < 5 ; j++) {
766 DELAY(100);
767 serbst = csa_readio(resp, BA0_SERBST);
768 if ((serbst & SERBST_WBSY) == 0)
769 break;
770 }
771 if ((serbst & SERBST_WBSY) != 0) {
772 if (!pwr)
773 csa_writeio(resp, BA0_CLKCR1, clkcr1);
774 }
775 /* Write the serial port FIFO index. */
776 csa_writeio(resp, BA0_SERBAD, i);
777 /* Tell the serial port to load the new value into the FIFO location. */
778 csa_writeio(resp, BA0_SERBCM, SERBCM_WRC);
779 }
780 /*
781 * Now, if we powered up the devices, then power them back down again.
782 * This is kinda ugly, but should never happen.
783 */
784 if (!pwr)
785 csa_writeio(resp, BA0_CLKCR1, clkcr1);
786 }
787
788 void
csa_resetdsp(csa_res * resp)789 csa_resetdsp(csa_res *resp)
790 {
791 int i;
792
793 /*
794 * Write the reset bit of the SP control register.
795 */
796 csa_writemem(resp, BA1_SPCR, SPCR_RSTSP);
797
798 /*
799 * Write the control register.
800 */
801 csa_writemem(resp, BA1_SPCR, SPCR_DRQEN);
802
803 /*
804 * Clear the trap registers.
805 */
806 for (i = 0 ; i < 8 ; i++) {
807 csa_writemem(resp, BA1_DREG, DREG_REGID_TRAP_SELECT + i);
808 csa_writemem(resp, BA1_TWPR, 0xffff);
809 }
810 csa_writemem(resp, BA1_DREG, 0);
811
812 /*
813 * Set the frame timer to reflect the number of cycles per frame.
814 */
815 csa_writemem(resp, BA1_FRMT, 0xadf);
816 }
817
818 static int
csa_downloadimage(csa_res * resp)819 csa_downloadimage(csa_res *resp)
820 {
821 int ret;
822 u_long ul, offset;
823
824 for (ul = 0, offset = 0 ; ul < INKY_MEMORY_COUNT ; ul++) {
825 /*
826 * DMA this block from host memory to the appropriate
827 * memory on the CSDevice.
828 */
829 ret = csa_transferimage(resp,
830 cs461x_firmware.BA1Array + offset,
831 cs461x_firmware.MemoryStat[ul].ulDestAddr,
832 cs461x_firmware.MemoryStat[ul].ulSourceSize);
833 if (ret)
834 return (ret);
835 offset += cs461x_firmware.MemoryStat[ul].ulSourceSize >> 2;
836 }
837 return (0);
838 }
839
840 static int
csa_transferimage(csa_res * resp,u_int32_t * src,u_long dest,u_long len)841 csa_transferimage(csa_res *resp, u_int32_t *src, u_long dest, u_long len)
842 {
843 u_long ul;
844
845 /*
846 * We do not allow DMAs from host memory to host memory (although the DMA
847 * can do it) and we do not allow DMAs which are not a multiple of 4 bytes
848 * in size (because that DMA can not do that). Return an error if either
849 * of these conditions exist.
850 */
851 if ((len & 0x3) != 0)
852 return (EINVAL);
853
854 /* Check the destination address that it is a multiple of 4 */
855 if ((dest & 0x3) != 0)
856 return (EINVAL);
857
858 /* Write the buffer out. */
859 for (ul = 0 ; ul < len ; ul += 4)
860 csa_writemem(resp, dest + ul, src[ul >> 2]);
861 return (0);
862 }
863
864 int
csa_readcodec(csa_res * resp,u_long offset,u_int32_t * data)865 csa_readcodec(csa_res *resp, u_long offset, u_int32_t *data)
866 {
867 int i;
868 u_int32_t acctl, acsts;
869
870 /*
871 * Make sure that there is not data sitting around from a previous
872 * uncompleted access. ACSDA = Status Data Register = 47Ch
873 */
874 csa_readio(resp, BA0_ACSDA);
875
876 /*
877 * Setup the AC97 control registers on the CS461x to send the
878 * appropriate command to the AC97 to perform the read.
879 * ACCAD = Command Address Register = 46Ch
880 * ACCDA = Command Data Register = 470h
881 * ACCTL = Control Register = 460h
882 * set DCV - will clear when process completed
883 * set CRW - Read command
884 * set VFRM - valid frame enabled
885 * set ESYN - ASYNC generation enabled
886 * set RSTN - ARST# inactive, AC97 codec not reset
887 */
888
889 /*
890 * Get the actual AC97 register from the offset
891 */
892 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET);
893 csa_writeio(resp, BA0_ACCDA, 0);
894 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
895
896 /*
897 * Wait for the read to occur.
898 */
899 acctl = 0;
900 for (i = 0 ; i < 10 ; i++) {
901 /*
902 * First, we want to wait for a short time.
903 */
904 DELAY(25);
905
906 /*
907 * Now, check to see if the read has completed.
908 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
909 */
910 acctl = csa_readio(resp, BA0_ACCTL);
911 if ((acctl & ACCTL_DCV) == 0)
912 break;
913 }
914
915 /*
916 * Make sure the read completed.
917 */
918 if ((acctl & ACCTL_DCV) != 0)
919 return (EAGAIN);
920
921 /*
922 * Wait for the valid status bit to go active.
923 */
924 acsts = 0;
925 for (i = 0 ; i < 10 ; i++) {
926 /*
927 * Read the AC97 status register.
928 * ACSTS = Status Register = 464h
929 */
930 acsts = csa_readio(resp, BA0_ACSTS);
931 /*
932 * See if we have valid status.
933 * VSTS - Valid Status
934 */
935 if ((acsts & ACSTS_VSTS) != 0)
936 break;
937 /*
938 * Wait for a short while.
939 */
940 DELAY(25);
941 }
942
943 /*
944 * Make sure we got valid status.
945 */
946 if ((acsts & ACSTS_VSTS) == 0)
947 return (EAGAIN);
948
949 /*
950 * Read the data returned from the AC97 register.
951 * ACSDA = Status Data Register = 474h
952 */
953 *data = csa_readio(resp, BA0_ACSDA);
954
955 return (0);
956 }
957
958 int
csa_writecodec(csa_res * resp,u_long offset,u_int32_t data)959 csa_writecodec(csa_res *resp, u_long offset, u_int32_t data)
960 {
961 int i;
962 u_int32_t acctl;
963
964 /*
965 * Setup the AC97 control registers on the CS461x to send the
966 * appropriate command to the AC97 to perform the write.
967 * ACCAD = Command Address Register = 46Ch
968 * ACCDA = Command Data Register = 470h
969 * ACCTL = Control Register = 460h
970 * set DCV - will clear when process completed
971 * set VFRM - valid frame enabled
972 * set ESYN - ASYNC generation enabled
973 * set RSTN - ARST# inactive, AC97 codec not reset
974 */
975
976 /*
977 * Get the actual AC97 register from the offset
978 */
979 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET);
980 csa_writeio(resp, BA0_ACCDA, data);
981 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
982
983 /*
984 * Wait for the write to occur.
985 */
986 acctl = 0;
987 for (i = 0 ; i < 10 ; i++) {
988 /*
989 * First, we want to wait for a short time.
990 */
991 DELAY(25);
992
993 /*
994 * Now, check to see if the read has completed.
995 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
996 */
997 acctl = csa_readio(resp, BA0_ACCTL);
998 if ((acctl & ACCTL_DCV) == 0)
999 break;
1000 }
1001
1002 /*
1003 * Make sure the write completed.
1004 */
1005 if ((acctl & ACCTL_DCV) != 0)
1006 return (EAGAIN);
1007
1008 return (0);
1009 }
1010
1011 u_int32_t
csa_readio(csa_res * resp,u_long offset)1012 csa_readio(csa_res *resp, u_long offset)
1013 {
1014 u_int32_t ul;
1015
1016 if (offset < BA0_AC97_RESET)
1017 return bus_space_read_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset) & 0xffffffff;
1018 else {
1019 if (csa_readcodec(resp, offset, &ul))
1020 ul = 0;
1021 return (ul);
1022 }
1023 }
1024
1025 void
csa_writeio(csa_res * resp,u_long offset,u_int32_t data)1026 csa_writeio(csa_res *resp, u_long offset, u_int32_t data)
1027 {
1028 if (offset < BA0_AC97_RESET)
1029 bus_space_write_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset, data);
1030 else
1031 csa_writecodec(resp, offset, data);
1032 }
1033
1034 u_int32_t
csa_readmem(csa_res * resp,u_long offset)1035 csa_readmem(csa_res *resp, u_long offset)
1036 {
1037 return bus_space_read_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset);
1038 }
1039
1040 void
csa_writemem(csa_res * resp,u_long offset,u_int32_t data)1041 csa_writemem(csa_res *resp, u_long offset, u_int32_t data)
1042 {
1043 bus_space_write_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset, data);
1044 }
1045
1046 static device_method_t csa_methods[] = {
1047 /* Device interface */
1048 DEVMETHOD(device_probe, csa_probe),
1049 DEVMETHOD(device_attach, csa_attach),
1050 DEVMETHOD(device_detach, csa_detach),
1051 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1052 DEVMETHOD(device_suspend, bus_generic_suspend),
1053 DEVMETHOD(device_resume, csa_resume),
1054
1055 /* Bus interface */
1056 DEVMETHOD(bus_child_deleted, csa_child_deleted),
1057 DEVMETHOD(bus_alloc_resource, csa_alloc_resource),
1058 DEVMETHOD(bus_release_resource, csa_release_resource),
1059 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
1060 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
1061 DEVMETHOD(bus_setup_intr, csa_setup_intr),
1062 DEVMETHOD(bus_teardown_intr, csa_teardown_intr),
1063
1064 DEVMETHOD_END
1065 };
1066
1067 static driver_t csa_driver = {
1068 "csa",
1069 csa_methods,
1070 sizeof(struct csa_softc),
1071 };
1072
1073 /*
1074 * csa can be attached to a pci bus.
1075 */
1076 DRIVER_MODULE(snd_csa, pci, csa_driver, 0, 0);
1077 MODULE_DEPEND(snd_csa, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
1078 MODULE_VERSION(snd_csa, 1);
1079