1 /*-
2 * Copyright 2014 Svatopluk Kraus <onwahe@gmail.com>
3 * Copyright 2014 Michal Meloun <meloun@miracle.cz>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
30
31 #include <sys/param.h>
32 #include <sys/systm.h>
33
34 #include <machine/cpuinfo.h>
35 #include <machine/cpu-v6.h>
36
37 struct cpuinfo cpuinfo =
38 {
39 /* Use safe defaults for start */
40 .dcache_line_size = 32,
41 .dcache_line_mask = 31,
42 .icache_line_size = 32,
43 .icache_line_mask = 31,
44 };
45
46 /* Read and parse CPU id scheme */
47 void
cpuinfo_init(void)48 cpuinfo_init(void)
49 {
50
51 cpuinfo.midr = cp15_midr_get();
52 /* Test old version id schemes first */
53 if ((cpuinfo.midr & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_ARM_LTD) {
54 if (CPU_ID_ISOLD(cpuinfo.midr)) {
55 /* obsolete ARMv2 or ARMv3 CPU */
56 cpuinfo.midr = 0;
57 return;
58 }
59 if (CPU_ID_IS7(cpuinfo.midr)) {
60 if ((cpuinfo.midr & (1 << 23)) == 0) {
61 /* obsolete ARMv3 CPU */
62 cpuinfo.midr = 0;
63 return;
64 }
65 /* ARMv4T CPU */
66 cpuinfo.architecture = 1;
67 cpuinfo.revision = (cpuinfo.midr >> 16) & 0x7F;
68 } else {
69 /* ARM new id scheme */
70 cpuinfo.architecture = (cpuinfo.midr >> 16) & 0x0F;
71 cpuinfo.revision = (cpuinfo.midr >> 20) & 0x0F;
72 }
73 } else {
74 /* non ARM -> must be new id scheme */
75 cpuinfo.architecture = (cpuinfo.midr >> 16) & 0x0F;
76 cpuinfo.revision = (cpuinfo.midr >> 20) & 0x0F;
77 }
78 /* Parse rest of MIDR */
79 cpuinfo.implementer = (cpuinfo.midr >> 24) & 0xFF;
80 cpuinfo.part_number = (cpuinfo.midr >> 4) & 0xFFF;
81 cpuinfo.patch = cpuinfo.midr & 0x0F;
82
83 /* CP15 c0,c0 regs 0-7 exist on all CPUs (although aliased with MIDR) */
84 cpuinfo.ctr = cp15_ctr_get();
85 cpuinfo.tcmtr = cp15_tcmtr_get();
86 cpuinfo.tlbtr = cp15_tlbtr_get();
87 cpuinfo.mpidr = cp15_mpidr_get();
88 cpuinfo.revidr = cp15_revidr_get();
89
90 /* if CPU is not v7 cpu id scheme */
91 if (cpuinfo.architecture != 0xF)
92 return;
93
94 cpuinfo.id_pfr0 = cp15_id_pfr0_get();
95 cpuinfo.id_pfr1 = cp15_id_pfr1_get();
96 cpuinfo.id_dfr0 = cp15_id_dfr0_get();
97 cpuinfo.id_afr0 = cp15_id_afr0_get();
98 cpuinfo.id_mmfr0 = cp15_id_mmfr0_get();
99 cpuinfo.id_mmfr1 = cp15_id_mmfr1_get();
100 cpuinfo.id_mmfr2 = cp15_id_mmfr2_get();
101 cpuinfo.id_mmfr3 = cp15_id_mmfr3_get();
102 cpuinfo.id_isar0 = cp15_id_isar0_get();
103 cpuinfo.id_isar1 = cp15_id_isar1_get();
104 cpuinfo.id_isar2 = cp15_id_isar2_get();
105 cpuinfo.id_isar3 = cp15_id_isar3_get();
106 cpuinfo.id_isar4 = cp15_id_isar4_get();
107 cpuinfo.id_isar5 = cp15_id_isar5_get();
108
109 /* Not yet - CBAR only exist on ARM SMP Cortex A CPUs
110 cpuinfo.cbar = cp15_cbar_get();
111 */
112
113 /* Test if revidr is implemented */
114 if (cpuinfo.revidr == cpuinfo.midr)
115 cpuinfo.revidr = 0;
116
117 /* parsed bits of above registers */
118 /* id_mmfr0 */
119 cpuinfo.outermost_shareability = (cpuinfo.id_mmfr0 >> 8) & 0xF;
120 cpuinfo.shareability_levels = (cpuinfo.id_mmfr0 >> 12) & 0xF;
121 cpuinfo.auxiliary_registers = (cpuinfo.id_mmfr0 >> 20) & 0xF;
122 cpuinfo.innermost_shareability = (cpuinfo.id_mmfr0 >> 28) & 0xF;
123 /* id_mmfr2 */
124 cpuinfo.mem_barrier = (cpuinfo.id_mmfr2 >> 20) & 0xF;
125 /* id_mmfr3 */
126 cpuinfo.coherent_walk = (cpuinfo.id_mmfr3 >> 20) & 0xF;
127 cpuinfo.maintenance_broadcast =(cpuinfo.id_mmfr3 >> 12) & 0xF;
128 /* id_pfr1 */
129 cpuinfo.generic_timer_ext = (cpuinfo.id_pfr1 >> 16) & 0xF;
130 cpuinfo.virtualization_ext = (cpuinfo.id_pfr1 >> 12) & 0xF;
131 cpuinfo.security_ext = (cpuinfo.id_pfr1 >> 4) & 0xF;
132
133 /* L1 Cache sizes */
134 if (CPU_CT_FORMAT(cpuinfo.ctr) == CPU_CT_ARMV7) {
135 cpuinfo.dcache_line_size =
136 1 << (CPU_CT_DMINLINE(cpuinfo.ctr) + 2);
137 cpuinfo.icache_line_size =
138 1 << (CPU_CT_IMINLINE(cpuinfo.ctr) + 2);
139 } else {
140 cpuinfo.dcache_line_size =
141 1 << (CPU_CT_xSIZE_LEN(CPU_CT_DSIZE(cpuinfo.ctr)) + 3);
142 cpuinfo.icache_line_size =
143 1 << (CPU_CT_xSIZE_LEN(CPU_CT_ISIZE(cpuinfo.ctr)) + 3);
144 }
145 cpuinfo.dcache_line_mask = cpuinfo.dcache_line_size - 1;
146 cpuinfo.icache_line_mask = cpuinfo.icache_line_size - 1;
147 }
148
149 /*
150 * Get bits that must be set or cleared in ACLR register.
151 * Note: Bits in ACLR register are IMPLEMENTATION DEFINED.
152 * Its expected that SCU is in operational state before this
153 * function is called.
154 */
155 void
cpuinfo_get_actlr_modifier(uint32_t * actlr_mask,uint32_t * actlr_set)156 cpuinfo_get_actlr_modifier(uint32_t *actlr_mask, uint32_t *actlr_set)
157 {
158 *actlr_mask = 0;
159 *actlr_set = 0;
160
161 if (cpuinfo.implementer == CPU_IMPLEMENTER_ARM) {
162 switch (cpuinfo.part_number) {
163
164 case CPU_ARCH_CORTEX_A17:
165 case CPU_ARCH_CORTEX_A12: /* A12 is merged to A17 */
166 /*
167 * Enable SMP mode
168 */
169 *actlr_mask = (1 << 6);
170 *actlr_set = (1 << 6);
171 break;
172 case CPU_ARCH_CORTEX_A15:
173 /*
174 * Enable snoop-delayed exclusive handling
175 * Enable SMP mode
176 */
177 *actlr_mask = (1U << 31) |(1 << 6);
178 *actlr_set = (1U << 31) |(1 << 6);
179 break;
180 case CPU_ARCH_CORTEX_A9:
181 /*
182 * Disable exclusive L1/L2 cache control
183 * Enable SMP mode
184 * Enable Cache and TLB maintenance broadcast
185 */
186 *actlr_mask = (1 << 7) | (1 << 6) | (1 << 0);
187 *actlr_set = (1 << 6) | (1 << 0);
188 break;
189 case CPU_ARCH_CORTEX_A8:
190 /*
191 * Enable L2 cache
192 * Enable L1 data cache hardware alias checks
193 */
194 *actlr_mask = (1 << 1) | (1 << 0);
195 *actlr_set = (1 << 1);
196 break;
197 case CPU_ARCH_CORTEX_A7:
198 /*
199 * Enable SMP mode
200 */
201 *actlr_mask = (1 << 6);
202 *actlr_set = (1 << 6);
203 break;
204 case CPU_ARCH_CORTEX_A5:
205 /*
206 * Disable exclusive L1/L2 cache control
207 * Enable SMP mode
208 * Enable Cache and TLB maintenance broadcast
209 */
210 *actlr_mask = (1 << 7) | (1 << 6) | (1 << 0);
211 *actlr_set = (1 << 6) | (1 << 0);
212 break;
213 case CPU_ARCH_ARM1176:
214 /*
215 * Restrict cache size to 16KB
216 * Enable the return stack
217 * Enable dynamic branch prediction
218 * Enable static branch prediction
219 */
220 *actlr_mask = (1 << 6) | (1 << 2) | (1 << 1) | (1 << 0);
221 *actlr_set = (1 << 6) | (1 << 2) | (1 << 1) | (1 << 0);
222 break;
223 }
224 return;
225 }
226 }
227