1 /*-
2 * Copyright (c) KATO Takenori, 1997, 1998.
3 *
4 * All rights reserved. Unpublished rights reserved under the copyright
5 * laws of Japan.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer as
13 * the first lines of this file unmodified.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD: stable/9/sys/amd64/amd64/initcpu.c 304132 2016-08-15 09:06:33Z avg $");
32
33 #include "opt_cpu.h"
34
35 #include <sys/param.h>
36 #include <sys/kernel.h>
37 #include <sys/pcpu.h>
38 #include <sys/systm.h>
39 #include <sys/sysctl.h>
40
41 #include <machine/cputypes.h>
42 #include <machine/md_var.h>
43 #include <machine/specialreg.h>
44
45 #include <vm/vm.h>
46 #include <vm/pmap.h>
47
48 static int hw_instruction_sse;
49 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
50 &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU");
51 /*
52 * -1: automatic (default)
53 * 0: keep enable CLFLUSH
54 * 1: force disable CLFLUSH
55 */
56 static int hw_clflush_disable = -1;
57
58 int cpu; /* Are we 386, 386sx, 486, etc? */
59 u_int cpu_feature; /* Feature flags */
60 u_int cpu_feature2; /* Feature flags */
61 u_int amd_feature; /* AMD feature flags */
62 u_int amd_feature2; /* AMD feature flags */
63 u_int amd_pminfo; /* AMD advanced power management info */
64 u_int via_feature_rng; /* VIA RNG features */
65 u_int via_feature_xcrypt; /* VIA ACE features */
66 u_int cpu_high; /* Highest arg to CPUID */
67 u_int cpu_exthigh; /* Highest arg to extended CPUID */
68 u_int cpu_id; /* Stepping ID */
69 u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */
70 u_int cpu_procinfo2; /* Multicore info */
71 char cpu_vendor[20]; /* CPU Origin code */
72 u_int cpu_vendor_id; /* CPU vendor ID */
73 u_int cpu_fxsr; /* SSE enabled */
74 u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */
75 u_int cpu_clflush_line_size = 32;
76 u_int cpu_stdext_feature;
77 u_int cpu_max_ext_state_size;
78
79 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
80 &via_feature_rng, 0, "VIA RNG feature available in CPU");
81 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
82 &via_feature_xcrypt, 0, "VIA xcrypt feature available in CPU");
83
84 static void
init_amd(void)85 init_amd(void)
86 {
87 uint64_t msr;
88
89 /*
90 * Work around Erratum 721 for Family 10h and 12h processors.
91 * These processors may incorrectly update the stack pointer
92 * after a long series of push and/or near-call instructions,
93 * or a long series of pop and/or near-return instructions.
94 *
95 * http://support.amd.com/us/Processor_TechDocs/41322_10h_Rev_Gd.pdf
96 * http://support.amd.com/us/Processor_TechDocs/44739_12h_Rev_Gd.pdf
97 *
98 * Hypervisors do not provide access to the errata MSR,
99 * causing #GP exception on attempt to apply the errata. The
100 * MSR write shall be done on host and persist globally
101 * anyway, so do not try to do it when under virtualization.
102 */
103 switch (CPUID_TO_FAMILY(cpu_id)) {
104 case 0x10:
105 case 0x12:
106 if ((cpu_feature2 & CPUID2_HV) == 0)
107 wrmsr(0xc0011029, rdmsr(0xc0011029) | 1);
108 break;
109 }
110
111 /*
112 * BIOS may fail to set InitApicIdCpuIdLo to 1 as it should per BKDG.
113 * So, do it here or otherwise some tools could be confused by
114 * Initial Local APIC ID reported with CPUID Function 1 in EBX.
115 */
116 if (CPUID_TO_FAMILY(cpu_id) == 0x10) {
117 if ((cpu_feature2 & CPUID2_HV) == 0) {
118 msr = rdmsr(MSR_NB_CFG1);
119 msr |= (uint64_t)1 << 54;
120 wrmsr(MSR_NB_CFG1, msr);
121 }
122 }
123
124 /*
125 * BIOS may configure Family 10h processors to convert WC+ cache type
126 * to CD. That can hurt performance of guest VMs using nested paging.
127 * The relevant MSR bit is not documented in the BKDG,
128 * the fix is borrowed from Linux.
129 */
130 if (CPUID_TO_FAMILY(cpu_id) == 0x10) {
131 if ((cpu_feature2 & CPUID2_HV) == 0) {
132 msr = rdmsr(0xc001102a);
133 msr &= ~((uint64_t)1 << 24);
134 wrmsr(0xc001102a, msr);
135 }
136 }
137 }
138
139 /*
140 * Initialize special VIA features
141 */
142 static void
init_via(void)143 init_via(void)
144 {
145 u_int regs[4], val;
146
147 /*
148 * Check extended CPUID for PadLock features.
149 *
150 * http://www.via.com.tw/en/downloads/whitepapers/initiatives/padlock/programming_guide.pdf
151 */
152 do_cpuid(0xc0000000, regs);
153 if (regs[0] >= 0xc0000001) {
154 do_cpuid(0xc0000001, regs);
155 val = regs[3];
156 } else
157 return;
158
159 /* Enable RNG if present. */
160 if ((val & VIA_CPUID_HAS_RNG) != 0) {
161 via_feature_rng = VIA_HAS_RNG;
162 wrmsr(0x110B, rdmsr(0x110B) | VIA_CPUID_DO_RNG);
163 }
164
165 /* Enable PadLock if present. */
166 if ((val & VIA_CPUID_HAS_ACE) != 0)
167 via_feature_xcrypt |= VIA_HAS_AES;
168 if ((val & VIA_CPUID_HAS_ACE2) != 0)
169 via_feature_xcrypt |= VIA_HAS_AESCTR;
170 if ((val & VIA_CPUID_HAS_PHE) != 0)
171 via_feature_xcrypt |= VIA_HAS_SHA;
172 if ((val & VIA_CPUID_HAS_PMM) != 0)
173 via_feature_xcrypt |= VIA_HAS_MM;
174 if (via_feature_xcrypt != 0)
175 wrmsr(0x1107, rdmsr(0x1107) | (1 << 28));
176 }
177
178 /*
179 * Initialize CPU control registers
180 */
181 void
initializecpu(void)182 initializecpu(void)
183 {
184 uint64_t msr;
185 uint32_t cr4;
186
187 cr4 = rcr4();
188 if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) {
189 cr4 |= CR4_FXSR | CR4_XMM;
190 cpu_fxsr = hw_instruction_sse = 1;
191 }
192 if (cpu_stdext_feature & CPUID_STDEXT_FSGSBASE)
193 cr4 |= CR4_FSGSBASE;
194
195 /*
196 * Postpone enabling the SMEP on the boot CPU until the page
197 * tables are switched from the boot loader identity mapping
198 * to the kernel tables. The boot loader enables the U bit in
199 * its tables.
200 */
201 if (!IS_BSP() && (cpu_stdext_feature & CPUID_STDEXT_SMEP))
202 cr4 |= CR4_SMEP;
203 load_cr4(cr4);
204 if ((amd_feature & AMDID_NX) != 0) {
205 msr = rdmsr(MSR_EFER) | EFER_NXE;
206 wrmsr(MSR_EFER, msr);
207 pg_nx = PG_NX;
208 }
209 switch (cpu_vendor_id) {
210 case CPU_VENDOR_AMD:
211 init_amd();
212 break;
213 case CPU_VENDOR_CENTAUR:
214 init_via();
215 break;
216 }
217 }
218
219 void
initializecpucache()220 initializecpucache()
221 {
222
223 /*
224 * CPUID with %eax = 1, %ebx returns
225 * Bits 15-8: CLFLUSH line size
226 * (Value * 8 = cache line size in bytes)
227 */
228 if ((cpu_feature & CPUID_CLFSH) != 0)
229 cpu_clflush_line_size = ((cpu_procinfo >> 8) & 0xff) * 8;
230 /*
231 * XXXKIB: (temporary) hack to work around traps generated
232 * when CLFLUSHing APIC register window under virtualization
233 * environments. These environments tend to disable the
234 * CPUID_SS feature even though the native CPU supports it.
235 */
236 TUNABLE_INT_FETCH("hw.clflush_disable", &hw_clflush_disable);
237 if (vm_guest != VM_GUEST_NO && hw_clflush_disable == -1)
238 cpu_feature &= ~CPUID_CLFSH;
239 /*
240 * Allow to disable CLFLUSH feature manually by
241 * hw.clflush_disable tunable.
242 */
243 if (hw_clflush_disable == 1)
244 cpu_feature &= ~CPUID_CLFSH;
245 }
246