1 /** $MirOS: src/sys/arch/i386/i386/machdep.c,v 1.25 2014/01/11 18:16:13 tg Exp $ */
2 /* $OpenBSD: machdep.c,v 1.310 2004/11/02 21:20:59 miod Exp $ */
3 /* $NetBSD: machdep.c,v 1.214 1996/11/10 03:16:17 thorpej Exp $ */
4
5 /*-
6 * Copyright (c) 1996, 1997 The NetBSD Foundation, Inc.
7 * All rights reserved.
8 *
9 * This code is derived from software contributed to The NetBSD Foundation
10 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
11 * NASA Ames Research Center.
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 * 3. All advertising materials mentioning features or use of this software
22 * must display the following acknowledgement:
23 * This product includes software developed by the NetBSD
24 * Foundation, Inc. and its contributors.
25 * 4. Neither the name of The NetBSD Foundation nor the names of its
26 * contributors may be used to endorse or promote products derived
27 * from this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
31 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
32 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
33 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
34 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
37 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
39 * POSSIBILITY OF SUCH DAMAGE.
40 */
41
42 /*-
43 * Copyright (c) 2010
44 * Thorsten Glaser <tg@mirbsd.org>
45 * Copyright (c) 1993, 1994, 1995, 1996 Charles M. Hannum. All rights reserved.
46 * Copyright (c) 1992 Terrence R. Lambert.
47 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
48 * All rights reserved.
49 *
50 * This code is derived from software contributed to Berkeley by
51 * William Jolitz.
52 *
53 * Redistribution and use in source and binary forms, with or without
54 * modification, are permitted provided that the following conditions
55 * are met:
56 * 1. Redistributions of source code must retain the above copyright
57 * notice, this list of conditions and the following disclaimer.
58 * 2. Redistributions in binary form must reproduce the above copyright
59 * notice, this list of conditions and the following disclaimer in the
60 * documentation and/or other materials provided with the distribution.
61 * 3. Neither the name of the University nor the names of its contributors
62 * may be used to endorse or promote products derived from this software
63 * without specific prior written permission.
64 *
65 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
66 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
67 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
68 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
69 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
70 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
71 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
72 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
73 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
74 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
75 * SUCH DAMAGE.
76 *
77 * @(#)machdep.c 7.4 (Berkeley) 6/3/91
78 */
79
80 #include <sys/param.h>
81 #include <sys/systm.h>
82 #include <sys/signalvar.h>
83 #include <sys/kernel.h>
84 #include <sys/proc.h>
85 #include <sys/user.h>
86 #include <sys/exec.h>
87 #include <sys/buf.h>
88 #include <sys/reboot.h>
89 #include <sys/conf.h>
90 #include <sys/file.h>
91 #include <sys/timeout.h>
92 #include <sys/malloc.h>
93 #include <sys/mbuf.h>
94 #include <sys/msgbuf.h>
95 #include <sys/mount.h>
96 #include <sys/vnode.h>
97 #include <sys/device.h>
98 #include <sys/extent.h>
99 #include <sys/sysctl.h>
100 #include <sys/syscallargs.h>
101 #include <sys/core.h>
102 #include <sys/kcore.h>
103 #ifdef SYSVMSG
104 #include <sys/msg.h>
105 #endif
106
107 #ifdef KGDB
108 #include <sys/kgdb.h>
109 #endif
110
111 #include <dev/cons.h>
112 #include <stand/boot/bootarg.h>
113
114 #include <uvm/uvm_extern.h>
115
116 #define _I386_BUS_DMA_PRIVATE
117 #include <machine/bus.h>
118
119 #include <machine/cpu.h>
120 #include <machine/cpufunc.h>
121 #include <machine/gdt.h>
122 #include <machine/pio.h>
123 #include <machine/bus.h>
124 #include <machine/psl.h>
125 #include <machine/reg.h>
126 #include <machine/specialreg.h>
127 #include <machine/biosvar.h>
128
129 #include <dev/rndvar.h>
130 #include <dev/isa/isareg.h>
131 #include <dev/isa/isavar.h>
132 #include <dev/ic/i8042reg.h>
133 #include <dev/ic/mc146818reg.h>
134 #include <i386/isa/isa_machdep.h>
135 #include <i386/isa/nvram.h>
136
137 #include "apm.h"
138 #if NAPM > 0
139 #include <machine/apmvar.h>
140 #endif
141
142 #ifdef DDB
143 #include <machine/db_machdep.h>
144 #include <ddb/db_access.h>
145 #include <ddb/db_sym.h>
146 #include <ddb/db_extern.h>
147 #endif
148
149 #ifdef VM86
150 #include <machine/vm86.h>
151 #endif
152
153 #include "isa.h"
154 #include "isadma.h"
155 #include "npx.h"
156 #if NNPX > 0
157 extern struct proc *npxproc;
158 #endif
159
160 #include "bios.h"
161 #include "com.h"
162 #include "pccom.h"
163
164 #if NPCCOM > 0
165 #include <sys/termios.h>
166 #include <dev/ic/comreg.h>
167 #if NCOM > 0
168 #include <dev/ic/comvar.h>
169 #elif NPCCOM > 0
170 #include <arch/i386/isa/pccomvar.h>
171 #endif
172 #endif /* NCOM > 0 || NPCCOM > 0 */
173
174 #ifndef SMALL_KERNEL
175 #include "powernowhack.h"
176 #endif
177
178 #if defined(_KERN_DO_ECOFF)
179 #include <sys/exec_ecoff.h>
180 #endif
181
182 /*
183 * The following defines are for the code in setup_buffers that tries to
184 * ensure that enough ISA DMAable memory is still left after the buffercache
185 * has been allocated.
186 */
187 #define CHUNKSZ (3 * 1024 * 1024)
188 #define ISADMA_LIMIT (16 * 1024 * 1024) /* XXX wrong place */
189 #define ALLOC_PGS(sz, limit, pgs) \
190 uvm_pglistalloc((sz), 0, (limit), PAGE_SIZE, 0, &(pgs), 1, 0)
191 #define FREE_PGS(pgs) uvm_pglistfree(&(pgs))
192
193 /* the following is used externally (sysctl_hw) */
194 char machine[] = "i386"; /* cpu "architecture" */
195
196 /*
197 * Declare these as initialized data so we can patch them.
198 */
199 #if NAPM > 0
200 int cpu_apmhalt = 0; /* sysctl'd to 1 for halt -p hack */
201 #endif
202
203 #ifdef USER_LDT
204 int user_ldt_enable = 1; /* sysctl'd to 0 to disable */
205 #endif
206
207 #ifdef NBUF
208 int nbuf = NBUF;
209 #else
210 int nbuf = 0;
211 #endif
212
213 #ifndef BUFCACHEPERCENT
214 #define BUFCACHEPERCENT 5
215 #endif
216
217 #ifdef BUFPAGES
218 int bufpages = BUFPAGES;
219 #else
220 int bufpages = 0;
221 #endif
222 int bufcachepercent = BUFCACHEPERCENT;
223
224 extern int boothowto;
225 int physmem;
226
227 struct dumpmem {
228 paddr_t start;
229 paddr_t end;
230 } dumpmem[VM_PHYSSEG_MAX];
231 u_int ndumpmem;
232
233 /*
234 * These variables are needed by /sbin/savecore
235 */
236 u_long dumpmag = 0x8fca0101; /* magic number */
237 int dumpsize = 0; /* pages */
238 long dumplo = 0; /* blocks */
239
240 int cpu_class;
241 int i386_fpu_present;
242 int i386_fpu_exception;
243 int i386_fpu_fdivbug;
244
245 int i386_use_fxsave;
246 int i386_has_sse;
247 int i386_has_sse2;
248 int i386_has_xcrypt;
249
250 bootarg_t *bootargp;
251 paddr_t avail_end;
252
253 struct vm_map *exec_map = NULL;
254 struct vm_map *phys_map = NULL;
255
256 int kbd_reset;
257 int p4_model;
258 int p3_step;
259 int setperf_prio = 0; /* for concurrent handlers */
260
261 void (*update_cpuspeed)(void) = NULL;
262
263 /*
264 * Extent maps to manage I/O and ISA memory hole space. Allocate
265 * storage for 8 regions in each, initially. Later, ioport_malloc_safe
266 * will indicate that it's safe to use malloc() to dynamically allocate
267 * region descriptors.
268 *
269 * N.B. At least two regions are _always_ allocated from the iomem
270 * extent map; (0 -> ISA hole) and (end of ISA hole -> end of RAM).
271 *
272 * The extent maps are not static! Machine-dependent ISA and EISA
273 * routines need access to them for bus address space allocation.
274 */
275 static long ioport_ex_storage[EXTENT_FIXED_STORAGE_SIZE(16) / sizeof(long)];
276 static long iomem_ex_storage[EXTENT_FIXED_STORAGE_SIZE(16) / sizeof(long)];
277 struct extent *ioport_ex;
278 struct extent *iomem_ex;
279 static int ioport_malloc_safe;
280
281 caddr_t allocsys(caddr_t);
282 void setup_buffers(vaddr_t *);
283 void dumpsys(void);
284 int cpu_dump(void);
285 void identifycpu(void);
286 void init386(paddr_t);
287 void consinit(void);
288 void (*cpuresetfn)(void);
289
290 int bus_mem_add_mapping(bus_addr_t, bus_size_t,
291 int, bus_space_handle_t *);
292 int _bus_dmamap_load_buffer(bus_dma_tag_t, bus_dmamap_t, void *,
293 bus_size_t, struct proc *, int, paddr_t *, int *, int);
294
295 #ifdef KGDB
296 #ifndef KGDB_DEVNAME
297 #ifdef __i386__
298 #define KGDB_DEVNAME "pccom"
299 #else
300 #define KGDB_DEVNAME "com"
301 #endif
302 #endif /* KGDB_DEVNAME */
303 char kgdb_devname[] = KGDB_DEVNAME;
304 #if (NCOM > 0 || NPCCOM > 0)
305 #ifndef KGDBADDR
306 #define KGDBADDR 0x3f8
307 #endif
308 int comkgdbaddr = KGDBADDR;
309 #ifndef KGDBRATE
310 #define KGDBRATE TTYDEF_SPEED
311 #endif
312 int comkgdbrate = KGDBRATE;
313 #ifndef KGDBMODE
314 #define KGDBMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */
315 #endif
316 int comkgdbmode = KGDBMODE;
317 #endif /* NCOM || NPCCOM */
318 void kgdb_port_init(void);
319 #endif /* KGDB */
320
321 #ifdef APERTURE
322 #ifdef INSECURE
323 int allowaperture = 1;
324 #else
325 int allowaperture = 0;
326 #endif
327 int aperture_vreset = 1;
328 #endif
329
330 void winchip_cpu_setup(const char *, int, int);
331 void amd_family5_setup(const char *, int, int);
332 void amd_family6_setup(const char *, int, int);
333 void cyrix3_cpu_setup(const char *, int, int);
334 void cyrix6x86_cpu_setup(const char *, int, int);
335 void natsem6x86_cpu_setup(const char *, int, int);
336 void intel586_cpu_setup(const char *, int, int);
337 void intel686_common_cpu_setup(const char *, int, int);
338 void intel686_cpu_setup(const char *, int, int);
339 void intel686_p4_cpu_setup(const char *, int, int);
340 void tm86_cpu_setup(const char *, int, int);
341 char * intel686_cpu_name(int);
342 char * cyrix3_cpu_name(int, int);
343 char * tm86_cpu_name(int);
344 void p4_update_cpuspeed(void);
345 void p3_update_cpuspeed(void);
346 int pentium_cpuspeed(int *);
347
348 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
349 static __inline u_char
cyrix_read_reg(u_char reg)350 cyrix_read_reg(u_char reg)
351 {
352 outb(0x22, reg);
353 return inb(0x23);
354 }
355
356 static __inline void
cyrix_write_reg(u_char reg,u_char data)357 cyrix_write_reg(u_char reg, u_char data)
358 {
359 outb(0x22, reg);
360 outb(0x23, data);
361 }
362 #endif
363
364 /*
365 * cpuid instruction. request in eax, result in eax, ebx, ecx, edx.
366 * requires caller to provide u_int32_t regs[4] array.
367 */
368 void
cpuid(u_int32_t ax,u_int32_t * regs)369 cpuid(u_int32_t ax, u_int32_t *regs)
370 {
371 __asm __volatile(
372 "cpuid\n\t"
373 "movl %%eax, 0(%2)\n\t"
374 "movl %%ebx, 4(%2)\n\t"
375 "movl %%ecx, 8(%2)\n\t"
376 "movl %%edx, 12(%2)\n\t"
377 :"=a" (ax)
378 :"0" (ax), "S" (regs)
379 :"bx", "cx", "dx");
380 }
381
382 /*
383 * Machine-dependent startup code
384 */
385 void
cpu_startup()386 cpu_startup()
387 {
388 unsigned i;
389 caddr_t v;
390 int sz;
391 vaddr_t minaddr, maxaddr, va;
392 paddr_t pa;
393
394 /*
395 * Initialize error message buffer (at end of core).
396 * (space reserved in pmap_bootstrap)
397 */
398 pa = avail_end;
399 va = (vaddr_t)msgbufp;
400 for (i = 0; i < btoc(MSGBUFSIZE); i++) {
401 pmap_kenter_pa(va, pa, VM_PROT_READ|VM_PROT_WRITE);
402 va += PAGE_SIZE;
403 pa += PAGE_SIZE;
404 }
405 pmap_update(pmap_kernel());
406 initmsgbuf((caddr_t)msgbufp, round_page(MSGBUFSIZE));
407
408 printf("%s", version);
409 startrtclock();
410
411 identifycpu();
412 printf("real mem = %u (%uK)\n", ctob(physmem), ctob(physmem)/1024U);
413
414 /*
415 * Find out how much space we need, allocate it,
416 * and then give everything true virtual addresses.
417 */
418 sz = (int)allocsys((caddr_t)0);
419 if ((v = (caddr_t)uvm_km_zalloc(kernel_map, round_page(sz))) == 0)
420 panic("startup: no room for tables");
421 if (allocsys(v) - v != sz)
422 panic("startup: table size inconsistency");
423
424 /*
425 * Now allocate buffers proper. They are different than the above
426 * in that they usually occupy more virtual memory than physical.
427 */
428 setup_buffers(&maxaddr);
429
430 /*
431 * Allocate a submap for exec arguments. This map effectively
432 * limits the number of processes exec'ing at any time.
433 */
434 exec_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr,
435 16*NCARGS, VM_MAP_PAGEABLE, FALSE, NULL);
436
437 /*
438 * Allocate a submap for physio
439 */
440 phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr,
441 VM_PHYS_SIZE, 0, FALSE, NULL);
442
443 printf("avail mem = %lu (%luK)\n", ptoa(uvmexp.free),
444 ptoa(uvmexp.free)/1024U);
445 printf("using %d buffers containing %u bytes (%uK) of memory\n",
446 nbuf, bufpages * PAGE_SIZE, bufpages * PAGE_SIZE / 1024U);
447
448 /*
449 * Set up buffers, so they can be used to read disk labels.
450 */
451 bufinit();
452
453 /*
454 * Configure the system.
455 */
456 if (boothowto & RB_CONFIG) {
457 #ifdef BOOT_CONFIG
458 user_config();
459 #else
460 printf("kernel does not support -c; continuing..\n");
461 #endif
462 }
463 ioport_malloc_safe = 1;
464 }
465
466 /*
467 * Set up proc0's TSS and LDT.
468 */
469 void
i386_proc0_tss_ldt_init()470 i386_proc0_tss_ldt_init()
471 {
472 struct pcb *pcb;
473 int x;
474
475 curpcb = pcb = &proc0.p_addr->u_pcb;
476 pcb->pcb_tss.tss_ioopt =
477 ((caddr_t)pcb->pcb_iomap - (caddr_t)&pcb->pcb_tss) << 16;
478 for (x = 0; x < sizeof(pcb->pcb_iomap) / 4; x++)
479 pcb->pcb_iomap[x] = 0xffffffff;
480 pcb->pcb_iomap_pad = 0xff;
481
482 pcb->pcb_ldt_sel = pmap_kernel()->pm_ldt_sel = GSEL(GLDT_SEL, SEL_KPL);
483 pcb->pcb_cr0 = rcr0();
484 pcb->pcb_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
485 pcb->pcb_tss.tss_esp0 = (int)proc0.p_addr + USPACE - 16;
486 tss_alloc(pcb);
487
488 ltr(pcb->pcb_tss_sel);
489 lldt(pcb->pcb_ldt_sel);
490
491 proc0.p_md.md_regs = (struct trapframe *)pcb->pcb_tss.tss_esp0 - 1;
492 }
493
494 /*
495 * Allocate space for system data structures. We are given
496 * a starting virtual address and we return a final virtual
497 * address; along the way we set each data structure pointer.
498 *
499 * We call allocsys() with 0 to find out how much space we want,
500 * allocate that much and fill it with zeroes, and then call
501 * allocsys() again with the correct base virtual address.
502 */
503 caddr_t
allocsys(v)504 allocsys(v)
505 register caddr_t v;
506 {
507
508 #define valloc(name, type, num) \
509 v = (caddr_t)(((name) = (type *)v) + (num))
510
511 #ifdef SYSVMSG
512 valloc(msgpool, char, msginfo.msgmax);
513 valloc(msgmaps, struct msgmap, msginfo.msgseg);
514 valloc(msghdrs, struct msg, msginfo.msgtql);
515 valloc(msqids, struct msqid_ds, msginfo.msgmni);
516 #endif
517
518 /*
519 * Determine how many buffers to allocate. We use 10% of the
520 * first 2MB of memory, and 5% of the rest, with a minimum of 16
521 * buffers. We allocate 1/2 as many swap buffer headers as file
522 * i/o buffers.
523 */
524 if (bufpages == 0) {
525 bufpages = (btoc(2 * 1024 * 1024) + physmem) *
526 bufcachepercent / 100;
527 }
528 if (nbuf == 0) {
529 nbuf = bufpages;
530 if (nbuf < 16)
531 nbuf = 16;
532 }
533
534 /* Restrict to at most 35% filled kvm */
535 /* XXX - This needs UBC... */
536 if (nbuf >
537 (VM_MAX_KERNEL_ADDRESS-VM_MIN_KERNEL_ADDRESS) / MAXBSIZE * 35 / 100)
538 nbuf = (VM_MAX_KERNEL_ADDRESS-VM_MIN_KERNEL_ADDRESS) /
539 MAXBSIZE * 35 / 100;
540
541 /* More buffer pages than fits into the buffers is senseless. */
542 if (bufpages > nbuf * MAXBSIZE / PAGE_SIZE)
543 bufpages = nbuf * MAXBSIZE / PAGE_SIZE;
544
545 valloc(buf, struct buf, nbuf);
546 return v;
547 }
548
549 void
setup_buffers(maxaddr)550 setup_buffers(maxaddr)
551 vaddr_t *maxaddr;
552 {
553 vsize_t size;
554 vaddr_t addr;
555 int base, residual, left, chunk, i;
556 struct pglist pgs, saved_pgs;
557 struct vm_page *pg;
558
559 size = MAXBSIZE * nbuf;
560 if (uvm_map(kernel_map, (vaddr_t *) &buffers, round_page(size),
561 NULL, UVM_UNKNOWN_OFFSET, 0,
562 UVM_MAPFLAG(UVM_PROT_NONE, UVM_PROT_NONE, UVM_INH_NONE,
563 UVM_ADV_NORMAL, 0)))
564 panic("cpu_startup: cannot allocate VM for buffers");
565 addr = (vaddr_t)buffers;
566
567 base = bufpages / nbuf;
568 residual = bufpages % nbuf;
569 if (base >= MAXBSIZE / PAGE_SIZE) {
570 /* don't want to alloc more physical mem than needed */
571 base = MAXBSIZE / PAGE_SIZE;
572 residual = 0;
573 }
574
575 /*
576 * In case we might need DMA bouncing we have to make sure there
577 * is some memory below 16MB available. On machines with many
578 * pages reserved for the buffer cache we risk filling all of that
579 * area with buffer pages. We still want much of the buffers
580 * reside there as that lowers the probability of them needing to
581 * bounce, but we have to set aside some space for DMA buffers too.
582 *
583 * The current strategy is to grab hold of one 3MB chunk below 16MB
584 * first, which we are saving for DMA buffers, then try to get
585 * one chunk at a time for fs buffers, until that is not possible
586 * anymore, at which point we get the rest wherever we may find it.
587 * After that we give our saved area back. That will guarantee at
588 * least 3MB below 16MB left for drivers' attach routines, among
589 * them isadma. However we still have a potential problem of PCI
590 * devices attached earlier snatching that memory. This can be
591 * solved by making the PCI DMA memory allocation routines go for
592 * memory above 16MB first.
593 */
594
595 left = bufpages;
596
597 /*
598 * First, save ISA DMA bounce buffer area so we won't lose that
599 * capability.
600 */
601 TAILQ_INIT(&saved_pgs);
602 TAILQ_INIT(&pgs);
603 if (!ALLOC_PGS(CHUNKSZ, ISADMA_LIMIT, saved_pgs)) {
604 /*
605 * Then, grab as much ISA DMAable memory as possible
606 * for the buffer cache as it is nice to not need to
607 * bounce all buffer I/O.
608 */
609 for (left = bufpages; left > 0; left -= chunk) {
610 chunk = min(left, CHUNKSZ / PAGE_SIZE);
611 if (ALLOC_PGS(chunk * PAGE_SIZE, ISADMA_LIMIT, pgs))
612 break;
613 }
614 }
615
616 /*
617 * If we need more pages for the buffer cache, get them from anywhere.
618 */
619 if (left > 0 && ALLOC_PGS(left * PAGE_SIZE, avail_end, pgs))
620 panic("cannot get physical memory for buffer cache");
621
622 /*
623 * Finally, give back the ISA DMA bounce buffer area, so it can be
624 * allocated by the isadma driver later.
625 */
626 if (!TAILQ_EMPTY(&saved_pgs))
627 FREE_PGS(saved_pgs);
628
629 pg = TAILQ_FIRST(&pgs);
630 for (i = 0; i < nbuf; i++) {
631 /*
632 * First <residual> buffers get (base+1) physical pages
633 * allocated for them. The rest get (base) physical pages.
634 *
635 * The rest of each buffer occupies virtual space,
636 * but has no physical memory allocated for it.
637 */
638 addr = (vaddr_t)buffers + i * MAXBSIZE;
639 for (size = PAGE_SIZE * (i < residual ? base + 1 : base);
640 size > 0; size -= PAGE_SIZE, addr += PAGE_SIZE) {
641 pmap_kenter_pa(addr, VM_PAGE_TO_PHYS(pg),
642 VM_PROT_READ|VM_PROT_WRITE);
643 pg = TAILQ_NEXT(pg, pageq);
644 }
645 }
646 pmap_update(pmap_kernel());
647 }
648
649 /*
650 * Info for CTL_HW
651 */
652 char cpu_model[120];
653
654 /*
655 * Note: these are just the ones that may not have a cpuid instruction.
656 * We deal with the rest in a different way.
657 */
658 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = {
659 { CPUVENDOR_INTEL, "Intel", "386SX", CPUCLASS_386,
660 NULL}, /* CPU_386SX */
661 { CPUVENDOR_INTEL, "Intel", "386DX", CPUCLASS_386,
662 NULL}, /* CPU_386 */
663 { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486,
664 NULL}, /* CPU_486SX */
665 { CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486,
666 NULL}, /* CPU_486 */
667 { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486,
668 NULL}, /* CPU_486DLC */
669 { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486,
670 cyrix6x86_cpu_setup}, /* CPU_6x86 */
671 { CPUVENDOR_NEXGEN,"NexGen","586", CPUCLASS_386,
672 NULL}, /* CPU_NX586 */
673 };
674
675 const char *classnames[] = {
676 "386",
677 "486",
678 "586",
679 "686"
680 };
681
682 const char *modifiers[] = {
683 "",
684 "OverDrive ",
685 "Dual ",
686 ""
687 };
688
689 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = {
690 {
691 "GenuineIntel",
692 CPUVENDOR_INTEL,
693 "Intel",
694 /* Family 4 */
695 { {
696 CPUCLASS_486,
697 {
698 "486DX", "486DX", "486SX", "486DX2", "486SL",
699 "486SX2", 0, "486DX2 W/B",
700 "486DX4", 0, 0, 0, 0, 0, 0, 0,
701 "486" /* Default */
702 },
703 NULL
704 },
705 /* Family 5 */
706 {
707 CPUCLASS_586,
708 {
709 "Pentium (A-step)", "Pentium (P5)",
710 "Pentium (P54C)", "Pentium (P24T)",
711 "Pentium/MMX", "Pentium", 0,
712 "Pentium (P54C)", "Pentium/MMX",
713 0, 0, 0, 0, 0, 0, 0,
714 "Pentium" /* Default */
715 },
716 intel586_cpu_setup
717 },
718 /* Family 6 */
719 {
720 CPUCLASS_686,
721 {
722 "Pentium Pro", "Pentium Pro", 0,
723 "Pentium II", "Pentium Pro",
724 "Pentium II/Celeron",
725 "Celeron",
726 "Pentium III",
727 "Pentium III",
728 "Pentium M",
729 "Pentium III Xeon",
730 "Pentium III", 0,
731 "Pentium M",
732 "Core Duo/Solo", 0,
733 "Pentium Pro, II or III" /* Default */
734 },
735 intel686_cpu_setup
736 },
737 /* Family 7 */
738 {
739 CPUCLASS_686,
740 } ,
741 /* Family 8 */
742 {
743 CPUCLASS_686,
744 } ,
745 /* Family 9 */
746 {
747 CPUCLASS_686,
748 } ,
749 /* Family A */
750 {
751 CPUCLASS_686,
752 } ,
753 /* Family B */
754 {
755 CPUCLASS_686,
756 } ,
757 /* Family C */
758 {
759 CPUCLASS_686,
760 } ,
761 /* Family D */
762 {
763 CPUCLASS_686,
764 } ,
765 /* Family E */
766 {
767 CPUCLASS_686,
768 } ,
769 /* Family F */
770 {
771 CPUCLASS_686,
772 {
773 "Pentium 4", 0, 0, 0,
774 0, 0, 0, 0,
775 0, 0, 0, 0,
776 0, 0, 0, 0,
777 "Pentium 4" /* Default */
778 },
779 intel686_p4_cpu_setup
780 } }
781 },
782 {
783 "AuthenticAMD",
784 CPUVENDOR_AMD,
785 "AMD",
786 /* Family 4 */
787 { {
788 CPUCLASS_486,
789 {
790 0, 0, 0, "Am486DX2 W/T",
791 0, 0, 0, "Am486DX2 W/B",
792 "Am486DX4 W/T or Am5x86 W/T 150",
793 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0,
794 0, 0, "Am5x86 W/T 133/160",
795 "Am5x86 W/B 133/160",
796 "Am486 or Am5x86" /* Default */
797 },
798 NULL
799 },
800 /* Family 5 */
801 {
802 CPUCLASS_586,
803 {
804 "K5", "K5", "K5", "K5", 0, 0, "K6",
805 "K6", "K6-2", "K6-III", 0, 0, 0,
806 "K6-2+/III+", 0, 0,
807 "K5 or K6" /* Default */
808 },
809 amd_family5_setup
810 },
811 /* Family 6 */
812 {
813 CPUCLASS_686,
814 {
815 0, "Athlon Model 1", "Athlon Model 2",
816 "Duron Model 3",
817 "Athlon Model 4",
818 0, "Athlon XP Model 6",
819 "Duron Model 7",
820 "Athlon XP Model 8",
821 0, "Athlon XP Model 10",
822 0, 0, 0, 0, 0,
823 "K7" /* Default */
824 },
825 amd_family6_setup
826 },
827 /* Family 7 */
828 {
829 CPUCLASS_686,
830 } ,
831 /* Family 8 */
832 {
833 CPUCLASS_686,
834 } ,
835 /* Family 9 */
836 {
837 CPUCLASS_686,
838 } ,
839 /* Family A */
840 {
841 CPUCLASS_686,
842 } ,
843 /* Family B */
844 {
845 CPUCLASS_686,
846 } ,
847 /* Family C */
848 {
849 CPUCLASS_686,
850 } ,
851 /* Family D */
852 {
853 CPUCLASS_686,
854 } ,
855 /* Family E */
856 {
857 CPUCLASS_686,
858 } ,
859 /* Family F */
860 {
861 CPUCLASS_686,
862 {
863 0, 0, 0, 0, "Athlon64",
864 "Opteron or Athlon64FX", 0, 0,
865 0, 0, 0, 0, 0, 0, 0, 0,
866 "AMD64" /* DEFAULT */
867 },
868 amd_family6_setup
869 } }
870 },
871 {
872 "CyrixInstead",
873 CPUVENDOR_CYRIX,
874 "Cyrix",
875 /* Family 4 */
876 { {
877 CPUCLASS_486,
878 {
879 0, 0, 0, "MediaGX", 0, 0, 0, 0, "5x86", 0, 0,
880 0, 0, 0, 0,
881 "486 class" /* Default */
882 },
883 NULL
884 },
885 /* Family 5 */
886 {
887 CPUCLASS_586,
888 {
889 0, 0, "6x86", 0, "GXm", 0, 0, 0, 0, 0,
890 0, 0, 0, 0, 0, 0,
891 "586 class" /* Default */
892 },
893 cyrix6x86_cpu_setup
894 },
895 /* Family 6 */
896 {
897 CPUCLASS_686,
898 {
899 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
900 0, 0, 0, 0,
901 "686 class" /* Default */
902 },
903 NULL
904 } }
905 },
906 {
907 "CentaurHauls",
908 CPUVENDOR_IDT,
909 "IDT",
910 /* Family 4, not available from IDT */
911 { {
912 CPUCLASS_486,
913 {
914 0, 0, 0, 0, 0, 0, 0, 0,
915 0, 0, 0, 0, 0, 0, 0, 0,
916 "486 class" /* Default */
917 },
918 NULL
919 },
920 /* Family 5 */
921 {
922 CPUCLASS_586,
923 {
924 0, 0, 0, 0, "WinChip C6", 0, 0, 0,
925 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0,
926 "WinChip" /* Default */
927 },
928 winchip_cpu_setup
929 },
930 /* Family 6 */
931 {
932 CPUCLASS_686,
933 {
934 0, 0, 0, 0, 0, 0,
935 "C3 Samuel",
936 "C3 Samuel 2/Ezra",
937 "C3 Ezra-T",
938 "C3 Nehemiah", "C3 Esther", 0, 0, 0, 0, 0,
939 "C3" /* Default */
940 },
941 cyrix3_cpu_setup
942 } }
943 },
944 {
945 "RiseRiseRise",
946 CPUVENDOR_RISE,
947 "Rise",
948 /* Family 4, not available from Rise */
949 { {
950 CPUCLASS_486,
951 {
952 0, 0, 0, 0, 0, 0, 0, 0,
953 0, 0, 0, 0, 0, 0, 0, 0,
954 "486 class" /* Default */
955 },
956 NULL
957 },
958 /* Family 5 */
959 {
960 CPUCLASS_586,
961 {
962 "mP6", 0, "mP6", 0, 0, 0, 0, 0,
963 0, 0, 0, 0, 0, 0, 0, 0,
964 "mP6" /* Default */
965 },
966 NULL
967 },
968 /* Family 6, not yet available from Rise */
969 {
970 CPUCLASS_686,
971 {
972 0, 0, 0, 0, 0, 0, 0, 0,
973 0, 0, 0, 0, 0, 0, 0, 0,
974 "686 class" /* Default */
975 },
976 NULL
977 } }
978 },
979 {
980 "GenuineTMx86",
981 CPUVENDOR_TRANSMETA,
982 "Transmeta",
983 /* Family 4, not available from Transmeta */
984 { {
985 CPUCLASS_486,
986 {
987 0, 0, 0, 0, 0, 0, 0, 0,
988 0, 0, 0, 0, 0, 0, 0, 0,
989 "486 class" /* Default */
990 },
991 NULL
992 },
993 /* Family 5 */
994 {
995 CPUCLASS_586,
996 {
997 0, 0, 0, 0, "TMS5x00", 0, 0,
998 0, 0, 0, 0, 0, 0, 0, 0, 0,
999 "TMS5x00" /* Default */
1000 },
1001 tm86_cpu_setup
1002 },
1003 /* Family 6, not yet available from Transmeta */
1004 {
1005 CPUCLASS_686,
1006 {
1007 0, 0, 0, 0, 0, 0, 0, 0,
1008 0, 0, 0, 0, 0, 0, 0, 0,
1009 "686 class" /* Default */
1010 },
1011 NULL
1012 } }
1013 },
1014 {
1015 "Geode by NSC",
1016 CPUVENDOR_NS,
1017 "National Semiconductor",
1018 /* Family 4, not available from National Semiconductor */
1019 { {
1020 CPUCLASS_486,
1021 {
1022 0, 0, 0, 0, 0, 0, 0, 0,
1023 0, 0, 0, 0, 0, 0, 0, 0,
1024 "486 class" /* Default */
1025 },
1026 NULL
1027 },
1028 /* Family 5 */
1029 {
1030 CPUCLASS_586,
1031 {
1032 0, 0, 0, 0, "Geode GX1", 0, 0, 0, 0, 0,
1033 0, 0, 0, 0, 0, 0,
1034 "586 class" /* Default */
1035 },
1036 natsem6x86_cpu_setup
1037 } }
1038 },
1039 {
1040 "SiS SiS SiS ",
1041 CPUVENDOR_SIS,
1042 "SiS",
1043 /* Family 4, not available from SiS */
1044 { {
1045 CPUCLASS_486,
1046 {
1047 0, 0, 0, 0, 0, 0, 0, 0,
1048 0, 0, 0, 0, 0, 0, 0, 0,
1049 "486 class" /* Default */
1050 },
1051 NULL
1052 },
1053 /* Family 5 */
1054 {
1055 CPUCLASS_586,
1056 {
1057 "SiS55x", 0, 0, 0, 0, 0, 0, 0, 0, 0,
1058 0, 0, 0, 0, 0, 0,
1059 "586 class" /* Default */
1060 },
1061 NULL
1062 } }
1063 }
1064 };
1065
1066 const struct cpu_cpuid_feature i386_cpuid_features[] = {
1067 { CPUID_FPU, "FPU" },
1068 { CPUID_VME, "V86" },
1069 { CPUID_DE, "DE" },
1070 { CPUID_PSE, "PSE" },
1071 { CPUID_TSC, "TSC" },
1072 { CPUID_MSR, "MSR" },
1073 { CPUID_PAE, "PAE" },
1074 { CPUID_MCE, "MCE" },
1075 { CPUID_CX8, "CX8" },
1076 { CPUID_APIC, "APIC" },
1077 { CPUID_SYS1, "SYS" },
1078 { CPUID_SEP, "SEP" },
1079 { CPUID_MTRR, "MTRR" },
1080 { CPUID_PGE, "PGE" },
1081 { CPUID_MCA, "MCA" },
1082 { CPUID_CMOV, "CMOV" },
1083 { CPUID_PAT, "PAT" },
1084 { CPUID_PSE36, "PSE36" },
1085 { CPUID_SER, "SER" },
1086 { CPUID_CFLUSH, "CFLUSH" },
1087 { CPUID_ACPI, "ACPI" },
1088 { CPUID_MMX, "MMX" },
1089 { CPUID_FXSR, "FXSR" },
1090 { CPUID_SSE, "SSE" },
1091 { CPUID_SSE2, "SSE2" },
1092 { CPUID_SS, "SS" },
1093 { CPUID_HTT, "HTT" },
1094 { CPUID_TM, "TM" },
1095 { CPUID_SBF, "SBF" },
1096 { CPUID_3DNOW, "3DNOW" },
1097 };
1098
1099 const struct cpu_cpuid_feature i386_cpuid_ecxfeatures[] = {
1100 { CPUIDECX_PNI, "PNI" },
1101 { CPUIDECX_MWAIT, "MWAIT" },
1102 { CPUIDECX_EST, "EST" },
1103 { CPUIDECX_TM2, "TM2" },
1104 { CPUIDECX_CNXTID, "CNXT-ID" },
1105 };
1106
1107 void
winchip_cpu_setup(cpu_device,model,step)1108 winchip_cpu_setup(cpu_device, model, step)
1109 const char *cpu_device;
1110 int model, step;
1111 {
1112 #if defined(I586_CPU)
1113
1114 switch (model) {
1115 case 4: /* WinChip C6 */
1116 cpu_feature &= ~CPUID_TSC;
1117 /* Disable RDTSC instruction from user-level. */
1118 lcr4(rcr4() | CR4_TSD);
1119
1120 printf("%s: TSC disabled\n", cpu_device);
1121 break;
1122 }
1123 #endif
1124 }
1125
1126 void
cyrix3_cpu_setup(cpu_device,model,step)1127 cyrix3_cpu_setup(cpu_device, model, step)
1128 const char *cpu_device;
1129 int model, step;
1130 {
1131 #if defined(I686_CPU)
1132 u_int64_t msreg;
1133 u_int32_t regs[4];
1134 unsigned int val;
1135 #if !defined(SMALL_KERNEL)
1136 extern void (*pagezero)(void *, size_t);
1137 extern void i686_pagezero(void *, size_t);
1138
1139 pagezero = i686_pagezero;
1140 #endif
1141
1142
1143 switch (model) {
1144 case 6: /* C3 Samuel 1 */
1145 case 7: /* C3 Samuel 2 or C3 Ezra */
1146 case 8: /* C3 Ezra-T */
1147 cpuid(0x80000001, regs);
1148 val = regs[3];
1149 if (val & (1U << 31)) {
1150 cpu_feature |= CPUID_3DNOW;
1151 } else {
1152 cpu_feature &= ~CPUID_3DNOW;
1153 }
1154 break;
1155
1156 case 9:
1157 if (step < 3)
1158 break;
1159
1160 /*
1161 * C3 Nehemiah: fall through.
1162 */
1163 case 10:
1164 /*
1165 * C3 Nehemiah/Esther:
1166 * First we check for extended feature flags, and then
1167 * (if present) retrieve the ones at 0xC0000001. In this
1168 * bit 2 tells us if the RNG is present. Bit 3 tells us
1169 * if the RNG has been enabled. In order to use the RNG
1170 * we need 3 things: We need an RNG, we need the FXSR bit
1171 * enabled in cr4 (SSE/SSE2 stuff), and we need to have
1172 * Bit 6 of MSR 0x110B set to 1 (the default), which will
1173 * show up as bit 3 set here.
1174 */
1175 cpuid(0xC0000000, regs); /* Check for RNG */
1176 val = regs[0];
1177 if (val >= 0xC0000001) {
1178 cpuid(0xC0000001, regs);
1179 val = regs[3];
1180 } else
1181 val = 0;
1182
1183 if (val & (C3_CPUID_HAS_RNG | C3_CPUID_HAS_ACE))
1184 printf("%s:", cpu_device);
1185
1186 /* Enable RNG if present and disabled */
1187 if (val & C3_CPUID_HAS_RNG) {
1188 extern int viac3_rnd_present;
1189
1190 if (!(val & C3_CPUID_DO_RNG)) {
1191 msreg = rdmsr(0x110B);
1192 msreg |= 0x40;
1193 wrmsr(0x110B, msreg);
1194 }
1195 viac3_rnd_present = 1;
1196 printf(" RNG");
1197 }
1198
1199 /* Enable AES engine if present and disabled */
1200 if (val & C3_CPUID_HAS_ACE) {
1201 #ifdef CRYPTO
1202 extern int viac3_crypto_present;
1203
1204 if (!(val & C3_CPUID_DO_ACE)) {
1205 msreg = rdmsr(0x1107);
1206 msreg |= (0x01 << 28);
1207 wrmsr(0x1107, msreg);
1208 }
1209 viac3_crypto_present = 1;
1210 #endif /* CRYPTO */
1211 printf(" AES");
1212 }
1213
1214 printf("\n");
1215 break;
1216 }
1217 #endif
1218 }
1219
1220 void
cyrix6x86_cpu_setup(cpu_device,model,step)1221 cyrix6x86_cpu_setup(cpu_device, model, step)
1222 const char *cpu_device;
1223 int model, step;
1224 {
1225 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
1226 extern int clock_broken_latch;
1227
1228 switch (model) {
1229 case -1: /* M1 w/o cpuid */
1230 case 2: /* M1 */
1231 /* set up various cyrix registers */
1232 /* Enable suspend on halt */
1233 cyrix_write_reg(0xc2, cyrix_read_reg(0xc2) | 0x08);
1234 /* enable access to ccr4/ccr5 */
1235 cyrix_write_reg(0xC3, cyrix_read_reg(0xC3) | 0x10);
1236 /* cyrix's workaround for the "coma bug" */
1237 cyrix_write_reg(0x31, cyrix_read_reg(0x31) | 0xf8);
1238 cyrix_write_reg(0x32, cyrix_read_reg(0x32) | 0x7f);
1239 cyrix_write_reg(0x33, cyrix_read_reg(0x33) & ~0xff);
1240 cyrix_write_reg(0x3c, cyrix_read_reg(0x3c) | 0x87);
1241 /* disable access to ccr4/ccr5 */
1242 cyrix_write_reg(0xC3, cyrix_read_reg(0xC3) & ~0x10);
1243
1244 printf("%s: xchg bug workaround performed\n", cpu_device);
1245 break; /* fallthrough? */
1246 case 4:
1247 clock_broken_latch = 1;
1248 cpu_feature &= ~CPUID_TSC;
1249 printf("%s: TSC disabled\n", cpu_device);
1250 break;
1251 }
1252 #endif
1253 }
1254
1255 #if defined(I586_CPU) || defined(I686_CPU)
1256 void natsem6x86_cpureset(void);
1257
1258 void
natsem6x86_cpureset(void)1259 natsem6x86_cpureset(void)
1260 {
1261 /* reset control SC1100 (datasheet page 170) */
1262 outl(0xCF8, 0x80009044UL);
1263 /* system wide reset */
1264 outb(0xCFC, 0x0F);
1265 }
1266 #endif
1267
1268 void
natsem6x86_cpu_setup(cpu_device,model,step)1269 natsem6x86_cpu_setup(cpu_device, model, step)
1270 const char *cpu_device;
1271 int model, step;
1272 {
1273 #if defined(I586_CPU) || defined(I686_CPU)
1274 extern int clock_broken_latch;
1275
1276 clock_broken_latch = 1;
1277 switch (model) {
1278 case 4:
1279 cpu_feature &= ~CPUID_TSC;
1280 printf("%s: TSC disabled\n", cpu_device);
1281 break;
1282 }
1283 cpuresetfn = natsem6x86_cpureset;
1284 #endif
1285 }
1286
1287
1288 void
intel586_cpu_setup(cpu_device,model,step)1289 intel586_cpu_setup(cpu_device, model, step)
1290 const char *cpu_device;
1291 int model, step;
1292 {
1293 #if defined(I586_CPU)
1294 fix_f00f();
1295 printf("%s: F00F bug workaround installed\n", cpu_device);
1296 #endif
1297 }
1298
1299 void
amd_family5_setup(cpu_device,model,step)1300 amd_family5_setup(cpu_device, model, step)
1301 const char *cpu_device;
1302 int model, step;
1303 {
1304 switch (model) {
1305 case 0: /* AMD-K5 Model 0 */
1306 /*
1307 * According to the AMD Processor Recognition App Note,
1308 * the AMD-K5 Model 0 uses the wrong bit to indicate
1309 * support for global PTEs, instead using bit 9 (APIC)
1310 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!).
1311 */
1312 if (cpu_feature & CPUID_APIC)
1313 cpu_feature = (cpu_feature & ~CPUID_APIC) | CPUID_PGE;
1314 /*
1315 * XXX But pmap_pg_g is already initialized -- need to kick
1316 * XXX the pmap somehow. How does the MP branch do this?
1317 */
1318 break;
1319 case 12:
1320 case 13:
1321 #ifndef SMALL_KERNEL
1322 k6_powernow_init();
1323 #endif
1324 break;
1325 }
1326 }
1327
1328 struct amd_pn_flag {
1329 int mask;
1330 const char *name;
1331 };
1332
1333 void
amd_family6_setup(cpu_device,model,step)1334 amd_family6_setup(cpu_device, model, step)
1335 const char *cpu_device;
1336 int model, step;
1337 {
1338 #if !defined(SMALL_KERNEL) && defined(I686_CPU)
1339 extern void (*pagezero)(void *, size_t);
1340 extern void sse2_pagezero(void *, size_t);
1341 extern void i686_pagezero(void *, size_t);
1342 static struct amd_pn_flag amd_pn_flags[] = {
1343 {0x01, "TS"},
1344 {0x02, "FID"},
1345 {0x04, "VID"},
1346 {0x08, "TTP"},
1347 {0x10, "TM"},
1348 {0x20, "STC"}
1349 };
1350 u_int regs[4];
1351 int i;
1352
1353 if (cpu_feature & CPUID_SSE2)
1354 pagezero = sse2_pagezero;
1355 else
1356 pagezero = i686_pagezero;
1357 cpuid(0x80000000, regs);
1358 if (regs[0] > 0x80000007) {
1359 cpuid(0x80000007, regs);
1360 printf("%s: AMD Powernow:", cpu_device);
1361 for (i = 0; i < 6; i++) {
1362 if (regs[3] & amd_pn_flags[i].mask)
1363 printf(" %s", amd_pn_flags[i].name);
1364 }
1365 printf("\n");
1366 #if NPOWERNOWHACK > 0
1367 if (regs[3] & 6)
1368 k7_powernow_init();
1369 #endif
1370 }
1371 #endif
1372 }
1373
1374 void
intel686_common_cpu_setup(const char * cpu_device,int model,int step)1375 intel686_common_cpu_setup(const char *cpu_device, int model, int step)
1376 {
1377 /*
1378 * Make sure SYSENTER is disabled.
1379 */
1380 if (cpu_feature & CPUID_SEP)
1381 wrmsr(MSR_SYSENTER_CS, 0);
1382
1383 #if !defined(SMALL_KERNEL) && defined(I686_CPU)
1384 if (cpu_ecxfeature & CPUIDECX_EST) {
1385 if (rdmsr(MSR_MISC_ENABLE) & (1 << 16))
1386 est_init(cpu_device);
1387 else
1388 printf("%s: Enhanced SpeedStep disabled by BIOS\n",
1389 cpu_device);
1390 } else if ((cpu_feature & (CPUID_ACPI | CPUID_TM)) ==
1391 (CPUID_ACPI | CPUID_TM))
1392 p4tcc_init(model, step);
1393
1394 {
1395 extern void (*pagezero)(void *, size_t);
1396 extern void sse2_pagezero(void *, size_t);
1397 extern void i686_pagezero(void *, size_t);
1398
1399 if (cpu_feature & CPUID_SSE2)
1400 pagezero = sse2_pagezero;
1401 else
1402 pagezero = i686_pagezero;
1403 }
1404 #endif
1405 }
1406
1407 void
intel686_cpu_setup(const char * cpu_device,int model,int step)1408 intel686_cpu_setup(const char *cpu_device, int model, int step)
1409 {
1410 u_quad_t msr119;
1411
1412 intel686_common_cpu_setup(cpu_device, model, step);
1413
1414 /*
1415 * Original PPro returns SYSCALL in CPUID but is non-functional.
1416 * From Intel Application Note #485.
1417 */
1418 if ((model == 1) && (step < 3))
1419 cpu_feature &= ~CPUID_SEP;
1420
1421 /*
1422 * Disable the Pentium3 serial number.
1423 */
1424 if ((model == 7) && (cpu_feature & CPUID_SER)) {
1425 uint32_t ser_regs[8];
1426 int i = 0;
1427
1428 /* but hash it into the entropy pool first */
1429 cpuid(1, &(ser_regs[0]));
1430 cpuid(3, &(ser_regs[4]));
1431 /* privacy */
1432 while (i < 8)
1433 ser_regs[i] += arc4random();
1434 rnd_lopool_add(ser_regs, sizeof(ser_regs));
1435
1436 /* make it so they can't read it again before reset */
1437 msr119 = rdmsr(MSR_BBL_CR_CTL);
1438 msr119 |= 0x0000000000200000LL;
1439 wrmsr(MSR_BBL_CR_CTL, msr119);
1440
1441 printf("%s: disabling processor serial number\n", cpu_device);
1442 cpu_feature &= ~CPUID_SER;
1443 cpuid_level = 2;
1444 }
1445
1446 #if !defined(SMALL_KERNEL) && defined(I686_CPU)
1447 p3_step = step;
1448 update_cpuspeed = p3_update_cpuspeed;
1449 update_cpuspeed();
1450 #endif
1451 }
1452
1453 void
intel686_p4_cpu_setup(const char * cpu_device,int model,int step)1454 intel686_p4_cpu_setup(const char *cpu_device, int model, int step)
1455 {
1456 intel686_common_cpu_setup(cpu_device, model, step);
1457
1458 #if !defined(SMALL_KERNEL) && defined(I686_CPU)
1459 p4_model = model;
1460 update_cpuspeed = p4_update_cpuspeed;
1461 update_cpuspeed();
1462 #endif
1463 }
1464
1465 void
tm86_cpu_setup(cpu_device,model,step)1466 tm86_cpu_setup(cpu_device, model, step)
1467 const char *cpu_device;
1468 int model, step;
1469 {
1470 #if !defined(SMALL_KERNEL) && defined(I586_CPU)
1471 longrun_init();
1472 #endif
1473 }
1474
1475 char *
intel686_cpu_name(model)1476 intel686_cpu_name(model)
1477 int model;
1478 {
1479 extern int cpu_cache_edx;
1480 char *ret = NULL;
1481
1482 switch (model) {
1483 case 5:
1484 switch (cpu_cache_edx & 0xFF) {
1485 case 0x40:
1486 case 0x41:
1487 ret = "Celeron";
1488 break;
1489 /* 0x42 should not exist in this model. */
1490 case 0x43:
1491 ret = "Pentium II";
1492 break;
1493 case 0x44:
1494 case 0x45:
1495 ret = "Pentium II Xeon";
1496 break;
1497 }
1498 break;
1499 case 7:
1500 switch (cpu_cache_edx & 0xFF) {
1501 /* 0x40 - 0x42 should not exist in this model. */
1502 case 0x43:
1503 ret = "Pentium III";
1504 break;
1505 case 0x44:
1506 case 0x45:
1507 ret = "Pentium III Xeon";
1508 break;
1509 }
1510 break;
1511 }
1512
1513 return (ret);
1514 }
1515
1516 char *
cyrix3_cpu_name(model,step)1517 cyrix3_cpu_name(model, step)
1518 int model, step;
1519 {
1520 char *name = NULL;
1521
1522 switch (model) {
1523 case 7:
1524 if (step < 8)
1525 name = "C3 Samuel 2";
1526 else
1527 name = "C3 Ezra";
1528 break;
1529 }
1530 return name;
1531 }
1532
1533 char *
tm86_cpu_name(model)1534 tm86_cpu_name(model)
1535 int model;
1536 {
1537 u_int32_t regs[4];
1538 char *name = NULL;
1539
1540 cpuid(0x80860001, regs);
1541
1542 switch(model) {
1543 case 4:
1544 if (((regs[1] >> 16) & 0xff) >= 0x3)
1545 name = "TMS5800";
1546 else
1547 name = "TMS5600";
1548 }
1549
1550 return name;
1551 }
1552
1553 void
identifycpu()1554 identifycpu()
1555 {
1556 extern char cpu_vendor[];
1557 extern char cpu_brandstr[];
1558 extern int cpu_id;
1559 #ifdef CPUDEBUG
1560 extern int cpu_cache_eax, cpu_cache_ebx, cpu_cache_ecx, cpu_cache_edx;
1561 #else
1562 extern int cpu_cache_edx;
1563 #endif
1564 const char *name, *modifier, *vendorname, *token;
1565 const char *cpu_device = "cpu0";
1566 int class = CPUCLASS_386, vendor, i, max;
1567 int family = 0, model, step, modif, cachesize;
1568 const struct cpu_cpuid_nameclass *cpup = NULL;
1569 void (*cpu_setup)(const char *, int, int);
1570 char *brandstr_from, *brandstr_to;
1571 int skipspace;
1572
1573 if (cpuid_level == -1) {
1574 #ifdef DIAGNOSTIC
1575 if (cpu < 0 || cpu >=
1576 (sizeof i386_nocpuid_cpus/sizeof(struct cpu_nocpuid_nameclass)))
1577 panic("unknown cpu type %d", cpu);
1578 #endif
1579 name = i386_nocpuid_cpus[cpu].cpu_name;
1580 vendor = i386_nocpuid_cpus[cpu].cpu_vendor;
1581 vendorname = i386_nocpuid_cpus[cpu].cpu_vendorname;
1582 model = -1;
1583 step = -1;
1584 class = i386_nocpuid_cpus[cpu].cpu_class;
1585 cpu_setup = i386_nocpuid_cpus[cpu].cpu_setup;
1586 modifier = "";
1587 token = "";
1588 } else {
1589 max = sizeof (i386_cpuid_cpus) / sizeof (i386_cpuid_cpus[0]);
1590 modif = (cpu_id >> 12) & 3;
1591 family = (cpu_id >> 8) & 15;
1592 if (family < CPU_MINFAMILY)
1593 panic("identifycpu: strange family value");
1594 model = (cpu_id >> 4) & 15;
1595 step = cpu_id & 15;
1596 #ifdef CPUDEBUG
1597 printf("%s: family %x model %x step %x\n", cpu_device, family,
1598 model, step);
1599 printf("%s: cpuid level %d cache eax %x ebx %x ecx %x edx %x\n",
1600 cpu_device, cpuid_level, cpu_cache_eax, cpu_cache_ebx,
1601 cpu_cache_ecx, cpu_cache_edx);
1602 #endif
1603
1604 for (i = 0; i < max; i++) {
1605 if (!strncmp(cpu_vendor,
1606 i386_cpuid_cpus[i].cpu_id, 12)) {
1607 cpup = &i386_cpuid_cpus[i];
1608 break;
1609 }
1610 }
1611
1612 if (cpup == NULL) {
1613 vendor = CPUVENDOR_UNKNOWN;
1614 if (cpu_vendor[0] != '\0')
1615 vendorname = &cpu_vendor[0];
1616 else
1617 vendorname = "Unknown";
1618 if (family > CPU_MAXFAMILY)
1619 family = CPU_MAXFAMILY;
1620 class = family - 3;
1621 if (class > CPUCLASS_686)
1622 class = CPUCLASS_686;
1623 modifier = "";
1624 name = "";
1625 token = "";
1626 cpu_setup = NULL;
1627 } else {
1628 token = cpup->cpu_id;
1629 vendor = cpup->cpu_vendor;
1630 vendorname = cpup->cpu_vendorname;
1631 /*
1632 * Special hack for the VIA C3 series.
1633 *
1634 * VIA bought Centaur Technology from IDT in Aug 1999
1635 * and marketed the processors as VIA Cyrix III/C3.
1636 */
1637 if (vendor == CPUVENDOR_IDT && family >= 6) {
1638 vendor = CPUVENDOR_VIA;
1639 vendorname = "VIA";
1640 }
1641 modifier = modifiers[modif];
1642 if (family > CPU_MAXFAMILY) {
1643 family = CPU_MAXFAMILY;
1644 model = CPU_DEFMODEL;
1645 } else if (model > CPU_MAXMODEL)
1646 model = CPU_DEFMODEL;
1647 i = family - CPU_MINFAMILY;
1648
1649 /* Special hack for the PentiumII/III series. */
1650 if (vendor == CPUVENDOR_INTEL && family == 6 &&
1651 (model == 5 || model == 7)) {
1652 name = intel686_cpu_name(model);
1653 /* Special hack for the VIA C3 series. */
1654 } else if (vendor == CPUVENDOR_VIA && family == 6 &&
1655 model == 7) {
1656 name = cyrix3_cpu_name(model, step);
1657 /* Special hack for the TMS5x00 series. */
1658 } else if (vendor == CPUVENDOR_TRANSMETA &&
1659 family == 5 && model == 4) {
1660 name = tm86_cpu_name(model);
1661 } else
1662 name = cpup->cpu_family[i].cpu_models[model];
1663 if (name == NULL) {
1664 name = cpup->cpu_family[i].cpu_models[CPU_DEFMODEL];
1665 if (name == NULL)
1666 name = "";
1667 }
1668 class = cpup->cpu_family[i].cpu_class;
1669 cpu_setup = cpup->cpu_family[i].cpu_setup;
1670 }
1671 }
1672
1673 /* Find the amount of on-chip L2 cache. */
1674 cachesize = -1;
1675 if (vendor == CPUVENDOR_INTEL && cpuid_level >= 2 && family < 0xf) {
1676 int intel_cachetable[] = { 0, 128, 256, 512, 1024, 2048 };
1677 if ((cpu_cache_edx & 0xFF) >= 0x40 &&
1678 (cpu_cache_edx & 0xFF) <= 0x45)
1679 cachesize = intel_cachetable[(cpu_cache_edx & 0xFF) - 0x40];
1680 } else if (vendor == CPUVENDOR_AMD && class == CPUCLASS_686) {
1681 u_int regs[4];
1682 cpuid(0x80000000, regs);
1683 if (regs[0] >= 0x80000006) {
1684 cpuid(0x80000006, regs);
1685 cachesize = (regs[2] >> 16);
1686 }
1687 }
1688
1689 /* Remove leading and duplicated spaces from cpu_brandstr */
1690 brandstr_from = brandstr_to = cpu_brandstr;
1691 skipspace = 1;
1692 while (*brandstr_from != '\0') {
1693 if (!skipspace || *brandstr_from != ' ') {
1694 skipspace = 0;
1695 *(brandstr_to++) = *brandstr_from;
1696 }
1697 if (*brandstr_from == ' ')
1698 skipspace = 1;
1699 brandstr_from++;
1700 }
1701 *brandstr_to = '\0';
1702
1703 if (cpu_brandstr[0] == '\0') {
1704 snprintf(cpu_brandstr, 48 /* sizeof(cpu_brandstr) */,
1705 "%s %s%s", vendorname, modifier, name);
1706 }
1707
1708 if (cachesize > -1) {
1709 snprintf(cpu_model, sizeof(cpu_model),
1710 "%s (%s%s%s%s-class, %dKB L2 cache)",
1711 cpu_brandstr,
1712 ((*token) ? "\"" : ""), ((*token) ? token : ""),
1713 ((*token) ? "\" " : ""), classnames[class], cachesize);
1714 } else {
1715 snprintf(cpu_model, sizeof(cpu_model),
1716 "%s (%s%s%s%s-class)",
1717 cpu_brandstr,
1718 ((*token) ? "\"" : ""), ((*token) ? token : ""),
1719 ((*token) ? "\" " : ""), classnames[class]);
1720 }
1721
1722 printf("%s: %s", cpu_device, cpu_model);
1723
1724 #if defined(I586_CPU) || defined(I686_CPU)
1725 if (cpu_feature & CPUID_TSC) { /* Has TSC */
1726 calibrate_cyclecounter();
1727 if (pentium_mhz > 994) {
1728 int ghz, fr;
1729
1730 ghz = (pentium_mhz + 9) / 1000;
1731 fr = ((pentium_mhz + 9) / 10 ) % 100;
1732 if (fr)
1733 printf(" %d.%02d GHz", ghz, fr);
1734 else
1735 printf(" %d GHz", ghz);
1736 } else
1737 printf(" %d MHz", pentium_mhz);
1738 #ifdef PENTIUM_BROKEN_TSC
1739 printf("\n%s: not using TSC for timekeeping", cpu_device);
1740 #endif
1741 }
1742 #endif
1743 printf("\n");
1744
1745 if (cpu_feature) {
1746 int numbits = 0;
1747
1748 printf("%s: ", cpu_device);
1749 max = sizeof(i386_cpuid_features)
1750 / sizeof(i386_cpuid_features[0]);
1751 for (i = 0; i < max; i++) {
1752 if (cpu_feature & i386_cpuid_features[i].feature_bit) {
1753 printf("%s%s", (numbits == 0 ? "" : ","),
1754 i386_cpuid_features[i].feature_name);
1755 numbits++;
1756 }
1757 }
1758 max = sizeof(i386_cpuid_ecxfeatures)
1759 / sizeof(i386_cpuid_ecxfeatures[0]);
1760 for (i = 0; i < max; i++) {
1761 if (cpu_ecxfeature &
1762 i386_cpuid_ecxfeatures[i].feature_bit) {
1763 printf("%s%s", (numbits == 0 ? "" : ","),
1764 i386_cpuid_ecxfeatures[i].feature_name);
1765 numbits++;
1766 }
1767 }
1768 printf("\n");
1769 }
1770
1771 /* configure the CPU if needed */
1772 if (cpu_setup != NULL)
1773 cpu_setup(cpu_device, model, step);
1774
1775 #ifndef SMALL_KERNEL
1776 #if defined(I586_CPU) || defined(I686_CPU)
1777 if (pentium_mhz != 0)
1778 cpu_cpuspeed = pentium_cpuspeed;
1779 #endif
1780 #endif
1781
1782 cpu_class = class;
1783
1784 /*
1785 * Now that we have told the user what they have,
1786 * let them know if that machine type isn't configured.
1787 */
1788 switch (cpu_class) {
1789 #if !defined(I386_CPU) && !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
1790 #error No CPU classes configured.
1791 #endif
1792 #ifndef I686_CPU
1793 case CPUCLASS_686:
1794 printf("NOTICE: this kernel does not support Pentium Pro CPU class\n");
1795 #ifdef I586_CPU
1796 printf("NOTICE: lowering CPU class to i586\n");
1797 cpu_class = CPUCLASS_586;
1798 break;
1799 #endif
1800 #endif
1801 #ifndef I586_CPU
1802 case CPUCLASS_586:
1803 printf("NOTICE: this kernel does not support Pentium CPU class\n");
1804 #ifdef I486_CPU
1805 printf("NOTICE: lowering CPU class to i486\n");
1806 cpu_class = CPUCLASS_486;
1807 break;
1808 #endif
1809 #endif
1810 #ifndef I486_CPU
1811 case CPUCLASS_486:
1812 printf("NOTICE: this kernel does not support i486 CPU class\n");
1813 #ifdef I386_CPU
1814 printf("NOTICE: lowering CPU class to i386\n");
1815 cpu_class = CPUCLASS_386;
1816 break;
1817 #endif
1818 #endif
1819 #ifndef I386_CPU
1820 case CPUCLASS_386:
1821 printf("NOTICE: this kernel does not support i386 CPU class\n");
1822 panic("no appropriate CPU class available");
1823 #endif
1824 default:
1825 break;
1826 }
1827
1828 if (cpu == CPU_486DLC) {
1829 #ifndef CYRIX_CACHE_WORKS
1830 printf("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n");
1831 #else
1832 #ifndef CYRIX_CACHE_REALLY_WORKS
1833 printf("WARNING: CYRIX 486DLC CACHE ENABLED IN HOLD-FLUSH MODE.\n");
1834 #else
1835 printf("WARNING: CYRIX 486DLC CACHE ENABLED.\n");
1836 #endif
1837 #endif
1838 }
1839
1840 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
1841 /*
1842 * On a 486 or above, enable ring 0 write protection.
1843 */
1844 if (cpu_class >= CPUCLASS_486)
1845 lcr0(rcr0() | CR0_WP);
1846 #endif
1847
1848 #if defined(I686_CPU)
1849 /*
1850 * If we have FXSAVE/FXRESTOR, use them.
1851 */
1852 if (cpu_feature & CPUID_FXSR) {
1853 i386_use_fxsave = 1;
1854 lcr4(rcr4() | CR4_OSFXSR);
1855
1856 /*
1857 * If we have SSE/SSE2, enable XMM exceptions, and
1858 * notify userland.
1859 */
1860 if (cpu_feature & (CPUID_SSE|CPUID_SSE2)) {
1861 if (cpu_feature & CPUID_SSE)
1862 i386_has_sse = 1;
1863 if (cpu_feature & CPUID_SSE2)
1864 i386_has_sse2 = 1;
1865 lcr4(rcr4() | CR4_OSXMMEXCPT);
1866 }
1867 } else
1868 i386_use_fxsave = 0;
1869 #endif /* I686_CPU */
1870
1871 }
1872
1873 #ifndef SMALL_KERNEL
1874 #ifdef I686_CPU
1875 void
p4_update_cpuspeed(void)1876 p4_update_cpuspeed(void)
1877 {
1878 u_int64_t msr;
1879 int bus, mult, freq;
1880
1881 msr = rdmsr(MSR_EBC_FREQUENCY_ID);
1882 if (p4_model < 2) {
1883 bus = (msr >> 21) & 0x7;
1884 switch (bus) {
1885 case 0:
1886 bus = 100;
1887 break;
1888 case 1:
1889 bus = 133;
1890 break;
1891 }
1892 } else {
1893 bus = (msr >> 16) & 0x7;
1894 switch (bus) {
1895 case 0:
1896 bus = 100;
1897 break;
1898 case 1:
1899 bus = 133;
1900 break;
1901 case 2:
1902 bus = 200;
1903 break;
1904 }
1905 }
1906 mult = ((msr >> 24) & 0xff);
1907 freq = bus * mult;
1908 /* 133MHz actually means 133.(3)MHz */
1909 if (bus == 133)
1910 freq += mult / 3;
1911
1912 pentium_mhz = freq;
1913 }
1914
1915 void
p3_update_cpuspeed(void)1916 p3_update_cpuspeed(void)
1917 {
1918 u_int64_t msr;
1919 int bus, mult;
1920 const u_int8_t mult_code[] = {
1921 50, 30, 40, 0, 55, 35, 45, 0, 0, 70, 80, 60, 0, 75, 0, 65 };
1922
1923 msr = rdmsr(MSR_EBL_CR_POWERON);
1924 bus = (msr >> 18) & 0x3;
1925 switch (bus) {
1926 case 0:
1927 bus = 66;
1928 break;
1929 case 1:
1930 bus = 133;
1931 break;
1932 case 2:
1933 bus = 100;
1934 break;
1935 }
1936
1937 mult = (msr >> 22) & 0xf;
1938 mult = mult_code[mult];
1939 if (p3_step > 1)
1940 mult += ((msr >> 27) & 0x1) * 40;
1941
1942 pentium_mhz = (bus * mult) / 10;
1943 }
1944 #endif /* I686_CPU */
1945
1946 #if defined(I586_CPU) || defined(I686_CPU)
1947 int
pentium_cpuspeed(int * freq)1948 pentium_cpuspeed(int *freq)
1949 {
1950 *freq = pentium_mhz;
1951 return (0);
1952 }
1953 #endif
1954 #endif /* !SMALL_KERNEL */
1955
1956 /*
1957 * Send an interrupt to process.
1958 *
1959 * Stack is set up to allow sigcode stored
1960 * in u. to call routine, followed by kcall
1961 * to sigreturn routine below. After sigreturn
1962 * resets the signal mask, the stack, and the
1963 * frame pointer, it returns to the user
1964 * specified pc, psl.
1965 */
1966 void
sendsig(catcher,sig,mask,code,type,val)1967 sendsig(catcher, sig, mask, code, type, val)
1968 sig_t catcher;
1969 int sig, mask;
1970 u_long code;
1971 int type;
1972 union sigval val;
1973 {
1974 struct proc *p = curproc;
1975 struct pmap *pmap = vm_map_pmap(&p->p_vmspace->vm_map);
1976 struct trapframe *tf = p->p_md.md_regs;
1977 struct sigframe *fp, frame;
1978 struct sigacts *psp = p->p_sigacts;
1979 int oonstack = psp->ps_sigstk.ss_flags & SS_ONSTACK;
1980
1981 /*
1982 * Build the argument list for the signal handler.
1983 */
1984 frame.sf_signum = sig;
1985
1986 /*
1987 * Allocate space for the signal handler context.
1988 */
1989 if ((psp->ps_flags & SAS_ALTSTACK) && !oonstack &&
1990 (psp->ps_sigonstack & sigmask(sig))) {
1991 fp = (struct sigframe *)(psp->ps_sigstk.ss_sp +
1992 psp->ps_sigstk.ss_size - sizeof(struct sigframe));
1993 psp->ps_sigstk.ss_flags |= SS_ONSTACK;
1994 } else {
1995 fp = (struct sigframe *)tf->tf_esp - 1;
1996 }
1997
1998 frame.sf_scp = &fp->sf_sc;
1999 frame.sf_sip = NULL;
2000 frame.sf_handler = catcher;
2001
2002 /*
2003 * Build the signal context to be used by sigreturn.
2004 */
2005 frame.sf_sc.sc_err = tf->tf_err;
2006 frame.sf_sc.sc_trapno = tf->tf_trapno;
2007 frame.sf_sc.sc_onstack = oonstack;
2008 frame.sf_sc.sc_mask = mask;
2009 #ifdef VM86
2010 if (tf->tf_eflags & PSL_VM) {
2011 frame.sf_sc.sc_gs = tf->tf_vm86_gs;
2012 frame.sf_sc.sc_fs = tf->tf_vm86_fs;
2013 frame.sf_sc.sc_es = tf->tf_vm86_es;
2014 frame.sf_sc.sc_ds = tf->tf_vm86_ds;
2015 frame.sf_sc.sc_eflags = get_vflags(p);
2016 } else
2017 #endif
2018 {
2019 __asm("movw %%gs,%w0" : "=r" (frame.sf_sc.sc_gs));
2020 __asm("movw %%fs,%w0" : "=r" (frame.sf_sc.sc_fs));
2021 frame.sf_sc.sc_es = tf->tf_es;
2022 frame.sf_sc.sc_ds = tf->tf_ds;
2023 frame.sf_sc.sc_eflags = tf->tf_eflags;
2024 }
2025 frame.sf_sc.sc_edi = tf->tf_edi;
2026 frame.sf_sc.sc_esi = tf->tf_esi;
2027 frame.sf_sc.sc_ebp = tf->tf_ebp;
2028 frame.sf_sc.sc_ebx = tf->tf_ebx;
2029 frame.sf_sc.sc_edx = tf->tf_edx;
2030 frame.sf_sc.sc_ecx = tf->tf_ecx;
2031 frame.sf_sc.sc_eax = tf->tf_eax;
2032 frame.sf_sc.sc_eip = tf->tf_eip;
2033 frame.sf_sc.sc_cs = tf->tf_cs;
2034 frame.sf_sc.sc_esp = tf->tf_esp;
2035 frame.sf_sc.sc_ss = tf->tf_ss;
2036
2037 if (psp->ps_siginfo & sigmask(sig)) {
2038 frame.sf_sip = &fp->sf_si;
2039 initsiginfo(&frame.sf_si, sig, code, type, val);
2040 #ifdef VM86
2041 if (sig == SIGURG) /* VM86 userland trap */
2042 frame.sf_si.si_trapno = code;
2043 #endif
2044 }
2045
2046 /* XXX don't copyout siginfo if not needed? */
2047 if (copyout(&frame, fp, sizeof(frame)) != 0) {
2048 /*
2049 * Process has trashed its stack; give it an illegal
2050 * instruction to halt it in its tracks.
2051 */
2052 sigexit(p, SIGILL);
2053 /* NOTREACHED */
2054 }
2055
2056 /*
2057 * Build context to run handler in.
2058 */
2059 __asm("movw %w0,%%gs" : : "r" (GSEL(GUDATA_SEL, SEL_UPL)));
2060 __asm("movw %w0,%%fs" : : "r" (GSEL(GUDATA_SEL, SEL_UPL)));
2061 tf->tf_es = GSEL(GUDATA_SEL, SEL_UPL);
2062 tf->tf_ds = GSEL(GUDATA_SEL, SEL_UPL);
2063 tf->tf_eip = p->p_sigcode;
2064 tf->tf_cs = pmap->pm_hiexec > I386_MAX_EXE_ADDR ?
2065 GSEL(GUCODE1_SEL, SEL_UPL) : GSEL(GUCODE_SEL, SEL_UPL);
2066 tf->tf_eflags &= ~(PSL_D|PSL_T|PSL_VM|PSL_AC);
2067 tf->tf_esp = (int)fp;
2068 tf->tf_ss = GSEL(GUDATA_SEL, SEL_UPL);
2069 }
2070
2071 /*
2072 * System call to cleanup state after a signal
2073 * has been taken. Reset signal mask and
2074 * stack state from context left by sendsig (above).
2075 * Return to previous pc and psl as specified by
2076 * context left by sendsig. Check carefully to
2077 * make sure that the user has not modified the
2078 * psl to gain improper privileges or to cause
2079 * a machine fault.
2080 */
2081 int
sys_sigreturn(p,v,retval)2082 sys_sigreturn(p, v, retval)
2083 struct proc *p;
2084 void *v;
2085 register_t *retval;
2086 {
2087 struct sys_sigreturn_args /* {
2088 syscallarg(struct sigcontext *) sigcntxp;
2089 } */ *uap = v;
2090 struct sigcontext *scp, context;
2091 register struct trapframe *tf;
2092
2093 tf = p->p_md.md_regs;
2094
2095 /*
2096 * The trampoline code hands us the context.
2097 * It is unsafe to keep track of it ourselves, in the event that a
2098 * program jumps out of a signal handler.
2099 */
2100 scp = SCARG(uap, sigcntxp);
2101 if (copyin((caddr_t)scp, &context, sizeof(*scp)) != 0)
2102 return (EFAULT);
2103
2104 /*
2105 * Restore signal context.
2106 */
2107 #ifdef VM86
2108 if (context.sc_eflags & PSL_VM) {
2109 tf->tf_vm86_gs = context.sc_gs;
2110 tf->tf_vm86_fs = context.sc_fs;
2111 tf->tf_vm86_es = context.sc_es;
2112 tf->tf_vm86_ds = context.sc_ds;
2113 set_vflags(p, context.sc_eflags);
2114 } else
2115 #endif
2116 {
2117 /*
2118 * Check for security violations. If we're returning to
2119 * protected mode, the CPU will validate the segment registers
2120 * automatically and generate a trap on violations. We handle
2121 * the trap, rather than doing all of the checking here.
2122 */
2123 if (((context.sc_eflags ^ tf->tf_eflags) & PSL_USERSTATIC) != 0 ||
2124 !USERMODE(context.sc_cs, context.sc_eflags))
2125 return (EINVAL);
2126
2127 /* %fs and %gs were restored by the trampoline. */
2128 tf->tf_es = context.sc_es;
2129 tf->tf_ds = context.sc_ds;
2130 tf->tf_eflags = context.sc_eflags;
2131 }
2132 tf->tf_edi = context.sc_edi;
2133 tf->tf_esi = context.sc_esi;
2134 tf->tf_ebp = context.sc_ebp;
2135 tf->tf_ebx = context.sc_ebx;
2136 tf->tf_edx = context.sc_edx;
2137 tf->tf_ecx = context.sc_ecx;
2138 tf->tf_eax = context.sc_eax;
2139 tf->tf_eip = context.sc_eip;
2140 tf->tf_cs = context.sc_cs;
2141 tf->tf_esp = context.sc_esp;
2142 tf->tf_ss = context.sc_ss;
2143
2144 if (context.sc_onstack & 01)
2145 p->p_sigacts->ps_sigstk.ss_flags |= SS_ONSTACK;
2146 else
2147 p->p_sigacts->ps_sigstk.ss_flags &= ~SS_ONSTACK;
2148 p->p_sigmask = context.sc_mask & ~sigcantmask;
2149
2150 return (EJUSTRETURN);
2151 }
2152
2153 int waittime = -1;
2154 struct pcb dumppcb;
2155
2156 void
boot(howto)2157 boot(howto)
2158 int howto;
2159 {
2160 if (cold) {
2161 /*
2162 * If the system is cold, just halt, unless the user
2163 * explicitly asked for reboot.
2164 */
2165 if ((howto & RB_USERREQ) == 0)
2166 howto |= RB_HALT;
2167 goto haltsys;
2168 }
2169
2170 boothowto = howto;
2171 if ((howto & RB_NOSYNC) == 0 && waittime < 0) {
2172 extern struct proc proc0;
2173
2174 /* protect against curproc->p_stats.foo refs in sync() XXX */
2175 if (curproc == NULL)
2176 curproc = &proc0;
2177
2178 waittime = 0;
2179 vfs_shutdown();
2180 /*
2181 * If we've been adjusting the clock, the todr
2182 * will be out of synch; adjust it now.
2183 */
2184 if ((howto & RB_TIMEBAD) == 0) {
2185 resettodr();
2186 } else {
2187 printf("WARNING: not updating battery clock\n");
2188 }
2189 }
2190
2191 /* Disable interrupts. */
2192 splhigh();
2193
2194 /* Do a dump if requested. */
2195 if (howto & RB_DUMP)
2196 dumpsys();
2197
2198 haltsys:
2199 doshutdownhooks();
2200
2201 if (howto & RB_HALT) {
2202 #if NAPM > 0
2203 if (howto & RB_POWERDOWN) {
2204 int rv;
2205
2206 printf("\nAttempting to power down... %X\n",
2207 arc4random());
2208 /*
2209 * Turn off, if we can. But try to turn disk off and
2210 * wait a bit first--some disk drives are slow to
2211 * clean up and users have reported disk corruption.
2212 *
2213 * If apm_set_powstate() fails the first time, don't
2214 * try to turn the system off.
2215 */
2216 delay(500000);
2217 /*
2218 * It's been reported that the following bit of code
2219 * is required on most systems <mickey@openbsd.org>
2220 * but cause powerdown problem on other systems
2221 * <smcho@tsp.korea.ac.kr>. Use sysctl to set
2222 * apmhalt to a non-zero value to skip the offending
2223 * code.
2224 */
2225 if (!cpu_apmhalt) {
2226 apm_set_powstate(APM_DEV_DISK(0xff),
2227 APM_SYS_OFF);
2228 delay(500000);
2229 }
2230 rv = apm_set_powstate(APM_DEV_DISK(0xff), APM_SYS_OFF);
2231 if (rv == 0 || rv == ENXIO) {
2232 delay(500000);
2233 (void) apm_set_powstate(APM_DEV_ALLDEVS,
2234 APM_SYS_OFF);
2235 }
2236 }
2237 #endif
2238 printf("\n");
2239 printf("The operating system has halted. %X\n", arc4random());
2240 printf("Please press any key to reboot.\n\n");
2241 cngetc();
2242 }
2243
2244 printf("rebooting... %X\n", arc4random());
2245 cpu_reset();
2246 /*NOTREACHED*/
2247 }
2248
2249 /*
2250 * This is called by configure to set dumplo and dumpsize.
2251 * Dumps always skip the first block of disk space
2252 * in case there might be a disk label stored there.
2253 * If there is extra space, put dump at the end to
2254 * reduce the chance that swapping trashes it.
2255 */
2256 void
dumpconf()2257 dumpconf()
2258 {
2259 int nblks; /* size of dump area */
2260 register int maj, i;
2261
2262 if (dumpdev == NODEV)
2263 return;
2264 maj = major(dumpdev);
2265 if (maj < 0 || maj >= nblkdev)
2266 panic("dumpconf: bad dumpdev=0x%x", dumpdev);
2267 if (bdevsw[maj].d_psize == NULL)
2268 return;
2269 nblks = (*bdevsw[maj].d_psize)(dumpdev);
2270 if (nblks <= ctod(1))
2271 return;
2272
2273 /* Always skip the first block, in case there is a label there. */
2274 if (dumplo < ctod(1))
2275 dumplo = ctod(1);
2276
2277 for (i = 0; i < ndumpmem; i++)
2278 dumpsize = max(dumpsize, dumpmem[i].end);
2279
2280 /* Put dump at end of partition, and make it fit. */
2281 if (dumpsize > dtoc(nblks - dumplo - 1))
2282 dumpsize = dtoc(nblks - dumplo - 1);
2283 if (dumplo < nblks - ctod(dumpsize) - 1)
2284 dumplo = nblks - ctod(dumpsize) - 1;
2285 }
2286
2287 /*
2288 * cpu_dump: dump machine-dependent kernel core dump headers.
2289 */
2290 int
cpu_dump()2291 cpu_dump()
2292 {
2293 int (*dump)(dev_t, daddr_t, caddr_t, size_t);
2294 long buf[dbtob(1) / sizeof (long)];
2295 kcore_seg_t *segp;
2296
2297 dump = bdevsw[major(dumpdev)].d_dump;
2298
2299 segp = (kcore_seg_t *)buf;
2300
2301 /*
2302 * Generate a segment header.
2303 */
2304 CORE_SETMAGIC(*segp, KCORE_MAGIC, MID_MACHINE, CORE_CPU);
2305 segp->c_size = dbtob(1) - ALIGN(sizeof(*segp));
2306
2307 return (dump(dumpdev, dumplo, (caddr_t)buf, dbtob(1)));
2308 }
2309
2310 /*
2311 * Doadump comes here after turning off memory management and
2312 * getting on the dump stack, either when called above, or by
2313 * the auto-restart code.
2314 */
2315 static vaddr_t dumpspace;
2316
2317 vaddr_t
reserve_dumppages(vaddr_t p)2318 reserve_dumppages(vaddr_t p)
2319 {
2320
2321 dumpspace = p;
2322 return (p + PAGE_SIZE);
2323 }
2324
2325 void
dumpsys()2326 dumpsys()
2327 {
2328 register u_int i, j, npg;
2329 register int maddr;
2330 daddr_t blkno;
2331 int (*dump)(dev_t, daddr_t, caddr_t, size_t);
2332 int error;
2333 register char *str;
2334 extern int msgbufmapped;
2335
2336 /* Save registers. */
2337 savectx(&dumppcb);
2338
2339 msgbufmapped = 0; /* don't record dump msgs in msgbuf */
2340 if (dumpdev == NODEV)
2341 return;
2342
2343 /*
2344 * For dumps during autoconfiguration,
2345 * if dump device has already configured...
2346 */
2347 if (dumpsize == 0)
2348 dumpconf();
2349 if (dumplo < 0)
2350 return;
2351 printf("\ndumping to dev %x, offset %ld\n", dumpdev, dumplo);
2352
2353 error = (*bdevsw[major(dumpdev)].d_psize)(dumpdev);
2354 printf("dump ");
2355 if (error == -1) {
2356 printf("area unavailable\n");
2357 return;
2358 }
2359
2360 #if 0 /* XXX this doesn't work. grr. */
2361 /* toss any characters present prior to dump */
2362 while (sget() != NULL); /*syscons and pccons differ */
2363 #endif
2364
2365 /* scan through the dumpmem list */
2366 dump = bdevsw[major(dumpdev)].d_dump;
2367 error = cpu_dump();
2368 for (i = 0; !error && i < ndumpmem; i++) {
2369
2370 npg = dumpmem[i].end - dumpmem[i].start;
2371 maddr = ctob(dumpmem[i].start);
2372 blkno = dumplo + btodb(maddr) + 1;
2373 #if 0
2374 printf("(%d %ld %d) ", maddr, blkno, npg);
2375 #endif
2376 for (j = npg; j--; maddr += NBPG, blkno += btodb(NBPG)) {
2377
2378 /* Print out how many MBs we have more to go. */
2379 if (dbtob(blkno - dumplo) % (1024 * 1024) < NBPG)
2380 printf("%d ",
2381 (ctob(dumpsize) - maddr) / (1024 * 1024));
2382 #if 0
2383 printf("(%x %d) ", maddr, blkno);
2384 #endif
2385 pmap_enter(pmap_kernel(), dumpspace, maddr,
2386 VM_PROT_READ, PMAP_WIRED);
2387 if ((error = (*dump)(dumpdev, blkno,
2388 (caddr_t)dumpspace, NBPG)))
2389 break;
2390
2391 #if 0 /* XXX this doesn't work. grr. */
2392 /* operator aborting dump? */
2393 if (sget() != NULL) {
2394 error = EINTR;
2395 break;
2396 }
2397 #endif
2398 }
2399 }
2400
2401 switch (error) {
2402
2403 case 0: str = "succeeded\n\n"; break;
2404 case ENXIO: str = "device bad\n\n"; break;
2405 case EFAULT: str = "device not ready\n\n"; break;
2406 case EINVAL: str = "area improper\n\n"; break;
2407 case EIO: str = "i/o error\n\n"; break;
2408 case EINTR: str = "aborted from console\n\n"; break;
2409 default: str = "error %d\n\n"; break;
2410 }
2411 printf(str, error);
2412
2413 delay(5000000); /* 5 seconds */
2414 }
2415
2416 #ifdef HZ
2417 /*
2418 * If HZ is defined we use this code, otherwise the code in
2419 * /sys/arch/i386/i386/microtime.s is used. The other code only works
2420 * for HZ=100.
2421 */
2422 void
microtime(tvp)2423 microtime(tvp)
2424 register struct timeval *tvp;
2425 {
2426 int s = splhigh();
2427
2428 *tvp = time;
2429 tvp->tv_usec += tick;
2430 splx(s);
2431 while (tvp->tv_usec >= 1000000) {
2432 tvp->tv_sec++;
2433 tvp->tv_usec -= 1000000;
2434 }
2435 }
2436 #endif /* HZ */
2437
2438 /*
2439 * Clear registers on exec
2440 */
2441 void
setregs(p,pack,stack,retval)2442 setregs(p, pack, stack, retval)
2443 struct proc *p;
2444 struct exec_package *pack;
2445 u_long stack;
2446 register_t *retval;
2447 {
2448 struct pcb *pcb = &p->p_addr->u_pcb;
2449 struct pmap *pmap = vm_map_pmap(&p->p_vmspace->vm_map);
2450 struct trapframe *tf = p->p_md.md_regs;
2451
2452 #if NNPX > 0
2453 /* If we were using the FPU, forget about it. */
2454 if (npxproc == p)
2455 npxdrop();
2456 #endif
2457
2458 #ifdef USER_LDT
2459 pmap_ldt_cleanup(p);
2460 #endif
2461
2462 p->p_md.md_flags &= ~MDP_USEDFPU;
2463 if (i386_use_fxsave) {
2464 pcb->pcb_savefpu.sv_xmm.sv_env.en_cw = __NPXCW__;
2465 pcb->pcb_savefpu.sv_xmm.sv_env.en_mxcsr = __INITIAL_MXCSR__;
2466 } else
2467 pcb->pcb_savefpu.sv_87.sv_env.en_cw = __NPXCW__;
2468
2469 __asm("movw %w0,%%gs" : : "r" (LSEL(LUDATA_SEL, SEL_UPL)));
2470 __asm("movw %w0,%%fs" : : "r" (LSEL(LUDATA_SEL, SEL_UPL)));
2471 tf->tf_es = LSEL(LUDATA_SEL, SEL_UPL);
2472 tf->tf_ds = LSEL(LUDATA_SEL, SEL_UPL);
2473 tf->tf_ebp = 0;
2474 tf->tf_ebx = (int)PS_STRINGS;
2475 tf->tf_eip = pack->ep_entry;
2476 tf->tf_cs = pmap->pm_hiexec > I386_MAX_EXE_ADDR ?
2477 LSEL(LUCODE1_SEL, SEL_UPL) : LSEL(LUCODE_SEL, SEL_UPL);
2478 tf->tf_eflags = PSL_USERSET;
2479 tf->tf_esp = stack;
2480 tf->tf_ss = LSEL(LUDATA_SEL, SEL_UPL);
2481
2482 retval[1] = 0;
2483 }
2484
2485 /*
2486 * Initialize segments and descriptor tables
2487 */
2488
2489 union descriptor gdt[NGDT];
2490 union descriptor ldt[NLDT];
2491 struct gate_descriptor idt_region[NIDT];
2492 struct gate_descriptor *idt = idt_region;
2493
2494 extern struct user *proc0paddr;
2495
2496 void
setgate(gd,func,args,type,dpl,seg)2497 setgate(gd, func, args, type, dpl, seg)
2498 struct gate_descriptor *gd;
2499 void *func;
2500 int args, type, dpl, seg;
2501 {
2502
2503 gd->gd_looffset = (int)func;
2504 gd->gd_selector = GSEL(seg, SEL_KPL);
2505 gd->gd_stkcpy = args;
2506 gd->gd_xx = 0;
2507 gd->gd_type = type;
2508 gd->gd_dpl = dpl;
2509 gd->gd_p = 1;
2510 gd->gd_hioffset = (int)func >> 16;
2511 }
2512
2513 void
setregion(rd,base,limit)2514 setregion(rd, base, limit)
2515 struct region_descriptor *rd;
2516 void *base;
2517 size_t limit;
2518 {
2519
2520 rd->rd_limit = (int)limit;
2521 rd->rd_base = (int)base;
2522 }
2523
2524 void
setsegment(sd,base,limit,type,dpl,def32,gran)2525 setsegment(sd, base, limit, type, dpl, def32, gran)
2526 struct segment_descriptor *sd;
2527 void *base;
2528 size_t limit;
2529 int type, dpl, def32, gran;
2530 {
2531
2532 sd->sd_lolimit = (int)limit;
2533 sd->sd_lobase = (int)base;
2534 sd->sd_type = type;
2535 sd->sd_dpl = dpl;
2536 sd->sd_p = 1;
2537 sd->sd_hilimit = (int)limit >> 16;
2538 sd->sd_xx = 0;
2539 sd->sd_def32 = def32;
2540 sd->sd_gran = gran;
2541 sd->sd_hibase = (int)base >> 24;
2542 }
2543
2544 #define IDTVEC(name) __CONCAT(X, name)
2545 extern int IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl),
2546 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(dble), IDTVEC(fpusegm),
2547 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot), IDTVEC(page),
2548 IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align), IDTVEC(syscall),
2549 IDTVEC(osyscall);
2550
2551 #if defined(I586_CPU)
2552 extern int IDTVEC(f00f_redirect);
2553
2554 int cpu_f00f_bug = 0;
2555
2556 void
fix_f00f(void)2557 fix_f00f(void)
2558 {
2559 struct region_descriptor region;
2560 vaddr_t va;
2561 pt_entry_t *pte;
2562 void *p;
2563
2564 /* Allocate two new pages */
2565 va = uvm_km_zalloc(kernel_map, NBPG*2);
2566 p = (void *)(va + NBPG - 7*sizeof(*idt));
2567
2568 /* Copy over old IDT */
2569 bcopy(idt, p, sizeof(idt_region));
2570 idt = p;
2571
2572 /* Fix up paging redirect */
2573 setgate(&idt[ 14], &IDTVEC(f00f_redirect), 0, SDT_SYS386TGT,
2574 SEL_KPL, GCODE_SEL);
2575
2576 /* Map first page RO */
2577 pte = PTE_BASE + i386_btop(va);
2578 *pte &= ~PG_RW;
2579
2580 /* Reload idtr */
2581 setregion(®ion, idt, sizeof(idt_region) - 1);
2582 lidt(®ion);
2583
2584 /* Tell the rest of the world */
2585 cpu_f00f_bug = 1;
2586 }
2587 #endif
2588
2589 void
init386(paddr_t first_avail)2590 init386(paddr_t first_avail)
2591 {
2592 int i;
2593 struct region_descriptor region;
2594 bios_memmap_t *im;
2595
2596 proc0.p_addr = proc0paddr;
2597 curpcb = &proc0.p_addr->u_pcb;
2598
2599 /*
2600 * Initialize the I/O port and I/O mem extent maps.
2601 * Note: we don't have to check the return value since
2602 * creation of a fixed extent map will never fail (since
2603 * descriptor storage has already been allocated).
2604 *
2605 * N.B. The iomem extent manages _all_ physical addresses
2606 * on the machine. When the amount of RAM is found, the two
2607 * extents of RAM are allocated from the map (0 -> ISA hole
2608 * and end of ISA hole -> end of RAM).
2609 */
2610 ioport_ex = extent_create("ioport", 0x0, 0xffff, M_DEVBUF,
2611 (caddr_t)ioport_ex_storage, sizeof(ioport_ex_storage),
2612 EX_NOCOALESCE|EX_NOWAIT);
2613 iomem_ex = extent_create("iomem", 0x0, 0xffffffff, M_DEVBUF,
2614 (caddr_t)iomem_ex_storage, sizeof(iomem_ex_storage),
2615 EX_NOCOALESCE|EX_NOWAIT);
2616
2617 /* make gdt gates and memory segments */
2618 setsegment(&gdt[GCODE_SEL].sd, 0, 0xfffff, SDT_MEMERA, SEL_KPL, 1, 1);
2619 setsegment(&gdt[GICODE_SEL].sd, 0, 0xfffff, SDT_MEMERA, SEL_KPL, 1, 1);
2620 setsegment(&gdt[GDATA_SEL].sd, 0, 0xfffff, SDT_MEMRWA, SEL_KPL, 1, 1);
2621 setsegment(&gdt[GLDT_SEL].sd, ldt, sizeof(ldt) - 1, SDT_SYSLDT, SEL_KPL,
2622 0, 0);
2623 setsegment(&gdt[GUCODE1_SEL].sd, 0, i386_btop(VM_MAXUSER_ADDRESS) - 1,
2624 SDT_MEMERA, SEL_UPL, 1, 1);
2625 setsegment(&gdt[GUCODE_SEL].sd, 0, i386_btop(I386_MAX_EXE_ADDR) - 1,
2626 SDT_MEMERA, SEL_UPL, 1, 1);
2627 setsegment(&gdt[GUDATA_SEL].sd, 0, i386_btop(VM_MAXUSER_ADDRESS) - 1,
2628 SDT_MEMRWA, SEL_UPL, 1, 1);
2629
2630 /* make ldt gates and memory segments */
2631 setgate(&ldt[LSYS5CALLS_SEL].gd, &IDTVEC(osyscall), 1, SDT_SYS386CGT,
2632 SEL_UPL, GCODE_SEL);
2633 ldt[LUCODE1_SEL] = gdt[GUCODE1_SEL];
2634 ldt[LUCODE_SEL] = gdt[GUCODE_SEL];
2635 ldt[LUDATA_SEL] = gdt[GUDATA_SEL];
2636 ldt[LBSDICALLS_SEL] = ldt[LSYS5CALLS_SEL];
2637
2638 /* exceptions */
2639 setgate(&idt[ 0], &IDTVEC(div), 0, SDT_SYS386TGT, SEL_KPL, GCODE_SEL);
2640 setgate(&idt[ 1], &IDTVEC(dbg), 0, SDT_SYS386TGT, SEL_KPL, GCODE_SEL);
2641 setgate(&idt[ 2], &IDTVEC(nmi), 0, SDT_SYS386TGT, SEL_KPL, GCODE_SEL);
2642 setgate(&idt[ 3], &IDTVEC(bpt), 0, SDT_SYS386TGT, SEL_UPL, GCODE_SEL);
2643 setgate(&idt[ 4], &IDTVEC(ofl), 0, SDT_SYS386TGT, SEL_UPL, GCODE_SEL);
2644 setgate(&idt[ 5], &IDTVEC(bnd), 0, SDT_SYS386TGT, SEL_KPL, GCODE_SEL);
2645 setgate(&idt[ 6], &IDTVEC(ill), 0, SDT_SYS386TGT, SEL_KPL, GCODE_SEL);
2646 setgate(&idt[ 7], &IDTVEC(dna), 0, SDT_SYS386TGT, SEL_KPL, GCODE_SEL);
2647 setgate(&idt[ 8], &IDTVEC(dble), 0, SDT_SYS386TGT, SEL_KPL, GCODE_SEL);
2648 setgate(&idt[ 9], &IDTVEC(fpusegm), 0, SDT_SYS386TGT, SEL_KPL, GCODE_SEL);
2649 setgate(&idt[ 10], &IDTVEC(tss), 0, SDT_SYS386TGT, SEL_KPL, GCODE_SEL);
2650 setgate(&idt[ 11], &IDTVEC(missing), 0, SDT_SYS386TGT, SEL_KPL, GCODE_SEL);
2651 setgate(&idt[ 12], &IDTVEC(stk), 0, SDT_SYS386TGT, SEL_KPL, GCODE_SEL);
2652 setgate(&idt[ 13], &IDTVEC(prot), 0, SDT_SYS386TGT, SEL_KPL, GCODE_SEL);
2653 setgate(&idt[ 14], &IDTVEC(page), 0, SDT_SYS386TGT, SEL_KPL, GCODE_SEL);
2654 setgate(&idt[ 15], &IDTVEC(rsvd), 0, SDT_SYS386TGT, SEL_KPL, GCODE_SEL);
2655 setgate(&idt[ 16], &IDTVEC(fpu), 0, SDT_SYS386TGT, SEL_KPL, GCODE_SEL);
2656 setgate(&idt[ 17], &IDTVEC(align), 0, SDT_SYS386TGT, SEL_KPL, GCODE_SEL);
2657 setgate(&idt[ 18], &IDTVEC(rsvd), 0, SDT_SYS386TGT, SEL_KPL, GCODE_SEL);
2658 for (i = 19; i < NIDT; i++)
2659 setgate(&idt[i], &IDTVEC(rsvd), 0, SDT_SYS386TGT, SEL_KPL, GCODE_SEL);
2660 setgate(&idt[128], &IDTVEC(syscall), 0, SDT_SYS386TGT, SEL_UPL, GCODE_SEL);
2661
2662 setregion(®ion, gdt, sizeof(gdt) - 1);
2663 lgdt(®ion);
2664 setregion(®ion, idt, sizeof(idt_region) - 1);
2665 lidt(®ion);
2666
2667 #if NISA > 0
2668 isa_defaultirq();
2669 #endif
2670
2671 consinit(); /* XXX SHOULD NOT BE DONE HERE */
2672 /* XXX here, until we can use bios for printfs */
2673
2674 /*
2675 * Saving SSE registers won't work if the save area isn't
2676 * 16-byte aligned.
2677 */
2678 if (offsetof(struct user, u_pcb.pcb_savefpu) & 0xf)
2679 panic("init386: pcb_savefpu not 16-byte aligned");
2680
2681 /* call pmap initialization to make new kernel address space */
2682 pmap_bootstrap((vaddr_t)atdevbase + IOM_SIZE);
2683
2684 /*
2685 * Boot arguments are in a single page specified by /boot.
2686 *
2687 * We require the "new" vector form, as well as memory ranges
2688 * to be given in bytes rather than KB.
2689 */
2690 if ((bootapiver & (BAPIV_VECTOR | BAPIV_BMEMMAP)) ==
2691 (BAPIV_VECTOR | BAPIV_BMEMMAP)) {
2692 if (bootargc > NBPG)
2693 panic("too many boot args");
2694
2695 if (extent_alloc_region(iomem_ex, (paddr_t)bootargv, bootargc,
2696 EX_NOWAIT))
2697 panic("cannot reserve /boot args memory");
2698
2699 pmap_enter(pmap_kernel(), (vaddr_t)bootargp, (paddr_t)bootargv,
2700 VM_PROT_READ|VM_PROT_WRITE,
2701 VM_PROT_READ|VM_PROT_WRITE|PMAP_WIRED);
2702
2703 bios_getopt();
2704
2705 } else
2706 panic("/boot too old: upgrade!");
2707
2708 #ifdef DIAGNOSTIC
2709 if (bios_memmap == NULL)
2710 panic("no BIOS memory map supplied");
2711 #endif
2712
2713 /*
2714 * account all the memory passed in the map from /boot
2715 * calculate avail_end and count the physmem.
2716 */
2717 avail_end = 0;
2718 physmem = 0;
2719 #ifdef DEBUG
2720 printf("memmap:");
2721 #endif
2722 for(i = 0, im = bios_memmap; im->type != BIOS_MAP_END; im++)
2723 if (im->type == BIOS_MAP_FREE) {
2724 register paddr_t a, e;
2725
2726 a = i386_round_page(im->addr);
2727 e = i386_trunc_page(im->addr + im->size);
2728 /* skip first four pages */
2729 if (a < 4 * NBPG)
2730 a = 4 * NBPG;
2731 #ifdef DEBUG
2732 printf(" %u-%u", a, e);
2733 #endif
2734
2735 /* skip shorter than page regions */
2736 if (a >= e || (e - a) < NBPG) {
2737 #ifdef DEBUG
2738 printf("-S");
2739 #endif
2740 continue;
2741 }
2742 if ((a > IOM_BEGIN && a < IOM_END) ||
2743 (e > IOM_BEGIN && e < IOM_END)) {
2744 #ifdef DEBUG
2745 printf("-I");
2746 #endif
2747 continue;
2748 }
2749
2750 if (extent_alloc_region(iomem_ex, a, e - a, EX_NOWAIT))
2751 /* XXX What should we do? */
2752 printf("\nWARNING: CAN'T ALLOCATE RAM (%lx-%lx)"
2753 " FROM IOMEM EXTENT MAP!\n", (unsigned long) a,
2754 (unsigned long) e);
2755
2756 physmem += atop(e - a);
2757 dumpmem[i].start = atop(a);
2758 dumpmem[i].end = atop(e);
2759 i++;
2760 avail_end = max(avail_end, e);
2761 }
2762
2763 ndumpmem = i;
2764 avail_end -= i386_round_page(MSGBUFSIZE);
2765
2766 #ifdef DEBUG
2767 printf(": %lx\n", avail_end);
2768 #endif
2769 if (physmem < atop(4 * 1024 * 1024)) {
2770 printf("\awarning: too little memory available;"
2771 "running in degraded mode\npress a key to confirm\n\n");
2772 cngetc();
2773 }
2774
2775 #ifdef DEBUG
2776 printf("physload: ");
2777 #endif
2778 for (i = 0; i < ndumpmem; i++) {
2779 paddr_t a, e;
2780 paddr_t lim;
2781
2782 a = dumpmem[i].start;
2783 e = dumpmem[i].end;
2784 if (a < atop(first_avail) && e > atop(first_avail))
2785 a = atop(first_avail);
2786 if (e > atop(avail_end))
2787 e = atop(avail_end);
2788
2789 if (a < e) {
2790 if (a < atop(16 * 1024 * 1024)) {
2791 lim = MIN(atop(16 * 1024 * 1024), e);
2792 #ifdef DEBUG
2793 printf(" %x-%x (<16M)", a, lim);
2794 #endif
2795 uvm_page_physload(a, lim, a, lim,
2796 VM_FREELIST_FIRST16);
2797 if (e > lim) {
2798 #ifdef DEBUG
2799 printf(" %x-%x", lim, e);
2800 #endif
2801 uvm_page_physload(lim, e, lim, e,
2802 VM_FREELIST_DEFAULT);
2803 }
2804 } else {
2805 #ifdef DEBUG
2806 printf(" %x-%x", a, e);
2807 #endif
2808 uvm_page_physload(a, e, a, e,
2809 VM_FREELIST_DEFAULT);
2810 }
2811 }
2812 }
2813 #ifdef DEBUG
2814 printf("\n");
2815 #endif
2816 tlbflush();
2817 #if 0
2818 #if NISADMA > 0
2819 /*
2820 * Some motherboards/BIOSes remap the 384K of RAM that would
2821 * normally be covered by the ISA hole to the end of memory
2822 * so that it can be used. However, on a 16M system, this
2823 * would cause bounce buffers to be allocated and used.
2824 * This is not desirable behaviour, as more than 384K of
2825 * bounce buffers might be allocated. As a work-around,
2826 * we round memory down to the nearest 1M boundary if
2827 * we're using any isadma devices and the remapped memory
2828 * is what puts us over 16M.
2829 */
2830 if (extmem > (15*1024) && extmem < (16*1024)) {
2831 printf("Warning: ignoring %uK of remapped memory\n",
2832 extmem - (15*1024U));
2833 extmem = (15*1024);
2834 }
2835 #endif
2836 #endif
2837
2838 #ifdef DDB
2839 db_machine_init();
2840 ddb_init();
2841 if (boothowto & RB_KDB)
2842 Debugger();
2843 #endif
2844 #ifdef KGDB
2845 kgdb_port_init();
2846 if (boothowto & RB_KDB) {
2847 kgdb_debug_init = 1;
2848 kgdb_connect(1);
2849 }
2850 #endif /* KGDB */
2851 }
2852
2853 struct queue {
2854 struct queue *q_next, *q_prev;
2855 };
2856
2857 /*
2858 * insert an element into a queue
2859 */
2860 void
_insque(v1,v2)2861 _insque(v1, v2)
2862 void *v1;
2863 void *v2;
2864 {
2865 register struct queue *elem = v1, *head = v2;
2866 register struct queue *next;
2867
2868 next = head->q_next;
2869 elem->q_next = next;
2870 head->q_next = elem;
2871 elem->q_prev = head;
2872 next->q_prev = elem;
2873 }
2874
2875 /*
2876 * remove an element from a queue
2877 */
2878 void
_remque(v)2879 _remque(v)
2880 void *v;
2881 {
2882 register struct queue *elem = v;
2883 register struct queue *next, *prev;
2884
2885 next = elem->q_next;
2886 prev = elem->q_prev;
2887 next->q_prev = prev;
2888 prev->q_next = next;
2889 elem->q_prev = 0;
2890 }
2891
2892 /*
2893 * cpu_exec_aout_makecmds():
2894 * cpu-dependent a.out format hook for execve().
2895 *
2896 * Determine of the given exec package refers to something which we
2897 * understand and, if so, set up the vmcmds for it.
2898 */
2899 int
cpu_exec_aout_makecmds(p,epp)2900 cpu_exec_aout_makecmds(p, epp)
2901 struct proc *p;
2902 struct exec_package *epp;
2903 {
2904 return ENOEXEC;
2905 }
2906
2907 /*
2908 * consinit:
2909 * initialize the system console.
2910 * XXX - shouldn't deal with this initted thing, but then,
2911 * it shouldn't be called from init386 either.
2912 */
2913 void
consinit()2914 consinit()
2915 {
2916 static int initted;
2917
2918 if (initted)
2919 return;
2920 initted = 1;
2921 cninit();
2922 }
2923
2924 #ifdef KGDB
2925 void
kgdb_port_init()2926 kgdb_port_init()
2927 {
2928
2929 #if (NCOM > 0 || NPCCOM > 0)
2930 if (!strcmp(kgdb_devname, "com") || !strcmp(kgdb_devname, "pccom")) {
2931 bus_space_tag_t tag = I386_BUS_SPACE_IO;
2932 com_kgdb_attach(tag, comkgdbaddr, comkgdbrate, COM_FREQ,
2933 comkgdbmode);
2934 }
2935 #endif
2936 }
2937 #endif /* KGDB */
2938
2939 void
cpu_reset()2940 cpu_reset()
2941 {
2942 struct region_descriptor region;
2943 uint8_t b;
2944
2945 disable_intr();
2946
2947 if (cpuresetfn)
2948 (*cpuresetfn)();
2949
2950 /* Toggle the hardware reset line on the keyboard controller. */
2951 outb(IO_KBD + KBCMDP, KBC_PULSE0);
2952 delay(100000);
2953 outb(IO_KBD + KBCMDP, KBC_PULSE0);
2954 delay(100000);
2955
2956 /*
2957 * Attempt to force a reset via the Reset Control register at
2958 * I/O port 0xcf9. Bit 2 forces a system reset when it
2959 * transitions from 0 to 1. Bit 1 selects the type of reset
2960 * to attempt: 0 selects a "soft" reset, and 1 selects a
2961 * "hard" reset. We try a "hard" reset. The first write sets
2962 * bit 1 to select a "hard" reset and clears bit 2. The
2963 * second write forces a 0 -> 1 transition in bit 2 to trigger
2964 * a reset.
2965 */
2966 outb(0xcf9, 0x2);
2967 outb(0xcf9, 0x6);
2968 delay(500000); /* wait 0.5 sec to see if that did it */
2969
2970 /*
2971 * Attempt to force a reset via the Fast A20 and Init register
2972 * at I/O port 0x92. Bit 1 serves as an alternate A20 gate.
2973 * Bit 0 asserts INIT# when set to 1. We are careful to only
2974 * preserve bit 1 while setting bit 0. We also must clear bit
2975 * 0 before setting it if it isn't already clear.
2976 */
2977 b = inb(0x92);
2978 if (b != 0xff) {
2979 if ((b & 0x1) != 0)
2980 outb(0x92, b & 0xfe);
2981 outb(0x92, b | 0x1);
2982 delay(500000); /* wait 0.5 sec to see if that did it */
2983 }
2984
2985 /*
2986 * Try to cause a triple fault and watchdog reset by setting the
2987 * IDT to point to nothing.
2988 */
2989 bzero((caddr_t)idt, sizeof(idt_region));
2990 setregion(®ion, idt, sizeof(idt_region) - 1);
2991 lidt(®ion);
2992 __asm __volatile("divl %0,%1" : : "q" (0), "a" (0));
2993
2994 #if 1
2995 /*
2996 * Try to cause a triple fault and watchdog reset by unmapping the
2997 * entire address space.
2998 */
2999 bzero((caddr_t)PTD, NBPG);
3000 tlbflush();
3001 #endif
3002
3003 for (;;);
3004 /*NOTREACHED*/
3005 }
3006
3007 /*
3008 * machine dependent system variables.
3009 */
3010 int
cpu_sysctl(name,namelen,oldp,oldlenp,newp,newlen,p)3011 cpu_sysctl(name, namelen, oldp, oldlenp, newp, newlen, p)
3012 int *name;
3013 u_int namelen;
3014 void *oldp;
3015 size_t *oldlenp;
3016 void *newp;
3017 size_t newlen;
3018 struct proc *p;
3019 {
3020 extern char cpu_vendor[];
3021 extern int cpu_id;
3022 #if NAPM > 0
3023 extern int cpu_apmwarn;
3024 #endif
3025 dev_t dev;
3026
3027 switch (name[0]) {
3028 case CPU_CONSDEV:
3029 if (namelen != 1)
3030 return (ENOTDIR); /* overloaded */
3031
3032 if (cn_tab != NULL)
3033 dev = cn_tab->cn_dev;
3034 else
3035 dev = NODEV;
3036 return sysctl_rdstruct(oldp, oldlenp, newp, &dev, sizeof(dev));
3037 #if NBIOS > 0
3038 case CPU_BIOS:
3039 return bios_sysctl(name + 1, namelen - 1, oldp, oldlenp,
3040 newp, newlen, p);
3041 #endif
3042 case CPU_BLK2CHR:
3043 if (namelen != 2)
3044 return (ENOTDIR); /* overloaded */
3045 dev = blktochr((dev_t)name[1]);
3046 return sysctl_rdstruct(oldp, oldlenp, newp, &dev, sizeof(dev));
3047 case CPU_CHR2BLK:
3048 if (namelen != 2)
3049 return (ENOTDIR); /* overloaded */
3050 dev = chrtoblk((dev_t)name[1]);
3051 return sysctl_rdstruct(oldp, oldlenp, newp, &dev, sizeof(dev));
3052 case CPU_ALLOWAPERTURE:
3053 #ifdef APERTURE
3054 if (securelevel > 0)
3055 return (sysctl_rdint(oldp, oldlenp, newp,
3056 allowaperture));
3057 else
3058 return (sysctl_int(oldp, oldlenp, newp, newlen,
3059 &allowaperture));
3060 #else
3061 return (sysctl_rdint(oldp, oldlenp, newp, 0));
3062 #endif
3063 case CPU_CPUVENDOR:
3064 return (sysctl_rdstring(oldp, oldlenp, newp, cpu_vendor));
3065 case CPU_CPUID:
3066 return (sysctl_rdint(oldp, oldlenp, newp, cpu_id));
3067 case CPU_CPUFEATURE:
3068 return (sysctl_rdint(oldp, oldlenp, newp, cpu_feature));
3069 #if NAPM > 0
3070 case CPU_APMWARN:
3071 return (sysctl_int(oldp, oldlenp, newp, newlen, &cpu_apmwarn));
3072 case CPU_APMHALT:
3073 return (sysctl_int(oldp, oldlenp, newp, newlen, &cpu_apmhalt));
3074 #endif
3075 case CPU_KBDRESET:
3076 if (securelevel > 0)
3077 return (sysctl_rdint(oldp, oldlenp, newp,
3078 kbd_reset));
3079 else
3080 return (sysctl_int(oldp, oldlenp, newp, newlen,
3081 &kbd_reset));
3082 #ifdef USER_LDT
3083 case CPU_USERLDT:
3084 return (sysctl_int(oldp, oldlenp, newp, newlen,
3085 &user_ldt_enable));
3086 #endif
3087 case CPU_OSFXSR:
3088 return (sysctl_rdint(oldp, oldlenp, newp, i386_use_fxsave));
3089 case CPU_SSE:
3090 return (sysctl_rdint(oldp, oldlenp, newp, i386_has_sse));
3091 case CPU_SSE2:
3092 return (sysctl_rdint(oldp, oldlenp, newp, i386_has_sse2));
3093 case CPU_XCRYPT:
3094 return (sysctl_rdint(oldp, oldlenp, newp, i386_has_xcrypt));
3095 #ifdef APERTURE
3096 case CPU_APVRESET:
3097 return (sysctl_int(oldp, oldlenp, newp, newlen, &aperture_vreset));
3098 #endif
3099 default:
3100 return (EOPNOTSUPP);
3101 }
3102 /* NOTREACHED */
3103 }
3104
3105 int
bus_space_map(t,bpa,size,cacheable,bshp)3106 bus_space_map(t, bpa, size, cacheable, bshp)
3107 bus_space_tag_t t;
3108 bus_addr_t bpa;
3109 bus_size_t size;
3110 int cacheable;
3111 bus_space_handle_t *bshp;
3112 {
3113 int error;
3114 struct extent *ex;
3115
3116 /*
3117 * Pick the appropriate extent map.
3118 */
3119 switch (t) {
3120 case I386_BUS_SPACE_IO:
3121 ex = ioport_ex;
3122 break;
3123
3124 case I386_BUS_SPACE_MEM:
3125 ex = iomem_ex;
3126 break;
3127
3128 default:
3129 panic("bus_space_map: bad bus space tag");
3130 }
3131
3132 /*
3133 * Before we go any further, let's make sure that this
3134 * region is available.
3135 */
3136 error = extent_alloc_region(ex, bpa, size,
3137 EX_NOWAIT | (ioport_malloc_safe ? EX_MALLOCOK : 0));
3138 if (error)
3139 return (error);
3140
3141 /*
3142 * For I/O space, that's all she wrote.
3143 */
3144 if (t == I386_BUS_SPACE_IO) {
3145 *bshp = bpa;
3146 return (0);
3147 }
3148
3149 if (IOM_BEGIN <= bpa && bpa <= IOM_END) {
3150 *bshp = (bus_space_handle_t)ISA_HOLE_VADDR(bpa);
3151 return (0);
3152 }
3153
3154 /*
3155 * For memory space, map the bus physical address to
3156 * a kernel virtual address.
3157 */
3158 error = bus_mem_add_mapping(bpa, size, cacheable, bshp);
3159 if (error) {
3160 if (extent_free(ex, bpa, size, EX_NOWAIT |
3161 (ioport_malloc_safe ? EX_MALLOCOK : 0))) {
3162 printf("bus_space_map: pa 0x%lx, size 0x%lx\n",
3163 bpa, size);
3164 printf("bus_space_map: can't free region\n");
3165 }
3166 }
3167
3168 return (error);
3169 }
3170
3171 int
_bus_space_map(t,bpa,size,cacheable,bshp)3172 _bus_space_map(t, bpa, size, cacheable, bshp)
3173 bus_space_tag_t t;
3174 bus_addr_t bpa;
3175 bus_size_t size;
3176 int cacheable;
3177 bus_space_handle_t *bshp;
3178 {
3179 /*
3180 * For I/O space, that's all she wrote.
3181 */
3182 if (t == I386_BUS_SPACE_IO) {
3183 *bshp = bpa;
3184 return (0);
3185 }
3186
3187 /*
3188 * For memory space, map the bus physical address to
3189 * a kernel virtual address.
3190 */
3191 return (bus_mem_add_mapping(bpa, size, cacheable, bshp));
3192 }
3193
3194 int
bus_space_alloc(t,rstart,rend,size,alignment,boundary,cacheable,bpap,bshp)3195 bus_space_alloc(t, rstart, rend, size, alignment, boundary, cacheable,
3196 bpap, bshp)
3197 bus_space_tag_t t;
3198 bus_addr_t rstart, rend;
3199 bus_size_t size, alignment, boundary;
3200 int cacheable;
3201 bus_addr_t *bpap;
3202 bus_space_handle_t *bshp;
3203 {
3204 struct extent *ex;
3205 u_long bpa;
3206 int error;
3207
3208 /*
3209 * Pick the appropriate extent map.
3210 */
3211 switch (t) {
3212 case I386_BUS_SPACE_IO:
3213 ex = ioport_ex;
3214 break;
3215
3216 case I386_BUS_SPACE_MEM:
3217 ex = iomem_ex;
3218 break;
3219
3220 default:
3221 panic("bus_space_alloc: bad bus space tag");
3222 }
3223
3224 /*
3225 * Sanity check the allocation against the extent's boundaries.
3226 */
3227 if (rstart < ex->ex_start || rend > ex->ex_end)
3228 panic("bus_space_alloc: bad region start/end");
3229
3230 /*
3231 * Do the requested allocation.
3232 */
3233 error = extent_alloc_subregion(ex, rstart, rend, size, alignment, 0,
3234 boundary, EX_NOWAIT | (ioport_malloc_safe ? EX_MALLOCOK : 0),
3235 &bpa);
3236
3237 if (error)
3238 return (error);
3239
3240 /*
3241 * For I/O space, that's all she wrote.
3242 */
3243 if (t == I386_BUS_SPACE_IO) {
3244 *bshp = *bpap = bpa;
3245 return (0);
3246 }
3247
3248 /*
3249 * For memory space, map the bus physical address to
3250 * a kernel virtual address.
3251 */
3252 error = bus_mem_add_mapping(bpa, size, cacheable, bshp);
3253 if (error) {
3254 if (extent_free(iomem_ex, bpa, size, EX_NOWAIT |
3255 (ioport_malloc_safe ? EX_MALLOCOK : 0))) {
3256 printf("bus_space_alloc: pa 0x%lx, size 0x%lx\n",
3257 bpa, size);
3258 printf("bus_space_alloc: can't free region\n");
3259 }
3260 }
3261
3262 *bpap = bpa;
3263
3264 return (error);
3265 }
3266
3267 int
bus_mem_add_mapping(bpa,size,cacheable,bshp)3268 bus_mem_add_mapping(bpa, size, cacheable, bshp)
3269 bus_addr_t bpa;
3270 bus_size_t size;
3271 int cacheable;
3272 bus_space_handle_t *bshp;
3273 {
3274 u_long pa, endpa;
3275 vaddr_t va;
3276 pt_entry_t *pte;
3277 bus_size_t map_size;
3278
3279 pa = i386_trunc_page(bpa);
3280 endpa = i386_round_page(bpa + size);
3281
3282 #ifdef DIAGNOSTIC
3283 if (endpa <= pa && endpa != 0)
3284 panic("bus_mem_add_mapping: overflow");
3285 #endif
3286
3287 map_size = endpa - pa;
3288
3289 va = uvm_km_valloc(kernel_map, map_size);
3290 if (va == 0)
3291 return (ENOMEM);
3292
3293 *bshp = (bus_space_handle_t)(va + (bpa & PGOFSET));
3294
3295 for (; map_size > 0;
3296 pa += PAGE_SIZE, va += PAGE_SIZE, map_size -= PAGE_SIZE) {
3297 pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE);
3298
3299 /*
3300 * PG_N doesn't exist on 386's, so we assume that
3301 * the mainboard has wired up device space non-cacheable
3302 * on those machines.
3303 */
3304 if (cpu_class != CPUCLASS_386) {
3305 pte = kvtopte(va);
3306 if (cacheable)
3307 *pte &= ~PG_N;
3308 else
3309 *pte |= PG_N;
3310 pmap_update_pg(va);
3311 }
3312 }
3313 pmap_update(pmap_kernel());
3314
3315 return 0;
3316 }
3317
3318 void
bus_space_unmap(t,bsh,size)3319 bus_space_unmap(t, bsh, size)
3320 bus_space_tag_t t;
3321 bus_space_handle_t bsh;
3322 bus_size_t size;
3323 {
3324 struct extent *ex;
3325 u_long va, endva;
3326 bus_addr_t bpa;
3327
3328 /*
3329 * Find the correct extent and bus physical address.
3330 */
3331 if (t == I386_BUS_SPACE_IO) {
3332 ex = ioport_ex;
3333 bpa = bsh;
3334 } else if (t == I386_BUS_SPACE_MEM) {
3335 ex = iomem_ex;
3336 bpa = (bus_addr_t)ISA_PHYSADDR(bsh);
3337 if (IOM_BEGIN <= bpa && bpa <= IOM_END)
3338 goto ok;
3339
3340 va = i386_trunc_page(bsh);
3341 endva = i386_round_page(bsh + size);
3342
3343 #ifdef DIAGNOSTIC
3344 if (endva <= va)
3345 panic("bus_space_unmap: overflow");
3346 #endif
3347
3348 (void) pmap_extract(pmap_kernel(), va, &bpa);
3349 bpa += (bsh & PGOFSET);
3350
3351 /*
3352 * Free the kernel virtual mapping.
3353 */
3354 uvm_km_free(kernel_map, va, endva - va);
3355 } else
3356 panic("bus_space_unmap: bad bus space tag");
3357
3358 ok:
3359 if (extent_free(ex, bpa, size,
3360 EX_NOWAIT | (ioport_malloc_safe ? EX_MALLOCOK : 0))) {
3361 printf("bus_space_unmap: %s 0x%lx, size 0x%lx\n",
3362 (t == I386_BUS_SPACE_IO) ? "port" : "pa", bpa, size);
3363 printf("bus_space_unmap: can't free region\n");
3364 }
3365 }
3366
3367 void
_bus_space_unmap(bus_space_tag_t t,bus_space_handle_t bsh,bus_size_t size,bus_addr_t * adrp)3368 _bus_space_unmap(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t size,
3369 bus_addr_t *adrp)
3370 {
3371 u_long va, endva;
3372 bus_addr_t bpa;
3373
3374 /*
3375 * Find the correct bus physical address.
3376 */
3377 if (t == I386_BUS_SPACE_IO) {
3378 bpa = bsh;
3379 } else if (t == I386_BUS_SPACE_MEM) {
3380 bpa = (bus_addr_t)ISA_PHYSADDR(bsh);
3381 if (IOM_BEGIN <= bpa && bpa <= IOM_END)
3382 goto ok;
3383
3384 va = i386_trunc_page(bsh);
3385 endva = i386_round_page(bsh + size);
3386
3387 #ifdef DIAGNOSTIC
3388 if (endva <= va)
3389 panic("_bus_space_unmap: overflow");
3390 #endif
3391
3392 (void) pmap_extract(pmap_kernel(), va, &bpa);
3393 bpa += (bsh & PGOFSET);
3394
3395 /*
3396 * Free the kernel virtual mapping.
3397 */
3398 uvm_km_free(kernel_map, va, endva - va);
3399 } else
3400 panic("bus_space_unmap: bad bus space tag");
3401
3402 ok:
3403 if (adrp != NULL) {
3404 *adrp = bpa;
3405 }
3406 }
3407
3408 void
bus_space_free(t,bsh,size)3409 bus_space_free(t, bsh, size)
3410 bus_space_tag_t t;
3411 bus_space_handle_t bsh;
3412 bus_size_t size;
3413 {
3414
3415 /* bus_space_unmap() does all that we need to do. */
3416 bus_space_unmap(t, bsh, size);
3417 }
3418
3419 int
bus_space_subregion(t,bsh,offset,size,nbshp)3420 bus_space_subregion(t, bsh, offset, size, nbshp)
3421 bus_space_tag_t t;
3422 bus_space_handle_t bsh;
3423 bus_size_t offset, size;
3424 bus_space_handle_t *nbshp;
3425 {
3426 *nbshp = bsh + offset;
3427 return (0);
3428 }
3429
3430 /*
3431 * Common function for DMA map creation. May be called by bus-specific
3432 * DMA map creation functions.
3433 */
3434 int
_bus_dmamap_create(t,size,nsegments,maxsegsz,boundary,flags,dmamp)3435 _bus_dmamap_create(t, size, nsegments, maxsegsz, boundary, flags, dmamp)
3436 bus_dma_tag_t t;
3437 bus_size_t size;
3438 int nsegments;
3439 bus_size_t maxsegsz;
3440 bus_size_t boundary;
3441 int flags;
3442 bus_dmamap_t *dmamp;
3443 {
3444 struct i386_bus_dmamap *map;
3445 void *mapstore;
3446 size_t mapsize;
3447
3448 /*
3449 * Allocate and initialize the DMA map. The end of the map
3450 * is a variable-sized array of segments, so we allocate enough
3451 * room for them in one shot.
3452 *
3453 * Note we don't preserve the WAITOK or NOWAIT flags. Preservation
3454 * of ALLOCNOW notifies others that we've reserved these resources,
3455 * and they are not to be freed.
3456 *
3457 * The bus_dmamap_t includes one bus_dma_segment_t, hence
3458 * the (nsegments - 1).
3459 */
3460 mapsize = sizeof(struct i386_bus_dmamap) +
3461 (sizeof(bus_dma_segment_t) * (nsegments - 1));
3462 if ((mapstore = malloc(mapsize, M_DEVBUF,
3463 (flags & BUS_DMA_NOWAIT) ? M_NOWAIT : M_WAITOK)) == NULL)
3464 return (ENOMEM);
3465
3466 bzero(mapstore, mapsize);
3467 map = (struct i386_bus_dmamap *)mapstore;
3468 map->_dm_size = size;
3469 map->_dm_segcnt = nsegments;
3470 map->_dm_maxsegsz = maxsegsz;
3471 map->_dm_boundary = boundary;
3472 map->_dm_flags = flags & ~(BUS_DMA_WAITOK|BUS_DMA_NOWAIT);
3473 map->dm_mapsize = 0; /* no valid mappings */
3474 map->dm_nsegs = 0;
3475
3476 *dmamp = map;
3477 return (0);
3478 }
3479
3480 /*
3481 * Common function for DMA map destruction. May be called by bus-specific
3482 * DMA map destruction functions.
3483 */
3484 void
_bus_dmamap_destroy(t,map)3485 _bus_dmamap_destroy(t, map)
3486 bus_dma_tag_t t;
3487 bus_dmamap_t map;
3488 {
3489
3490 free(map, M_DEVBUF);
3491 }
3492
3493 /*
3494 * Common function for loading a DMA map with a linear buffer. May
3495 * be called by bus-specific DMA map load functions.
3496 */
3497 int
_bus_dmamap_load(t,map,buf,buflen,p,flags)3498 _bus_dmamap_load(t, map, buf, buflen, p, flags)
3499 bus_dma_tag_t t;
3500 bus_dmamap_t map;
3501 void *buf;
3502 bus_size_t buflen;
3503 struct proc *p;
3504 int flags;
3505 {
3506 bus_addr_t lastaddr;
3507 int seg, error;
3508
3509 /*
3510 * Make sure that on error condition we return "no valid mappings".
3511 */
3512 map->dm_mapsize = 0;
3513 map->dm_nsegs = 0;
3514
3515 if (buflen > map->_dm_size)
3516 return (EINVAL);
3517
3518 seg = 0;
3519 error = _bus_dmamap_load_buffer(t, map, buf, buflen, p, flags,
3520 &lastaddr, &seg, 1);
3521 if (error == 0) {
3522 map->dm_mapsize = buflen;
3523 map->dm_nsegs = seg + 1;
3524 }
3525 return (error);
3526 }
3527
3528 /*
3529 * Like _bus_dmamap_load(), but for mbufs.
3530 */
3531 int
_bus_dmamap_load_mbuf(t,map,m0,flags)3532 _bus_dmamap_load_mbuf(t, map, m0, flags)
3533 bus_dma_tag_t t;
3534 bus_dmamap_t map;
3535 struct mbuf *m0;
3536 int flags;
3537 {
3538 paddr_t lastaddr;
3539 int seg, error, first;
3540 struct mbuf *m;
3541
3542 /*
3543 * Make sure that on error condition we return "no valid mappings".
3544 */
3545 map->dm_mapsize = 0;
3546 map->dm_nsegs = 0;
3547
3548 #ifdef DIAGNOSTIC
3549 if ((m0->m_flags & M_PKTHDR) == 0)
3550 panic("_bus_dmamap_load_mbuf: no packet header");
3551 #endif
3552
3553 if (m0->m_pkthdr.len > map->_dm_size)
3554 return (EINVAL);
3555
3556 first = 1;
3557 seg = 0;
3558 error = 0;
3559 for (m = m0; m != NULL && error == 0; m = m->m_next) {
3560 if (m->m_len == 0)
3561 continue;
3562 error = _bus_dmamap_load_buffer(t, map, m->m_data, m->m_len,
3563 NULL, flags, &lastaddr, &seg, first);
3564 first = 0;
3565 }
3566 if (error == 0) {
3567 map->dm_mapsize = m0->m_pkthdr.len;
3568 map->dm_nsegs = seg + 1;
3569 }
3570 return (error);
3571 }
3572
3573 /*
3574 * Like _bus_dmamap_load(), but for uios.
3575 */
3576 int
_bus_dmamap_load_uio(t,map,uio,flags)3577 _bus_dmamap_load_uio(t, map, uio, flags)
3578 bus_dma_tag_t t;
3579 bus_dmamap_t map;
3580 struct uio *uio;
3581 int flags;
3582 {
3583 paddr_t lastaddr;
3584 int seg, i, error, first;
3585 bus_size_t minlen, resid;
3586 struct proc *p = NULL;
3587 struct iovec *iov;
3588 caddr_t addr;
3589
3590 /*
3591 * Make sure that on error condition we return "no valid mappings".
3592 */
3593 map->dm_mapsize = 0;
3594 map->dm_nsegs = 0;
3595
3596 resid = uio->uio_resid;
3597 iov = uio->uio_iov;
3598
3599 if (resid > map->_dm_size)
3600 return (EINVAL);
3601
3602 if (uio->uio_segflg == UIO_USERSPACE) {
3603 p = uio->uio_procp;
3604 #ifdef DIAGNOSTIC
3605 if (p == NULL)
3606 panic("_bus_dmamap_load_uio: USERSPACE but no proc");
3607 #endif
3608 }
3609
3610 first = 1;
3611 seg = 0;
3612 error = 0;
3613 for (i = 0; i < uio->uio_iovcnt && resid != 0 && error == 0; i++) {
3614 /*
3615 * Now at the first iovec to load. Load each iovec
3616 * until we have exhausted the residual count.
3617 */
3618 minlen = resid < iov[i].iov_len ? resid : iov[i].iov_len;
3619 addr = (caddr_t)iov[i].iov_base;
3620
3621 error = _bus_dmamap_load_buffer(t, map, addr, minlen,
3622 p, flags, &lastaddr, &seg, first);
3623 first = 0;
3624
3625 resid -= minlen;
3626 }
3627 if (error == 0) {
3628 map->dm_mapsize = uio->uio_resid;
3629 map->dm_nsegs = seg + 1;
3630 }
3631 return (error);
3632 }
3633
3634 /*
3635 * Like _bus_dmamap_load(), but for raw memory allocated with
3636 * bus_dmamem_alloc().
3637 */
3638 int
_bus_dmamap_load_raw(t,map,segs,nsegs,size,flags)3639 _bus_dmamap_load_raw(t, map, segs, nsegs, size, flags)
3640 bus_dma_tag_t t;
3641 bus_dmamap_t map;
3642 bus_dma_segment_t *segs;
3643 int nsegs;
3644 bus_size_t size;
3645 int flags;
3646 {
3647 if (nsegs > map->_dm_segcnt || size > map->_dm_size)
3648 return (EINVAL);
3649
3650 /*
3651 * Make sure we don't cross any boundaries.
3652 */
3653 if (map->_dm_boundary) {
3654 bus_addr_t bmask = ~(map->_dm_boundary - 1);
3655 int i;
3656
3657 for (i = 0; i < nsegs; i++) {
3658 if (segs[i].ds_len > map->_dm_maxsegsz)
3659 return (EINVAL);
3660 if ((segs[i].ds_addr & bmask) !=
3661 ((segs[i].ds_addr + segs[i].ds_len - 1) & bmask))
3662 return (EINVAL);
3663 }
3664 }
3665
3666 bcopy(segs, map->dm_segs, nsegs * sizeof(*segs));
3667 map->dm_nsegs = nsegs;
3668 return (0);
3669 }
3670
3671 /*
3672 * Common function for unloading a DMA map. May be called by
3673 * bus-specific DMA map unload functions.
3674 */
3675 void
_bus_dmamap_unload(t,map)3676 _bus_dmamap_unload(t, map)
3677 bus_dma_tag_t t;
3678 bus_dmamap_t map;
3679 {
3680
3681 /*
3682 * No resources to free; just mark the mappings as
3683 * invalid.
3684 */
3685 map->dm_mapsize = 0;
3686 map->dm_nsegs = 0;
3687 }
3688
3689 /*
3690 * Common function for DMA map synchronization. May be called
3691 * by bus-specific DMA map synchronization functions.
3692 */
3693 void
_bus_dmamap_sync(t,map,addr,size,op)3694 _bus_dmamap_sync(t, map, addr, size, op)
3695 bus_dma_tag_t t;
3696 bus_dmamap_t map;
3697 bus_addr_t addr;
3698 bus_size_t size;
3699 int op;
3700 {
3701
3702 /* Nothing to do here. */
3703 }
3704
3705 /*
3706 * Common function for DMA-safe memory allocation. May be called
3707 * by bus-specific DMA memory allocation functions.
3708 */
3709 int
_bus_dmamem_alloc(t,size,alignment,boundary,segs,nsegs,rsegs,flags)3710 _bus_dmamem_alloc(t, size, alignment, boundary, segs, nsegs, rsegs, flags)
3711 bus_dma_tag_t t;
3712 bus_size_t size, alignment, boundary;
3713 bus_dma_segment_t *segs;
3714 int nsegs;
3715 int *rsegs;
3716 int flags;
3717 {
3718
3719 return (_bus_dmamem_alloc_range(t, size, alignment, boundary,
3720 segs, nsegs, rsegs, flags, 0, trunc_page(avail_end)));
3721 }
3722
3723 /*
3724 * Common function for freeing DMA-safe memory. May be called by
3725 * bus-specific DMA memory free functions.
3726 */
3727 void
_bus_dmamem_free(t,segs,nsegs)3728 _bus_dmamem_free(t, segs, nsegs)
3729 bus_dma_tag_t t;
3730 bus_dma_segment_t *segs;
3731 int nsegs;
3732 {
3733 struct vm_page *m;
3734 bus_addr_t addr;
3735 struct pglist mlist;
3736 int curseg;
3737
3738 /*
3739 * Build a list of pages to free back to the VM system.
3740 */
3741 TAILQ_INIT(&mlist);
3742 for (curseg = 0; curseg < nsegs; curseg++) {
3743 for (addr = segs[curseg].ds_addr;
3744 addr < (segs[curseg].ds_addr + segs[curseg].ds_len);
3745 addr += PAGE_SIZE) {
3746 m = PHYS_TO_VM_PAGE(addr);
3747 TAILQ_INSERT_TAIL(&mlist, m, pageq);
3748 }
3749 }
3750
3751 uvm_pglistfree(&mlist);
3752 }
3753
3754 /*
3755 * Common function for mapping DMA-safe memory. May be called by
3756 * bus-specific DMA memory map functions.
3757 */
3758 int
_bus_dmamem_map(t,segs,nsegs,size,kvap,flags)3759 _bus_dmamem_map(t, segs, nsegs, size, kvap, flags)
3760 bus_dma_tag_t t;
3761 bus_dma_segment_t *segs;
3762 int nsegs;
3763 size_t size;
3764 caddr_t *kvap;
3765 int flags;
3766 {
3767 vaddr_t va;
3768 bus_addr_t addr;
3769 int curseg;
3770
3771 size = round_page(size);
3772 va = uvm_km_valloc(kernel_map, size);
3773 if (va == 0)
3774 return (ENOMEM);
3775
3776 *kvap = (caddr_t)va;
3777
3778 for (curseg = 0; curseg < nsegs; curseg++) {
3779 for (addr = segs[curseg].ds_addr;
3780 addr < (segs[curseg].ds_addr + segs[curseg].ds_len);
3781 addr += PAGE_SIZE, va += PAGE_SIZE, size -= PAGE_SIZE) {
3782 if (size == 0)
3783 panic("_bus_dmamem_map: size botch");
3784 pmap_enter(pmap_kernel(), va, addr,
3785 VM_PROT_READ | VM_PROT_WRITE,
3786 VM_PROT_READ | VM_PROT_WRITE | PMAP_WIRED);
3787 }
3788 }
3789 pmap_update(pmap_kernel());
3790
3791 return (0);
3792 }
3793
3794 /*
3795 * Common function for unmapping DMA-safe memory. May be called by
3796 * bus-specific DMA memory unmapping functions.
3797 */
3798 void
_bus_dmamem_unmap(t,kva,size)3799 _bus_dmamem_unmap(t, kva, size)
3800 bus_dma_tag_t t;
3801 caddr_t kva;
3802 size_t size;
3803 {
3804
3805 #ifdef DIAGNOSTIC
3806 if ((u_long)kva & PGOFSET)
3807 panic("_bus_dmamem_unmap");
3808 #endif
3809
3810 size = round_page(size);
3811 uvm_km_free(kernel_map, (vaddr_t)kva, size);
3812 }
3813
3814 /*
3815 * Common functin for mmap(2)'ing DMA-safe memory. May be called by
3816 * bus-specific DMA mmap(2)'ing functions.
3817 */
3818 paddr_t
_bus_dmamem_mmap(t,segs,nsegs,off,prot,flags)3819 _bus_dmamem_mmap(t, segs, nsegs, off, prot, flags)
3820 bus_dma_tag_t t;
3821 bus_dma_segment_t *segs;
3822 int nsegs;
3823 off_t off;
3824 int prot, flags;
3825 {
3826 int i;
3827
3828 for (i = 0; i < nsegs; i++) {
3829 #ifdef DIAGNOSTIC
3830 if (off & PGOFSET)
3831 panic("_bus_dmamem_mmap: offset unaligned");
3832 if (segs[i].ds_addr & PGOFSET)
3833 panic("_bus_dmamem_mmap: segment unaligned");
3834 if (segs[i].ds_len & PGOFSET)
3835 panic("_bus_dmamem_mmap: segment size not multiple"
3836 " of page size");
3837 #endif
3838 if (off >= segs[i].ds_len) {
3839 off -= segs[i].ds_len;
3840 continue;
3841 }
3842
3843 return (i386_btop((caddr_t)segs[i].ds_addr + off));
3844 }
3845
3846 /* Page not found. */
3847 return (-1);
3848 }
3849
3850 /**********************************************************************
3851 * DMA utility functions
3852 **********************************************************************/
3853 /*
3854 * Utility function to load a linear buffer. lastaddrp holds state
3855 * between invocations (for multiple-buffer loads). segp contains
3856 * the starting segment on entrace, and the ending segment on exit.
3857 * first indicates if this is the first invocation of this function.
3858 */
3859 int
_bus_dmamap_load_buffer(t,map,buf,buflen,p,flags,lastaddrp,segp,first)3860 _bus_dmamap_load_buffer(t, map, buf, buflen, p, flags, lastaddrp, segp, first)
3861 bus_dma_tag_t t;
3862 bus_dmamap_t map;
3863 void *buf;
3864 bus_size_t buflen;
3865 struct proc *p;
3866 int flags;
3867 paddr_t *lastaddrp;
3868 int *segp;
3869 int first;
3870 {
3871 bus_size_t sgsize;
3872 bus_addr_t curaddr, lastaddr, baddr, bmask;
3873 vaddr_t vaddr = (vaddr_t)buf;
3874 int seg;
3875 pmap_t pmap;
3876
3877 if (p != NULL)
3878 pmap = p->p_vmspace->vm_map.pmap;
3879 else
3880 pmap = pmap_kernel();
3881
3882 lastaddr = *lastaddrp;
3883 bmask = ~(map->_dm_boundary - 1);
3884
3885 for (seg = *segp; buflen > 0 ; ) {
3886 /*
3887 * Get the physical address for this segment.
3888 */
3889 pmap_extract(pmap, vaddr, (paddr_t *)&curaddr);
3890
3891 /*
3892 * Compute the segment size, and adjust counts.
3893 */
3894 sgsize = PAGE_SIZE - ((u_long)vaddr & PGOFSET);
3895 if (buflen < sgsize)
3896 sgsize = buflen;
3897
3898 /*
3899 * Make sure we don't cross any boundaries.
3900 */
3901 if (map->_dm_boundary > 0) {
3902 baddr = (curaddr + map->_dm_boundary) & bmask;
3903 if (sgsize > (baddr - curaddr))
3904 sgsize = (baddr - curaddr);
3905 }
3906
3907 /*
3908 * Insert chunk into a segment, coalescing with
3909 * previous segment if possible.
3910 */
3911 if (first) {
3912 map->dm_segs[seg].ds_addr = curaddr;
3913 map->dm_segs[seg].ds_len = sgsize;
3914 first = 0;
3915 } else {
3916 if (curaddr == lastaddr &&
3917 (map->dm_segs[seg].ds_len + sgsize) <=
3918 map->_dm_maxsegsz &&
3919 (map->_dm_boundary == 0 ||
3920 (map->dm_segs[seg].ds_addr & bmask) ==
3921 (curaddr & bmask)))
3922 map->dm_segs[seg].ds_len += sgsize;
3923 else {
3924 if (++seg >= map->_dm_segcnt)
3925 break;
3926 map->dm_segs[seg].ds_addr = curaddr;
3927 map->dm_segs[seg].ds_len = sgsize;
3928 }
3929 }
3930
3931 lastaddr = curaddr + sgsize;
3932 vaddr += sgsize;
3933 buflen -= sgsize;
3934 }
3935
3936 *segp = seg;
3937 *lastaddrp = lastaddr;
3938
3939 /*
3940 * Did we fit?
3941 */
3942 if (buflen != 0)
3943 return (EFBIG); /* XXX better return value here? */
3944 return (0);
3945 }
3946
3947 /*
3948 * Allocate physical memory from the given physical address range.
3949 * Called by DMA-safe memory allocation methods.
3950 */
3951 int
_bus_dmamem_alloc_range(t,size,alignment,boundary,segs,nsegs,rsegs,flags,low,high)3952 _bus_dmamem_alloc_range(t, size, alignment, boundary, segs, nsegs, rsegs,
3953 flags, low, high)
3954 bus_dma_tag_t t;
3955 bus_size_t size, alignment, boundary;
3956 bus_dma_segment_t *segs;
3957 int nsegs;
3958 int *rsegs;
3959 int flags;
3960 paddr_t low;
3961 paddr_t high;
3962 {
3963 paddr_t curaddr, lastaddr;
3964 struct vm_page *m;
3965 struct pglist mlist;
3966 int curseg, error;
3967
3968 /* Always round the size. */
3969 size = round_page(size);
3970
3971 /*
3972 * Allocate pages from the VM system.
3973 */
3974 TAILQ_INIT(&mlist);
3975 error = uvm_pglistalloc(size, low, high,
3976 alignment, boundary, &mlist, nsegs, (flags & BUS_DMA_NOWAIT) == 0);
3977 if (error)
3978 return (error);
3979
3980 /*
3981 * Compute the location, size, and number of segments actually
3982 * returned by the VM code.
3983 */
3984 m = TAILQ_FIRST(&mlist);
3985 curseg = 0;
3986 lastaddr = segs[curseg].ds_addr = VM_PAGE_TO_PHYS(m);
3987 segs[curseg].ds_len = PAGE_SIZE;
3988
3989 for (m = TAILQ_NEXT(m, pageq); m != NULL; m = TAILQ_NEXT(m, pageq)) {
3990 curaddr = VM_PAGE_TO_PHYS(m);
3991 #ifdef DIAGNOSTIC
3992 if (curseg == nsegs) {
3993 printf("uvm_pglistalloc returned too many\n");
3994 panic("_bus_dmamem_alloc_range");
3995 }
3996 if (curaddr < low || curaddr >= high) {
3997 printf("uvm_pglistalloc returned non-sensical"
3998 " address 0x%lx\n", curaddr);
3999 panic("_bus_dmamem_alloc_range");
4000 }
4001 #endif
4002 if (curaddr == (lastaddr + PAGE_SIZE))
4003 segs[curseg].ds_len += PAGE_SIZE;
4004 else {
4005 curseg++;
4006 segs[curseg].ds_addr = curaddr;
4007 segs[curseg].ds_len = PAGE_SIZE;
4008 }
4009 lastaddr = curaddr;
4010 }
4011
4012 *rsegs = curseg + 1;
4013
4014 return (0);
4015 }
4016
4017 #ifdef _KERN_DO_ECOFF
4018 int
cpu_exec_ecoff_hook(struct proc * p,struct exec_package * epp)4019 cpu_exec_ecoff_hook(struct proc *p, struct exec_package *epp)
4020 {
4021 return (0);
4022 }
4023 #endif
4024
4025 #ifdef DIAGNOSTIC
4026 void
splassert_check(int wantipl,const char * func)4027 splassert_check(int wantipl, const char *func)
4028 {
4029 if (cpl < wantipl) {
4030 splassert_fail(wantipl, cpl, func);
4031 }
4032 }
4033 #endif
4034
4035 /* If SMALL_KERNEL this results in an out of line definition of splx. */
4036 SPLX_OUTLINED_BODY
4037