1 /*-
2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4 * Copyright (c) 1997 KATO Takenori.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to Berkeley by
8 * William Jolitz.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the University of
21 * California, Berkeley and its contributors.
22 * 4. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * SUCH DAMAGE.
37 *
38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
39 */
40
41 #include <sys/cdefs.h>
42 #include "opt_cpu.h"
43
44 #include <sys/param.h>
45 #include <sys/bus.h>
46 #include <sys/cpu.h>
47 #include <sys/eventhandler.h>
48 #include <sys/limits.h>
49 #include <sys/systm.h>
50 #include <sys/kernel.h>
51 #include <sys/sysctl.h>
52 #include <sys/power.h>
53
54 #include <vm/vm.h>
55 #include <vm/pmap.h>
56
57 #include <machine/asmacros.h>
58 #include <machine/clock.h>
59 #include <machine/cputypes.h>
60 #include <machine/frame.h>
61 #include <machine/intr_machdep.h>
62 #include <machine/md_var.h>
63 #include <machine/segments.h>
64 #include <machine/specialreg.h>
65
66 #include <amd64/vmm/intel/vmx_controls.h>
67 #include <x86/isa/icu.h>
68 #include <x86/vmware.h>
69
70 #ifdef __i386__
71 #define IDENTBLUE_CYRIX486 0
72 #define IDENTBLUE_IBMCPU 1
73 #define IDENTBLUE_CYRIXM2 2
74
75 static void identifycyrix(void);
76 static void print_transmeta_info(void);
77 #endif
78 static u_int find_cpu_vendor_id(void);
79 static void print_AMD_info(void);
80 static void print_INTEL_info(void);
81 static void print_INTEL_TLB(u_int data);
82 static void print_hypervisor_info(void);
83 static void print_svm_info(void);
84 static void print_via_padlock_info(void);
85 static void print_vmx_info(void);
86
87 #ifdef __i386__
88 int cpu; /* Are we 386, 386sx, 486, etc? */
89 int cpu_class;
90 #endif
91 u_int cpu_feature; /* Feature flags */
92 u_int cpu_feature2; /* Feature flags */
93 u_int amd_feature; /* AMD feature flags */
94 u_int amd_feature2; /* AMD feature flags */
95 u_int amd_rascap; /* AMD RAS capabilities */
96 u_int amd_pminfo; /* AMD advanced power management info */
97 u_int amd_extended_feature_extensions;
98 u_int via_feature_rng; /* VIA RNG features */
99 u_int via_feature_xcrypt; /* VIA ACE features */
100 u_int cpu_high; /* Highest arg to CPUID */
101 u_int cpu_exthigh; /* Highest arg to extended CPUID */
102 u_int cpu_id; /* Stepping ID */
103 u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */
104 u_int cpu_procinfo2; /* Multicore info */
105 u_int cpu_procinfo3;
106 char cpu_vendor[20]; /* CPU Origin code */
107 u_int cpu_vendor_id; /* CPU vendor ID */
108 u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */
109 u_int cpu_clflush_line_size = 32;
110 u_int cpu_stdext_feature; /* %ebx */
111 u_int cpu_stdext_feature2; /* %ecx */
112 u_int cpu_stdext_feature3; /* %edx */
113 uint64_t cpu_ia32_arch_caps;
114 u_int cpu_max_ext_state_size;
115 u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */
116 u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */
117 u_int cpu_mon_max_size; /* MONITOR minimum range size, bytes */
118 u_int cpu_maxphyaddr; /* Max phys addr width in bits */
119 u_int cpu_power_eax; /* 06H: Power management leaf, %eax */
120 u_int cpu_power_ebx; /* 06H: Power management leaf, %ebx */
121 u_int cpu_power_ecx; /* 06H: Power management leaf, %ecx */
122 u_int cpu_power_edx; /* 06H: Power management leaf, %edx */
123 const char machine[] = MACHINE;
124
125 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
126 &via_feature_rng, 0,
127 "VIA RNG feature available in CPU");
128 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
129 &via_feature_xcrypt, 0,
130 "VIA xcrypt feature available in CPU");
131
132 #ifdef __amd64__
133 #ifdef SCTL_MASK32
134 extern int adaptive_machine_arch;
135 #endif
136
137 static int
sysctl_hw_machine(SYSCTL_HANDLER_ARGS)138 sysctl_hw_machine(SYSCTL_HANDLER_ARGS)
139 {
140 #ifdef SCTL_MASK32
141 static const char machine32[] = "i386";
142 #endif
143 int error;
144
145 #ifdef SCTL_MASK32
146 if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch)
147 error = SYSCTL_OUT(req, machine32, sizeof(machine32));
148 else
149 #endif
150 error = SYSCTL_OUT(req, machine, sizeof(machine));
151 return (error);
152
153 }
154 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD |
155 CTLFLAG_CAPRD | CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A", "Machine class");
156 #else
157 SYSCTL_CONST_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD | CTLFLAG_CAPRD,
158 machine, "Machine class");
159 #endif
160
161 char cpu_model[128];
162 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD | CTLFLAG_CAPRD,
163 cpu_model, 0, "Machine model");
164
165 static int hw_clockrate;
166 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
167 &hw_clockrate, 0, "CPU instruction clock rate");
168
169 u_int hv_base;
170 u_int hv_high;
171 char hv_vendor[16];
172 SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD, hv_vendor,
173 0, "Hypervisor vendor");
174
175 static eventhandler_tag tsc_post_tag;
176
177 static char cpu_brand[48];
178
179 #ifdef __i386__
180 #define MAX_BRAND_INDEX 8
181
182 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
183 NULL, /* No brand */
184 "Intel Celeron",
185 "Intel Pentium III",
186 "Intel Pentium III Xeon",
187 NULL,
188 NULL,
189 NULL,
190 NULL,
191 "Intel Pentium 4"
192 };
193
194 static struct {
195 char *cpu_name;
196 int cpu_class;
197 } cpus[] = {
198 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */
199 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */
200 { "i386DX", CPUCLASS_386 }, /* CPU_386 */
201 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */
202 { "i486DX", CPUCLASS_486 }, /* CPU_486 */
203 { "Pentium", CPUCLASS_586 }, /* CPU_586 */
204 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */
205 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */
206 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */
207 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */
208 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */
209 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */
210 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */
211 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */
212 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */
213 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */
214 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */
215 };
216 #endif
217
218 static struct {
219 char *vendor;
220 u_int vendor_id;
221 } cpu_vendors[] = {
222 { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */
223 { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */
224 { HYGON_VENDOR_ID, CPU_VENDOR_HYGON }, /* HygonGenuine */
225 { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */
226 #ifdef __i386__
227 { NSC_VENDOR_ID, CPU_VENDOR_NSC }, /* Geode by NSC */
228 { CYRIX_VENDOR_ID, CPU_VENDOR_CYRIX }, /* CyrixInstead */
229 { TRANSMETA_VENDOR_ID, CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
230 { SIS_VENDOR_ID, CPU_VENDOR_SIS }, /* SiS SiS SiS */
231 { UMC_VENDOR_ID, CPU_VENDOR_UMC }, /* UMC UMC UMC */
232 { NEXGEN_VENDOR_ID, CPU_VENDOR_NEXGEN }, /* NexGenDriven */
233 { RISE_VENDOR_ID, CPU_VENDOR_RISE }, /* RiseRiseRise */
234 #if 0
235 /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
236 { "TransmetaCPU", CPU_VENDOR_TRANSMETA },
237 #endif
238 #endif
239 };
240
241 void
printcpuinfo(void)242 printcpuinfo(void)
243 {
244 u_int regs[4], i;
245 char *brand;
246
247 printf("CPU: ");
248 #ifdef __i386__
249 cpu_class = cpus[cpu].cpu_class;
250 strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model));
251 #else
252 strncpy(cpu_model, "Hammer", sizeof (cpu_model));
253 #endif
254
255 /* Check for extended CPUID information and a processor name. */
256 if (cpu_exthigh >= 0x80000004) {
257 brand = cpu_brand;
258 for (i = 0x80000002; i < 0x80000005; i++) {
259 do_cpuid(i, regs);
260 memcpy(brand, regs, sizeof(regs));
261 brand += sizeof(regs);
262 }
263 }
264
265 switch (cpu_vendor_id) {
266 case CPU_VENDOR_INTEL:
267 #ifdef __i386__
268 if ((cpu_id & 0xf00) > 0x300) {
269 u_int brand_index;
270
271 cpu_model[0] = '\0';
272
273 switch (cpu_id & 0x3000) {
274 case 0x1000:
275 strcpy(cpu_model, "Overdrive ");
276 break;
277 case 0x2000:
278 strcpy(cpu_model, "Dual ");
279 break;
280 }
281
282 switch (cpu_id & 0xf00) {
283 case 0x400:
284 strcat(cpu_model, "i486 ");
285 /* Check the particular flavor of 486 */
286 switch (cpu_id & 0xf0) {
287 case 0x00:
288 case 0x10:
289 strcat(cpu_model, "DX");
290 break;
291 case 0x20:
292 strcat(cpu_model, "SX");
293 break;
294 case 0x30:
295 strcat(cpu_model, "DX2");
296 break;
297 case 0x40:
298 strcat(cpu_model, "SL");
299 break;
300 case 0x50:
301 strcat(cpu_model, "SX2");
302 break;
303 case 0x70:
304 strcat(cpu_model,
305 "DX2 Write-Back Enhanced");
306 break;
307 case 0x80:
308 strcat(cpu_model, "DX4");
309 break;
310 }
311 break;
312 case 0x500:
313 /* Check the particular flavor of 586 */
314 strcat(cpu_model, "Pentium");
315 switch (cpu_id & 0xf0) {
316 case 0x00:
317 strcat(cpu_model, " A-step");
318 break;
319 case 0x10:
320 strcat(cpu_model, "/P5");
321 break;
322 case 0x20:
323 strcat(cpu_model, "/P54C");
324 break;
325 case 0x30:
326 strcat(cpu_model, "/P24T");
327 break;
328 case 0x40:
329 strcat(cpu_model, "/P55C");
330 break;
331 case 0x70:
332 strcat(cpu_model, "/P54C");
333 break;
334 case 0x80:
335 strcat(cpu_model, "/P55C (quarter-micron)");
336 break;
337 default:
338 /* nothing */
339 break;
340 }
341 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
342 /*
343 * XXX - If/when Intel fixes the bug, this
344 * should also check the version of the
345 * CPU, not just that it's a Pentium.
346 */
347 has_f00f_bug = 1;
348 #endif
349 break;
350 case 0x600:
351 /* Check the particular flavor of 686 */
352 switch (cpu_id & 0xf0) {
353 case 0x00:
354 strcat(cpu_model, "Pentium Pro A-step");
355 break;
356 case 0x10:
357 strcat(cpu_model, "Pentium Pro");
358 break;
359 case 0x30:
360 case 0x50:
361 case 0x60:
362 strcat(cpu_model,
363 "Pentium II/Pentium II Xeon/Celeron");
364 cpu = CPU_PII;
365 break;
366 case 0x70:
367 case 0x80:
368 case 0xa0:
369 case 0xb0:
370 strcat(cpu_model,
371 "Pentium III/Pentium III Xeon/Celeron");
372 cpu = CPU_PIII;
373 break;
374 default:
375 strcat(cpu_model, "Unknown 80686");
376 break;
377 }
378 break;
379 case 0xf00:
380 strcat(cpu_model, "Pentium 4");
381 cpu = CPU_P4;
382 break;
383 default:
384 strcat(cpu_model, "unknown");
385 break;
386 }
387
388 /*
389 * If we didn't get a brand name from the extended
390 * CPUID, try to look it up in the brand table.
391 */
392 if (cpu_high > 0 && *cpu_brand == '\0') {
393 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
394 if (brand_index <= MAX_BRAND_INDEX &&
395 cpu_brandtable[brand_index] != NULL)
396 strcpy(cpu_brand,
397 cpu_brandtable[brand_index]);
398 }
399 }
400 #else
401 /* Please make up your mind folks! */
402 strcat(cpu_model, "EM64T");
403 #endif
404 break;
405 case CPU_VENDOR_AMD:
406 /*
407 * Values taken from AMD Processor Recognition
408 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
409 * (also describes ``Features'' encodings.
410 */
411 strcpy(cpu_model, "AMD ");
412 #ifdef __i386__
413 switch (cpu_id & 0xFF0) {
414 case 0x410:
415 strcat(cpu_model, "Standard Am486DX");
416 break;
417 case 0x430:
418 strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
419 break;
420 case 0x470:
421 strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
422 break;
423 case 0x480:
424 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
425 break;
426 case 0x490:
427 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
428 break;
429 case 0x4E0:
430 strcat(cpu_model, "Am5x86 Write-Through");
431 break;
432 case 0x4F0:
433 strcat(cpu_model, "Am5x86 Write-Back");
434 break;
435 case 0x500:
436 strcat(cpu_model, "K5 model 0");
437 break;
438 case 0x510:
439 strcat(cpu_model, "K5 model 1");
440 break;
441 case 0x520:
442 strcat(cpu_model, "K5 PR166 (model 2)");
443 break;
444 case 0x530:
445 strcat(cpu_model, "K5 PR200 (model 3)");
446 break;
447 case 0x560:
448 strcat(cpu_model, "K6");
449 break;
450 case 0x570:
451 strcat(cpu_model, "K6 266 (model 1)");
452 break;
453 case 0x580:
454 strcat(cpu_model, "K6-2");
455 break;
456 case 0x590:
457 strcat(cpu_model, "K6-III");
458 break;
459 case 0x5a0:
460 strcat(cpu_model, "Geode LX");
461 break;
462 default:
463 strcat(cpu_model, "Unknown");
464 break;
465 }
466 #else
467 if ((cpu_id & 0xf00) == 0xf00)
468 strcat(cpu_model, "AMD64 Processor");
469 else
470 strcat(cpu_model, "Unknown");
471 #endif
472 break;
473 #ifdef __i386__
474 case CPU_VENDOR_CYRIX:
475 strcpy(cpu_model, "Cyrix ");
476 switch (cpu_id & 0xff0) {
477 case 0x440:
478 strcat(cpu_model, "MediaGX");
479 break;
480 case 0x520:
481 strcat(cpu_model, "6x86");
482 break;
483 case 0x540:
484 cpu_class = CPUCLASS_586;
485 strcat(cpu_model, "GXm");
486 break;
487 case 0x600:
488 strcat(cpu_model, "6x86MX");
489 break;
490 default:
491 /*
492 * Even though CPU supports the cpuid
493 * instruction, it can be disabled.
494 * Therefore, this routine supports all Cyrix
495 * CPUs.
496 */
497 switch (cyrix_did & 0xf0) {
498 case 0x00:
499 switch (cyrix_did & 0x0f) {
500 case 0x00:
501 strcat(cpu_model, "486SLC");
502 break;
503 case 0x01:
504 strcat(cpu_model, "486DLC");
505 break;
506 case 0x02:
507 strcat(cpu_model, "486SLC2");
508 break;
509 case 0x03:
510 strcat(cpu_model, "486DLC2");
511 break;
512 case 0x04:
513 strcat(cpu_model, "486SRx");
514 break;
515 case 0x05:
516 strcat(cpu_model, "486DRx");
517 break;
518 case 0x06:
519 strcat(cpu_model, "486SRx2");
520 break;
521 case 0x07:
522 strcat(cpu_model, "486DRx2");
523 break;
524 case 0x08:
525 strcat(cpu_model, "486SRu");
526 break;
527 case 0x09:
528 strcat(cpu_model, "486DRu");
529 break;
530 case 0x0a:
531 strcat(cpu_model, "486SRu2");
532 break;
533 case 0x0b:
534 strcat(cpu_model, "486DRu2");
535 break;
536 default:
537 strcat(cpu_model, "Unknown");
538 break;
539 }
540 break;
541 case 0x10:
542 switch (cyrix_did & 0x0f) {
543 case 0x00:
544 strcat(cpu_model, "486S");
545 break;
546 case 0x01:
547 strcat(cpu_model, "486S2");
548 break;
549 case 0x02:
550 strcat(cpu_model, "486Se");
551 break;
552 case 0x03:
553 strcat(cpu_model, "486S2e");
554 break;
555 case 0x0a:
556 strcat(cpu_model, "486DX");
557 break;
558 case 0x0b:
559 strcat(cpu_model, "486DX2");
560 break;
561 case 0x0f:
562 strcat(cpu_model, "486DX4");
563 break;
564 default:
565 strcat(cpu_model, "Unknown");
566 break;
567 }
568 break;
569 case 0x20:
570 if ((cyrix_did & 0x0f) < 8)
571 strcat(cpu_model, "6x86"); /* Where did you get it? */
572 else
573 strcat(cpu_model, "5x86");
574 break;
575 case 0x30:
576 strcat(cpu_model, "6x86");
577 break;
578 case 0x40:
579 if ((cyrix_did & 0xf000) == 0x3000) {
580 cpu_class = CPUCLASS_586;
581 strcat(cpu_model, "GXm");
582 } else
583 strcat(cpu_model, "MediaGX");
584 break;
585 case 0x50:
586 strcat(cpu_model, "6x86MX");
587 break;
588 case 0xf0:
589 switch (cyrix_did & 0x0f) {
590 case 0x0d:
591 strcat(cpu_model, "Overdrive CPU");
592 break;
593 case 0x0e:
594 strcpy(cpu_model, "Texas Instruments 486SXL");
595 break;
596 case 0x0f:
597 strcat(cpu_model, "486SLC/DLC");
598 break;
599 default:
600 strcat(cpu_model, "Unknown");
601 break;
602 }
603 break;
604 default:
605 strcat(cpu_model, "Unknown");
606 break;
607 }
608 break;
609 }
610 break;
611 case CPU_VENDOR_RISE:
612 strcpy(cpu_model, "Rise ");
613 switch (cpu_id & 0xff0) {
614 case 0x500: /* 6401 and 6441 (Kirin) */
615 case 0x520: /* 6510 (Lynx) */
616 strcat(cpu_model, "mP6");
617 break;
618 default:
619 strcat(cpu_model, "Unknown");
620 }
621 break;
622 #endif
623 case CPU_VENDOR_CENTAUR:
624 #ifdef __i386__
625 switch (cpu_id & 0xff0) {
626 case 0x540:
627 strcpy(cpu_model, "IDT WinChip C6");
628 break;
629 case 0x580:
630 strcpy(cpu_model, "IDT WinChip 2");
631 break;
632 case 0x590:
633 strcpy(cpu_model, "IDT WinChip 3");
634 break;
635 case 0x660:
636 strcpy(cpu_model, "VIA C3 Samuel");
637 break;
638 case 0x670:
639 if (cpu_id & 0x8)
640 strcpy(cpu_model, "VIA C3 Ezra");
641 else
642 strcpy(cpu_model, "VIA C3 Samuel 2");
643 break;
644 case 0x680:
645 strcpy(cpu_model, "VIA C3 Ezra-T");
646 break;
647 case 0x690:
648 strcpy(cpu_model, "VIA C3 Nehemiah");
649 break;
650 case 0x6a0:
651 case 0x6d0:
652 strcpy(cpu_model, "VIA C7 Esther");
653 break;
654 case 0x6f0:
655 strcpy(cpu_model, "VIA Nano");
656 break;
657 default:
658 strcpy(cpu_model, "VIA/IDT Unknown");
659 }
660 #else
661 strcpy(cpu_model, "VIA ");
662 if ((cpu_id & 0xff0) == 0x6f0)
663 strcat(cpu_model, "Nano Processor");
664 else
665 strcat(cpu_model, "Unknown");
666 #endif
667 break;
668 #ifdef __i386__
669 case CPU_VENDOR_IBM:
670 strcpy(cpu_model, "Blue Lightning CPU");
671 break;
672 case CPU_VENDOR_NSC:
673 switch (cpu_id & 0xff0) {
674 case 0x540:
675 strcpy(cpu_model, "Geode SC1100");
676 cpu = CPU_GEODE1100;
677 break;
678 default:
679 strcpy(cpu_model, "Geode/NSC unknown");
680 break;
681 }
682 break;
683 #endif
684 case CPU_VENDOR_HYGON:
685 strcpy(cpu_model, "Hygon ");
686 #ifdef __i386__
687 strcat(cpu_model, "Unknown");
688 #else
689 if ((cpu_id & 0xf00) == 0xf00)
690 strcat(cpu_model, "AMD64 Processor");
691 else
692 strcat(cpu_model, "Unknown");
693 #endif
694 break;
695
696 default:
697 strcat(cpu_model, "Unknown");
698 break;
699 }
700
701 /*
702 * Replace cpu_model with cpu_brand minus leading spaces if
703 * we have one.
704 */
705 brand = cpu_brand;
706 while (*brand == ' ')
707 ++brand;
708 if (*brand != '\0')
709 strcpy(cpu_model, brand);
710
711 printf("%s (", cpu_model);
712 if (tsc_freq != 0) {
713 hw_clockrate = (tsc_freq + 5000) / 1000000;
714 printf("%jd.%02d-MHz ",
715 (intmax_t)(tsc_freq + 4999) / 1000000,
716 (u_int)((tsc_freq + 4999) / 10000) % 100);
717 }
718 #ifdef __i386__
719 switch(cpu_class) {
720 case CPUCLASS_286:
721 printf("286");
722 break;
723 case CPUCLASS_386:
724 printf("386");
725 break;
726 #if defined(I486_CPU)
727 case CPUCLASS_486:
728 printf("486");
729 break;
730 #endif
731 #if defined(I586_CPU)
732 case CPUCLASS_586:
733 printf("586");
734 break;
735 #endif
736 #if defined(I686_CPU)
737 case CPUCLASS_686:
738 printf("686");
739 break;
740 #endif
741 default:
742 printf("Unknown"); /* will panic below... */
743 }
744 #else
745 printf("K8");
746 #endif
747 printf("-class CPU)\n");
748 if (*cpu_vendor)
749 printf(" Origin=\"%s\"", cpu_vendor);
750 if (cpu_id)
751 printf(" Id=0x%x", cpu_id);
752
753 if (cpu_vendor_id == CPU_VENDOR_INTEL ||
754 cpu_vendor_id == CPU_VENDOR_AMD ||
755 cpu_vendor_id == CPU_VENDOR_HYGON ||
756 cpu_vendor_id == CPU_VENDOR_CENTAUR ||
757 #ifdef __i386__
758 cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
759 cpu_vendor_id == CPU_VENDOR_RISE ||
760 cpu_vendor_id == CPU_VENDOR_NSC ||
761 (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) ||
762 #endif
763 0) {
764 printf(" Family=0x%x", CPUID_TO_FAMILY(cpu_id));
765 printf(" Model=0x%x", CPUID_TO_MODEL(cpu_id));
766 printf(" Stepping=%u", cpu_id & CPUID_STEPPING);
767 #ifdef __i386__
768 if (cpu_vendor_id == CPU_VENDOR_CYRIX)
769 printf("\n DIR=0x%04x", cyrix_did);
770 #endif
771
772 /*
773 * AMD CPUID Specification
774 * http://support.amd.com/us/Embedded_TechDocs/25481.pdf
775 *
776 * Intel Processor Identification and CPUID Instruction
777 * http://www.intel.com/assets/pdf/appnote/241618.pdf
778 */
779 if (cpu_high > 0) {
780 /*
781 * Here we should probably set up flags indicating
782 * whether or not various features are available.
783 * The interesting ones are probably VME, PSE, PAE,
784 * and PGE. The code already assumes without bothering
785 * to check that all CPUs >= Pentium have a TSC and
786 * MSRs.
787 */
788 printf("\n Features=0x%b", cpu_feature,
789 "\020"
790 "\001FPU" /* Integral FPU */
791 "\002VME" /* Extended VM86 mode support */
792 "\003DE" /* Debugging Extensions (CR4.DE) */
793 "\004PSE" /* 4MByte page tables */
794 "\005TSC" /* Timestamp counter */
795 "\006MSR" /* Machine specific registers */
796 "\007PAE" /* Physical address extension */
797 "\010MCE" /* Machine Check support */
798 "\011CX8" /* CMPEXCH8 instruction */
799 "\012APIC" /* SMP local APIC */
800 "\013oldMTRR" /* Previous implementation of MTRR */
801 "\014SEP" /* Fast System Call */
802 "\015MTRR" /* Memory Type Range Registers */
803 "\016PGE" /* PG_G (global bit) support */
804 "\017MCA" /* Machine Check Architecture */
805 "\020CMOV" /* CMOV instruction */
806 "\021PAT" /* Page attributes table */
807 "\022PSE36" /* 36 bit address space support */
808 "\023PN" /* Processor Serial number */
809 "\024CLFLUSH" /* Has the CLFLUSH instruction */
810 "\025<b20>"
811 "\026DTS" /* Debug Trace Store */
812 "\027ACPI" /* ACPI support */
813 "\030MMX" /* MMX instructions */
814 "\031FXSR" /* FXSAVE/FXRSTOR */
815 "\032SSE" /* Streaming SIMD Extensions */
816 "\033SSE2" /* Streaming SIMD Extensions #2 */
817 "\034SS" /* Self snoop */
818 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */
819 "\036TM" /* Thermal Monitor clock slowdown */
820 "\037IA64" /* CPU can execute IA64 instructions */
821 "\040PBE" /* Pending Break Enable */
822 );
823
824 if (cpu_feature2 != 0) {
825 printf("\n Features2=0x%b", cpu_feature2,
826 "\020"
827 "\001SSE3" /* SSE3 */
828 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
829 "\003DTES64" /* 64-bit Debug Trace */
830 "\004MON" /* MONITOR/MWAIT Instructions */
831 "\005DS_CPL" /* CPL Qualified Debug Store */
832 "\006VMX" /* Virtual Machine Extensions */
833 "\007SMX" /* Safer Mode Extensions */
834 "\010EST" /* Enhanced SpeedStep */
835 "\011TM2" /* Thermal Monitor 2 */
836 "\012SSSE3" /* SSSE3 */
837 "\013CNXT-ID" /* L1 context ID available */
838 "\014SDBG" /* IA32 silicon debug */
839 "\015FMA" /* Fused Multiply Add */
840 "\016CX16" /* CMPXCHG16B Instruction */
841 "\017xTPR" /* Send Task Priority Messages*/
842 "\020PDCM" /* Perf/Debug Capability MSR */
843 "\021<b16>"
844 "\022PCID" /* Process-context Identifiers*/
845 "\023DCA" /* Direct Cache Access */
846 "\024SSE4.1" /* SSE 4.1 */
847 "\025SSE4.2" /* SSE 4.2 */
848 "\026x2APIC" /* xAPIC Extensions */
849 "\027MOVBE" /* MOVBE Instruction */
850 "\030POPCNT" /* POPCNT Instruction */
851 "\031TSCDLT" /* TSC-Deadline Timer */
852 "\032AESNI" /* AES Crypto */
853 "\033XSAVE" /* XSAVE/XRSTOR States */
854 "\034OSXSAVE" /* OS-Enabled State Management*/
855 "\035AVX" /* Advanced Vector Extensions */
856 "\036F16C" /* Half-precision conversions */
857 "\037RDRAND" /* RDRAND Instruction */
858 "\040HV" /* Hypervisor */
859 );
860 }
861
862 if (amd_feature != 0) {
863 printf("\n AMD Features=0x%b", amd_feature,
864 "\020" /* in hex */
865 "\001<s0>" /* Same */
866 "\002<s1>" /* Same */
867 "\003<s2>" /* Same */
868 "\004<s3>" /* Same */
869 "\005<s4>" /* Same */
870 "\006<s5>" /* Same */
871 "\007<s6>" /* Same */
872 "\010<s7>" /* Same */
873 "\011<s8>" /* Same */
874 "\012<s9>" /* Same */
875 "\013<b10>" /* Undefined */
876 "\014SYSCALL" /* Have SYSCALL/SYSRET */
877 "\015<s12>" /* Same */
878 "\016<s13>" /* Same */
879 "\017<s14>" /* Same */
880 "\020<s15>" /* Same */
881 "\021<s16>" /* Same */
882 "\022<s17>" /* Same */
883 "\023<b18>" /* Reserved, unknown */
884 "\024MP" /* Multiprocessor Capable */
885 "\025NX" /* Has EFER.NXE, NX */
886 "\026<b21>" /* Undefined */
887 "\027MMX+" /* AMD MMX Extensions */
888 "\030<s23>" /* Same */
889 "\031<s24>" /* Same */
890 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */
891 "\033Page1GB" /* 1-GB large page support */
892 "\034RDTSCP" /* RDTSCP */
893 "\035<b28>" /* Undefined */
894 "\036LM" /* 64 bit long mode */
895 "\0373DNow!+" /* AMD 3DNow! Extensions */
896 "\0403DNow!" /* AMD 3DNow! */
897 );
898 }
899
900 if (amd_feature2 != 0) {
901 printf("\n AMD Features2=0x%b", amd_feature2,
902 "\020"
903 "\001LAHF" /* LAHF/SAHF in long mode */
904 "\002CMP" /* CMP legacy */
905 "\003SVM" /* Secure Virtual Mode */
906 "\004ExtAPIC" /* Extended APIC register */
907 "\005CR8" /* CR8 in legacy mode */
908 "\006ABM" /* LZCNT instruction */
909 "\007SSE4A" /* SSE4A */
910 "\010MAS" /* Misaligned SSE mode */
911 "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */
912 "\012OSVW" /* OS visible workaround */
913 "\013IBS" /* Instruction based sampling */
914 "\014XOP" /* XOP extended instructions */
915 "\015SKINIT" /* SKINIT/STGI */
916 "\016WDT" /* Watchdog timer */
917 "\017<b14>"
918 "\020LWP" /* Lightweight Profiling */
919 "\021FMA4" /* 4-operand FMA instructions */
920 "\022TCE" /* Translation Cache Extension */
921 "\023<b18>"
922 "\024NodeId" /* NodeId MSR support */
923 "\025<b20>"
924 "\026TBM" /* Trailing Bit Manipulation */
925 "\027Topology" /* Topology Extensions */
926 "\030PCXC" /* Core perf count */
927 "\031PNXC" /* NB perf count */
928 "\032<b25>"
929 "\033DBE" /* Data Breakpoint extension */
930 "\034PTSC" /* Performance TSC */
931 "\035PL2I" /* L2I perf count */
932 "\036MWAITX" /* MONITORX/MWAITX instructions */
933 "\037ADMSKX" /* Address mask extension */
934 "\040<b31>"
935 );
936 }
937
938 if (cpu_stdext_feature != 0) {
939 printf("\n Structured Extended Features=0x%b",
940 cpu_stdext_feature,
941 "\020"
942 /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
943 "\001FSGSBASE"
944 "\002TSCADJ"
945 "\003SGX"
946 /* Bit Manipulation Instructions */
947 "\004BMI1"
948 /* Hardware Lock Elision */
949 "\005HLE"
950 /* Advanced Vector Instructions 2 */
951 "\006AVX2"
952 /* FDP_EXCPTN_ONLY */
953 "\007FDPEXC"
954 /* Supervisor Mode Execution Prot. */
955 "\010SMEP"
956 /* Bit Manipulation Instructions */
957 "\011BMI2"
958 "\012ERMS"
959 /* Invalidate Processor Context ID */
960 "\013INVPCID"
961 /* Restricted Transactional Memory */
962 "\014RTM"
963 "\015PQM"
964 "\016NFPUSG"
965 /* Intel Memory Protection Extensions */
966 "\017MPX"
967 "\020PQE"
968 /* AVX512 Foundation */
969 "\021AVX512F"
970 "\022AVX512DQ"
971 /* Enhanced NRBG */
972 "\023RDSEED"
973 /* ADCX + ADOX */
974 "\024ADX"
975 /* Supervisor Mode Access Prevention */
976 "\025SMAP"
977 "\026AVX512IFMA"
978 /* Formerly PCOMMIT */
979 "\027<b22>"
980 "\030CLFLUSHOPT"
981 "\031CLWB"
982 "\032PROCTRACE"
983 "\033AVX512PF"
984 "\034AVX512ER"
985 "\035AVX512CD"
986 "\036SHA"
987 "\037AVX512BW"
988 "\040AVX512VL"
989 );
990 }
991
992 if (cpu_stdext_feature2 != 0) {
993 printf("\n Structured Extended Features2=0x%b",
994 cpu_stdext_feature2,
995 "\020"
996 "\001PREFETCHWT1"
997 "\002AVX512VBMI"
998 "\003UMIP"
999 "\004PKU"
1000 "\005OSPKE"
1001 "\006WAITPKG"
1002 "\007AVX512VBMI2"
1003 "\011GFNI"
1004 "\012VAES"
1005 "\013VPCLMULQDQ"
1006 "\014AVX512VNNI"
1007 "\015AVX512BITALG"
1008 "\016TME"
1009 "\017AVX512VPOPCNTDQ"
1010 "\021LA57"
1011 "\027RDPID"
1012 "\032CLDEMOTE"
1013 "\034MOVDIRI"
1014 "\035MOVDIR64B"
1015 "\036ENQCMD"
1016 "\037SGXLC"
1017 );
1018 }
1019
1020 if (cpu_stdext_feature3 != 0) {
1021 printf("\n Structured Extended Features3=0x%b",
1022 cpu_stdext_feature3,
1023 "\020"
1024 "\003AVX512_4VNNIW"
1025 "\004AVX512_4FMAPS"
1026 "\005FSRM"
1027 "\011AVX512VP2INTERSECT"
1028 "\012MCUOPT"
1029 "\013MD_CLEAR"
1030 "\016TSXFA"
1031 "\023PCONFIG"
1032 "\025IBT"
1033 "\033IBPB"
1034 "\034STIBP"
1035 "\035L1DFL"
1036 "\036ARCH_CAP"
1037 "\037CORE_CAP"
1038 "\040SSBD"
1039 );
1040 }
1041
1042 if ((cpu_feature2 & CPUID2_XSAVE) != 0) {
1043 cpuid_count(0xd, 0x1, regs);
1044 if (regs[0] != 0) {
1045 printf("\n XSAVE Features=0x%b",
1046 regs[0],
1047 "\020"
1048 "\001XSAVEOPT"
1049 "\002XSAVEC"
1050 "\003XINUSE"
1051 "\004XSAVES");
1052 }
1053 }
1054
1055 if (cpu_ia32_arch_caps != 0) {
1056 printf("\n IA32_ARCH_CAPS=0x%b",
1057 (u_int)cpu_ia32_arch_caps,
1058 "\020"
1059 "\001RDCL_NO"
1060 "\002IBRS_ALL"
1061 "\003RSBA"
1062 "\004SKIP_L1DFL_VME"
1063 "\005SSB_NO"
1064 "\006MDS_NO"
1065 "\010TSX_CTRL"
1066 "\011TAA_NO"
1067 );
1068 }
1069
1070 if (amd_extended_feature_extensions != 0) {
1071 u_int amd_fe_masked;
1072
1073 amd_fe_masked = amd_extended_feature_extensions;
1074 if ((amd_fe_masked & AMDFEID_IBRS) == 0)
1075 amd_fe_masked &=
1076 ~(AMDFEID_IBRS_ALWAYSON |
1077 AMDFEID_PREFER_IBRS);
1078 if ((amd_fe_masked & AMDFEID_STIBP) == 0)
1079 amd_fe_masked &=
1080 ~AMDFEID_STIBP_ALWAYSON;
1081
1082 printf("\n "
1083 "AMD Extended Feature Extensions ID EBX="
1084 "0x%b", amd_fe_masked,
1085 "\020"
1086 "\001CLZERO"
1087 "\002IRPerf"
1088 "\003XSaveErPtr"
1089 "\004INVLPGB"
1090 "\005RDPRU"
1091 "\007BE"
1092 "\011MCOMMIT"
1093 "\012WBNOINVD"
1094 "\015IBPB"
1095 "\016INT_WBINVD"
1096 "\017IBRS"
1097 "\020STIBP"
1098 "\021IBRS_ALWAYSON"
1099 "\022STIBP_ALWAYSON"
1100 "\023PREFER_IBRS"
1101 "\024SAMEMODE_IBRS"
1102 "\025NOLMSLE"
1103 "\026INVLPGBNEST"
1104 "\030PPIN"
1105 "\031SSBD"
1106 "\032VIRT_SSBD"
1107 "\033SSB_NO"
1108 "\034CPPC"
1109 "\035PSFD"
1110 "\036BTC_NO"
1111 "\037IBPB_RET"
1112 );
1113 }
1114
1115 if (via_feature_rng != 0 || via_feature_xcrypt != 0)
1116 print_via_padlock_info();
1117
1118 if (cpu_feature2 & CPUID2_VMX)
1119 print_vmx_info();
1120
1121 if (amd_feature2 & AMDID2_SVM)
1122 print_svm_info();
1123
1124 if ((cpu_feature & CPUID_HTT) &&
1125 (cpu_vendor_id == CPU_VENDOR_AMD ||
1126 cpu_vendor_id == CPU_VENDOR_HYGON))
1127 cpu_feature &= ~CPUID_HTT;
1128
1129 /*
1130 * If this CPU supports P-state invariant TSC then
1131 * mention the capability.
1132 */
1133 if (tsc_is_invariant) {
1134 printf("\n TSC: P-state invariant");
1135 if (tsc_perf_stat)
1136 printf(", performance statistics");
1137 }
1138 }
1139 #ifdef __i386__
1140 } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1141 printf(" DIR=0x%04x", cyrix_did);
1142 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12);
1143 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8);
1144 #ifndef CYRIX_CACHE_REALLY_WORKS
1145 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
1146 printf("\n CPU cache: write-through mode");
1147 #endif
1148 #endif
1149 }
1150
1151 /* Avoid ugly blank lines: only print newline when we have to. */
1152 if (*cpu_vendor || cpu_id)
1153 printf("\n");
1154
1155 if (bootverbose) {
1156 if (cpu_vendor_id == CPU_VENDOR_AMD ||
1157 cpu_vendor_id == CPU_VENDOR_HYGON)
1158 print_AMD_info();
1159 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
1160 print_INTEL_info();
1161 #ifdef __i386__
1162 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
1163 print_transmeta_info();
1164 #endif
1165 }
1166
1167 print_hypervisor_info();
1168 }
1169
1170 #ifdef __i386__
1171 void
panicifcpuunsupported(void)1172 panicifcpuunsupported(void)
1173 {
1174
1175 #if !defined(lint)
1176 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
1177 #error This kernel is not configured for one of the supported CPUs
1178 #endif
1179 #else /* lint */
1180 #endif /* lint */
1181 /*
1182 * Now that we have told the user what they have,
1183 * let them know if that machine type isn't configured.
1184 */
1185 switch (cpu_class) {
1186 case CPUCLASS_286: /* a 286 should not make it this far, anyway */
1187 case CPUCLASS_386:
1188 #if !defined(I486_CPU)
1189 case CPUCLASS_486:
1190 #endif
1191 #if !defined(I586_CPU)
1192 case CPUCLASS_586:
1193 #endif
1194 #if !defined(I686_CPU)
1195 case CPUCLASS_686:
1196 #endif
1197 panic("CPU class not configured");
1198 default:
1199 break;
1200 }
1201 }
1202
1203 static volatile u_int trap_by_rdmsr;
1204
1205 /*
1206 * Special exception 6 handler.
1207 * The rdmsr instruction generates invalid opcodes fault on 486-class
1208 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the
1209 * function identblue() when this handler is called. Stacked eip should
1210 * be advanced.
1211 */
1212 inthand_t bluetrap6;
1213 #ifdef __GNUCLIKE_ASM
1214 __asm
1215 (" \n\
1216 .text \n\
1217 .p2align 2,0x90 \n\
1218 .type " __XSTRING(CNAME(bluetrap6)) ",@function \n\
1219 " __XSTRING(CNAME(bluetrap6)) ": \n\
1220 ss \n\
1221 movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
1222 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
1223 iret \n\
1224 ");
1225 #endif
1226
1227 /*
1228 * Special exception 13 handler.
1229 * Accessing non-existent MSR generates general protection fault.
1230 */
1231 inthand_t bluetrap13;
1232 #ifdef __GNUCLIKE_ASM
1233 __asm
1234 (" \n\
1235 .text \n\
1236 .p2align 2,0x90 \n\
1237 .type " __XSTRING(CNAME(bluetrap13)) ",@function \n\
1238 " __XSTRING(CNAME(bluetrap13)) ": \n\
1239 ss \n\
1240 movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
1241 popl %eax /* discard error code */ \n\
1242 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
1243 iret \n\
1244 ");
1245 #endif
1246
1247 /*
1248 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
1249 * support cpuid instruction. This function should be called after
1250 * loading interrupt descriptor table register.
1251 *
1252 * I don't like this method that handles fault, but I couldn't get
1253 * information for any other methods. Does blue giant know?
1254 */
1255 static int
identblue(void)1256 identblue(void)
1257 {
1258
1259 trap_by_rdmsr = 0;
1260
1261 /*
1262 * Cyrix 486-class CPU does not support rdmsr instruction.
1263 * The rdmsr instruction generates invalid opcode fault, and exception
1264 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The
1265 * bluetrap6() set the magic number to trap_by_rdmsr.
1266 */
1267 setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
1268 GSEL(GCODE_SEL, SEL_KPL));
1269
1270 /*
1271 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
1272 * In this case, rdmsr generates general protection fault, and
1273 * exception will be trapped by bluetrap13().
1274 */
1275 setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
1276 GSEL(GCODE_SEL, SEL_KPL));
1277
1278 rdmsr(0x1002); /* Cyrix CPU generates fault. */
1279
1280 if (trap_by_rdmsr == 0xa8c1d)
1281 return IDENTBLUE_CYRIX486;
1282 else if (trap_by_rdmsr == 0xa89c4)
1283 return IDENTBLUE_CYRIXM2;
1284 return IDENTBLUE_IBMCPU;
1285 }
1286
1287 /*
1288 * identifycyrix() set lower 16 bits of cyrix_did as follows:
1289 *
1290 * F E D C B A 9 8 7 6 5 4 3 2 1 0
1291 * +-------+-------+---------------+
1292 * | SID | RID | Device ID |
1293 * | (DIR 1) | (DIR 0) |
1294 * +-------+-------+---------------+
1295 */
1296 static void
identifycyrix(void)1297 identifycyrix(void)
1298 {
1299 register_t saveintr;
1300 int ccr2_test = 0, dir_test = 0;
1301 u_char ccr2, ccr3;
1302
1303 saveintr = intr_disable();
1304
1305 ccr2 = read_cyrix_reg(CCR2);
1306 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
1307 read_cyrix_reg(CCR2);
1308 if (read_cyrix_reg(CCR2) != ccr2)
1309 ccr2_test = 1;
1310 write_cyrix_reg(CCR2, ccr2);
1311
1312 ccr3 = read_cyrix_reg(CCR3);
1313 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
1314 read_cyrix_reg(CCR3);
1315 if (read_cyrix_reg(CCR3) != ccr3)
1316 dir_test = 1; /* CPU supports DIRs. */
1317 write_cyrix_reg(CCR3, ccr3);
1318
1319 if (dir_test) {
1320 /* Device ID registers are available. */
1321 cyrix_did = read_cyrix_reg(DIR1) << 8;
1322 cyrix_did += read_cyrix_reg(DIR0);
1323 } else if (ccr2_test)
1324 cyrix_did = 0x0010; /* 486S A-step */
1325 else
1326 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */
1327
1328 intr_restore(saveintr);
1329 }
1330 #endif
1331
1332 /* Update TSC freq with the value indicated by the caller. */
1333 static void
tsc_freq_changed(void * arg __unused,const struct cf_level * level,int status)1334 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status)
1335 {
1336
1337 /* If there was an error during the transition, don't do anything. */
1338 if (status != 0)
1339 return;
1340
1341 /* Total setting for this level gives the new frequency in MHz. */
1342 hw_clockrate = level->total_set.freq;
1343 }
1344
1345 static void
hook_tsc_freq(void * arg __unused)1346 hook_tsc_freq(void *arg __unused)
1347 {
1348
1349 if (tsc_is_invariant)
1350 return;
1351
1352 tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change,
1353 tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY);
1354 }
1355
1356 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL);
1357
1358 static const struct {
1359 const char * vm_bname;
1360 int vm_guest;
1361 } vm_bnames[] = {
1362 { "QEMU", VM_GUEST_VM }, /* QEMU */
1363 { "Plex86", VM_GUEST_VM }, /* Plex86 */
1364 { "Bochs", VM_GUEST_VM }, /* Bochs */
1365 { "Xen", VM_GUEST_XEN }, /* Xen */
1366 { "BHYVE", VM_GUEST_BHYVE }, /* bhyve */
1367 { "Seabios", VM_GUEST_KVM }, /* KVM */
1368 };
1369
1370 static const struct {
1371 const char * vm_pname;
1372 int vm_guest;
1373 } vm_pnames[] = {
1374 { "VMware Virtual Platform", VM_GUEST_VMWARE },
1375 { "Virtual Machine", VM_GUEST_VM }, /* Microsoft VirtualPC */
1376 { "VirtualBox", VM_GUEST_VBOX },
1377 { "Parallels Virtual Platform", VM_GUEST_PARALLELS },
1378 { "KVM", VM_GUEST_KVM },
1379 };
1380
1381 static struct {
1382 const char *vm_cpuid;
1383 int vm_guest;
1384 } vm_cpuids[] = {
1385 { "XenVMMXenVMM", VM_GUEST_XEN }, /* XEN */
1386 { "Microsoft Hv", VM_GUEST_HV }, /* Microsoft Hyper-V */
1387 { "VMwareVMware", VM_GUEST_VMWARE }, /* VMware VM */
1388 { "KVMKVMKVM", VM_GUEST_KVM }, /* KVM */
1389 { "bhyve bhyve ", VM_GUEST_BHYVE }, /* bhyve */
1390 { "VBoxVBoxVBox", VM_GUEST_VBOX }, /* VirtualBox */
1391 { "___ NVMM ___", VM_GUEST_NVMM }, /* NVMM */
1392 };
1393
1394 static void
identify_hypervisor_cpuid_base(void)1395 identify_hypervisor_cpuid_base(void)
1396 {
1397 u_int leaf, regs[4];
1398 int i;
1399
1400 /*
1401 * [RFC] CPUID usage for interaction between Hypervisors and Linux.
1402 * http://lkml.org/lkml/2008/10/1/246
1403 *
1404 * KB1009458: Mechanisms to determine if software is running in
1405 * a VMware virtual machine
1406 * http://kb.vmware.com/kb/1009458
1407 *
1408 * Search for a hypervisor that we recognize. If we cannot find
1409 * a specific hypervisor, return the first information about the
1410 * hypervisor that we found, as others may be able to use.
1411 */
1412 for (leaf = 0x40000000; leaf < 0x40010000; leaf += 0x100) {
1413 do_cpuid(leaf, regs);
1414
1415 /*
1416 * KVM from Linux kernels prior to commit
1417 * 57c22e5f35aa4b9b2fe11f73f3e62bbf9ef36190 set %eax
1418 * to 0 rather than a valid hv_high value. Check for
1419 * the KVM signature bytes and fixup %eax to the
1420 * highest supported leaf in that case.
1421 */
1422 if (regs[0] == 0 && regs[1] == 0x4b4d564b &&
1423 regs[2] == 0x564b4d56 && regs[3] == 0x0000004d)
1424 regs[0] = leaf + 1;
1425
1426 if (regs[0] >= leaf) {
1427 for (i = 0; i < nitems(vm_cpuids); i++)
1428 if (strncmp((const char *)®s[1],
1429 vm_cpuids[i].vm_cpuid, 12) == 0) {
1430 vm_guest = vm_cpuids[i].vm_guest;
1431 break;
1432 }
1433
1434 /*
1435 * If this is the first entry or we found a
1436 * specific hypervisor, record the base, high value,
1437 * and vendor identifier.
1438 */
1439 if (vm_guest != VM_GUEST_VM || leaf == 0x40000000) {
1440 hv_base = leaf;
1441 hv_high = regs[0];
1442 ((u_int *)&hv_vendor)[0] = regs[1];
1443 ((u_int *)&hv_vendor)[1] = regs[2];
1444 ((u_int *)&hv_vendor)[2] = regs[3];
1445 hv_vendor[12] = '\0';
1446
1447 /*
1448 * If we found a specific hypervisor, then
1449 * we are finished.
1450 */
1451 if (vm_guest != VM_GUEST_VM)
1452 return;
1453 }
1454 }
1455 }
1456 }
1457
1458 void
identify_hypervisor(void)1459 identify_hypervisor(void)
1460 {
1461 u_int regs[4];
1462 char *p;
1463 int i;
1464
1465 /*
1466 * If CPUID2_HV is set, we are running in a hypervisor environment.
1467 */
1468 if (cpu_feature2 & CPUID2_HV) {
1469 vm_guest = VM_GUEST_VM;
1470 identify_hypervisor_cpuid_base();
1471
1472 /* If we have a definitive vendor, we can return now. */
1473 if (*hv_vendor != '\0')
1474 return;
1475 }
1476
1477 /*
1478 * Examine SMBIOS strings for older hypervisors.
1479 */
1480 p = kern_getenv("smbios.system.serial");
1481 if (p != NULL) {
1482 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) {
1483 vmware_hvcall(VMW_HVCMD_GETVERSION, regs);
1484 if (regs[1] == VMW_HVMAGIC) {
1485 vm_guest = VM_GUEST_VMWARE;
1486 freeenv(p);
1487 return;
1488 }
1489 }
1490 freeenv(p);
1491 }
1492
1493 /*
1494 * XXX: Some of these entries may not be needed since they were
1495 * added to FreeBSD before the checks above.
1496 */
1497 p = kern_getenv("smbios.bios.vendor");
1498 if (p != NULL) {
1499 for (i = 0; i < nitems(vm_bnames); i++)
1500 if (strcmp(p, vm_bnames[i].vm_bname) == 0) {
1501 vm_guest = vm_bnames[i].vm_guest;
1502 /* If we have a specific match, return */
1503 if (vm_guest != VM_GUEST_VM) {
1504 freeenv(p);
1505 return;
1506 }
1507 /*
1508 * We are done with bnames, but there might be
1509 * a more specific match in the pnames
1510 */
1511 break;
1512 }
1513 freeenv(p);
1514 }
1515 p = kern_getenv("smbios.system.product");
1516 if (p != NULL) {
1517 for (i = 0; i < nitems(vm_pnames); i++)
1518 if (strcmp(p, vm_pnames[i].vm_pname) == 0) {
1519 vm_guest = vm_pnames[i].vm_guest;
1520 freeenv(p);
1521 return;
1522 }
1523 freeenv(p);
1524 }
1525 }
1526
1527 bool
fix_cpuid(void)1528 fix_cpuid(void)
1529 {
1530 uint64_t msr;
1531
1532 /*
1533 * Clear "Limit CPUID Maxval" bit and return true if the caller should
1534 * get the largest standard CPUID function number again if it is set
1535 * from BIOS. It is necessary for probing correct CPU topology later
1536 * and for the correct operation of the AVX-aware userspace.
1537 */
1538 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
1539 ((CPUID_TO_FAMILY(cpu_id) == 0xf &&
1540 CPUID_TO_MODEL(cpu_id) >= 0x3) ||
1541 (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1542 CPUID_TO_MODEL(cpu_id) >= 0xe))) {
1543 msr = rdmsr(MSR_IA32_MISC_ENABLE);
1544 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) {
1545 msr &= ~IA32_MISC_EN_LIMCPUID;
1546 wrmsr(MSR_IA32_MISC_ENABLE, msr);
1547 return (true);
1548 }
1549 }
1550
1551 /*
1552 * Re-enable AMD Topology Extension that could be disabled by BIOS
1553 * on some notebook processors. Without the extension it's really
1554 * hard to determine the correct CPU cache topology.
1555 * See BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h
1556 * Models 60h-6Fh Processors, Publication # 50742.
1557 */
1558 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_AMD &&
1559 CPUID_TO_FAMILY(cpu_id) == 0x15) {
1560 msr = rdmsr(MSR_EXTFEATURES);
1561 if ((msr & ((uint64_t)1 << 54)) == 0) {
1562 msr |= (uint64_t)1 << 54;
1563 wrmsr(MSR_EXTFEATURES, msr);
1564 return (true);
1565 }
1566 }
1567 return (false);
1568 }
1569
1570 void
identify_cpu1(void)1571 identify_cpu1(void)
1572 {
1573 u_int regs[4];
1574
1575 do_cpuid(0, regs);
1576 cpu_high = regs[0];
1577 ((u_int *)&cpu_vendor)[0] = regs[1];
1578 ((u_int *)&cpu_vendor)[1] = regs[3];
1579 ((u_int *)&cpu_vendor)[2] = regs[2];
1580 cpu_vendor[12] = '\0';
1581
1582 do_cpuid(1, regs);
1583 cpu_id = regs[0];
1584 cpu_procinfo = regs[1];
1585 cpu_feature = regs[3];
1586 cpu_feature2 = regs[2];
1587 }
1588
1589 void
identify_cpu2(void)1590 identify_cpu2(void)
1591 {
1592 u_int regs[4], cpu_stdext_disable;
1593
1594 if (cpu_high >= 6) {
1595 cpuid_count(6, 0, regs);
1596 cpu_power_eax = regs[0];
1597 cpu_power_ebx = regs[1];
1598 cpu_power_ecx = regs[2];
1599 cpu_power_edx = regs[3];
1600 }
1601
1602 if (cpu_high >= 7) {
1603 cpuid_count(7, 0, regs);
1604 cpu_stdext_feature = regs[1];
1605
1606 /*
1607 * Some hypervisors failed to filter out unsupported
1608 * extended features. Allow to disable the
1609 * extensions, activation of which requires setting a
1610 * bit in CR4, and which VM monitors do not support.
1611 */
1612 cpu_stdext_disable = 0;
1613 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable);
1614 cpu_stdext_feature &= ~cpu_stdext_disable;
1615
1616 cpu_stdext_feature2 = regs[2];
1617 cpu_stdext_feature3 = regs[3];
1618
1619 if ((cpu_stdext_feature3 & CPUID_STDEXT3_ARCH_CAP) != 0)
1620 cpu_ia32_arch_caps = rdmsr(MSR_IA32_ARCH_CAP);
1621 }
1622 }
1623
1624 void
identify_cpu_ext_features(void)1625 identify_cpu_ext_features(void)
1626 {
1627 u_int regs[4];
1628
1629 if (cpu_high >= 7) {
1630 cpuid_count(7, 0, regs);
1631 cpu_stdext_feature2 = regs[2];
1632 cpu_stdext_feature3 = regs[3];
1633 }
1634 }
1635
1636 void
identify_cpu_fixup_bsp(void)1637 identify_cpu_fixup_bsp(void)
1638 {
1639 u_int regs[4];
1640
1641 cpu_vendor_id = find_cpu_vendor_id();
1642
1643 if (fix_cpuid()) {
1644 do_cpuid(0, regs);
1645 cpu_high = regs[0];
1646 }
1647 }
1648
1649 /*
1650 * Final stage of CPU identification.
1651 */
1652 void
finishidentcpu(void)1653 finishidentcpu(void)
1654 {
1655 u_int regs[4];
1656 #ifdef __i386__
1657 u_char ccr3;
1658 #endif
1659
1660 identify_cpu_fixup_bsp();
1661
1662 if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) {
1663 do_cpuid(5, regs);
1664 cpu_mon_mwait_flags = regs[2];
1665 cpu_mon_min_size = regs[0] & CPUID5_MON_MIN_SIZE;
1666 cpu_mon_max_size = regs[1] & CPUID5_MON_MAX_SIZE;
1667 }
1668
1669 identify_cpu2();
1670
1671 #ifdef __i386__
1672 if (cpu_high > 0 &&
1673 (cpu_vendor_id == CPU_VENDOR_INTEL ||
1674 cpu_vendor_id == CPU_VENDOR_AMD ||
1675 cpu_vendor_id == CPU_VENDOR_HYGON ||
1676 cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
1677 cpu_vendor_id == CPU_VENDOR_CENTAUR ||
1678 cpu_vendor_id == CPU_VENDOR_NSC)) {
1679 do_cpuid(0x80000000, regs);
1680 if (regs[0] >= 0x80000000)
1681 cpu_exthigh = regs[0];
1682 }
1683 #else
1684 if (cpu_vendor_id == CPU_VENDOR_INTEL ||
1685 cpu_vendor_id == CPU_VENDOR_AMD ||
1686 cpu_vendor_id == CPU_VENDOR_HYGON ||
1687 cpu_vendor_id == CPU_VENDOR_CENTAUR) {
1688 do_cpuid(0x80000000, regs);
1689 cpu_exthigh = regs[0];
1690 }
1691 #endif
1692 if (cpu_exthigh >= 0x80000001) {
1693 do_cpuid(0x80000001, regs);
1694 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
1695 amd_feature2 = regs[2];
1696 }
1697 if (cpu_exthigh >= 0x80000007) {
1698 do_cpuid(0x80000007, regs);
1699 amd_rascap = regs[1];
1700 amd_pminfo = regs[3];
1701 }
1702 if (cpu_exthigh >= 0x80000008) {
1703 do_cpuid(0x80000008, regs);
1704 cpu_maxphyaddr = regs[0] & 0xff;
1705 amd_extended_feature_extensions = regs[1];
1706 cpu_procinfo2 = regs[2];
1707 cpu_procinfo3 = regs[3];
1708 } else {
1709 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32;
1710 }
1711
1712 #ifdef __i386__
1713 if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1714 if (cpu == CPU_486) {
1715 /*
1716 * These conditions are equivalent to:
1717 * - CPU does not support cpuid instruction.
1718 * - Cyrix/IBM CPU is detected.
1719 */
1720 if (identblue() == IDENTBLUE_IBMCPU) {
1721 strcpy(cpu_vendor, "IBM");
1722 cpu_vendor_id = CPU_VENDOR_IBM;
1723 cpu = CPU_BLUE;
1724 return;
1725 }
1726 }
1727 switch (cpu_id & 0xf00) {
1728 case 0x600:
1729 /*
1730 * Cyrix's datasheet does not describe DIRs.
1731 * Therefor, I assume it does not have them
1732 * and use the result of the cpuid instruction.
1733 * XXX they seem to have it for now at least. -Peter
1734 */
1735 identifycyrix();
1736 cpu = CPU_M2;
1737 break;
1738 default:
1739 identifycyrix();
1740 /*
1741 * This routine contains a trick.
1742 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
1743 */
1744 switch (cyrix_did & 0x00f0) {
1745 case 0x00:
1746 case 0xf0:
1747 cpu = CPU_486DLC;
1748 break;
1749 case 0x10:
1750 cpu = CPU_CY486DX;
1751 break;
1752 case 0x20:
1753 if ((cyrix_did & 0x000f) < 8)
1754 cpu = CPU_M1;
1755 else
1756 cpu = CPU_M1SC;
1757 break;
1758 case 0x30:
1759 cpu = CPU_M1;
1760 break;
1761 case 0x40:
1762 /* MediaGX CPU */
1763 cpu = CPU_M1SC;
1764 break;
1765 default:
1766 /* M2 and later CPUs are treated as M2. */
1767 cpu = CPU_M2;
1768
1769 /*
1770 * enable cpuid instruction.
1771 */
1772 ccr3 = read_cyrix_reg(CCR3);
1773 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1774 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1775 write_cyrix_reg(CCR3, ccr3);
1776
1777 do_cpuid(0, regs);
1778 cpu_high = regs[0]; /* eax */
1779 do_cpuid(1, regs);
1780 cpu_id = regs[0]; /* eax */
1781 cpu_feature = regs[3]; /* edx */
1782 break;
1783 }
1784 }
1785 } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1786 /*
1787 * There are BlueLightning CPUs that do not change
1788 * undefined flags by dividing 5 by 2. In this case,
1789 * the CPU identification routine in locore.s leaves
1790 * cpu_vendor null string and puts CPU_486 into the
1791 * cpu.
1792 */
1793 if (identblue() == IDENTBLUE_IBMCPU) {
1794 strcpy(cpu_vendor, "IBM");
1795 cpu_vendor_id = CPU_VENDOR_IBM;
1796 cpu = CPU_BLUE;
1797 return;
1798 }
1799 }
1800 #endif
1801 }
1802
1803 int
pti_get_default(void)1804 pti_get_default(void)
1805 {
1806
1807 if (strcmp(cpu_vendor, AMD_VENDOR_ID) == 0 ||
1808 strcmp(cpu_vendor, HYGON_VENDOR_ID) == 0)
1809 return (0);
1810 if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_RDCL_NO) != 0)
1811 return (0);
1812 return (1);
1813 }
1814
1815 static u_int
find_cpu_vendor_id(void)1816 find_cpu_vendor_id(void)
1817 {
1818 int i;
1819
1820 for (i = 0; i < nitems(cpu_vendors); i++)
1821 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
1822 return (cpu_vendors[i].vendor_id);
1823 return (0);
1824 }
1825
1826 static void
print_AMD_assoc(int i)1827 print_AMD_assoc(int i)
1828 {
1829 if (i == 255)
1830 printf(", fully associative\n");
1831 else
1832 printf(", %d-way associative\n", i);
1833 }
1834
1835 static void
print_AMD_l2_assoc(int i)1836 print_AMD_l2_assoc(int i)
1837 {
1838 switch (i & 0x0f) {
1839 case 0: printf(", disabled/not present\n"); break;
1840 case 1: printf(", direct mapped\n"); break;
1841 case 2: printf(", 2-way associative\n"); break;
1842 case 4: printf(", 4-way associative\n"); break;
1843 case 6: printf(", 8-way associative\n"); break;
1844 case 8: printf(", 16-way associative\n"); break;
1845 case 15: printf(", fully associative\n"); break;
1846 default: printf(", reserved configuration\n"); break;
1847 }
1848 }
1849
1850 static void
print_AMD_info(void)1851 print_AMD_info(void)
1852 {
1853 #ifdef __i386__
1854 uint64_t amd_whcr;
1855 #endif
1856 u_int regs[4];
1857
1858 if (cpu_exthigh >= 0x80000005) {
1859 do_cpuid(0x80000005, regs);
1860 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
1861 print_AMD_assoc(regs[0] >> 24);
1862
1863 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
1864 print_AMD_assoc((regs[0] >> 8) & 0xff);
1865
1866 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
1867 print_AMD_assoc(regs[1] >> 24);
1868
1869 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
1870 print_AMD_assoc((regs[1] >> 8) & 0xff);
1871
1872 printf("L1 data cache: %d kbytes", regs[2] >> 24);
1873 printf(", %d bytes/line", regs[2] & 0xff);
1874 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1875 print_AMD_assoc((regs[2] >> 16) & 0xff);
1876
1877 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1878 printf(", %d bytes/line", regs[3] & 0xff);
1879 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1880 print_AMD_assoc((regs[3] >> 16) & 0xff);
1881 }
1882
1883 if (cpu_exthigh >= 0x80000006) {
1884 do_cpuid(0x80000006, regs);
1885 if ((regs[0] >> 16) != 0) {
1886 printf("L2 2MB data TLB: %d entries",
1887 (regs[0] >> 16) & 0xfff);
1888 print_AMD_l2_assoc(regs[0] >> 28);
1889 printf("L2 2MB instruction TLB: %d entries",
1890 regs[0] & 0xfff);
1891 print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1892 } else {
1893 printf("L2 2MB unified TLB: %d entries",
1894 regs[0] & 0xfff);
1895 print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1896 }
1897 if ((regs[1] >> 16) != 0) {
1898 printf("L2 4KB data TLB: %d entries",
1899 (regs[1] >> 16) & 0xfff);
1900 print_AMD_l2_assoc(regs[1] >> 28);
1901
1902 printf("L2 4KB instruction TLB: %d entries",
1903 (regs[1] >> 16) & 0xfff);
1904 print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1905 } else {
1906 printf("L2 4KB unified TLB: %d entries",
1907 (regs[1] >> 16) & 0xfff);
1908 print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1909 }
1910 printf("L2 unified cache: %d kbytes", regs[2] >> 16);
1911 printf(", %d bytes/line", regs[2] & 0xff);
1912 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1913 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
1914 }
1915
1916 #ifdef __i386__
1917 if (((cpu_id & 0xf00) == 0x500)
1918 && (((cpu_id & 0x0f0) > 0x80)
1919 || (((cpu_id & 0x0f0) == 0x80)
1920 && (cpu_id & 0x00f) > 0x07))) {
1921 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1922 amd_whcr = rdmsr(0xc0000082);
1923 if (!(amd_whcr & (0x3ff << 22))) {
1924 printf("Write Allocate Disable\n");
1925 } else {
1926 printf("Write Allocate Enable Limit: %dM bytes\n",
1927 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1928 printf("Write Allocate 15-16M bytes: %s\n",
1929 (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1930 }
1931 } else if (((cpu_id & 0xf00) == 0x500)
1932 && ((cpu_id & 0x0f0) > 0x50)) {
1933 /* K6, K6-2(old core) */
1934 amd_whcr = rdmsr(0xc0000082);
1935 if (!(amd_whcr & (0x7f << 1))) {
1936 printf("Write Allocate Disable\n");
1937 } else {
1938 printf("Write Allocate Enable Limit: %dM bytes\n",
1939 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1940 printf("Write Allocate 15-16M bytes: %s\n",
1941 (amd_whcr & 0x0001) ? "Enable" : "Disable");
1942 printf("Hardware Write Allocate Control: %s\n",
1943 (amd_whcr & 0x0100) ? "Enable" : "Disable");
1944 }
1945 }
1946 #endif
1947 /*
1948 * Opteron Rev E shows a bug as in very rare occasions a read memory
1949 * barrier is not performed as expected if it is followed by a
1950 * non-atomic read-modify-write instruction.
1951 * As long as that bug pops up very rarely (intensive machine usage
1952 * on other operating systems generally generates one unexplainable
1953 * crash any 2 months) and as long as a model specific fix would be
1954 * impractical at this stage, print out a warning string if the broken
1955 * model and family are identified.
1956 */
1957 if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
1958 CPUID_TO_MODEL(cpu_id) <= 0x3f)
1959 printf("WARNING: This architecture revision has known SMP "
1960 "hardware bugs which may cause random instability\n");
1961 }
1962
1963 static void
print_INTEL_info(void)1964 print_INTEL_info(void)
1965 {
1966 u_int regs[4];
1967 u_int rounds, regnum;
1968 u_int nwaycode, nway;
1969
1970 if (cpu_high >= 2) {
1971 rounds = 0;
1972 do {
1973 do_cpuid(0x2, regs);
1974 if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1975 break; /* we have a buggy CPU */
1976
1977 for (regnum = 0; regnum <= 3; ++regnum) {
1978 if (regs[regnum] & (1<<31))
1979 continue;
1980 if (regnum != 0)
1981 print_INTEL_TLB(regs[regnum] & 0xff);
1982 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
1983 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
1984 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
1985 }
1986 } while (--rounds > 0);
1987 }
1988
1989 if (cpu_exthigh >= 0x80000006) {
1990 do_cpuid(0x80000006, regs);
1991 nwaycode = (regs[2] >> 12) & 0x0f;
1992 if (nwaycode >= 0x02 && nwaycode <= 0x08)
1993 nway = 1 << (nwaycode / 2);
1994 else
1995 nway = 0;
1996 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n",
1997 (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
1998 }
1999 }
2000
2001 static void
print_INTEL_TLB(u_int data)2002 print_INTEL_TLB(u_int data)
2003 {
2004 switch (data) {
2005 case 0x0:
2006 case 0x40:
2007 default:
2008 break;
2009 case 0x1:
2010 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n");
2011 break;
2012 case 0x2:
2013 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n");
2014 break;
2015 case 0x3:
2016 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n");
2017 break;
2018 case 0x4:
2019 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n");
2020 break;
2021 case 0x6:
2022 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n");
2023 break;
2024 case 0x8:
2025 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n");
2026 break;
2027 case 0x9:
2028 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n");
2029 break;
2030 case 0xa:
2031 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n");
2032 break;
2033 case 0xb:
2034 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n");
2035 break;
2036 case 0xc:
2037 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n");
2038 break;
2039 case 0xd:
2040 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size");
2041 break;
2042 case 0xe:
2043 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n");
2044 break;
2045 case 0x1d:
2046 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n");
2047 break;
2048 case 0x21:
2049 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n");
2050 break;
2051 case 0x22:
2052 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2053 break;
2054 case 0x23:
2055 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2056 break;
2057 case 0x24:
2058 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n");
2059 break;
2060 case 0x25:
2061 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2062 break;
2063 case 0x29:
2064 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2065 break;
2066 case 0x2c:
2067 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n");
2068 break;
2069 case 0x30:
2070 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n");
2071 break;
2072 case 0x39: /* De-listed in SDM rev. 54 */
2073 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2074 break;
2075 case 0x3b: /* De-listed in SDM rev. 54 */
2076 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n");
2077 break;
2078 case 0x3c: /* De-listed in SDM rev. 54 */
2079 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2080 break;
2081 case 0x41:
2082 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n");
2083 break;
2084 case 0x42:
2085 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n");
2086 break;
2087 case 0x43:
2088 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n");
2089 break;
2090 case 0x44:
2091 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n");
2092 break;
2093 case 0x45:
2094 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n");
2095 break;
2096 case 0x46:
2097 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n");
2098 break;
2099 case 0x47:
2100 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n");
2101 break;
2102 case 0x48:
2103 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n");
2104 break;
2105 case 0x49:
2106 if (CPUID_TO_FAMILY(cpu_id) == 0xf &&
2107 CPUID_TO_MODEL(cpu_id) == 0x6)
2108 printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n");
2109 else
2110 printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size");
2111 break;
2112 case 0x4a:
2113 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n");
2114 break;
2115 case 0x4b:
2116 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n");
2117 break;
2118 case 0x4c:
2119 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n");
2120 break;
2121 case 0x4d:
2122 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n");
2123 break;
2124 case 0x4e:
2125 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n");
2126 break;
2127 case 0x4f:
2128 printf("Instruction TLB: 4 KByte pages, 32 entries\n");
2129 break;
2130 case 0x50:
2131 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n");
2132 break;
2133 case 0x51:
2134 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n");
2135 break;
2136 case 0x52:
2137 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n");
2138 break;
2139 case 0x55:
2140 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n");
2141 break;
2142 case 0x56:
2143 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n");
2144 break;
2145 case 0x57:
2146 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n");
2147 break;
2148 case 0x59:
2149 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n");
2150 break;
2151 case 0x5a:
2152 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n");
2153 break;
2154 case 0x5b:
2155 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n");
2156 break;
2157 case 0x5c:
2158 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n");
2159 break;
2160 case 0x5d:
2161 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n");
2162 break;
2163 case 0x60:
2164 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2165 break;
2166 case 0x61:
2167 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n");
2168 break;
2169 case 0x63:
2170 printf("Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries\n");
2171 break;
2172 case 0x64:
2173 printf("Data TLB: 4 KBytes pages, 4-way set associative, 512 entries\n");
2174 break;
2175 case 0x66:
2176 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2177 break;
2178 case 0x67:
2179 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2180 break;
2181 case 0x68:
2182 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n");
2183 break;
2184 case 0x6a:
2185 printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n");
2186 break;
2187 case 0x6b:
2188 printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n");
2189 break;
2190 case 0x6c:
2191 printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n");
2192 break;
2193 case 0x6d:
2194 printf("DTLB: 1 GByte pages, fully associative, 16 entries\n");
2195 break;
2196 case 0x70:
2197 printf("Trace cache: 12K-uops, 8-way set associative\n");
2198 break;
2199 case 0x71:
2200 printf("Trace cache: 16K-uops, 8-way set associative\n");
2201 break;
2202 case 0x72:
2203 printf("Trace cache: 32K-uops, 8-way set associative\n");
2204 break;
2205 case 0x76:
2206 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n");
2207 break;
2208 case 0x78:
2209 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n");
2210 break;
2211 case 0x79:
2212 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2213 break;
2214 case 0x7a:
2215 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2216 break;
2217 case 0x7b:
2218 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2219 break;
2220 case 0x7c:
2221 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2222 break;
2223 case 0x7d:
2224 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n");
2225 break;
2226 case 0x7f:
2227 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n");
2228 break;
2229 case 0x80:
2230 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n");
2231 break;
2232 case 0x82:
2233 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n");
2234 break;
2235 case 0x83:
2236 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n");
2237 break;
2238 case 0x84:
2239 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n");
2240 break;
2241 case 0x85:
2242 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n");
2243 break;
2244 case 0x86:
2245 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n");
2246 break;
2247 case 0x87:
2248 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n");
2249 break;
2250 case 0xa0:
2251 printf("DTLB: 4k pages, fully associative, 32 entries\n");
2252 break;
2253 case 0xb0:
2254 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2255 break;
2256 case 0xb1:
2257 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n");
2258 break;
2259 case 0xb2:
2260 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n");
2261 break;
2262 case 0xb3:
2263 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2264 break;
2265 case 0xb4:
2266 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n");
2267 break;
2268 case 0xb5:
2269 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n");
2270 break;
2271 case 0xb6:
2272 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n");
2273 break;
2274 case 0xba:
2275 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n");
2276 break;
2277 case 0xc0:
2278 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n");
2279 break;
2280 case 0xc1:
2281 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n");
2282 break;
2283 case 0xc2:
2284 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n");
2285 break;
2286 case 0xc3:
2287 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n");
2288 break;
2289 case 0xc4:
2290 printf("DTLB: 2M/4M Byte pages, 4-way associative, 32 entries\n");
2291 break;
2292 case 0xca:
2293 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n");
2294 break;
2295 case 0xd0:
2296 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n");
2297 break;
2298 case 0xd1:
2299 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n");
2300 break;
2301 case 0xd2:
2302 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n");
2303 break;
2304 case 0xd6:
2305 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n");
2306 break;
2307 case 0xd7:
2308 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n");
2309 break;
2310 case 0xd8:
2311 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n");
2312 break;
2313 case 0xdc:
2314 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n");
2315 break;
2316 case 0xdd:
2317 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n");
2318 break;
2319 case 0xde:
2320 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n");
2321 break;
2322 case 0xe2:
2323 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n");
2324 break;
2325 case 0xe3:
2326 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n");
2327 break;
2328 case 0xe4:
2329 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n");
2330 break;
2331 case 0xea:
2332 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n");
2333 break;
2334 case 0xeb:
2335 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n");
2336 break;
2337 case 0xec:
2338 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n");
2339 break;
2340 case 0xf0:
2341 printf("64-Byte prefetching\n");
2342 break;
2343 case 0xf1:
2344 printf("128-Byte prefetching\n");
2345 break;
2346 }
2347 }
2348
2349 static void
print_svm_info(void)2350 print_svm_info(void)
2351 {
2352 u_int features, regs[4];
2353 uint64_t msr;
2354 int comma;
2355
2356 printf("\n SVM: ");
2357 do_cpuid(0x8000000A, regs);
2358 features = regs[3];
2359
2360 msr = rdmsr(MSR_VM_CR);
2361 if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS)
2362 printf("(disabled in BIOS) ");
2363
2364 if (!bootverbose) {
2365 comma = 0;
2366 if (features & (1 << 0)) {
2367 printf("%sNP", comma ? "," : "");
2368 comma = 1;
2369 }
2370 if (features & (1 << 3)) {
2371 printf("%sNRIP", comma ? "," : "");
2372 comma = 1;
2373 }
2374 if (features & (1 << 5)) {
2375 printf("%sVClean", comma ? "," : "");
2376 comma = 1;
2377 }
2378 if (features & (1 << 6)) {
2379 printf("%sAFlush", comma ? "," : "");
2380 comma = 1;
2381 }
2382 if (features & (1 << 7)) {
2383 printf("%sDAssist", comma ? "," : "");
2384 comma = 1;
2385 }
2386 printf("%sNAsids=%d", comma ? "," : "", regs[1]);
2387 return;
2388 }
2389
2390 printf("Features=0x%b", features,
2391 "\020"
2392 "\001NP" /* Nested paging */
2393 "\002LbrVirt" /* LBR virtualization */
2394 "\003SVML" /* SVM lock */
2395 "\004NRIPS" /* NRIP save */
2396 "\005TscRateMsr" /* MSR based TSC rate control */
2397 "\006VmcbClean" /* VMCB clean bits */
2398 "\007FlushByAsid" /* Flush by ASID */
2399 "\010DecodeAssist" /* Decode assist */
2400 "\011<b8>"
2401 "\012<b9>"
2402 "\013PauseFilter" /* PAUSE intercept filter */
2403 "\014EncryptedMcodePatch"
2404 "\015PauseFilterThreshold" /* PAUSE filter threshold */
2405 "\016AVIC" /* virtual interrupt controller */
2406 "\017<b14>"
2407 "\020V_VMSAVE_VMLOAD"
2408 "\021vGIF"
2409 "\022GMET" /* Guest Mode Execute Trap */
2410 "\023<b18>"
2411 "\024<b19>"
2412 "\025GuesSpecCtl" /* Guest Spec_ctl */
2413 "\026<b21>"
2414 "\027<b22>"
2415 "\030<b23>"
2416 "\031<b24>"
2417 "\032<b25>"
2418 "\033<b26>"
2419 "\034<b27>"
2420 "\035<b28>"
2421 "\036<b29>"
2422 "\037<b30>"
2423 "\040<b31>"
2424 );
2425 printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]);
2426 }
2427
2428 #ifdef __i386__
2429 static void
print_transmeta_info(void)2430 print_transmeta_info(void)
2431 {
2432 u_int regs[4], nreg = 0;
2433
2434 do_cpuid(0x80860000, regs);
2435 nreg = regs[0];
2436 if (nreg >= 0x80860001) {
2437 do_cpuid(0x80860001, regs);
2438 printf(" Processor revision %u.%u.%u.%u\n",
2439 (regs[1] >> 24) & 0xff,
2440 (regs[1] >> 16) & 0xff,
2441 (regs[1] >> 8) & 0xff,
2442 regs[1] & 0xff);
2443 }
2444 if (nreg >= 0x80860002) {
2445 do_cpuid(0x80860002, regs);
2446 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n",
2447 (regs[1] >> 24) & 0xff,
2448 (regs[1] >> 16) & 0xff,
2449 (regs[1] >> 8) & 0xff,
2450 regs[1] & 0xff,
2451 regs[2]);
2452 }
2453 if (nreg >= 0x80860006) {
2454 char info[65];
2455 do_cpuid(0x80860003, (u_int*) &info[0]);
2456 do_cpuid(0x80860004, (u_int*) &info[16]);
2457 do_cpuid(0x80860005, (u_int*) &info[32]);
2458 do_cpuid(0x80860006, (u_int*) &info[48]);
2459 info[64] = 0;
2460 printf(" %s\n", info);
2461 }
2462 }
2463 #endif
2464
2465 static void
print_via_padlock_info(void)2466 print_via_padlock_info(void)
2467 {
2468 u_int regs[4];
2469
2470 do_cpuid(0xc0000001, regs);
2471 printf("\n VIA Padlock Features=0x%b", regs[3],
2472 "\020"
2473 "\003RNG" /* RNG */
2474 "\007AES" /* ACE */
2475 "\011AES-CTR" /* ACE2 */
2476 "\013SHA1,SHA256" /* PHE */
2477 "\015RSA" /* PMM */
2478 );
2479 }
2480
2481 static uint32_t
vmx_settable(uint64_t basic,int msr,int true_msr)2482 vmx_settable(uint64_t basic, int msr, int true_msr)
2483 {
2484 uint64_t val;
2485
2486 if (basic & (1ULL << 55))
2487 val = rdmsr(true_msr);
2488 else
2489 val = rdmsr(msr);
2490
2491 /* Just report the controls that can be set to 1. */
2492 return (val >> 32);
2493 }
2494
2495 static void
print_vmx_info(void)2496 print_vmx_info(void)
2497 {
2498 uint64_t basic, msr;
2499 uint32_t entry, exit, mask, pin, proc, proc2;
2500 int comma;
2501
2502 printf("\n VT-x: ");
2503 msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
2504 if (!(msr & IA32_FEATURE_CONTROL_VMX_EN))
2505 printf("(disabled in BIOS) ");
2506 basic = rdmsr(MSR_VMX_BASIC);
2507 pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS,
2508 MSR_VMX_TRUE_PINBASED_CTLS);
2509 proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS,
2510 MSR_VMX_TRUE_PROCBASED_CTLS);
2511 if (proc & PROCBASED_SECONDARY_CONTROLS)
2512 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2,
2513 MSR_VMX_PROCBASED_CTLS2);
2514 else
2515 proc2 = 0;
2516 exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS);
2517 entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS);
2518
2519 if (!bootverbose) {
2520 comma = 0;
2521 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT &&
2522 entry & VM_ENTRY_LOAD_PAT) {
2523 printf("%sPAT", comma ? "," : "");
2524 comma = 1;
2525 }
2526 if (proc & PROCBASED_HLT_EXITING) {
2527 printf("%sHLT", comma ? "," : "");
2528 comma = 1;
2529 }
2530 if (proc & PROCBASED_MTF) {
2531 printf("%sMTF", comma ? "," : "");
2532 comma = 1;
2533 }
2534 if (proc & PROCBASED_PAUSE_EXITING) {
2535 printf("%sPAUSE", comma ? "," : "");
2536 comma = 1;
2537 }
2538 if (proc2 & PROCBASED2_ENABLE_EPT) {
2539 printf("%sEPT", comma ? "," : "");
2540 comma = 1;
2541 }
2542 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) {
2543 printf("%sUG", comma ? "," : "");
2544 comma = 1;
2545 }
2546 if (proc2 & PROCBASED2_ENABLE_VPID) {
2547 printf("%sVPID", comma ? "," : "");
2548 comma = 1;
2549 }
2550 if (proc & PROCBASED_USE_TPR_SHADOW &&
2551 proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES &&
2552 proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE &&
2553 proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION &&
2554 proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) {
2555 printf("%sVID", comma ? "," : "");
2556 comma = 1;
2557 if (pin & PINBASED_POSTED_INTERRUPT)
2558 printf(",PostIntr");
2559 }
2560 return;
2561 }
2562
2563 mask = basic >> 32;
2564 printf("Basic Features=0x%b", mask,
2565 "\020"
2566 "\02132PA" /* 32-bit physical addresses */
2567 "\022SMM" /* SMM dual-monitor */
2568 "\027INS/OUTS" /* VM-exit info for INS and OUTS */
2569 "\030TRUE" /* TRUE_CTLS MSRs */
2570 );
2571 printf("\n Pin-Based Controls=0x%b", pin,
2572 "\020"
2573 "\001ExtINT" /* External-interrupt exiting */
2574 "\004NMI" /* NMI exiting */
2575 "\006VNMI" /* Virtual NMIs */
2576 "\007PreTmr" /* Activate VMX-preemption timer */
2577 "\010PostIntr" /* Process posted interrupts */
2578 );
2579 printf("\n Primary Processor Controls=0x%b", proc,
2580 "\020"
2581 "\003INTWIN" /* Interrupt-window exiting */
2582 "\004TSCOff" /* Use TSC offsetting */
2583 "\010HLT" /* HLT exiting */
2584 "\012INVLPG" /* INVLPG exiting */
2585 "\013MWAIT" /* MWAIT exiting */
2586 "\014RDPMC" /* RDPMC exiting */
2587 "\015RDTSC" /* RDTSC exiting */
2588 "\020CR3-LD" /* CR3-load exiting */
2589 "\021CR3-ST" /* CR3-store exiting */
2590 "\024CR8-LD" /* CR8-load exiting */
2591 "\025CR8-ST" /* CR8-store exiting */
2592 "\026TPR" /* Use TPR shadow */
2593 "\027NMIWIN" /* NMI-window exiting */
2594 "\030MOV-DR" /* MOV-DR exiting */
2595 "\031IO" /* Unconditional I/O exiting */
2596 "\032IOmap" /* Use I/O bitmaps */
2597 "\034MTF" /* Monitor trap flag */
2598 "\035MSRmap" /* Use MSR bitmaps */
2599 "\036MONITOR" /* MONITOR exiting */
2600 "\037PAUSE" /* PAUSE exiting */
2601 );
2602 if (proc & PROCBASED_SECONDARY_CONTROLS)
2603 printf("\n Secondary Processor Controls=0x%b", proc2,
2604 "\020"
2605 "\001APIC" /* Virtualize APIC accesses */
2606 "\002EPT" /* Enable EPT */
2607 "\003DT" /* Descriptor-table exiting */
2608 "\004RDTSCP" /* Enable RDTSCP */
2609 "\005x2APIC" /* Virtualize x2APIC mode */
2610 "\006VPID" /* Enable VPID */
2611 "\007WBINVD" /* WBINVD exiting */
2612 "\010UG" /* Unrestricted guest */
2613 "\011APIC-reg" /* APIC-register virtualization */
2614 "\012VID" /* Virtual-interrupt delivery */
2615 "\013PAUSE-loop" /* PAUSE-loop exiting */
2616 "\014RDRAND" /* RDRAND exiting */
2617 "\015INVPCID" /* Enable INVPCID */
2618 "\016VMFUNC" /* Enable VM functions */
2619 "\017VMCS" /* VMCS shadowing */
2620 "\020EPT#VE" /* EPT-violation #VE */
2621 "\021XSAVES" /* Enable XSAVES/XRSTORS */
2622 );
2623 printf("\n Exit Controls=0x%b", mask,
2624 "\020"
2625 "\003DR" /* Save debug controls */
2626 /* Ignore Host address-space size */
2627 "\015PERF" /* Load MSR_PERF_GLOBAL_CTRL */
2628 "\020AckInt" /* Acknowledge interrupt on exit */
2629 "\023PAT-SV" /* Save MSR_PAT */
2630 "\024PAT-LD" /* Load MSR_PAT */
2631 "\025EFER-SV" /* Save MSR_EFER */
2632 "\026EFER-LD" /* Load MSR_EFER */
2633 "\027PTMR-SV" /* Save VMX-preemption timer value */
2634 );
2635 printf("\n Entry Controls=0x%b", mask,
2636 "\020"
2637 "\003DR" /* Save debug controls */
2638 /* Ignore IA-32e mode guest */
2639 /* Ignore Entry to SMM */
2640 /* Ignore Deactivate dual-monitor treatment */
2641 "\016PERF" /* Load MSR_PERF_GLOBAL_CTRL */
2642 "\017PAT" /* Load MSR_PAT */
2643 "\020EFER" /* Load MSR_EFER */
2644 );
2645 if (proc & PROCBASED_SECONDARY_CONTROLS &&
2646 (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) {
2647 msr = rdmsr(MSR_VMX_EPT_VPID_CAP);
2648 mask = msr;
2649 printf("\n EPT Features=0x%b", mask,
2650 "\020"
2651 "\001XO" /* Execute-only translations */
2652 "\007PW4" /* Page-walk length of 4 */
2653 "\011UC" /* EPT paging-structure mem can be UC */
2654 "\017WB" /* EPT paging-structure mem can be WB */
2655 "\0212M" /* EPT PDE can map a 2-Mbyte page */
2656 "\0221G" /* EPT PDPTE can map a 1-Gbyte page */
2657 "\025INVEPT" /* INVEPT is supported */
2658 "\026AD" /* Accessed and dirty flags for EPT */
2659 "\032single" /* INVEPT single-context type */
2660 "\033all" /* INVEPT all-context type */
2661 );
2662 mask = msr >> 32;
2663 printf("\n VPID Features=0x%b", mask,
2664 "\020"
2665 "\001INVVPID" /* INVVPID is supported */
2666 "\011individual" /* INVVPID individual-address type */
2667 "\012single" /* INVVPID single-context type */
2668 "\013all" /* INVVPID all-context type */
2669 /* INVVPID single-context-retaining-globals type */
2670 "\014single-globals"
2671 );
2672 }
2673 }
2674
2675 static void
print_hypervisor_info(void)2676 print_hypervisor_info(void)
2677 {
2678
2679 if (*hv_vendor != '\0')
2680 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor);
2681 }
2682
2683 /*
2684 * Returns the maximum physical address that can be used with the
2685 * current system.
2686 */
2687 vm_paddr_t
cpu_getmaxphyaddr(void)2688 cpu_getmaxphyaddr(void)
2689 {
2690
2691 #if defined(__i386__)
2692 if (!pae_mode)
2693 return (0xffffffff);
2694 #endif
2695 return ((1ULL << cpu_maxphyaddr) - 1);
2696 }
2697