1 /*-
2 * Copyright (c) 2003 Peter Wemm.
3 * Copyright (c) 1992 Terrence R. Lambert.
4 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to Berkeley by
8 * William Jolitz.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the University of
21 * California, Berkeley and its contributors.
22 * 4. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * SUCH DAMAGE.
37 *
38 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
39 */
40
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD$");
43
44 #include "opt_atpic.h"
45 #include "opt_compat.h"
46 #include "opt_cpu.h"
47 #include "opt_ddb.h"
48 #include "opt_inet.h"
49 #include "opt_isa.h"
50 #include "opt_kstack_pages.h"
51 #include "opt_maxmem.h"
52 #include "opt_mp_watchdog.h"
53 #include "opt_perfmon.h"
54 #include "opt_platform.h"
55 #ifdef __i386__
56 #include "opt_npx.h"
57 #include "opt_apic.h"
58 #include "opt_xbox.h"
59 #endif
60
61 #include <sys/param.h>
62 #include <sys/proc.h>
63 #include <sys/systm.h>
64 #include <sys/bus.h>
65 #include <sys/cpu.h>
66 #include <sys/kdb.h>
67 #include <sys/kernel.h>
68 #include <sys/ktr.h>
69 #include <sys/lock.h>
70 #include <sys/malloc.h>
71 #include <sys/mutex.h>
72 #include <sys/pcpu.h>
73 #include <sys/rwlock.h>
74 #include <sys/sched.h>
75 #ifdef SMP
76 #include <sys/smp.h>
77 #endif
78 #include <sys/sysctl.h>
79
80 #include <machine/clock.h>
81 #include <machine/cpu.h>
82 #include <machine/cputypes.h>
83 #include <machine/specialreg.h>
84 #include <machine/md_var.h>
85 #include <machine/mp_watchdog.h>
86 #ifdef PERFMON
87 #include <machine/perfmon.h>
88 #endif
89 #include <machine/tss.h>
90 #ifdef SMP
91 #include <machine/smp.h>
92 #endif
93 #include <x86/acpica_machdep.h>
94
95 #include <vm/vm.h>
96 #include <vm/vm_extern.h>
97 #include <vm/vm_kern.h>
98 #include <vm/vm_page.h>
99 #include <vm/vm_map.h>
100 #include <vm/vm_object.h>
101 #include <vm/vm_pager.h>
102 #include <vm/vm_param.h>
103
104 #define STATE_RUNNING 0x0
105 #define STATE_MWAIT 0x1
106 #define STATE_SLEEPING 0x2
107
108 /*
109 * Machine dependent boot() routine
110 *
111 * I haven't seen anything to put here yet
112 * Possibly some stuff might be grafted back here from boot()
113 */
114 void
cpu_boot(int howto)115 cpu_boot(int howto)
116 {
117 }
118
119 /*
120 * Flush the D-cache for non-DMA I/O so that the I-cache can
121 * be made coherent later.
122 */
123 void
cpu_flush_dcache(void * ptr,size_t len)124 cpu_flush_dcache(void *ptr, size_t len)
125 {
126 /* Not applicable */
127 }
128
129 void
acpi_cpu_c1(void)130 acpi_cpu_c1(void)
131 {
132
133 __asm __volatile("sti; hlt");
134 }
135
136 void
acpi_cpu_idle_mwait(uint32_t mwait_hint)137 acpi_cpu_idle_mwait(uint32_t mwait_hint)
138 {
139 int *state;
140
141 /*
142 * XXXKIB. Software coordination mode should be supported,
143 * but all Intel CPUs provide hardware coordination.
144 */
145
146 state = (int *)PCPU_PTR(monitorbuf);
147 KASSERT(*state == STATE_SLEEPING,
148 ("cpu_mwait_cx: wrong monitorbuf state"));
149 *state = STATE_MWAIT;
150 cpu_monitor(state, 0, 0);
151 if (*state == STATE_MWAIT)
152 cpu_mwait(MWAIT_INTRBREAK, mwait_hint);
153
154 /*
155 * We should exit on any event that interrupts mwait, because
156 * that event might be a wanted interrupt.
157 */
158 *state = STATE_RUNNING;
159 }
160
161 /* Get current clock frequency for the given cpu id. */
162 int
cpu_est_clockrate(int cpu_id,uint64_t * rate)163 cpu_est_clockrate(int cpu_id, uint64_t *rate)
164 {
165 uint64_t tsc1, tsc2;
166 uint64_t acnt, mcnt, perf;
167 register_t reg;
168
169 if (pcpu_find(cpu_id) == NULL || rate == NULL)
170 return (EINVAL);
171 #ifdef __i386__
172 if ((cpu_feature & CPUID_TSC) == 0)
173 return (EOPNOTSUPP);
174 #endif
175
176 /*
177 * If TSC is P-state invariant and APERF/MPERF MSRs do not exist,
178 * DELAY(9) based logic fails.
179 */
180 if (tsc_is_invariant && !tsc_perf_stat)
181 return (EOPNOTSUPP);
182
183 #ifdef SMP
184 if (smp_cpus > 1) {
185 /* Schedule ourselves on the indicated cpu. */
186 thread_lock(curthread);
187 sched_bind(curthread, cpu_id);
188 thread_unlock(curthread);
189 }
190 #endif
191
192 /* Calibrate by measuring a short delay. */
193 reg = intr_disable();
194 if (tsc_is_invariant) {
195 wrmsr(MSR_MPERF, 0);
196 wrmsr(MSR_APERF, 0);
197 tsc1 = rdtsc();
198 DELAY(1000);
199 mcnt = rdmsr(MSR_MPERF);
200 acnt = rdmsr(MSR_APERF);
201 tsc2 = rdtsc();
202 intr_restore(reg);
203 perf = 1000 * acnt / mcnt;
204 *rate = (tsc2 - tsc1) * perf;
205 } else {
206 tsc1 = rdtsc();
207 DELAY(1000);
208 tsc2 = rdtsc();
209 intr_restore(reg);
210 *rate = (tsc2 - tsc1) * 1000;
211 }
212
213 #ifdef SMP
214 if (smp_cpus > 1) {
215 thread_lock(curthread);
216 sched_unbind(curthread);
217 thread_unlock(curthread);
218 }
219 #endif
220
221 return (0);
222 }
223
224 /*
225 * Shutdown the CPU as much as possible
226 */
227 void
cpu_halt(void)228 cpu_halt(void)
229 {
230 for (;;)
231 halt();
232 }
233
234 bool
cpu_mwait_usable(void)235 cpu_mwait_usable(void)
236 {
237
238 return ((cpu_feature2 & CPUID2_MON) != 0 && ((cpu_mon_mwait_flags &
239 (CPUID5_MON_MWAIT_EXT | CPUID5_MWAIT_INTRBREAK)) ==
240 (CPUID5_MON_MWAIT_EXT | CPUID5_MWAIT_INTRBREAK)));
241 }
242
243 void (*cpu_idle_hook)(sbintime_t) = NULL; /* ACPI idle hook. */
244 static int cpu_ident_amdc1e = 0; /* AMD C1E supported. */
245 static int idle_mwait = 1; /* Use MONITOR/MWAIT for short idle. */
246 SYSCTL_INT(_machdep, OID_AUTO, idle_mwait, CTLFLAG_RWTUN, &idle_mwait,
247 0, "Use MONITOR/MWAIT for short idle");
248
249 #ifndef PC98
250 static void
cpu_idle_acpi(sbintime_t sbt)251 cpu_idle_acpi(sbintime_t sbt)
252 {
253 int *state;
254
255 state = (int *)PCPU_PTR(monitorbuf);
256 *state = STATE_SLEEPING;
257
258 /* See comments in cpu_idle_hlt(). */
259 disable_intr();
260 if (sched_runnable())
261 enable_intr();
262 else if (cpu_idle_hook)
263 cpu_idle_hook(sbt);
264 else
265 acpi_cpu_c1();
266 *state = STATE_RUNNING;
267 }
268 #endif /* !PC98 */
269
270 static void
cpu_idle_hlt(sbintime_t sbt)271 cpu_idle_hlt(sbintime_t sbt)
272 {
273 int *state;
274
275 state = (int *)PCPU_PTR(monitorbuf);
276 *state = STATE_SLEEPING;
277
278 /*
279 * Since we may be in a critical section from cpu_idle(), if
280 * an interrupt fires during that critical section we may have
281 * a pending preemption. If the CPU halts, then that thread
282 * may not execute until a later interrupt awakens the CPU.
283 * To handle this race, check for a runnable thread after
284 * disabling interrupts and immediately return if one is
285 * found. Also, we must absolutely guarentee that hlt is
286 * the next instruction after sti. This ensures that any
287 * interrupt that fires after the call to disable_intr() will
288 * immediately awaken the CPU from hlt. Finally, please note
289 * that on x86 this works fine because of interrupts enabled only
290 * after the instruction following sti takes place, while IF is set
291 * to 1 immediately, allowing hlt instruction to acknowledge the
292 * interrupt.
293 */
294 disable_intr();
295 if (sched_runnable())
296 enable_intr();
297 else
298 acpi_cpu_c1();
299 *state = STATE_RUNNING;
300 }
301
302 static void
cpu_idle_mwait(sbintime_t sbt)303 cpu_idle_mwait(sbintime_t sbt)
304 {
305 int *state;
306
307 state = (int *)PCPU_PTR(monitorbuf);
308 *state = STATE_MWAIT;
309
310 /* See comments in cpu_idle_hlt(). */
311 disable_intr();
312 if (sched_runnable()) {
313 enable_intr();
314 *state = STATE_RUNNING;
315 return;
316 }
317 cpu_monitor(state, 0, 0);
318 if (*state == STATE_MWAIT)
319 __asm __volatile("sti; mwait" : : "a" (MWAIT_C1), "c" (0));
320 else
321 enable_intr();
322 *state = STATE_RUNNING;
323 }
324
325 static void
cpu_idle_spin(sbintime_t sbt)326 cpu_idle_spin(sbintime_t sbt)
327 {
328 int *state;
329 int i;
330
331 state = (int *)PCPU_PTR(monitorbuf);
332 *state = STATE_RUNNING;
333
334 /*
335 * The sched_runnable() call is racy but as long as there is
336 * a loop missing it one time will have just a little impact if any
337 * (and it is much better than missing the check at all).
338 */
339 for (i = 0; i < 1000; i++) {
340 if (sched_runnable())
341 return;
342 cpu_spinwait();
343 }
344 }
345
346 /*
347 * C1E renders the local APIC timer dead, so we disable it by
348 * reading the Interrupt Pending Message register and clearing
349 * both C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
350 *
351 * Reference:
352 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors"
353 * #32559 revision 3.00+
354 */
355 #define MSR_AMDK8_IPM 0xc0010055
356 #define AMDK8_SMIONCMPHALT (1ULL << 27)
357 #define AMDK8_C1EONCMPHALT (1ULL << 28)
358 #define AMDK8_CMPHALT (AMDK8_SMIONCMPHALT | AMDK8_C1EONCMPHALT)
359
360 void
cpu_probe_amdc1e(void)361 cpu_probe_amdc1e(void)
362 {
363
364 /*
365 * Detect the presence of C1E capability mostly on latest
366 * dual-cores (or future) k8 family.
367 */
368 if (cpu_vendor_id == CPU_VENDOR_AMD &&
369 (cpu_id & 0x00000f00) == 0x00000f00 &&
370 (cpu_id & 0x0fff0000) >= 0x00040000) {
371 cpu_ident_amdc1e = 1;
372 }
373 }
374
375 #if defined(__i386__) && defined(PC98)
376 void (*cpu_idle_fn)(sbintime_t) = cpu_idle_hlt;
377 #else
378 void (*cpu_idle_fn)(sbintime_t) = cpu_idle_acpi;
379 #endif
380
381 void
cpu_idle(int busy)382 cpu_idle(int busy)
383 {
384 uint64_t msr;
385 sbintime_t sbt = -1;
386
387 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d",
388 busy, curcpu);
389 #ifdef MP_WATCHDOG
390 ap_watchdog(PCPU_GET(cpuid));
391 #endif
392
393 /* If we are busy - try to use fast methods. */
394 if (busy) {
395 if ((cpu_feature2 & CPUID2_MON) && idle_mwait) {
396 cpu_idle_mwait(busy);
397 goto out;
398 }
399 }
400
401 /* If we have time - switch timers into idle mode. */
402 if (!busy) {
403 critical_enter();
404 sbt = cpu_idleclock();
405 }
406
407 /* Apply AMD APIC timer C1E workaround. */
408 if (cpu_ident_amdc1e && cpu_disable_c3_sleep) {
409 msr = rdmsr(MSR_AMDK8_IPM);
410 if (msr & AMDK8_CMPHALT)
411 wrmsr(MSR_AMDK8_IPM, msr & ~AMDK8_CMPHALT);
412 }
413
414 /* Call main idle method. */
415 cpu_idle_fn(sbt);
416
417 /* Switch timers back into active mode. */
418 if (!busy) {
419 cpu_activeclock();
420 critical_exit();
421 }
422 out:
423 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done",
424 busy, curcpu);
425 }
426
427 int
cpu_idle_wakeup(int cpu)428 cpu_idle_wakeup(int cpu)
429 {
430 struct pcpu *pcpu;
431 int *state;
432
433 pcpu = pcpu_find(cpu);
434 state = (int *)pcpu->pc_monitorbuf;
435 /*
436 * This doesn't need to be atomic since missing the race will
437 * simply result in unnecessary IPIs.
438 */
439 if (*state == STATE_SLEEPING)
440 return (0);
441 if (*state == STATE_MWAIT)
442 *state = STATE_RUNNING;
443 return (1);
444 }
445
446 /*
447 * Ordered by speed/power consumption.
448 */
449 struct {
450 void *id_fn;
451 char *id_name;
452 } idle_tbl[] = {
453 { cpu_idle_spin, "spin" },
454 { cpu_idle_mwait, "mwait" },
455 { cpu_idle_hlt, "hlt" },
456 #if !defined(__i386__) || !defined(PC98)
457 { cpu_idle_acpi, "acpi" },
458 #endif
459 { NULL, NULL }
460 };
461
462 static int
idle_sysctl_available(SYSCTL_HANDLER_ARGS)463 idle_sysctl_available(SYSCTL_HANDLER_ARGS)
464 {
465 char *avail, *p;
466 int error;
467 int i;
468
469 avail = malloc(256, M_TEMP, M_WAITOK);
470 p = avail;
471 for (i = 0; idle_tbl[i].id_name != NULL; i++) {
472 if (strstr(idle_tbl[i].id_name, "mwait") &&
473 (cpu_feature2 & CPUID2_MON) == 0)
474 continue;
475 #if !defined(__i386__) || !defined(PC98)
476 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 &&
477 cpu_idle_hook == NULL)
478 continue;
479 #endif
480 p += sprintf(p, "%s%s", p != avail ? ", " : "",
481 idle_tbl[i].id_name);
482 }
483 error = sysctl_handle_string(oidp, avail, 0, req);
484 free(avail, M_TEMP);
485 return (error);
486 }
487
488 SYSCTL_PROC(_machdep, OID_AUTO, idle_available, CTLTYPE_STRING | CTLFLAG_RD,
489 0, 0, idle_sysctl_available, "A", "list of available idle functions");
490
491 static int
idle_sysctl(SYSCTL_HANDLER_ARGS)492 idle_sysctl(SYSCTL_HANDLER_ARGS)
493 {
494 char buf[16];
495 int error;
496 char *p;
497 int i;
498
499 p = "unknown";
500 for (i = 0; idle_tbl[i].id_name != NULL; i++) {
501 if (idle_tbl[i].id_fn == cpu_idle_fn) {
502 p = idle_tbl[i].id_name;
503 break;
504 }
505 }
506 strncpy(buf, p, sizeof(buf));
507 error = sysctl_handle_string(oidp, buf, sizeof(buf), req);
508 if (error != 0 || req->newptr == NULL)
509 return (error);
510 for (i = 0; idle_tbl[i].id_name != NULL; i++) {
511 if (strstr(idle_tbl[i].id_name, "mwait") &&
512 (cpu_feature2 & CPUID2_MON) == 0)
513 continue;
514 #if !defined(__i386__) || !defined(PC98)
515 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 &&
516 cpu_idle_hook == NULL)
517 continue;
518 #endif
519 if (strcmp(idle_tbl[i].id_name, buf))
520 continue;
521 cpu_idle_fn = idle_tbl[i].id_fn;
522 return (0);
523 }
524 return (EINVAL);
525 }
526
527 SYSCTL_PROC(_machdep, OID_AUTO, idle, CTLTYPE_STRING | CTLFLAG_RW, 0, 0,
528 idle_sysctl, "A", "currently selected idle function");
529