1 /*-
2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4 * Copyright (c) 1997 KATO Takenori.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to Berkeley by
8 * William Jolitz.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the University of
21 * California, Berkeley and its contributors.
22 * 4. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * SUCH DAMAGE.
37 *
38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
39 */
40
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD$");
43
44 #include "opt_cpu.h"
45
46 #include <sys/param.h>
47 #include <sys/bus.h>
48 #include <sys/cpu.h>
49 #include <sys/eventhandler.h>
50 #include <sys/limits.h>
51 #include <sys/systm.h>
52 #include <sys/kernel.h>
53 #include <sys/sysctl.h>
54 #include <sys/power.h>
55
56 #include <machine/asmacros.h>
57 #include <machine/clock.h>
58 #include <machine/cputypes.h>
59 #include <machine/frame.h>
60 #include <machine/intr_machdep.h>
61 #include <machine/md_var.h>
62 #include <machine/segments.h>
63 #include <machine/specialreg.h>
64
65 #include <amd64/vmm/intel/vmx_controls.h>
66 #include <x86/isa/icu.h>
67 #include <x86/vmware.h>
68
69 #ifdef __i386__
70 #if !defined(CPU_DISABLE_SSE) && defined(I686_CPU)
71 #define CPU_ENABLE_SSE
72 #endif
73
74 #define IDENTBLUE_CYRIX486 0
75 #define IDENTBLUE_IBMCPU 1
76 #define IDENTBLUE_CYRIXM2 2
77
78 static void identifycyrix(void);
79 static void print_transmeta_info(void);
80 #endif
81 static u_int find_cpu_vendor_id(void);
82 static void print_AMD_info(void);
83 static void print_INTEL_info(void);
84 static void print_INTEL_TLB(u_int data);
85 static void print_hypervisor_info(void);
86 static void print_svm_info(void);
87 static void print_via_padlock_info(void);
88 static void print_vmx_info(void);
89
90 int cpu; /* Are we 386, 386sx, 486, etc? */
91 int cpu_class;
92 u_int cpu_feature; /* Feature flags */
93 u_int cpu_feature2; /* Feature flags */
94 u_int amd_feature; /* AMD feature flags */
95 u_int amd_feature2; /* AMD feature flags */
96 u_int amd_pminfo; /* AMD advanced power management info */
97 u_int via_feature_rng; /* VIA RNG features */
98 u_int via_feature_xcrypt; /* VIA ACE features */
99 u_int cpu_high; /* Highest arg to CPUID */
100 u_int cpu_exthigh; /* Highest arg to extended CPUID */
101 u_int cpu_id; /* Stepping ID */
102 u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */
103 u_int cpu_procinfo2; /* Multicore info */
104 char cpu_vendor[20]; /* CPU Origin code */
105 u_int cpu_vendor_id; /* CPU vendor ID */
106 #if defined(__amd64__) || defined(CPU_ENABLE_SSE)
107 u_int cpu_fxsr; /* SSE enabled */
108 u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */
109 #endif
110 u_int cpu_clflush_line_size = 32;
111 u_int cpu_stdext_feature;
112 u_int cpu_stdext_feature2;
113 u_int cpu_max_ext_state_size;
114 u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */
115 u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */
116 u_int cpu_mon_max_size; /* MONITOR minimum range size, bytes */
117 u_int cpu_maxphyaddr; /* Max phys addr width in bits */
118 char machine[] = MACHINE;
119
120 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
121 &via_feature_rng, 0,
122 "VIA RNG feature available in CPU");
123 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
124 &via_feature_xcrypt, 0,
125 "VIA xcrypt feature available in CPU");
126
127 #ifdef __amd64__
128 #ifdef SCTL_MASK32
129 extern int adaptive_machine_arch;
130 #endif
131
132 static int
sysctl_hw_machine(SYSCTL_HANDLER_ARGS)133 sysctl_hw_machine(SYSCTL_HANDLER_ARGS)
134 {
135 #ifdef SCTL_MASK32
136 static const char machine32[] = "i386";
137 #endif
138 int error;
139
140 #ifdef SCTL_MASK32
141 if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch)
142 error = SYSCTL_OUT(req, machine32, sizeof(machine32));
143 else
144 #endif
145 error = SYSCTL_OUT(req, machine, sizeof(machine));
146 return (error);
147
148 }
149 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD,
150 NULL, 0, sysctl_hw_machine, "A", "Machine class");
151 #else
152 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
153 machine, 0, "Machine class");
154 #endif
155
156 static char cpu_model[128];
157 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
158 cpu_model, 0, "Machine model");
159
160 static int hw_clockrate;
161 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
162 &hw_clockrate, 0, "CPU instruction clock rate");
163
164 u_int hv_high;
165 char hv_vendor[16];
166 SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD, hv_vendor, 0,
167 "Hypervisor vendor");
168
169 static eventhandler_tag tsc_post_tag;
170
171 static char cpu_brand[48];
172
173 #ifdef __i386__
174 #define MAX_BRAND_INDEX 8
175
176 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
177 NULL, /* No brand */
178 "Intel Celeron",
179 "Intel Pentium III",
180 "Intel Pentium III Xeon",
181 NULL,
182 NULL,
183 NULL,
184 NULL,
185 "Intel Pentium 4"
186 };
187 #endif
188
189 static struct {
190 char *cpu_name;
191 int cpu_class;
192 } cpus[] = {
193 #ifdef __i386__
194 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */
195 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */
196 { "i386DX", CPUCLASS_386 }, /* CPU_386 */
197 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */
198 { "i486DX", CPUCLASS_486 }, /* CPU_486 */
199 { "Pentium", CPUCLASS_586 }, /* CPU_586 */
200 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */
201 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */
202 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */
203 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */
204 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */
205 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */
206 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */
207 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */
208 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */
209 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */
210 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */
211 #else
212 { "Clawhammer", CPUCLASS_K8 }, /* CPU_CLAWHAMMER */
213 { "Sledgehammer", CPUCLASS_K8 }, /* CPU_SLEDGEHAMMER */
214 #endif
215 };
216
217 static struct {
218 char *vendor;
219 u_int vendor_id;
220 } cpu_vendors[] = {
221 { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */
222 { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */
223 { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */
224 #ifdef __i386__
225 { NSC_VENDOR_ID, CPU_VENDOR_NSC }, /* Geode by NSC */
226 { CYRIX_VENDOR_ID, CPU_VENDOR_CYRIX }, /* CyrixInstead */
227 { TRANSMETA_VENDOR_ID, CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
228 { SIS_VENDOR_ID, CPU_VENDOR_SIS }, /* SiS SiS SiS */
229 { UMC_VENDOR_ID, CPU_VENDOR_UMC }, /* UMC UMC UMC */
230 { NEXGEN_VENDOR_ID, CPU_VENDOR_NEXGEN }, /* NexGenDriven */
231 { RISE_VENDOR_ID, CPU_VENDOR_RISE }, /* RiseRiseRise */
232 #if 0
233 /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
234 { "TransmetaCPU", CPU_VENDOR_TRANSMETA },
235 #endif
236 #endif
237 };
238
239 void
printcpuinfo(void)240 printcpuinfo(void)
241 {
242 u_int regs[4], i;
243 char *brand;
244
245 cpu_class = cpus[cpu].cpu_class;
246 printf("CPU: ");
247 strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model));
248
249 /* Check for extended CPUID information and a processor name. */
250 if (cpu_exthigh >= 0x80000004) {
251 brand = cpu_brand;
252 for (i = 0x80000002; i < 0x80000005; i++) {
253 do_cpuid(i, regs);
254 memcpy(brand, regs, sizeof(regs));
255 brand += sizeof(regs);
256 }
257 }
258
259 switch (cpu_vendor_id) {
260 case CPU_VENDOR_INTEL:
261 #ifdef __i386__
262 if ((cpu_id & 0xf00) > 0x300) {
263 u_int brand_index;
264
265 cpu_model[0] = '\0';
266
267 switch (cpu_id & 0x3000) {
268 case 0x1000:
269 strcpy(cpu_model, "Overdrive ");
270 break;
271 case 0x2000:
272 strcpy(cpu_model, "Dual ");
273 break;
274 }
275
276 switch (cpu_id & 0xf00) {
277 case 0x400:
278 strcat(cpu_model, "i486 ");
279 /* Check the particular flavor of 486 */
280 switch (cpu_id & 0xf0) {
281 case 0x00:
282 case 0x10:
283 strcat(cpu_model, "DX");
284 break;
285 case 0x20:
286 strcat(cpu_model, "SX");
287 break;
288 case 0x30:
289 strcat(cpu_model, "DX2");
290 break;
291 case 0x40:
292 strcat(cpu_model, "SL");
293 break;
294 case 0x50:
295 strcat(cpu_model, "SX2");
296 break;
297 case 0x70:
298 strcat(cpu_model,
299 "DX2 Write-Back Enhanced");
300 break;
301 case 0x80:
302 strcat(cpu_model, "DX4");
303 break;
304 }
305 break;
306 case 0x500:
307 /* Check the particular flavor of 586 */
308 strcat(cpu_model, "Pentium");
309 switch (cpu_id & 0xf0) {
310 case 0x00:
311 strcat(cpu_model, " A-step");
312 break;
313 case 0x10:
314 strcat(cpu_model, "/P5");
315 break;
316 case 0x20:
317 strcat(cpu_model, "/P54C");
318 break;
319 case 0x30:
320 strcat(cpu_model, "/P24T");
321 break;
322 case 0x40:
323 strcat(cpu_model, "/P55C");
324 break;
325 case 0x70:
326 strcat(cpu_model, "/P54C");
327 break;
328 case 0x80:
329 strcat(cpu_model, "/P55C (quarter-micron)");
330 break;
331 default:
332 /* nothing */
333 break;
334 }
335 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
336 /*
337 * XXX - If/when Intel fixes the bug, this
338 * should also check the version of the
339 * CPU, not just that it's a Pentium.
340 */
341 has_f00f_bug = 1;
342 #endif
343 break;
344 case 0x600:
345 /* Check the particular flavor of 686 */
346 switch (cpu_id & 0xf0) {
347 case 0x00:
348 strcat(cpu_model, "Pentium Pro A-step");
349 break;
350 case 0x10:
351 strcat(cpu_model, "Pentium Pro");
352 break;
353 case 0x30:
354 case 0x50:
355 case 0x60:
356 strcat(cpu_model,
357 "Pentium II/Pentium II Xeon/Celeron");
358 cpu = CPU_PII;
359 break;
360 case 0x70:
361 case 0x80:
362 case 0xa0:
363 case 0xb0:
364 strcat(cpu_model,
365 "Pentium III/Pentium III Xeon/Celeron");
366 cpu = CPU_PIII;
367 break;
368 default:
369 strcat(cpu_model, "Unknown 80686");
370 break;
371 }
372 break;
373 case 0xf00:
374 strcat(cpu_model, "Pentium 4");
375 cpu = CPU_P4;
376 break;
377 default:
378 strcat(cpu_model, "unknown");
379 break;
380 }
381
382 /*
383 * If we didn't get a brand name from the extended
384 * CPUID, try to look it up in the brand table.
385 */
386 if (cpu_high > 0 && *cpu_brand == '\0') {
387 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
388 if (brand_index <= MAX_BRAND_INDEX &&
389 cpu_brandtable[brand_index] != NULL)
390 strcpy(cpu_brand,
391 cpu_brandtable[brand_index]);
392 }
393 }
394 #else
395 /* Please make up your mind folks! */
396 strcat(cpu_model, "EM64T");
397 #endif
398 break;
399 case CPU_VENDOR_AMD:
400 /*
401 * Values taken from AMD Processor Recognition
402 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
403 * (also describes ``Features'' encodings.
404 */
405 strcpy(cpu_model, "AMD ");
406 #ifdef __i386__
407 switch (cpu_id & 0xFF0) {
408 case 0x410:
409 strcat(cpu_model, "Standard Am486DX");
410 break;
411 case 0x430:
412 strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
413 break;
414 case 0x470:
415 strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
416 break;
417 case 0x480:
418 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
419 break;
420 case 0x490:
421 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
422 break;
423 case 0x4E0:
424 strcat(cpu_model, "Am5x86 Write-Through");
425 break;
426 case 0x4F0:
427 strcat(cpu_model, "Am5x86 Write-Back");
428 break;
429 case 0x500:
430 strcat(cpu_model, "K5 model 0");
431 break;
432 case 0x510:
433 strcat(cpu_model, "K5 model 1");
434 break;
435 case 0x520:
436 strcat(cpu_model, "K5 PR166 (model 2)");
437 break;
438 case 0x530:
439 strcat(cpu_model, "K5 PR200 (model 3)");
440 break;
441 case 0x560:
442 strcat(cpu_model, "K6");
443 break;
444 case 0x570:
445 strcat(cpu_model, "K6 266 (model 1)");
446 break;
447 case 0x580:
448 strcat(cpu_model, "K6-2");
449 break;
450 case 0x590:
451 strcat(cpu_model, "K6-III");
452 break;
453 case 0x5a0:
454 strcat(cpu_model, "Geode LX");
455 break;
456 default:
457 strcat(cpu_model, "Unknown");
458 break;
459 }
460 #else
461 if ((cpu_id & 0xf00) == 0xf00)
462 strcat(cpu_model, "AMD64 Processor");
463 else
464 strcat(cpu_model, "Unknown");
465 #endif
466 break;
467 #ifdef __i386__
468 case CPU_VENDOR_CYRIX:
469 strcpy(cpu_model, "Cyrix ");
470 switch (cpu_id & 0xff0) {
471 case 0x440:
472 strcat(cpu_model, "MediaGX");
473 break;
474 case 0x520:
475 strcat(cpu_model, "6x86");
476 break;
477 case 0x540:
478 cpu_class = CPUCLASS_586;
479 strcat(cpu_model, "GXm");
480 break;
481 case 0x600:
482 strcat(cpu_model, "6x86MX");
483 break;
484 default:
485 /*
486 * Even though CPU supports the cpuid
487 * instruction, it can be disabled.
488 * Therefore, this routine supports all Cyrix
489 * CPUs.
490 */
491 switch (cyrix_did & 0xf0) {
492 case 0x00:
493 switch (cyrix_did & 0x0f) {
494 case 0x00:
495 strcat(cpu_model, "486SLC");
496 break;
497 case 0x01:
498 strcat(cpu_model, "486DLC");
499 break;
500 case 0x02:
501 strcat(cpu_model, "486SLC2");
502 break;
503 case 0x03:
504 strcat(cpu_model, "486DLC2");
505 break;
506 case 0x04:
507 strcat(cpu_model, "486SRx");
508 break;
509 case 0x05:
510 strcat(cpu_model, "486DRx");
511 break;
512 case 0x06:
513 strcat(cpu_model, "486SRx2");
514 break;
515 case 0x07:
516 strcat(cpu_model, "486DRx2");
517 break;
518 case 0x08:
519 strcat(cpu_model, "486SRu");
520 break;
521 case 0x09:
522 strcat(cpu_model, "486DRu");
523 break;
524 case 0x0a:
525 strcat(cpu_model, "486SRu2");
526 break;
527 case 0x0b:
528 strcat(cpu_model, "486DRu2");
529 break;
530 default:
531 strcat(cpu_model, "Unknown");
532 break;
533 }
534 break;
535 case 0x10:
536 switch (cyrix_did & 0x0f) {
537 case 0x00:
538 strcat(cpu_model, "486S");
539 break;
540 case 0x01:
541 strcat(cpu_model, "486S2");
542 break;
543 case 0x02:
544 strcat(cpu_model, "486Se");
545 break;
546 case 0x03:
547 strcat(cpu_model, "486S2e");
548 break;
549 case 0x0a:
550 strcat(cpu_model, "486DX");
551 break;
552 case 0x0b:
553 strcat(cpu_model, "486DX2");
554 break;
555 case 0x0f:
556 strcat(cpu_model, "486DX4");
557 break;
558 default:
559 strcat(cpu_model, "Unknown");
560 break;
561 }
562 break;
563 case 0x20:
564 if ((cyrix_did & 0x0f) < 8)
565 strcat(cpu_model, "6x86"); /* Where did you get it? */
566 else
567 strcat(cpu_model, "5x86");
568 break;
569 case 0x30:
570 strcat(cpu_model, "6x86");
571 break;
572 case 0x40:
573 if ((cyrix_did & 0xf000) == 0x3000) {
574 cpu_class = CPUCLASS_586;
575 strcat(cpu_model, "GXm");
576 } else
577 strcat(cpu_model, "MediaGX");
578 break;
579 case 0x50:
580 strcat(cpu_model, "6x86MX");
581 break;
582 case 0xf0:
583 switch (cyrix_did & 0x0f) {
584 case 0x0d:
585 strcat(cpu_model, "Overdrive CPU");
586 break;
587 case 0x0e:
588 strcpy(cpu_model, "Texas Instruments 486SXL");
589 break;
590 case 0x0f:
591 strcat(cpu_model, "486SLC/DLC");
592 break;
593 default:
594 strcat(cpu_model, "Unknown");
595 break;
596 }
597 break;
598 default:
599 strcat(cpu_model, "Unknown");
600 break;
601 }
602 break;
603 }
604 break;
605 case CPU_VENDOR_RISE:
606 strcpy(cpu_model, "Rise ");
607 switch (cpu_id & 0xff0) {
608 case 0x500: /* 6401 and 6441 (Kirin) */
609 case 0x520: /* 6510 (Lynx) */
610 strcat(cpu_model, "mP6");
611 break;
612 default:
613 strcat(cpu_model, "Unknown");
614 }
615 break;
616 #endif
617 case CPU_VENDOR_CENTAUR:
618 #ifdef __i386__
619 switch (cpu_id & 0xff0) {
620 case 0x540:
621 strcpy(cpu_model, "IDT WinChip C6");
622 break;
623 case 0x580:
624 strcpy(cpu_model, "IDT WinChip 2");
625 break;
626 case 0x590:
627 strcpy(cpu_model, "IDT WinChip 3");
628 break;
629 case 0x660:
630 strcpy(cpu_model, "VIA C3 Samuel");
631 break;
632 case 0x670:
633 if (cpu_id & 0x8)
634 strcpy(cpu_model, "VIA C3 Ezra");
635 else
636 strcpy(cpu_model, "VIA C3 Samuel 2");
637 break;
638 case 0x680:
639 strcpy(cpu_model, "VIA C3 Ezra-T");
640 break;
641 case 0x690:
642 strcpy(cpu_model, "VIA C3 Nehemiah");
643 break;
644 case 0x6a0:
645 case 0x6d0:
646 strcpy(cpu_model, "VIA C7 Esther");
647 break;
648 case 0x6f0:
649 strcpy(cpu_model, "VIA Nano");
650 break;
651 default:
652 strcpy(cpu_model, "VIA/IDT Unknown");
653 }
654 #else
655 strcpy(cpu_model, "VIA ");
656 if ((cpu_id & 0xff0) == 0x6f0)
657 strcat(cpu_model, "Nano Processor");
658 else
659 strcat(cpu_model, "Unknown");
660 #endif
661 break;
662 #ifdef __i386__
663 case CPU_VENDOR_IBM:
664 strcpy(cpu_model, "Blue Lightning CPU");
665 break;
666 case CPU_VENDOR_NSC:
667 switch (cpu_id & 0xff0) {
668 case 0x540:
669 strcpy(cpu_model, "Geode SC1100");
670 cpu = CPU_GEODE1100;
671 break;
672 default:
673 strcpy(cpu_model, "Geode/NSC unknown");
674 break;
675 }
676 break;
677 #endif
678 default:
679 strcat(cpu_model, "Unknown");
680 break;
681 }
682
683 /*
684 * Replace cpu_model with cpu_brand minus leading spaces if
685 * we have one.
686 */
687 brand = cpu_brand;
688 while (*brand == ' ')
689 ++brand;
690 if (*brand != '\0')
691 strcpy(cpu_model, brand);
692
693 printf("%s (", cpu_model);
694 if (tsc_freq != 0) {
695 hw_clockrate = (tsc_freq + 5000) / 1000000;
696 printf("%jd.%02d-MHz ",
697 (intmax_t)(tsc_freq + 4999) / 1000000,
698 (u_int)((tsc_freq + 4999) / 10000) % 100);
699 }
700 switch(cpu_class) {
701 #ifdef __i386__
702 case CPUCLASS_286:
703 printf("286");
704 break;
705 case CPUCLASS_386:
706 printf("386");
707 break;
708 #if defined(I486_CPU)
709 case CPUCLASS_486:
710 printf("486");
711 break;
712 #endif
713 #if defined(I586_CPU)
714 case CPUCLASS_586:
715 printf("586");
716 break;
717 #endif
718 #if defined(I686_CPU)
719 case CPUCLASS_686:
720 printf("686");
721 break;
722 #endif
723 #else
724 case CPUCLASS_K8:
725 printf("K8");
726 break;
727 #endif
728 default:
729 printf("Unknown"); /* will panic below... */
730 }
731 printf("-class CPU)\n");
732 if (*cpu_vendor)
733 printf(" Origin=\"%s\"", cpu_vendor);
734 if (cpu_id)
735 printf(" Id=0x%x", cpu_id);
736
737 if (cpu_vendor_id == CPU_VENDOR_INTEL ||
738 cpu_vendor_id == CPU_VENDOR_AMD ||
739 cpu_vendor_id == CPU_VENDOR_CENTAUR ||
740 #ifdef __i386__
741 cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
742 cpu_vendor_id == CPU_VENDOR_RISE ||
743 cpu_vendor_id == CPU_VENDOR_NSC ||
744 (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) ||
745 #endif
746 0) {
747 printf(" Family=0x%x", CPUID_TO_FAMILY(cpu_id));
748 printf(" Model=0x%x", CPUID_TO_MODEL(cpu_id));
749 printf(" Stepping=%u", cpu_id & CPUID_STEPPING);
750 #ifdef __i386__
751 if (cpu_vendor_id == CPU_VENDOR_CYRIX)
752 printf("\n DIR=0x%04x", cyrix_did);
753 #endif
754
755 /*
756 * AMD CPUID Specification
757 * http://support.amd.com/us/Embedded_TechDocs/25481.pdf
758 *
759 * Intel Processor Identification and CPUID Instruction
760 * http://www.intel.com/assets/pdf/appnote/241618.pdf
761 */
762 if (cpu_high > 0) {
763
764 /*
765 * Here we should probably set up flags indicating
766 * whether or not various features are available.
767 * The interesting ones are probably VME, PSE, PAE,
768 * and PGE. The code already assumes without bothering
769 * to check that all CPUs >= Pentium have a TSC and
770 * MSRs.
771 */
772 printf("\n Features=0x%b", cpu_feature,
773 "\020"
774 "\001FPU" /* Integral FPU */
775 "\002VME" /* Extended VM86 mode support */
776 "\003DE" /* Debugging Extensions (CR4.DE) */
777 "\004PSE" /* 4MByte page tables */
778 "\005TSC" /* Timestamp counter */
779 "\006MSR" /* Machine specific registers */
780 "\007PAE" /* Physical address extension */
781 "\010MCE" /* Machine Check support */
782 "\011CX8" /* CMPEXCH8 instruction */
783 "\012APIC" /* SMP local APIC */
784 "\013oldMTRR" /* Previous implementation of MTRR */
785 "\014SEP" /* Fast System Call */
786 "\015MTRR" /* Memory Type Range Registers */
787 "\016PGE" /* PG_G (global bit) support */
788 "\017MCA" /* Machine Check Architecture */
789 "\020CMOV" /* CMOV instruction */
790 "\021PAT" /* Page attributes table */
791 "\022PSE36" /* 36 bit address space support */
792 "\023PN" /* Processor Serial number */
793 "\024CLFLUSH" /* Has the CLFLUSH instruction */
794 "\025<b20>"
795 "\026DTS" /* Debug Trace Store */
796 "\027ACPI" /* ACPI support */
797 "\030MMX" /* MMX instructions */
798 "\031FXSR" /* FXSAVE/FXRSTOR */
799 "\032SSE" /* Streaming SIMD Extensions */
800 "\033SSE2" /* Streaming SIMD Extensions #2 */
801 "\034SS" /* Self snoop */
802 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */
803 "\036TM" /* Thermal Monitor clock slowdown */
804 "\037IA64" /* CPU can execute IA64 instructions */
805 "\040PBE" /* Pending Break Enable */
806 );
807
808 if (cpu_feature2 != 0) {
809 printf("\n Features2=0x%b", cpu_feature2,
810 "\020"
811 "\001SSE3" /* SSE3 */
812 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
813 "\003DTES64" /* 64-bit Debug Trace */
814 "\004MON" /* MONITOR/MWAIT Instructions */
815 "\005DS_CPL" /* CPL Qualified Debug Store */
816 "\006VMX" /* Virtual Machine Extensions */
817 "\007SMX" /* Safer Mode Extensions */
818 "\010EST" /* Enhanced SpeedStep */
819 "\011TM2" /* Thermal Monitor 2 */
820 "\012SSSE3" /* SSSE3 */
821 "\013CNXT-ID" /* L1 context ID available */
822 "\014SDBG" /* IA32 silicon debug */
823 "\015FMA" /* Fused Multiply Add */
824 "\016CX16" /* CMPXCHG16B Instruction */
825 "\017xTPR" /* Send Task Priority Messages*/
826 "\020PDCM" /* Perf/Debug Capability MSR */
827 "\021<b16>"
828 "\022PCID" /* Process-context Identifiers*/
829 "\023DCA" /* Direct Cache Access */
830 "\024SSE4.1" /* SSE 4.1 */
831 "\025SSE4.2" /* SSE 4.2 */
832 "\026x2APIC" /* xAPIC Extensions */
833 "\027MOVBE" /* MOVBE Instruction */
834 "\030POPCNT" /* POPCNT Instruction */
835 "\031TSCDLT" /* TSC-Deadline Timer */
836 "\032AESNI" /* AES Crypto */
837 "\033XSAVE" /* XSAVE/XRSTOR States */
838 "\034OSXSAVE" /* OS-Enabled State Management*/
839 "\035AVX" /* Advanced Vector Extensions */
840 "\036F16C" /* Half-precision conversions */
841 "\037RDRAND" /* RDRAND Instruction */
842 "\040HV" /* Hypervisor */
843 );
844 }
845
846 if (amd_feature != 0) {
847 printf("\n AMD Features=0x%b", amd_feature,
848 "\020" /* in hex */
849 "\001<s0>" /* Same */
850 "\002<s1>" /* Same */
851 "\003<s2>" /* Same */
852 "\004<s3>" /* Same */
853 "\005<s4>" /* Same */
854 "\006<s5>" /* Same */
855 "\007<s6>" /* Same */
856 "\010<s7>" /* Same */
857 "\011<s8>" /* Same */
858 "\012<s9>" /* Same */
859 "\013<b10>" /* Undefined */
860 "\014SYSCALL" /* Have SYSCALL/SYSRET */
861 "\015<s12>" /* Same */
862 "\016<s13>" /* Same */
863 "\017<s14>" /* Same */
864 "\020<s15>" /* Same */
865 "\021<s16>" /* Same */
866 "\022<s17>" /* Same */
867 "\023<b18>" /* Reserved, unknown */
868 "\024MP" /* Multiprocessor Capable */
869 "\025NX" /* Has EFER.NXE, NX */
870 "\026<b21>" /* Undefined */
871 "\027MMX+" /* AMD MMX Extensions */
872 "\030<s23>" /* Same */
873 "\031<s24>" /* Same */
874 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */
875 "\033Page1GB" /* 1-GB large page support */
876 "\034RDTSCP" /* RDTSCP */
877 "\035<b28>" /* Undefined */
878 "\036LM" /* 64 bit long mode */
879 "\0373DNow!+" /* AMD 3DNow! Extensions */
880 "\0403DNow!" /* AMD 3DNow! */
881 );
882 }
883
884 if (amd_feature2 != 0) {
885 printf("\n AMD Features2=0x%b", amd_feature2,
886 "\020"
887 "\001LAHF" /* LAHF/SAHF in long mode */
888 "\002CMP" /* CMP legacy */
889 "\003SVM" /* Secure Virtual Mode */
890 "\004ExtAPIC" /* Extended APIC register */
891 "\005CR8" /* CR8 in legacy mode */
892 "\006ABM" /* LZCNT instruction */
893 "\007SSE4A" /* SSE4A */
894 "\010MAS" /* Misaligned SSE mode */
895 "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */
896 "\012OSVW" /* OS visible workaround */
897 "\013IBS" /* Instruction based sampling */
898 "\014XOP" /* XOP extended instructions */
899 "\015SKINIT" /* SKINIT/STGI */
900 "\016WDT" /* Watchdog timer */
901 "\017<b14>"
902 "\020LWP" /* Lightweight Profiling */
903 "\021FMA4" /* 4-operand FMA instructions */
904 "\022TCE" /* Translation Cache Extension */
905 "\023<b18>"
906 "\024NodeId" /* NodeId MSR support */
907 "\025<b20>"
908 "\026TBM" /* Trailing Bit Manipulation */
909 "\027Topology" /* Topology Extensions */
910 "\030PCXC" /* Core perf count */
911 "\031PNXC" /* NB perf count */
912 "\032<b25>"
913 "\033DBE" /* Data Breakpoint extension */
914 "\034PTSC" /* Performance TSC */
915 "\035PL2I" /* L2I perf count */
916 "\036<b29>"
917 "\037<b30>"
918 "\040<b31>"
919 );
920 }
921
922 if (cpu_stdext_feature != 0) {
923 printf("\n Structured Extended Features=0x%b",
924 cpu_stdext_feature,
925 "\020"
926 /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
927 "\001FSGSBASE"
928 "\002TSCADJ"
929 /* Bit Manipulation Instructions */
930 "\004BMI1"
931 /* Hardware Lock Elision */
932 "\005HLE"
933 /* Advanced Vector Instructions 2 */
934 "\006AVX2"
935 /* FDP_EXCPTN_ONLY */
936 "\007FDPEXC"
937 /* Supervisor Mode Execution Prot. */
938 "\010SMEP"
939 /* Bit Manipulation Instructions */
940 "\011BMI2"
941 "\012ERMS"
942 /* Invalidate Processor Context ID */
943 "\013INVPCID"
944 /* Restricted Transactional Memory */
945 "\014RTM"
946 "\015PQM"
947 "\016NFPUSG"
948 "\020PQE"
949 /* Intel Memory Protection Extensions */
950 "\017MPX"
951 /* AVX512 Foundation */
952 "\021AVX512F"
953 "\022AVX512DQ"
954 /* Enhanced NRBG */
955 "\023RDSEED"
956 /* ADCX + ADOX */
957 "\024ADX"
958 /* Supervisor Mode Access Prevention */
959 "\025SMAP"
960 "\026AVX512IFMA"
961 "\027PCOMMIT"
962 "\030CLFLUSHOPT"
963 "\031CLWB"
964 "\032PROCTRACE"
965 "\033AVX512PF"
966 "\034AVX512ER"
967 "\035AVX512CD"
968 "\036SHA"
969 "\037AVX512BW"
970 );
971 }
972
973 if (cpu_stdext_feature2 != 0) {
974 printf("\n Structured Extended Features2=0x%b",
975 cpu_stdext_feature2,
976 "\020"
977 "\001PREFETCHWT1"
978 "\002AVX512VBMI"
979 "\004PKU"
980 "\005OSPKE"
981 );
982 }
983
984 if ((cpu_feature2 & CPUID2_XSAVE) != 0) {
985 cpuid_count(0xd, 0x1, regs);
986 if (regs[0] != 0) {
987 printf("\n XSAVE Features=0x%b",
988 regs[0],
989 "\020"
990 "\001XSAVEOPT"
991 "\002XSAVEC"
992 "\003XINUSE"
993 "\004XSAVES");
994 }
995 }
996
997 if (via_feature_rng != 0 || via_feature_xcrypt != 0)
998 print_via_padlock_info();
999
1000 if (cpu_feature2 & CPUID2_VMX)
1001 print_vmx_info();
1002
1003 if (amd_feature2 & AMDID2_SVM)
1004 print_svm_info();
1005
1006 if ((cpu_feature & CPUID_HTT) &&
1007 cpu_vendor_id == CPU_VENDOR_AMD)
1008 cpu_feature &= ~CPUID_HTT;
1009
1010 /*
1011 * If this CPU supports P-state invariant TSC then
1012 * mention the capability.
1013 */
1014 if (tsc_is_invariant) {
1015 printf("\n TSC: P-state invariant");
1016 if (tsc_perf_stat)
1017 printf(", performance statistics");
1018 }
1019 }
1020 #ifdef __i386__
1021 } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1022 printf(" DIR=0x%04x", cyrix_did);
1023 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12);
1024 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8);
1025 #ifndef CYRIX_CACHE_REALLY_WORKS
1026 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
1027 printf("\n CPU cache: write-through mode");
1028 #endif
1029 #endif
1030 }
1031
1032 /* Avoid ugly blank lines: only print newline when we have to. */
1033 if (*cpu_vendor || cpu_id)
1034 printf("\n");
1035
1036 if (bootverbose) {
1037 if (cpu_vendor_id == CPU_VENDOR_AMD)
1038 print_AMD_info();
1039 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
1040 print_INTEL_info();
1041 #ifdef __i386__
1042 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
1043 print_transmeta_info();
1044 #endif
1045 }
1046
1047 print_hypervisor_info();
1048 }
1049
1050 void
panicifcpuunsupported(void)1051 panicifcpuunsupported(void)
1052 {
1053
1054 #ifdef __i386__
1055 #if !defined(lint)
1056 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
1057 #error This kernel is not configured for one of the supported CPUs
1058 #endif
1059 #else /* lint */
1060 #endif /* lint */
1061 #else /* __amd64__ */
1062 #ifndef HAMMER
1063 #error "You need to specify a cpu type"
1064 #endif
1065 #endif
1066 /*
1067 * Now that we have told the user what they have,
1068 * let them know if that machine type isn't configured.
1069 */
1070 switch (cpu_class) {
1071 #ifdef __i386__
1072 case CPUCLASS_286: /* a 286 should not make it this far, anyway */
1073 case CPUCLASS_386:
1074 #if !defined(I486_CPU)
1075 case CPUCLASS_486:
1076 #endif
1077 #if !defined(I586_CPU)
1078 case CPUCLASS_586:
1079 #endif
1080 #if !defined(I686_CPU)
1081 case CPUCLASS_686:
1082 #endif
1083 #else /* __amd64__ */
1084 case CPUCLASS_X86:
1085 #ifndef HAMMER
1086 case CPUCLASS_K8:
1087 #endif
1088 #endif
1089 panic("CPU class not configured");
1090 default:
1091 break;
1092 }
1093 }
1094
1095 #ifdef __i386__
1096 static volatile u_int trap_by_rdmsr;
1097
1098 /*
1099 * Special exception 6 handler.
1100 * The rdmsr instruction generates invalid opcodes fault on 486-class
1101 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the
1102 * function identblue() when this handler is called. Stacked eip should
1103 * be advanced.
1104 */
1105 inthand_t bluetrap6;
1106 #ifdef __GNUCLIKE_ASM
1107 __asm
1108 (" \n\
1109 .text \n\
1110 .p2align 2,0x90 \n\
1111 .type " __XSTRING(CNAME(bluetrap6)) ",@function \n\
1112 " __XSTRING(CNAME(bluetrap6)) ": \n\
1113 ss \n\
1114 movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
1115 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
1116 iret \n\
1117 ");
1118 #endif
1119
1120 /*
1121 * Special exception 13 handler.
1122 * Accessing non-existent MSR generates general protection fault.
1123 */
1124 inthand_t bluetrap13;
1125 #ifdef __GNUCLIKE_ASM
1126 __asm
1127 (" \n\
1128 .text \n\
1129 .p2align 2,0x90 \n\
1130 .type " __XSTRING(CNAME(bluetrap13)) ",@function \n\
1131 " __XSTRING(CNAME(bluetrap13)) ": \n\
1132 ss \n\
1133 movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
1134 popl %eax /* discard error code */ \n\
1135 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
1136 iret \n\
1137 ");
1138 #endif
1139
1140 /*
1141 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
1142 * support cpuid instruction. This function should be called after
1143 * loading interrupt descriptor table register.
1144 *
1145 * I don't like this method that handles fault, but I couldn't get
1146 * information for any other methods. Does blue giant know?
1147 */
1148 static int
identblue(void)1149 identblue(void)
1150 {
1151
1152 trap_by_rdmsr = 0;
1153
1154 /*
1155 * Cyrix 486-class CPU does not support rdmsr instruction.
1156 * The rdmsr instruction generates invalid opcode fault, and exception
1157 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The
1158 * bluetrap6() set the magic number to trap_by_rdmsr.
1159 */
1160 setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
1161 GSEL(GCODE_SEL, SEL_KPL));
1162
1163 /*
1164 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
1165 * In this case, rdmsr generates general protection fault, and
1166 * exception will be trapped by bluetrap13().
1167 */
1168 setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
1169 GSEL(GCODE_SEL, SEL_KPL));
1170
1171 rdmsr(0x1002); /* Cyrix CPU generates fault. */
1172
1173 if (trap_by_rdmsr == 0xa8c1d)
1174 return IDENTBLUE_CYRIX486;
1175 else if (trap_by_rdmsr == 0xa89c4)
1176 return IDENTBLUE_CYRIXM2;
1177 return IDENTBLUE_IBMCPU;
1178 }
1179
1180
1181 /*
1182 * identifycyrix() set lower 16 bits of cyrix_did as follows:
1183 *
1184 * F E D C B A 9 8 7 6 5 4 3 2 1 0
1185 * +-------+-------+---------------+
1186 * | SID | RID | Device ID |
1187 * | (DIR 1) | (DIR 0) |
1188 * +-------+-------+---------------+
1189 */
1190 static void
identifycyrix(void)1191 identifycyrix(void)
1192 {
1193 register_t saveintr;
1194 int ccr2_test = 0, dir_test = 0;
1195 u_char ccr2, ccr3;
1196
1197 saveintr = intr_disable();
1198
1199 ccr2 = read_cyrix_reg(CCR2);
1200 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
1201 read_cyrix_reg(CCR2);
1202 if (read_cyrix_reg(CCR2) != ccr2)
1203 ccr2_test = 1;
1204 write_cyrix_reg(CCR2, ccr2);
1205
1206 ccr3 = read_cyrix_reg(CCR3);
1207 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
1208 read_cyrix_reg(CCR3);
1209 if (read_cyrix_reg(CCR3) != ccr3)
1210 dir_test = 1; /* CPU supports DIRs. */
1211 write_cyrix_reg(CCR3, ccr3);
1212
1213 if (dir_test) {
1214 /* Device ID registers are available. */
1215 cyrix_did = read_cyrix_reg(DIR1) << 8;
1216 cyrix_did += read_cyrix_reg(DIR0);
1217 } else if (ccr2_test)
1218 cyrix_did = 0x0010; /* 486S A-step */
1219 else
1220 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */
1221
1222 intr_restore(saveintr);
1223 }
1224 #endif
1225
1226 /* Update TSC freq with the value indicated by the caller. */
1227 static void
tsc_freq_changed(void * arg __unused,const struct cf_level * level,int status)1228 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status)
1229 {
1230
1231 /* If there was an error during the transition, don't do anything. */
1232 if (status != 0)
1233 return;
1234
1235 /* Total setting for this level gives the new frequency in MHz. */
1236 hw_clockrate = level->total_set.freq;
1237 }
1238
1239 static void
hook_tsc_freq(void * arg __unused)1240 hook_tsc_freq(void *arg __unused)
1241 {
1242
1243 if (tsc_is_invariant)
1244 return;
1245
1246 tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change,
1247 tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY);
1248 }
1249
1250 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL);
1251
1252 static const char *const vm_bnames[] = {
1253 "QEMU", /* QEMU */
1254 "Plex86", /* Plex86 */
1255 "Bochs", /* Bochs */
1256 "Xen", /* Xen */
1257 "BHYVE", /* bhyve */
1258 "Seabios", /* KVM */
1259 NULL
1260 };
1261
1262 static const char *const vm_pnames[] = {
1263 "VMware Virtual Platform", /* VMWare VM */
1264 "Virtual Machine", /* Microsoft VirtualPC */
1265 "VirtualBox", /* Sun xVM VirtualBox */
1266 "Parallels Virtual Platform", /* Parallels VM */
1267 "KVM", /* KVM */
1268 NULL
1269 };
1270
1271 static void
identify_hypervisor(void)1272 identify_hypervisor(void)
1273 {
1274 u_int regs[4];
1275 char *p;
1276 int i;
1277
1278 /*
1279 * [RFC] CPUID usage for interaction between Hypervisors and Linux.
1280 * http://lkml.org/lkml/2008/10/1/246
1281 *
1282 * KB1009458: Mechanisms to determine if software is running in
1283 * a VMware virtual machine
1284 * http://kb.vmware.com/kb/1009458
1285 */
1286 if (cpu_feature2 & CPUID2_HV) {
1287 vm_guest = VM_GUEST_VM;
1288 do_cpuid(0x40000000, regs);
1289 if (regs[0] >= 0x40000000) {
1290 hv_high = regs[0];
1291 ((u_int *)&hv_vendor)[0] = regs[1];
1292 ((u_int *)&hv_vendor)[1] = regs[2];
1293 ((u_int *)&hv_vendor)[2] = regs[3];
1294 hv_vendor[12] = '\0';
1295 if (strcmp(hv_vendor, "VMwareVMware") == 0)
1296 vm_guest = VM_GUEST_VMWARE;
1297 }
1298 return;
1299 }
1300
1301 /*
1302 * Examine SMBIOS strings for older hypervisors.
1303 */
1304 p = kern_getenv("smbios.system.serial");
1305 if (p != NULL) {
1306 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) {
1307 vmware_hvcall(VMW_HVCMD_GETVERSION, regs);
1308 if (regs[1] == VMW_HVMAGIC) {
1309 vm_guest = VM_GUEST_VMWARE;
1310 freeenv(p);
1311 return;
1312 }
1313 }
1314 freeenv(p);
1315 }
1316
1317 /*
1318 * XXX: Some of these entries may not be needed since they were
1319 * added to FreeBSD before the checks above.
1320 */
1321 p = kern_getenv("smbios.bios.vendor");
1322 if (p != NULL) {
1323 for (i = 0; vm_bnames[i] != NULL; i++)
1324 if (strcmp(p, vm_bnames[i]) == 0) {
1325 vm_guest = VM_GUEST_VM;
1326 freeenv(p);
1327 return;
1328 }
1329 freeenv(p);
1330 }
1331 p = kern_getenv("smbios.system.product");
1332 if (p != NULL) {
1333 for (i = 0; vm_pnames[i] != NULL; i++)
1334 if (strcmp(p, vm_pnames[i]) == 0) {
1335 vm_guest = VM_GUEST_VM;
1336 freeenv(p);
1337 return;
1338 }
1339 freeenv(p);
1340 }
1341 }
1342
1343 /*
1344 * Clear "Limit CPUID Maxval" bit and return true if the caller should
1345 * get the largest standard CPUID function number again if it is set
1346 * from BIOS. It is necessary for probing correct CPU topology later
1347 * and for the correct operation of the AVX-aware userspace.
1348 */
1349 bool
intel_fix_cpuid(void)1350 intel_fix_cpuid(void)
1351 {
1352 uint64_t msr;
1353
1354 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1355 return (false);
1356 if ((CPUID_TO_FAMILY(cpu_id) == 0xf &&
1357 CPUID_TO_MODEL(cpu_id) >= 0x3) ||
1358 (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1359 CPUID_TO_MODEL(cpu_id) >= 0xe)) {
1360 msr = rdmsr(MSR_IA32_MISC_ENABLE);
1361 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) {
1362 msr &= ~IA32_MISC_EN_LIMCPUID;
1363 wrmsr(MSR_IA32_MISC_ENABLE, msr);
1364 return (true);
1365 }
1366 }
1367 return (false);
1368 }
1369
1370 /*
1371 * Final stage of CPU identification.
1372 */
1373 #ifdef __i386__
1374 void
finishidentcpu(void)1375 finishidentcpu(void)
1376 #else
1377 void
1378 identify_cpu(void)
1379 #endif
1380 {
1381 u_int regs[4], cpu_stdext_disable;
1382 #ifdef __i386__
1383 u_char ccr3;
1384 #endif
1385
1386 #ifdef __amd64__
1387 do_cpuid(0, regs);
1388 cpu_high = regs[0];
1389 ((u_int *)&cpu_vendor)[0] = regs[1];
1390 ((u_int *)&cpu_vendor)[1] = regs[3];
1391 ((u_int *)&cpu_vendor)[2] = regs[2];
1392 cpu_vendor[12] = '\0';
1393
1394 do_cpuid(1, regs);
1395 cpu_id = regs[0];
1396 cpu_procinfo = regs[1];
1397 cpu_feature = regs[3];
1398 cpu_feature2 = regs[2];
1399 #endif
1400
1401 identify_hypervisor();
1402 cpu_vendor_id = find_cpu_vendor_id();
1403
1404 if (intel_fix_cpuid()) {
1405 do_cpuid(0, regs);
1406 cpu_high = regs[0];
1407 }
1408
1409 if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) {
1410 do_cpuid(5, regs);
1411 cpu_mon_mwait_flags = regs[2];
1412 cpu_mon_min_size = regs[0] & CPUID5_MON_MIN_SIZE;
1413 cpu_mon_max_size = regs[1] & CPUID5_MON_MAX_SIZE;
1414 }
1415
1416 if (cpu_high >= 7) {
1417 cpuid_count(7, 0, regs);
1418 cpu_stdext_feature = regs[1];
1419
1420 /*
1421 * Some hypervisors fail to filter out unsupported
1422 * extended features. For now, disable the
1423 * extensions, activation of which requires setting a
1424 * bit in CR4, and which VM monitors do not support.
1425 */
1426 if (cpu_feature2 & CPUID2_HV) {
1427 cpu_stdext_disable = CPUID_STDEXT_FSGSBASE |
1428 CPUID_STDEXT_SMEP;
1429 } else
1430 cpu_stdext_disable = 0;
1431 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable);
1432 cpu_stdext_feature &= ~cpu_stdext_disable;
1433 cpu_stdext_feature2 = regs[2];
1434 }
1435
1436 #ifdef __i386__
1437 if (cpu_high > 0 &&
1438 (cpu_vendor_id == CPU_VENDOR_INTEL ||
1439 cpu_vendor_id == CPU_VENDOR_AMD ||
1440 cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
1441 cpu_vendor_id == CPU_VENDOR_CENTAUR ||
1442 cpu_vendor_id == CPU_VENDOR_NSC)) {
1443 do_cpuid(0x80000000, regs);
1444 if (regs[0] >= 0x80000000)
1445 cpu_exthigh = regs[0];
1446 }
1447 #else
1448 if (cpu_vendor_id == CPU_VENDOR_INTEL ||
1449 cpu_vendor_id == CPU_VENDOR_AMD ||
1450 cpu_vendor_id == CPU_VENDOR_CENTAUR) {
1451 do_cpuid(0x80000000, regs);
1452 cpu_exthigh = regs[0];
1453 }
1454 #endif
1455 if (cpu_exthigh >= 0x80000001) {
1456 do_cpuid(0x80000001, regs);
1457 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
1458 amd_feature2 = regs[2];
1459 }
1460 if (cpu_exthigh >= 0x80000007) {
1461 do_cpuid(0x80000007, regs);
1462 amd_pminfo = regs[3];
1463 }
1464 if (cpu_exthigh >= 0x80000008) {
1465 do_cpuid(0x80000008, regs);
1466 cpu_maxphyaddr = regs[0] & 0xff;
1467 cpu_procinfo2 = regs[2];
1468 } else {
1469 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32;
1470 }
1471
1472 #ifdef __i386__
1473 if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1474 if (cpu == CPU_486) {
1475 /*
1476 * These conditions are equivalent to:
1477 * - CPU does not support cpuid instruction.
1478 * - Cyrix/IBM CPU is detected.
1479 */
1480 if (identblue() == IDENTBLUE_IBMCPU) {
1481 strcpy(cpu_vendor, "IBM");
1482 cpu_vendor_id = CPU_VENDOR_IBM;
1483 cpu = CPU_BLUE;
1484 return;
1485 }
1486 }
1487 switch (cpu_id & 0xf00) {
1488 case 0x600:
1489 /*
1490 * Cyrix's datasheet does not describe DIRs.
1491 * Therefor, I assume it does not have them
1492 * and use the result of the cpuid instruction.
1493 * XXX they seem to have it for now at least. -Peter
1494 */
1495 identifycyrix();
1496 cpu = CPU_M2;
1497 break;
1498 default:
1499 identifycyrix();
1500 /*
1501 * This routine contains a trick.
1502 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
1503 */
1504 switch (cyrix_did & 0x00f0) {
1505 case 0x00:
1506 case 0xf0:
1507 cpu = CPU_486DLC;
1508 break;
1509 case 0x10:
1510 cpu = CPU_CY486DX;
1511 break;
1512 case 0x20:
1513 if ((cyrix_did & 0x000f) < 8)
1514 cpu = CPU_M1;
1515 else
1516 cpu = CPU_M1SC;
1517 break;
1518 case 0x30:
1519 cpu = CPU_M1;
1520 break;
1521 case 0x40:
1522 /* MediaGX CPU */
1523 cpu = CPU_M1SC;
1524 break;
1525 default:
1526 /* M2 and later CPUs are treated as M2. */
1527 cpu = CPU_M2;
1528
1529 /*
1530 * enable cpuid instruction.
1531 */
1532 ccr3 = read_cyrix_reg(CCR3);
1533 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1534 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1535 write_cyrix_reg(CCR3, ccr3);
1536
1537 do_cpuid(0, regs);
1538 cpu_high = regs[0]; /* eax */
1539 do_cpuid(1, regs);
1540 cpu_id = regs[0]; /* eax */
1541 cpu_feature = regs[3]; /* edx */
1542 break;
1543 }
1544 }
1545 } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1546 /*
1547 * There are BlueLightning CPUs that do not change
1548 * undefined flags by dividing 5 by 2. In this case,
1549 * the CPU identification routine in locore.s leaves
1550 * cpu_vendor null string and puts CPU_486 into the
1551 * cpu.
1552 */
1553 if (identblue() == IDENTBLUE_IBMCPU) {
1554 strcpy(cpu_vendor, "IBM");
1555 cpu_vendor_id = CPU_VENDOR_IBM;
1556 cpu = CPU_BLUE;
1557 return;
1558 }
1559 }
1560 #else
1561 /* XXX */
1562 cpu = CPU_CLAWHAMMER;
1563 #endif
1564 }
1565
1566 static u_int
find_cpu_vendor_id(void)1567 find_cpu_vendor_id(void)
1568 {
1569 int i;
1570
1571 for (i = 0; i < sizeof(cpu_vendors) / sizeof(cpu_vendors[0]); i++)
1572 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
1573 return (cpu_vendors[i].vendor_id);
1574 return (0);
1575 }
1576
1577 static void
print_AMD_assoc(int i)1578 print_AMD_assoc(int i)
1579 {
1580 if (i == 255)
1581 printf(", fully associative\n");
1582 else
1583 printf(", %d-way associative\n", i);
1584 }
1585
1586 static void
print_AMD_l2_assoc(int i)1587 print_AMD_l2_assoc(int i)
1588 {
1589 switch (i & 0x0f) {
1590 case 0: printf(", disabled/not present\n"); break;
1591 case 1: printf(", direct mapped\n"); break;
1592 case 2: printf(", 2-way associative\n"); break;
1593 case 4: printf(", 4-way associative\n"); break;
1594 case 6: printf(", 8-way associative\n"); break;
1595 case 8: printf(", 16-way associative\n"); break;
1596 case 15: printf(", fully associative\n"); break;
1597 default: printf(", reserved configuration\n"); break;
1598 }
1599 }
1600
1601 static void
print_AMD_info(void)1602 print_AMD_info(void)
1603 {
1604 #ifdef __i386__
1605 uint64_t amd_whcr;
1606 #endif
1607 u_int regs[4];
1608
1609 if (cpu_exthigh >= 0x80000005) {
1610 do_cpuid(0x80000005, regs);
1611 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
1612 print_AMD_assoc(regs[0] >> 24);
1613
1614 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
1615 print_AMD_assoc((regs[0] >> 8) & 0xff);
1616
1617 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
1618 print_AMD_assoc(regs[1] >> 24);
1619
1620 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
1621 print_AMD_assoc((regs[1] >> 8) & 0xff);
1622
1623 printf("L1 data cache: %d kbytes", regs[2] >> 24);
1624 printf(", %d bytes/line", regs[2] & 0xff);
1625 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1626 print_AMD_assoc((regs[2] >> 16) & 0xff);
1627
1628 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1629 printf(", %d bytes/line", regs[3] & 0xff);
1630 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1631 print_AMD_assoc((regs[3] >> 16) & 0xff);
1632 }
1633
1634 if (cpu_exthigh >= 0x80000006) {
1635 do_cpuid(0x80000006, regs);
1636 if ((regs[0] >> 16) != 0) {
1637 printf("L2 2MB data TLB: %d entries",
1638 (regs[0] >> 16) & 0xfff);
1639 print_AMD_l2_assoc(regs[0] >> 28);
1640 printf("L2 2MB instruction TLB: %d entries",
1641 regs[0] & 0xfff);
1642 print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1643 } else {
1644 printf("L2 2MB unified TLB: %d entries",
1645 regs[0] & 0xfff);
1646 print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1647 }
1648 if ((regs[1] >> 16) != 0) {
1649 printf("L2 4KB data TLB: %d entries",
1650 (regs[1] >> 16) & 0xfff);
1651 print_AMD_l2_assoc(regs[1] >> 28);
1652
1653 printf("L2 4KB instruction TLB: %d entries",
1654 (regs[1] >> 16) & 0xfff);
1655 print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1656 } else {
1657 printf("L2 4KB unified TLB: %d entries",
1658 (regs[1] >> 16) & 0xfff);
1659 print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1660 }
1661 printf("L2 unified cache: %d kbytes", regs[2] >> 16);
1662 printf(", %d bytes/line", regs[2] & 0xff);
1663 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1664 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
1665 }
1666
1667 #ifdef __i386__
1668 if (((cpu_id & 0xf00) == 0x500)
1669 && (((cpu_id & 0x0f0) > 0x80)
1670 || (((cpu_id & 0x0f0) == 0x80)
1671 && (cpu_id & 0x00f) > 0x07))) {
1672 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1673 amd_whcr = rdmsr(0xc0000082);
1674 if (!(amd_whcr & (0x3ff << 22))) {
1675 printf("Write Allocate Disable\n");
1676 } else {
1677 printf("Write Allocate Enable Limit: %dM bytes\n",
1678 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1679 printf("Write Allocate 15-16M bytes: %s\n",
1680 (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1681 }
1682 } else if (((cpu_id & 0xf00) == 0x500)
1683 && ((cpu_id & 0x0f0) > 0x50)) {
1684 /* K6, K6-2(old core) */
1685 amd_whcr = rdmsr(0xc0000082);
1686 if (!(amd_whcr & (0x7f << 1))) {
1687 printf("Write Allocate Disable\n");
1688 } else {
1689 printf("Write Allocate Enable Limit: %dM bytes\n",
1690 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1691 printf("Write Allocate 15-16M bytes: %s\n",
1692 (amd_whcr & 0x0001) ? "Enable" : "Disable");
1693 printf("Hardware Write Allocate Control: %s\n",
1694 (amd_whcr & 0x0100) ? "Enable" : "Disable");
1695 }
1696 }
1697 #endif
1698 /*
1699 * Opteron Rev E shows a bug as in very rare occasions a read memory
1700 * barrier is not performed as expected if it is followed by a
1701 * non-atomic read-modify-write instruction.
1702 * As long as that bug pops up very rarely (intensive machine usage
1703 * on other operating systems generally generates one unexplainable
1704 * crash any 2 months) and as long as a model specific fix would be
1705 * impratical at this stage, print out a warning string if the broken
1706 * model and family are identified.
1707 */
1708 if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
1709 CPUID_TO_MODEL(cpu_id) <= 0x3f)
1710 printf("WARNING: This architecture revision has known SMP "
1711 "hardware bugs which may cause random instability\n");
1712 }
1713
1714 static void
print_INTEL_info(void)1715 print_INTEL_info(void)
1716 {
1717 u_int regs[4];
1718 u_int rounds, regnum;
1719 u_int nwaycode, nway;
1720
1721 if (cpu_high >= 2) {
1722 rounds = 0;
1723 do {
1724 do_cpuid(0x2, regs);
1725 if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1726 break; /* we have a buggy CPU */
1727
1728 for (regnum = 0; regnum <= 3; ++regnum) {
1729 if (regs[regnum] & (1<<31))
1730 continue;
1731 if (regnum != 0)
1732 print_INTEL_TLB(regs[regnum] & 0xff);
1733 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
1734 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
1735 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
1736 }
1737 } while (--rounds > 0);
1738 }
1739
1740 if (cpu_exthigh >= 0x80000006) {
1741 do_cpuid(0x80000006, regs);
1742 nwaycode = (regs[2] >> 12) & 0x0f;
1743 if (nwaycode >= 0x02 && nwaycode <= 0x08)
1744 nway = 1 << (nwaycode / 2);
1745 else
1746 nway = 0;
1747 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n",
1748 (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
1749 }
1750 }
1751
1752 static void
print_INTEL_TLB(u_int data)1753 print_INTEL_TLB(u_int data)
1754 {
1755 switch (data) {
1756 case 0x0:
1757 case 0x40:
1758 default:
1759 break;
1760 case 0x1:
1761 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n");
1762 break;
1763 case 0x2:
1764 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n");
1765 break;
1766 case 0x3:
1767 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n");
1768 break;
1769 case 0x4:
1770 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n");
1771 break;
1772 case 0x6:
1773 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n");
1774 break;
1775 case 0x8:
1776 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n");
1777 break;
1778 case 0x9:
1779 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n");
1780 break;
1781 case 0xa:
1782 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n");
1783 break;
1784 case 0xb:
1785 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n");
1786 break;
1787 case 0xc:
1788 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n");
1789 break;
1790 case 0xd:
1791 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size");
1792 break;
1793 case 0xe:
1794 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n");
1795 break;
1796 case 0x1d:
1797 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n");
1798 break;
1799 case 0x21:
1800 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n");
1801 break;
1802 case 0x22:
1803 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1804 break;
1805 case 0x23:
1806 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1807 break;
1808 case 0x24:
1809 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n");
1810 break;
1811 case 0x25:
1812 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1813 break;
1814 case 0x29:
1815 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1816 break;
1817 case 0x2c:
1818 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n");
1819 break;
1820 case 0x30:
1821 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n");
1822 break;
1823 case 0x39: /* De-listed in SDM rev. 54 */
1824 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1825 break;
1826 case 0x3b: /* De-listed in SDM rev. 54 */
1827 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n");
1828 break;
1829 case 0x3c: /* De-listed in SDM rev. 54 */
1830 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1831 break;
1832 case 0x41:
1833 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n");
1834 break;
1835 case 0x42:
1836 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n");
1837 break;
1838 case 0x43:
1839 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n");
1840 break;
1841 case 0x44:
1842 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n");
1843 break;
1844 case 0x45:
1845 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n");
1846 break;
1847 case 0x46:
1848 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n");
1849 break;
1850 case 0x47:
1851 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n");
1852 break;
1853 case 0x48:
1854 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n");
1855 break;
1856 case 0x49:
1857 if (CPUID_TO_FAMILY(cpu_id) == 0xf &&
1858 CPUID_TO_MODEL(cpu_id) == 0x6)
1859 printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n");
1860 else
1861 printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size");
1862 break;
1863 case 0x4a:
1864 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n");
1865 break;
1866 case 0x4b:
1867 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n");
1868 break;
1869 case 0x4c:
1870 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n");
1871 break;
1872 case 0x4d:
1873 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n");
1874 break;
1875 case 0x4e:
1876 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n");
1877 break;
1878 case 0x4f:
1879 printf("Instruction TLB: 4 KByte pages, 32 entries\n");
1880 break;
1881 case 0x50:
1882 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n");
1883 break;
1884 case 0x51:
1885 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n");
1886 break;
1887 case 0x52:
1888 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n");
1889 break;
1890 case 0x55:
1891 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n");
1892 break;
1893 case 0x56:
1894 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n");
1895 break;
1896 case 0x57:
1897 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n");
1898 break;
1899 case 0x59:
1900 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n");
1901 break;
1902 case 0x5a:
1903 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n");
1904 break;
1905 case 0x5b:
1906 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n");
1907 break;
1908 case 0x5c:
1909 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n");
1910 break;
1911 case 0x5d:
1912 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n");
1913 break;
1914 case 0x60:
1915 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1916 break;
1917 case 0x61:
1918 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n");
1919 break;
1920 case 0x63:
1921 printf("Data TLB: 1 GByte pages, 4-way set associative, 4 entries\n");
1922 break;
1923 case 0x66:
1924 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1925 break;
1926 case 0x67:
1927 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1928 break;
1929 case 0x68:
1930 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n");
1931 break;
1932 case 0x6a:
1933 printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n");
1934 break;
1935 case 0x6b:
1936 printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n");
1937 break;
1938 case 0x6c:
1939 printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n");
1940 break;
1941 case 0x6d:
1942 printf("DTLB: 1 GByte pages, fully associative, 16 entries\n");
1943 break;
1944 case 0x70:
1945 printf("Trace cache: 12K-uops, 8-way set associative\n");
1946 break;
1947 case 0x71:
1948 printf("Trace cache: 16K-uops, 8-way set associative\n");
1949 break;
1950 case 0x72:
1951 printf("Trace cache: 32K-uops, 8-way set associative\n");
1952 break;
1953 case 0x76:
1954 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n");
1955 break;
1956 case 0x78:
1957 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n");
1958 break;
1959 case 0x79:
1960 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1961 break;
1962 case 0x7a:
1963 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1964 break;
1965 case 0x7b:
1966 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1967 break;
1968 case 0x7c:
1969 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1970 break;
1971 case 0x7d:
1972 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n");
1973 break;
1974 case 0x7f:
1975 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n");
1976 break;
1977 case 0x80:
1978 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n");
1979 break;
1980 case 0x82:
1981 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n");
1982 break;
1983 case 0x83:
1984 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n");
1985 break;
1986 case 0x84:
1987 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n");
1988 break;
1989 case 0x85:
1990 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n");
1991 break;
1992 case 0x86:
1993 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n");
1994 break;
1995 case 0x87:
1996 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n");
1997 break;
1998 case 0xa0:
1999 printf("DTLB: 4k pages, fully associative, 32 entries\n");
2000 break;
2001 case 0xb0:
2002 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2003 break;
2004 case 0xb1:
2005 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n");
2006 break;
2007 case 0xb2:
2008 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n");
2009 break;
2010 case 0xb3:
2011 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2012 break;
2013 case 0xb4:
2014 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n");
2015 break;
2016 case 0xb5:
2017 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n");
2018 break;
2019 case 0xb6:
2020 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n");
2021 break;
2022 case 0xba:
2023 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n");
2024 break;
2025 case 0xc0:
2026 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n");
2027 break;
2028 case 0xc1:
2029 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n");
2030 break;
2031 case 0xc2:
2032 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n");
2033 break;
2034 case 0xc3:
2035 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n");
2036 break;
2037 case 0xca:
2038 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n");
2039 break;
2040 case 0xd0:
2041 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n");
2042 break;
2043 case 0xd1:
2044 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n");
2045 break;
2046 case 0xd2:
2047 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n");
2048 break;
2049 case 0xd6:
2050 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n");
2051 break;
2052 case 0xd7:
2053 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n");
2054 break;
2055 case 0xd8:
2056 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n");
2057 break;
2058 case 0xdc:
2059 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n");
2060 break;
2061 case 0xdd:
2062 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n");
2063 break;
2064 case 0xde:
2065 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n");
2066 break;
2067 case 0xe2:
2068 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n");
2069 break;
2070 case 0xe3:
2071 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n");
2072 break;
2073 case 0xe4:
2074 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n");
2075 break;
2076 case 0xea:
2077 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n");
2078 break;
2079 case 0xeb:
2080 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n");
2081 break;
2082 case 0xec:
2083 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n");
2084 break;
2085 case 0xf0:
2086 printf("64-Byte prefetching\n");
2087 break;
2088 case 0xf1:
2089 printf("128-Byte prefetching\n");
2090 break;
2091 }
2092 }
2093
2094 static void
print_svm_info(void)2095 print_svm_info(void)
2096 {
2097 u_int features, regs[4];
2098 uint64_t msr;
2099 int comma;
2100
2101 printf("\n SVM: ");
2102 do_cpuid(0x8000000A, regs);
2103 features = regs[3];
2104
2105 msr = rdmsr(MSR_VM_CR);
2106 if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS)
2107 printf("(disabled in BIOS) ");
2108
2109 if (!bootverbose) {
2110 comma = 0;
2111 if (features & (1 << 0)) {
2112 printf("%sNP", comma ? "," : "");
2113 comma = 1;
2114 }
2115 if (features & (1 << 3)) {
2116 printf("%sNRIP", comma ? "," : "");
2117 comma = 1;
2118 }
2119 if (features & (1 << 5)) {
2120 printf("%sVClean", comma ? "," : "");
2121 comma = 1;
2122 }
2123 if (features & (1 << 6)) {
2124 printf("%sAFlush", comma ? "," : "");
2125 comma = 1;
2126 }
2127 if (features & (1 << 7)) {
2128 printf("%sDAssist", comma ? "," : "");
2129 comma = 1;
2130 }
2131 printf("%sNAsids=%d", comma ? "," : "", regs[1]);
2132 return;
2133 }
2134
2135 printf("Features=0x%b", features,
2136 "\020"
2137 "\001NP" /* Nested paging */
2138 "\002LbrVirt" /* LBR virtualization */
2139 "\003SVML" /* SVM lock */
2140 "\004NRIPS" /* NRIP save */
2141 "\005TscRateMsr" /* MSR based TSC rate control */
2142 "\006VmcbClean" /* VMCB clean bits */
2143 "\007FlushByAsid" /* Flush by ASID */
2144 "\010DecodeAssist" /* Decode assist */
2145 "\011<b8>"
2146 "\012<b9>"
2147 "\013PauseFilter" /* PAUSE intercept filter */
2148 "\014<b11>"
2149 "\015PauseFilterThreshold" /* PAUSE filter threshold */
2150 "\016AVIC" /* virtual interrupt controller */
2151 );
2152 printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]);
2153 }
2154
2155 #ifdef __i386__
2156 static void
print_transmeta_info(void)2157 print_transmeta_info(void)
2158 {
2159 u_int regs[4], nreg = 0;
2160
2161 do_cpuid(0x80860000, regs);
2162 nreg = regs[0];
2163 if (nreg >= 0x80860001) {
2164 do_cpuid(0x80860001, regs);
2165 printf(" Processor revision %u.%u.%u.%u\n",
2166 (regs[1] >> 24) & 0xff,
2167 (regs[1] >> 16) & 0xff,
2168 (regs[1] >> 8) & 0xff,
2169 regs[1] & 0xff);
2170 }
2171 if (nreg >= 0x80860002) {
2172 do_cpuid(0x80860002, regs);
2173 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n",
2174 (regs[1] >> 24) & 0xff,
2175 (regs[1] >> 16) & 0xff,
2176 (regs[1] >> 8) & 0xff,
2177 regs[1] & 0xff,
2178 regs[2]);
2179 }
2180 if (nreg >= 0x80860006) {
2181 char info[65];
2182 do_cpuid(0x80860003, (u_int*) &info[0]);
2183 do_cpuid(0x80860004, (u_int*) &info[16]);
2184 do_cpuid(0x80860005, (u_int*) &info[32]);
2185 do_cpuid(0x80860006, (u_int*) &info[48]);
2186 info[64] = 0;
2187 printf(" %s\n", info);
2188 }
2189 }
2190 #endif
2191
2192 static void
print_via_padlock_info(void)2193 print_via_padlock_info(void)
2194 {
2195 u_int regs[4];
2196
2197 do_cpuid(0xc0000001, regs);
2198 printf("\n VIA Padlock Features=0x%b", regs[3],
2199 "\020"
2200 "\003RNG" /* RNG */
2201 "\007AES" /* ACE */
2202 "\011AES-CTR" /* ACE2 */
2203 "\013SHA1,SHA256" /* PHE */
2204 "\015RSA" /* PMM */
2205 );
2206 }
2207
2208 static uint32_t
vmx_settable(uint64_t basic,int msr,int true_msr)2209 vmx_settable(uint64_t basic, int msr, int true_msr)
2210 {
2211 uint64_t val;
2212
2213 if (basic & (1ULL << 55))
2214 val = rdmsr(true_msr);
2215 else
2216 val = rdmsr(msr);
2217
2218 /* Just report the controls that can be set to 1. */
2219 return (val >> 32);
2220 }
2221
2222 static void
print_vmx_info(void)2223 print_vmx_info(void)
2224 {
2225 uint64_t basic, msr;
2226 uint32_t entry, exit, mask, pin, proc, proc2;
2227 int comma;
2228
2229 printf("\n VT-x: ");
2230 msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
2231 if (!(msr & IA32_FEATURE_CONTROL_VMX_EN))
2232 printf("(disabled in BIOS) ");
2233 basic = rdmsr(MSR_VMX_BASIC);
2234 pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS,
2235 MSR_VMX_TRUE_PINBASED_CTLS);
2236 proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS,
2237 MSR_VMX_TRUE_PROCBASED_CTLS);
2238 if (proc & PROCBASED_SECONDARY_CONTROLS)
2239 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2,
2240 MSR_VMX_PROCBASED_CTLS2);
2241 else
2242 proc2 = 0;
2243 exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS);
2244 entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS);
2245
2246 if (!bootverbose) {
2247 comma = 0;
2248 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT &&
2249 entry & VM_ENTRY_LOAD_PAT) {
2250 printf("%sPAT", comma ? "," : "");
2251 comma = 1;
2252 }
2253 if (proc & PROCBASED_HLT_EXITING) {
2254 printf("%sHLT", comma ? "," : "");
2255 comma = 1;
2256 }
2257 if (proc & PROCBASED_MTF) {
2258 printf("%sMTF", comma ? "," : "");
2259 comma = 1;
2260 }
2261 if (proc & PROCBASED_PAUSE_EXITING) {
2262 printf("%sPAUSE", comma ? "," : "");
2263 comma = 1;
2264 }
2265 if (proc2 & PROCBASED2_ENABLE_EPT) {
2266 printf("%sEPT", comma ? "," : "");
2267 comma = 1;
2268 }
2269 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) {
2270 printf("%sUG", comma ? "," : "");
2271 comma = 1;
2272 }
2273 if (proc2 & PROCBASED2_ENABLE_VPID) {
2274 printf("%sVPID", comma ? "," : "");
2275 comma = 1;
2276 }
2277 if (proc & PROCBASED_USE_TPR_SHADOW &&
2278 proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES &&
2279 proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE &&
2280 proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION &&
2281 proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) {
2282 printf("%sVID", comma ? "," : "");
2283 comma = 1;
2284 if (pin & PINBASED_POSTED_INTERRUPT)
2285 printf(",PostIntr");
2286 }
2287 return;
2288 }
2289
2290 mask = basic >> 32;
2291 printf("Basic Features=0x%b", mask,
2292 "\020"
2293 "\02132PA" /* 32-bit physical addresses */
2294 "\022SMM" /* SMM dual-monitor */
2295 "\027INS/OUTS" /* VM-exit info for INS and OUTS */
2296 "\030TRUE" /* TRUE_CTLS MSRs */
2297 );
2298 printf("\n Pin-Based Controls=0x%b", pin,
2299 "\020"
2300 "\001ExtINT" /* External-interrupt exiting */
2301 "\004NMI" /* NMI exiting */
2302 "\006VNMI" /* Virtual NMIs */
2303 "\007PreTmr" /* Activate VMX-preemption timer */
2304 "\010PostIntr" /* Process posted interrupts */
2305 );
2306 printf("\n Primary Processor Controls=0x%b", proc,
2307 "\020"
2308 "\003INTWIN" /* Interrupt-window exiting */
2309 "\004TSCOff" /* Use TSC offsetting */
2310 "\010HLT" /* HLT exiting */
2311 "\012INVLPG" /* INVLPG exiting */
2312 "\013MWAIT" /* MWAIT exiting */
2313 "\014RDPMC" /* RDPMC exiting */
2314 "\015RDTSC" /* RDTSC exiting */
2315 "\020CR3-LD" /* CR3-load exiting */
2316 "\021CR3-ST" /* CR3-store exiting */
2317 "\024CR8-LD" /* CR8-load exiting */
2318 "\025CR8-ST" /* CR8-store exiting */
2319 "\026TPR" /* Use TPR shadow */
2320 "\027NMIWIN" /* NMI-window exiting */
2321 "\030MOV-DR" /* MOV-DR exiting */
2322 "\031IO" /* Unconditional I/O exiting */
2323 "\032IOmap" /* Use I/O bitmaps */
2324 "\034MTF" /* Monitor trap flag */
2325 "\035MSRmap" /* Use MSR bitmaps */
2326 "\036MONITOR" /* MONITOR exiting */
2327 "\037PAUSE" /* PAUSE exiting */
2328 );
2329 if (proc & PROCBASED_SECONDARY_CONTROLS)
2330 printf("\n Secondary Processor Controls=0x%b", proc2,
2331 "\020"
2332 "\001APIC" /* Virtualize APIC accesses */
2333 "\002EPT" /* Enable EPT */
2334 "\003DT" /* Descriptor-table exiting */
2335 "\004RDTSCP" /* Enable RDTSCP */
2336 "\005x2APIC" /* Virtualize x2APIC mode */
2337 "\006VPID" /* Enable VPID */
2338 "\007WBINVD" /* WBINVD exiting */
2339 "\010UG" /* Unrestricted guest */
2340 "\011APIC-reg" /* APIC-register virtualization */
2341 "\012VID" /* Virtual-interrupt delivery */
2342 "\013PAUSE-loop" /* PAUSE-loop exiting */
2343 "\014RDRAND" /* RDRAND exiting */
2344 "\015INVPCID" /* Enable INVPCID */
2345 "\016VMFUNC" /* Enable VM functions */
2346 "\017VMCS" /* VMCS shadowing */
2347 "\020EPT#VE" /* EPT-violation #VE */
2348 "\021XSAVES" /* Enable XSAVES/XRSTORS */
2349 );
2350 printf("\n Exit Controls=0x%b", mask,
2351 "\020"
2352 "\003DR" /* Save debug controls */
2353 /* Ignore Host address-space size */
2354 "\015PERF" /* Load MSR_PERF_GLOBAL_CTRL */
2355 "\020AckInt" /* Acknowledge interrupt on exit */
2356 "\023PAT-SV" /* Save MSR_PAT */
2357 "\024PAT-LD" /* Load MSR_PAT */
2358 "\025EFER-SV" /* Save MSR_EFER */
2359 "\026EFER-LD" /* Load MSR_EFER */
2360 "\027PTMR-SV" /* Save VMX-preemption timer value */
2361 );
2362 printf("\n Entry Controls=0x%b", mask,
2363 "\020"
2364 "\003DR" /* Save debug controls */
2365 /* Ignore IA-32e mode guest */
2366 /* Ignore Entry to SMM */
2367 /* Ignore Deactivate dual-monitor treatment */
2368 "\016PERF" /* Load MSR_PERF_GLOBAL_CTRL */
2369 "\017PAT" /* Load MSR_PAT */
2370 "\020EFER" /* Load MSR_EFER */
2371 );
2372 if (proc & PROCBASED_SECONDARY_CONTROLS &&
2373 (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) {
2374 msr = rdmsr(MSR_VMX_EPT_VPID_CAP);
2375 mask = msr;
2376 printf("\n EPT Features=0x%b", mask,
2377 "\020"
2378 "\001XO" /* Execute-only translations */
2379 "\007PW4" /* Page-walk length of 4 */
2380 "\011UC" /* EPT paging-structure mem can be UC */
2381 "\017WB" /* EPT paging-structure mem can be WB */
2382 "\0212M" /* EPT PDE can map a 2-Mbyte page */
2383 "\0221G" /* EPT PDPTE can map a 1-Gbyte page */
2384 "\025INVEPT" /* INVEPT is supported */
2385 "\026AD" /* Accessed and dirty flags for EPT */
2386 "\032single" /* INVEPT single-context type */
2387 "\033all" /* INVEPT all-context type */
2388 );
2389 mask = msr >> 32;
2390 printf("\n VPID Features=0x%b", mask,
2391 "\020"
2392 "\001INVVPID" /* INVVPID is supported */
2393 "\011individual" /* INVVPID individual-address type */
2394 "\012single" /* INVVPID single-context type */
2395 "\013all" /* INVVPID all-context type */
2396 /* INVVPID single-context-retaining-globals type */
2397 "\014single-globals"
2398 );
2399 }
2400 }
2401
2402 static void
print_hypervisor_info(void)2403 print_hypervisor_info(void)
2404 {
2405
2406 if (*hv_vendor)
2407 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor);
2408 }
2409