1 /* Tracing support for CGEN-based simulators.
2 Copyright (C) 1996-2024 Free Software Foundation, Inc.
3 Contributed by Cygnus Support.
4
5 This file is part of GDB, the GNU debugger.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20 /* This must come before any other includes. */
21 #include "defs.h"
22
23 #include <errno.h>
24 #include <stdarg.h>
25 #include <stdlib.h>
26
27 #include "bfd.h"
28 #include "diagnostics.h"
29 #include "dis-asm.h"
30
31 #include "sim-main.h"
32 #include "sim-fpu.h"
33 #include "sim/callback.h"
34
35 #ifndef SIZE_INSTRUCTION
36 #define SIZE_INSTRUCTION 16
37 #endif
38
39 #ifndef SIZE_LOCATION
40 #define SIZE_LOCATION 20
41 #endif
42
43 #ifndef SIZE_PC
44 #define SIZE_PC 6
45 #endif
46
47 #ifndef SIZE_LINE_NUMBER
48 #define SIZE_LINE_NUMBER 4
49 #endif
50
51 #ifndef SIZE_CYCLE_COUNT
52 #define SIZE_CYCLE_COUNT 2
53 #endif
54
55 #ifndef SIZE_TOTAL_CYCLE_COUNT
56 #define SIZE_TOTAL_CYCLE_COUNT 9
57 #endif
58
59 #ifndef SIZE_TRACE_BUF
60 #define SIZE_TRACE_BUF 1024
61 #endif
62
63 /* Text is queued in TRACE_BUF because we want to output the insn's cycle
64 count first but that isn't known until after the insn has executed.
65 This also handles the queueing of trace results, TRACE_RESULT may be
66 called multiple times for one insn. */
67 static char trace_buf[SIZE_TRACE_BUF];
68 /* If NULL, output to stdout directly. */
69 static char *bufptr;
70
71 /* Non-zero if this is the first insn in a set of parallel insns. */
72 static int first_insn_p;
73
74 /* For communication between cgen_trace_insn and cgen_trace_result. */
75 static int printed_result_p;
76
77 /* Insn and its extracted fields.
78 Set by cgen_trace_insn, used by cgen_trace_insn_fini.
79 ??? Move to SIM_CPU to support heterogeneous multi-cpu case. */
80 static const struct cgen_insn *current_insn;
81 static const struct argbuf *current_abuf;
82
83 void
cgen_trace_insn_init(SIM_CPU * cpu,int first_p)84 cgen_trace_insn_init (SIM_CPU *cpu, int first_p)
85 {
86 bufptr = trace_buf;
87 *bufptr = 0;
88 first_insn_p = first_p;
89
90 /* Set to NULL so cgen_trace_insn_fini can know if cgen_trace_insn was
91 called. */
92 current_insn = NULL;
93 current_abuf = NULL;
94 }
95
96 void
cgen_trace_insn_fini(SIM_CPU * cpu,const struct argbuf * abuf,int last_p)97 cgen_trace_insn_fini (SIM_CPU *cpu, const struct argbuf *abuf, int last_p)
98 {
99 SIM_DESC sd = CPU_STATE (cpu);
100
101 /* Was insn traced? It might not be if trace ranges are in effect. */
102 if (current_insn == NULL)
103 return;
104
105 /* The first thing printed is current and total cycle counts. */
106
107 if (PROFILE_MODEL_P (cpu)
108 && ARGBUF_PROFILE_P (current_abuf))
109 {
110 unsigned long total = PROFILE_MODEL_TOTAL_CYCLES (CPU_PROFILE_DATA (cpu));
111 unsigned long this_insn = PROFILE_MODEL_CUR_INSN_CYCLES (CPU_PROFILE_DATA (cpu));
112
113 if (last_p)
114 {
115 trace_printf (sd, cpu, "%-*ld %-*ld ",
116 SIZE_CYCLE_COUNT, this_insn,
117 SIZE_TOTAL_CYCLE_COUNT, total);
118 }
119 else
120 {
121 trace_printf (sd, cpu, "%-*ld %-*s ",
122 SIZE_CYCLE_COUNT, this_insn,
123 SIZE_TOTAL_CYCLE_COUNT, "---");
124 }
125 }
126
127 /* Print the disassembled insn. */
128
129 trace_printf (sd, cpu, "%s", TRACE_PREFIX (CPU_TRACE_DATA (cpu)));
130
131 #if 0
132 /* Print insn results. */
133 {
134 const CGEN_OPINST *opinst = CGEN_INSN_OPERANDS (current_insn);
135
136 if (opinst)
137 {
138 int i;
139 int indices[MAX_OPERAND_INSTANCES];
140
141 /* Fetch the operands used by the insn. */
142 /* FIXME: Add fn ptr to CGEN_CPU_DESC. */
143 CGEN_SYM (get_insn_operands) (CPU_CPU_DESC (cpu), current_insn,
144 0, CGEN_FIELDS_BITSIZE (&insn_fields),
145 indices);
146
147 for (i = 0;
148 CGEN_OPINST_TYPE (opinst) != CGEN_OPINST_END;
149 ++i, ++opinst)
150 {
151 if (CGEN_OPINST_TYPE (opinst) == CGEN_OPINST_OUTPUT)
152 cgen_trace_result (cpu, current_insn, opinst, indices[i]);
153 }
154 }
155 }
156 #endif
157
158 /* Print anything else requested. */
159
160 if (*trace_buf)
161 trace_printf (sd, cpu, " %s\n", trace_buf);
162 else
163 trace_printf (sd, cpu, "\n");
164 }
165
166 void
cgen_trace_insn(SIM_CPU * cpu,const struct cgen_insn * opcode,const struct argbuf * abuf,IADDR pc)167 cgen_trace_insn (SIM_CPU *cpu, const struct cgen_insn *opcode,
168 const struct argbuf *abuf, IADDR pc)
169 {
170 char disasm_buf[50];
171
172 printed_result_p = 0;
173 current_insn = opcode;
174 current_abuf = abuf;
175
176 if (CGEN_INSN_VIRTUAL_P (opcode))
177 {
178 trace_prefix (CPU_STATE (cpu), cpu, NULL_CIA, pc, 0,
179 NULL, 0, "%s", CGEN_INSN_NAME (opcode));
180 return;
181 }
182
183 CPU_DISASSEMBLER (cpu) (cpu, opcode, abuf, pc, disasm_buf);
184 trace_prefix (CPU_STATE (cpu), cpu, NULL_CIA, pc, TRACE_LINENUM_P (cpu),
185 NULL, 0,
186 "%s%-*s",
187 first_insn_p ? " " : "|",
188 SIZE_INSTRUCTION, disasm_buf);
189 }
190
191 void
cgen_trace_extract(SIM_CPU * cpu,IADDR pc,const char * name,...)192 cgen_trace_extract (SIM_CPU *cpu, IADDR pc, const char *name, ...)
193 {
194 va_list args;
195 int printed_one_p = 0;
196 const char *fmt;
197
198 va_start (args, name);
199
200 trace_printf (CPU_STATE (cpu), cpu, "Extract: 0x%.*lx: %s ",
201 SIZE_PC, (unsigned long) pc, name);
202
203 do {
204 int type,ival;
205
206 fmt = va_arg (args, const char *);
207
208 if (fmt)
209 {
210 if (printed_one_p)
211 trace_printf (CPU_STATE (cpu), cpu, ", ");
212 printed_one_p = 1;
213 type = va_arg (args, int);
214 switch (type)
215 {
216 case 'x' :
217 ival = va_arg (args, int);
218 DIAGNOSTIC_PUSH
219 DIAGNOSTIC_IGNORE_FORMAT_NONLITERAL
220 trace_printf (CPU_STATE (cpu), cpu, fmt, ival);
221 DIAGNOSTIC_POP
222 break;
223 default :
224 abort ();
225 }
226 }
227 } while (fmt);
228
229 va_end (args);
230 trace_printf (CPU_STATE (cpu), cpu, "\n");
231 }
232
233 void
cgen_trace_result(SIM_CPU * cpu,const char * name,int type,...)234 cgen_trace_result (SIM_CPU *cpu, const char *name, int type, ...)
235 {
236 va_list args;
237
238 va_start (args, type);
239 if (printed_result_p)
240 cgen_trace_printf (cpu, ", ");
241
242 switch (type)
243 {
244 case 'x' :
245 default :
246 cgen_trace_printf (cpu, "%s <- 0x%x", name, va_arg (args, int));
247 break;
248 case 'f':
249 {
250 DI di;
251 sim_fpu f;
252
253 /* this is separated from previous line for sunos cc */
254 di = va_arg (args, DI);
255 sim_fpu_64to (&f, di);
256
257 cgen_trace_printf (cpu, "%s <- ", name);
258 sim_fpu_printn_fpu (&f, (sim_fpu_print_func *) cgen_trace_printf, 4, cpu);
259 break;
260 }
261 case 'D' :
262 {
263 DI di;
264 /* this is separated from previous line for sunos cc */
265 di = va_arg (args, DI);
266 cgen_trace_printf (cpu, "%s <- 0x%x%08x", name,
267 GETHIDI(di), GETLODI (di));
268 break;
269 }
270 }
271
272 printed_result_p = 1;
273 va_end (args);
274 }
275
276 /* Print trace output to BUFPTR if active, otherwise print normally.
277 This is only for tracing semantic code. */
278
279 void
cgen_trace_printf(SIM_CPU * cpu,const char * fmt,...)280 cgen_trace_printf (SIM_CPU *cpu, const char *fmt, ...)
281 {
282 va_list args;
283
284 va_start (args, fmt);
285
286 if (bufptr == NULL)
287 {
288 if (TRACE_FILE (CPU_TRACE_DATA (cpu)) == NULL)
289 (* STATE_CALLBACK (CPU_STATE (cpu))->evprintf_filtered)
290 (STATE_CALLBACK (CPU_STATE (cpu)), fmt, args);
291 else
292 vfprintf (TRACE_FILE (CPU_TRACE_DATA (cpu)), fmt, args);
293 }
294 else
295 {
296 vsprintf (bufptr, fmt, args);
297 bufptr += strlen (bufptr);
298 /* ??? Need version of SIM_ASSERT that is always enabled. */
299 if (bufptr - trace_buf > SIZE_TRACE_BUF)
300 abort ();
301 }
302
303 va_end (args);
304 }
305
306 /* Disassembly support. */
307
308 /* sprintf to a "stream" */
309
310 int
sim_disasm_sprintf(SFILE * f,const char * format,...)311 sim_disasm_sprintf (SFILE *f, const char *format, ...)
312 {
313 int n;
314 va_list args;
315
316 va_start (args, format);
317 vsprintf (f->current, format, args);
318 f->current += n = strlen (f->current);
319 va_end (args);
320 return n;
321 }
322
323 /* sprintf to a "stream" with styling. */
324
325 int
sim_disasm_styled_sprintf(SFILE * f,enum disassembler_style style,const char * format,...)326 sim_disasm_styled_sprintf (SFILE *f, enum disassembler_style style,
327 const char *format, ...)
328 {
329 int n;
330 va_list args;
331
332 va_start (args, format);
333 vsprintf (f->current, format, args);
334 f->current += n = strlen (f->current);
335 va_end (args);
336 return n;
337 }
338
339 /* Memory read support for an opcodes disassembler. */
340
341 int
sim_disasm_read_memory(bfd_vma memaddr,bfd_byte * myaddr,unsigned int length,struct disassemble_info * info)342 sim_disasm_read_memory (bfd_vma memaddr, bfd_byte *myaddr, unsigned int length,
343 struct disassemble_info *info)
344 {
345 SIM_CPU *cpu = (SIM_CPU *) info->application_data;
346 SIM_DESC sd = CPU_STATE (cpu);
347 unsigned length_read;
348
349 length_read = sim_core_read_buffer (sd, cpu, read_map, myaddr, memaddr,
350 length);
351 if (length_read != length)
352 return EIO;
353 return 0;
354 }
355
356 /* Memory error support for an opcodes disassembler. */
357
358 void
sim_disasm_perror_memory(int status,bfd_vma memaddr,struct disassemble_info * info)359 sim_disasm_perror_memory (int status, bfd_vma memaddr,
360 struct disassemble_info *info)
361 {
362 if (status != EIO)
363 /* Can't happen. */
364 info->fprintf_func (info->stream, "Unknown error %d.", status);
365 else
366 /* Actually, address between memaddr and memaddr + len was
367 out of bounds. */
368 info->fprintf_func (info->stream,
369 "Address 0x%" PRIx64 " is out of bounds.",
370 (uint64_t) memaddr);
371 }
372
373 /* Disassemble using the CGEN opcode table.
374 ??? While executing an instruction, the insn has been decoded and all its
375 fields have been extracted. It is certainly possible to do the disassembly
376 with that data. This seems simpler, but maybe in the future the already
377 extracted fields will be used. */
378
379 void
sim_cgen_disassemble_insn(SIM_CPU * cpu,const CGEN_INSN * insn,const ARGBUF * abuf,IADDR pc,char * buf)380 sim_cgen_disassemble_insn (SIM_CPU *cpu, const CGEN_INSN *insn,
381 const ARGBUF *abuf, IADDR pc, char *buf)
382 {
383 unsigned int length;
384 unsigned int base_length;
385 unsigned long insn_value;
386 struct disassemble_info disasm_info;
387 SFILE sfile;
388 union {
389 uint8_t bytes[CGEN_MAX_INSN_SIZE];
390 uint16_t shorts[8];
391 uint32_t words[4];
392 } insn_buf;
393 SIM_DESC sd = CPU_STATE (cpu);
394 CGEN_CPU_DESC cd = CPU_CPU_DESC (cpu);
395 CGEN_EXTRACT_INFO ex_info;
396 CGEN_FIELDS *fields = alloca (CGEN_CPU_SIZEOF_FIELDS (cd));
397 int insn_bit_length = CGEN_INSN_BITSIZE (insn);
398 int insn_length = insn_bit_length / 8;
399
400 sfile.buffer = sfile.current = buf;
401 INIT_DISASSEMBLE_INFO (disasm_info, (FILE *) &sfile,
402 (fprintf_ftype) sim_disasm_sprintf,
403 (fprintf_styled_ftype) sim_disasm_styled_sprintf);
404 disasm_info.endian =
405 (bfd_big_endian (STATE_PROG_BFD (sd)) ? BFD_ENDIAN_BIG
406 : bfd_little_endian (STATE_PROG_BFD (sd)) ? BFD_ENDIAN_LITTLE
407 : BFD_ENDIAN_UNKNOWN);
408
409 length = sim_core_read_buffer (sd, cpu, read_map, &insn_buf, pc,
410 insn_length);
411
412 if (length != insn_length)
413 {
414 sim_io_error (sd, "unable to read address %" PRIxTA, pc);
415 }
416
417 /* If the entire insn will fit into an integer, then do it. Otherwise, just
418 use the bits of the base_insn. */
419 if (insn_bit_length <= 32)
420 base_length = insn_bit_length;
421 else
422 base_length = min (cd->base_insn_bitsize, insn_bit_length);
423 switch (base_length)
424 {
425 case 0 : return; /* fake insn, typically "compile" (aka "invalid") */
426 case 8 : insn_value = insn_buf.bytes[0]; break;
427 case 16 : insn_value = T2H_2 (insn_buf.shorts[0]); break;
428 case 32 : insn_value = T2H_4 (insn_buf.words[0]); break;
429 default: abort ();
430 }
431
432 disasm_info.buffer_vma = pc;
433 disasm_info.buffer = insn_buf.bytes;
434 disasm_info.buffer_length = length;
435
436 ex_info.dis_info = &disasm_info;
437 ex_info.valid = (1 << length) - 1;
438 ex_info.insn_bytes = insn_buf.bytes;
439
440 length = (*CGEN_EXTRACT_FN (cd, insn)) (cd, insn, &ex_info, insn_value, fields, pc);
441 /* Result of extract fn is in bits. */
442 /* ??? This assumes that each instruction has a fixed length (and thus
443 for insns with multiple versions of variable lengths they would each
444 have their own table entry). */
445 if (length == insn_bit_length)
446 {
447 (*CGEN_PRINT_FN (cd, insn)) (cd, &disasm_info, insn, fields, pc, length);
448 }
449 else
450 {
451 /* This shouldn't happen, but aborting is too drastic. */
452 strcpy (buf, "***unknown***");
453 }
454 }
455