1 /*
2  * Copyright 2010 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  *
23  * Authors:
24  *     Alex Deucher <alexander.deucher@amd.com>
25  */
26 
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD: stable/9/sys/dev/drm2/radeon/cayman_blit_shaders.c 254885 2013-08-25 19:37:15Z dumbbell $");
29 
30 #include <dev/drm2/drmP.h>
31 
32 /*
33  * evergreen cards need to use the 3D engine to blit data which requires
34  * quite a bit of hw state setup.  Rather than pull the whole 3D driver
35  * (which normally generates the 3D state) into the DRM, we opt to use
36  * statically generated state tables.  The regsiter state and shaders
37  * were hand generated to support blitting functionality.  See the 3D
38  * driver or documentation for descriptions of the registers and
39  * shader instructions.
40  */
41 
42 const u32 cayman_default_state[] =
43 {
44 	0xc0066900,
45 	0x00000000,
46 	0x00000060, /* DB_RENDER_CONTROL */
47 	0x00000000, /* DB_COUNT_CONTROL */
48 	0x00000000, /* DB_DEPTH_VIEW */
49 	0x0000002a, /* DB_RENDER_OVERRIDE */
50 	0x00000000, /* DB_RENDER_OVERRIDE2 */
51 	0x00000000, /* DB_HTILE_DATA_BASE */
52 
53 	0xc0026900,
54 	0x0000000a,
55 	0x00000000, /* DB_STENCIL_CLEAR */
56 	0x00000000, /* DB_DEPTH_CLEAR */
57 
58 	0xc0036900,
59 	0x0000000f,
60 	0x00000000, /* DB_DEPTH_INFO */
61 	0x00000000, /* DB_Z_INFO */
62 	0x00000000, /* DB_STENCIL_INFO */
63 
64 	0xc0016900,
65 	0x00000080,
66 	0x00000000, /* PA_SC_WINDOW_OFFSET */
67 
68 	0xc00d6900,
69 	0x00000083,
70 	0x0000ffff, /* PA_SC_CLIPRECT_RULE */
71 	0x00000000, /* PA_SC_CLIPRECT_0_TL */
72 	0x20002000, /* PA_SC_CLIPRECT_0_BR */
73 	0x00000000,
74 	0x20002000,
75 	0x00000000,
76 	0x20002000,
77 	0x00000000,
78 	0x20002000,
79 	0xaaaaaaaa, /* PA_SC_EDGERULE */
80 	0x00000000, /* PA_SU_HARDWARE_SCREEN_OFFSET */
81 	0x0000000f, /* CB_TARGET_MASK */
82 	0x0000000f, /* CB_SHADER_MASK */
83 
84 	0xc0226900,
85 	0x00000094,
86 	0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */
87 	0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */
88 	0x80000000,
89 	0x20002000,
90 	0x80000000,
91 	0x20002000,
92 	0x80000000,
93 	0x20002000,
94 	0x80000000,
95 	0x20002000,
96 	0x80000000,
97 	0x20002000,
98 	0x80000000,
99 	0x20002000,
100 	0x80000000,
101 	0x20002000,
102 	0x80000000,
103 	0x20002000,
104 	0x80000000,
105 	0x20002000,
106 	0x80000000,
107 	0x20002000,
108 	0x80000000,
109 	0x20002000,
110 	0x80000000,
111 	0x20002000,
112 	0x80000000,
113 	0x20002000,
114 	0x80000000,
115 	0x20002000,
116 	0x80000000,
117 	0x20002000,
118 	0x00000000, /* PA_SC_VPORT_ZMIN_0 */
119 	0x3f800000, /* PA_SC_VPORT_ZMAX_0 */
120 
121 	0xc0016900,
122 	0x000000d4,
123 	0x00000000, /* SX_MISC */
124 
125 	0xc0026900,
126 	0x000000d9,
127 	0x00000000, /* CP_RINGID */
128 	0x00000000, /* CP_VMID */
129 
130 	0xc0096900,
131 	0x00000100,
132 	0x00ffffff, /* VGT_MAX_VTX_INDX */
133 	0x00000000, /* VGT_MIN_VTX_INDX */
134 	0x00000000, /* VGT_INDX_OFFSET */
135 	0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */
136 	0x00000000, /* SX_ALPHA_TEST_CONTROL */
137 	0x00000000, /* CB_BLEND_RED */
138 	0x00000000, /* CB_BLEND_GREEN */
139 	0x00000000, /* CB_BLEND_BLUE */
140 	0x00000000, /* CB_BLEND_ALPHA */
141 
142 	0xc0016900,
143 	0x00000187,
144 	0x00000100, /* SPI_VS_OUT_ID_0 */
145 
146 	0xc0026900,
147 	0x00000191,
148 	0x00000100, /* SPI_PS_INPUT_CNTL_0 */
149 	0x00000101, /* SPI_PS_INPUT_CNTL_1 */
150 
151 	0xc0016900,
152 	0x000001b1,
153 	0x00000000, /* SPI_VS_OUT_CONFIG */
154 
155 	0xc0106900,
156 	0x000001b3,
157 	0x20000001, /* SPI_PS_IN_CONTROL_0 */
158 	0x00000000, /* SPI_PS_IN_CONTROL_1 */
159 	0x00000000, /* SPI_INTERP_CONTROL_0 */
160 	0x00000000, /* SPI_INPUT_Z */
161 	0x00000000, /* SPI_FOG_CNTL */
162 	0x00100000, /* SPI_BARYC_CNTL */
163 	0x00000000, /* SPI_PS_IN_CONTROL_2 */
164 	0x00000000, /* SPI_COMPUTE_INPUT_CNTL */
165 	0x00000000, /* SPI_COMPUTE_NUM_THREAD_X */
166 	0x00000000, /* SPI_COMPUTE_NUM_THREAD_Y */
167 	0x00000000, /* SPI_COMPUTE_NUM_THREAD_Z */
168 	0x00000000, /* SPI_GPR_MGMT */
169 	0x00000000, /* SPI_LDS_MGMT */
170 	0x00000000, /* SPI_STACK_MGMT */
171 	0x00000000, /* SPI_WAVE_MGMT_1 */
172 	0x00000000, /* SPI_WAVE_MGMT_2 */
173 
174 	0xc0016900,
175 	0x000001e0,
176 	0x00000000, /* CB_BLEND0_CONTROL */
177 
178 	0xc00e6900,
179 	0x00000200,
180 	0x00000000, /* DB_DEPTH_CONTROL */
181 	0x00000000, /* DB_EQAA */
182 	0x00cc0010, /* CB_COLOR_CONTROL */
183 	0x00000210, /* DB_SHADER_CONTROL */
184 	0x00010000, /* PA_CL_CLIP_CNTL */
185 	0x00000004, /* PA_SU_SC_MODE_CNTL */
186 	0x00000100, /* PA_CL_VTE_CNTL */
187 	0x00000000, /* PA_CL_VS_OUT_CNTL */
188 	0x00000000, /* PA_CL_NANINF_CNTL */
189 	0x00000000, /* PA_SU_LINE_STIPPLE_CNTL */
190 	0x00000000, /* PA_SU_LINE_STIPPLE_SCALE */
191 	0x00000000, /* PA_SU_PRIM_FILTER_CNTL */
192 	0x00000000, /*  */
193 	0x00000000, /*  */
194 
195 	0xc0026900,
196 	0x00000229,
197 	0x00000000, /* SQ_PGM_START_FS */
198 	0x00000000,
199 
200 	0xc0016900,
201 	0x0000023b,
202 	0x00000000, /* SQ_LDS_ALLOC_PS */
203 
204 	0xc0066900,
205 	0x00000240,
206 	0x00000000, /* SQ_ESGS_RING_ITEMSIZE */
207 	0x00000000,
208 	0x00000000,
209 	0x00000000,
210 	0x00000000,
211 	0x00000000,
212 
213 	0xc0046900,
214 	0x00000247,
215 	0x00000000, /* SQ_GS_VERT_ITEMSIZE */
216 	0x00000000,
217 	0x00000000,
218 	0x00000000,
219 
220 	0xc0116900,
221 	0x00000280,
222 	0x00000000, /* PA_SU_POINT_SIZE */
223 	0x00000000, /* PA_SU_POINT_MINMAX */
224 	0x00000008, /* PA_SU_LINE_CNTL */
225 	0x00000000, /* PA_SC_LINE_STIPPLE */
226 	0x00000000, /* VGT_OUTPUT_PATH_CNTL */
227 	0x00000000, /* VGT_HOS_CNTL */
228 	0x00000000,
229 	0x00000000,
230 	0x00000000,
231 	0x00000000,
232 	0x00000000,
233 	0x00000000,
234 	0x00000000,
235 	0x00000000,
236 	0x00000000,
237 	0x00000000,
238 	0x00000000, /* VGT_GS_MODE */
239 
240 	0xc0026900,
241 	0x00000292,
242 	0x00000000, /* PA_SC_MODE_CNTL_0 */
243 	0x00000000, /* PA_SC_MODE_CNTL_1 */
244 
245 	0xc0016900,
246 	0x000002a1,
247 	0x00000000, /* VGT_PRIMITIVEID_EN */
248 
249 	0xc0016900,
250 	0x000002a5,
251 	0x00000000, /* VGT_MULTI_PRIM_IB_RESET_EN */
252 
253 	0xc0026900,
254 	0x000002a8,
255 	0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
256 	0x00000000,
257 
258 	0xc0026900,
259 	0x000002ad,
260 	0x00000000, /* VGT_REUSE_OFF */
261 	0x00000000,
262 
263 	0xc0016900,
264 	0x000002d5,
265 	0x00000000, /* VGT_SHADER_STAGES_EN */
266 
267 	0xc0016900,
268 	0x000002dc,
269 	0x0000aa00, /* DB_ALPHA_TO_MASK */
270 
271 	0xc0066900,
272 	0x000002de,
273 	0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
274 	0x00000000,
275 	0x00000000,
276 	0x00000000,
277 	0x00000000,
278 	0x00000000,
279 
280 	0xc0026900,
281 	0x000002e5,
282 	0x00000000, /* VGT_STRMOUT_CONFIG */
283 	0x00000000,
284 
285 	0xc01b6900,
286 	0x000002f5,
287 	0x76543210, /* PA_SC_CENTROID_PRIORITY_0 */
288 	0xfedcba98, /* PA_SC_CENTROID_PRIORITY_1 */
289 	0x00000000, /* PA_SC_LINE_CNTL */
290 	0x00000000, /* PA_SC_AA_CONFIG */
291 	0x00000005, /* PA_SU_VTX_CNTL */
292 	0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */
293 	0x3f800000, /* PA_CL_GB_VERT_DISC_ADJ */
294 	0x3f800000, /* PA_CL_GB_HORZ_CLIP_ADJ */
295 	0x3f800000, /* PA_CL_GB_HORZ_DISC_ADJ */
296 	0x00000000, /* PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 */
297 	0x00000000,
298 	0x00000000,
299 	0x00000000,
300 	0x00000000,
301 	0x00000000,
302 	0x00000000,
303 	0x00000000,
304 	0x00000000,
305 	0x00000000,
306 	0x00000000,
307 	0x00000000,
308 	0x00000000,
309 	0x00000000,
310 	0x00000000,
311 	0x00000000,
312 	0xffffffff, /* PA_SC_AA_MASK_X0Y0_X1Y0 */
313 	0xffffffff,
314 
315 	0xc0026900,
316 	0x00000316,
317 	0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */
318 	0x00000010, /*  */
319 };
320 
321 const u32 cayman_vs[] =
322 {
323 	0x00000004,
324 	0x80400400,
325 	0x0000a03c,
326 	0x95000688,
327 	0x00004000,
328 	0x15000688,
329 	0x00000000,
330 	0x88000000,
331 	0x04000000,
332 	0x67961001,
333 #ifdef __BIG_ENDIAN
334 	0x00020000,
335 #else
336 	0x00000000,
337 #endif
338 	0x00000000,
339 	0x04000000,
340 	0x67961000,
341 #ifdef __BIG_ENDIAN
342 	0x00020008,
343 #else
344 	0x00000008,
345 #endif
346 	0x00000000,
347 };
348 
349 const u32 cayman_ps[] =
350 {
351 	0x00000004,
352 	0xa00c0000,
353 	0x00000008,
354 	0x80400000,
355 	0x00000000,
356 	0x95000688,
357 	0x00000000,
358 	0x88000000,
359 	0x00380400,
360 	0x00146b10,
361 	0x00380000,
362 	0x20146b10,
363 	0x00380400,
364 	0x40146b00,
365 	0x80380000,
366 	0x60146b00,
367 	0x00000010,
368 	0x000d1000,
369 	0xb0800000,
370 	0x00000000,
371 };
372 
373 const u32 cayman_ps_size = DRM_ARRAY_SIZE(cayman_ps);
374 const u32 cayman_vs_size = DRM_ARRAY_SIZE(cayman_vs);
375 const u32 cayman_default_size = DRM_ARRAY_SIZE(cayman_default_state);
376