1 /*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24 #include <linux/firmware.h>
25 #include <linux/module.h>
26 #include <drm/drmP.h>
27 #include "radeon.h"
28 #include "radeon_asic.h"
29 #include "radeon_audio.h"
30 #include <drm/radeon_drm.h>
31 #include "nid.h"
32 #include "atom.h"
33 #include "ni_reg.h"
34 #include "cayman_blit_shaders.h"
35 #include "radeon_ucode.h"
36 #include "clearstate_cayman.h"
37
38 /*
39 * Indirect registers accessor
40 */
tn_smc_rreg(struct radeon_device * rdev,u32 reg)41 u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
42 {
43 u32 r;
44
45 lockmgr(&rdev->smc_idx_lock, LK_EXCLUSIVE);
46 WREG32(TN_SMC_IND_INDEX_0, (reg));
47 r = RREG32(TN_SMC_IND_DATA_0);
48 lockmgr(&rdev->smc_idx_lock, LK_RELEASE);
49 return r;
50 }
51
tn_smc_wreg(struct radeon_device * rdev,u32 reg,u32 v)52 void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
53 {
54 lockmgr(&rdev->smc_idx_lock, LK_EXCLUSIVE);
55 WREG32(TN_SMC_IND_INDEX_0, (reg));
56 WREG32(TN_SMC_IND_DATA_0, (v));
57 lockmgr(&rdev->smc_idx_lock, LK_RELEASE);
58 }
59
60 static const u32 tn_rlc_save_restore_register_list[] =
61 {
62 0x98fc,
63 0x98f0,
64 0x9834,
65 0x9838,
66 0x9870,
67 0x9874,
68 0x8a14,
69 0x8b24,
70 0x8bcc,
71 0x8b10,
72 0x8c30,
73 0x8d00,
74 0x8d04,
75 0x8c00,
76 0x8c04,
77 0x8c10,
78 0x8c14,
79 0x8d8c,
80 0x8cf0,
81 0x8e38,
82 0x9508,
83 0x9688,
84 0x9608,
85 0x960c,
86 0x9610,
87 0x9614,
88 0x88c4,
89 0x8978,
90 0x88d4,
91 0x900c,
92 0x9100,
93 0x913c,
94 0x90e8,
95 0x9354,
96 0xa008,
97 0x98f8,
98 0x9148,
99 0x914c,
100 0x3f94,
101 0x98f4,
102 0x9b7c,
103 0x3f8c,
104 0x8950,
105 0x8954,
106 0x8a18,
107 0x8b28,
108 0x9144,
109 0x3f90,
110 0x915c,
111 0x9160,
112 0x9178,
113 0x917c,
114 0x9180,
115 0x918c,
116 0x9190,
117 0x9194,
118 0x9198,
119 0x919c,
120 0x91a8,
121 0x91ac,
122 0x91b0,
123 0x91b4,
124 0x91b8,
125 0x91c4,
126 0x91c8,
127 0x91cc,
128 0x91d0,
129 0x91d4,
130 0x91e0,
131 0x91e4,
132 0x91ec,
133 0x91f0,
134 0x91f4,
135 0x9200,
136 0x9204,
137 0x929c,
138 0x8030,
139 0x9150,
140 0x9a60,
141 0x920c,
142 0x9210,
143 0x9228,
144 0x922c,
145 0x9244,
146 0x9248,
147 0x91e8,
148 0x9294,
149 0x9208,
150 0x9224,
151 0x9240,
152 0x9220,
153 0x923c,
154 0x9258,
155 0x9744,
156 0xa200,
157 0xa204,
158 0xa208,
159 0xa20c,
160 0x8d58,
161 0x9030,
162 0x9034,
163 0x9038,
164 0x903c,
165 0x9040,
166 0x9654,
167 0x897c,
168 0xa210,
169 0xa214,
170 0x9868,
171 0xa02c,
172 0x9664,
173 0x9698,
174 0x949c,
175 0x8e10,
176 0x8e18,
177 0x8c50,
178 0x8c58,
179 0x8c60,
180 0x8c68,
181 0x89b4,
182 0x9830,
183 0x802c,
184 };
185
186 /* Firmware Names */
187 MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
188 MODULE_FIRMWARE("radeon/BARTS_me.bin");
189 MODULE_FIRMWARE("radeon/BARTS_mc.bin");
190 MODULE_FIRMWARE("radeon/BARTS_smc.bin");
191 MODULE_FIRMWARE("radeon/BTC_rlc.bin");
192 MODULE_FIRMWARE("radeon/TURKS_pfp.bin");
193 MODULE_FIRMWARE("radeon/TURKS_me.bin");
194 MODULE_FIRMWARE("radeon/TURKS_mc.bin");
195 MODULE_FIRMWARE("radeon/TURKS_smc.bin");
196 MODULE_FIRMWARE("radeon/CAICOS_pfp.bin");
197 MODULE_FIRMWARE("radeon/CAICOS_me.bin");
198 MODULE_FIRMWARE("radeon/CAICOS_mc.bin");
199 MODULE_FIRMWARE("radeon/CAICOS_smc.bin");
200 MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin");
201 MODULE_FIRMWARE("radeon/CAYMAN_me.bin");
202 MODULE_FIRMWARE("radeon/CAYMAN_mc.bin");
203 MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin");
204 MODULE_FIRMWARE("radeon/CAYMAN_smc.bin");
205 MODULE_FIRMWARE("radeon/ARUBA_pfp.bin");
206 MODULE_FIRMWARE("radeon/ARUBA_me.bin");
207 MODULE_FIRMWARE("radeon/ARUBA_rlc.bin");
208
209
210 static const u32 cayman_golden_registers2[] =
211 {
212 0x3e5c, 0xffffffff, 0x00000000,
213 0x3e48, 0xffffffff, 0x00000000,
214 0x3e4c, 0xffffffff, 0x00000000,
215 0x3e64, 0xffffffff, 0x00000000,
216 0x3e50, 0xffffffff, 0x00000000,
217 0x3e60, 0xffffffff, 0x00000000
218 };
219
220 static const u32 cayman_golden_registers[] =
221 {
222 0x5eb4, 0xffffffff, 0x00000002,
223 0x5e78, 0x8f311ff1, 0x001000f0,
224 0x3f90, 0xffff0000, 0xff000000,
225 0x9148, 0xffff0000, 0xff000000,
226 0x3f94, 0xffff0000, 0xff000000,
227 0x914c, 0xffff0000, 0xff000000,
228 0xc78, 0x00000080, 0x00000080,
229 0xbd4, 0x70073777, 0x00011003,
230 0xd02c, 0xbfffff1f, 0x08421000,
231 0xd0b8, 0x73773777, 0x02011003,
232 0x5bc0, 0x00200000, 0x50100000,
233 0x98f8, 0x33773777, 0x02011003,
234 0x98fc, 0xffffffff, 0x76541032,
235 0x7030, 0x31000311, 0x00000011,
236 0x2f48, 0x33773777, 0x42010001,
237 0x6b28, 0x00000010, 0x00000012,
238 0x7728, 0x00000010, 0x00000012,
239 0x10328, 0x00000010, 0x00000012,
240 0x10f28, 0x00000010, 0x00000012,
241 0x11b28, 0x00000010, 0x00000012,
242 0x12728, 0x00000010, 0x00000012,
243 0x240c, 0x000007ff, 0x00000000,
244 0x8a14, 0xf000001f, 0x00000007,
245 0x8b24, 0x3fff3fff, 0x00ff0fff,
246 0x8b10, 0x0000ff0f, 0x00000000,
247 0x28a4c, 0x07ffffff, 0x06000000,
248 0x10c, 0x00000001, 0x00010003,
249 0xa02c, 0xffffffff, 0x0000009b,
250 0x913c, 0x0000010f, 0x01000100,
251 0x8c04, 0xf8ff00ff, 0x40600060,
252 0x28350, 0x00000f01, 0x00000000,
253 0x9508, 0x3700001f, 0x00000002,
254 0x960c, 0xffffffff, 0x54763210,
255 0x88c4, 0x001f3ae3, 0x00000082,
256 0x88d0, 0xffffffff, 0x0f40df40,
257 0x88d4, 0x0000001f, 0x00000010,
258 0x8974, 0xffffffff, 0x00000000
259 };
260
261 static const u32 dvst_golden_registers2[] =
262 {
263 0x8f8, 0xffffffff, 0,
264 0x8fc, 0x00380000, 0,
265 0x8f8, 0xffffffff, 1,
266 0x8fc, 0x0e000000, 0
267 };
268
269 static const u32 dvst_golden_registers[] =
270 {
271 0x690, 0x3fff3fff, 0x20c00033,
272 0x918c, 0x0fff0fff, 0x00010006,
273 0x91a8, 0x0fff0fff, 0x00010006,
274 0x9150, 0xffffdfff, 0x6e944040,
275 0x917c, 0x0fff0fff, 0x00030002,
276 0x9198, 0x0fff0fff, 0x00030002,
277 0x915c, 0x0fff0fff, 0x00010000,
278 0x3f90, 0xffff0001, 0xff000000,
279 0x9178, 0x0fff0fff, 0x00070000,
280 0x9194, 0x0fff0fff, 0x00070000,
281 0x9148, 0xffff0001, 0xff000000,
282 0x9190, 0x0fff0fff, 0x00090008,
283 0x91ac, 0x0fff0fff, 0x00090008,
284 0x3f94, 0xffff0000, 0xff000000,
285 0x914c, 0xffff0000, 0xff000000,
286 0x929c, 0x00000fff, 0x00000001,
287 0x55e4, 0xff607fff, 0xfc000100,
288 0x8a18, 0xff000fff, 0x00000100,
289 0x8b28, 0xff000fff, 0x00000100,
290 0x9144, 0xfffc0fff, 0x00000100,
291 0x6ed8, 0x00010101, 0x00010000,
292 0x9830, 0xffffffff, 0x00000000,
293 0x9834, 0xf00fffff, 0x00000400,
294 0x9838, 0xfffffffe, 0x00000000,
295 0xd0c0, 0xff000fff, 0x00000100,
296 0xd02c, 0xbfffff1f, 0x08421000,
297 0xd0b8, 0x73773777, 0x12010001,
298 0x5bb0, 0x000000f0, 0x00000070,
299 0x98f8, 0x73773777, 0x12010001,
300 0x98fc, 0xffffffff, 0x00000010,
301 0x9b7c, 0x00ff0000, 0x00fc0000,
302 0x8030, 0x00001f0f, 0x0000100a,
303 0x2f48, 0x73773777, 0x12010001,
304 0x2408, 0x00030000, 0x000c007f,
305 0x8a14, 0xf000003f, 0x00000007,
306 0x8b24, 0x3fff3fff, 0x00ff0fff,
307 0x8b10, 0x0000ff0f, 0x00000000,
308 0x28a4c, 0x07ffffff, 0x06000000,
309 0x4d8, 0x00000fff, 0x00000100,
310 0xa008, 0xffffffff, 0x00010000,
311 0x913c, 0xffff03ff, 0x01000100,
312 0x8c00, 0x000000ff, 0x00000003,
313 0x8c04, 0xf8ff00ff, 0x40600060,
314 0x8cf0, 0x1fff1fff, 0x08e00410,
315 0x28350, 0x00000f01, 0x00000000,
316 0x9508, 0xf700071f, 0x00000002,
317 0x960c, 0xffffffff, 0x54763210,
318 0x20ef8, 0x01ff01ff, 0x00000002,
319 0x20e98, 0xfffffbff, 0x00200000,
320 0x2015c, 0xffffffff, 0x00000f40,
321 0x88c4, 0x001f3ae3, 0x00000082,
322 0x8978, 0x3fffffff, 0x04050140,
323 0x88d4, 0x0000001f, 0x00000010,
324 0x8974, 0xffffffff, 0x00000000
325 };
326
327 static const u32 scrapper_golden_registers[] =
328 {
329 0x690, 0x3fff3fff, 0x20c00033,
330 0x918c, 0x0fff0fff, 0x00010006,
331 0x918c, 0x0fff0fff, 0x00010006,
332 0x91a8, 0x0fff0fff, 0x00010006,
333 0x91a8, 0x0fff0fff, 0x00010006,
334 0x9150, 0xffffdfff, 0x6e944040,
335 0x9150, 0xffffdfff, 0x6e944040,
336 0x917c, 0x0fff0fff, 0x00030002,
337 0x917c, 0x0fff0fff, 0x00030002,
338 0x9198, 0x0fff0fff, 0x00030002,
339 0x9198, 0x0fff0fff, 0x00030002,
340 0x915c, 0x0fff0fff, 0x00010000,
341 0x915c, 0x0fff0fff, 0x00010000,
342 0x3f90, 0xffff0001, 0xff000000,
343 0x3f90, 0xffff0001, 0xff000000,
344 0x9178, 0x0fff0fff, 0x00070000,
345 0x9178, 0x0fff0fff, 0x00070000,
346 0x9194, 0x0fff0fff, 0x00070000,
347 0x9194, 0x0fff0fff, 0x00070000,
348 0x9148, 0xffff0001, 0xff000000,
349 0x9148, 0xffff0001, 0xff000000,
350 0x9190, 0x0fff0fff, 0x00090008,
351 0x9190, 0x0fff0fff, 0x00090008,
352 0x91ac, 0x0fff0fff, 0x00090008,
353 0x91ac, 0x0fff0fff, 0x00090008,
354 0x3f94, 0xffff0000, 0xff000000,
355 0x3f94, 0xffff0000, 0xff000000,
356 0x914c, 0xffff0000, 0xff000000,
357 0x914c, 0xffff0000, 0xff000000,
358 0x929c, 0x00000fff, 0x00000001,
359 0x929c, 0x00000fff, 0x00000001,
360 0x55e4, 0xff607fff, 0xfc000100,
361 0x8a18, 0xff000fff, 0x00000100,
362 0x8a18, 0xff000fff, 0x00000100,
363 0x8b28, 0xff000fff, 0x00000100,
364 0x8b28, 0xff000fff, 0x00000100,
365 0x9144, 0xfffc0fff, 0x00000100,
366 0x9144, 0xfffc0fff, 0x00000100,
367 0x6ed8, 0x00010101, 0x00010000,
368 0x9830, 0xffffffff, 0x00000000,
369 0x9830, 0xffffffff, 0x00000000,
370 0x9834, 0xf00fffff, 0x00000400,
371 0x9834, 0xf00fffff, 0x00000400,
372 0x9838, 0xfffffffe, 0x00000000,
373 0x9838, 0xfffffffe, 0x00000000,
374 0xd0c0, 0xff000fff, 0x00000100,
375 0xd02c, 0xbfffff1f, 0x08421000,
376 0xd02c, 0xbfffff1f, 0x08421000,
377 0xd0b8, 0x73773777, 0x12010001,
378 0xd0b8, 0x73773777, 0x12010001,
379 0x5bb0, 0x000000f0, 0x00000070,
380 0x98f8, 0x73773777, 0x12010001,
381 0x98f8, 0x73773777, 0x12010001,
382 0x98fc, 0xffffffff, 0x00000010,
383 0x98fc, 0xffffffff, 0x00000010,
384 0x9b7c, 0x00ff0000, 0x00fc0000,
385 0x9b7c, 0x00ff0000, 0x00fc0000,
386 0x8030, 0x00001f0f, 0x0000100a,
387 0x8030, 0x00001f0f, 0x0000100a,
388 0x2f48, 0x73773777, 0x12010001,
389 0x2f48, 0x73773777, 0x12010001,
390 0x2408, 0x00030000, 0x000c007f,
391 0x8a14, 0xf000003f, 0x00000007,
392 0x8a14, 0xf000003f, 0x00000007,
393 0x8b24, 0x3fff3fff, 0x00ff0fff,
394 0x8b24, 0x3fff3fff, 0x00ff0fff,
395 0x8b10, 0x0000ff0f, 0x00000000,
396 0x8b10, 0x0000ff0f, 0x00000000,
397 0x28a4c, 0x07ffffff, 0x06000000,
398 0x28a4c, 0x07ffffff, 0x06000000,
399 0x4d8, 0x00000fff, 0x00000100,
400 0x4d8, 0x00000fff, 0x00000100,
401 0xa008, 0xffffffff, 0x00010000,
402 0xa008, 0xffffffff, 0x00010000,
403 0x913c, 0xffff03ff, 0x01000100,
404 0x913c, 0xffff03ff, 0x01000100,
405 0x90e8, 0x001fffff, 0x010400c0,
406 0x8c00, 0x000000ff, 0x00000003,
407 0x8c00, 0x000000ff, 0x00000003,
408 0x8c04, 0xf8ff00ff, 0x40600060,
409 0x8c04, 0xf8ff00ff, 0x40600060,
410 0x8c30, 0x0000000f, 0x00040005,
411 0x8cf0, 0x1fff1fff, 0x08e00410,
412 0x8cf0, 0x1fff1fff, 0x08e00410,
413 0x900c, 0x00ffffff, 0x0017071f,
414 0x28350, 0x00000f01, 0x00000000,
415 0x28350, 0x00000f01, 0x00000000,
416 0x9508, 0xf700071f, 0x00000002,
417 0x9508, 0xf700071f, 0x00000002,
418 0x9688, 0x00300000, 0x0017000f,
419 0x960c, 0xffffffff, 0x54763210,
420 0x960c, 0xffffffff, 0x54763210,
421 0x20ef8, 0x01ff01ff, 0x00000002,
422 0x20e98, 0xfffffbff, 0x00200000,
423 0x2015c, 0xffffffff, 0x00000f40,
424 0x88c4, 0x001f3ae3, 0x00000082,
425 0x88c4, 0x001f3ae3, 0x00000082,
426 0x8978, 0x3fffffff, 0x04050140,
427 0x8978, 0x3fffffff, 0x04050140,
428 0x88d4, 0x0000001f, 0x00000010,
429 0x88d4, 0x0000001f, 0x00000010,
430 0x8974, 0xffffffff, 0x00000000,
431 0x8974, 0xffffffff, 0x00000000
432 };
433
ni_init_golden_registers(struct radeon_device * rdev)434 static void ni_init_golden_registers(struct radeon_device *rdev)
435 {
436 switch (rdev->family) {
437 case CHIP_CAYMAN:
438 radeon_program_register_sequence(rdev,
439 cayman_golden_registers,
440 (const u32)ARRAY_SIZE(cayman_golden_registers));
441 radeon_program_register_sequence(rdev,
442 cayman_golden_registers2,
443 (const u32)ARRAY_SIZE(cayman_golden_registers2));
444 break;
445 case CHIP_ARUBA:
446 if ((rdev->pdev->device == 0x9900) ||
447 (rdev->pdev->device == 0x9901) ||
448 (rdev->pdev->device == 0x9903) ||
449 (rdev->pdev->device == 0x9904) ||
450 (rdev->pdev->device == 0x9905) ||
451 (rdev->pdev->device == 0x9906) ||
452 (rdev->pdev->device == 0x9907) ||
453 (rdev->pdev->device == 0x9908) ||
454 (rdev->pdev->device == 0x9909) ||
455 (rdev->pdev->device == 0x990A) ||
456 (rdev->pdev->device == 0x990B) ||
457 (rdev->pdev->device == 0x990C) ||
458 (rdev->pdev->device == 0x990D) ||
459 (rdev->pdev->device == 0x990E) ||
460 (rdev->pdev->device == 0x990F) ||
461 (rdev->pdev->device == 0x9910) ||
462 (rdev->pdev->device == 0x9913) ||
463 (rdev->pdev->device == 0x9917) ||
464 (rdev->pdev->device == 0x9918)) {
465 radeon_program_register_sequence(rdev,
466 dvst_golden_registers,
467 (const u32)ARRAY_SIZE(dvst_golden_registers));
468 radeon_program_register_sequence(rdev,
469 dvst_golden_registers2,
470 (const u32)ARRAY_SIZE(dvst_golden_registers2));
471 } else {
472 radeon_program_register_sequence(rdev,
473 scrapper_golden_registers,
474 (const u32)ARRAY_SIZE(scrapper_golden_registers));
475 radeon_program_register_sequence(rdev,
476 dvst_golden_registers2,
477 (const u32)ARRAY_SIZE(dvst_golden_registers2));
478 }
479 break;
480 default:
481 break;
482 }
483 }
484
485 #define BTC_IO_MC_REGS_SIZE 29
486
487 static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
488 {0x00000077, 0xff010100},
489 {0x00000078, 0x00000000},
490 {0x00000079, 0x00001434},
491 {0x0000007a, 0xcc08ec08},
492 {0x0000007b, 0x00040000},
493 {0x0000007c, 0x000080c0},
494 {0x0000007d, 0x09000000},
495 {0x0000007e, 0x00210404},
496 {0x00000081, 0x08a8e800},
497 {0x00000082, 0x00030444},
498 {0x00000083, 0x00000000},
499 {0x00000085, 0x00000001},
500 {0x00000086, 0x00000002},
501 {0x00000087, 0x48490000},
502 {0x00000088, 0x20244647},
503 {0x00000089, 0x00000005},
504 {0x0000008b, 0x66030000},
505 {0x0000008c, 0x00006603},
506 {0x0000008d, 0x00000100},
507 {0x0000008f, 0x00001c0a},
508 {0x00000090, 0xff000001},
509 {0x00000094, 0x00101101},
510 {0x00000095, 0x00000fff},
511 {0x00000096, 0x00116fff},
512 {0x00000097, 0x60010000},
513 {0x00000098, 0x10010000},
514 {0x00000099, 0x00006000},
515 {0x0000009a, 0x00001000},
516 {0x0000009f, 0x00946a00}
517 };
518
519 static const u32 turks_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
520 {0x00000077, 0xff010100},
521 {0x00000078, 0x00000000},
522 {0x00000079, 0x00001434},
523 {0x0000007a, 0xcc08ec08},
524 {0x0000007b, 0x00040000},
525 {0x0000007c, 0x000080c0},
526 {0x0000007d, 0x09000000},
527 {0x0000007e, 0x00210404},
528 {0x00000081, 0x08a8e800},
529 {0x00000082, 0x00030444},
530 {0x00000083, 0x00000000},
531 {0x00000085, 0x00000001},
532 {0x00000086, 0x00000002},
533 {0x00000087, 0x48490000},
534 {0x00000088, 0x20244647},
535 {0x00000089, 0x00000005},
536 {0x0000008b, 0x66030000},
537 {0x0000008c, 0x00006603},
538 {0x0000008d, 0x00000100},
539 {0x0000008f, 0x00001c0a},
540 {0x00000090, 0xff000001},
541 {0x00000094, 0x00101101},
542 {0x00000095, 0x00000fff},
543 {0x00000096, 0x00116fff},
544 {0x00000097, 0x60010000},
545 {0x00000098, 0x10010000},
546 {0x00000099, 0x00006000},
547 {0x0000009a, 0x00001000},
548 {0x0000009f, 0x00936a00}
549 };
550
551 static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
552 {0x00000077, 0xff010100},
553 {0x00000078, 0x00000000},
554 {0x00000079, 0x00001434},
555 {0x0000007a, 0xcc08ec08},
556 {0x0000007b, 0x00040000},
557 {0x0000007c, 0x000080c0},
558 {0x0000007d, 0x09000000},
559 {0x0000007e, 0x00210404},
560 {0x00000081, 0x08a8e800},
561 {0x00000082, 0x00030444},
562 {0x00000083, 0x00000000},
563 {0x00000085, 0x00000001},
564 {0x00000086, 0x00000002},
565 {0x00000087, 0x48490000},
566 {0x00000088, 0x20244647},
567 {0x00000089, 0x00000005},
568 {0x0000008b, 0x66030000},
569 {0x0000008c, 0x00006603},
570 {0x0000008d, 0x00000100},
571 {0x0000008f, 0x00001c0a},
572 {0x00000090, 0xff000001},
573 {0x00000094, 0x00101101},
574 {0x00000095, 0x00000fff},
575 {0x00000096, 0x00116fff},
576 {0x00000097, 0x60010000},
577 {0x00000098, 0x10010000},
578 {0x00000099, 0x00006000},
579 {0x0000009a, 0x00001000},
580 {0x0000009f, 0x00916a00}
581 };
582
583 static const u32 cayman_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
584 {0x00000077, 0xff010100},
585 {0x00000078, 0x00000000},
586 {0x00000079, 0x00001434},
587 {0x0000007a, 0xcc08ec08},
588 {0x0000007b, 0x00040000},
589 {0x0000007c, 0x000080c0},
590 {0x0000007d, 0x09000000},
591 {0x0000007e, 0x00210404},
592 {0x00000081, 0x08a8e800},
593 {0x00000082, 0x00030444},
594 {0x00000083, 0x00000000},
595 {0x00000085, 0x00000001},
596 {0x00000086, 0x00000002},
597 {0x00000087, 0x48490000},
598 {0x00000088, 0x20244647},
599 {0x00000089, 0x00000005},
600 {0x0000008b, 0x66030000},
601 {0x0000008c, 0x00006603},
602 {0x0000008d, 0x00000100},
603 {0x0000008f, 0x00001c0a},
604 {0x00000090, 0xff000001},
605 {0x00000094, 0x00101101},
606 {0x00000095, 0x00000fff},
607 {0x00000096, 0x00116fff},
608 {0x00000097, 0x60010000},
609 {0x00000098, 0x10010000},
610 {0x00000099, 0x00006000},
611 {0x0000009a, 0x00001000},
612 {0x0000009f, 0x00976b00}
613 };
614
ni_mc_load_microcode(struct radeon_device * rdev)615 int ni_mc_load_microcode(struct radeon_device *rdev)
616 {
617 const __be32 *fw_data;
618 u32 mem_type, running, blackout = 0;
619 u32 *io_mc_regs;
620 int i, ucode_size, regs_size;
621
622 if (!rdev->mc_fw)
623 return -EINVAL;
624
625 switch (rdev->family) {
626 case CHIP_BARTS:
627 io_mc_regs = (u32 *)&barts_io_mc_regs;
628 ucode_size = BTC_MC_UCODE_SIZE;
629 regs_size = BTC_IO_MC_REGS_SIZE;
630 break;
631 case CHIP_TURKS:
632 io_mc_regs = (u32 *)&turks_io_mc_regs;
633 ucode_size = BTC_MC_UCODE_SIZE;
634 regs_size = BTC_IO_MC_REGS_SIZE;
635 break;
636 case CHIP_CAICOS:
637 default:
638 io_mc_regs = (u32 *)&caicos_io_mc_regs;
639 ucode_size = BTC_MC_UCODE_SIZE;
640 regs_size = BTC_IO_MC_REGS_SIZE;
641 break;
642 case CHIP_CAYMAN:
643 io_mc_regs = (u32 *)&cayman_io_mc_regs;
644 ucode_size = CAYMAN_MC_UCODE_SIZE;
645 regs_size = BTC_IO_MC_REGS_SIZE;
646 break;
647 }
648
649 mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT;
650 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
651
652 if ((mem_type == MC_SEQ_MISC0_GDDR5_VALUE) && (running == 0)) {
653 if (running) {
654 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
655 WREG32(MC_SHARED_BLACKOUT_CNTL, 1);
656 }
657
658 /* reset the engine and set to writable */
659 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
660 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
661
662 /* load mc io regs */
663 for (i = 0; i < regs_size; i++) {
664 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
665 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
666 }
667 /* load the MC ucode */
668 fw_data = (const __be32 *)rdev->mc_fw->data;
669 for (i = 0; i < ucode_size; i++)
670 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
671
672 /* put the engine back into the active state */
673 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
674 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
675 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
676
677 /* wait for training to complete */
678 for (i = 0; i < rdev->usec_timeout; i++) {
679 if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD)
680 break;
681 udelay(1);
682 }
683
684 if (running)
685 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
686 }
687
688 return 0;
689 }
690
ni_init_microcode(struct radeon_device * rdev)691 int ni_init_microcode(struct radeon_device *rdev)
692 {
693 const char *chip_name;
694 const char *rlc_chip_name;
695 size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size;
696 size_t smc_req_size = 0;
697 char fw_name[30];
698 int err;
699
700 DRM_DEBUG("\n");
701
702 switch (rdev->family) {
703 case CHIP_BARTS:
704 chip_name = "BARTS";
705 rlc_chip_name = "BTC";
706 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
707 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
708 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
709 mc_req_size = BTC_MC_UCODE_SIZE * 4;
710 smc_req_size = ALIGN(BARTS_SMC_UCODE_SIZE, 4);
711 break;
712 case CHIP_TURKS:
713 chip_name = "TURKS";
714 rlc_chip_name = "BTC";
715 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
716 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
717 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
718 mc_req_size = BTC_MC_UCODE_SIZE * 4;
719 smc_req_size = ALIGN(TURKS_SMC_UCODE_SIZE, 4);
720 break;
721 case CHIP_CAICOS:
722 chip_name = "CAICOS";
723 rlc_chip_name = "BTC";
724 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
725 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
726 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
727 mc_req_size = BTC_MC_UCODE_SIZE * 4;
728 smc_req_size = ALIGN(CAICOS_SMC_UCODE_SIZE, 4);
729 break;
730 case CHIP_CAYMAN:
731 chip_name = "CAYMAN";
732 rlc_chip_name = "CAYMAN";
733 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
734 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
735 rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4;
736 mc_req_size = CAYMAN_MC_UCODE_SIZE * 4;
737 smc_req_size = ALIGN(CAYMAN_SMC_UCODE_SIZE, 4);
738 break;
739 case CHIP_ARUBA:
740 chip_name = "ARUBA";
741 rlc_chip_name = "ARUBA";
742 /* pfp/me same size as CAYMAN */
743 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
744 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
745 rlc_req_size = ARUBA_RLC_UCODE_SIZE * 4;
746 mc_req_size = 0;
747 break;
748 default: BUG();
749 }
750
751 DRM_INFO("Loading %s Microcode\n", chip_name);
752
753 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_pfp", chip_name);
754 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
755 if (err)
756 goto out;
757 if (rdev->pfp_fw->datasize != pfp_req_size) {
758 printk(KERN_ERR
759 "ni_pfp: Bogus length %zu in firmware \"%s\"\n",
760 rdev->pfp_fw->datasize, fw_name);
761 err = -EINVAL;
762 goto out;
763 }
764
765 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_me", chip_name);
766 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
767 if (err)
768 goto out;
769 if (rdev->me_fw->datasize != me_req_size) {
770 printk(KERN_ERR
771 "ni_me: Bogus length %zu in firmware \"%s\"\n",
772 rdev->me_fw->datasize, fw_name);
773 err = -EINVAL;
774 }
775
776 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_rlc",
777 rlc_chip_name);
778 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
779 if (err)
780 goto out;
781 if (rdev->rlc_fw->datasize != rlc_req_size) {
782 printk(KERN_ERR
783 "ni_rlc: Bogus length %zu in firmware \"%s\"\n",
784 rdev->rlc_fw->datasize, fw_name);
785 err = -EINVAL;
786 }
787
788 /* no MC ucode on TN */
789 if (!(rdev->flags & RADEON_IS_IGP)) {
790 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_mc", chip_name);
791 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
792 if (err)
793 goto out;
794 if (rdev->mc_fw->datasize != mc_req_size) {
795 printk(KERN_ERR
796 "ni_mc: Bogus length %zu in firmware \"%s\"\n",
797 rdev->mc_fw->datasize, fw_name);
798 err = -EINVAL;
799 }
800 }
801
802 if ((rdev->family >= CHIP_BARTS) && (rdev->family <= CHIP_CAYMAN)) {
803 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_smc", chip_name);
804 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
805 if (err) {
806 printk(KERN_ERR
807 "smc: error loading firmware \"%s\"\n",
808 fw_name);
809 release_firmware(rdev->smc_fw);
810 rdev->smc_fw = NULL;
811 err = 0;
812 } else if (rdev->smc_fw->datasize != smc_req_size) {
813 printk(KERN_ERR
814 "ni_smc: Bogus length %zu in firmware \"%s\"\n",
815 rdev->smc_fw->datasize, fw_name);
816 err = -EINVAL;
817 }
818 }
819
820 out:
821 if (err) {
822 if (err != -EINVAL)
823 pr_err("ni_cp: Failed to load firmware \"%s\"\n",
824 fw_name);
825 release_firmware(rdev->pfp_fw);
826 rdev->pfp_fw = NULL;
827 release_firmware(rdev->me_fw);
828 rdev->me_fw = NULL;
829 release_firmware(rdev->rlc_fw);
830 rdev->rlc_fw = NULL;
831 release_firmware(rdev->mc_fw);
832 rdev->mc_fw = NULL;
833 release_firmware(rdev->smc_fw);
834 rdev->smc_fw = NULL;
835 }
836 return err;
837 }
838
839 /**
840 * ni_fini_microcode - drop the firmwares image references
841 *
842 * @rdev: radeon_device pointer
843 *
844 * Drop the pfp, me, mc and rlc firmwares image references.
845 * Called at driver shutdown.
846 */
ni_fini_microcode(struct radeon_device * rdev)847 void ni_fini_microcode(struct radeon_device *rdev)
848 {
849 release_firmware(rdev->pfp_fw);
850 rdev->pfp_fw = NULL;
851 release_firmware(rdev->me_fw);
852 rdev->me_fw = NULL;
853 release_firmware(rdev->rlc_fw);
854 rdev->rlc_fw = NULL;
855 release_firmware(rdev->mc_fw);
856 rdev->mc_fw = NULL;
857 release_firmware(rdev->smc_fw);
858 rdev->smc_fw = NULL;
859 }
860
861 /**
862 * cayman_get_allowed_info_register - fetch the register for the info ioctl
863 *
864 * @rdev: radeon_device pointer
865 * @reg: register offset in bytes
866 * @val: register value
867 *
868 * Returns 0 for success or -EINVAL for an invalid register
869 *
870 */
cayman_get_allowed_info_register(struct radeon_device * rdev,u32 reg,u32 * val)871 int cayman_get_allowed_info_register(struct radeon_device *rdev,
872 u32 reg, u32 *val)
873 {
874 switch (reg) {
875 case GRBM_STATUS:
876 case GRBM_STATUS_SE0:
877 case GRBM_STATUS_SE1:
878 case SRBM_STATUS:
879 case SRBM_STATUS2:
880 case (DMA_STATUS_REG + DMA0_REGISTER_OFFSET):
881 case (DMA_STATUS_REG + DMA1_REGISTER_OFFSET):
882 case UVD_STATUS:
883 *val = RREG32(reg);
884 return 0;
885 default:
886 return -EINVAL;
887 }
888 }
889
tn_get_temp(struct radeon_device * rdev)890 int tn_get_temp(struct radeon_device *rdev)
891 {
892 u32 temp = RREG32_SMC(TN_CURRENT_GNB_TEMP) & 0x7ff;
893 int actual_temp = (temp / 8) - 49;
894
895 return actual_temp * 1000;
896 }
897
898 /*
899 * Core functions
900 */
cayman_gpu_init(struct radeon_device * rdev)901 static void cayman_gpu_init(struct radeon_device *rdev)
902 {
903 u32 gb_addr_config = 0;
904 u32 mc_shared_chmap, mc_arb_ramcfg;
905 u32 cgts_tcc_disable;
906 u32 sx_debug_1;
907 u32 smx_dc_ctl0;
908 u32 cgts_sm_ctrl_reg;
909 u32 hdp_host_path_cntl;
910 u32 tmp;
911 u32 disabled_rb_mask;
912 int i, j;
913
914 switch (rdev->family) {
915 case CHIP_CAYMAN:
916 rdev->config.cayman.max_shader_engines = 2;
917 rdev->config.cayman.max_pipes_per_simd = 4;
918 rdev->config.cayman.max_tile_pipes = 8;
919 rdev->config.cayman.max_simds_per_se = 12;
920 rdev->config.cayman.max_backends_per_se = 4;
921 rdev->config.cayman.max_texture_channel_caches = 8;
922 rdev->config.cayman.max_gprs = 256;
923 rdev->config.cayman.max_threads = 256;
924 rdev->config.cayman.max_gs_threads = 32;
925 rdev->config.cayman.max_stack_entries = 512;
926 rdev->config.cayman.sx_num_of_sets = 8;
927 rdev->config.cayman.sx_max_export_size = 256;
928 rdev->config.cayman.sx_max_export_pos_size = 64;
929 rdev->config.cayman.sx_max_export_smx_size = 192;
930 rdev->config.cayman.max_hw_contexts = 8;
931 rdev->config.cayman.sq_num_cf_insts = 2;
932
933 rdev->config.cayman.sc_prim_fifo_size = 0x100;
934 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
935 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
936 gb_addr_config = CAYMAN_GB_ADDR_CONFIG_GOLDEN;
937 break;
938 case CHIP_ARUBA:
939 default:
940 rdev->config.cayman.max_shader_engines = 1;
941 rdev->config.cayman.max_pipes_per_simd = 4;
942 rdev->config.cayman.max_tile_pipes = 2;
943 if ((rdev->pdev->device == 0x9900) ||
944 (rdev->pdev->device == 0x9901) ||
945 (rdev->pdev->device == 0x9905) ||
946 (rdev->pdev->device == 0x9906) ||
947 (rdev->pdev->device == 0x9907) ||
948 (rdev->pdev->device == 0x9908) ||
949 (rdev->pdev->device == 0x9909) ||
950 (rdev->pdev->device == 0x990B) ||
951 (rdev->pdev->device == 0x990C) ||
952 (rdev->pdev->device == 0x990F) ||
953 (rdev->pdev->device == 0x9910) ||
954 (rdev->pdev->device == 0x9917) ||
955 (rdev->pdev->device == 0x9999) ||
956 (rdev->pdev->device == 0x999C)) {
957 rdev->config.cayman.max_simds_per_se = 6;
958 rdev->config.cayman.max_backends_per_se = 2;
959 rdev->config.cayman.max_hw_contexts = 8;
960 rdev->config.cayman.sx_max_export_size = 256;
961 rdev->config.cayman.sx_max_export_pos_size = 64;
962 rdev->config.cayman.sx_max_export_smx_size = 192;
963 } else if ((rdev->pdev->device == 0x9903) ||
964 (rdev->pdev->device == 0x9904) ||
965 (rdev->pdev->device == 0x990A) ||
966 (rdev->pdev->device == 0x990D) ||
967 (rdev->pdev->device == 0x990E) ||
968 (rdev->pdev->device == 0x9913) ||
969 (rdev->pdev->device == 0x9918) ||
970 (rdev->pdev->device == 0x999D)) {
971 rdev->config.cayman.max_simds_per_se = 4;
972 rdev->config.cayman.max_backends_per_se = 2;
973 rdev->config.cayman.max_hw_contexts = 8;
974 rdev->config.cayman.sx_max_export_size = 256;
975 rdev->config.cayman.sx_max_export_pos_size = 64;
976 rdev->config.cayman.sx_max_export_smx_size = 192;
977 } else if ((rdev->pdev->device == 0x9919) ||
978 (rdev->pdev->device == 0x9990) ||
979 (rdev->pdev->device == 0x9991) ||
980 (rdev->pdev->device == 0x9994) ||
981 (rdev->pdev->device == 0x9995) ||
982 (rdev->pdev->device == 0x9996) ||
983 (rdev->pdev->device == 0x999A) ||
984 (rdev->pdev->device == 0x99A0)) {
985 rdev->config.cayman.max_simds_per_se = 3;
986 rdev->config.cayman.max_backends_per_se = 1;
987 rdev->config.cayman.max_hw_contexts = 4;
988 rdev->config.cayman.sx_max_export_size = 128;
989 rdev->config.cayman.sx_max_export_pos_size = 32;
990 rdev->config.cayman.sx_max_export_smx_size = 96;
991 } else {
992 rdev->config.cayman.max_simds_per_se = 2;
993 rdev->config.cayman.max_backends_per_se = 1;
994 rdev->config.cayman.max_hw_contexts = 4;
995 rdev->config.cayman.sx_max_export_size = 128;
996 rdev->config.cayman.sx_max_export_pos_size = 32;
997 rdev->config.cayman.sx_max_export_smx_size = 96;
998 }
999 rdev->config.cayman.max_texture_channel_caches = 2;
1000 rdev->config.cayman.max_gprs = 256;
1001 rdev->config.cayman.max_threads = 256;
1002 rdev->config.cayman.max_gs_threads = 32;
1003 rdev->config.cayman.max_stack_entries = 512;
1004 rdev->config.cayman.sx_num_of_sets = 8;
1005 rdev->config.cayman.sq_num_cf_insts = 2;
1006
1007 rdev->config.cayman.sc_prim_fifo_size = 0x40;
1008 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
1009 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
1010 gb_addr_config = ARUBA_GB_ADDR_CONFIG_GOLDEN;
1011 break;
1012 }
1013
1014 /* Initialize HDP */
1015 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1016 WREG32((0x2c14 + j), 0x00000000);
1017 WREG32((0x2c18 + j), 0x00000000);
1018 WREG32((0x2c1c + j), 0x00000000);
1019 WREG32((0x2c20 + j), 0x00000000);
1020 WREG32((0x2c24 + j), 0x00000000);
1021 }
1022
1023 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1024 WREG32(SRBM_INT_CNTL, 0x1);
1025 WREG32(SRBM_INT_ACK, 0x1);
1026
1027 evergreen_fix_pci_max_read_req_size(rdev);
1028
1029 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1030 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1031
1032 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
1033 rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1034 if (rdev->config.cayman.mem_row_size_in_kb > 4)
1035 rdev->config.cayman.mem_row_size_in_kb = 4;
1036 /* XXX use MC settings? */
1037 rdev->config.cayman.shader_engine_tile_size = 32;
1038 rdev->config.cayman.num_gpus = 1;
1039 rdev->config.cayman.multi_gpu_tile_size = 64;
1040
1041 tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
1042 rdev->config.cayman.num_tile_pipes = (1 << tmp);
1043 tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
1044 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
1045 tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
1046 rdev->config.cayman.num_shader_engines = tmp + 1;
1047 tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
1048 rdev->config.cayman.num_gpus = tmp + 1;
1049 tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
1050 rdev->config.cayman.multi_gpu_tile_size = 1 << tmp;
1051 tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
1052 rdev->config.cayman.mem_row_size_in_kb = 1 << tmp;
1053
1054
1055 /* setup tiling info dword. gb_addr_config is not adequate since it does
1056 * not have bank info, so create a custom tiling dword.
1057 * bits 3:0 num_pipes
1058 * bits 7:4 num_banks
1059 * bits 11:8 group_size
1060 * bits 15:12 row_size
1061 */
1062 rdev->config.cayman.tile_config = 0;
1063 switch (rdev->config.cayman.num_tile_pipes) {
1064 case 1:
1065 default:
1066 rdev->config.cayman.tile_config |= (0 << 0);
1067 break;
1068 case 2:
1069 rdev->config.cayman.tile_config |= (1 << 0);
1070 break;
1071 case 4:
1072 rdev->config.cayman.tile_config |= (2 << 0);
1073 break;
1074 case 8:
1075 rdev->config.cayman.tile_config |= (3 << 0);
1076 break;
1077 }
1078
1079 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
1080 if (rdev->flags & RADEON_IS_IGP)
1081 rdev->config.cayman.tile_config |= 1 << 4;
1082 else {
1083 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
1084 case 0: /* four banks */
1085 rdev->config.cayman.tile_config |= 0 << 4;
1086 break;
1087 case 1: /* eight banks */
1088 rdev->config.cayman.tile_config |= 1 << 4;
1089 break;
1090 case 2: /* sixteen banks */
1091 default:
1092 rdev->config.cayman.tile_config |= 2 << 4;
1093 break;
1094 }
1095 }
1096 rdev->config.cayman.tile_config |=
1097 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
1098 rdev->config.cayman.tile_config |=
1099 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
1100
1101 tmp = 0;
1102 for (i = (rdev->config.cayman.max_shader_engines - 1); i >= 0; i--) {
1103 u32 rb_disable_bitmap;
1104
1105 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1106 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1107 rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;
1108 tmp <<= 4;
1109 tmp |= rb_disable_bitmap;
1110 }
1111 /* enabled rb are just the one not disabled :) */
1112 disabled_rb_mask = tmp;
1113 tmp = 0;
1114 for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++)
1115 tmp |= (1 << i);
1116 /* if all the backends are disabled, fix it up here */
1117 if ((disabled_rb_mask & tmp) == tmp) {
1118 for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++)
1119 disabled_rb_mask &= ~(1 << i);
1120 }
1121
1122 for (i = 0; i < rdev->config.cayman.max_shader_engines; i++) {
1123 u32 simd_disable_bitmap;
1124
1125 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1126 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1127 simd_disable_bitmap = (RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffff0000) >> 16;
1128 simd_disable_bitmap |= 0xffffffff << rdev->config.cayman.max_simds_per_se;
1129 tmp <<= 16;
1130 tmp |= simd_disable_bitmap;
1131 }
1132 rdev->config.cayman.active_simds = hweight32(~tmp);
1133
1134 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
1135 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
1136
1137 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1138 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1139 if (ASIC_IS_DCE6(rdev))
1140 WREG32(DMIF_ADDR_CALC, gb_addr_config);
1141 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1142 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1143 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
1144 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
1145 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
1146 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
1147
1148 if ((rdev->config.cayman.max_backends_per_se == 1) &&
1149 (rdev->flags & RADEON_IS_IGP)) {
1150 if ((disabled_rb_mask & 3) == 2) {
1151 /* RB1 disabled, RB0 enabled */
1152 tmp = 0x00000000;
1153 } else {
1154 /* RB0 disabled, RB1 enabled */
1155 tmp = 0x11111111;
1156 }
1157 } else {
1158 tmp = gb_addr_config & NUM_PIPES_MASK;
1159 tmp = r6xx_remap_render_backend(rdev, tmp,
1160 rdev->config.cayman.max_backends_per_se *
1161 rdev->config.cayman.max_shader_engines,
1162 CAYMAN_MAX_BACKENDS, disabled_rb_mask);
1163 }
1164 WREG32(GB_BACKEND_MAP, tmp);
1165
1166 cgts_tcc_disable = 0xffff0000;
1167 for (i = 0; i < rdev->config.cayman.max_texture_channel_caches; i++)
1168 cgts_tcc_disable &= ~(1 << (16 + i));
1169 WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);
1170 WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable);
1171 WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable);
1172 WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable);
1173
1174 /* reprogram the shader complex */
1175 cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG);
1176 for (i = 0; i < 16; i++)
1177 WREG32(CGTS_SM_CTRL_REG, OVERRIDE);
1178 WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);
1179
1180 /* set HW defaults for 3D engine */
1181 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
1182
1183 sx_debug_1 = RREG32(SX_DEBUG_1);
1184 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
1185 WREG32(SX_DEBUG_1, sx_debug_1);
1186
1187 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
1188 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
1189 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets);
1190 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
1191
1192 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE);
1193
1194 /* need to be explicitly zero-ed */
1195 WREG32(VGT_OFFCHIP_LDS_BASE, 0);
1196 WREG32(SQ_LSTMP_RING_BASE, 0);
1197 WREG32(SQ_HSTMP_RING_BASE, 0);
1198 WREG32(SQ_ESTMP_RING_BASE, 0);
1199 WREG32(SQ_GSTMP_RING_BASE, 0);
1200 WREG32(SQ_VSTMP_RING_BASE, 0);
1201 WREG32(SQ_PSTMP_RING_BASE, 0);
1202
1203 WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO);
1204
1205 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) |
1206 POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) |
1207 SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1)));
1208
1209 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) |
1210 SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) |
1211 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size)));
1212
1213
1214 WREG32(VGT_NUM_INSTANCES, 1);
1215
1216 WREG32(CP_PERFMON_CNTL, 0);
1217
1218 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) |
1219 FETCH_FIFO_HIWATER(0x4) |
1220 DONE_FIFO_HIWATER(0xe0) |
1221 ALU_UPDATE_FIFO_HIWATER(0x8)));
1222
1223 WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4));
1224 WREG32(SQ_CONFIG, (VC_ENABLE |
1225 EXPORT_SRC_C |
1226 GFX_PRIO(0) |
1227 CS1_PRIO(0) |
1228 CS2_PRIO(1)));
1229 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE);
1230
1231 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1232 FORCE_EOV_MAX_REZ_CNT(255)));
1233
1234 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
1235 AUTO_INVLD_EN(ES_AND_GS_AUTO));
1236
1237 WREG32(VGT_GS_VERTEX_REUSE, 16);
1238 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1239
1240 WREG32(CB_PERF_CTR0_SEL_0, 0);
1241 WREG32(CB_PERF_CTR0_SEL_1, 0);
1242 WREG32(CB_PERF_CTR1_SEL_0, 0);
1243 WREG32(CB_PERF_CTR1_SEL_1, 0);
1244 WREG32(CB_PERF_CTR2_SEL_0, 0);
1245 WREG32(CB_PERF_CTR2_SEL_1, 0);
1246 WREG32(CB_PERF_CTR3_SEL_0, 0);
1247 WREG32(CB_PERF_CTR3_SEL_1, 0);
1248
1249 tmp = RREG32(HDP_MISC_CNTL);
1250 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
1251 WREG32(HDP_MISC_CNTL, tmp);
1252
1253 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1254 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1255
1256 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
1257
1258 udelay(50);
1259
1260 /* set clockgating golden values on TN */
1261 if (rdev->family == CHIP_ARUBA) {
1262 tmp = RREG32_CG(CG_CGTT_LOCAL_0);
1263 tmp &= ~0x00380000;
1264 WREG32_CG(CG_CGTT_LOCAL_0, tmp);
1265 tmp = RREG32_CG(CG_CGTT_LOCAL_1);
1266 tmp &= ~0x0e000000;
1267 WREG32_CG(CG_CGTT_LOCAL_1, tmp);
1268 }
1269 }
1270
1271 /*
1272 * GART
1273 */
cayman_pcie_gart_tlb_flush(struct radeon_device * rdev)1274 void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev)
1275 {
1276 /* flush hdp cache */
1277 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1278
1279 /* bits 0-7 are the VM contexts0-7 */
1280 WREG32(VM_INVALIDATE_REQUEST, 1);
1281 }
1282
cayman_pcie_gart_enable(struct radeon_device * rdev)1283 static int cayman_pcie_gart_enable(struct radeon_device *rdev)
1284 {
1285 int i, r;
1286
1287 if (rdev->gart.robj == NULL) {
1288 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
1289 return -EINVAL;
1290 }
1291 r = radeon_gart_table_vram_pin(rdev);
1292 if (r)
1293 return r;
1294 /* Setup TLB control */
1295 WREG32(MC_VM_MX_L1_TLB_CNTL,
1296 (0xA << 7) |
1297 ENABLE_L1_TLB |
1298 ENABLE_L1_FRAGMENT_PROCESSING |
1299 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1300 ENABLE_ADVANCED_DRIVER_MODEL |
1301 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
1302 /* Setup L2 cache */
1303 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
1304 ENABLE_L2_FRAGMENT_PROCESSING |
1305 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1306 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
1307 EFFECTIVE_L2_QUEUE_SIZE(7) |
1308 CONTEXT1_IDENTITY_ACCESS_MODE(1));
1309 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
1310 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
1311 BANK_SELECT(6) |
1312 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
1313 /* setup context0 */
1314 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1315 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1316 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1317 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1318 (u32)(rdev->dummy_page.addr >> 12));
1319 WREG32(VM_CONTEXT0_CNTL2, 0);
1320 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1321 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1322
1323 WREG32(0x15D4, 0);
1324 WREG32(0x15D8, 0);
1325 WREG32(0x15DC, 0);
1326
1327 /* empty context1-7 */
1328 /* Assign the pt base to something valid for now; the pts used for
1329 * the VMs are determined by the application and setup and assigned
1330 * on the fly in the vm part of radeon_gart.c
1331 */
1332 for (i = 1; i < 8; i++) {
1333 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0);
1334 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2),
1335 rdev->vm_manager.max_pfn - 1);
1336 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
1337 rdev->vm_manager.saved_table_addr[i]);
1338 }
1339
1340 /* enable context1-7 */
1341 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
1342 (u32)(rdev->dummy_page.addr >> 12));
1343 WREG32(VM_CONTEXT1_CNTL2, 4);
1344 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
1345 PAGE_TABLE_BLOCK_SIZE(radeon_vm_block_size - 9) |
1346 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
1347 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
1348 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
1349 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT |
1350 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT |
1351 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT |
1352 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT |
1353 VALID_PROTECTION_FAULT_ENABLE_DEFAULT |
1354 READ_PROTECTION_FAULT_ENABLE_INTERRUPT |
1355 READ_PROTECTION_FAULT_ENABLE_DEFAULT |
1356 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
1357 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
1358
1359 cayman_pcie_gart_tlb_flush(rdev);
1360 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1361 (unsigned)(rdev->mc.gtt_size >> 20),
1362 (unsigned long long)rdev->gart.table_addr);
1363 rdev->gart.ready = true;
1364 return 0;
1365 }
1366
cayman_pcie_gart_disable(struct radeon_device * rdev)1367 static void cayman_pcie_gart_disable(struct radeon_device *rdev)
1368 {
1369 unsigned i;
1370
1371 for (i = 1; i < 8; ++i) {
1372 rdev->vm_manager.saved_table_addr[i] = RREG32(
1373 VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2));
1374 }
1375
1376 /* Disable all tables */
1377 WREG32(VM_CONTEXT0_CNTL, 0);
1378 WREG32(VM_CONTEXT1_CNTL, 0);
1379 /* Setup TLB control */
1380 WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING |
1381 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1382 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
1383 /* Setup L2 cache */
1384 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1385 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
1386 EFFECTIVE_L2_QUEUE_SIZE(7) |
1387 CONTEXT1_IDENTITY_ACCESS_MODE(1));
1388 WREG32(VM_L2_CNTL2, 0);
1389 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
1390 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
1391 radeon_gart_table_vram_unpin(rdev);
1392 }
1393
cayman_pcie_gart_fini(struct radeon_device * rdev)1394 static void cayman_pcie_gart_fini(struct radeon_device *rdev)
1395 {
1396 cayman_pcie_gart_disable(rdev);
1397 radeon_gart_table_vram_free(rdev);
1398 radeon_gart_fini(rdev);
1399 }
1400
cayman_cp_int_cntl_setup(struct radeon_device * rdev,int ring,u32 cp_int_cntl)1401 void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
1402 int ring, u32 cp_int_cntl)
1403 {
1404 WREG32(SRBM_GFX_CNTL, RINGID(ring));
1405 WREG32(CP_INT_CNTL, cp_int_cntl);
1406 }
1407
1408 /*
1409 * CP.
1410 */
cayman_fence_ring_emit(struct radeon_device * rdev,struct radeon_fence * fence)1411 void cayman_fence_ring_emit(struct radeon_device *rdev,
1412 struct radeon_fence *fence)
1413 {
1414 struct radeon_ring *ring = &rdev->ring[fence->ring];
1415 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
1416 u32 cp_coher_cntl = PACKET3_FULL_CACHE_ENA | PACKET3_TC_ACTION_ENA |
1417 PACKET3_SH_ACTION_ENA;
1418
1419 /* flush read cache over gart for this vmid */
1420 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1421 radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl);
1422 radeon_ring_write(ring, 0xFFFFFFFF);
1423 radeon_ring_write(ring, 0);
1424 radeon_ring_write(ring, 10); /* poll interval */
1425 /* EVENT_WRITE_EOP - flush caches, send int */
1426 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1427 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
1428 radeon_ring_write(ring, lower_32_bits(addr));
1429 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
1430 radeon_ring_write(ring, fence->seq);
1431 radeon_ring_write(ring, 0);
1432 }
1433
cayman_ring_ib_execute(struct radeon_device * rdev,struct radeon_ib * ib)1434 void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1435 {
1436 struct radeon_ring *ring = &rdev->ring[ib->ring];
1437 unsigned vm_id = ib->vm ? ib->vm->ids[ib->ring].id : 0;
1438 u32 cp_coher_cntl = PACKET3_FULL_CACHE_ENA | PACKET3_TC_ACTION_ENA |
1439 PACKET3_SH_ACTION_ENA;
1440
1441 /* set to DX10/11 mode */
1442 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
1443 radeon_ring_write(ring, 1);
1444
1445 if (ring->rptr_save_reg) {
1446 uint32_t next_rptr = ring->wptr + 3 + 4 + 8;
1447 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1448 radeon_ring_write(ring, ((ring->rptr_save_reg -
1449 PACKET3_SET_CONFIG_REG_START) >> 2));
1450 radeon_ring_write(ring, next_rptr);
1451 }
1452
1453 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1454 radeon_ring_write(ring,
1455 #ifdef __BIG_ENDIAN
1456 (2 << 0) |
1457 #endif
1458 (ib->gpu_addr & 0xFFFFFFFC));
1459 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
1460 radeon_ring_write(ring, ib->length_dw | (vm_id << 24));
1461
1462 /* flush read cache over gart for this vmid */
1463 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1464 radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl);
1465 radeon_ring_write(ring, 0xFFFFFFFF);
1466 radeon_ring_write(ring, 0);
1467 radeon_ring_write(ring, (vm_id << 24) | 10); /* poll interval */
1468 }
1469
cayman_cp_enable(struct radeon_device * rdev,bool enable)1470 static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
1471 {
1472 if (enable)
1473 WREG32(CP_ME_CNTL, 0);
1474 else {
1475 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
1476 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1477 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
1478 WREG32(SCRATCH_UMSK, 0);
1479 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1480 }
1481 }
1482
cayman_gfx_get_rptr(struct radeon_device * rdev,struct radeon_ring * ring)1483 u32 cayman_gfx_get_rptr(struct radeon_device *rdev,
1484 struct radeon_ring *ring)
1485 {
1486 u32 rptr;
1487
1488 if (rdev->wb.enabled)
1489 rptr = rdev->wb.wb[ring->rptr_offs/4];
1490 else {
1491 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX)
1492 rptr = RREG32(CP_RB0_RPTR);
1493 else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX)
1494 rptr = RREG32(CP_RB1_RPTR);
1495 else
1496 rptr = RREG32(CP_RB2_RPTR);
1497 }
1498
1499 return rptr;
1500 }
1501
cayman_gfx_get_wptr(struct radeon_device * rdev,struct radeon_ring * ring)1502 u32 cayman_gfx_get_wptr(struct radeon_device *rdev,
1503 struct radeon_ring *ring)
1504 {
1505 u32 wptr;
1506
1507 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX)
1508 wptr = RREG32(CP_RB0_WPTR);
1509 else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX)
1510 wptr = RREG32(CP_RB1_WPTR);
1511 else
1512 wptr = RREG32(CP_RB2_WPTR);
1513
1514 return wptr;
1515 }
1516
cayman_gfx_set_wptr(struct radeon_device * rdev,struct radeon_ring * ring)1517 void cayman_gfx_set_wptr(struct radeon_device *rdev,
1518 struct radeon_ring *ring)
1519 {
1520 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX) {
1521 WREG32(CP_RB0_WPTR, ring->wptr);
1522 (void)RREG32(CP_RB0_WPTR);
1523 } else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX) {
1524 WREG32(CP_RB1_WPTR, ring->wptr);
1525 (void)RREG32(CP_RB1_WPTR);
1526 } else {
1527 WREG32(CP_RB2_WPTR, ring->wptr);
1528 (void)RREG32(CP_RB2_WPTR);
1529 }
1530 }
1531
cayman_cp_load_microcode(struct radeon_device * rdev)1532 static int cayman_cp_load_microcode(struct radeon_device *rdev)
1533 {
1534 const __be32 *fw_data;
1535 int i;
1536
1537 if (!rdev->me_fw || !rdev->pfp_fw)
1538 return -EINVAL;
1539
1540 cayman_cp_enable(rdev, false);
1541
1542 fw_data = (const __be32 *)rdev->pfp_fw->data;
1543 WREG32(CP_PFP_UCODE_ADDR, 0);
1544 for (i = 0; i < CAYMAN_PFP_UCODE_SIZE; i++)
1545 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1546 WREG32(CP_PFP_UCODE_ADDR, 0);
1547
1548 fw_data = (const __be32 *)rdev->me_fw->data;
1549 WREG32(CP_ME_RAM_WADDR, 0);
1550 for (i = 0; i < CAYMAN_PM4_UCODE_SIZE; i++)
1551 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1552
1553 WREG32(CP_PFP_UCODE_ADDR, 0);
1554 WREG32(CP_ME_RAM_WADDR, 0);
1555 WREG32(CP_ME_RAM_RADDR, 0);
1556 return 0;
1557 }
1558
cayman_cp_start(struct radeon_device * rdev)1559 static int cayman_cp_start(struct radeon_device *rdev)
1560 {
1561 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1562 int r, i;
1563
1564 r = radeon_ring_lock(rdev, ring, 7);
1565 if (r) {
1566 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1567 return r;
1568 }
1569 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1570 radeon_ring_write(ring, 0x1);
1571 radeon_ring_write(ring, 0x0);
1572 radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1);
1573 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1574 radeon_ring_write(ring, 0);
1575 radeon_ring_write(ring, 0);
1576 radeon_ring_unlock_commit(rdev, ring, false);
1577
1578 cayman_cp_enable(rdev, true);
1579
1580 r = radeon_ring_lock(rdev, ring, cayman_default_size + 19);
1581 if (r) {
1582 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1583 return r;
1584 }
1585
1586 /* setup clear context state */
1587 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1588 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1589
1590 for (i = 0; i < cayman_default_size; i++)
1591 radeon_ring_write(ring, cayman_default_state[i]);
1592
1593 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1594 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1595
1596 /* set clear context state */
1597 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1598 radeon_ring_write(ring, 0);
1599
1600 /* SQ_VTX_BASE_VTX_LOC */
1601 radeon_ring_write(ring, 0xc0026f00);
1602 radeon_ring_write(ring, 0x00000000);
1603 radeon_ring_write(ring, 0x00000000);
1604 radeon_ring_write(ring, 0x00000000);
1605
1606 /* Clear consts */
1607 radeon_ring_write(ring, 0xc0036f00);
1608 radeon_ring_write(ring, 0x00000bc4);
1609 radeon_ring_write(ring, 0xffffffff);
1610 radeon_ring_write(ring, 0xffffffff);
1611 radeon_ring_write(ring, 0xffffffff);
1612
1613 radeon_ring_write(ring, 0xc0026900);
1614 radeon_ring_write(ring, 0x00000316);
1615 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1616 radeon_ring_write(ring, 0x00000010); /* */
1617
1618 radeon_ring_unlock_commit(rdev, ring, false);
1619
1620 /* XXX init other rings */
1621
1622 return 0;
1623 }
1624
cayman_cp_fini(struct radeon_device * rdev)1625 static void cayman_cp_fini(struct radeon_device *rdev)
1626 {
1627 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1628 cayman_cp_enable(rdev, false);
1629 radeon_ring_fini(rdev, ring);
1630 radeon_scratch_free(rdev, ring->rptr_save_reg);
1631 }
1632
cayman_cp_resume(struct radeon_device * rdev)1633 static int cayman_cp_resume(struct radeon_device *rdev)
1634 {
1635 static const int ridx[] = {
1636 RADEON_RING_TYPE_GFX_INDEX,
1637 CAYMAN_RING_TYPE_CP1_INDEX,
1638 CAYMAN_RING_TYPE_CP2_INDEX
1639 };
1640 static const unsigned cp_rb_cntl[] = {
1641 CP_RB0_CNTL,
1642 CP_RB1_CNTL,
1643 CP_RB2_CNTL,
1644 };
1645 static const unsigned cp_rb_rptr_addr[] = {
1646 CP_RB0_RPTR_ADDR,
1647 CP_RB1_RPTR_ADDR,
1648 CP_RB2_RPTR_ADDR
1649 };
1650 static const unsigned cp_rb_rptr_addr_hi[] = {
1651 CP_RB0_RPTR_ADDR_HI,
1652 CP_RB1_RPTR_ADDR_HI,
1653 CP_RB2_RPTR_ADDR_HI
1654 };
1655 static const unsigned cp_rb_base[] = {
1656 CP_RB0_BASE,
1657 CP_RB1_BASE,
1658 CP_RB2_BASE
1659 };
1660 static const unsigned cp_rb_rptr[] = {
1661 CP_RB0_RPTR,
1662 CP_RB1_RPTR,
1663 CP_RB2_RPTR
1664 };
1665 static const unsigned cp_rb_wptr[] = {
1666 CP_RB0_WPTR,
1667 CP_RB1_WPTR,
1668 CP_RB2_WPTR
1669 };
1670 struct radeon_ring *ring;
1671 int i, r;
1672
1673 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1674 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1675 SOFT_RESET_PA |
1676 SOFT_RESET_SH |
1677 SOFT_RESET_VGT |
1678 SOFT_RESET_SPI |
1679 SOFT_RESET_SX));
1680 RREG32(GRBM_SOFT_RESET);
1681 mdelay(15);
1682 WREG32(GRBM_SOFT_RESET, 0);
1683 RREG32(GRBM_SOFT_RESET);
1684
1685 WREG32(CP_SEM_WAIT_TIMER, 0x0);
1686 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1687
1688 /* Set the write pointer delay */
1689 WREG32(CP_RB_WPTR_DELAY, 0);
1690
1691 WREG32(CP_DEBUG, (1 << 27));
1692
1693 /* set the wb address whether it's enabled or not */
1694 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1695 WREG32(SCRATCH_UMSK, 0xff);
1696
1697 for (i = 0; i < 3; ++i) {
1698 uint32_t rb_cntl;
1699 uint64_t addr;
1700
1701 /* Set ring buffer size */
1702 ring = &rdev->ring[ridx[i]];
1703 rb_cntl = order_base_2(ring->ring_size / 8);
1704 rb_cntl |= order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8;
1705 #ifdef __BIG_ENDIAN
1706 rb_cntl |= BUF_SWAP_32BIT;
1707 #endif
1708 WREG32(cp_rb_cntl[i], rb_cntl);
1709
1710 /* set the wb address whether it's enabled or not */
1711 addr = rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET;
1712 WREG32(cp_rb_rptr_addr[i], addr & 0xFFFFFFFC);
1713 WREG32(cp_rb_rptr_addr_hi[i], upper_32_bits(addr) & 0xFF);
1714 }
1715
1716 /* set the rb base addr, this causes an internal reset of ALL rings */
1717 for (i = 0; i < 3; ++i) {
1718 ring = &rdev->ring[ridx[i]];
1719 WREG32(cp_rb_base[i], ring->gpu_addr >> 8);
1720 }
1721
1722 for (i = 0; i < 3; ++i) {
1723 /* Initialize the ring buffer's read and write pointers */
1724 ring = &rdev->ring[ridx[i]];
1725 WREG32_P(cp_rb_cntl[i], RB_RPTR_WR_ENA, ~RB_RPTR_WR_ENA);
1726
1727 ring->wptr = 0;
1728 WREG32(cp_rb_rptr[i], 0);
1729 WREG32(cp_rb_wptr[i], ring->wptr);
1730
1731 mdelay(1);
1732 WREG32_P(cp_rb_cntl[i], 0, ~RB_RPTR_WR_ENA);
1733 }
1734
1735 /* start the rings */
1736 cayman_cp_start(rdev);
1737 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
1738 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1739 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
1740 /* this only test cp0 */
1741 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1742 if (r) {
1743 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1744 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1745 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
1746 return r;
1747 }
1748
1749 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
1750 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1751
1752 return 0;
1753 }
1754
cayman_gpu_check_soft_reset(struct radeon_device * rdev)1755 u32 cayman_gpu_check_soft_reset(struct radeon_device *rdev)
1756 {
1757 u32 reset_mask = 0;
1758 u32 tmp;
1759
1760 /* GRBM_STATUS */
1761 tmp = RREG32(GRBM_STATUS);
1762 if (tmp & (PA_BUSY | SC_BUSY |
1763 SH_BUSY | SX_BUSY |
1764 TA_BUSY | VGT_BUSY |
1765 DB_BUSY | CB_BUSY |
1766 GDS_BUSY | SPI_BUSY |
1767 IA_BUSY | IA_BUSY_NO_DMA))
1768 reset_mask |= RADEON_RESET_GFX;
1769
1770 if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
1771 CP_BUSY | CP_COHERENCY_BUSY))
1772 reset_mask |= RADEON_RESET_CP;
1773
1774 if (tmp & GRBM_EE_BUSY)
1775 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
1776
1777 /* DMA_STATUS_REG 0 */
1778 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
1779 if (!(tmp & DMA_IDLE))
1780 reset_mask |= RADEON_RESET_DMA;
1781
1782 /* DMA_STATUS_REG 1 */
1783 tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);
1784 if (!(tmp & DMA_IDLE))
1785 reset_mask |= RADEON_RESET_DMA1;
1786
1787 /* SRBM_STATUS2 */
1788 tmp = RREG32(SRBM_STATUS2);
1789 if (tmp & DMA_BUSY)
1790 reset_mask |= RADEON_RESET_DMA;
1791
1792 if (tmp & DMA1_BUSY)
1793 reset_mask |= RADEON_RESET_DMA1;
1794
1795 /* SRBM_STATUS */
1796 tmp = RREG32(SRBM_STATUS);
1797 if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
1798 reset_mask |= RADEON_RESET_RLC;
1799
1800 if (tmp & IH_BUSY)
1801 reset_mask |= RADEON_RESET_IH;
1802
1803 if (tmp & SEM_BUSY)
1804 reset_mask |= RADEON_RESET_SEM;
1805
1806 if (tmp & GRBM_RQ_PENDING)
1807 reset_mask |= RADEON_RESET_GRBM;
1808
1809 if (tmp & VMC_BUSY)
1810 reset_mask |= RADEON_RESET_VMC;
1811
1812 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
1813 MCC_BUSY | MCD_BUSY))
1814 reset_mask |= RADEON_RESET_MC;
1815
1816 if (evergreen_is_display_hung(rdev))
1817 reset_mask |= RADEON_RESET_DISPLAY;
1818
1819 /* VM_L2_STATUS */
1820 tmp = RREG32(VM_L2_STATUS);
1821 if (tmp & L2_BUSY)
1822 reset_mask |= RADEON_RESET_VMC;
1823
1824 /* Skip MC reset as it's mostly likely not hung, just busy */
1825 if (reset_mask & RADEON_RESET_MC) {
1826 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
1827 reset_mask &= ~RADEON_RESET_MC;
1828 }
1829
1830 return reset_mask;
1831 }
1832
cayman_gpu_soft_reset(struct radeon_device * rdev,u32 reset_mask)1833 static void cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
1834 {
1835 struct evergreen_mc_save save;
1836 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
1837 u32 tmp;
1838
1839 if (reset_mask == 0)
1840 return;
1841
1842 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
1843
1844 evergreen_print_gpu_status_regs(rdev);
1845 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n",
1846 RREG32(0x14F8));
1847 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",
1848 RREG32(0x14D8));
1849 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1850 RREG32(0x14FC));
1851 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1852 RREG32(0x14DC));
1853
1854 /* Disable CP parsing/prefetching */
1855 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
1856
1857 if (reset_mask & RADEON_RESET_DMA) {
1858 /* dma0 */
1859 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
1860 tmp &= ~DMA_RB_ENABLE;
1861 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
1862 }
1863
1864 if (reset_mask & RADEON_RESET_DMA1) {
1865 /* dma1 */
1866 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
1867 tmp &= ~DMA_RB_ENABLE;
1868 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
1869 }
1870
1871 udelay(50);
1872
1873 evergreen_mc_stop(rdev, &save);
1874 if (evergreen_mc_wait_for_idle(rdev)) {
1875 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1876 }
1877
1878 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {
1879 grbm_soft_reset = SOFT_RESET_CB |
1880 SOFT_RESET_DB |
1881 SOFT_RESET_GDS |
1882 SOFT_RESET_PA |
1883 SOFT_RESET_SC |
1884 SOFT_RESET_SPI |
1885 SOFT_RESET_SH |
1886 SOFT_RESET_SX |
1887 SOFT_RESET_TC |
1888 SOFT_RESET_TA |
1889 SOFT_RESET_VGT |
1890 SOFT_RESET_IA;
1891 }
1892
1893 if (reset_mask & RADEON_RESET_CP) {
1894 grbm_soft_reset |= SOFT_RESET_CP | SOFT_RESET_VGT;
1895
1896 srbm_soft_reset |= SOFT_RESET_GRBM;
1897 }
1898
1899 if (reset_mask & RADEON_RESET_DMA)
1900 srbm_soft_reset |= SOFT_RESET_DMA;
1901
1902 if (reset_mask & RADEON_RESET_DMA1)
1903 srbm_soft_reset |= SOFT_RESET_DMA1;
1904
1905 if (reset_mask & RADEON_RESET_DISPLAY)
1906 srbm_soft_reset |= SOFT_RESET_DC;
1907
1908 if (reset_mask & RADEON_RESET_RLC)
1909 srbm_soft_reset |= SOFT_RESET_RLC;
1910
1911 if (reset_mask & RADEON_RESET_SEM)
1912 srbm_soft_reset |= SOFT_RESET_SEM;
1913
1914 if (reset_mask & RADEON_RESET_IH)
1915 srbm_soft_reset |= SOFT_RESET_IH;
1916
1917 if (reset_mask & RADEON_RESET_GRBM)
1918 srbm_soft_reset |= SOFT_RESET_GRBM;
1919
1920 if (reset_mask & RADEON_RESET_VMC)
1921 srbm_soft_reset |= SOFT_RESET_VMC;
1922
1923 if (!(rdev->flags & RADEON_IS_IGP)) {
1924 if (reset_mask & RADEON_RESET_MC)
1925 srbm_soft_reset |= SOFT_RESET_MC;
1926 }
1927
1928 if (grbm_soft_reset) {
1929 tmp = RREG32(GRBM_SOFT_RESET);
1930 tmp |= grbm_soft_reset;
1931 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
1932 WREG32(GRBM_SOFT_RESET, tmp);
1933 tmp = RREG32(GRBM_SOFT_RESET);
1934
1935 udelay(50);
1936
1937 tmp &= ~grbm_soft_reset;
1938 WREG32(GRBM_SOFT_RESET, tmp);
1939 tmp = RREG32(GRBM_SOFT_RESET);
1940 }
1941
1942 if (srbm_soft_reset) {
1943 tmp = RREG32(SRBM_SOFT_RESET);
1944 tmp |= srbm_soft_reset;
1945 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1946 WREG32(SRBM_SOFT_RESET, tmp);
1947 tmp = RREG32(SRBM_SOFT_RESET);
1948
1949 udelay(50);
1950
1951 tmp &= ~srbm_soft_reset;
1952 WREG32(SRBM_SOFT_RESET, tmp);
1953 tmp = RREG32(SRBM_SOFT_RESET);
1954 }
1955
1956 /* Wait a little for things to settle down */
1957 udelay(50);
1958
1959 evergreen_mc_resume(rdev, &save);
1960 udelay(50);
1961
1962 evergreen_print_gpu_status_regs(rdev);
1963 }
1964
cayman_asic_reset(struct radeon_device * rdev,bool hard)1965 int cayman_asic_reset(struct radeon_device *rdev, bool hard)
1966 {
1967 u32 reset_mask;
1968
1969 if (hard) {
1970 evergreen_gpu_pci_config_reset(rdev);
1971 return 0;
1972 }
1973
1974 reset_mask = cayman_gpu_check_soft_reset(rdev);
1975
1976 if (reset_mask)
1977 r600_set_bios_scratch_engine_hung(rdev, true);
1978
1979 cayman_gpu_soft_reset(rdev, reset_mask);
1980
1981 reset_mask = cayman_gpu_check_soft_reset(rdev);
1982
1983 if (reset_mask)
1984 evergreen_gpu_pci_config_reset(rdev);
1985
1986 r600_set_bios_scratch_engine_hung(rdev, false);
1987
1988 return 0;
1989 }
1990
1991 /**
1992 * cayman_gfx_is_lockup - Check if the GFX engine is locked up
1993 *
1994 * @rdev: radeon_device pointer
1995 * @ring: radeon_ring structure holding ring information
1996 *
1997 * Check if the GFX engine is locked up.
1998 * Returns true if the engine appears to be locked up, false if not.
1999 */
cayman_gfx_is_lockup(struct radeon_device * rdev,struct radeon_ring * ring)2000 bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2001 {
2002 u32 reset_mask = cayman_gpu_check_soft_reset(rdev);
2003
2004 if (!(reset_mask & (RADEON_RESET_GFX |
2005 RADEON_RESET_COMPUTE |
2006 RADEON_RESET_CP))) {
2007 radeon_ring_lockup_update(rdev, ring);
2008 return false;
2009 }
2010 return radeon_ring_test_lockup(rdev, ring);
2011 }
2012
cayman_uvd_init(struct radeon_device * rdev)2013 static void cayman_uvd_init(struct radeon_device *rdev)
2014 {
2015 int r;
2016
2017 if (!rdev->has_uvd)
2018 return;
2019
2020 r = radeon_uvd_init(rdev);
2021 if (r) {
2022 dev_err(rdev->dev, "failed UVD (%d) init.\n", r);
2023 /*
2024 * At this point rdev->uvd.vcpu_bo is NULL which trickles down
2025 * to early fails uvd_v2_2_resume() and thus nothing happens
2026 * there. So it is pointless to try to go through that code
2027 * hence why we disable uvd here.
2028 */
2029 rdev->has_uvd = 0;
2030 return;
2031 }
2032 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;
2033 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096);
2034 }
2035
cayman_uvd_start(struct radeon_device * rdev)2036 static void cayman_uvd_start(struct radeon_device *rdev)
2037 {
2038 int r;
2039
2040 if (!rdev->has_uvd)
2041 return;
2042
2043 r = uvd_v2_2_resume(rdev);
2044 if (r) {
2045 dev_err(rdev->dev, "failed UVD resume (%d).\n", r);
2046 goto error;
2047 }
2048 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX);
2049 if (r) {
2050 dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r);
2051 goto error;
2052 }
2053 return;
2054
2055 error:
2056 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
2057 }
2058
cayman_uvd_resume(struct radeon_device * rdev)2059 static void cayman_uvd_resume(struct radeon_device *rdev)
2060 {
2061 struct radeon_ring *ring;
2062 int r;
2063
2064 if (!rdev->has_uvd || !rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size)
2065 return;
2066
2067 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
2068 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0));
2069 if (r) {
2070 dev_err(rdev->dev, "failed initializing UVD ring (%d).\n", r);
2071 return;
2072 }
2073 r = uvd_v1_0_init(rdev);
2074 if (r) {
2075 dev_err(rdev->dev, "failed initializing UVD (%d).\n", r);
2076 return;
2077 }
2078 }
2079
cayman_vce_init(struct radeon_device * rdev)2080 static void cayman_vce_init(struct radeon_device *rdev)
2081 {
2082 int r;
2083
2084 /* Only set for CHIP_ARUBA */
2085 if (!rdev->has_vce)
2086 return;
2087
2088 r = radeon_vce_init(rdev);
2089 if (r) {
2090 dev_err(rdev->dev, "failed VCE (%d) init.\n", r);
2091 /*
2092 * At this point rdev->vce.vcpu_bo is NULL which trickles down
2093 * to early fails cayman_vce_start() and thus nothing happens
2094 * there. So it is pointless to try to go through that code
2095 * hence why we disable vce here.
2096 */
2097 rdev->has_vce = 0;
2098 return;
2099 }
2100 rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_obj = NULL;
2101 r600_ring_init(rdev, &rdev->ring[TN_RING_TYPE_VCE1_INDEX], 4096);
2102 rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_obj = NULL;
2103 r600_ring_init(rdev, &rdev->ring[TN_RING_TYPE_VCE2_INDEX], 4096);
2104 }
2105
cayman_vce_start(struct radeon_device * rdev)2106 static void cayman_vce_start(struct radeon_device *rdev)
2107 {
2108 int r;
2109
2110 if (!rdev->has_vce)
2111 return;
2112
2113 r = radeon_vce_resume(rdev);
2114 if (r) {
2115 dev_err(rdev->dev, "failed VCE resume (%d).\n", r);
2116 goto error;
2117 }
2118 r = vce_v1_0_resume(rdev);
2119 if (r) {
2120 dev_err(rdev->dev, "failed VCE resume (%d).\n", r);
2121 goto error;
2122 }
2123 r = radeon_fence_driver_start_ring(rdev, TN_RING_TYPE_VCE1_INDEX);
2124 if (r) {
2125 dev_err(rdev->dev, "failed initializing VCE1 fences (%d).\n", r);
2126 goto error;
2127 }
2128 r = radeon_fence_driver_start_ring(rdev, TN_RING_TYPE_VCE2_INDEX);
2129 if (r) {
2130 dev_err(rdev->dev, "failed initializing VCE2 fences (%d).\n", r);
2131 goto error;
2132 }
2133 return;
2134
2135 error:
2136 rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size = 0;
2137 rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_size = 0;
2138 }
2139
cayman_vce_resume(struct radeon_device * rdev)2140 static void cayman_vce_resume(struct radeon_device *rdev)
2141 {
2142 struct radeon_ring *ring;
2143 int r;
2144
2145 if (!rdev->has_vce || !rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size)
2146 return;
2147
2148 ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX];
2149 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 0x0);
2150 if (r) {
2151 dev_err(rdev->dev, "failed initializing VCE1 ring (%d).\n", r);
2152 return;
2153 }
2154 ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX];
2155 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 0x0);
2156 if (r) {
2157 dev_err(rdev->dev, "failed initializing VCE1 ring (%d).\n", r);
2158 return;
2159 }
2160 r = vce_v1_0_init(rdev);
2161 if (r) {
2162 dev_err(rdev->dev, "failed initializing VCE (%d).\n", r);
2163 return;
2164 }
2165 }
2166
cayman_startup(struct radeon_device * rdev)2167 static int cayman_startup(struct radeon_device *rdev)
2168 {
2169 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2170 int r;
2171
2172 /* enable pcie gen2 link */
2173 evergreen_pcie_gen2_enable(rdev);
2174 /* enable aspm */
2175 evergreen_program_aspm(rdev);
2176
2177 /* scratch needs to be initialized before MC */
2178 r = r600_vram_scratch_init(rdev);
2179 if (r)
2180 return r;
2181
2182 evergreen_mc_program(rdev);
2183
2184 if (!(rdev->flags & RADEON_IS_IGP) && !rdev->pm.dpm_enabled) {
2185 r = ni_mc_load_microcode(rdev);
2186 if (r) {
2187 DRM_ERROR("Failed to load MC firmware!\n");
2188 return r;
2189 }
2190 }
2191
2192 r = cayman_pcie_gart_enable(rdev);
2193 if (r)
2194 return r;
2195 cayman_gpu_init(rdev);
2196
2197 /* allocate rlc buffers */
2198 if (rdev->flags & RADEON_IS_IGP) {
2199 rdev->rlc.reg_list = tn_rlc_save_restore_register_list;
2200 rdev->rlc.reg_list_size =
2201 (u32)ARRAY_SIZE(tn_rlc_save_restore_register_list);
2202 rdev->rlc.cs_data = cayman_cs_data;
2203 r = sumo_rlc_init(rdev);
2204 if (r) {
2205 DRM_ERROR("Failed to init rlc BOs!\n");
2206 return r;
2207 }
2208 }
2209
2210 /* allocate wb buffer */
2211 r = radeon_wb_init(rdev);
2212 if (r)
2213 return r;
2214
2215 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
2216 if (r) {
2217 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
2218 return r;
2219 }
2220
2221 cayman_uvd_start(rdev);
2222 cayman_vce_start(rdev);
2223
2224 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
2225 if (r) {
2226 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
2227 return r;
2228 }
2229
2230 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
2231 if (r) {
2232 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
2233 return r;
2234 }
2235
2236 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
2237 if (r) {
2238 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
2239 return r;
2240 }
2241
2242 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
2243 if (r) {
2244 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
2245 return r;
2246 }
2247
2248 /* Enable IRQ */
2249 if (!rdev->irq.installed) {
2250 r = radeon_irq_kms_init(rdev);
2251 if (r)
2252 return r;
2253 }
2254
2255 r = r600_irq_init(rdev);
2256 if (r) {
2257 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2258 radeon_irq_kms_fini(rdev);
2259 return r;
2260 }
2261 evergreen_irq_set(rdev);
2262
2263 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
2264 RADEON_CP_PACKET2);
2265 if (r)
2266 return r;
2267
2268 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
2269 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
2270 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
2271 if (r)
2272 return r;
2273
2274 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
2275 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
2276 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
2277 if (r)
2278 return r;
2279
2280 r = cayman_cp_load_microcode(rdev);
2281 if (r)
2282 return r;
2283 r = cayman_cp_resume(rdev);
2284 if (r)
2285 return r;
2286
2287 r = cayman_dma_resume(rdev);
2288 if (r)
2289 return r;
2290
2291 cayman_uvd_resume(rdev);
2292 cayman_vce_resume(rdev);
2293
2294 r = radeon_ib_pool_init(rdev);
2295 if (r) {
2296 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2297 return r;
2298 }
2299
2300 r = radeon_vm_manager_init(rdev);
2301 if (r) {
2302 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
2303 return r;
2304 }
2305
2306 r = radeon_audio_init(rdev);
2307 if (r)
2308 return r;
2309
2310 return 0;
2311 }
2312
cayman_resume(struct radeon_device * rdev)2313 int cayman_resume(struct radeon_device *rdev)
2314 {
2315 int r;
2316
2317 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
2318 * posting will perform necessary task to bring back GPU into good
2319 * shape.
2320 */
2321 /* post card */
2322 atom_asic_init(rdev->mode_info.atom_context);
2323
2324 /* init golden registers */
2325 ni_init_golden_registers(rdev);
2326
2327 if (rdev->pm.pm_method == PM_METHOD_DPM)
2328 radeon_pm_resume(rdev);
2329
2330 rdev->accel_working = true;
2331 r = cayman_startup(rdev);
2332 if (r) {
2333 DRM_ERROR("cayman startup failed on resume\n");
2334 rdev->accel_working = false;
2335 return r;
2336 }
2337 return r;
2338 }
2339
cayman_suspend(struct radeon_device * rdev)2340 int cayman_suspend(struct radeon_device *rdev)
2341 {
2342 radeon_pm_suspend(rdev);
2343 radeon_audio_fini(rdev);
2344 radeon_vm_manager_fini(rdev);
2345 cayman_cp_enable(rdev, false);
2346 cayman_dma_stop(rdev);
2347 if (rdev->has_uvd) {
2348 uvd_v1_0_fini(rdev);
2349 radeon_uvd_suspend(rdev);
2350 }
2351 evergreen_irq_suspend(rdev);
2352 radeon_wb_disable(rdev);
2353 cayman_pcie_gart_disable(rdev);
2354 return 0;
2355 }
2356
2357 /* Plan is to move initialization in that function and use
2358 * helper function so that radeon_device_init pretty much
2359 * do nothing more than calling asic specific function. This
2360 * should also allow to remove a bunch of callback function
2361 * like vram_info.
2362 */
cayman_init(struct radeon_device * rdev)2363 int cayman_init(struct radeon_device *rdev)
2364 {
2365 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2366 int r;
2367
2368 /* Read BIOS */
2369 if (!radeon_get_bios(rdev)) {
2370 if (ASIC_IS_AVIVO(rdev))
2371 return -EINVAL;
2372 }
2373 /* Must be an ATOMBIOS */
2374 if (!rdev->is_atom_bios) {
2375 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
2376 return -EINVAL;
2377 }
2378 r = radeon_atombios_init(rdev);
2379 if (r)
2380 return r;
2381
2382 /* Post card if necessary */
2383 if (!radeon_card_posted(rdev)) {
2384 if (!rdev->bios) {
2385 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2386 return -EINVAL;
2387 }
2388 DRM_INFO("GPU not posted. posting now...\n");
2389 atom_asic_init(rdev->mode_info.atom_context);
2390 }
2391 /* init golden registers */
2392 ni_init_golden_registers(rdev);
2393 /* Initialize scratch registers */
2394 r600_scratch_init(rdev);
2395 /* Initialize surface registers */
2396 radeon_surface_init(rdev);
2397 /* Initialize clocks */
2398 radeon_get_clock_info(rdev->ddev);
2399 /* Fence driver */
2400 r = radeon_fence_driver_init(rdev);
2401 if (r)
2402 return r;
2403 /* initialize memory controller */
2404 r = evergreen_mc_init(rdev);
2405 if (r)
2406 return r;
2407 /* Memory manager */
2408 r = radeon_bo_init(rdev);
2409 if (r)
2410 return r;
2411
2412 if (rdev->flags & RADEON_IS_IGP) {
2413 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2414 r = ni_init_microcode(rdev);
2415 if (r) {
2416 DRM_ERROR("Failed to load firmware!\n");
2417 return r;
2418 }
2419 }
2420 } else {
2421 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
2422 r = ni_init_microcode(rdev);
2423 if (r) {
2424 DRM_ERROR("Failed to load firmware!\n");
2425 return r;
2426 }
2427 }
2428 }
2429
2430 /* Initialize power management */
2431 radeon_pm_init(rdev);
2432
2433 ring->ring_obj = NULL;
2434 r600_ring_init(rdev, ring, 1024 * 1024);
2435
2436 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
2437 ring->ring_obj = NULL;
2438 r600_ring_init(rdev, ring, 64 * 1024);
2439
2440 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
2441 ring->ring_obj = NULL;
2442 r600_ring_init(rdev, ring, 64 * 1024);
2443
2444 cayman_uvd_init(rdev);
2445 cayman_vce_init(rdev);
2446
2447 rdev->ih.ring_obj = NULL;
2448 r600_ih_ring_init(rdev, 64 * 1024);
2449
2450 r = r600_pcie_gart_init(rdev);
2451 if (r)
2452 return r;
2453
2454 rdev->accel_working = true;
2455 r = cayman_startup(rdev);
2456 if (r) {
2457 dev_err(rdev->dev, "disabling GPU acceleration\n");
2458 cayman_cp_fini(rdev);
2459 cayman_dma_fini(rdev);
2460 r600_irq_fini(rdev);
2461 if (rdev->flags & RADEON_IS_IGP)
2462 sumo_rlc_fini(rdev);
2463 radeon_wb_fini(rdev);
2464 radeon_ib_pool_fini(rdev);
2465 radeon_vm_manager_fini(rdev);
2466 radeon_irq_kms_fini(rdev);
2467 cayman_pcie_gart_fini(rdev);
2468 rdev->accel_working = false;
2469 }
2470
2471 /* Don't start up if the MC ucode is missing.
2472 * The default clocks and voltages before the MC ucode
2473 * is loaded are not suffient for advanced operations.
2474 *
2475 * We can skip this check for TN, because there is no MC
2476 * ucode.
2477 */
2478 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
2479 DRM_ERROR("radeon: MC ucode required for NI+.\n");
2480 return -EINVAL;
2481 }
2482
2483 return 0;
2484 }
2485
cayman_fini(struct radeon_device * rdev)2486 void cayman_fini(struct radeon_device *rdev)
2487 {
2488 radeon_pm_fini(rdev);
2489 cayman_cp_fini(rdev);
2490 cayman_dma_fini(rdev);
2491 r600_irq_fini(rdev);
2492 if (rdev->flags & RADEON_IS_IGP)
2493 sumo_rlc_fini(rdev);
2494 radeon_wb_fini(rdev);
2495 radeon_vm_manager_fini(rdev);
2496 radeon_ib_pool_fini(rdev);
2497 radeon_irq_kms_fini(rdev);
2498 uvd_v1_0_fini(rdev);
2499 radeon_uvd_fini(rdev);
2500 if (rdev->has_vce)
2501 radeon_vce_fini(rdev);
2502 cayman_pcie_gart_fini(rdev);
2503 r600_vram_scratch_fini(rdev);
2504 radeon_gem_fini(rdev);
2505 radeon_fence_driver_fini(rdev);
2506 radeon_bo_fini(rdev);
2507 radeon_atombios_fini(rdev);
2508 ni_fini_microcode(rdev);
2509 kfree(rdev->bios);
2510 rdev->bios = NULL;
2511 }
2512
2513 /*
2514 * vm
2515 */
cayman_vm_init(struct radeon_device * rdev)2516 int cayman_vm_init(struct radeon_device *rdev)
2517 {
2518 /* number of VMs */
2519 rdev->vm_manager.nvm = 8;
2520 /* base offset of vram pages */
2521 if (rdev->flags & RADEON_IS_IGP) {
2522 u64 tmp = RREG32(FUS_MC_VM_FB_OFFSET);
2523 tmp <<= 22;
2524 rdev->vm_manager.vram_base_offset = tmp;
2525 } else
2526 rdev->vm_manager.vram_base_offset = 0;
2527 return 0;
2528 }
2529
cayman_vm_fini(struct radeon_device * rdev)2530 void cayman_vm_fini(struct radeon_device *rdev)
2531 {
2532 }
2533
2534 /**
2535 * cayman_vm_decode_fault - print human readable fault info
2536 *
2537 * @rdev: radeon_device pointer
2538 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
2539 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
2540 *
2541 * Print human readable fault information (cayman/TN).
2542 */
cayman_vm_decode_fault(struct radeon_device * rdev,u32 status,u32 addr)2543 void cayman_vm_decode_fault(struct radeon_device *rdev,
2544 u32 status, u32 addr)
2545 {
2546 u32 mc_id = (status & MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT;
2547 u32 vmid = (status & FAULT_VMID_MASK) >> FAULT_VMID_SHIFT;
2548 u32 protections = (status & PROTECTIONS_MASK) >> PROTECTIONS_SHIFT;
2549 char *block;
2550
2551 switch (mc_id) {
2552 case 32:
2553 case 16:
2554 case 96:
2555 case 80:
2556 case 160:
2557 case 144:
2558 case 224:
2559 case 208:
2560 block = "CB";
2561 break;
2562 case 33:
2563 case 17:
2564 case 97:
2565 case 81:
2566 case 161:
2567 case 145:
2568 case 225:
2569 case 209:
2570 block = "CB_FMASK";
2571 break;
2572 case 34:
2573 case 18:
2574 case 98:
2575 case 82:
2576 case 162:
2577 case 146:
2578 case 226:
2579 case 210:
2580 block = "CB_CMASK";
2581 break;
2582 case 35:
2583 case 19:
2584 case 99:
2585 case 83:
2586 case 163:
2587 case 147:
2588 case 227:
2589 case 211:
2590 block = "CB_IMMED";
2591 break;
2592 case 36:
2593 case 20:
2594 case 100:
2595 case 84:
2596 case 164:
2597 case 148:
2598 case 228:
2599 case 212:
2600 block = "DB";
2601 break;
2602 case 37:
2603 case 21:
2604 case 101:
2605 case 85:
2606 case 165:
2607 case 149:
2608 case 229:
2609 case 213:
2610 block = "DB_HTILE";
2611 break;
2612 case 38:
2613 case 22:
2614 case 102:
2615 case 86:
2616 case 166:
2617 case 150:
2618 case 230:
2619 case 214:
2620 block = "SX";
2621 break;
2622 case 39:
2623 case 23:
2624 case 103:
2625 case 87:
2626 case 167:
2627 case 151:
2628 case 231:
2629 case 215:
2630 block = "DB_STEN";
2631 break;
2632 case 40:
2633 case 24:
2634 case 104:
2635 case 88:
2636 case 232:
2637 case 216:
2638 case 168:
2639 case 152:
2640 block = "TC_TFETCH";
2641 break;
2642 case 41:
2643 case 25:
2644 case 105:
2645 case 89:
2646 case 233:
2647 case 217:
2648 case 169:
2649 case 153:
2650 block = "TC_VFETCH";
2651 break;
2652 case 42:
2653 case 26:
2654 case 106:
2655 case 90:
2656 case 234:
2657 case 218:
2658 case 170:
2659 case 154:
2660 block = "VC";
2661 break;
2662 case 112:
2663 block = "CP";
2664 break;
2665 case 113:
2666 case 114:
2667 block = "SH";
2668 break;
2669 case 115:
2670 block = "VGT";
2671 break;
2672 case 178:
2673 block = "IH";
2674 break;
2675 case 51:
2676 block = "RLC";
2677 break;
2678 case 55:
2679 block = "DMA";
2680 break;
2681 case 56:
2682 block = "HDP";
2683 break;
2684 default:
2685 block = "unknown";
2686 break;
2687 }
2688
2689 printk("VM fault (0x%02x, vmid %d) at page %u, %s from %s (%d)\n",
2690 protections, vmid, addr,
2691 (status & MEMORY_CLIENT_RW_MASK) ? "write" : "read",
2692 block, mc_id);
2693 }
2694
2695 /**
2696 * cayman_vm_flush - vm flush using the CP
2697 *
2698 * @rdev: radeon_device pointer
2699 *
2700 * Update the page table base and flush the VM TLB
2701 * using the CP (cayman-si).
2702 */
cayman_vm_flush(struct radeon_device * rdev,struct radeon_ring * ring,unsigned vm_id,uint64_t pd_addr)2703 void cayman_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
2704 unsigned vm_id, uint64_t pd_addr)
2705 {
2706 radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2), 0));
2707 radeon_ring_write(ring, pd_addr >> 12);
2708
2709 /* flush hdp cache */
2710 radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0));
2711 radeon_ring_write(ring, 0x1);
2712
2713 /* bits 0-7 are the VM contexts0-7 */
2714 radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0));
2715 radeon_ring_write(ring, 1 << vm_id);
2716
2717 /* wait for the invalidate to complete */
2718 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2719 radeon_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */
2720 WAIT_REG_MEM_ENGINE(0))); /* me */
2721 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
2722 radeon_ring_write(ring, 0);
2723 radeon_ring_write(ring, 0); /* ref */
2724 radeon_ring_write(ring, 0); /* mask */
2725 radeon_ring_write(ring, 0x20); /* poll interval */
2726
2727 /* sync PFP to ME, otherwise we might get invalid PFP reads */
2728 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2729 radeon_ring_write(ring, 0x0);
2730 }
2731
tn_set_vce_clocks(struct radeon_device * rdev,u32 evclk,u32 ecclk)2732 int tn_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk)
2733 {
2734 struct atom_clock_dividers dividers;
2735 int r, i;
2736
2737 r = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
2738 ecclk, false, ÷rs);
2739 if (r)
2740 return r;
2741
2742 for (i = 0; i < 100; i++) {
2743 if (RREG32(CG_ECLK_STATUS) & ECLK_STATUS)
2744 break;
2745 mdelay(10);
2746 }
2747 if (i == 100)
2748 return -ETIMEDOUT;
2749
2750 WREG32_P(CG_ECLK_CNTL, dividers.post_div, ~(ECLK_DIR_CNTL_EN|ECLK_DIVIDER_MASK));
2751
2752 for (i = 0; i < 100; i++) {
2753 if (RREG32(CG_ECLK_STATUS) & ECLK_STATUS)
2754 break;
2755 mdelay(10);
2756 }
2757 if (i == 100)
2758 return -ETIMEDOUT;
2759
2760 return 0;
2761 }
2762