1 /* $NetBSD: bcm53xx_board.c,v 1.27 2024/02/16 16:28:49 skrll Exp $ */
2 /*-
3 * Copyright (c) 2012 The NetBSD Foundation, Inc.
4 * All rights reserved.
5 *
6 * This code is derived from software contributed to The NetBSD Foundation
7 * by Matt Thomas of 3am Software Foundry.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31 #include "opt_arm_debug.h"
32 #include "opt_broadcom.h"
33 #include "arml2cc.h"
34
35 #define _ARM32_BUS_DMA_PRIVATE
36
37 #include <sys/cdefs.h>
38
39 __KERNEL_RCSID(1, "$NetBSD: bcm53xx_board.c,v 1.27 2024/02/16 16:28:49 skrll Exp $");
40
41 #include <sys/param.h>
42 #include <sys/bus.h>
43 #include <sys/cpu.h>
44 #include <sys/device.h>
45
46 #include <prop/proplib.h>
47
48 #include <net/if.h>
49 #include <net/if_ether.h>
50
51 #define CCA_PRIVATE
52 #define CRU_PRIVATE
53 #define DDR_PRIVATE
54 #define DMU_PRIVATE
55 #define ARMCORE_PRIVATE
56 #define SRAB_PRIVATE
57
58 #include <arm/cortex/a9tmr_var.h>
59 #include <arm/cortex/pl310_var.h>
60 #include <arm/mainbus/mainbus.h>
61
62 #include <arm/broadcom/bcm53xx_reg.h>
63 #include <arm/broadcom/bcm53xx_var.h>
64
65 bus_space_tag_t bcm53xx_ioreg_bst = &bcmgen_bs_tag;
66 bus_space_handle_t bcm53xx_ioreg_bsh;
67 bus_space_tag_t bcm53xx_armcore_bst = &bcmgen_bs_tag;
68 bus_space_handle_t bcm53xx_armcore_bsh;
69
70 static struct cpu_softc cpu_softc;
71
72 struct arm32_dma_range bcm53xx_dma_ranges[] = {
73 #ifdef BCM5301X
74 [0] = {
75 .dr_sysbase = 0x80000000,
76 .dr_busbase = 0x80000000,
77 .dr_len = 0x10000000,
78 }, [1] = {
79 .dr_sysbase = 0x90000000,
80 .dr_busbase = 0x90000000,
81 },
82 #elif defined(BCM563XX)
83 [0] = {
84 .dr_sysbase = 0x60000000,
85 .dr_busbase = 0x60000000,
86 .dr_len = 0x20000000,
87 }, [1] = {
88 .dr_sysbase = 0x80000000,
89 .dr_busbase = 0x80000000,
90 },
91 #endif
92 };
93
94 struct arm32_bus_dma_tag bcm53xx_dma_tag = {
95 ._ranges = bcm53xx_dma_ranges,
96 ._nranges = __arraycount(bcm53xx_dma_ranges),
97 _BUS_DMAMAP_FUNCS,
98 _BUS_DMAMEM_FUNCS,
99 _BUS_DMATAG_FUNCS,
100 };
101
102 struct arm32_dma_range bcm53xx_coherent_dma_ranges[] = {
103 #ifdef BCM5301X
104 [0] = {
105 .dr_sysbase = 0x80000000,
106 .dr_busbase = 0x80000000,
107 .dr_len = 0x10000000,
108 .dr_flags = _BUS_DMAMAP_COHERENT,
109 }, [1] = {
110 .dr_sysbase = 0x90000000,
111 .dr_busbase = 0x90000000,
112 },
113 #elif defined(BCM563XX)
114 [0] = {
115 .dr_sysbase = 0x60000000,
116 .dr_busbase = 0x60000000,
117 .dr_len = 0x20000000,
118 .dr_flags = _BUS_DMAMAP_COHERENT,
119 }, [1] = {
120 .dr_sysbase = 0x80000000,
121 .dr_busbase = 0x80000000,
122 },
123 #endif
124 };
125
126 struct arm32_bus_dma_tag bcm53xx_coherent_dma_tag = {
127 ._ranges = bcm53xx_coherent_dma_ranges,
128 ._nranges = __arraycount(bcm53xx_coherent_dma_ranges),
129 _BUS_DMAMAP_FUNCS,
130 _BUS_DMAMEM_FUNCS,
131 _BUS_DMATAG_FUNCS,
132 };
133
134 #ifdef _ARM32_NEED_BUS_DMA_BOUNCE
135 struct arm32_bus_dma_tag bcm53xx_bounce_dma_tag = {
136 ._ranges = bcm53xx_coherent_dma_ranges,
137 ._nranges = 1,
138 _BUS_DMAMAP_FUNCS,
139 _BUS_DMAMEM_FUNCS,
140 _BUS_DMATAG_FUNCS,
141 };
142 #endif
143
144 psize_t
bcm53xx_memprobe(void)145 bcm53xx_memprobe(void)
146 {
147 bus_space_tag_t bst = bcm53xx_ioreg_bst;
148 bus_space_handle_t bsh = bcm53xx_ioreg_bsh;
149
150 /*
151 * First, let's read the magic DDR registers!
152 */
153 const uint32_t v01 = bus_space_read_4(bst, bsh, DDR_BASE + DDR_CTL_01);
154 const uint32_t v82 = bus_space_read_4(bst, bsh, DDR_BASE + DDR_CTL_82);
155 const uint32_t v86 = bus_space_read_4(bst, bsh, DDR_BASE + DDR_CTL_86);
156 const uint32_t v87 = bus_space_read_4(bst, bsh, DDR_BASE + DDR_CTL_87);
157
158 /*
159 * Calculate chip parameters
160 * */
161 const u_int rows = __SHIFTOUT(v01, CTL_01_MAX_ROW)
162 - __SHIFTOUT(v82, CTL_82_ROW_DIFF);
163 const u_int cols = __SHIFTOUT(v01, CTL_01_MAX_COL)
164 - __SHIFTOUT(v82, CTL_82_COL_DIFF);
165 const u_int banks_log2 = 3 - __SHIFTOUT(v82, CTL_82_BANK_DIFF);
166
167 /*
168 * For each chip select, increase the chip count if if is enabled.
169 */
170 const u_int max_chips = __SHIFTOUT(v01, CTL_01_MAX_CHIP_SEL);
171 u_int cs_map = __SHIFTOUT(v86, CTL_86_CS_MAP);
172 u_int chips = 0;
173
174 for (u_int i = 0; cs_map != 0 && i < max_chips; i++, cs_map >>= 1) {
175 chips += (cs_map & 1);
176 }
177
178 /* get log2(ddr width) */
179
180 const u_int ddr_width_log2 = (v87 & CTL_87_REDUC) ? 1 : 2;
181
182 /*
183 * Let's add up all the things that contribute to the size of a chip.
184 */
185 const u_int chip_size_log2 = cols + rows + banks_log2 + ddr_width_log2;
186
187 /*
188 * Now our memory size is simply the number of chip shifted by the
189 * log2(chip_size).
190 */
191 return (psize_t) chips << chip_size_log2;
192 }
193
194 static inline uint32_t
bcm53xx_freq_calc(struct bcm53xx_clock_info * clk,uint32_t pdiv,uint32_t ndiv_int,uint32_t ndiv_frac)195 bcm53xx_freq_calc(struct bcm53xx_clock_info *clk,
196 uint32_t pdiv, uint32_t ndiv_int, uint32_t ndiv_frac)
197 {
198 if (ndiv_frac == 0 && pdiv == 1)
199 return ndiv_int * clk->clk_ref;
200
201 uint64_t freq64 = ((uint64_t)ndiv_int << 30) + ndiv_frac;
202 freq64 *= clk->clk_ref;
203 if (pdiv > 1)
204 freq64 /= pdiv;
205 return (uint32_t) (freq64 >> 30);
206 }
207
208 static uint32_t
bcm53xx_value_wrap(uint32_t value,uint32_t mask)209 bcm53xx_value_wrap(uint32_t value, uint32_t mask)
210 {
211 /*
212 * n is n except when n is 0 then n = mask + 1.
213 */
214 return ((__SHIFTOUT(value, mask) - 1) & __SHIFTOUT(mask, mask)) + 1;
215 }
216
217 static void
bcm53xx_genpll_clock_init(struct bcm53xx_clock_info * clk,uint32_t control5,uint32_t control6,uint32_t control7)218 bcm53xx_genpll_clock_init(struct bcm53xx_clock_info *clk, uint32_t control5,
219 uint32_t control6, uint32_t control7)
220 {
221 const uint32_t pdiv = bcm53xx_value_wrap(control6,
222 GENPLL_CONTROL6_PDIV);
223 const uint32_t ndiv_int = bcm53xx_value_wrap(control5,
224 GENPLL_CONTROL5_NDIV_INT);
225 const uint32_t ndiv_frac = __SHIFTOUT(control5,
226 GENPLL_CONTROL5_NDIV_FRAC);
227
228 clk->clk_genpll = bcm53xx_freq_calc(clk, pdiv, ndiv_int, ndiv_frac);
229
230 const uint32_t ch0_mdiv = bcm53xx_value_wrap(control6,
231 GENPLL_CONTROL6_CH0_MDIV);
232 const uint32_t ch1_mdiv = bcm53xx_value_wrap(control6,
233 GENPLL_CONTROL6_CH1_MDIV);
234 const uint32_t ch2_mdiv = bcm53xx_value_wrap(control6,
235 GENPLL_CONTROL6_CH2_MDIV);
236 const uint32_t ch3_mdiv = bcm53xx_value_wrap(control7,
237 GENPLL_CONTROL7_CH3_MDIV);
238
239 clk->clk_mac = clk->clk_genpll / ch0_mdiv; // GENPLL CH0
240 clk->clk_robo = clk->clk_genpll / ch1_mdiv; // GENPLL CH1
241 clk->clk_usb2 = clk->clk_genpll / ch2_mdiv; // GENPLL CH2
242 clk->clk_iproc = clk->clk_genpll / ch3_mdiv; // GENPLL CH3
243 }
244
245 static void
bcm53xx_lcpll_clock_init(struct bcm53xx_clock_info * clk,uint32_t control1,uint32_t control2)246 bcm53xx_lcpll_clock_init(struct bcm53xx_clock_info *clk, uint32_t control1,
247 uint32_t control2)
248 {
249 const uint32_t pdiv = bcm53xx_value_wrap(control1,
250 LCPLL_CONTROL1_PDIV);
251 const uint32_t ndiv_int = bcm53xx_value_wrap(control1,
252 LCPLL_CONTROL1_NDIV_INT);
253 const uint32_t ndiv_frac = __SHIFTOUT(control1,
254 LCPLL_CONTROL1_NDIV_FRAC);
255
256 clk->clk_lcpll = bcm53xx_freq_calc(clk, pdiv, ndiv_int, ndiv_frac);
257
258 const uint32_t ch0_mdiv = bcm53xx_value_wrap(control2,
259 LCPLL_CONTROL2_CH0_MDIV);
260 const uint32_t ch1_mdiv = bcm53xx_value_wrap(control2,
261 LCPLL_CONTROL2_CH1_MDIV);
262 const uint32_t ch2_mdiv = bcm53xx_value_wrap(control2,
263 LCPLL_CONTROL2_CH2_MDIV);
264 const uint32_t ch3_mdiv = bcm53xx_value_wrap(control2,
265 LCPLL_CONTROL2_CH3_MDIV);
266
267 clk->clk_pcie_ref = clk->clk_lcpll / ch0_mdiv; // LCPLL CH0
268 clk->clk_sdio = clk->clk_lcpll / ch1_mdiv; // LCPLL CH1
269 clk->clk_ddr_ref = clk->clk_lcpll / ch2_mdiv; // LCPLL CH2
270 clk->clk_axi = clk->clk_lcpll / ch3_mdiv; // LCPLL CH3
271 }
272
273 static void
bcm53xx_usb_clock_init(struct bcm53xx_clock_info * clk,uint32_t usb2_control)274 bcm53xx_usb_clock_init(struct bcm53xx_clock_info *clk, uint32_t usb2_control)
275 {
276 const uint32_t pdiv = bcm53xx_value_wrap(usb2_control,
277 USB2_CONTROL_PDIV);
278 const uint32_t ndiv = bcm53xx_value_wrap(usb2_control,
279 USB2_CONTROL_NDIV_INT);
280
281 uint32_t usb_ref = (clk->clk_usb2 / pdiv) * ndiv;
282 if (usb_ref != USB2_REF_CLK) {
283 /*
284 * USB Reference Clock isn't 1.92GHz. So we need to modify
285 * USB2_CONTROL to produce it.
286 */
287 uint32_t new_ndiv = (USB2_REF_CLK / clk->clk_usb2) * pdiv;
288 usb2_control &= ~USB2_CONTROL_NDIV_INT;
289 usb2_control |= __SHIFTIN(new_ndiv, USB2_CONTROL_NDIV_INT);
290
291 // Allow Clocks to be modified
292 bus_space_write_4(bcm53xx_ioreg_bst, bcm53xx_ioreg_bsh,
293 CRU_BASE + CRU_CLKSET_KEY, CRU_CLKSET_KEY_MAGIC);
294
295 // Update USB2 clock generator
296 bus_space_write_4(bcm53xx_ioreg_bst, bcm53xx_ioreg_bsh,
297 CRU_BASE + CRU_USB2_CONTROL, usb2_control);
298
299 // Prevent Clock modification
300 bus_space_write_4(bcm53xx_ioreg_bst, bcm53xx_ioreg_bsh,
301 CRU_BASE + CRU_CLKSET_KEY, 0);
302
303 usb_ref = (clk->clk_usb2 / pdiv) * new_ndiv;
304 }
305
306 clk->clk_usb_ref = usb_ref;
307 }
308
309
310 static void
bcm53xx_clock_init(struct bcm53xx_clock_info * clk)311 bcm53xx_clock_init(struct bcm53xx_clock_info *clk)
312 {
313 clk->clk_ref = BCM53XX_REF_CLK;
314 clk->clk_sys = 8*clk->clk_ref;
315 }
316
317 /*
318 * F(ddr) = ((1 / pdiv) * ndiv * CH2) / (post_div * 2)
319 */
320 static void
bcm53xx_get_ddr_freq(struct bcm53xx_clock_info * clk,uint32_t pll_status,uint32_t pll_dividers)321 bcm53xx_get_ddr_freq(struct bcm53xx_clock_info *clk, uint32_t pll_status,
322 uint32_t pll_dividers)
323 {
324 const bool clocking_4x = (pll_status & PLL_STATUS_CLOCKING_4X) != 0;
325 u_int post_div = __SHIFTOUT(pll_dividers, PLL_DIVIDERS_POST_DIV);
326 u_int pdiv = __SHIFTOUT(pll_dividers, PLL_DIVIDERS_PDIV);
327 u_int ndiv = __SHIFTOUT(pll_dividers, PLL_DIVIDERS_NDIV);
328
329 pdiv = ((pdiv - (clocking_4x ? 1 : 5)) & 7) + 1;
330
331 clk->clk_ddr_mhz = __SHIFTOUT(pll_status, PLL_STATUS_MHZ);
332 clk->clk_ddr = (clk->clk_ddr_ref / pdiv) * ndiv / (2 + post_div);
333 }
334
335 /*
336 * CPU_CLK = (1 / pdiv) * (ndiv_int + (ndiv_frac / 0x40000000)) x F(ref)
337 */
338 static void
bcm53xx_get_cpu_freq(struct bcm53xx_clock_info * clk,uint32_t pllarma,uint32_t pllarmb,uint32_t policy)339 bcm53xx_get_cpu_freq(struct bcm53xx_clock_info *clk,
340 uint32_t pllarma, uint32_t pllarmb, uint32_t policy)
341 {
342 policy = __SHIFTOUT(policy, CLK_POLICY_FREQ_POLICY2);
343
344 if (policy == CLK_POLICY_REF_CLK) {
345 clk->clk_cpu = clk->clk_ref;
346 clk->clk_apb = clk->clk_cpu;
347 return;
348 }
349
350 if (policy == CLK_POLICY_SYS_CLK) {
351 clk->clk_cpu = clk->clk_sys;
352 clk->clk_apb = clk->clk_cpu / 4;
353 return;
354 }
355
356 const u_int pdiv = bcm53xx_value_wrap(pllarma, CLK_PLLARMA_PDIV);
357 const u_int ndiv_int = bcm53xx_value_wrap(pllarma, CLK_PLLARMA_NDIV_INT);
358 const u_int ndiv_frac = __SHIFTOUT(pllarmb, CLK_PLLARMB_NDIV_FRAC);
359 // const u_int apb_clk_div = __SHIFTOUT(apb_clk_div, CLK_APB_DIV_VALUE)+1;
360
361 const u_int cpu_div = (policy == CLK_POLICY_ARM_PLL_CH0) ? 4 : 2;
362
363 clk->clk_cpu = bcm53xx_freq_calc(clk, pdiv, ndiv_int, ndiv_frac) / cpu_div;
364 clk->clk_apb = clk->clk_cpu / 4;
365 }
366
367 struct bcm53xx_chip_state {
368 uint32_t bcs_lcpll_control1;
369 uint32_t bcs_lcpll_control2;
370
371 uint32_t bcs_genpll_control5;
372 uint32_t bcs_genpll_control6;
373 uint32_t bcs_genpll_control7;
374
375 uint32_t bcs_usb2_control;
376
377 uint32_t bcs_ddr_phy_ctl_pll_status;
378 uint32_t bcs_ddr_phy_ctl_pll_dividers;
379
380 uint32_t bcs_armcore_clk_policy;
381 uint32_t bcs_armcore_clk_pllarma;
382 uint32_t bcs_armcore_clk_pllarmb;
383 };
384
385 static void
bcm53xx_get_chip_ioreg_state(struct bcm53xx_chip_state * bcs,bus_space_tag_t bst,bus_space_handle_t bsh)386 bcm53xx_get_chip_ioreg_state(struct bcm53xx_chip_state *bcs,
387 bus_space_tag_t bst, bus_space_handle_t bsh)
388 {
389 bcs->bcs_lcpll_control1 = bus_space_read_4(bst, bsh,
390 DMU_BASE + DMU_LCPLL_CONTROL1);
391 bcs->bcs_lcpll_control2 = bus_space_read_4(bst, bsh,
392 DMU_BASE + DMU_LCPLL_CONTROL2);
393
394 bcs->bcs_genpll_control5 = bus_space_read_4(bst, bsh,
395 CRU_BASE + CRU_GENPLL_CONTROL5);
396 bcs->bcs_genpll_control6 = bus_space_read_4(bst, bsh,
397 CRU_BASE + CRU_GENPLL_CONTROL6);
398 bcs->bcs_genpll_control7 = bus_space_read_4(bst, bsh,
399 CRU_BASE + CRU_GENPLL_CONTROL7);
400
401 bcs->bcs_usb2_control = bus_space_read_4(bst, bsh,
402 CRU_BASE + CRU_USB2_CONTROL);
403
404 bcs->bcs_ddr_phy_ctl_pll_status = bus_space_read_4(bst, bsh,
405 DDR_BASE + DDR_PHY_CTL_PLL_STATUS);
406 bcs->bcs_ddr_phy_ctl_pll_dividers = bus_space_read_4(bst, bsh,
407 DDR_BASE + DDR_PHY_CTL_PLL_DIVIDERS);
408 }
409
410 static void
bcm53xx_get_chip_armcore_state(struct bcm53xx_chip_state * bcs,bus_space_tag_t bst,bus_space_handle_t bsh)411 bcm53xx_get_chip_armcore_state(struct bcm53xx_chip_state *bcs,
412 bus_space_tag_t bst, bus_space_handle_t bsh)
413 {
414 bcs->bcs_armcore_clk_policy = bus_space_read_4(bst, bsh,
415 ARMCORE_CLK_POLICY_FREQ);
416 bcs->bcs_armcore_clk_pllarma = bus_space_read_4(bst, bsh,
417 ARMCORE_CLK_PLLARMA);
418 bcs->bcs_armcore_clk_pllarmb = bus_space_read_4(bst, bsh,
419 ARMCORE_CLK_PLLARMB);
420 }
421
422 void
bcm53xx_cpu_softc_init(struct cpu_info * ci)423 bcm53xx_cpu_softc_init(struct cpu_info *ci)
424 {
425 struct cpu_softc * const cpu = ci->ci_softc;
426
427 cpu->cpu_ioreg_bst = bcm53xx_ioreg_bst;
428 cpu->cpu_ioreg_bsh = bcm53xx_ioreg_bsh;
429
430 cpu->cpu_armcore_bst = bcm53xx_armcore_bst;
431 cpu->cpu_armcore_bsh = bcm53xx_armcore_bsh;
432
433 const uint32_t chipid = bus_space_read_4(cpu->cpu_ioreg_bst,
434 cpu->cpu_ioreg_bsh, CCA_MISC_BASE + MISC_CHIPID);
435
436 cpu->cpu_chipid = __SHIFTOUT(chipid, CHIPID_ID);
437 }
438
439 void
bcm53xx_print_clocks(void)440 bcm53xx_print_clocks(void)
441 {
442 #if defined(VERBOSE_INIT_ARM)
443 const struct bcm53xx_clock_info * const clk = &cpu_softc.cpu_clk;
444 printf("ref clk = %u (%#x)\n", clk->clk_ref, clk->clk_ref);
445 printf("sys clk = %u (%#x)\n", clk->clk_sys, clk->clk_sys);
446 printf("lcpll clk = %u (%#x)\n", clk->clk_lcpll, clk->clk_lcpll);
447 printf("pcie ref clk = %u (%#x) [CH0]\n", clk->clk_pcie_ref, clk->clk_pcie_ref);
448 printf("sdio clk = %u (%#x) [CH1]\n", clk->clk_sdio, clk->clk_sdio);
449 printf("ddr ref clk = %u (%#x) [CH2]\n", clk->clk_ddr_ref, clk->clk_ddr_ref);
450 printf("axi clk = %u (%#x) [CH3]\n", clk->clk_axi, clk->clk_axi);
451 printf("genpll clk = %u (%#x)\n", clk->clk_genpll, clk->clk_genpll);
452 printf("mac clk = %u (%#x) [CH0]\n", clk->clk_mac, clk->clk_mac);
453 printf("robo clk = %u (%#x) [CH1]\n", clk->clk_robo, clk->clk_robo);
454 printf("usb2 clk = %u (%#x) [CH2]\n", clk->clk_usb2, clk->clk_usb2);
455 printf("iproc clk = %u (%#x) [CH3]\n", clk->clk_iproc, clk->clk_iproc);
456 printf("ddr clk = %u (%#x)\n", clk->clk_ddr, clk->clk_ddr);
457 printf("ddr mhz = %u (%#x)\n", clk->clk_ddr_mhz, clk->clk_ddr_mhz);
458 printf("cpu clk = %u (%#x)\n", clk->clk_cpu, clk->clk_cpu);
459 printf("apb clk = %u (%#x)\n", clk->clk_apb, clk->clk_apb);
460 printf("usb ref clk = %u (%#x)\n", clk->clk_usb_ref, clk->clk_usb_ref);
461 #endif
462 }
463
464 void
bcm53xx_bootstrap(vaddr_t iobase)465 bcm53xx_bootstrap(vaddr_t iobase)
466 {
467 struct bcm53xx_chip_state bcs;
468 int error;
469
470 bcm53xx_ioreg_bsh = (bus_space_handle_t) iobase;
471 error = bus_space_map(bcm53xx_ioreg_bst, BCM53XX_IOREG_PBASE,
472 BCM53XX_IOREG_SIZE, 0, &bcm53xx_ioreg_bsh);
473 if (error)
474 panic("%s: failed to map BCM53xx %s registers: %d",
475 __func__, "io", error);
476
477 bcm53xx_armcore_bsh = (bus_space_handle_t) iobase + BCM53XX_IOREG_SIZE;
478 error = bus_space_map(bcm53xx_armcore_bst, BCM53XX_ARMCORE_PBASE,
479 BCM53XX_ARMCORE_SIZE, 0, &bcm53xx_armcore_bsh);
480 if (error)
481 panic("%s: failed to map BCM53xx %s registers: %d",
482 __func__, "armcore", error);
483
484 curcpu()->ci_softc = &cpu_softc;
485
486 bcm53xx_get_chip_ioreg_state(&bcs, bcm53xx_ioreg_bst, bcm53xx_ioreg_bsh);
487 bcm53xx_get_chip_armcore_state(&bcs, bcm53xx_armcore_bst, bcm53xx_armcore_bsh);
488
489 struct bcm53xx_clock_info * const clk = &cpu_softc.cpu_clk;
490
491 bcm53xx_clock_init(clk);
492 bcm53xx_lcpll_clock_init(clk, bcs.bcs_lcpll_control1,
493 bcs.bcs_lcpll_control2);
494 bcm53xx_genpll_clock_init(clk, bcs.bcs_genpll_control5,
495 bcs.bcs_genpll_control6, bcs.bcs_genpll_control7);
496 bcm53xx_usb_clock_init(clk, bcs.bcs_usb2_control);
497 bcm53xx_get_ddr_freq(clk, bcs.bcs_ddr_phy_ctl_pll_status,
498 bcs.bcs_ddr_phy_ctl_pll_dividers);
499 bcm53xx_get_cpu_freq(clk, bcs.bcs_armcore_clk_pllarma,
500 bcs.bcs_armcore_clk_pllarmb, bcs.bcs_armcore_clk_policy);
501
502 curcpu()->ci_data.cpu_cc_freq = clk->clk_cpu;
503
504 #if NARML2CC > 0
505 arml2cc_init(bcm53xx_armcore_bst, bcm53xx_armcore_bsh,
506 ARMCORE_L2C_BASE);
507 #endif
508 }
509
510 void
bcm53xx_dma_bootstrap(psize_t memsize)511 bcm53xx_dma_bootstrap(psize_t memsize)
512 {
513 if (memsize <= 256*1024*1024) {
514 bcm53xx_dma_ranges[0].dr_len = memsize;
515 bcm53xx_coherent_dma_ranges[0].dr_len = memsize;
516 bcm53xx_dma_tag._nranges = 1;
517 bcm53xx_coherent_dma_tag._nranges = 1;
518 } else {
519 /*
520 * By setting up two ranges, bus_dmamem_alloc will always
521 * try to allocate from range 0 first resulting in allocations
522 * below 256MB which for PCI and GMAC are coherent.
523 */
524 bcm53xx_dma_ranges[1].dr_len = memsize - 0x10000000;
525 bcm53xx_coherent_dma_ranges[1].dr_len = memsize - 0x10000000;
526 }
527 KASSERT(bcm53xx_dma_tag._ranges[0].dr_flags == 0);
528 KASSERT(bcm53xx_coherent_dma_tag._ranges[0].dr_flags == _BUS_DMAMAP_COHERENT);
529 #ifdef _ARM32_NEED_BUS_DMA_BOUNCE
530 KASSERT(bcm53xx_bounce_dma_tag._ranges[0].dr_flags == _BUS_DMAMAP_COHERENT);
531 #endif
532 }
533
534 #ifdef MULTIPROCESSOR
535 void
bcm53xx_cpu_hatch(struct cpu_info * ci)536 bcm53xx_cpu_hatch(struct cpu_info *ci)
537 {
538 a9tmr_init_cpu_clock(ci);
539 }
540 #endif
541
542 void
bcm53xx_device_register(device_t self,void * aux)543 bcm53xx_device_register(device_t self, void *aux)
544 {
545 prop_dictionary_t dict = device_properties(self);
546
547 if (device_is_a(self, "armperiph")
548 && device_is_a(device_parent(self), "mainbus")) {
549 /*
550 * XXX KLUDGE ALERT XXX
551 * The iot mainbus supplies is completely wrong since it scales
552 * addresses by 2. The simplest remedy is to replace with our
553 * bus space used for the armcore registers (which armperiph uses).
554 */
555 struct mainbus_attach_args * const mb = aux;
556 mb->mb_iot = bcm53xx_armcore_bst;
557 return;
558 }
559
560 /*
561 * We need to tell the A9 Global/Watchdog Timer
562 * what frequency it runs at.
563 */
564 if (device_is_a(self, "arma9tmr") || device_is_a(self, "a9wdt")) {
565 /*
566 * This clock always runs at (arm_clk div 2) and only goes
567 * to timers that are part of the A9 MP core subsystem.
568 */
569 prop_dictionary_set_uint32(dict, "frequency",
570 cpu_softc.cpu_clk.clk_cpu / 2);
571 return;
572 }
573
574 if (device_is_a(self, "bcmeth")) {
575 const struct bcmccb_attach_args * const ccbaa = aux;
576 const uint8_t enaddr[ETHER_ADDR_LEN] = {
577 0x00, 0x01, 0x02, 0x03, 0x04,
578 0x05 + 2 * ccbaa->ccbaa_loc.loc_port,
579 };
580 prop_data_t pd = prop_data_create_data(enaddr, ETHER_ADDR_LEN);
581 KASSERT(pd != NULL);
582 if (prop_dictionary_set(device_properties(self), "mac-address", pd) == false) {
583 printf("WARNING: Unable to set mac-address property for %s\n", device_xname(self));
584 }
585 prop_object_release(pd);
586 }
587 }
588
589 #ifdef SRAB_BASE
590 static kmutex_t srab_lock __cacheline_aligned;
591
592 void
bcm53xx_srab_init(void)593 bcm53xx_srab_init(void)
594 {
595 mutex_init(&srab_lock, MUTEX_DEFAULT, IPL_VM);
596
597 bcm53xx_srab_write_4(0x0079, 0x90); // reset switch
598 for (u_int port = 0; port < 8; port++) {
599 /* per port control: no stp */
600 bcm53xx_srab_write_4(port, 0x00);
601 }
602 bcm53xx_srab_write_4(0x0008, 0x1c); // IMP port (enab UC/MC/BC)
603 bcm53xx_srab_write_4(0x000e, 0xbb); // IMP port force-link 1G
604 bcm53xx_srab_write_4(0x005d, 0x7b); // port5 force-link 1G
605 bcm53xx_srab_write_4(0x005f, 0x7b); // port7 force-link 1G
606 bcm53xx_srab_write_4(0x000b, 0x7); // management mode
607 bcm53xx_srab_write_4(0x0203, 0x0); // disable BRCM tag
608 bcm53xx_srab_write_4(0x0200, 0x80); // enable IMP=port8
609 }
610
611 static inline void
bcm53xx_srab_busywait(bus_space_tag_t bst,bus_space_handle_t bsh)612 bcm53xx_srab_busywait(bus_space_tag_t bst, bus_space_handle_t bsh)
613 {
614 while (bus_space_read_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT) & SRA_GORDYN) {
615 delay(10);
616 }
617 }
618
619 uint32_t
bcm53xx_srab_read_4(u_int pageoffset)620 bcm53xx_srab_read_4(u_int pageoffset)
621 {
622 bus_space_tag_t bst = bcm53xx_ioreg_bst;
623 bus_space_handle_t bsh = bcm53xx_ioreg_bsh;
624 uint32_t rv;
625
626 mutex_spin_enter(&srab_lock);
627
628 bcm53xx_srab_busywait(bst, bsh);
629 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT,
630 __SHIFTIN(pageoffset, SRA_PAGEOFFSET) | SRA_GORDYN);
631 bcm53xx_srab_busywait(bst, bsh);
632 rv = bus_space_read_4(bst, bsh, SRAB_BASE + SRAB_RDL);
633
634 mutex_spin_exit(&srab_lock);
635 return rv;
636 }
637
638 uint64_t
bcm53xx_srab_read_8(u_int pageoffset)639 bcm53xx_srab_read_8(u_int pageoffset)
640 {
641 bus_space_tag_t bst = bcm53xx_ioreg_bst;
642 bus_space_handle_t bsh = bcm53xx_ioreg_bsh;
643 uint64_t rv;
644
645 mutex_spin_enter(&srab_lock);
646
647 bcm53xx_srab_busywait(bst, bsh);
648 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT,
649 __SHIFTIN(pageoffset, SRA_PAGEOFFSET) | SRA_GORDYN);
650 bcm53xx_srab_busywait(bst, bsh);
651 rv = bus_space_read_4(bst, bsh, SRAB_BASE + SRAB_RDH);
652 rv <<= 32;
653 rv |= bus_space_read_4(bst, bsh, SRAB_BASE + SRAB_RDL);
654
655 mutex_spin_exit(&srab_lock);
656 return rv;
657 }
658
659 void
bcm53xx_srab_write_4(u_int pageoffset,uint32_t val)660 bcm53xx_srab_write_4(u_int pageoffset, uint32_t val)
661 {
662 bus_space_tag_t bst = bcm53xx_ioreg_bst;
663 bus_space_handle_t bsh = bcm53xx_ioreg_bsh;
664
665 mutex_spin_enter(&srab_lock);
666
667 bcm53xx_srab_busywait(bst, bsh);
668 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_WDL, val);
669 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT,
670 __SHIFTIN(pageoffset, SRA_PAGEOFFSET) | SRA_WRITE | SRA_GORDYN);
671 bcm53xx_srab_busywait(bst, bsh);
672
673 mutex_spin_exit(&srab_lock);
674 }
675
676 void
bcm53xx_srab_write_8(u_int pageoffset,uint64_t val)677 bcm53xx_srab_write_8(u_int pageoffset, uint64_t val)
678 {
679 bus_space_tag_t bst = bcm53xx_ioreg_bst;
680 bus_space_handle_t bsh = bcm53xx_ioreg_bsh;
681
682 mutex_spin_enter(&srab_lock);
683
684 bcm53xx_srab_busywait(bst, bsh);
685 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_WDL, val);
686 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_WDH, val >> 32);
687 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT,
688 __SHIFTIN(pageoffset, SRA_PAGEOFFSET) | SRA_WRITE | SRA_GORDYN);
689 bcm53xx_srab_busywait(bst, bsh);
690 mutex_spin_exit(&srab_lock);
691 }
692 #endif
693