1 /*
2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
14 * PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include "opt_ah.h"
18
19 #include "ah.h"
20 #include "ah_internal.h"
21 #include "ah_devid.h"
22 #ifdef AH_DEBUG
23 #include "ah_desc.h" /* NB: for HAL_PHYERR* */
24 #endif
25
26 #include "ar9300/ar9300.h"
27 #include "ar9300/ar9300reg.h"
28 #include "ar9300/ar9300phy.h"
29
30
31 void
ar9300_get_hw_hangs(struct ath_hal * ah,hal_hw_hangs_t * hangs)32 ar9300_get_hw_hangs(struct ath_hal *ah, hal_hw_hangs_t *hangs)
33 {
34 struct ath_hal_9300 *ahp = AH9300(ah);
35 *hangs = 0;
36
37 if (ar9300_get_capability(ah, HAL_CAP_BB_RIFS_HANG, 0, AH_NULL) == HAL_OK) {
38 *hangs |= HAL_RIFS_BB_HANG_WAR;
39 }
40 if (ar9300_get_capability(ah, HAL_CAP_BB_DFS_HANG, 0, AH_NULL) == HAL_OK) {
41 *hangs |= HAL_DFS_BB_HANG_WAR;
42 }
43 if (ar9300_get_capability(ah, HAL_CAP_BB_RX_CLEAR_STUCK_HANG, 0, AH_NULL)
44 == HAL_OK)
45 {
46 *hangs |= HAL_RX_STUCK_LOW_BB_HANG_WAR;
47 }
48 if (ar9300_get_capability(ah, HAL_CAP_MAC_HANG, 0, AH_NULL) == HAL_OK) {
49 *hangs |= HAL_MAC_HANG_WAR;
50 }
51 if (ar9300_get_capability(ah, HAL_CAP_PHYRESTART_CLR_WAR, 0, AH_NULL)
52 == HAL_OK)
53 {
54 *hangs |= HAL_PHYRESTART_CLR_WAR;
55 }
56
57 ahp->ah_hang_wars = *hangs;
58 }
59
60 /*
61 * XXX FreeBSD: the HAL version of ath_hal_mac_usec() knows about
62 * HT20, HT40, fast-clock, turbo mode, etc.
63 */
64 static u_int
ar9300_mac_to_usec(struct ath_hal * ah,u_int clks)65 ar9300_mac_to_usec(struct ath_hal *ah, u_int clks)
66 {
67 #if 0
68 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
69
70 if (chan && IEEE80211_IS_CHAN_HT40(chan)) {
71 return (ath_hal_mac_usec(ah, clks) / 2);
72 } else {
73 return (ath_hal_mac_usec(ah, clks));
74 }
75 #endif
76 return (ath_hal_mac_usec(ah, clks));
77 }
78
79 u_int
ar9300_mac_to_clks(struct ath_hal * ah,u_int usecs)80 ar9300_mac_to_clks(struct ath_hal *ah, u_int usecs)
81 {
82 #if 0
83 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
84
85 if (chan && IEEE80211_IS_CHAN_HT40(chan)) {
86 return (ath_hal_mac_clks(ah, usecs) * 2);
87 } else {
88 return (ath_hal_mac_clks(ah, usecs));
89 }
90 #endif
91 return (ath_hal_mac_clks(ah, usecs));
92 }
93
94 void
ar9300_get_mac_address(struct ath_hal * ah,u_int8_t * mac)95 ar9300_get_mac_address(struct ath_hal *ah, u_int8_t *mac)
96 {
97 struct ath_hal_9300 *ahp = AH9300(ah);
98
99 OS_MEMCPY(mac, ahp->ah_macaddr, IEEE80211_ADDR_LEN);
100 }
101
102 HAL_BOOL
ar9300_set_mac_address(struct ath_hal * ah,const u_int8_t * mac)103 ar9300_set_mac_address(struct ath_hal *ah, const u_int8_t *mac)
104 {
105 struct ath_hal_9300 *ahp = AH9300(ah);
106
107 OS_MEMCPY(ahp->ah_macaddr, mac, IEEE80211_ADDR_LEN);
108 return AH_TRUE;
109 }
110
111 void
ar9300_get_bss_id_mask(struct ath_hal * ah,u_int8_t * mask)112 ar9300_get_bss_id_mask(struct ath_hal *ah, u_int8_t *mask)
113 {
114 struct ath_hal_9300 *ahp = AH9300(ah);
115
116 OS_MEMCPY(mask, ahp->ah_bssid_mask, IEEE80211_ADDR_LEN);
117 }
118
119 HAL_BOOL
ar9300_set_bss_id_mask(struct ath_hal * ah,const u_int8_t * mask)120 ar9300_set_bss_id_mask(struct ath_hal *ah, const u_int8_t *mask)
121 {
122 struct ath_hal_9300 *ahp = AH9300(ah);
123
124 /* save it since it must be rewritten on reset */
125 OS_MEMCPY(ahp->ah_bssid_mask, mask, IEEE80211_ADDR_LEN);
126
127 OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssid_mask));
128 OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssid_mask + 4));
129 return AH_TRUE;
130 }
131
132 /*
133 * Attempt to change the cards operating regulatory domain to the given value
134 * Returns: A_EINVAL for an unsupported regulatory domain.
135 * A_HARDWARE for an unwritable EEPROM or bad EEPROM version
136 */
137 HAL_BOOL
ar9300_set_regulatory_domain(struct ath_hal * ah,u_int16_t reg_domain,HAL_STATUS * status)138 ar9300_set_regulatory_domain(struct ath_hal *ah,
139 u_int16_t reg_domain, HAL_STATUS *status)
140 {
141 HAL_STATUS ecode;
142
143 if (AH_PRIVATE(ah)->ah_currentRD == 0) {
144 AH_PRIVATE(ah)->ah_currentRD = reg_domain;
145 return AH_TRUE;
146 }
147 ecode = HAL_EIO;
148
149 #if 0
150 bad:
151 #endif
152 if (status) {
153 *status = ecode;
154 }
155 return AH_FALSE;
156 }
157
158 /*
159 * Return the wireless modes (a,b,g,t) supported by hardware.
160 *
161 * This value is what is actually supported by the hardware
162 * and is unaffected by regulatory/country code settings.
163 *
164 */
165 u_int
ar9300_get_wireless_modes(struct ath_hal * ah)166 ar9300_get_wireless_modes(struct ath_hal *ah)
167 {
168 return AH_PRIVATE(ah)->ah_caps.halWirelessModes;
169 }
170
171 /*
172 * Set the interrupt and GPIO values so the ISR can disable RF
173 * on a switch signal. Assumes GPIO port and interrupt polarity
174 * are set prior to call.
175 */
176 void
ar9300_enable_rf_kill(struct ath_hal * ah)177 ar9300_enable_rf_kill(struct ath_hal *ah)
178 {
179 /* TODO - can this really be above the hal on the GPIO interface for
180 * TODO - the client only?
181 */
182 struct ath_hal_9300 *ahp = AH9300(ah);
183
184 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) {
185 /* Check RF kill GPIO before set/clear RFSILENT bits. */
186 if (ar9300_gpio_get(ah, ahp->ah_gpio_select) == ahp->ah_polarity) {
187 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_RFSILENT),
188 AR_RFSILENT_FORCE);
189 OS_REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
190 }
191 else {
192 OS_REG_CLR_BIT(ah, AR_HOSTIF_REG(ah, AR_RFSILENT),
193 AR_RFSILENT_FORCE);
194 OS_REG_CLR_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
195 }
196 }
197 else {
198 /* Connect rfsilent_bb_l to baseband */
199 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL),
200 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
201
202 /* Set input mux for rfsilent_bb_l to GPIO #0 */
203 OS_REG_CLR_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2),
204 AR_GPIO_INPUT_MUX2_RFSILENT);
205 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2),
206 (ahp->ah_gpio_select & 0x0f) << 4);
207
208 /*
209 * Configure the desired GPIO port for input and
210 * enable baseband rf silence
211 */
212 ath_hal_gpioCfgInput(ah, ahp->ah_gpio_select);
213 OS_REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
214 }
215
216 /*
217 * If radio disable switch connection to GPIO bit x is enabled
218 * program GPIO interrupt.
219 * If rfkill bit on eeprom is 1, setupeeprommap routine has already
220 * verified that it is a later version of eeprom, it has a place for
221 * rfkill bit and it is set to 1, indicating that GPIO bit x hardware
222 * connection is present.
223 */
224 /*
225 * RFKill uses polling not interrupt,
226 * disable interrupt to avoid Eee PC 2.6.21.4 hang up issue
227 */
228 if (ath_hal_hasrfkill_int(ah)) {
229 if (ahp->ah_gpio_bit == ar9300_gpio_get(ah, ahp->ah_gpio_select)) {
230 /* switch already closed, set to interrupt upon open */
231 ar9300_gpio_set_intr(ah, ahp->ah_gpio_select, !ahp->ah_gpio_bit);
232 } else {
233 ar9300_gpio_set_intr(ah, ahp->ah_gpio_select, ahp->ah_gpio_bit);
234 }
235 }
236 }
237
238 /*
239 * Change the LED blinking pattern to correspond to the connectivity
240 */
241 void
ar9300_set_led_state(struct ath_hal * ah,HAL_LED_STATE state)242 ar9300_set_led_state(struct ath_hal *ah, HAL_LED_STATE state)
243 {
244 static const u_int32_t ledbits[8] = {
245 AR_CFG_LED_ASSOC_NONE, /* HAL_LED_RESET */
246 AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_INIT */
247 AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_READY */
248 AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_SCAN */
249 AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_AUTH */
250 AR_CFG_LED_ASSOC_ACTIVE, /* HAL_LED_ASSOC */
251 AR_CFG_LED_ASSOC_ACTIVE, /* HAL_LED_RUN */
252 AR_CFG_LED_ASSOC_NONE,
253 };
254
255 OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_ASSOC_CTL, ledbits[state]);
256 }
257
258 /*
259 * Sets the Power LED on the cardbus without affecting the Network LED.
260 */
261 void
ar9300_set_power_led_state(struct ath_hal * ah,u_int8_t enabled)262 ar9300_set_power_led_state(struct ath_hal *ah, u_int8_t enabled)
263 {
264 u_int32_t val;
265
266 val = enabled ? AR_CFG_LED_MODE_POWER_ON : AR_CFG_LED_MODE_POWER_OFF;
267 OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_POWER, val);
268 }
269
270 /*
271 * Sets the Network LED on the cardbus without affecting the Power LED.
272 */
273 void
ar9300_set_network_led_state(struct ath_hal * ah,u_int8_t enabled)274 ar9300_set_network_led_state(struct ath_hal *ah, u_int8_t enabled)
275 {
276 u_int32_t val;
277
278 val = enabled ? AR_CFG_LED_MODE_NETWORK_ON : AR_CFG_LED_MODE_NETWORK_OFF;
279 OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_NETWORK, val);
280 }
281
282 /*
283 * Change association related fields programmed into the hardware.
284 * Writing a valid BSSID to the hardware effectively enables the hardware
285 * to synchronize its TSF to the correct beacons and receive frames coming
286 * from that BSSID. It is called by the SME JOIN operation.
287 */
288 void
ar9300_write_associd(struct ath_hal * ah,const u_int8_t * bssid,u_int16_t assoc_id)289 ar9300_write_associd(struct ath_hal *ah, const u_int8_t *bssid,
290 u_int16_t assoc_id)
291 {
292 struct ath_hal_9300 *ahp = AH9300(ah);
293
294 /* save bssid and assoc_id for restore on reset */
295 OS_MEMCPY(ahp->ah_bssid, bssid, IEEE80211_ADDR_LEN);
296 ahp->ah_assoc_id = assoc_id;
297
298 OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));
299 OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4) |
300 ((assoc_id & 0x3fff) << AR_BSS_ID1_AID_S));
301 }
302
303 /*
304 * Get the current hardware tsf for stamlme
305 */
306 u_int64_t
ar9300_get_tsf64(struct ath_hal * ah)307 ar9300_get_tsf64(struct ath_hal *ah)
308 {
309 u_int64_t tsf;
310
311 /* XXX sync multi-word read? */
312 tsf = OS_REG_READ(ah, AR_TSF_U32);
313 tsf = (tsf << 32) | OS_REG_READ(ah, AR_TSF_L32);
314 return tsf;
315 }
316
317 void
ar9300_set_tsf64(struct ath_hal * ah,u_int64_t tsf)318 ar9300_set_tsf64(struct ath_hal *ah, u_int64_t tsf)
319 {
320 OS_REG_WRITE(ah, AR_TSF_L32, (tsf & 0xffffffff));
321 OS_REG_WRITE(ah, AR_TSF_U32, ((tsf >> 32) & 0xffffffff));
322 }
323
324 /*
325 * Get the current hardware tsf for stamlme
326 */
327 u_int32_t
ar9300_get_tsf32(struct ath_hal * ah)328 ar9300_get_tsf32(struct ath_hal *ah)
329 {
330 return OS_REG_READ(ah, AR_TSF_L32);
331 }
332
333 u_int32_t
ar9300_get_tsf2_32(struct ath_hal * ah)334 ar9300_get_tsf2_32(struct ath_hal *ah)
335 {
336 return OS_REG_READ(ah, AR_TSF2_L32);
337 }
338
339 /*
340 * Reset the current hardware tsf for stamlme.
341 */
342 void
ar9300_reset_tsf(struct ath_hal * ah)343 ar9300_reset_tsf(struct ath_hal *ah)
344 {
345 int count;
346
347 count = 0;
348 while (OS_REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
349 count++;
350 if (count > 10) {
351 HALDEBUG(ah, HAL_DEBUG_RESET,
352 "%s: AR_SLP32_TSF_WRITE_STATUS limit exceeded\n", __func__);
353 break;
354 }
355 OS_DELAY(10);
356 }
357 OS_REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
358 }
359
360 /*
361 * Set or clear hardware basic rate bit
362 * Set hardware basic rate set if basic rate is found
363 * and basic rate is equal or less than 2Mbps
364 */
365 void
ar9300_set_basic_rate(struct ath_hal * ah,HAL_RATE_SET * rs)366 ar9300_set_basic_rate(struct ath_hal *ah, HAL_RATE_SET *rs)
367 {
368 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
369 u_int32_t reg;
370 u_int8_t xset;
371 int i;
372
373 if (chan == AH_NULL || !IEEE80211_IS_CHAN_CCK(chan)) {
374 return;
375 }
376 xset = 0;
377 for (i = 0; i < rs->rs_count; i++) {
378 u_int8_t rset = rs->rs_rates[i];
379 /* Basic rate defined? */
380 if ((rset & 0x80) && (rset &= 0x7f) >= xset) {
381 xset = rset;
382 }
383 }
384 /*
385 * Set the h/w bit to reflect whether or not the basic
386 * rate is found to be equal or less than 2Mbps.
387 */
388 reg = OS_REG_READ(ah, AR_STA_ID1);
389 if (xset && xset / 2 <= 2) {
390 OS_REG_WRITE(ah, AR_STA_ID1, reg | AR_STA_ID1_BASE_RATE_11B);
391 } else {
392 OS_REG_WRITE(ah, AR_STA_ID1, reg &~ AR_STA_ID1_BASE_RATE_11B);
393 }
394 }
395
396 /*
397 * Grab a semi-random value from hardware registers - may not
398 * change often
399 */
400 u_int32_t
ar9300_get_random_seed(struct ath_hal * ah)401 ar9300_get_random_seed(struct ath_hal *ah)
402 {
403 u_int32_t nf;
404
405 nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff;
406 if (nf & 0x100) {
407 nf = 0 - ((nf ^ 0x1ff) + 1);
408 }
409 return (OS_REG_READ(ah, AR_TSF_U32) ^
410 OS_REG_READ(ah, AR_TSF_L32) ^ nf);
411 }
412
413 /*
414 * Detect if our card is present
415 */
416 HAL_BOOL
ar9300_detect_card_present(struct ath_hal * ah)417 ar9300_detect_card_present(struct ath_hal *ah)
418 {
419 u_int16_t mac_version, mac_rev;
420 u_int32_t v;
421
422 /*
423 * Read the Silicon Revision register and compare that
424 * to what we read at attach time. If the same, we say
425 * a card/device is present.
426 */
427 v = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_SREV)) & AR_SREV_ID;
428 if (v == 0xFF) {
429 /* new SREV format */
430 v = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_SREV));
431 /*
432 * Include 6-bit Chip Type (masked to 0) to differentiate
433 * from pre-Sowl versions
434 */
435 mac_version = (v & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
436 mac_rev = MS(v, AR_SREV_REVISION2);
437 } else {
438 mac_version = MS(v, AR_SREV_VERSION);
439 mac_rev = v & AR_SREV_REVISION;
440 }
441 return (AH_PRIVATE(ah)->ah_macVersion == mac_version &&
442 AH_PRIVATE(ah)->ah_macRev == mac_rev);
443 }
444
445 /*
446 * Update MIB Counters
447 */
448 void
ar9300_update_mib_mac_stats(struct ath_hal * ah)449 ar9300_update_mib_mac_stats(struct ath_hal *ah)
450 {
451 struct ath_hal_9300 *ahp = AH9300(ah);
452 HAL_MIB_STATS* stats = &ahp->ah_stats.ast_mibstats;
453
454 stats->ackrcv_bad += OS_REG_READ(ah, AR_ACK_FAIL);
455 stats->rts_bad += OS_REG_READ(ah, AR_RTS_FAIL);
456 stats->fcs_bad += OS_REG_READ(ah, AR_FCS_FAIL);
457 stats->rts_good += OS_REG_READ(ah, AR_RTS_OK);
458 stats->beacons += OS_REG_READ(ah, AR_BEACON_CNT);
459 }
460
461 void
ar9300_get_mib_mac_stats(struct ath_hal * ah,HAL_MIB_STATS * stats)462 ar9300_get_mib_mac_stats(struct ath_hal *ah, HAL_MIB_STATS* stats)
463 {
464 struct ath_hal_9300 *ahp = AH9300(ah);
465 HAL_MIB_STATS* istats = &ahp->ah_stats.ast_mibstats;
466
467 stats->ackrcv_bad = istats->ackrcv_bad;
468 stats->rts_bad = istats->rts_bad;
469 stats->fcs_bad = istats->fcs_bad;
470 stats->rts_good = istats->rts_good;
471 stats->beacons = istats->beacons;
472 }
473
474 /*
475 * Detect if the HW supports spreading a CCK signal on channel 14
476 */
477 HAL_BOOL
ar9300_is_japan_channel_spread_supported(struct ath_hal * ah)478 ar9300_is_japan_channel_spread_supported(struct ath_hal *ah)
479 {
480 return AH_TRUE;
481 }
482
483 /*
484 * Get the rssi of frame curently being received.
485 */
486 u_int32_t
ar9300_get_cur_rssi(struct ath_hal * ah)487 ar9300_get_cur_rssi(struct ath_hal *ah)
488 {
489 /* XXX return (OS_REG_READ(ah, AR_PHY_CURRENT_RSSI) & 0xff); */
490 /* get combined RSSI */
491 return (OS_REG_READ(ah, AR_PHY_RSSI_3) & 0xff);
492 }
493
494 #if ATH_GEN_RANDOMNESS
495 /*
496 * Get the rssi value from BB on ctl chain0.
497 */
498 u_int32_t
ar9300_get_rssi_chain0(struct ath_hal * ah)499 ar9300_get_rssi_chain0(struct ath_hal *ah)
500 {
501 /* get ctl chain0 RSSI */
502 return OS_REG_READ(ah, AR_PHY_RSSI_0) & 0xff;
503 }
504 #endif
505
506 u_int
ar9300_get_def_antenna(struct ath_hal * ah)507 ar9300_get_def_antenna(struct ath_hal *ah)
508 {
509 return (OS_REG_READ(ah, AR_DEF_ANTENNA) & 0x7);
510 }
511
512 /* Setup coverage class */
513 void
ar9300_set_coverage_class(struct ath_hal * ah,u_int8_t coverageclass,int now)514 ar9300_set_coverage_class(struct ath_hal *ah, u_int8_t coverageclass, int now)
515 {
516 }
517
518 void
ar9300_set_def_antenna(struct ath_hal * ah,u_int antenna)519 ar9300_set_def_antenna(struct ath_hal *ah, u_int antenna)
520 {
521 OS_REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
522 }
523
524 HAL_BOOL
ar9300_set_antenna_switch(struct ath_hal * ah,HAL_ANT_SETTING settings,const struct ieee80211_channel * chan,u_int8_t * tx_chainmask,u_int8_t * rx_chainmask,u_int8_t * antenna_cfgd)525 ar9300_set_antenna_switch(struct ath_hal *ah,
526 HAL_ANT_SETTING settings, const struct ieee80211_channel *chan,
527 u_int8_t *tx_chainmask, u_int8_t *rx_chainmask, u_int8_t *antenna_cfgd)
528 {
529 struct ath_hal_9300 *ahp = AH9300(ah);
530
531 /*
532 * Owl does not support diversity or changing antennas.
533 *
534 * Instead this API and function are defined differently for AR9300.
535 * To support Tablet PC's, this interface allows the system
536 * to dramatically reduce the TX power on a particular chain.
537 *
538 * Based on the value of (redefined) diversity_control, the
539 * reset code will decrease power on chain 0 or chain 1/2.
540 *
541 * Based on the value of bit 0 of antenna_switch_swap,
542 * the mapping between OID call and chain is defined as:
543 * 0: map A -> 0, B -> 1;
544 * 1: map A -> 1, B -> 0;
545 *
546 * NOTE:
547 * The devices that use this OID should use a tx_chain_mask and
548 * tx_chain_select_legacy setting of 5 or 3 if ANTENNA_FIXED_B is
549 * used in order to ensure an active transmit antenna. This
550 * API will allow the host to turn off the only transmitting
551 * antenna to ensure the antenna closest to the user's body is
552 * powered-down.
553 */
554 /*
555 * Set antenna control for use during reset sequence by
556 * ar9300_decrease_chain_power()
557 */
558 ahp->ah_diversity_control = settings;
559
560 return AH_TRUE;
561 }
562
563 HAL_BOOL
ar9300_is_sleep_after_beacon_broken(struct ath_hal * ah)564 ar9300_is_sleep_after_beacon_broken(struct ath_hal *ah)
565 {
566 return AH_TRUE;
567 }
568
569 HAL_BOOL
ar9300_set_slot_time(struct ath_hal * ah,u_int us)570 ar9300_set_slot_time(struct ath_hal *ah, u_int us)
571 {
572 struct ath_hal_9300 *ahp = AH9300(ah);
573 if (us < HAL_SLOT_TIME_9 || us > ar9300_mac_to_usec(ah, 0xffff)) {
574 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: bad slot time %u\n", __func__, us);
575 ahp->ah_slot_time = (u_int) -1; /* restore default handling */
576 return AH_FALSE;
577 } else {
578 /* convert to system clocks */
579 OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ar9300_mac_to_clks(ah, us));
580 ahp->ah_slot_time = us;
581 return AH_TRUE;
582 }
583 }
584
585 HAL_BOOL
ar9300_set_ack_timeout(struct ath_hal * ah,u_int us)586 ar9300_set_ack_timeout(struct ath_hal *ah, u_int us)
587 {
588 struct ath_hal_9300 *ahp = AH9300(ah);
589
590 if (us > ar9300_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
591 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: bad ack timeout %u\n", __func__, us);
592 ahp->ah_ack_timeout = (u_int) -1; /* restore default handling */
593 return AH_FALSE;
594 } else {
595 /* convert to system clocks */
596 OS_REG_RMW_FIELD(ah,
597 AR_TIME_OUT, AR_TIME_OUT_ACK, ar9300_mac_to_clks(ah, us));
598 ahp->ah_ack_timeout = us;
599 return AH_TRUE;
600 }
601 }
602
603 u_int
ar9300_get_ack_timeout(struct ath_hal * ah)604 ar9300_get_ack_timeout(struct ath_hal *ah)
605 {
606 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK);
607 return ar9300_mac_to_usec(ah, clks); /* convert from system clocks */
608 }
609
610 HAL_STATUS
ar9300_set_quiet(struct ath_hal * ah,u_int32_t period,u_int32_t duration,u_int32_t next_start,HAL_QUIET_FLAG flag)611 ar9300_set_quiet(struct ath_hal *ah, u_int32_t period, u_int32_t duration,
612 u_int32_t next_start, HAL_QUIET_FLAG flag)
613 {
614 #define TU_TO_USEC(_tu) ((_tu) << 10)
615 HAL_STATUS status = HAL_EIO;
616 u_int32_t tsf = 0, j, next_start_us = 0;
617 if (flag & HAL_QUIET_ENABLE) {
618 for (j = 0; j < 2; j++) {
619 next_start_us = TU_TO_USEC(next_start);
620 tsf = OS_REG_READ(ah, AR_TSF_L32);
621 if ((!next_start) || (flag & HAL_QUIET_ADD_CURRENT_TSF)) {
622 next_start_us += tsf;
623 }
624 if (flag & HAL_QUIET_ADD_SWBA_RESP_TIME) {
625 next_start_us +=
626 ah->ah_config.ah_sw_beacon_response_time;
627 }
628 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
629 OS_REG_WRITE(ah, AR_QUIET2, SM(duration, AR_QUIET2_QUIET_DUR));
630 OS_REG_WRITE(ah, AR_QUIET_PERIOD, TU_TO_USEC(period));
631 OS_REG_WRITE(ah, AR_NEXT_QUIET_TIMER, next_start_us);
632 OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
633 if ((OS_REG_READ(ah, AR_TSF_L32) >> 10) == tsf >> 10) {
634 status = HAL_OK;
635 break;
636 }
637 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: TSF have moved "
638 "while trying to set quiet time TSF: 0x%08x\n", __func__, tsf);
639 /* TSF shouldn't count twice or reg access is taking forever */
640 HALASSERT(j < 1);
641 }
642 } else {
643 OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
644 status = HAL_OK;
645 }
646
647 return status;
648 #undef TU_TO_USEC
649 }
650 #ifdef ATH_SUPPORT_DFS
651 void
ar9300_cac_tx_quiet(struct ath_hal * ah,HAL_BOOL enable)652 ar9300_cac_tx_quiet(struct ath_hal *ah, HAL_BOOL enable)
653 {
654 u32 reg1, reg2;
655
656 reg1 = OS_REG_READ(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE));
657 reg2 = OS_REG_READ(ah, AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1));
658 AH9300(ah)->ah_cac_quiet_enabled = enable;
659
660 if (enable) {
661 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE),
662 reg1 | AR_PCU_FORCE_QUIET_COLL);
663 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1),
664 reg2 & ~AR_QUIET1_QUIET_ACK_CTS_ENABLE);
665 } else {
666 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE),
667 reg1 & ~AR_PCU_FORCE_QUIET_COLL);
668 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1),
669 reg2 | AR_QUIET1_QUIET_ACK_CTS_ENABLE);
670 }
671 }
672 #endif /* ATH_SUPPORT_DFS */
673
674 void
ar9300_set_pcu_config(struct ath_hal * ah)675 ar9300_set_pcu_config(struct ath_hal *ah)
676 {
677 ar9300_set_operating_mode(ah, AH_PRIVATE(ah)->ah_opmode);
678 }
679
680 HAL_STATUS
ar9300_get_capability(struct ath_hal * ah,HAL_CAPABILITY_TYPE type,u_int32_t capability,u_int32_t * result)681 ar9300_get_capability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
682 u_int32_t capability, u_int32_t *result)
683 {
684 struct ath_hal_9300 *ahp = AH9300(ah);
685 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
686 struct ar9300_ani_state *ani;
687
688 switch (type) {
689 case HAL_CAP_CIPHER: /* cipher handled in hardware */
690 switch (capability) {
691 case HAL_CIPHER_AES_CCM:
692 case HAL_CIPHER_AES_OCB:
693 case HAL_CIPHER_TKIP:
694 case HAL_CIPHER_WEP:
695 case HAL_CIPHER_MIC:
696 case HAL_CIPHER_CLR:
697 return HAL_OK;
698 default:
699 return HAL_ENOTSUPP;
700 }
701 case HAL_CAP_TKIP_MIC: /* handle TKIP MIC in hardware */
702 switch (capability) {
703 case 0: /* hardware capability */
704 return HAL_OK;
705 case 1:
706 return (ahp->ah_sta_id1_defaults &
707 AR_STA_ID1_CRPT_MIC_ENABLE) ? HAL_OK : HAL_ENXIO;
708 default:
709 return HAL_ENOTSUPP;
710 }
711 case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */
712 switch (capability) {
713 case 0: /* hardware capability */
714 return p_cap->halTkipMicTxRxKeySupport ? HAL_ENXIO : HAL_OK;
715 case 1: /* current setting */
716 return (ahp->ah_misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
717 HAL_ENXIO : HAL_OK;
718 default:
719 return HAL_ENOTSUPP;
720 }
721 case HAL_CAP_WME_TKIPMIC:
722 /* hardware can do TKIP MIC when WMM is turned on */
723 return HAL_OK;
724 case HAL_CAP_PHYCOUNTERS: /* hardware PHY error counters */
725 return HAL_OK;
726 case HAL_CAP_DIVERSITY: /* hardware supports fast diversity */
727 switch (capability) {
728 case 0: /* hardware capability */
729 return HAL_OK;
730 case 1: /* current setting */
731 return (OS_REG_READ(ah, AR_PHY_CCK_DETECT) &
732 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
733 HAL_OK : HAL_ENXIO;
734 }
735 return HAL_EINVAL;
736 case HAL_CAP_TPC:
737 switch (capability) {
738 case 0: /* hardware capability */
739 return HAL_OK;
740 case 1:
741 return ah->ah_config.ath_hal_desc_tpc ?
742 HAL_OK : HAL_ENXIO;
743 }
744 return HAL_OK;
745 case HAL_CAP_PHYDIAG: /* radar pulse detection capability */
746 return HAL_OK;
747 case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */
748 switch (capability) {
749 case 0: /* hardware capability */
750 return HAL_OK;
751 case 1:
752 if (OS_REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
753 /*
754 * Owl and Merlin have problems in mcast key search.
755 * Disable this cap. in Ad-hoc mode. see Bug 25776 and
756 * 26802
757 */
758 return HAL_ENXIO;
759 } else {
760 return (ahp->ah_sta_id1_defaults &
761 AR_STA_ID1_MCAST_KSRCH) ? HAL_OK : HAL_ENXIO;
762 }
763 }
764 return HAL_EINVAL;
765 case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */
766 switch (capability) {
767 case 0: /* hardware capability */
768 return p_cap->halTsfAddSupport ? HAL_OK : HAL_ENOTSUPP;
769 case 1:
770 return (ahp->ah_misc_mode & AR_PCU_TX_ADD_TSF) ?
771 HAL_OK : HAL_ENXIO;
772 }
773 return HAL_EINVAL;
774 case HAL_CAP_RFSILENT: /* rfsilent support */
775 if (capability == 3) { /* rfkill interrupt */
776 /*
777 * XXX: Interrupt-based notification of RF Kill state
778 * changes not working yet. Report that this feature
779 * is not supported so that polling is used instead.
780 */
781 return (HAL_ENOTSUPP);
782 }
783 return ath_hal_getcapability(ah, type, capability, result);
784 case HAL_CAP_4ADDR_AGGR:
785 return HAL_OK;
786 case HAL_CAP_BB_RIFS_HANG:
787 return HAL_ENOTSUPP;
788 case HAL_CAP_BB_DFS_HANG:
789 return HAL_ENOTSUPP;
790 case HAL_CAP_BB_RX_CLEAR_STUCK_HANG:
791 /* Track chips that are known to have BB hangs related
792 * to rx_clear stuck low.
793 */
794 return HAL_ENOTSUPP;
795 case HAL_CAP_MAC_HANG:
796 /* Track chips that are known to have MAC hangs.
797 */
798 return HAL_OK;
799 case HAL_CAP_RIFS_RX_ENABLED:
800 /* Is RIFS RX currently enabled */
801 return (ahp->ah_rifs_enabled == AH_TRUE) ? HAL_OK : HAL_ENOTSUPP;
802 #if 0
803 case HAL_CAP_ANT_CFG_2GHZ:
804 *result = p_cap->halNumAntCfg2Ghz;
805 return HAL_OK;
806 case HAL_CAP_ANT_CFG_5GHZ:
807 *result = p_cap->halNumAntCfg5Ghz;
808 return HAL_OK;
809 case HAL_CAP_RX_STBC:
810 *result = p_cap->hal_rx_stbc_support;
811 return HAL_OK;
812 case HAL_CAP_TX_STBC:
813 *result = p_cap->hal_tx_stbc_support;
814 return HAL_OK;
815 #endif
816 case HAL_CAP_LDPC:
817 *result = p_cap->halLDPCSupport;
818 return HAL_OK;
819 case HAL_CAP_DYNAMIC_SMPS:
820 return HAL_OK;
821 case HAL_CAP_DS:
822 return (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah) ||
823 (p_cap->halTxChainMask & 0x3) != 0x3 ||
824 (p_cap->halRxChainMask & 0x3) != 0x3) ?
825 HAL_ENOTSUPP : HAL_OK;
826 case HAL_CAP_TS:
827 return (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah) ||
828 (p_cap->halTxChainMask & 0x7) != 0x7 ||
829 (p_cap->halRxChainMask & 0x7) != 0x7) ?
830 HAL_ENOTSUPP : HAL_OK;
831 case HAL_CAP_OL_PWRCTRL:
832 return (ar9300_eeprom_get(ahp, EEP_OL_PWRCTRL)) ?
833 HAL_OK : HAL_ENOTSUPP;
834 case HAL_CAP_CRDC:
835 #if ATH_SUPPORT_CRDC
836 return (AR_SREV_WASP(ah) &&
837 ah->ah_config.ath_hal_crdc_enable) ?
838 HAL_OK : HAL_ENOTSUPP;
839 #else
840 return HAL_ENOTSUPP;
841 #endif
842 #if 0
843 case HAL_CAP_MAX_WEP_TKIP_HT20_TX_RATEKBPS:
844 *result = (u_int32_t)(-1);
845 return HAL_OK;
846 case HAL_CAP_MAX_WEP_TKIP_HT40_TX_RATEKBPS:
847 *result = (u_int32_t)(-1);
848 return HAL_OK;
849 #endif
850 case HAL_CAP_BB_PANIC_WATCHDOG:
851 return HAL_OK;
852 case HAL_CAP_PHYRESTART_CLR_WAR:
853 if ((AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_OSPREY) &&
854 (AH_PRIVATE((ah))->ah_macRev < AR_SREV_REVISION_AR9580_10))
855 {
856 return HAL_OK;
857 }
858 else
859 {
860 return HAL_ENOTSUPP;
861 }
862 case HAL_CAP_ENTERPRISE_MODE:
863 *result = ahp->ah_enterprise_mode >> 16;
864 /*
865 * WAR for EV 77658 - Add delimiters to first sub-frame when using
866 * RTS/CTS with aggregation and non-enterprise Osprey.
867 *
868 * Bug fixed in AR9580/Peacock, Wasp1.1 and later
869 */
870 if ((ahp->ah_enterprise_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE) &&
871 !AR_SREV_AR9580_10_OR_LATER(ah) && (!AR_SREV_WASP(ah) ||
872 AR_SREV_WASP_10(ah))) {
873 *result |= AH_ENT_RTSCTS_DELIM_WAR;
874 }
875 return HAL_OK;
876 case HAL_CAP_LDPCWAR:
877 /* WAR for RIFS+LDPC issue is required for all chips currently
878 * supported by ar9300 HAL.
879 */
880 return HAL_OK;
881 case HAL_CAP_ENABLE_APM:
882 *result = p_cap->halApmEnable;
883 return HAL_OK;
884 case HAL_CAP_PCIE_LCR_EXTSYNC_EN:
885 return (p_cap->hal_pcie_lcr_extsync_en == AH_TRUE) ? HAL_OK : HAL_ENOTSUPP;
886 case HAL_CAP_PCIE_LCR_OFFSET:
887 *result = p_cap->hal_pcie_lcr_offset;
888 return HAL_OK;
889 case HAL_CAP_SMARTANTENNA:
890 /* FIXME A request is pending with h/w team to add feature bit in
891 * caldata to detect if board has smart antenna or not, once added
892 * we need to fix his piece of code to read and return value without
893 * any compile flags
894 */
895 #if UMAC_SUPPORT_SMARTANTENNA
896 /* enable smart antenna for Peacock, Wasp and scorpion
897 for future chips need to modify */
898 if (AR_SREV_AR9580_10(ah) || (AR_SREV_WASP(ah)) || AR_SREV_SCORPION(ah)) {
899 return HAL_OK;
900 } else {
901 return HAL_ENOTSUPP;
902 }
903 #else
904 return HAL_ENOTSUPP;
905 #endif
906
907 #ifdef ATH_TRAFFIC_FAST_RECOVER
908 case HAL_CAP_TRAFFIC_FAST_RECOVER:
909 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_WASP_11(ah)) {
910 return HAL_OK;
911 } else {
912 return HAL_ENOTSUPP;
913 }
914 #endif
915
916 /* FreeBSD ANI */
917 case HAL_CAP_INTMIT: /* interference mitigation */
918 switch (capability) {
919 case HAL_CAP_INTMIT_PRESENT: /* hardware capability */
920 return HAL_OK;
921 case HAL_CAP_INTMIT_ENABLE:
922 return (ahp->ah_proc_phy_err & HAL_PROCESS_ANI) ?
923 HAL_OK : HAL_ENXIO;
924 case HAL_CAP_INTMIT_NOISE_IMMUNITY_LEVEL:
925 case HAL_CAP_INTMIT_OFDM_WEAK_SIGNAL_LEVEL:
926 // case HAL_CAP_INTMIT_CCK_WEAK_SIGNAL_THR:
927 case HAL_CAP_INTMIT_FIRSTEP_LEVEL:
928 case HAL_CAP_INTMIT_SPUR_IMMUNITY_LEVEL:
929 ani = ar9300_ani_get_current_state(ah);
930 if (ani == AH_NULL)
931 return HAL_ENXIO;
932 switch (capability) {
933 /* XXX AR9300 HAL has OFDM/CCK noise immunity level params? */
934 case 2: *result = ani->ofdm_noise_immunity_level; break;
935 case 3: *result = !ani->ofdm_weak_sig_detect_off; break;
936 // case 4: *result = ani->cck_weak_sig_threshold; break;
937 case 5: *result = ani->firstep_level; break;
938 case 6: *result = ani->spur_immunity_level; break;
939 }
940 return HAL_OK;
941 }
942 return HAL_EINVAL;
943 case HAL_CAP_ENFORCE_TXOP:
944 if (capability == 0)
945 return (HAL_OK);
946 if (capability != 1)
947 return (HAL_ENOTSUPP);
948 (*result) = !! (ahp->ah_misc_mode & AR_PCU_TXOP_TBTT_LIMIT_ENA);
949 return (HAL_OK);
950 default:
951 return ath_hal_getcapability(ah, type, capability, result);
952 }
953 }
954
955 HAL_BOOL
ar9300_set_capability(struct ath_hal * ah,HAL_CAPABILITY_TYPE type,u_int32_t capability,u_int32_t setting,HAL_STATUS * status)956 ar9300_set_capability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
957 u_int32_t capability, u_int32_t setting, HAL_STATUS *status)
958 {
959 struct ath_hal_9300 *ahp = AH9300(ah);
960 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
961 u_int32_t v;
962
963 switch (type) {
964 case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */
965 if (! p_cap->halTkipMicTxRxKeySupport)
966 return AH_FALSE;
967
968 if (setting)
969 ahp->ah_misc_mode &= ~AR_PCU_MIC_NEW_LOC_ENA;
970 else
971 ahp->ah_misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
972
973 OS_REG_WRITE(ah, AR_PCU_MISC, ahp->ah_misc_mode);
974 return AH_TRUE;
975
976 case HAL_CAP_TKIP_MIC: /* handle TKIP MIC in hardware */
977 if (setting) {
978 ahp->ah_sta_id1_defaults |= AR_STA_ID1_CRPT_MIC_ENABLE;
979 } else {
980 ahp->ah_sta_id1_defaults &= ~AR_STA_ID1_CRPT_MIC_ENABLE;
981 }
982 return AH_TRUE;
983 case HAL_CAP_DIVERSITY:
984 v = OS_REG_READ(ah, AR_PHY_CCK_DETECT);
985 if (setting) {
986 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
987 } else {
988 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
989 }
990 OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
991 return AH_TRUE;
992 case HAL_CAP_DIAG: /* hardware diagnostic support */
993 /*
994 * NB: could split this up into virtual capabilities,
995 * (e.g. 1 => ACK, 2 => CTS, etc.) but it hardly
996 * seems worth the additional complexity.
997 */
998 #ifdef AH_DEBUG
999 AH_PRIVATE(ah)->ah_diagreg = setting;
1000 #else
1001 AH_PRIVATE(ah)->ah_diagreg = setting & 0x6; /* ACK+CTS */
1002 #endif
1003 OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);
1004 return AH_TRUE;
1005 case HAL_CAP_TPC:
1006 ah->ah_config.ath_hal_desc_tpc = (setting != 0);
1007 return AH_TRUE;
1008 case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */
1009 if (setting) {
1010 ahp->ah_sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
1011 } else {
1012 ahp->ah_sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
1013 }
1014 return AH_TRUE;
1015 case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */
1016 if (p_cap->halTsfAddSupport) {
1017 if (setting) {
1018 ahp->ah_misc_mode |= AR_PCU_TX_ADD_TSF;
1019 } else {
1020 ahp->ah_misc_mode &= ~AR_PCU_TX_ADD_TSF;
1021 }
1022 return AH_TRUE;
1023 }
1024 return AH_FALSE;
1025
1026 /* FreeBSD interrupt mitigation / ANI */
1027 case HAL_CAP_INTMIT: { /* interference mitigation */
1028 /* This maps the public ANI commands to the internal ANI commands */
1029 /* Private: HAL_ANI_CMD; Public: HAL_CAP_INTMIT_CMD */
1030 static const HAL_ANI_CMD cmds[] = {
1031 HAL_ANI_PRESENT,
1032 HAL_ANI_MODE,
1033 HAL_ANI_NOISE_IMMUNITY_LEVEL,
1034 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
1035 HAL_ANI_CCK_WEAK_SIGNAL_THR,
1036 HAL_ANI_FIRSTEP_LEVEL,
1037 HAL_ANI_SPUR_IMMUNITY_LEVEL,
1038 };
1039 #define N(a) (sizeof(a) / sizeof(a[0]))
1040 return capability < N(cmds) ?
1041 ar9300_ani_control(ah, cmds[capability], setting) :
1042 AH_FALSE;
1043 #undef N
1044 }
1045
1046 case HAL_CAP_RXBUFSIZE: /* set MAC receive buffer size */
1047 ahp->rx_buf_size = setting & AR_DATABUF_MASK;
1048 OS_REG_WRITE(ah, AR_DATABUF, ahp->rx_buf_size);
1049 return AH_TRUE;
1050
1051 case HAL_CAP_ENFORCE_TXOP:
1052 if (capability != 1)
1053 return AH_FALSE;
1054 if (setting) {
1055 ahp->ah_misc_mode |= AR_PCU_TXOP_TBTT_LIMIT_ENA;
1056 OS_REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_TXOP_TBTT_LIMIT_ENA);
1057 } else {
1058 ahp->ah_misc_mode &= ~AR_PCU_TXOP_TBTT_LIMIT_ENA;
1059 OS_REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_TXOP_TBTT_LIMIT_ENA);
1060 }
1061 return AH_TRUE;
1062
1063 /* fall thru... */
1064 default:
1065 return ath_hal_setcapability(ah, type, capability, setting, status);
1066 }
1067 }
1068
1069 #ifdef AH_DEBUG
1070 static void
ar9300_print_reg(struct ath_hal * ah,u_int32_t args)1071 ar9300_print_reg(struct ath_hal *ah, u_int32_t args)
1072 {
1073 u_int32_t i = 0;
1074
1075 /* Read 0x80d0 to trigger pcie analyzer */
1076 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1077 "0x%04x 0x%08x\n", 0x80d0, OS_REG_READ(ah, 0x80d0));
1078
1079 if (args & HAL_DIAG_PRINT_REG_COUNTER) {
1080 struct ath_hal_9300 *ahp = AH9300(ah);
1081 u_int32_t tf, rf, rc, cc;
1082
1083 tf = OS_REG_READ(ah, AR_TFCNT);
1084 rf = OS_REG_READ(ah, AR_RFCNT);
1085 rc = OS_REG_READ(ah, AR_RCCNT);
1086 cc = OS_REG_READ(ah, AR_CCCNT);
1087
1088 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1089 "AR_TFCNT Diff= 0x%x\n", tf - ahp->last_tf);
1090 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1091 "AR_RFCNT Diff= 0x%x\n", rf - ahp->last_rf);
1092 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1093 "AR_RCCNT Diff= 0x%x\n", rc - ahp->last_rc);
1094 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1095 "AR_CCCNT Diff= 0x%x\n", cc - ahp->last_cc);
1096
1097 ahp->last_tf = tf;
1098 ahp->last_rf = rf;
1099 ahp->last_rc = rc;
1100 ahp->last_cc = cc;
1101
1102 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1103 "DMADBG0 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_0));
1104 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1105 "DMADBG1 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_1));
1106 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1107 "DMADBG2 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_2));
1108 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1109 "DMADBG3 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_3));
1110 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1111 "DMADBG4 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_4));
1112 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1113 "DMADBG5 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_5));
1114 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1115 "DMADBG6 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_6));
1116 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1117 "DMADBG7 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_7));
1118 }
1119
1120 if (args & HAL_DIAG_PRINT_REG_ALL) {
1121 for (i = 0x8; i <= 0xB8; i += sizeof(u_int32_t)) {
1122 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1123 i, OS_REG_READ(ah, i));
1124 }
1125
1126 for (i = 0x800; i <= (0x800 + (10 << 2)); i += sizeof(u_int32_t)) {
1127 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1128 i, OS_REG_READ(ah, i));
1129 }
1130
1131 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1132 "0x%04x 0x%08x\n", 0x840, OS_REG_READ(ah, i));
1133
1134 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1135 "0x%04x 0x%08x\n", 0x880, OS_REG_READ(ah, i));
1136
1137 for (i = 0x8C0; i <= (0x8C0 + (10 << 2)); i += sizeof(u_int32_t)) {
1138 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1139 i, OS_REG_READ(ah, i));
1140 }
1141
1142 for (i = 0x1F00; i <= 0x1F04; i += sizeof(u_int32_t)) {
1143 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1144 i, OS_REG_READ(ah, i));
1145 }
1146
1147 for (i = 0x4000; i <= 0x408C; i += sizeof(u_int32_t)) {
1148 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1149 i, OS_REG_READ(ah, i));
1150 }
1151
1152 for (i = 0x5000; i <= 0x503C; i += sizeof(u_int32_t)) {
1153 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1154 i, OS_REG_READ(ah, i));
1155 }
1156
1157 for (i = 0x7040; i <= 0x7058; i += sizeof(u_int32_t)) {
1158 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1159 i, OS_REG_READ(ah, i));
1160 }
1161
1162 for (i = 0x8000; i <= 0x8098; i += sizeof(u_int32_t)) {
1163 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1164 i, OS_REG_READ(ah, i));
1165 }
1166
1167 for (i = 0x80D4; i <= 0x8200; i += sizeof(u_int32_t)) {
1168 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1169 i, OS_REG_READ(ah, i));
1170 }
1171
1172 for (i = 0x8240; i <= 0x97FC; i += sizeof(u_int32_t)) {
1173 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1174 i, OS_REG_READ(ah, i));
1175 }
1176
1177 for (i = 0x9800; i <= 0x99f0; i += sizeof(u_int32_t)) {
1178 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1179 i, OS_REG_READ(ah, i));
1180 }
1181
1182 for (i = 0x9c10; i <= 0x9CFC; i += sizeof(u_int32_t)) {
1183 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1184 i, OS_REG_READ(ah, i));
1185 }
1186
1187 for (i = 0xA200; i <= 0xA26C; i += sizeof(u_int32_t)) {
1188 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1189 i, OS_REG_READ(ah, i));
1190 }
1191 }
1192 }
1193 #endif
1194
1195 HAL_BOOL
ar9300_get_diag_state(struct ath_hal * ah,int request,const void * args,u_int32_t argsize,void ** result,u_int32_t * resultsize)1196 ar9300_get_diag_state(struct ath_hal *ah, int request,
1197 const void *args, u_int32_t argsize,
1198 void **result, u_int32_t *resultsize)
1199 {
1200 struct ath_hal_9300 *ahp = AH9300(ah);
1201 struct ar9300_ani_state *ani;
1202
1203 (void) ahp;
1204 if (ath_hal_getdiagstate(ah, request, args, argsize, result, resultsize)) {
1205 return AH_TRUE;
1206 }
1207 switch (request) {
1208 #ifdef AH_PRIVATE_DIAG
1209 case HAL_DIAG_EEPROM:
1210 *result = &ahp->ah_eeprom;
1211 *resultsize = sizeof(ar9300_eeprom_t);
1212 return AH_TRUE;
1213
1214 #if 0 /* XXX - TODO */
1215 case HAL_DIAG_EEPROM_EXP_11A:
1216 case HAL_DIAG_EEPROM_EXP_11B:
1217 case HAL_DIAG_EEPROM_EXP_11G:
1218 pe = &ahp->ah_mode_power_array2133[request - HAL_DIAG_EEPROM_EXP_11A];
1219 *result = pe->p_channels;
1220 *resultsize = (*result == AH_NULL) ? 0 :
1221 roundup(sizeof(u_int16_t) * pe->num_channels,
1222 sizeof(u_int32_t)) +
1223 sizeof(EXPN_DATA_PER_CHANNEL_2133) * pe->num_channels;
1224 return AH_TRUE;
1225 #endif
1226 case HAL_DIAG_RFGAIN:
1227 *result = &ahp->ah_gain_values;
1228 *resultsize = sizeof(GAIN_VALUES);
1229 return AH_TRUE;
1230 case HAL_DIAG_RFGAIN_CURSTEP:
1231 *result = (void *) ahp->ah_gain_values.curr_step;
1232 *resultsize = (*result == AH_NULL) ?
1233 0 : sizeof(GAIN_OPTIMIZATION_STEP);
1234 return AH_TRUE;
1235 #if 0 /* XXX - TODO */
1236 case HAL_DIAG_PCDAC:
1237 *result = ahp->ah_pcdac_table;
1238 *resultsize = ahp->ah_pcdac_table_size;
1239 return AH_TRUE;
1240 #endif
1241 case HAL_DIAG_ANI_CURRENT:
1242
1243 ani = ar9300_ani_get_current_state(ah);
1244 if (ani == AH_NULL)
1245 return AH_FALSE;
1246 /* Convert ar9300 HAL to FreeBSD HAL ANI state */
1247 /* XXX TODO: add all of these to the HAL ANI state structure */
1248 bzero(&ahp->ext_ani_state, sizeof(ahp->ext_ani_state));
1249 /* XXX should this be OFDM or CCK noise immunity level? */
1250 ahp->ext_ani_state.noiseImmunityLevel = ani->ofdm_noise_immunity_level;
1251 ahp->ext_ani_state.spurImmunityLevel = ani->spur_immunity_level;
1252 ahp->ext_ani_state.firstepLevel = ani->firstep_level;
1253 ahp->ext_ani_state.ofdmWeakSigDetectOff = ani->ofdm_weak_sig_detect_off;
1254 /* mrc_cck_off */
1255 /* cck_noise_immunity_level */
1256
1257 ahp->ext_ani_state.listenTime = ani->listen_time;
1258
1259 *result = &ahp->ext_ani_state;
1260 *resultsize = sizeof(ahp->ext_ani_state);
1261 #if 0
1262 *result = ar9300_ani_get_current_state(ah);
1263 *resultsize = (*result == AH_NULL) ?
1264 0 : sizeof(struct ar9300_ani_state);
1265 #endif
1266 return AH_TRUE;
1267 case HAL_DIAG_ANI_STATS:
1268 *result = ar9300_ani_get_current_stats(ah);
1269 *resultsize = (*result == AH_NULL) ?
1270 0 : sizeof(HAL_ANI_STATS);
1271 return AH_TRUE;
1272 case HAL_DIAG_ANI_CMD:
1273 if (argsize != 2*sizeof(u_int32_t)) {
1274 return AH_FALSE;
1275 }
1276 ar9300_ani_control(
1277 ah, ((const u_int32_t *)args)[0], ((const u_int32_t *)args)[1]);
1278 return AH_TRUE;
1279 #if 0
1280 case HAL_DIAG_TXCONT:
1281 /*AR9300_CONTTXMODE(ah, (struct ath_desc *)args, argsize );*/
1282 return AH_TRUE;
1283 #endif /* 0 */
1284 #endif /* AH_PRIVATE_DIAG */
1285 case HAL_DIAG_CHANNELS:
1286 #if 0
1287 *result = &(ahp->ah_priv.ah_channels[0]);
1288 *resultsize =
1289 sizeof(ahp->ah_priv.ah_channels[0]) * ahp->ah_priv.priv.ah_nchan;
1290 #endif
1291 return AH_TRUE;
1292 #ifdef AH_DEBUG
1293 case HAL_DIAG_PRINT_REG:
1294 ar9300_print_reg(ah, *((const u_int32_t *)args));
1295 return AH_TRUE;
1296 #endif
1297 default:
1298 break;
1299 }
1300
1301 return AH_FALSE;
1302 }
1303
1304 void
ar9300_dma_reg_dump(struct ath_hal * ah)1305 ar9300_dma_reg_dump(struct ath_hal *ah)
1306 {
1307 #ifdef AH_DEBUG
1308 #define NUM_DMA_DEBUG_REGS 8
1309 #define NUM_QUEUES 10
1310
1311 u_int32_t val[NUM_DMA_DEBUG_REGS];
1312 int qcu_offset = 0, dcu_offset = 0;
1313 u_int32_t *qcu_base = &val[0], *dcu_base = &val[4], reg;
1314 int i, j, k;
1315 int16_t nfarray[HAL_NUM_NF_READINGS];
1316 #ifdef ATH_NF_PER_CHAN
1317 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, AH_PRIVATE(ah)->ah_curchan);
1318 #endif /* ATH_NF_PER_CHAN */
1319 HAL_NFCAL_HIST_FULL *h = AH_HOME_CHAN_NFCAL_HIST(ah, ichan);
1320
1321 /* selecting DMA OBS 8 */
1322 OS_REG_WRITE(ah, AR_MACMISC,
1323 ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) |
1324 (AR_MACMISC_MISC_OBS_BUS_1 << AR_MACMISC_MISC_OBS_BUS_MSB_S)));
1325
1326 ath_hal_printf(ah, "Raw DMA Debug values:\n");
1327 for (i = 0; i < NUM_DMA_DEBUG_REGS; i++) {
1328 if (i % 4 == 0) {
1329 ath_hal_printf(ah, "\n");
1330 }
1331
1332 val[i] = OS_REG_READ(ah, AR_DMADBG_0 + (i * sizeof(u_int32_t)));
1333 ath_hal_printf(ah, "%d: %08x ", i, val[i]);
1334 }
1335
1336 ath_hal_printf(ah, "\n\n");
1337 ath_hal_printf(ah, "Num QCU: chain_st fsp_ok fsp_st DCU: chain_st\n");
1338
1339 for (i = 0; i < NUM_QUEUES; i++, qcu_offset += 4, dcu_offset += 5) {
1340 if (i == 8) {
1341 /* only 8 QCU entries in val[0] */
1342 qcu_offset = 0;
1343 qcu_base++;
1344 }
1345
1346 if (i == 6) {
1347 /* only 6 DCU entries in val[4] */
1348 dcu_offset = 0;
1349 dcu_base++;
1350 }
1351
1352 ath_hal_printf(ah,
1353 "%2d %2x %1x %2x %2x\n",
1354 i,
1355 (*qcu_base & (0x7 << qcu_offset)) >> qcu_offset,
1356 (*qcu_base & (0x8 << qcu_offset)) >> (qcu_offset + 3),
1357 val[2] & (0x7 << (i * 3)) >> (i * 3),
1358 (*dcu_base & (0x1f << dcu_offset)) >> dcu_offset);
1359 }
1360
1361 ath_hal_printf(ah, "\n");
1362 ath_hal_printf(ah,
1363 "qcu_stitch state: %2x qcu_fetch state: %2x\n",
1364 (val[3] & 0x003c0000) >> 18, (val[3] & 0x03c00000) >> 22);
1365 ath_hal_printf(ah,
1366 "qcu_complete state: %2x dcu_complete state: %2x\n",
1367 (val[3] & 0x1c000000) >> 26, (val[6] & 0x3));
1368 ath_hal_printf(ah,
1369 "dcu_arb state: %2x dcu_fp state: %2x\n",
1370 (val[5] & 0x06000000) >> 25, (val[5] & 0x38000000) >> 27);
1371 ath_hal_printf(ah,
1372 "chan_idle_dur: %3d chan_idle_dur_valid: %1d\n",
1373 (val[6] & 0x000003fc) >> 2, (val[6] & 0x00000400) >> 10);
1374 ath_hal_printf(ah,
1375 "txfifo_valid_0: %1d txfifo_valid_1: %1d\n",
1376 (val[6] & 0x00000800) >> 11, (val[6] & 0x00001000) >> 12);
1377 ath_hal_printf(ah,
1378 "txfifo_dcu_num_0: %2d txfifo_dcu_num_1: %2d\n",
1379 (val[6] & 0x0001e000) >> 13, (val[6] & 0x001e0000) >> 17);
1380 ath_hal_printf(ah, "pcu observe 0x%x \n", OS_REG_READ(ah, AR_OBS_BUS_1));
1381 ath_hal_printf(ah, "AR_CR 0x%x \n", OS_REG_READ(ah, AR_CR));
1382
1383 ar9300_upload_noise_floor(ah, 1, nfarray);
1384 ath_hal_printf(ah, "2G:\n");
1385 ath_hal_printf(ah, "Min CCA Out:\n");
1386 ath_hal_printf(ah, "\t\tChain 0\t\tChain 1\t\tChain 2\n");
1387 ath_hal_printf(ah, "Control:\t%8d\t%8d\t%8d\n",
1388 nfarray[0], nfarray[1], nfarray[2]);
1389 ath_hal_printf(ah, "Extension:\t%8d\t%8d\t%8d\n\n",
1390 nfarray[3], nfarray[4], nfarray[5]);
1391
1392 ar9300_upload_noise_floor(ah, 0, nfarray);
1393 ath_hal_printf(ah, "5G:\n");
1394 ath_hal_printf(ah, "Min CCA Out:\n");
1395 ath_hal_printf(ah, "\t\tChain 0\t\tChain 1\t\tChain 2\n");
1396 ath_hal_printf(ah, "Control:\t%8d\t%8d\t%8d\n",
1397 nfarray[0], nfarray[1], nfarray[2]);
1398 ath_hal_printf(ah, "Extension:\t%8d\t%8d\t%8d\n\n",
1399 nfarray[3], nfarray[4], nfarray[5]);
1400
1401 for (i = 0; i < HAL_NUM_NF_READINGS; i++) {
1402 ath_hal_printf(ah, "%s Chain %d NF History:\n",
1403 ((i < 3) ? "Control " : "Extension "), i%3);
1404 for (j = 0, k = h->base.curr_index;
1405 j < HAL_NF_CAL_HIST_LEN_FULL;
1406 j++, k++) {
1407 ath_hal_printf(ah, "Element %d: %d\n",
1408 j, h->nf_cal_buffer[k % HAL_NF_CAL_HIST_LEN_FULL][i]);
1409 }
1410 ath_hal_printf(ah, "Last Programmed NF: %d\n\n", h->base.priv_nf[i]);
1411 }
1412
1413 reg = OS_REG_READ(ah, AR_PHY_FIND_SIG_LOW);
1414 ath_hal_printf(ah, "FIRStep Low = 0x%x (%d)\n",
1415 MS(reg, AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW),
1416 MS(reg, AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW));
1417 reg = OS_REG_READ(ah, AR_PHY_DESIRED_SZ);
1418 ath_hal_printf(ah, "Total Desired = 0x%x (%d)\n",
1419 MS(reg, AR_PHY_DESIRED_SZ_TOT_DES),
1420 MS(reg, AR_PHY_DESIRED_SZ_TOT_DES));
1421 ath_hal_printf(ah, "ADC Desired = 0x%x (%d)\n",
1422 MS(reg, AR_PHY_DESIRED_SZ_ADC),
1423 MS(reg, AR_PHY_DESIRED_SZ_ADC));
1424 reg = OS_REG_READ(ah, AR_PHY_FIND_SIG);
1425 ath_hal_printf(ah, "FIRStep = 0x%x (%d)\n",
1426 MS(reg, AR_PHY_FIND_SIG_FIRSTEP),
1427 MS(reg, AR_PHY_FIND_SIG_FIRSTEP));
1428 reg = OS_REG_READ(ah, AR_PHY_AGC);
1429 ath_hal_printf(ah, "Coarse High = 0x%x (%d)\n",
1430 MS(reg, AR_PHY_AGC_COARSE_HIGH),
1431 MS(reg, AR_PHY_AGC_COARSE_HIGH));
1432 ath_hal_printf(ah, "Coarse Low = 0x%x (%d)\n",
1433 MS(reg, AR_PHY_AGC_COARSE_LOW),
1434 MS(reg, AR_PHY_AGC_COARSE_LOW));
1435 ath_hal_printf(ah, "Coarse Power Constant = 0x%x (%d)\n",
1436 MS(reg, AR_PHY_AGC_COARSE_PWR_CONST),
1437 MS(reg, AR_PHY_AGC_COARSE_PWR_CONST));
1438 reg = OS_REG_READ(ah, AR_PHY_TIMING5);
1439 ath_hal_printf(ah, "Enable Cyclic Power Thresh = %d\n",
1440 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1_ENABLE));
1441 ath_hal_printf(ah, "Cyclic Power Thresh = 0x%x (%d)\n",
1442 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1),
1443 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1));
1444 ath_hal_printf(ah, "Cyclic Power Thresh 1A= 0x%x (%d)\n",
1445 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1A),
1446 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1A));
1447 reg = OS_REG_READ(ah, AR_PHY_DAG_CTRLCCK);
1448 ath_hal_printf(ah, "Barker RSSI Thresh Enable = %d\n",
1449 MS(reg, AR_PHY_DAG_CTRLCCK_EN_RSSI_THR));
1450 ath_hal_printf(ah, "Barker RSSI Thresh = 0x%x (%d)\n",
1451 MS(reg, AR_PHY_DAG_CTRLCCK_RSSI_THR),
1452 MS(reg, AR_PHY_DAG_CTRLCCK_RSSI_THR));
1453
1454
1455 /* Step 1a: Set bit 23 of register 0xa360 to 0 */
1456 reg = OS_REG_READ(ah, 0xa360);
1457 reg &= ~0x00800000;
1458 OS_REG_WRITE(ah, 0xa360, reg);
1459
1460 /* Step 2a: Set register 0xa364 to 0x1000 */
1461 reg = 0x1000;
1462 OS_REG_WRITE(ah, 0xa364, reg);
1463
1464 /* Step 3a: Read bits 17:0 of register 0x9c20 */
1465 reg = OS_REG_READ(ah, 0x9c20);
1466 reg &= 0x0003ffff;
1467 ath_hal_printf(ah,
1468 "%s: Test Control Status [0x1000] 0x9c20[17:0] = 0x%x\n",
1469 __func__, reg);
1470
1471 /* Step 1b: Set bit 23 of register 0xa360 to 0 */
1472 reg = OS_REG_READ(ah, 0xa360);
1473 reg &= ~0x00800000;
1474 OS_REG_WRITE(ah, 0xa360, reg);
1475
1476 /* Step 2b: Set register 0xa364 to 0x1400 */
1477 reg = 0x1400;
1478 OS_REG_WRITE(ah, 0xa364, reg);
1479
1480 /* Step 3b: Read bits 17:0 of register 0x9c20 */
1481 reg = OS_REG_READ(ah, 0x9c20);
1482 reg &= 0x0003ffff;
1483 ath_hal_printf(ah,
1484 "%s: Test Control Status [0x1400] 0x9c20[17:0] = 0x%x\n",
1485 __func__, reg);
1486
1487 /* Step 1c: Set bit 23 of register 0xa360 to 0 */
1488 reg = OS_REG_READ(ah, 0xa360);
1489 reg &= ~0x00800000;
1490 OS_REG_WRITE(ah, 0xa360, reg);
1491
1492 /* Step 2c: Set register 0xa364 to 0x3C00 */
1493 reg = 0x3c00;
1494 OS_REG_WRITE(ah, 0xa364, reg);
1495
1496 /* Step 3c: Read bits 17:0 of register 0x9c20 */
1497 reg = OS_REG_READ(ah, 0x9c20);
1498 reg &= 0x0003ffff;
1499 ath_hal_printf(ah,
1500 "%s: Test Control Status [0x3C00] 0x9c20[17:0] = 0x%x\n",
1501 __func__, reg);
1502
1503 /* Step 1d: Set bit 24 of register 0xa360 to 0 */
1504 reg = OS_REG_READ(ah, 0xa360);
1505 reg &= ~0x001040000;
1506 OS_REG_WRITE(ah, 0xa360, reg);
1507
1508 /* Step 2d: Set register 0xa364 to 0x5005D */
1509 reg = 0x5005D;
1510 OS_REG_WRITE(ah, 0xa364, reg);
1511
1512 /* Step 3d: Read bits 17:0 of register 0xa368 */
1513 reg = OS_REG_READ(ah, 0xa368);
1514 reg &= 0x0003ffff;
1515 ath_hal_printf(ah,
1516 "%s: Test Control Status [0x5005D] 0xa368[17:0] = 0x%x\n",
1517 __func__, reg);
1518
1519 /* Step 1e: Set bit 24 of register 0xa360 to 0 */
1520 reg = OS_REG_READ(ah, 0xa360);
1521 reg &= ~0x001040000;
1522 OS_REG_WRITE(ah, 0xa360, reg);
1523
1524 /* Step 2e: Set register 0xa364 to 0x7005D */
1525 reg = 0x7005D;
1526 OS_REG_WRITE(ah, 0xa364, reg);
1527
1528 /* Step 3e: Read bits 17:0 of register 0xa368 */
1529 reg = OS_REG_READ(ah, 0xa368);
1530 reg &= 0x0003ffff;
1531 ath_hal_printf(ah,
1532 "%s: Test Control Status [0x7005D] 0xa368[17:0] = 0x%x\n",
1533 __func__, reg);
1534
1535 /* Step 1f: Set bit 24 of register 0xa360 to 0 */
1536 reg = OS_REG_READ(ah, 0xa360);
1537 reg &= ~0x001000000;
1538 reg |= 0x40000;
1539 OS_REG_WRITE(ah, 0xa360, reg);
1540
1541 /* Step 2f: Set register 0xa364 to 0x3005D */
1542 reg = 0x3005D;
1543 OS_REG_WRITE(ah, 0xa364, reg);
1544
1545 /* Step 3f: Read bits 17:0 of register 0xa368 */
1546 reg = OS_REG_READ(ah, 0xa368);
1547 reg &= 0x0003ffff;
1548 ath_hal_printf(ah,
1549 "%s: Test Control Status [0x3005D] 0xa368[17:0] = 0x%x\n",
1550 __func__, reg);
1551
1552 /* Step 1g: Set bit 24 of register 0xa360 to 0 */
1553 reg = OS_REG_READ(ah, 0xa360);
1554 reg &= ~0x001000000;
1555 reg |= 0x40000;
1556 OS_REG_WRITE(ah, 0xa360, reg);
1557
1558 /* Step 2g: Set register 0xa364 to 0x6005D */
1559 reg = 0x6005D;
1560 OS_REG_WRITE(ah, 0xa364, reg);
1561
1562 /* Step 3g: Read bits 17:0 of register 0xa368 */
1563 reg = OS_REG_READ(ah, 0xa368);
1564 reg &= 0x0003ffff;
1565 ath_hal_printf(ah,
1566 "%s: Test Control Status [0x6005D] 0xa368[17:0] = 0x%x\n",
1567 __func__, reg);
1568 #endif /* AH_DEBUG */
1569 }
1570
1571 /*
1572 * Return the busy for rx_frame, rx_clear, and tx_frame
1573 */
1574 u_int32_t
ar9300_get_mib_cycle_counts_pct(struct ath_hal * ah,u_int32_t * rxc_pcnt,u_int32_t * rxf_pcnt,u_int32_t * txf_pcnt)1575 ar9300_get_mib_cycle_counts_pct(struct ath_hal *ah, u_int32_t *rxc_pcnt,
1576 u_int32_t *rxf_pcnt, u_int32_t *txf_pcnt)
1577 {
1578 struct ath_hal_9300 *ahp = AH9300(ah);
1579 u_int32_t good = 1;
1580
1581 u_int32_t rc = OS_REG_READ(ah, AR_RCCNT);
1582 u_int32_t rf = OS_REG_READ(ah, AR_RFCNT);
1583 u_int32_t tf = OS_REG_READ(ah, AR_TFCNT);
1584 u_int32_t cc = OS_REG_READ(ah, AR_CCCNT); /* read cycles last */
1585
1586 if (ahp->ah_cycles == 0 || ahp->ah_cycles > cc) {
1587 /*
1588 * Cycle counter wrap (or initial call); it's not possible
1589 * to accurately calculate a value because the registers
1590 * right shift rather than wrap--so punt and return 0.
1591 */
1592 HALDEBUG(ah, HAL_DEBUG_CHANNEL,
1593 "%s: cycle counter wrap. ExtBusy = 0\n", __func__);
1594 good = 0;
1595 } else {
1596 u_int32_t cc_d = cc - ahp->ah_cycles;
1597 u_int32_t rc_d = rc - ahp->ah_rx_clear;
1598 u_int32_t rf_d = rf - ahp->ah_rx_frame;
1599 u_int32_t tf_d = tf - ahp->ah_tx_frame;
1600
1601 if (cc_d != 0) {
1602 *rxc_pcnt = rc_d * 100 / cc_d;
1603 *rxf_pcnt = rf_d * 100 / cc_d;
1604 *txf_pcnt = tf_d * 100 / cc_d;
1605 } else {
1606 good = 0;
1607 }
1608 }
1609
1610 ahp->ah_cycles = cc;
1611 ahp->ah_rx_frame = rf;
1612 ahp->ah_rx_clear = rc;
1613 ahp->ah_tx_frame = tf;
1614
1615 return good;
1616 }
1617
1618 /*
1619 * Return approximation of extension channel busy over an time interval
1620 * 0% (clear) -> 100% (busy)
1621 * -1 for invalid estimate
1622 */
1623 uint32_t
ar9300_get_11n_ext_busy(struct ath_hal * ah)1624 ar9300_get_11n_ext_busy(struct ath_hal *ah)
1625 {
1626 /*
1627 * Overflow condition to check before multiplying to get %
1628 * (x * 100 > 0xFFFFFFFF ) => (x > 0x28F5C28)
1629 */
1630 #define OVERFLOW_LIMIT 0x28F5C28
1631 #define ERROR_CODE -1
1632
1633 struct ath_hal_9300 *ahp = AH9300(ah);
1634 u_int32_t busy = 0; /* percentage */
1635 int8_t busyper = 0;
1636 u_int32_t cycle_count, ctl_busy, ext_busy;
1637
1638 /* cycle_count will always be the first to wrap; therefore, read it last
1639 * This sequence of reads is not atomic, and MIB counter wrap
1640 * could happen during it ?
1641 */
1642 ctl_busy = OS_REG_READ(ah, AR_RCCNT);
1643 ext_busy = OS_REG_READ(ah, AR_EXTRCCNT);
1644 cycle_count = OS_REG_READ(ah, AR_CCCNT);
1645
1646 if ((ahp->ah_cycle_count == 0) || (ahp->ah_cycle_count > cycle_count) ||
1647 (ahp->ah_ctl_busy > ctl_busy) || (ahp->ah_ext_busy > ext_busy))
1648 {
1649 /*
1650 * Cycle counter wrap (or initial call); it's not possible
1651 * to accurately calculate a value because the registers
1652 * right shift rather than wrap--so punt and return 0.
1653 */
1654 busyper = ERROR_CODE;
1655 HALDEBUG(ah, HAL_DEBUG_CHANNEL,
1656 "%s: cycle counter wrap. ExtBusy = 0\n", __func__);
1657 } else {
1658 u_int32_t cycle_delta = cycle_count - ahp->ah_cycle_count;
1659 u_int32_t ext_busy_delta = ext_busy - ahp->ah_ext_busy;
1660
1661 /*
1662 * Compute extension channel busy percentage
1663 * Overflow condition: 0xFFFFFFFF < ext_busy_delta * 100
1664 * Underflow condition/Divide-by-zero: check that cycle_delta >> 7 != 0
1665 * Will never happen, since (ext_busy_delta < cycle_delta) always,
1666 * and shift necessitated by large ext_busy_delta.
1667 * Due to timing difference to read the registers and counter overflow,
1668 * it may still happen that cycle_delta >> 7 = 0.
1669 *
1670 */
1671 if (cycle_delta) {
1672 if (ext_busy_delta > OVERFLOW_LIMIT) {
1673 if (cycle_delta >> 7) {
1674 busy = ((ext_busy_delta >> 7) * 100) / (cycle_delta >> 7);
1675 } else {
1676 busyper = ERROR_CODE;
1677 }
1678 } else {
1679 busy = (ext_busy_delta * 100) / cycle_delta;
1680 }
1681 } else {
1682 busyper = ERROR_CODE;
1683 }
1684
1685 if (busy > 100) {
1686 busy = 100;
1687 }
1688 if ( busyper != ERROR_CODE ) {
1689 busyper = busy;
1690 }
1691 }
1692
1693 ahp->ah_cycle_count = cycle_count;
1694 ahp->ah_ctl_busy = ctl_busy;
1695 ahp->ah_ext_busy = ext_busy;
1696
1697 return busyper;
1698 #undef OVERFLOW_LIMIT
1699 #undef ERROR_CODE
1700 }
1701
1702 /* BB Panic Watchdog declarations */
1703 #define HAL_BB_PANIC_WD_HT20_FACTOR 74 /* 0.74 */
1704 #define HAL_BB_PANIC_WD_HT40_FACTOR 37 /* 0.37 */
1705
1706 void
ar9300_config_bb_panic_watchdog(struct ath_hal * ah)1707 ar9300_config_bb_panic_watchdog(struct ath_hal *ah)
1708 {
1709 #define HAL_BB_PANIC_IDLE_TIME_OUT 0x0a8c0000
1710 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
1711 u_int32_t idle_tmo_ms = AH9300(ah)->ah_bb_panic_timeout_ms;
1712 u_int32_t val, idle_count;
1713
1714 if (idle_tmo_ms != 0) {
1715 /* enable IRQ, disable chip-reset for BB panic */
1716 val = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2) &
1717 AR_PHY_BB_PANIC_CNTL2_MASK;
1718 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_2,
1719 (val | AR_PHY_BB_PANIC_IRQ_ENABLE) & ~AR_PHY_BB_PANIC_RST_ENABLE);
1720 /* bound limit to 10 secs */
1721 if (idle_tmo_ms > 10000) {
1722 idle_tmo_ms = 10000;
1723 }
1724 if (chan != AH_NULL && IEEE80211_IS_CHAN_HT40(chan)) {
1725 idle_count = (100 * idle_tmo_ms) / HAL_BB_PANIC_WD_HT40_FACTOR;
1726 } else {
1727 idle_count = (100 * idle_tmo_ms) / HAL_BB_PANIC_WD_HT20_FACTOR;
1728 }
1729 /*
1730 * enable panic in non-IDLE mode,
1731 * disable in IDLE mode,
1732 * set idle time-out
1733 */
1734
1735 // EV92527 : Enable IDLE mode panic
1736
1737 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_1,
1738 AR_PHY_BB_PANIC_NON_IDLE_ENABLE |
1739 AR_PHY_BB_PANIC_IDLE_ENABLE |
1740 (AR_PHY_BB_PANIC_IDLE_MASK & HAL_BB_PANIC_IDLE_TIME_OUT) |
1741 (AR_PHY_BB_PANIC_NON_IDLE_MASK & (idle_count << 2)));
1742 } else {
1743 /* disable IRQ, disable chip-reset for BB panic */
1744 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_2,
1745 OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2) &
1746 ~(AR_PHY_BB_PANIC_RST_ENABLE | AR_PHY_BB_PANIC_IRQ_ENABLE));
1747 /* disable panic in non-IDLE mode, disable in IDLE mode */
1748 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_1,
1749 OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_1) &
1750 ~(AR_PHY_BB_PANIC_NON_IDLE_ENABLE | AR_PHY_BB_PANIC_IDLE_ENABLE));
1751 }
1752
1753 HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: %s BB Panic Watchdog tmo=%ums\n",
1754 __func__, idle_tmo_ms ? "Enabled" : "Disabled", idle_tmo_ms);
1755 #undef HAL_BB_PANIC_IDLE_TIME_OUT
1756 }
1757
1758
1759 void
ar9300_handle_bb_panic(struct ath_hal * ah)1760 ar9300_handle_bb_panic(struct ath_hal *ah)
1761 {
1762 u_int32_t status;
1763 /*
1764 * we want to avoid printing in ISR context so we save
1765 * panic watchdog status to be printed later in DPC context
1766 */
1767 AH9300(ah)->ah_bb_panic_last_status = status =
1768 OS_REG_READ(ah, AR_PHY_PANIC_WD_STATUS);
1769 /*
1770 * panic watchdog timer should reset on status read
1771 * but to make sure we write 0 to the watchdog status bit
1772 */
1773 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_STATUS, status & ~AR_PHY_BB_WD_STATUS_CLR);
1774 }
1775
1776 int
ar9300_get_bb_panic_info(struct ath_hal * ah,struct hal_bb_panic_info * bb_panic)1777 ar9300_get_bb_panic_info(struct ath_hal *ah, struct hal_bb_panic_info *bb_panic)
1778 {
1779 bb_panic->status = AH9300(ah)->ah_bb_panic_last_status;
1780
1781 /*
1782 * For signature 04000539 do not print anything.
1783 * This is a very common occurence as a compromise between
1784 * BB Panic and AH_FALSE detects (EV71009). It indicates
1785 * radar hang, which can be cleared by reprogramming
1786 * radar related register and does not requre a chip reset
1787 */
1788
1789 /* Suppress BB Status mesg following signature */
1790 switch (bb_panic->status) {
1791 case 0x04000539:
1792 case 0x04008009:
1793 case 0x04000b09:
1794 case 0x1300000a:
1795 return -1;
1796 }
1797
1798 bb_panic->tsf = ar9300_get_tsf32(ah);
1799 bb_panic->wd = MS(bb_panic->status, AR_PHY_BB_WD_STATUS);
1800 bb_panic->det = MS(bb_panic->status, AR_PHY_BB_WD_DET_HANG);
1801 bb_panic->rdar = MS(bb_panic->status, AR_PHY_BB_WD_RADAR_SM);
1802 bb_panic->r_odfm = MS(bb_panic->status, AR_PHY_BB_WD_RX_OFDM_SM);
1803 bb_panic->r_cck = MS(bb_panic->status, AR_PHY_BB_WD_RX_CCK_SM);
1804 bb_panic->t_odfm = MS(bb_panic->status, AR_PHY_BB_WD_TX_OFDM_SM);
1805 bb_panic->t_cck = MS(bb_panic->status, AR_PHY_BB_WD_TX_CCK_SM);
1806 bb_panic->agc = MS(bb_panic->status, AR_PHY_BB_WD_AGC_SM);
1807 bb_panic->src = MS(bb_panic->status, AR_PHY_BB_WD_SRCH_SM);
1808 bb_panic->phy_panic_wd_ctl1 = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_1);
1809 bb_panic->phy_panic_wd_ctl2 = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2);
1810 bb_panic->phy_gen_ctrl = OS_REG_READ(ah, AR_PHY_GEN_CTRL);
1811 bb_panic->rxc_pcnt = bb_panic->rxf_pcnt = bb_panic->txf_pcnt = 0;
1812 bb_panic->cycles = ar9300_get_mib_cycle_counts_pct(ah,
1813 &bb_panic->rxc_pcnt,
1814 &bb_panic->rxf_pcnt,
1815 &bb_panic->txf_pcnt);
1816
1817 if (ah->ah_config.ath_hal_show_bb_panic) {
1818 ath_hal_printf(ah, "\n==== BB update: BB status=0x%08x, "
1819 "tsf=0x%08x ====\n", bb_panic->status, bb_panic->tsf);
1820 ath_hal_printf(ah, "** BB state: wd=%u det=%u rdar=%u rOFDM=%d "
1821 "rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
1822 bb_panic->wd, bb_panic->det, bb_panic->rdar,
1823 bb_panic->r_odfm, bb_panic->r_cck, bb_panic->t_odfm,
1824 bb_panic->t_cck, bb_panic->agc, bb_panic->src);
1825 ath_hal_printf(ah, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
1826 bb_panic->phy_panic_wd_ctl1, bb_panic->phy_panic_wd_ctl2);
1827 ath_hal_printf(ah, "** BB mode: BB_gen_controls=0x%08x **\n",
1828 bb_panic->phy_gen_ctrl);
1829 if (bb_panic->cycles) {
1830 ath_hal_printf(ah, "** BB busy times: rx_clear=%d%%, "
1831 "rx_frame=%d%%, tx_frame=%d%% **\n", bb_panic->rxc_pcnt,
1832 bb_panic->rxf_pcnt, bb_panic->txf_pcnt);
1833 }
1834 ath_hal_printf(ah, "==== BB update: done ====\n\n");
1835 }
1836
1837 return 0; //The returned data will be stored for athstats to retrieve it
1838 }
1839
1840 /* set the reason for HAL reset */
1841 void
ar9300_set_hal_reset_reason(struct ath_hal * ah,u_int8_t resetreason)1842 ar9300_set_hal_reset_reason(struct ath_hal *ah, u_int8_t resetreason)
1843 {
1844 AH9300(ah)->ah_reset_reason = resetreason;
1845 }
1846
1847 /*
1848 * Configure 20/40 operation
1849 *
1850 * 20/40 = joint rx clear (control and extension)
1851 * 20 = rx clear (control)
1852 *
1853 * - NOTE: must stop MAC (tx) and requeue 40 MHz packets as 20 MHz
1854 * when changing from 20/40 => 20 only
1855 */
1856 void
ar9300_set_11n_mac2040(struct ath_hal * ah,HAL_HT_MACMODE mode)1857 ar9300_set_11n_mac2040(struct ath_hal *ah, HAL_HT_MACMODE mode)
1858 {
1859 u_int32_t macmode;
1860
1861 /* Configure MAC for 20/40 operation */
1862 if (mode == HAL_HT_MACMODE_2040 &&
1863 !ah->ah_config.ath_hal_cwm_ignore_ext_cca) {
1864 macmode = AR_2040_JOINED_RX_CLEAR;
1865 } else {
1866 macmode = 0;
1867 }
1868 OS_REG_WRITE(ah, AR_2040_MODE, macmode);
1869 }
1870
1871 /*
1872 * Get Rx clear (control/extension channel)
1873 *
1874 * Returns active low (busy) for ctrl/ext channel
1875 * Owl 2.0
1876 */
1877 HAL_HT_RXCLEAR
ar9300_get_11n_rx_clear(struct ath_hal * ah)1878 ar9300_get_11n_rx_clear(struct ath_hal *ah)
1879 {
1880 HAL_HT_RXCLEAR rxclear = 0;
1881 u_int32_t val;
1882
1883 val = OS_REG_READ(ah, AR_DIAG_SW);
1884
1885 /* control channel */
1886 if (val & AR_DIAG_RX_CLEAR_CTL_LOW) {
1887 rxclear |= HAL_RX_CLEAR_CTL_LOW;
1888 }
1889 /* extension channel */
1890 if (val & AR_DIAG_RX_CLEAR_EXT_LOW) {
1891 rxclear |= HAL_RX_CLEAR_EXT_LOW;
1892 }
1893 return rxclear;
1894 }
1895
1896 /*
1897 * Set Rx clear (control/extension channel)
1898 *
1899 * Useful for forcing the channel to appear busy for
1900 * debugging/diagnostics
1901 * Owl 2.0
1902 */
1903 void
ar9300_set_11n_rx_clear(struct ath_hal * ah,HAL_HT_RXCLEAR rxclear)1904 ar9300_set_11n_rx_clear(struct ath_hal *ah, HAL_HT_RXCLEAR rxclear)
1905 {
1906 /* control channel */
1907 if (rxclear & HAL_RX_CLEAR_CTL_LOW) {
1908 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_CTL_LOW);
1909 } else {
1910 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_CTL_LOW);
1911 }
1912 /* extension channel */
1913 if (rxclear & HAL_RX_CLEAR_EXT_LOW) {
1914 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_EXT_LOW);
1915 } else {
1916 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_EXT_LOW);
1917 }
1918 }
1919
1920
1921 /*
1922 * HAL support code for force ppm tracking workaround.
1923 */
1924
1925 u_int32_t
ar9300_ppm_get_rssi_dump(struct ath_hal * ah)1926 ar9300_ppm_get_rssi_dump(struct ath_hal *ah)
1927 {
1928 u_int32_t retval;
1929 u_int32_t off1;
1930 u_int32_t off2;
1931
1932 if (OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) & AR_PHY_SWAP_ALT_CHAIN) {
1933 off1 = 0x2000;
1934 off2 = 0x1000;
1935 } else {
1936 off1 = 0x1000;
1937 off2 = 0x2000;
1938 }
1939
1940 retval = ((0xff & OS_REG_READ(ah, AR_PHY_CHAN_INFO_GAIN_0 )) << 0) |
1941 ((0xff & OS_REG_READ(ah, AR_PHY_CHAN_INFO_GAIN_0 + off1)) << 8) |
1942 ((0xff & OS_REG_READ(ah, AR_PHY_CHAN_INFO_GAIN_0 + off2)) << 16);
1943
1944 return retval;
1945 }
1946
1947 u_int32_t
ar9300_ppm_force(struct ath_hal * ah)1948 ar9300_ppm_force(struct ath_hal *ah)
1949 {
1950 u_int32_t data_fine;
1951 u_int32_t data4;
1952 //u_int32_t off1;
1953 //u_int32_t off2;
1954 HAL_BOOL signed_val = AH_FALSE;
1955
1956 // if (OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) & AR_PHY_SWAP_ALT_CHAIN) {
1957 // off1 = 0x2000;
1958 // off2 = 0x1000;
1959 // } else {
1960 // off1 = 0x1000;
1961 // off2 = 0x2000;
1962 // }
1963 data_fine =
1964 AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK &
1965 OS_REG_READ(ah, AR_PHY_CHNINFO_GAINDIFF);
1966
1967 /*
1968 * bit [11-0] is new ppm value. bit 11 is the signed bit.
1969 * So check value from bit[10:0].
1970 * Now get the abs val of the ppm value read in bit[0:11].
1971 * After that do bound check on abs value.
1972 * if value is off limit, CAP the value and and restore signed bit.
1973 */
1974 if (data_fine & AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_SIGNED_BIT)
1975 {
1976 /* get the positive value */
1977 data_fine = (~data_fine + 1) & AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK;
1978 signed_val = AH_TRUE;
1979 }
1980 if (data_fine > AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT)
1981 {
1982 HALDEBUG(ah, HAL_DEBUG_REGIO,
1983 "%s Correcting ppm out of range %x\n",
1984 __func__, (data_fine & 0x7ff));
1985 data_fine = AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT;
1986 }
1987 /*
1988 * Restore signed value if changed above.
1989 * Use typecast to avoid compilation errors
1990 */
1991 if (signed_val) {
1992 data_fine = (-(int32_t)data_fine) &
1993 AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK;
1994 }
1995
1996 /* write value */
1997 data4 = OS_REG_READ(ah, AR_PHY_TIMING2) &
1998 ~(AR_PHY_TIMING2_USE_FORCE_PPM | AR_PHY_TIMING2_FORCE_PPM_VAL);
1999 OS_REG_WRITE(ah, AR_PHY_TIMING2,
2000 data4 | data_fine | AR_PHY_TIMING2_USE_FORCE_PPM);
2001
2002 return data_fine;
2003 }
2004
2005 void
ar9300_ppm_un_force(struct ath_hal * ah)2006 ar9300_ppm_un_force(struct ath_hal *ah)
2007 {
2008 u_int32_t data4;
2009
2010 data4 = OS_REG_READ(ah, AR_PHY_TIMING2) & ~AR_PHY_TIMING2_USE_FORCE_PPM;
2011 OS_REG_WRITE(ah, AR_PHY_TIMING2, data4);
2012 }
2013
2014 u_int32_t
ar9300_ppm_arm_trigger(struct ath_hal * ah)2015 ar9300_ppm_arm_trigger(struct ath_hal *ah)
2016 {
2017 u_int32_t val;
2018 u_int32_t ret;
2019
2020 val = OS_REG_READ(ah, AR_PHY_CHAN_INFO_MEMORY);
2021 ret = OS_REG_READ(ah, AR_TSF_L32);
2022 OS_REG_WRITE(ah, AR_PHY_CHAN_INFO_MEMORY,
2023 val | AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK);
2024
2025 /* return low word of TSF at arm time */
2026 return ret;
2027 }
2028
2029 int
ar9300_ppm_get_trigger(struct ath_hal * ah)2030 ar9300_ppm_get_trigger(struct ath_hal *ah)
2031 {
2032 if (OS_REG_READ(ah, AR_PHY_CHAN_INFO_MEMORY) &
2033 AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK)
2034 {
2035 /* has not triggered yet, return AH_FALSE */
2036 return 0;
2037 }
2038
2039 /* else triggered, return AH_TRUE */
2040 return 1;
2041 }
2042
2043 void
ar9300_mark_phy_inactive(struct ath_hal * ah)2044 ar9300_mark_phy_inactive(struct ath_hal *ah)
2045 {
2046 OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
2047 }
2048
2049 /* DEBUG */
2050 u_int32_t
ar9300_ppm_get_force_state(struct ath_hal * ah)2051 ar9300_ppm_get_force_state(struct ath_hal *ah)
2052 {
2053 return
2054 OS_REG_READ(ah, AR_PHY_TIMING2) &
2055 (AR_PHY_TIMING2_USE_FORCE_PPM | AR_PHY_TIMING2_FORCE_PPM_VAL);
2056 }
2057
2058 /*
2059 * Return the Cycle counts for rx_frame, rx_clear, and tx_frame
2060 */
2061 HAL_BOOL
ar9300_get_mib_cycle_counts(struct ath_hal * ah,HAL_SURVEY_SAMPLE * hs)2062 ar9300_get_mib_cycle_counts(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hs)
2063 {
2064 /*
2065 * XXX FreeBSD todo: reimplement this
2066 */
2067 #if 0
2068 p_cnts->tx_frame_count = OS_REG_READ(ah, AR_TFCNT);
2069 p_cnts->rx_frame_count = OS_REG_READ(ah, AR_RFCNT);
2070 p_cnts->rx_clear_count = OS_REG_READ(ah, AR_RCCNT);
2071 p_cnts->cycle_count = OS_REG_READ(ah, AR_CCCNT);
2072 p_cnts->is_tx_active = (OS_REG_READ(ah, AR_TFCNT) ==
2073 p_cnts->tx_frame_count) ? AH_FALSE : AH_TRUE;
2074 p_cnts->is_rx_active = (OS_REG_READ(ah, AR_RFCNT) ==
2075 p_cnts->rx_frame_count) ? AH_FALSE : AH_TRUE;
2076 #endif
2077 return AH_FALSE;
2078 }
2079
2080 void
ar9300_clear_mib_counters(struct ath_hal * ah)2081 ar9300_clear_mib_counters(struct ath_hal *ah)
2082 {
2083 u_int32_t reg_val;
2084
2085 reg_val = OS_REG_READ(ah, AR_MIBC);
2086 OS_REG_WRITE(ah, AR_MIBC, reg_val | AR_MIBC_CMC);
2087 OS_REG_WRITE(ah, AR_MIBC, reg_val & ~AR_MIBC_CMC);
2088 }
2089
2090
2091 /* Enable or Disable RIFS Rx capability as part of SW WAR for Bug 31602 */
2092 HAL_BOOL
ar9300_set_rifs_delay(struct ath_hal * ah,HAL_BOOL enable)2093 ar9300_set_rifs_delay(struct ath_hal *ah, HAL_BOOL enable)
2094 {
2095 struct ath_hal_9300 *ahp = AH9300(ah);
2096 HAL_CHANNEL_INTERNAL *ichan =
2097 ath_hal_checkchannel(ah, AH_PRIVATE(ah)->ah_curchan);
2098 HAL_BOOL is_chan_2g = IS_CHAN_2GHZ(ichan);
2099 u_int32_t tmp = 0;
2100
2101 if (enable) {
2102 if (ahp->ah_rifs_enabled == AH_TRUE) {
2103 return AH_TRUE;
2104 }
2105
2106 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, ahp->ah_rifs_reg[0]);
2107 OS_REG_WRITE(ah, AR_PHY_RIFS_SRCH,
2108 ahp->ah_rifs_reg[1]);
2109
2110 ahp->ah_rifs_enabled = AH_TRUE;
2111 OS_MEMZERO(ahp->ah_rifs_reg, sizeof(ahp->ah_rifs_reg));
2112 } else {
2113 if (ahp->ah_rifs_enabled == AH_TRUE) {
2114 ahp->ah_rifs_reg[0] = OS_REG_READ(ah,
2115 AR_PHY_SEARCH_START_DELAY);
2116 ahp->ah_rifs_reg[1] = OS_REG_READ(ah, AR_PHY_RIFS_SRCH);
2117 }
2118 /* Change rifs init delay to 0 */
2119 OS_REG_WRITE(ah, AR_PHY_RIFS_SRCH,
2120 (ahp->ah_rifs_reg[1] & ~(AR_PHY_RIFS_INIT_DELAY)));
2121 tmp = 0xfffff000 & OS_REG_READ(ah, AR_PHY_SEARCH_START_DELAY);
2122 if (is_chan_2g) {
2123 if (IEEE80211_IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) {
2124 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 500);
2125 } else { /* Sowl 2G HT-20 default is 0x134 for search start delay */
2126 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 250);
2127 }
2128 } else {
2129 if (IEEE80211_IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) {
2130 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 0x370);
2131 } else { /* Sowl 5G HT-20 default is 0x1b8 for search start delay */
2132 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 0x1b8);
2133 }
2134 }
2135
2136 ahp->ah_rifs_enabled = AH_FALSE;
2137 }
2138 return AH_TRUE;
2139
2140 } /* ar9300_set_rifs_delay () */
2141
2142 /* Set the current RIFS Rx setting */
2143 HAL_BOOL
ar9300_set_11n_rx_rifs(struct ath_hal * ah,HAL_BOOL enable)2144 ar9300_set_11n_rx_rifs(struct ath_hal *ah, HAL_BOOL enable)
2145 {
2146 /* Non-Owl 11n chips */
2147 if ((ath_hal_getcapability(ah, HAL_CAP_RIFS_RX, 0, AH_NULL) == HAL_OK)) {
2148 if (ar9300_get_capability(ah, HAL_CAP_LDPCWAR, 0, AH_NULL) == HAL_OK) {
2149 return ar9300_set_rifs_delay(ah, enable);
2150 }
2151 return AH_FALSE;
2152 }
2153
2154 return AH_TRUE;
2155 } /* ar9300_set_11n_rx_rifs () */
2156
2157 static hal_mac_hangs_t
ar9300_compare_dbg_hang(struct ath_hal * ah,mac_dbg_regs_t mac_dbg,hal_mac_hang_check_t hang_check,hal_mac_hangs_t hangs,u_int8_t * dcu_chain)2158 ar9300_compare_dbg_hang(struct ath_hal *ah, mac_dbg_regs_t mac_dbg,
2159 hal_mac_hang_check_t hang_check, hal_mac_hangs_t hangs, u_int8_t *dcu_chain)
2160 {
2161 int i = 0;
2162 hal_mac_hangs_t found_hangs = 0;
2163
2164 if (hangs & dcu_chain_state) {
2165 for (i = 0; i < 6; i++) {
2166 if (((mac_dbg.dma_dbg_4 >> (5 * i)) & 0x1f) ==
2167 hang_check.dcu_chain_state)
2168 {
2169 found_hangs |= dcu_chain_state;
2170 *dcu_chain = i;
2171 }
2172 }
2173 for (i = 0; i < 4; i++) {
2174 if (((mac_dbg.dma_dbg_5 >> (5 * i)) & 0x1f) ==
2175 hang_check.dcu_chain_state)
2176 {
2177 found_hangs |= dcu_chain_state;
2178 *dcu_chain = i + 6;
2179 }
2180 }
2181 }
2182
2183 if (hangs & dcu_complete_state) {
2184 if ((mac_dbg.dma_dbg_6 & 0x3) == hang_check.dcu_complete_state) {
2185 found_hangs |= dcu_complete_state;
2186 }
2187 }
2188
2189 return found_hangs;
2190
2191 } /* end - ar9300_compare_dbg_hang */
2192
2193 #define NUM_STATUS_READS 50
2194 HAL_BOOL
ar9300_detect_mac_hang(struct ath_hal * ah)2195 ar9300_detect_mac_hang(struct ath_hal *ah)
2196 {
2197 struct ath_hal_9300 *ahp = AH9300(ah);
2198 mac_dbg_regs_t mac_dbg;
2199 hal_mac_hang_check_t hang_sig1_val = {0x6, 0x1, 0, 0, 0, 0, 0, 0};
2200 hal_mac_hangs_t hang_sig1 = (dcu_chain_state | dcu_complete_state);
2201 int i = 0;
2202 u_int8_t dcu_chain = 0, current_dcu_chain_state, shift_val;
2203
2204 if (!(ahp->ah_hang_wars & HAL_MAC_HANG_WAR)) {
2205 return AH_FALSE;
2206 }
2207
2208 OS_MEMZERO(&mac_dbg, sizeof(mac_dbg));
2209
2210 mac_dbg.dma_dbg_4 = OS_REG_READ(ah, AR_DMADBG_4);
2211 mac_dbg.dma_dbg_5 = OS_REG_READ(ah, AR_DMADBG_5);
2212 mac_dbg.dma_dbg_6 = OS_REG_READ(ah, AR_DMADBG_6);
2213
2214 HALDEBUG(ah, HAL_DEBUG_DFS, " dma regs: %X %X %X \n",
2215 mac_dbg.dma_dbg_4, mac_dbg.dma_dbg_5,
2216 mac_dbg.dma_dbg_6);
2217
2218 if (hang_sig1 !=
2219 ar9300_compare_dbg_hang(ah, mac_dbg,
2220 hang_sig1_val, hang_sig1, &dcu_chain))
2221 {
2222 HALDEBUG(ah, HAL_DEBUG_DFS, " hang sig1 not found \n");
2223 return AH_FALSE;
2224 }
2225
2226 shift_val = (dcu_chain >= 6) ? (dcu_chain-6) : (dcu_chain);
2227 shift_val *= 5;
2228
2229 for (i = 1; i <= NUM_STATUS_READS; i++) {
2230 if (dcu_chain < 6) {
2231 mac_dbg.dma_dbg_4 = OS_REG_READ(ah, AR_DMADBG_4);
2232 current_dcu_chain_state =
2233 ((mac_dbg.dma_dbg_4 >> shift_val) & 0x1f);
2234 } else {
2235 mac_dbg.dma_dbg_5 = OS_REG_READ(ah, AR_DMADBG_5);
2236 current_dcu_chain_state = ((mac_dbg.dma_dbg_5 >> shift_val) & 0x1f);
2237 }
2238 mac_dbg.dma_dbg_6 = OS_REG_READ(ah, AR_DMADBG_6);
2239
2240 if (((mac_dbg.dma_dbg_6 & 0x3) != hang_sig1_val.dcu_complete_state)
2241 || (current_dcu_chain_state != hang_sig1_val.dcu_chain_state)) {
2242 return AH_FALSE;
2243 }
2244 }
2245 HALDEBUG(ah, HAL_DEBUG_DFS, "%s sig5count=%d sig6count=%d ", __func__,
2246 ahp->ah_hang[MAC_HANG_SIG1], ahp->ah_hang[MAC_HANG_SIG2]);
2247 ahp->ah_hang[MAC_HANG_SIG1]++;
2248 return AH_TRUE;
2249
2250 } /* end - ar9300_detect_mac_hang */
2251
2252 /* Determine if the baseband is hung by reading the Observation Bus Register */
2253 HAL_BOOL
ar9300_detect_bb_hang(struct ath_hal * ah)2254 ar9300_detect_bb_hang(struct ath_hal *ah)
2255 {
2256 #define N(a) (sizeof(a) / sizeof(a[0]))
2257 struct ath_hal_9300 *ahp = AH9300(ah);
2258 u_int32_t hang_sig = 0;
2259 int i = 0;
2260 /* Check the PCU Observation Bus 1 register (0x806c) NUM_STATUS_READS times
2261 *
2262 * 4 known BB hang signatures -
2263 * [1] bits 8,9,11 are 0. State machine state (bits 25-31) is 0x1E
2264 * [2] bits 8,9 are 1, bit 11 is 0. State machine state (bits 25-31) is 0x52
2265 * [3] bits 8,9 are 1, bit 11 is 0. State machine state (bits 25-31) is 0x18
2266 * [4] bit 10 is 1, bit 11 is 0. WEP state (bits 12-17) is 0x2,
2267 * Rx State (bits 20-24) is 0x7.
2268 */
2269 hal_hw_hang_check_t hang_list [] =
2270 {
2271 /* Offset Reg Value Reg Mask Hang Offset */
2272 {AR_OBS_BUS_1, 0x1E000000, 0x7E000B00, BB_HANG_SIG1},
2273 {AR_OBS_BUS_1, 0x52000B00, 0x7E000B00, BB_HANG_SIG2},
2274 {AR_OBS_BUS_1, 0x18000B00, 0x7E000B00, BB_HANG_SIG3},
2275 {AR_OBS_BUS_1, 0x00702400, 0x7E7FFFEF, BB_HANG_SIG4}
2276 };
2277
2278 if (!(ahp->ah_hang_wars & (HAL_RIFS_BB_HANG_WAR |
2279 HAL_DFS_BB_HANG_WAR |
2280 HAL_RX_STUCK_LOW_BB_HANG_WAR))) {
2281 return AH_FALSE;
2282 }
2283
2284 hang_sig = OS_REG_READ(ah, AR_OBS_BUS_1);
2285 for (i = 1; i <= NUM_STATUS_READS; i++) {
2286 if (hang_sig != OS_REG_READ(ah, AR_OBS_BUS_1)) {
2287 return AH_FALSE;
2288 }
2289 }
2290
2291 for (i = 0; i < N(hang_list); i++) {
2292 if ((hang_sig & hang_list[i].hang_mask) == hang_list[i].hang_val) {
2293 ahp->ah_hang[hang_list[i].hang_offset]++;
2294 HALDEBUG(ah, HAL_DEBUG_DFS, "%s sig1count=%d sig2count=%d "
2295 "sig3count=%d sig4count=%d\n", __func__,
2296 ahp->ah_hang[BB_HANG_SIG1], ahp->ah_hang[BB_HANG_SIG2],
2297 ahp->ah_hang[BB_HANG_SIG3], ahp->ah_hang[BB_HANG_SIG4]);
2298 return AH_TRUE;
2299 }
2300 }
2301
2302 HALDEBUG(ah, HAL_DEBUG_DFS, "%s Found an unknown BB hang signature! "
2303 "<0x806c>=0x%x\n", __func__, hang_sig);
2304
2305 return AH_FALSE;
2306
2307 #undef N
2308 } /* end - ar9300_detect_bb_hang () */
2309
2310 #undef NUM_STATUS_READS
2311
2312 HAL_STATUS
ar9300_select_ant_config(struct ath_hal * ah,u_int32_t cfg)2313 ar9300_select_ant_config(struct ath_hal *ah, u_int32_t cfg)
2314 {
2315 struct ath_hal_9300 *ahp = AH9300(ah);
2316 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
2317 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
2318 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
2319 u_int16_t ant_config;
2320 u_int32_t hal_num_ant_config;
2321
2322 hal_num_ant_config = IS_CHAN_2GHZ(ichan) ?
2323 p_cap->halNumAntCfg2GHz: p_cap->halNumAntCfg5GHz;
2324
2325 if (cfg < hal_num_ant_config) {
2326 if (HAL_OK == ar9300_eeprom_get_ant_cfg(ahp, chan, cfg, &ant_config)) {
2327 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
2328 return HAL_OK;
2329 }
2330 }
2331
2332 return HAL_EINVAL;
2333 }
2334
2335 /*
2336 * Functions to get/set DCS mode
2337 */
2338 void
ar9300_set_dcs_mode(struct ath_hal * ah,u_int32_t mode)2339 ar9300_set_dcs_mode(struct ath_hal *ah, u_int32_t mode)
2340 {
2341 AH9300(ah)->ah_dcs_enable = mode;
2342 }
2343
2344 u_int32_t
ar9300_get_dcs_mode(struct ath_hal * ah)2345 ar9300_get_dcs_mode(struct ath_hal *ah)
2346 {
2347 return AH9300(ah)->ah_dcs_enable;
2348 }
2349
2350 #if ATH_BT_COEX
2351 void
ar9300_set_bt_coex_info(struct ath_hal * ah,HAL_BT_COEX_INFO * btinfo)2352 ar9300_set_bt_coex_info(struct ath_hal *ah, HAL_BT_COEX_INFO *btinfo)
2353 {
2354 struct ath_hal_9300 *ahp = AH9300(ah);
2355
2356 ahp->ah_bt_module = btinfo->bt_module;
2357 ahp->ah_bt_coex_config_type = btinfo->bt_coex_config;
2358 ahp->ah_bt_active_gpio_select = btinfo->bt_gpio_bt_active;
2359 ahp->ah_bt_priority_gpio_select = btinfo->bt_gpio_bt_priority;
2360 ahp->ah_wlan_active_gpio_select = btinfo->bt_gpio_wlan_active;
2361 ahp->ah_bt_active_polarity = btinfo->bt_active_polarity;
2362 ahp->ah_bt_coex_single_ant = btinfo->bt_single_ant;
2363 ahp->ah_bt_wlan_isolation = btinfo->bt_isolation;
2364 }
2365
2366 void
ar9300_bt_coex_config(struct ath_hal * ah,HAL_BT_COEX_CONFIG * btconf)2367 ar9300_bt_coex_config(struct ath_hal *ah, HAL_BT_COEX_CONFIG *btconf)
2368 {
2369 struct ath_hal_9300 *ahp = AH9300(ah);
2370 HAL_BOOL rx_clear_polarity;
2371
2372 /*
2373 * For Kiwi and Osprey, the polarity of rx_clear is active high.
2374 * The bt_rxclear_polarity flag from ath_dev needs to be inverted.
2375 */
2376 rx_clear_polarity = !btconf->bt_rxclear_polarity;
2377
2378 ahp->ah_bt_coex_mode = (ahp->ah_bt_coex_mode & AR_BT_QCU_THRESH) |
2379 SM(btconf->bt_time_extend, AR_BT_TIME_EXTEND) |
2380 SM(btconf->bt_txstate_extend, AR_BT_TXSTATE_EXTEND) |
2381 SM(btconf->bt_txframe_extend, AR_BT_TX_FRAME_EXTEND) |
2382 SM(btconf->bt_mode, AR_BT_MODE) |
2383 SM(btconf->bt_quiet_collision, AR_BT_QUIET) |
2384 SM(rx_clear_polarity, AR_BT_RX_CLEAR_POLARITY) |
2385 SM(btconf->bt_priority_time, AR_BT_PRIORITY_TIME) |
2386 SM(btconf->bt_first_slot_time, AR_BT_FIRST_SLOT_TIME);
2387
2388 ahp->ah_bt_coex_mode2 |= SM(btconf->bt_hold_rxclear, AR_BT_HOLD_RX_CLEAR);
2389
2390 if (ahp->ah_bt_coex_single_ant == AH_FALSE) {
2391 /* Enable ACK to go out even though BT has higher priority. */
2392 ahp->ah_bt_coex_mode2 |= AR_BT_DISABLE_BT_ANT;
2393 }
2394 }
2395
2396 void
ar9300_bt_coex_set_qcu_thresh(struct ath_hal * ah,int qnum)2397 ar9300_bt_coex_set_qcu_thresh(struct ath_hal *ah, int qnum)
2398 {
2399 struct ath_hal_9300 *ahp = AH9300(ah);
2400
2401 /* clear the old value, then set the new value */
2402 ahp->ah_bt_coex_mode &= ~AR_BT_QCU_THRESH;
2403 ahp->ah_bt_coex_mode |= SM(qnum, AR_BT_QCU_THRESH);
2404 }
2405
2406 void
ar9300_bt_coex_set_weights(struct ath_hal * ah,u_int32_t stomp_type)2407 ar9300_bt_coex_set_weights(struct ath_hal *ah, u_int32_t stomp_type)
2408 {
2409 struct ath_hal_9300 *ahp = AH9300(ah);
2410
2411 ahp->ah_bt_coex_bt_weight[0] = AR9300_BT_WGHT;
2412 ahp->ah_bt_coex_bt_weight[1] = AR9300_BT_WGHT;
2413 ahp->ah_bt_coex_bt_weight[2] = AR9300_BT_WGHT;
2414 ahp->ah_bt_coex_bt_weight[3] = AR9300_BT_WGHT;
2415
2416 switch (stomp_type) {
2417 case HAL_BT_COEX_STOMP_ALL:
2418 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_ALL_WLAN_WGHT0;
2419 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_ALL_WLAN_WGHT1;
2420 break;
2421 case HAL_BT_COEX_STOMP_LOW:
2422 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_LOW_WLAN_WGHT0;
2423 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_LOW_WLAN_WGHT1;
2424 break;
2425 case HAL_BT_COEX_STOMP_ALL_FORCE:
2426 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_ALL_FORCE_WLAN_WGHT0;
2427 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_ALL_FORCE_WLAN_WGHT1;
2428 break;
2429 case HAL_BT_COEX_STOMP_LOW_FORCE:
2430 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_LOW_FORCE_WLAN_WGHT0;
2431 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_LOW_FORCE_WLAN_WGHT1;
2432 break;
2433 case HAL_BT_COEX_STOMP_NONE:
2434 case HAL_BT_COEX_NO_STOMP:
2435 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_NONE_WLAN_WGHT0;
2436 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_NONE_WLAN_WGHT1;
2437 break;
2438 default:
2439 /* There is a force_weight from registry */
2440 ahp->ah_bt_coex_wlan_weight[0] = stomp_type;
2441 ahp->ah_bt_coex_wlan_weight[1] = stomp_type;
2442 break;
2443 }
2444 }
2445
2446 void
ar9300_bt_coex_setup_bmiss_thresh(struct ath_hal * ah,u_int32_t thresh)2447 ar9300_bt_coex_setup_bmiss_thresh(struct ath_hal *ah, u_int32_t thresh)
2448 {
2449 struct ath_hal_9300 *ahp = AH9300(ah);
2450
2451 /* clear the old value, then set the new value */
2452 ahp->ah_bt_coex_mode2 &= ~AR_BT_BCN_MISS_THRESH;
2453 ahp->ah_bt_coex_mode2 |= SM(thresh, AR_BT_BCN_MISS_THRESH);
2454 }
2455
2456 static void
ar9300_bt_coex_antenna_diversity(struct ath_hal * ah,u_int32_t value)2457 ar9300_bt_coex_antenna_diversity(struct ath_hal *ah, u_int32_t value)
2458 {
2459 struct ath_hal_9300 *ahp = AH9300(ah);
2460 #if ATH_ANT_DIV_COMB
2461 //struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
2462 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
2463 #endif
2464
2465 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "%s: called, value=%d\n", __func__, value);
2466
2467 if (ahp->ah_bt_coex_flag & HAL_BT_COEX_FLAG_ANT_DIV_ALLOW)
2468 {
2469 if (ahp->ah_diversity_control == HAL_ANT_VARIABLE)
2470 {
2471 /* Config antenna diversity */
2472 #if ATH_ANT_DIV_COMB
2473 ar9300_ant_ctrl_set_lna_div_use_bt_ant(ah, value, chan);
2474 #endif
2475 }
2476 }
2477 }
2478
2479
2480 void
ar9300_bt_coex_set_parameter(struct ath_hal * ah,u_int32_t type,u_int32_t value)2481 ar9300_bt_coex_set_parameter(struct ath_hal *ah, u_int32_t type,
2482 u_int32_t value)
2483 {
2484 struct ath_hal_9300 *ahp = AH9300(ah);
2485 struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
2486
2487 switch (type) {
2488 case HAL_BT_COEX_SET_ACK_PWR:
2489 if (value) {
2490 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_LOW_ACK_PWR;
2491 } else {
2492 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_LOW_ACK_PWR;
2493 }
2494 ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit,
2495 ahpriv->ah_extraTxPow, 0);
2496 break;
2497
2498 case HAL_BT_COEX_ANTENNA_DIVERSITY:
2499 if (AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah)) {
2500 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_ANT_DIV_ALLOW;
2501 if (value) {
2502 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_ANT_DIV_ENABLE;
2503 }
2504 else {
2505 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_ANT_DIV_ENABLE;
2506 }
2507 ar9300_bt_coex_antenna_diversity(ah, value);
2508 }
2509 break;
2510 case HAL_BT_COEX_LOWER_TX_PWR:
2511 if (value) {
2512 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_LOWER_TX_PWR;
2513 }
2514 else {
2515 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_LOWER_TX_PWR;
2516 }
2517 ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit,
2518 ahpriv->ah_extraTxPow, 0);
2519 break;
2520 #if ATH_SUPPORT_MCI
2521 case HAL_BT_COEX_MCI_MAX_TX_PWR:
2522 if ((ah->ah_config.ath_hal_mci_config &
2523 ATH_MCI_CONFIG_CONCUR_TX) == ATH_MCI_CONCUR_TX_SHARED_CHN)
2524 {
2525 if (value) {
2526 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR;
2527 ahp->ah_mci_concur_tx_en = AH_TRUE;
2528 }
2529 else {
2530 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR;
2531 ahp->ah_mci_concur_tx_en = AH_FALSE;
2532 }
2533 ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit,
2534 ahpriv->ah_extraTxPow, 0);
2535 }
2536 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) concur_tx_en = %d\n",
2537 ahp->ah_mci_concur_tx_en);
2538 break;
2539 case HAL_BT_COEX_MCI_FTP_STOMP_RX:
2540 if (value) {
2541 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_MCI_FTP_STOMP_RX;
2542 }
2543 else {
2544 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_MCI_FTP_STOMP_RX;
2545 }
2546 break;
2547 #endif
2548 default:
2549 break;
2550 }
2551 }
2552
2553 void
ar9300_bt_coex_disable(struct ath_hal * ah)2554 ar9300_bt_coex_disable(struct ath_hal *ah)
2555 {
2556 struct ath_hal_9300 *ahp = AH9300(ah);
2557
2558 /* Always drive rx_clear_external output as 0 */
2559 ath_hal_gpioCfgOutput(ah, ahp->ah_wlan_active_gpio_select,
2560 HAL_GPIO_OUTPUT_MUX_AS_OUTPUT);
2561
2562 if (ahp->ah_bt_coex_single_ant == AH_TRUE) {
2563 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
2564 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
2565 }
2566
2567 OS_REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET | AR_BT_MODE);
2568 OS_REG_WRITE(ah, AR_BT_COEX_MODE2, 0);
2569 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, 0);
2570 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, 0);
2571 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS0, 0);
2572 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS1, 0);
2573 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS2, 0);
2574 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS3, 0);
2575
2576 ahp->ah_bt_coex_enabled = AH_FALSE;
2577 }
2578
2579 int
ar9300_bt_coex_enable(struct ath_hal * ah)2580 ar9300_bt_coex_enable(struct ath_hal *ah)
2581 {
2582 struct ath_hal_9300 *ahp = AH9300(ah);
2583
2584 /* Program coex mode and weight registers to actually enable coex */
2585 OS_REG_WRITE(ah, AR_BT_COEX_MODE, ahp->ah_bt_coex_mode);
2586 OS_REG_WRITE(ah, AR_BT_COEX_MODE2, ahp->ah_bt_coex_mode2);
2587 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, ahp->ah_bt_coex_wlan_weight[0]);
2588 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, ahp->ah_bt_coex_wlan_weight[1]);
2589 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS0, ahp->ah_bt_coex_bt_weight[0]);
2590 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS1, ahp->ah_bt_coex_bt_weight[1]);
2591 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS2, ahp->ah_bt_coex_bt_weight[2]);
2592 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS3, ahp->ah_bt_coex_bt_weight[3]);
2593
2594 if (ahp->ah_bt_coex_flag & HAL_BT_COEX_FLAG_LOW_ACK_PWR) {
2595 OS_REG_WRITE(ah, AR_TPC, HAL_BT_COEX_LOW_ACK_POWER);
2596 } else {
2597 OS_REG_WRITE(ah, AR_TPC, HAL_BT_COEX_HIGH_ACK_POWER);
2598 }
2599
2600 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
2601 if (ahp->ah_bt_coex_single_ant == AH_TRUE) {
2602 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 1);
2603 } else {
2604 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
2605 }
2606
2607 if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_3WIRE) {
2608 /* For 3-wire, configure the desired GPIO port for rx_clear */
2609 ath_hal_gpioCfgOutput(ah,
2610 ahp->ah_wlan_active_gpio_select,
2611 HAL_GPIO_OUTPUT_MUX_AS_WLAN_ACTIVE);
2612 }
2613 else if ((ahp->ah_bt_coex_config_type >= HAL_BT_COEX_CFG_2WIRE_2CH) &&
2614 (ahp->ah_bt_coex_config_type <= HAL_BT_COEX_CFG_2WIRE_CH0))
2615 {
2616 /* For 2-wire, configure the desired GPIO port for TX_FRAME output */
2617 ath_hal_gpioCfgOutput(ah,
2618 ahp->ah_wlan_active_gpio_select,
2619 HAL_GPIO_OUTPUT_MUX_AS_TX_FRAME);
2620 }
2621
2622 /*
2623 * Enable a weak pull down on BT_ACTIVE.
2624 * When BT device is disabled, BT_ACTIVE might be floating.
2625 */
2626 OS_REG_RMW(ah, AR_HOSTIF_REG(ah, AR_GPIO_PDPU),
2627 (AR_GPIO_PULL_DOWN << (ahp->ah_bt_active_gpio_select * 2)),
2628 (AR_GPIO_PDPU_OPTION << (ahp->ah_bt_active_gpio_select * 2)));
2629
2630 ahp->ah_bt_coex_enabled = AH_TRUE;
2631
2632 return 0;
2633 }
2634
ar9300_get_bt_active_gpio(struct ath_hal * ah,u_int32_t reg)2635 u_int32_t ar9300_get_bt_active_gpio(struct ath_hal *ah, u_int32_t reg)
2636 {
2637 return 0;
2638 }
2639
ar9300_get_wlan_active_gpio(struct ath_hal * ah,u_int32_t reg,u_int32_t bOn)2640 u_int32_t ar9300_get_wlan_active_gpio(struct ath_hal *ah, u_int32_t reg,u_int32_t bOn)
2641 {
2642 return bOn;
2643 }
2644
2645 void
ar9300_init_bt_coex(struct ath_hal * ah)2646 ar9300_init_bt_coex(struct ath_hal *ah)
2647 {
2648 struct ath_hal_9300 *ahp = AH9300(ah);
2649
2650 if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_3WIRE) {
2651 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL),
2652 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB |
2653 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB));
2654
2655 /*
2656 * Set input mux for bt_prority_async and
2657 * bt_active_async to GPIO pins
2658 */
2659 OS_REG_RMW_FIELD(ah,
2660 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1),
2661 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
2662 ahp->ah_bt_active_gpio_select);
2663 OS_REG_RMW_FIELD(ah,
2664 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1),
2665 AR_GPIO_INPUT_MUX1_BT_PRIORITY,
2666 ahp->ah_bt_priority_gpio_select);
2667
2668 /* Configure the desired GPIO ports for input */
2669 ath_hal_gpioCfgInput(ah, ahp->ah_bt_active_gpio_select);
2670 ath_hal_gpioCfgInput(ah, ahp->ah_bt_priority_gpio_select);
2671
2672 if (ahp->ah_bt_coex_enabled) {
2673 ar9300_bt_coex_enable(ah);
2674 } else {
2675 ar9300_bt_coex_disable(ah);
2676 }
2677 }
2678 else if ((ahp->ah_bt_coex_config_type >= HAL_BT_COEX_CFG_2WIRE_2CH) &&
2679 (ahp->ah_bt_coex_config_type <= HAL_BT_COEX_CFG_2WIRE_CH0))
2680 {
2681 /* 2-wire */
2682 if (ahp->ah_bt_coex_enabled) {
2683 /* Connect bt_active_async to baseband */
2684 OS_REG_CLR_BIT(ah,
2685 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL),
2686 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
2687 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
2688 OS_REG_SET_BIT(ah,
2689 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL),
2690 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
2691
2692 /*
2693 * Set input mux for bt_prority_async and
2694 * bt_active_async to GPIO pins
2695 */
2696 OS_REG_RMW_FIELD(ah,
2697 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1),
2698 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
2699 ahp->ah_bt_active_gpio_select);
2700
2701 /* Configure the desired GPIO ports for input */
2702 ath_hal_gpioCfgInput(ah, ahp->ah_bt_active_gpio_select);
2703
2704 /* Enable coexistence on initialization */
2705 ar9300_bt_coex_enable(ah);
2706 }
2707 }
2708 #if ATH_SUPPORT_MCI
2709 else if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_MCI) {
2710 if (ahp->ah_bt_coex_enabled) {
2711 ar9300_mci_bt_coex_enable(ah);
2712 }
2713 else {
2714 ar9300_mci_bt_coex_disable(ah);
2715 }
2716 }
2717 #endif /* ATH_SUPPORT_MCI */
2718 }
2719
2720 #endif /* ATH_BT_COEX */
2721
ar9300_set_proxy_sta(struct ath_hal * ah,HAL_BOOL enable)2722 HAL_STATUS ar9300_set_proxy_sta(struct ath_hal *ah, HAL_BOOL enable)
2723 {
2724 u_int32_t val;
2725 int wasp_mm_rev;
2726
2727 #define AR_SOC_RST_REVISION_ID 0xB8060090
2728 #define REG_READ(_reg) *((volatile u_int32_t *)(_reg))
2729 wasp_mm_rev = (REG_READ(AR_SOC_RST_REVISION_ID) &
2730 AR_SREV_REVISION_WASP_MINOR_MINOR_MASK) >>
2731 AR_SREV_REVISION_WASP_MINOR_MINOR_SHIFT;
2732 #undef AR_SOC_RST_REVISION_ID
2733 #undef REG_READ
2734
2735 /*
2736 * Azimuth (ProxySTA) Mode is only supported correctly by
2737 * Peacock or WASP 1.3.0.1 or later (hopefully) chips.
2738 *
2739 * Enable this feature for Scorpion at this time. The silicon
2740 * still needs to be validated.
2741 */
2742 if (!(AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_AR9580) &&
2743 !(AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_SCORPION) &&
2744 !((AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_WASP) &&
2745 ((AH_PRIVATE((ah))->ah_macRev > AR_SREV_REVISION_WASP_13) ||
2746 (AH_PRIVATE((ah))->ah_macRev == AR_SREV_REVISION_WASP_13 &&
2747 wasp_mm_rev >= 0 /* 1 */))))
2748 {
2749 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "%s error: current chip (ver 0x%x, "
2750 "rev 0x%x, minor minor rev 0x%x) cannot support Azimuth Mode\n",
2751 __func__, AH_PRIVATE((ah))->ah_macVersion,
2752 AH_PRIVATE((ah))->ah_macRev, wasp_mm_rev);
2753 return HAL_ENOTSUPP;
2754 }
2755
2756 OS_REG_WRITE(ah,
2757 AR_MAC_PCU_LOGIC_ANALYZER, AR_MAC_PCU_LOGIC_ANALYZER_PSTABUG75996);
2758
2759 /* turn on mode bit[24] for proxy sta */
2760 OS_REG_WRITE(ah, AR_PCU_MISC_MODE2,
2761 OS_REG_READ(ah, AR_PCU_MISC_MODE2) | AR_PCU_MISC_MODE2_PROXY_STA);
2762
2763 val = OS_REG_READ(ah, AR_AZIMUTH_MODE);
2764 if (enable) {
2765 val |= AR_AZIMUTH_KEY_SEARCH_AD1 |
2766 AR_AZIMUTH_CTS_MATCH_TX_AD2 |
2767 AR_AZIMUTH_BA_USES_AD1;
2768 /* turn off filter pass hold (bit 9) */
2769 val &= ~AR_AZIMUTH_FILTER_PASS_HOLD;
2770 } else {
2771 val &= ~(AR_AZIMUTH_KEY_SEARCH_AD1 |
2772 AR_AZIMUTH_CTS_MATCH_TX_AD2 |
2773 AR_AZIMUTH_BA_USES_AD1);
2774 }
2775 OS_REG_WRITE(ah, AR_AZIMUTH_MODE, val);
2776
2777 /* enable promiscous mode */
2778 OS_REG_WRITE(ah, AR_RX_FILTER,
2779 OS_REG_READ(ah, AR_RX_FILTER) | HAL_RX_FILTER_PROM);
2780 /* enable promiscous in azimuth mode */
2781 OS_REG_WRITE(ah, AR_PCU_MISC_MODE2, AR_PCU_MISC_MODE2_PROM_VC_MODE);
2782 OS_REG_WRITE(ah, AR_MAC_PCU_LOGIC_ANALYZER, AR_MAC_PCU_LOGIC_ANALYZER_VC_MODE);
2783
2784 /* turn on filter pass hold (bit 9) */
2785 OS_REG_WRITE(ah, AR_AZIMUTH_MODE,
2786 OS_REG_READ(ah, AR_AZIMUTH_MODE) | AR_AZIMUTH_FILTER_PASS_HOLD);
2787
2788 return HAL_OK;
2789 }
2790
2791 #if 0
2792 void ar9300_mat_enable(struct ath_hal *ah, int enable)
2793 {
2794 /*
2795 * MAT (s/w ProxySTA) implementation requires to turn off interrupt
2796 * mitigation and turn on key search always for better performance.
2797 */
2798 struct ath_hal_9300 *ahp = AH9300(ah);
2799 struct ath_hal_private *ap = AH_PRIVATE(ah);
2800
2801 ahp->ah_intr_mitigation_rx = !enable;
2802 if (ahp->ah_intr_mitigation_rx) {
2803 /*
2804 * Enable Interrupt Mitigation for Rx.
2805 * If no build-specific limits for the rx interrupt mitigation
2806 * timer have been specified, use conservative defaults.
2807 */
2808 #ifndef AH_RIMT_VAL_LAST
2809 #define AH_RIMT_LAST_MICROSEC 500
2810 #endif
2811 #ifndef AH_RIMT_VAL_FIRST
2812 #define AH_RIMT_FIRST_MICROSEC 2000
2813 #endif
2814 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, AH_RIMT_LAST_MICROSEC);
2815 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, AH_RIMT_FIRST_MICROSEC);
2816 } else {
2817 OS_REG_WRITE(ah, AR_RIMT, 0);
2818 }
2819
2820 ahp->ah_enable_keysearch_always = !!enable;
2821 ar9300_enable_keysearch_always(ah, ahp->ah_enable_keysearch_always);
2822 }
2823 #endif
2824
ar9300_enable_tpc(struct ath_hal * ah)2825 void ar9300_enable_tpc(struct ath_hal *ah)
2826 {
2827 u_int32_t val = 0;
2828
2829 ah->ah_config.ath_hal_desc_tpc = 1;
2830
2831 /* Enable TPC */
2832 OS_REG_RMW_FIELD(ah, AR_PHY_PWRTX_MAX, AR_PHY_PER_PACKET_POWERTX_MAX, 1);
2833
2834 /*
2835 * Disable per chain power reduction since we are already
2836 * accounting for this in our calculations
2837 */
2838 val = OS_REG_READ(ah, AR_PHY_POWER_TX_SUB);
2839 if (AR_SREV_WASP(ah)) {
2840 OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
2841 val & AR_PHY_POWER_TX_SUB_2_DISABLE);
2842 } else {
2843 OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
2844 val & AR_PHY_POWER_TX_SUB_3_DISABLE);
2845 }
2846 }
2847
2848
2849 /*
2850 * ar9300_force_tsf_sync
2851 * This function forces the TSF sync to the given bssid, this is implemented
2852 * as a temp hack to get the AoW demo, and is primarily used in the WDS client
2853 * mode of operation, where we sync the TSF to RootAP TSF values
2854 */
2855 void
ar9300_force_tsf_sync(struct ath_hal * ah,const u_int8_t * bssid,u_int16_t assoc_id)2856 ar9300_force_tsf_sync(struct ath_hal *ah, const u_int8_t *bssid,
2857 u_int16_t assoc_id)
2858 {
2859 ar9300_set_operating_mode(ah, HAL_M_STA);
2860 ar9300_write_associd(ah, bssid, assoc_id);
2861 }
2862
ar9300_chk_rssi_update_tx_pwr(struct ath_hal * ah,int rssi)2863 void ar9300_chk_rssi_update_tx_pwr(struct ath_hal *ah, int rssi)
2864 {
2865 struct ath_hal_9300 *ahp = AH9300(ah);
2866 u_int32_t temp_obdb_reg_val = 0, temp_tcp_reg_val;
2867 u_int32_t temp_powertx_rate9_reg_val;
2868 int8_t olpc_power_offset = 0;
2869 int8_t tmp_olpc_val = 0;
2870 HAL_RSSI_TX_POWER old_greentx_status;
2871 u_int8_t target_power_val_t[ar9300_rate_size];
2872 int8_t tmp_rss1_thr1, tmp_rss1_thr2;
2873
2874 if ((AH_PRIVATE(ah)->ah_opmode != HAL_M_STA) ||
2875 !ah->ah_config.ath_hal_sta_update_tx_pwr_enable) {
2876 return;
2877 }
2878
2879 old_greentx_status = AH9300(ah)->green_tx_status;
2880 if (ahp->ah_hw_green_tx_enable) {
2881 tmp_rss1_thr1 = AR9485_HW_GREEN_TX_THRES1_DB;
2882 tmp_rss1_thr2 = AR9485_HW_GREEN_TX_THRES2_DB;
2883 } else {
2884 tmp_rss1_thr1 = WB225_SW_GREEN_TX_THRES1_DB;
2885 tmp_rss1_thr2 = WB225_SW_GREEN_TX_THRES2_DB;
2886 }
2887
2888 if ((ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S1)
2889 && (rssi > tmp_rss1_thr1))
2890 {
2891 if (old_greentx_status != HAL_RSSI_TX_POWER_SHORT) {
2892 AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_SHORT;
2893 }
2894 } else if (ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S2
2895 && (rssi > tmp_rss1_thr2))
2896 {
2897 if (old_greentx_status != HAL_RSSI_TX_POWER_MIDDLE) {
2898 AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_MIDDLE;
2899 }
2900 } else if (ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S3) {
2901 if (old_greentx_status != HAL_RSSI_TX_POWER_LONG) {
2902 AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_LONG;
2903 }
2904 }
2905
2906 /* If status is not change, don't do anything */
2907 if (old_greentx_status == AH9300(ah)->green_tx_status) {
2908 return;
2909 }
2910
2911 /* for Poseidon which ath_hal_sta_update_tx_pwr_enable is enabled */
2912 if ((AH9300(ah)->green_tx_status != HAL_RSSI_TX_POWER_NONE)
2913 && AR_SREV_POSEIDON(ah))
2914 {
2915 if (ahp->ah_hw_green_tx_enable) {
2916 switch (AH9300(ah)->green_tx_status) {
2917 case HAL_RSSI_TX_POWER_SHORT:
2918 /* 1. TxPower Config */
2919 OS_MEMCPY(target_power_val_t, ar9485_hw_gtx_tp_distance_short,
2920 sizeof(target_power_val_t));
2921 /* 1.1 Store OLPC Delta Calibration Offset*/
2922 olpc_power_offset = 0;
2923 /* 2. Store OB/DB */
2924 /* 3. Store TPC settting */
2925 temp_tcp_reg_val = (SM(14, AR_TPC_ACK) |
2926 SM(14, AR_TPC_CTS) |
2927 SM(14, AR_TPC_CHIRP) |
2928 SM(14, AR_TPC_RPT));
2929 /* 4. Store BB_powertx_rate9 value */
2930 temp_powertx_rate9_reg_val =
2931 AR9485_BBPWRTXRATE9_HW_GREEN_TX_SHORT_VALUE;
2932 break;
2933 case HAL_RSSI_TX_POWER_MIDDLE:
2934 /* 1. TxPower Config */
2935 OS_MEMCPY(target_power_val_t, ar9485_hw_gtx_tp_distance_middle,
2936 sizeof(target_power_val_t));
2937 /* 1.1 Store OLPC Delta Calibration Offset*/
2938 olpc_power_offset = 0;
2939 /* 2. Store OB/DB */
2940 /* 3. Store TPC settting */
2941 temp_tcp_reg_val = (SM(18, AR_TPC_ACK) |
2942 SM(18, AR_TPC_CTS) |
2943 SM(18, AR_TPC_CHIRP) |
2944 SM(18, AR_TPC_RPT));
2945 /* 4. Store BB_powertx_rate9 value */
2946 temp_powertx_rate9_reg_val =
2947 AR9485_BBPWRTXRATE9_HW_GREEN_TX_MIDDLE_VALUE;
2948 break;
2949 case HAL_RSSI_TX_POWER_LONG:
2950 default:
2951 /* 1. TxPower Config */
2952 OS_MEMCPY(target_power_val_t, ahp->ah_default_tx_power,
2953 sizeof(target_power_val_t));
2954 /* 1.1 Store OLPC Delta Calibration Offset*/
2955 olpc_power_offset = 0;
2956 /* 2. Store OB/DB1/DB2 */
2957 /* 3. Store TPC settting */
2958 temp_tcp_reg_val =
2959 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC];
2960 /* 4. Store BB_powertx_rate9 value */
2961 temp_powertx_rate9_reg_val =
2962 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9];
2963 break;
2964 }
2965 } else {
2966 switch (AH9300(ah)->green_tx_status) {
2967 case HAL_RSSI_TX_POWER_SHORT:
2968 /* 1. TxPower Config */
2969 OS_MEMCPY(target_power_val_t, wb225_sw_gtx_tp_distance_short,
2970 sizeof(target_power_val_t));
2971 /* 1.1 Store OLPC Delta Calibration Offset*/
2972 olpc_power_offset =
2973 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_SHORT_VALUE] -
2974 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE];
2975 /* 2. Store OB/DB */
2976 temp_obdb_reg_val =
2977 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB];
2978 temp_obdb_reg_val &= ~(AR_PHY_65NM_CH0_TXRF2_DB2G |
2979 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK |
2980 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK |
2981 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM);
2982 temp_obdb_reg_val |= (SM(5, AR_PHY_65NM_CH0_TXRF2_DB2G) |
2983 SM(WB225_OB_GREEN_TX_SHORT_VALUE,
2984 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK) |
2985 SM(WB225_OB_GREEN_TX_SHORT_VALUE,
2986 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK) |
2987 SM(WB225_OB_GREEN_TX_SHORT_VALUE,
2988 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM));
2989 /* 3. Store TPC settting */
2990 temp_tcp_reg_val = (SM(6, AR_TPC_ACK) |
2991 SM(6, AR_TPC_CTS) |
2992 SM(6, AR_TPC_CHIRP) |
2993 SM(6, AR_TPC_RPT));
2994 /* 4. Store BB_powertx_rate9 value */
2995 temp_powertx_rate9_reg_val =
2996 WB225_BBPWRTXRATE9_SW_GREEN_TX_SHORT_VALUE;
2997 break;
2998 case HAL_RSSI_TX_POWER_MIDDLE:
2999 /* 1. TxPower Config */
3000 OS_MEMCPY(target_power_val_t, wb225_sw_gtx_tp_distance_middle,
3001 sizeof(target_power_val_t));
3002 /* 1.1 Store OLPC Delta Calibration Offset*/
3003 olpc_power_offset =
3004 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_MIDDLE_VALUE] -
3005 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE];
3006 /* 2. Store OB/DB */
3007 temp_obdb_reg_val =
3008 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB];
3009 temp_obdb_reg_val &= ~(AR_PHY_65NM_CH0_TXRF2_DB2G |
3010 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK |
3011 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK |
3012 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM);
3013 temp_obdb_reg_val |= (SM(5, AR_PHY_65NM_CH0_TXRF2_DB2G) |
3014 SM(WB225_OB_GREEN_TX_MIDDLE_VALUE,
3015 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK) |
3016 SM(WB225_OB_GREEN_TX_MIDDLE_VALUE,
3017 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK) |
3018 SM(WB225_OB_GREEN_TX_MIDDLE_VALUE,
3019 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM));
3020 /* 3. Store TPC settting */
3021 temp_tcp_reg_val = (SM(14, AR_TPC_ACK) |
3022 SM(14, AR_TPC_CTS) |
3023 SM(14, AR_TPC_CHIRP) |
3024 SM(14, AR_TPC_RPT));
3025 /* 4. Store BB_powertx_rate9 value */
3026 temp_powertx_rate9_reg_val =
3027 WB225_BBPWRTXRATE9_SW_GREEN_TX_MIDDLE_VALUE;
3028 break;
3029 case HAL_RSSI_TX_POWER_LONG:
3030 default:
3031 /* 1. TxPower Config */
3032 OS_MEMCPY(target_power_val_t, ahp->ah_default_tx_power,
3033 sizeof(target_power_val_t));
3034 /* 1.1 Store OLPC Delta Calibration Offset*/
3035 olpc_power_offset =
3036 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_LONG_VALUE] -
3037 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE];
3038 /* 2. Store OB/DB1/DB2 */
3039 temp_obdb_reg_val =
3040 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB];
3041 /* 3. Store TPC settting */
3042 temp_tcp_reg_val =
3043 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC];
3044 /* 4. Store BB_powertx_rate9 value */
3045 temp_powertx_rate9_reg_val =
3046 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9];
3047 break;
3048 }
3049 }
3050 /* 1.1 Do OLPC Delta Calibration Offset */
3051 tmp_olpc_val =
3052 (int8_t) AH9300(ah)->ah_db2[POSEIDON_STORED_REG_G2_OLPC_OFFSET];
3053 tmp_olpc_val += olpc_power_offset;
3054 OS_REG_RMW(ah, AR_PHY_TPC_11_B0,
3055 (tmp_olpc_val << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
3056 AR_PHY_TPC_OLPC_GAIN_DELTA);
3057
3058 /* 1.2 TxPower Config */
3059 ar9300_transmit_power_reg_write(ah, target_power_val_t);
3060 /* 2. Config OB/DB */
3061 if (!ahp->ah_hw_green_tx_enable) {
3062 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF2, temp_obdb_reg_val);
3063 }
3064 /* 3. config TPC settting */
3065 OS_REG_WRITE(ah, AR_TPC, temp_tcp_reg_val);
3066 /* 4. config BB_powertx_rate9 value */
3067 OS_REG_WRITE(ah, AR_PHY_BB_POWERTX_RATE9, temp_powertx_rate9_reg_val);
3068 }
3069 }
3070
3071 #if 0
3072 void
3073 ar9300_get_vow_stats(
3074 struct ath_hal *ah, HAL_VOWSTATS* p_stats, u_int8_t vow_reg_flags)
3075 {
3076 if (vow_reg_flags & AR_REG_TX_FRM_CNT) {
3077 p_stats->tx_frame_count = OS_REG_READ(ah, AR_TFCNT);
3078 }
3079 if (vow_reg_flags & AR_REG_RX_FRM_CNT) {
3080 p_stats->rx_frame_count = OS_REG_READ(ah, AR_RFCNT);
3081 }
3082 if (vow_reg_flags & AR_REG_RX_CLR_CNT) {
3083 p_stats->rx_clear_count = OS_REG_READ(ah, AR_RCCNT);
3084 }
3085 if (vow_reg_flags & AR_REG_CYCLE_CNT) {
3086 p_stats->cycle_count = OS_REG_READ(ah, AR_CCCNT);
3087 }
3088 if (vow_reg_flags & AR_REG_EXT_CYCLE_CNT) {
3089 p_stats->ext_cycle_count = OS_REG_READ(ah, AR_EXTRCCNT);
3090 }
3091 }
3092 #endif
3093
3094 /*
3095 * ar9300_is_skip_paprd_by_greentx
3096 *
3097 * This function check if we need to skip PAPRD tuning
3098 * when GreenTx in specific state.
3099 */
3100 HAL_BOOL
ar9300_is_skip_paprd_by_greentx(struct ath_hal * ah)3101 ar9300_is_skip_paprd_by_greentx(struct ath_hal *ah)
3102 {
3103 if (AR_SREV_POSEIDON(ah) &&
3104 ah->ah_config.ath_hal_sta_update_tx_pwr_enable &&
3105 ((AH9300(ah)->green_tx_status == HAL_RSSI_TX_POWER_SHORT) ||
3106 (AH9300(ah)->green_tx_status == HAL_RSSI_TX_POWER_MIDDLE)))
3107 {
3108 return AH_TRUE;
3109 }
3110 return AH_FALSE;
3111 }
3112
3113 void
ar9300_control_signals_for_green_tx_mode(struct ath_hal * ah)3114 ar9300_control_signals_for_green_tx_mode(struct ath_hal *ah)
3115 {
3116 unsigned int valid_obdb_0_b0 = 0x2d; // 5,5 - dB[0:2],oB[5:3]
3117 unsigned int valid_obdb_1_b0 = 0x25; // 4,5 - dB[0:2],oB[5:3]
3118 unsigned int valid_obdb_2_b0 = 0x1d; // 3,5 - dB[0:2],oB[5:3]
3119 unsigned int valid_obdb_3_b0 = 0x15; // 2,5 - dB[0:2],oB[5:3]
3120 unsigned int valid_obdb_4_b0 = 0xd; // 1,5 - dB[0:2],oB[5:3]
3121 struct ath_hal_9300 *ahp = AH9300(ah);
3122
3123 if (AR_SREV_POSEIDON(ah) && ahp->ah_hw_green_tx_enable) {
3124 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON,
3125 AR_PHY_PAPRD_VALID_OBDB_0, valid_obdb_0_b0);
3126 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON,
3127 AR_PHY_PAPRD_VALID_OBDB_1, valid_obdb_1_b0);
3128 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON,
3129 AR_PHY_PAPRD_VALID_OBDB_2, valid_obdb_2_b0);
3130 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON,
3131 AR_PHY_PAPRD_VALID_OBDB_3, valid_obdb_3_b0);
3132 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON,
3133 AR_PHY_PAPRD_VALID_OBDB_4, valid_obdb_4_b0);
3134 }
3135 }
3136
ar9300_hwgreentx_set_pal_spare(struct ath_hal * ah,int value)3137 void ar9300_hwgreentx_set_pal_spare(struct ath_hal *ah, int value)
3138 {
3139 struct ath_hal_9300 *ahp = AH9300(ah);
3140
3141 if (AR_SREV_POSEIDON(ah) && ahp->ah_hw_green_tx_enable) {
3142 if ((value == 0) || (value == 1)) {
3143 OS_REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_TXRF3,
3144 AR_PHY_65NM_CH0_TXRF3_OLD_PAL_SPARE, value);
3145 }
3146 }
3147 }
3148
ar9300_reset_hw_beacon_proc_crc(struct ath_hal * ah)3149 void ar9300_reset_hw_beacon_proc_crc(struct ath_hal *ah)
3150 {
3151 OS_REG_SET_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_RESET_CRC);
3152 }
3153
ar9300_get_hw_beacon_rssi(struct ath_hal * ah)3154 int32_t ar9300_get_hw_beacon_rssi(struct ath_hal *ah)
3155 {
3156 int32_t val = OS_REG_READ_FIELD(ah, AR_BCN_RSSI_AVE, AR_BCN_RSSI_AVE_VAL);
3157
3158 /* RSSI format is 8.4. Ignore lowest four bits */
3159 val = val >> 4;
3160 return val;
3161 }
3162
ar9300_set_hw_beacon_rssi_threshold(struct ath_hal * ah,u_int32_t rssi_threshold)3163 void ar9300_set_hw_beacon_rssi_threshold(struct ath_hal *ah,
3164 u_int32_t rssi_threshold)
3165 {
3166 struct ath_hal_9300 *ahp = AH9300(ah);
3167
3168 OS_REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_THR_VAL, rssi_threshold);
3169
3170 /* save value for restoring after chip reset */
3171 ahp->ah_beacon_rssi_threshold = rssi_threshold;
3172 }
3173
ar9300_reset_hw_beacon_rssi(struct ath_hal * ah)3174 void ar9300_reset_hw_beacon_rssi(struct ath_hal *ah)
3175 {
3176 OS_REG_SET_BIT(ah, AR_RSSI_THR, AR_RSSI_BCN_RSSI_RST);
3177 }
3178
ar9300_set_hw_beacon_proc(struct ath_hal * ah,HAL_BOOL on)3179 void ar9300_set_hw_beacon_proc(struct ath_hal *ah, HAL_BOOL on)
3180 {
3181 if (on) {
3182 OS_REG_SET_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_CRC_ENABLE |
3183 AR_HWBCNPROC1_EXCLUDE_TIM_ELM);
3184 }
3185 else {
3186 OS_REG_CLR_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_CRC_ENABLE |
3187 AR_HWBCNPROC1_EXCLUDE_TIM_ELM);
3188 }
3189 }
3190 /*
3191 * Gets the contents of the specified key cache entry.
3192 */
3193 HAL_BOOL
ar9300_print_keycache(struct ath_hal * ah)3194 ar9300_print_keycache(struct ath_hal *ah)
3195 {
3196
3197 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
3198 u_int32_t key0, key1, key2, key3, key4;
3199 u_int32_t mac_hi, mac_lo;
3200 u_int16_t entry = 0;
3201 u_int32_t valid = 0;
3202 u_int32_t key_type;
3203
3204 ath_hal_printf(ah, "Slot Key\t\t\t Valid Type Mac \n");
3205
3206 for (entry = 0 ; entry < p_cap->halKeyCacheSize; entry++) {
3207 key0 = OS_REG_READ(ah, AR_KEYTABLE_KEY0(entry));
3208 key1 = OS_REG_READ(ah, AR_KEYTABLE_KEY1(entry));
3209 key2 = OS_REG_READ(ah, AR_KEYTABLE_KEY2(entry));
3210 key3 = OS_REG_READ(ah, AR_KEYTABLE_KEY3(entry));
3211 key4 = OS_REG_READ(ah, AR_KEYTABLE_KEY4(entry));
3212
3213 key_type = OS_REG_READ(ah, AR_KEYTABLE_TYPE(entry));
3214
3215 mac_lo = OS_REG_READ(ah, AR_KEYTABLE_MAC0(entry));
3216 mac_hi = OS_REG_READ(ah, AR_KEYTABLE_MAC1(entry));
3217
3218 if (mac_hi & AR_KEYTABLE_VALID) {
3219 valid = 1;
3220 } else {
3221 valid = 0;
3222 }
3223
3224 if ((mac_hi != 0) && (mac_lo != 0)) {
3225 mac_hi &= ~0x8000;
3226 mac_hi <<= 1;
3227 mac_hi |= ((mac_lo & (1 << 31) )) >> 31;
3228 mac_lo <<= 1;
3229 }
3230
3231 ath_hal_printf(ah,
3232 "%03d "
3233 "%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x"
3234 " %02d %02d "
3235 "%02x:%02x:%02x:%02x:%02x:%02x \n",
3236 entry,
3237 (key0 << 24) >> 24, (key0 << 16) >> 24,
3238 (key0 << 8) >> 24, key0 >> 24,
3239 (key1 << 24) >> 24, (key1 << 16) >> 24,
3240 //(key1 << 8) >> 24, key1 >> 24,
3241 (key2 << 24) >> 24, (key2 << 16) >> 24,
3242 (key2 << 8) >> 24, key2 >> 24,
3243 (key3 << 24) >> 24, (key3 << 16) >> 24,
3244 //(key3 << 8) >> 24, key3 >> 24,
3245 (key4 << 24) >> 24, (key4 << 16) >> 24,
3246 (key4 << 8) >> 24, key4 >> 24,
3247 valid, key_type,
3248 (mac_lo << 24) >> 24, (mac_lo << 16) >> 24, (mac_lo << 8) >> 24,
3249 (mac_lo) >> 24, (mac_hi << 24) >> 24, (mac_hi << 16) >> 24 );
3250 }
3251
3252 return AH_TRUE;
3253 }
3254
3255 /* enable/disable smart antenna mode */
3256 HAL_BOOL
ar9300_set_smart_antenna(struct ath_hal * ah,HAL_BOOL enable)3257 ar9300_set_smart_antenna(struct ath_hal *ah, HAL_BOOL enable)
3258 {
3259 struct ath_hal_9300 *ahp = AH9300(ah);
3260
3261 if (enable) {
3262 OS_REG_SET_BIT(ah, AR_XRTO, AR_ENABLE_SMARTANTENNA);
3263 } else {
3264 OS_REG_CLR_BIT(ah, AR_XRTO, AR_ENABLE_SMARTANTENNA);
3265 }
3266
3267 /* if scropion and smart antenna is enabled, write swcom1 with 0x440
3268 * and swcom2 with 0
3269 * FIXME Ideally these registers need to be made read from caldata.
3270 * Until the calibration team gets them, keep them along with board
3271 * configuration.
3272 */
3273 if (enable && AR_SREV_SCORPION(ah) &&
3274 (HAL_OK == ar9300_get_capability(ah, HAL_CAP_SMARTANTENNA, 0,0))) {
3275
3276 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, 0x440);
3277 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM_2, 0);
3278 }
3279
3280 ahp->ah_smartantenna_enable = enable;
3281 return 1;
3282 }
3283
3284 #ifdef ATH_TX99_DIAG
3285 #ifndef ATH_SUPPORT_HTC
3286 void
ar9300_tx99_channel_pwr_update(struct ath_hal * ah,HAL_CHANNEL * c,u_int32_t txpower)3287 ar9300_tx99_channel_pwr_update(struct ath_hal *ah, HAL_CHANNEL *c,
3288 u_int32_t txpower)
3289 {
3290 #define PWR_MAS(_r, _s) (((_r) & 0x3f) << (_s))
3291 static int16_t p_pwr_array[ar9300_rate_size] = { 0 };
3292 int32_t i;
3293
3294 /* The max power is limited to 63 */
3295 if (txpower <= AR9300_MAX_RATE_POWER) {
3296 for (i = 0; i < ar9300_rate_size; i++) {
3297 p_pwr_array[i] = txpower;
3298 }
3299 } else {
3300 for (i = 0; i < ar9300_rate_size; i++) {
3301 p_pwr_array[i] = AR9300_MAX_RATE_POWER;
3302 }
3303 }
3304
3305 OS_REG_WRITE(ah, 0xa458, 0);
3306
3307 /* Write the OFDM power per rate set */
3308 /* 6 (LSB), 9, 12, 18 (MSB) */
3309 OS_REG_WRITE(ah, 0xa3c0,
3310 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 24)
3311 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 16)
3312 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 8)
3313 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0)
3314 );
3315 /* 24 (LSB), 36, 48, 54 (MSB) */
3316 OS_REG_WRITE(ah, 0xa3c4,
3317 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_54], 24)
3318 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_48], 16)
3319 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_36], 8)
3320 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0)
3321 );
3322
3323 /* Write the CCK power per rate set */
3324 /* 1L (LSB), reserved, 2L, 2S (MSB) */
3325 OS_REG_WRITE(ah, 0xa3c8,
3326 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 24)
3327 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 16)
3328 /* | PWR_MAS(txPowerTimes2, 8) */ /* this is reserved for Osprey */
3329 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0)
3330 );
3331 /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */
3332 OS_REG_WRITE(ah, 0xa3cc,
3333 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_11S], 24)
3334 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_11L], 16)
3335 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_5S], 8)
3336 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0)
3337 );
3338
3339 /* Write the HT20 power per rate set */
3340 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
3341 OS_REG_WRITE(ah, 0xa3d0,
3342 PWR_MAS(p_pwr_array[ALL_TARGET_HT20_5], 24)
3343 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_4], 16)
3344 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_1_3_9_11_17_19], 8)
3345 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_0_8_16], 0)
3346 );
3347
3348 /* 6 (LSB), 7, 12, 13 (MSB) */
3349 OS_REG_WRITE(ah, 0xa3d4,
3350 PWR_MAS(p_pwr_array[ALL_TARGET_HT20_13], 24)
3351 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_12], 16)
3352 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_7], 8)
3353 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_6], 0)
3354 );
3355
3356 /* 14 (LSB), 15, 20, 21 */
3357 OS_REG_WRITE(ah, 0xa3e4,
3358 PWR_MAS(p_pwr_array[ALL_TARGET_HT20_21], 24)
3359 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_20], 16)
3360 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_15], 8)
3361 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_14], 0)
3362 );
3363
3364 /* Mixed HT20 and HT40 rates */
3365 /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */
3366 OS_REG_WRITE(ah, 0xa3e8,
3367 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_23], 24)
3368 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_22], 16)
3369 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_23], 8)
3370 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_22], 0)
3371 );
3372
3373 /* Write the HT40 power per rate set */
3374 /* correct PAR difference between HT40 and HT20/LEGACY */
3375 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
3376 OS_REG_WRITE(ah, 0xa3d8,
3377 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_5], 24)
3378 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_4], 16)
3379 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_1_3_9_11_17_19], 8)
3380 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_0_8_16], 0)
3381 );
3382
3383 /* 6 (LSB), 7, 12, 13 (MSB) */
3384 OS_REG_WRITE(ah, 0xa3dc,
3385 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_13], 24)
3386 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_12], 16)
3387 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_7], 8)
3388 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_6], 0)
3389 );
3390
3391 /* 14 (LSB), 15, 20, 21 */
3392 OS_REG_WRITE(ah, 0xa3ec,
3393 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_21], 24)
3394 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_20], 16)
3395 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_15], 8)
3396 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_14], 0)
3397 );
3398 #undef PWR_MAS
3399 }
3400
3401 void
ar9300_tx99_chainmsk_setup(struct ath_hal * ah,int tx_chainmask)3402 ar9300_tx99_chainmsk_setup(struct ath_hal *ah, int tx_chainmask)
3403 {
3404 if (tx_chainmask == 0x5) {
3405 OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
3406 OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | AR_PHY_SWAP_ALT_CHAIN);
3407 }
3408 OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, tx_chainmask);
3409 OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, tx_chainmask);
3410
3411 OS_REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
3412 if (tx_chainmask == 0x5) {
3413 OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
3414 OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | AR_PHY_SWAP_ALT_CHAIN);
3415 }
3416 }
3417
3418 void
ar9300_tx99_set_single_carrier(struct ath_hal * ah,int tx_chain_mask,int chtype)3419 ar9300_tx99_set_single_carrier(struct ath_hal *ah, int tx_chain_mask,
3420 int chtype)
3421 {
3422 OS_REG_WRITE(ah, 0x98a4, OS_REG_READ(ah, 0x98a4) | (0x7ff << 11) | 0x7ff);
3423 OS_REG_WRITE(ah, 0xa364, OS_REG_READ(ah, 0xa364) | (1 << 7) | (1 << 1));
3424 OS_REG_WRITE(ah, 0xa350,
3425 (OS_REG_READ(ah, 0xa350) | (1 << 31) | (1 << 15)) & ~(1 << 13));
3426
3427 /* 11G mode */
3428 if (!chtype) {
3429 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2,
3430 OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) | (0x1 << 3) | (0x1 << 2));
3431 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
3432 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP,
3433 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4));
3434 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2,
3435 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2)
3436 | (0x1 << 26) | (0x7 << 24))
3437 & ~(0x1 << 22));
3438 } else {
3439 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP,
3440 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4));
3441 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2,
3442 (OS_REG_READ(ah, AR_HORNET_CH0_TOP2)
3443 | (0x1 << 26) | (0x7 << 24))
3444 & ~(0x1 << 22));
3445 }
3446
3447 /* chain zero */
3448 if ((tx_chain_mask & 0x01) == 0x01) {
3449 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX1,
3450 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX1)
3451 | (0x1 << 31) | (0x5 << 15)
3452 | (0x3 << 9)) & ~(0x1 << 27)
3453 & ~(0x1 << 12));
3454 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2,
3455 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)
3456 | (0x1 << 12) | (0x1 << 10)
3457 | (0x1 << 9) | (0x1 << 8)
3458 | (0x1 << 7)) & ~(0x1 << 11));
3459 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3,
3460 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3)
3461 | (0x1 << 29) | (0x1 << 25)
3462 | (0x1 << 23) | (0x1 << 19)
3463 | (0x1 << 10) | (0x1 << 9)
3464 | (0x1 << 8) | (0x1 << 3))
3465 & ~(0x1 << 28)& ~(0x1 << 24)
3466 & ~(0x1 << 22)& ~(0x1 << 7));
3467 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1,
3468 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1)
3469 | (0x1 << 23))& ~(0x1 << 21));
3470 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB1,
3471 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB1)
3472 | (0x1 << 12) | (0x1 << 10)
3473 | (0x1 << 9) | (0x1 << 8)
3474 | (0x1 << 6) | (0x1 << 5)
3475 | (0x1 << 4) | (0x1 << 3)
3476 | (0x1 << 2));
3477 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB2,
3478 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB2) | (0x1 << 31));
3479 }
3480 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
3481 /* chain one */
3482 if ((tx_chain_mask & 0x02) == 0x02 ) {
3483 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX1,
3484 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX1)
3485 | (0x1 << 31) | (0x5 << 15)
3486 | (0x3 << 9)) & ~(0x1 << 27)
3487 & ~(0x1 << 12));
3488 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2,
3489 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2)
3490 | (0x1 << 12) | (0x1 << 10)
3491 | (0x1 << 9) | (0x1 << 8)
3492 | (0x1 << 7)) & ~(0x1 << 11));
3493 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3,
3494 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3)
3495 | (0x1 << 29) | (0x1 << 25)
3496 | (0x1 << 23) | (0x1 << 19)
3497 | (0x1 << 10) | (0x1 << 9)
3498 | (0x1 << 8) | (0x1 << 3))
3499 & ~(0x1 << 28)& ~(0x1 << 24)
3500 & ~(0x1 << 22)& ~(0x1 << 7));
3501 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1,
3502 (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1)
3503 | (0x1 << 23))& ~(0x1 << 21));
3504 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB1,
3505 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB1)
3506 | (0x1 << 12) | (0x1 << 10)
3507 | (0x1 << 9) | (0x1 << 8)
3508 | (0x1 << 6) | (0x1 << 5)
3509 | (0x1 << 4) | (0x1 << 3)
3510 | (0x1 << 2));
3511 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB2,
3512 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB2) | (0x1 << 31));
3513 }
3514 }
3515 if (AR_SREV_OSPREY(ah)) {
3516 /* chain two */
3517 if ((tx_chain_mask & 0x04) == 0x04 ) {
3518 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX1,
3519 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX1)
3520 | (0x1 << 31) | (0x5 << 15)
3521 | (0x3 << 9)) & ~(0x1 << 27)
3522 & ~(0x1 << 12));
3523 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2,
3524 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2)
3525 | (0x1 << 12) | (0x1 << 10)
3526 | (0x1 << 9) | (0x1 << 8)
3527 | (0x1 << 7)) & ~(0x1 << 11));
3528 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3,
3529 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3)
3530 | (0x1 << 29) | (0x1 << 25)
3531 | (0x1 << 23) | (0x1 << 19)
3532 | (0x1 << 10) | (0x1 << 9)
3533 | (0x1 << 8) | (0x1 << 3))
3534 & ~(0x1 << 28)& ~(0x1 << 24)
3535 & ~(0x1 << 22)& ~(0x1 << 7));
3536 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1,
3537 (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1)
3538 | (0x1 << 23))& ~(0x1 << 21));
3539 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB1,
3540 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB1)
3541 | (0x1 << 12) | (0x1 << 10)
3542 | (0x1 << 9) | (0x1 << 8)
3543 | (0x1 << 6) | (0x1 << 5)
3544 | (0x1 << 4) | (0x1 << 3)
3545 | (0x1 << 2));
3546 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB2,
3547 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB2) | (0x1 << 31));
3548 }
3549 }
3550
3551 OS_REG_WRITE(ah, 0xa28c, 0x11111);
3552 OS_REG_WRITE(ah, 0xa288, 0x111);
3553 } else {
3554 /* chain zero */
3555 if ((tx_chain_mask & 0x01) == 0x01) {
3556 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX1,
3557 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX1)
3558 | (0x1 << 31) | (0x1 << 27)
3559 | (0x3 << 23) | (0x1 << 19)
3560 | (0x1 << 15) | (0x3 << 9))
3561 & ~(0x1 << 12));
3562 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2,
3563 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)
3564 | (0x1 << 12) | (0x1 << 10)
3565 | (0x1 << 9) | (0x1 << 8)
3566 | (0x1 << 7) | (0x1 << 3)
3567 | (0x1 << 2) | (0x1 << 1))
3568 & ~(0x1 << 11)& ~(0x1 << 0));
3569 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3,
3570 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3)
3571 | (0x1 << 29) | (0x1 << 25)
3572 | (0x1 << 23) | (0x1 << 19)
3573 | (0x1 << 10) | (0x1 << 9)
3574 | (0x1 << 8) | (0x1 << 3))
3575 & ~(0x1 << 28)& ~(0x1 << 24)
3576 & ~(0x1 << 22)& ~(0x1 << 7));
3577 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1,
3578 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1)
3579 | (0x1 << 23))& ~(0x1 << 21));
3580 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF2,
3581 OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF2)
3582 | (0x3 << 3) | (0x3 << 0));
3583 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF3,
3584 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF3)
3585 | (0x3 << 29) | (0x3 << 26)
3586 | (0x2 << 23) | (0x2 << 20)
3587 | (0x2 << 17))& ~(0x1 << 14));
3588 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB1,
3589 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB1)
3590 | (0x1 << 12) | (0x1 << 10)
3591 | (0x1 << 9) | (0x1 << 8)
3592 | (0x1 << 6) | (0x1 << 5)
3593 | (0x1 << 4) | (0x1 << 3)
3594 | (0x1 << 2));
3595 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB2,
3596 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB2) | (0x1 << 31));
3597 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
3598 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP,
3599 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4));
3600 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2,
3601 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2)
3602 | (0x1 << 26) | (0x7 << 24)
3603 | (0x3 << 22));
3604 } else {
3605 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP,
3606 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4));
3607 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2,
3608 OS_REG_READ(ah, AR_HORNET_CH0_TOP2)
3609 | (0x1 << 26) | (0x7 << 24)
3610 | (0x3 << 22));
3611 }
3612
3613 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
3614 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2,
3615 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2)
3616 | (0x1 << 3) | (0x1 << 2)
3617 | (0x1 << 1)) & ~(0x1 << 0));
3618 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3,
3619 OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3)
3620 | (0x1 << 19) | (0x1 << 3));
3621 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1,
3622 OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) | (0x1 << 23));
3623 }
3624 if (AR_SREV_OSPREY(ah)) {
3625 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2,
3626 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2)
3627 | (0x1 << 3) | (0x1 << 2)
3628 | (0x1 << 1)) & ~(0x1 << 0));
3629 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3,
3630 OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3)
3631 | (0x1 << 19) | (0x1 << 3));
3632 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1,
3633 OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) | (0x1 << 23));
3634 }
3635 }
3636 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
3637 /* chain one */
3638 if ((tx_chain_mask & 0x02) == 0x02 ) {
3639 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2,
3640 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)
3641 | (0x1 << 3) | (0x1 << 2)
3642 | (0x1 << 1)) & ~(0x1 << 0));
3643 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3,
3644 OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3)
3645 | (0x1 << 19) | (0x1 << 3));
3646 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1,
3647 OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) | (0x1 << 23));
3648 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
3649 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP,
3650 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4));
3651 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2,
3652 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2)
3653 | (0x1 << 26) | (0x7 << 24)
3654 | (0x3 << 22));
3655 } else {
3656 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP,
3657 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4));
3658 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2,
3659 OS_REG_READ(ah, AR_HORNET_CH0_TOP2)
3660 | (0x1 << 26) | (0x7 << 24)
3661 | (0x3 << 22));
3662 }
3663
3664 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX1,
3665 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX1)
3666 | (0x1 << 31) | (0x1 << 27)
3667 | (0x3 << 23) | (0x1 << 19)
3668 | (0x1 << 15) | (0x3 << 9))
3669 & ~(0x1 << 12));
3670 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2,
3671 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2)
3672 | (0x1 << 12) | (0x1 << 10)
3673 | (0x1 << 9) | (0x1 << 8)
3674 | (0x1 << 7) | (0x1 << 3)
3675 | (0x1 << 2) | (0x1 << 1))
3676 & ~(0x1 << 11)& ~(0x1 << 0));
3677 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3,
3678 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3)
3679 | (0x1 << 29) | (0x1 << 25)
3680 | (0x1 << 23) | (0x1 << 19)
3681 | (0x1 << 10) | (0x1 << 9)
3682 | (0x1 << 8) | (0x1 << 3))
3683 & ~(0x1 << 28)& ~(0x1 << 24)
3684 & ~(0x1 << 22)& ~(0x1 << 7));
3685 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1,
3686 (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1)
3687 | (0x1 << 23))& ~(0x1 << 21));
3688 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF2,
3689 OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF2)
3690 | (0x3 << 3) | (0x3 << 0));
3691 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF3,
3692 (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF3)
3693 | (0x3 << 29) | (0x3 << 26)
3694 | (0x2 << 23) | (0x2 << 20)
3695 | (0x2 << 17))& ~(0x1 << 14));
3696 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB1,
3697 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB1)
3698 | (0x1 << 12) | (0x1 << 10)
3699 | (0x1 << 9) | (0x1 << 8)
3700 | (0x1 << 6) | (0x1 << 5)
3701 | (0x1 << 4) | (0x1 << 3)
3702 | (0x1 << 2));
3703 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB2,
3704 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB2) | (0x1 << 31));
3705
3706 if (AR_SREV_OSPREY(ah)) {
3707 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2,
3708 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2)
3709 | (0x1 << 3) | (0x1 << 2)
3710 | (0x1 << 1)) & ~(0x1 << 0));
3711 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3,
3712 OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3)
3713 | (0x1 << 19) | (0x1 << 3));
3714 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1,
3715 OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) | (0x1 << 23));
3716 }
3717 }
3718 }
3719 if (AR_SREV_OSPREY(ah)) {
3720 /* chain two */
3721 if ((tx_chain_mask & 0x04) == 0x04 ) {
3722 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2,
3723 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)
3724 | (0x1 << 3) | (0x1 << 2)
3725 | (0x1 << 1)) & ~(0x1 << 0));
3726 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3,
3727 OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3)
3728 | (0x1 << 19) | (0x1 << 3));
3729 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1,
3730 OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) | (0x1 << 23));
3731 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
3732 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP,
3733 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4));
3734 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2,
3735 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2)
3736 | (0x1 << 26) | (0x7 << 24)
3737 | (0x3 << 22));
3738 } else {
3739 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP,
3740 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4));
3741 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2,
3742 OS_REG_READ(ah, AR_HORNET_CH0_TOP2)
3743 | (0x1 << 26) | (0x7 << 24)
3744 | (0x3 << 22));
3745 }
3746
3747 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2,
3748 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2)
3749 | (0x1 << 3) | (0x1 << 2)
3750 | (0x1 << 1)) & ~(0x1 << 0));
3751 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3,
3752 OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3)
3753 | (0x1 << 19) | (0x1 << 3));
3754 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1,
3755 OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) | (0x1 << 23));
3756
3757 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX1,
3758 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX1)
3759 | (0x1 << 31) | (0x1 << 27)
3760 | (0x3 << 23) | (0x1 << 19)
3761 | (0x1 << 15) | (0x3 << 9))
3762 & ~(0x1 << 12));
3763 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2,
3764 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2)
3765 | (0x1 << 12) | (0x1 << 10)
3766 | (0x1 << 9) | (0x1 << 8)
3767 | (0x1 << 7) | (0x1 << 3)
3768 | (0x1 << 2) | (0x1 << 1))
3769 & ~(0x1 << 11)& ~(0x1 << 0));
3770 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3,
3771 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3)
3772 | (0x1 << 29) | (0x1 << 25)
3773 | (0x1 << 23) | (0x1 << 19)
3774 | (0x1 << 10) | (0x1 << 9)
3775 | (0x1 << 8) | (0x1 << 3))
3776 & ~(0x1 << 28)& ~(0x1 << 24)
3777 & ~(0x1 << 22)& ~(0x1 << 7));
3778 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1,
3779 (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1)
3780 | (0x1 << 23))& ~(0x1 << 21));
3781 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF2,
3782 OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF2)
3783 | (0x3 << 3) | (0x3 << 0));
3784 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF3,
3785 (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF3)
3786 | (0x3 << 29) | (0x3 << 26)
3787 | (0x2 << 23) | (0x2 << 20)
3788 | (0x2 << 17))& ~(0x1 << 14));
3789 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB1,
3790 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB1)
3791 | (0x1 << 12) | (0x1 << 10)
3792 | (0x1 << 9) | (0x1 << 8)
3793 | (0x1 << 6) | (0x1 << 5)
3794 | (0x1 << 4) | (0x1 << 3)
3795 | (0x1 << 2));
3796 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB2,
3797 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB2) | (0x1 << 31));
3798 }
3799 }
3800
3801 OS_REG_WRITE(ah, 0xa28c, 0x22222);
3802 OS_REG_WRITE(ah, 0xa288, 0x222);
3803 }
3804 }
3805
3806 void
ar9300_tx99_start(struct ath_hal * ah,u_int8_t * data)3807 ar9300_tx99_start(struct ath_hal *ah, u_int8_t *data)
3808 {
3809 u_int32_t val;
3810 u_int32_t qnum = (u_int32_t)data;
3811
3812 /* Disable AGC to A2 */
3813 OS_REG_WRITE(ah, AR_PHY_TEST, (OS_REG_READ(ah, AR_PHY_TEST) | PHY_AGC_CLR));
3814 OS_REG_WRITE(ah, AR_DIAG_SW, OS_REG_READ(ah, AR_DIAG_SW) &~ AR_DIAG_RX_DIS);
3815
3816 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* set receive disable */
3817 /* set CW_MIN and CW_MAX both to 0, AIFS=2 */
3818 OS_REG_WRITE(ah, AR_DLCL_IFS(qnum), 0);
3819 OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); /* 50 OK */
3820 OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20);
3821 /* 200 ok for HT20, 400 ok for HT40 */
3822 OS_REG_WRITE(ah, AR_TIME_OUT, 0x00000400);
3823 OS_REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff);
3824
3825 /* set QCU modes to early termination */
3826 val = OS_REG_READ(ah, AR_QMISC(qnum));
3827 OS_REG_WRITE(ah, AR_QMISC(qnum), val | AR_Q_MISC_DCU_EARLY_TERM_REQ);
3828 }
3829
3830 void
ar9300_tx99_stop(struct ath_hal * ah)3831 ar9300_tx99_stop(struct ath_hal *ah)
3832 {
3833 /* this should follow the setting of start */
3834 OS_REG_WRITE(ah, AR_PHY_TEST, OS_REG_READ(ah, AR_PHY_TEST) &~ PHY_AGC_CLR);
3835 OS_REG_WRITE(ah, AR_DIAG_SW, OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_RX_DIS);
3836 }
3837 #endif /* ATH_TX99_DIAG */
3838 #endif /* ATH_SUPPORT_HTC */
3839
3840 HAL_BOOL
ar9300Get3StreamSignature(struct ath_hal * ah)3841 ar9300Get3StreamSignature(struct ath_hal *ah)
3842 {
3843 return AH_FALSE;
3844 }
3845
3846 HAL_BOOL
ar9300ForceVCS(struct ath_hal * ah)3847 ar9300ForceVCS(struct ath_hal *ah)
3848 {
3849 return AH_FALSE;
3850 }
3851
3852 HAL_BOOL
ar9300SetDfs3StreamFix(struct ath_hal * ah,u_int32_t val)3853 ar9300SetDfs3StreamFix(struct ath_hal *ah, u_int32_t val)
3854 {
3855 return AH_FALSE;
3856 }
3857
3858 HAL_BOOL
ar9300_set_ctl_pwr(struct ath_hal * ah,u_int8_t * ctl_array)3859 ar9300_set_ctl_pwr(struct ath_hal *ah, u_int8_t *ctl_array)
3860 {
3861 struct ath_hal_9300 *ahp = AH9300(ah);
3862 ar9300_eeprom_t *p_eep_data = &ahp->ah_eeprom;
3863 u_int8_t *ctl_index;
3864 u_int32_t offset = 0;
3865
3866 if (!ctl_array)
3867 return AH_FALSE;
3868
3869 /* copy 2G ctl freqbin and power data */
3870 ctl_index = p_eep_data->ctl_index_2g;
3871 OS_MEMCPY(ctl_index + OSPREY_NUM_CTLS_2G, ctl_array,
3872 OSPREY_NUM_CTLS_2G * OSPREY_NUM_BAND_EDGES_2G + /* ctl_freqbin_2G */
3873 OSPREY_NUM_CTLS_2G * sizeof(OSP_CAL_CTL_DATA_2G)); /* ctl_power_data_2g */
3874 offset = (OSPREY_NUM_CTLS_2G * OSPREY_NUM_BAND_EDGES_2G) +
3875 ( OSPREY_NUM_CTLS_2G * sizeof(OSP_CAL_CTL_DATA_2G));
3876
3877
3878 /* copy 2G ctl freqbin and power data */
3879 ctl_index = p_eep_data->ctl_index_5g;
3880 OS_MEMCPY(ctl_index + OSPREY_NUM_CTLS_5G, ctl_array + offset,
3881 OSPREY_NUM_CTLS_5G * OSPREY_NUM_BAND_EDGES_5G + /* ctl_freqbin_5G */
3882 OSPREY_NUM_CTLS_5G * sizeof(OSP_CAL_CTL_DATA_5G)); /* ctl_power_data_5g */
3883
3884 return AH_FALSE;
3885 }
3886
3887 void
ar9300_set_txchainmaskopt(struct ath_hal * ah,u_int8_t mask)3888 ar9300_set_txchainmaskopt(struct ath_hal *ah, u_int8_t mask)
3889 {
3890 struct ath_hal_9300 *ahp = AH9300(ah);
3891
3892 /* optional txchainmask should be subset of primary txchainmask */
3893 if ((mask & ahp->ah_tx_chainmask) != mask) {
3894 ahp->ah_tx_chainmaskopt = 0;
3895 ath_hal_printf(ah, "Error: ah_tx_chainmask=%d, mask=%d\n", ahp->ah_tx_chainmask, mask);
3896 return;
3897 }
3898
3899 ahp->ah_tx_chainmaskopt = mask;
3900 }
3901