1 /*-
2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD$
27 */
28
29 /*
30 * Machine dependent interrupt code for x86. For x86, we have to
31 * deal with different PICs. Thus, we use the passed in vector to lookup
32 * an interrupt source associated with that vector. The interrupt source
33 * describes which PIC the source belongs to and includes methods to handle
34 * that source.
35 */
36
37 #include "opt_atpic.h"
38 #include "opt_ddb.h"
39
40 #include <sys/param.h>
41 #include <sys/bus.h>
42 #include <sys/interrupt.h>
43 #include <sys/ktr.h>
44 #include <sys/kernel.h>
45 #include <sys/lock.h>
46 #include <sys/mutex.h>
47 #include <sys/proc.h>
48 #include <sys/smp.h>
49 #include <sys/syslog.h>
50 #include <sys/systm.h>
51 #include <machine/clock.h>
52 #include <machine/intr_machdep.h>
53 #include <machine/smp.h>
54 #ifdef DDB
55 #include <ddb/ddb.h>
56 #endif
57
58 #ifndef DEV_ATPIC
59 #include <machine/segments.h>
60 #include <machine/frame.h>
61 #include <dev/ic/i8259.h>
62 #include <x86/isa/icu.h>
63 #ifdef PC98
64 #include <pc98/cbus/cbus.h>
65 #else
66 #include <isa/isareg.h>
67 #endif
68 #endif
69
70 #define MAX_STRAY_LOG 5
71
72 typedef void (*mask_fn)(void *);
73
74 static int intrcnt_index;
75 static struct intsrc *interrupt_sources[NUM_IO_INTS];
76 static struct mtx intr_table_lock;
77 static struct mtx intrcnt_lock;
78 static TAILQ_HEAD(pics_head, pic) pics;
79
80 #ifdef SMP
81 static int assign_cpu;
82 #endif
83
84 u_long intrcnt[INTRCNT_COUNT];
85 char intrnames[INTRCNT_COUNT * (MAXCOMLEN + 1)];
86 size_t sintrcnt = sizeof(intrcnt);
87 size_t sintrnames = sizeof(intrnames);
88
89 static int intr_assign_cpu(void *arg, int cpu);
90 static void intr_disable_src(void *arg);
91 static void intr_init(void *__dummy);
92 static int intr_pic_registered(struct pic *pic);
93 static void intrcnt_setname(const char *name, int index);
94 static void intrcnt_updatename(struct intsrc *is);
95 static void intrcnt_register(struct intsrc *is);
96
97 static int
intr_pic_registered(struct pic * pic)98 intr_pic_registered(struct pic *pic)
99 {
100 struct pic *p;
101
102 TAILQ_FOREACH(p, &pics, pics) {
103 if (p == pic)
104 return (1);
105 }
106 return (0);
107 }
108
109 /*
110 * Register a new interrupt controller (PIC). This is to support suspend
111 * and resume where we suspend/resume controllers rather than individual
112 * sources. This also allows controllers with no active sources (such as
113 * 8259As in a system using the APICs) to participate in suspend and resume.
114 */
115 int
intr_register_pic(struct pic * pic)116 intr_register_pic(struct pic *pic)
117 {
118 int error;
119
120 mtx_lock(&intr_table_lock);
121 if (intr_pic_registered(pic))
122 error = EBUSY;
123 else {
124 TAILQ_INSERT_TAIL(&pics, pic, pics);
125 error = 0;
126 }
127 mtx_unlock(&intr_table_lock);
128 return (error);
129 }
130
131 /*
132 * Register a new interrupt source with the global interrupt system.
133 * The global interrupts need to be disabled when this function is
134 * called.
135 */
136 int
intr_register_source(struct intsrc * isrc)137 intr_register_source(struct intsrc *isrc)
138 {
139 int error, vector;
140
141 KASSERT(intr_pic_registered(isrc->is_pic), ("unregistered PIC"));
142 vector = isrc->is_pic->pic_vector(isrc);
143 if (interrupt_sources[vector] != NULL)
144 return (EEXIST);
145 error = intr_event_create(&isrc->is_event, isrc, 0, vector,
146 intr_disable_src, (mask_fn)isrc->is_pic->pic_enable_source,
147 (mask_fn)isrc->is_pic->pic_eoi_source, intr_assign_cpu, "irq%d:",
148 vector);
149 if (error)
150 return (error);
151 mtx_lock(&intr_table_lock);
152 if (interrupt_sources[vector] != NULL) {
153 mtx_unlock(&intr_table_lock);
154 intr_event_destroy(isrc->is_event);
155 return (EEXIST);
156 }
157 intrcnt_register(isrc);
158 interrupt_sources[vector] = isrc;
159 isrc->is_handlers = 0;
160 mtx_unlock(&intr_table_lock);
161 return (0);
162 }
163
164 struct intsrc *
intr_lookup_source(int vector)165 intr_lookup_source(int vector)
166 {
167
168 return (interrupt_sources[vector]);
169 }
170
171 int
intr_add_handler(const char * name,int vector,driver_filter_t filter,driver_intr_t handler,void * arg,enum intr_type flags,void ** cookiep)172 intr_add_handler(const char *name, int vector, driver_filter_t filter,
173 driver_intr_t handler, void *arg, enum intr_type flags, void **cookiep)
174 {
175 struct intsrc *isrc;
176 int error;
177
178 isrc = intr_lookup_source(vector);
179 if (isrc == NULL)
180 return (EINVAL);
181 error = intr_event_add_handler(isrc->is_event, name, filter, handler,
182 arg, intr_priority(flags), flags, cookiep);
183 if (error == 0) {
184 mtx_lock(&intr_table_lock);
185 intrcnt_updatename(isrc);
186 isrc->is_handlers++;
187 if (isrc->is_handlers == 1) {
188 isrc->is_pic->pic_enable_intr(isrc);
189 isrc->is_pic->pic_enable_source(isrc);
190 }
191 mtx_unlock(&intr_table_lock);
192 }
193 return (error);
194 }
195
196 int
intr_remove_handler(void * cookie)197 intr_remove_handler(void *cookie)
198 {
199 struct intsrc *isrc;
200 int error, mtx_owned;
201
202 isrc = intr_handler_source(cookie);
203 error = intr_event_remove_handler(cookie);
204 if (error == 0) {
205 /*
206 * Recursion is needed here so PICs can remove interrupts
207 * while resuming. It was previously not possible due to
208 * intr_resume holding the intr_table_lock and
209 * intr_remove_handler recursing on it.
210 */
211 mtx_owned = mtx_owned(&intr_table_lock);
212 if (mtx_owned == 0)
213 mtx_lock(&intr_table_lock);
214 isrc->is_handlers--;
215 if (isrc->is_handlers == 0) {
216 isrc->is_pic->pic_disable_source(isrc, PIC_NO_EOI);
217 isrc->is_pic->pic_disable_intr(isrc);
218 }
219 intrcnt_updatename(isrc);
220 if (mtx_owned == 0)
221 mtx_unlock(&intr_table_lock);
222 }
223 return (error);
224 }
225
226 int
intr_config_intr(int vector,enum intr_trigger trig,enum intr_polarity pol)227 intr_config_intr(int vector, enum intr_trigger trig, enum intr_polarity pol)
228 {
229 struct intsrc *isrc;
230
231 isrc = intr_lookup_source(vector);
232 if (isrc == NULL)
233 return (EINVAL);
234 return (isrc->is_pic->pic_config_intr(isrc, trig, pol));
235 }
236
237 static void
intr_disable_src(void * arg)238 intr_disable_src(void *arg)
239 {
240 struct intsrc *isrc;
241
242 isrc = arg;
243 isrc->is_pic->pic_disable_source(isrc, PIC_EOI);
244 }
245
246 void
intr_execute_handlers(struct intsrc * isrc,struct trapframe * frame)247 intr_execute_handlers(struct intsrc *isrc, struct trapframe *frame)
248 {
249 struct intr_event *ie;
250 int vector;
251
252 /*
253 * We count software interrupts when we process them. The
254 * code here follows previous practice, but there's an
255 * argument for counting hardware interrupts when they're
256 * processed too.
257 */
258 (*isrc->is_count)++;
259 PCPU_INC(cnt.v_intr);
260
261 ie = isrc->is_event;
262
263 /*
264 * XXX: We assume that IRQ 0 is only used for the ISA timer
265 * device (clk).
266 */
267 vector = isrc->is_pic->pic_vector(isrc);
268 if (vector == 0)
269 clkintr_pending = 1;
270
271 /*
272 * For stray interrupts, mask and EOI the source, bump the
273 * stray count, and log the condition.
274 */
275 if (intr_event_handle(ie, frame) != 0) {
276 isrc->is_pic->pic_disable_source(isrc, PIC_EOI);
277 (*isrc->is_straycount)++;
278 if (*isrc->is_straycount < MAX_STRAY_LOG)
279 log(LOG_ERR, "stray irq%d\n", vector);
280 else if (*isrc->is_straycount == MAX_STRAY_LOG)
281 log(LOG_CRIT,
282 "too many stray irq %d's: not logging anymore\n",
283 vector);
284 }
285 }
286
287 void
intr_resume(bool suspend_cancelled)288 intr_resume(bool suspend_cancelled)
289 {
290 struct pic *pic;
291
292 #ifndef DEV_ATPIC
293 atpic_reset();
294 #endif
295 mtx_lock(&intr_table_lock);
296 TAILQ_FOREACH(pic, &pics, pics) {
297 if (pic->pic_resume != NULL)
298 pic->pic_resume(pic, suspend_cancelled);
299 }
300 mtx_unlock(&intr_table_lock);
301 }
302
303 void
intr_suspend(void)304 intr_suspend(void)
305 {
306 struct pic *pic;
307
308 mtx_lock(&intr_table_lock);
309 TAILQ_FOREACH_REVERSE(pic, &pics, pics_head, pics) {
310 if (pic->pic_suspend != NULL)
311 pic->pic_suspend(pic);
312 }
313 mtx_unlock(&intr_table_lock);
314 }
315
316 static int
intr_assign_cpu(void * arg,int cpu)317 intr_assign_cpu(void *arg, int cpu)
318 {
319 #ifdef SMP
320 struct intsrc *isrc;
321 int error;
322
323 /*
324 * Don't do anything during early boot. We will pick up the
325 * assignment once the APs are started.
326 */
327 if (assign_cpu && cpu != NOCPU) {
328 isrc = arg;
329 mtx_lock(&intr_table_lock);
330 error = isrc->is_pic->pic_assign_cpu(isrc, cpu_apic_ids[cpu]);
331 mtx_unlock(&intr_table_lock);
332 } else
333 error = 0;
334 return (error);
335 #else
336 return (EOPNOTSUPP);
337 #endif
338 }
339
340 static void
intrcnt_setname(const char * name,int index)341 intrcnt_setname(const char *name, int index)
342 {
343
344 snprintf(intrnames + (MAXCOMLEN + 1) * index, MAXCOMLEN + 1, "%-*s",
345 MAXCOMLEN, name);
346 }
347
348 static void
intrcnt_updatename(struct intsrc * is)349 intrcnt_updatename(struct intsrc *is)
350 {
351
352 intrcnt_setname(is->is_event->ie_fullname, is->is_index);
353 }
354
355 static void
intrcnt_register(struct intsrc * is)356 intrcnt_register(struct intsrc *is)
357 {
358 char straystr[MAXCOMLEN + 1];
359
360 KASSERT(is->is_event != NULL, ("%s: isrc with no event", __func__));
361 mtx_lock_spin(&intrcnt_lock);
362 is->is_index = intrcnt_index;
363 intrcnt_index += 2;
364 snprintf(straystr, MAXCOMLEN + 1, "stray irq%d",
365 is->is_pic->pic_vector(is));
366 intrcnt_updatename(is);
367 is->is_count = &intrcnt[is->is_index];
368 intrcnt_setname(straystr, is->is_index + 1);
369 is->is_straycount = &intrcnt[is->is_index + 1];
370 mtx_unlock_spin(&intrcnt_lock);
371 }
372
373 void
intrcnt_add(const char * name,u_long ** countp)374 intrcnt_add(const char *name, u_long **countp)
375 {
376
377 mtx_lock_spin(&intrcnt_lock);
378 *countp = &intrcnt[intrcnt_index];
379 intrcnt_setname(name, intrcnt_index);
380 intrcnt_index++;
381 mtx_unlock_spin(&intrcnt_lock);
382 }
383
384 static void
intr_init(void * dummy __unused)385 intr_init(void *dummy __unused)
386 {
387
388 intrcnt_setname("???", 0);
389 intrcnt_index = 1;
390 TAILQ_INIT(&pics);
391 mtx_init(&intr_table_lock, "intr sources", NULL, MTX_DEF);
392 mtx_init(&intrcnt_lock, "intrcnt", NULL, MTX_SPIN);
393 }
394 SYSINIT(intr_init, SI_SUB_INTR, SI_ORDER_FIRST, intr_init, NULL);
395
396 #ifndef DEV_ATPIC
397 /* Initialize the two 8259A's to a known-good shutdown state. */
398 void
atpic_reset(void)399 atpic_reset(void)
400 {
401
402 outb(IO_ICU1, ICW1_RESET | ICW1_IC4);
403 outb(IO_ICU1 + ICU_IMR_OFFSET, IDT_IO_INTS);
404 outb(IO_ICU1 + ICU_IMR_OFFSET, IRQ_MASK(ICU_SLAVEID));
405 outb(IO_ICU1 + ICU_IMR_OFFSET, MASTER_MODE);
406 outb(IO_ICU1 + ICU_IMR_OFFSET, 0xff);
407 outb(IO_ICU1, OCW3_SEL | OCW3_RR);
408
409 outb(IO_ICU2, ICW1_RESET | ICW1_IC4);
410 outb(IO_ICU2 + ICU_IMR_OFFSET, IDT_IO_INTS + 8);
411 outb(IO_ICU2 + ICU_IMR_OFFSET, ICU_SLAVEID);
412 outb(IO_ICU2 + ICU_IMR_OFFSET, SLAVE_MODE);
413 outb(IO_ICU2 + ICU_IMR_OFFSET, 0xff);
414 outb(IO_ICU2, OCW3_SEL | OCW3_RR);
415 }
416 #endif
417
418 /* Add a description to an active interrupt handler. */
419 int
intr_describe(u_int vector,void * ih,const char * descr)420 intr_describe(u_int vector, void *ih, const char *descr)
421 {
422 struct intsrc *isrc;
423 int error;
424
425 isrc = intr_lookup_source(vector);
426 if (isrc == NULL)
427 return (EINVAL);
428 error = intr_event_describe_handler(isrc->is_event, ih, descr);
429 if (error)
430 return (error);
431 intrcnt_updatename(isrc);
432 return (0);
433 }
434
435 void
intr_reprogram(void)436 intr_reprogram(void)
437 {
438 struct intsrc *is;
439 int v;
440
441 mtx_lock(&intr_table_lock);
442 for (v = 0; v < NUM_IO_INTS; v++) {
443 is = interrupt_sources[v];
444 if (is == NULL)
445 continue;
446 if (is->is_pic->pic_reprogram_pin != NULL)
447 is->is_pic->pic_reprogram_pin(is);
448 }
449 mtx_unlock(&intr_table_lock);
450 }
451
452 #ifdef DDB
453 /*
454 * Dump data about interrupt handlers
455 */
DB_SHOW_COMMAND(irqs,db_show_irqs)456 DB_SHOW_COMMAND(irqs, db_show_irqs)
457 {
458 struct intsrc **isrc;
459 int i, verbose;
460
461 if (strcmp(modif, "v") == 0)
462 verbose = 1;
463 else
464 verbose = 0;
465 isrc = interrupt_sources;
466 for (i = 0; i < NUM_IO_INTS && !db_pager_quit; i++, isrc++)
467 if (*isrc != NULL)
468 db_dump_intr_event((*isrc)->is_event, verbose);
469 }
470 #endif
471
472 #ifdef SMP
473 /*
474 * Support for balancing interrupt sources across CPUs. For now we just
475 * allocate CPUs round-robin.
476 */
477
478 cpuset_t intr_cpus = CPUSET_T_INITIALIZER(0x1);
479 static int current_cpu;
480
481 /*
482 * Return the CPU that the next interrupt source should use. For now
483 * this just returns the next local APIC according to round-robin.
484 */
485 u_int
intr_next_cpu(void)486 intr_next_cpu(void)
487 {
488 u_int apic_id;
489
490 /* Leave all interrupts on the BSP during boot. */
491 if (!assign_cpu)
492 return (PCPU_GET(apic_id));
493
494 mtx_lock_spin(&icu_lock);
495 apic_id = cpu_apic_ids[current_cpu];
496 do {
497 current_cpu++;
498 if (current_cpu > mp_maxid)
499 current_cpu = 0;
500 } while (!CPU_ISSET(current_cpu, &intr_cpus));
501 mtx_unlock_spin(&icu_lock);
502 return (apic_id);
503 }
504
505 /* Attempt to bind the specified IRQ to the specified CPU. */
506 int
intr_bind(u_int vector,u_char cpu)507 intr_bind(u_int vector, u_char cpu)
508 {
509 struct intsrc *isrc;
510
511 isrc = intr_lookup_source(vector);
512 if (isrc == NULL)
513 return (EINVAL);
514 return (intr_event_bind(isrc->is_event, cpu));
515 }
516
517 /*
518 * Add a CPU to our mask of valid CPUs that can be destinations of
519 * interrupts.
520 */
521 void
intr_add_cpu(u_int cpu)522 intr_add_cpu(u_int cpu)
523 {
524
525 if (cpu >= MAXCPU)
526 panic("%s: Invalid CPU ID", __func__);
527 if (bootverbose)
528 printf("INTR: Adding local APIC %d as a target\n",
529 cpu_apic_ids[cpu]);
530
531 CPU_SET(cpu, &intr_cpus);
532 }
533
534 /*
535 * Distribute all the interrupt sources among the available CPUs once the
536 * AP's have been launched.
537 */
538 static void
intr_shuffle_irqs(void * arg __unused)539 intr_shuffle_irqs(void *arg __unused)
540 {
541 struct intsrc *isrc;
542 int i;
543
544 /* Don't bother on UP. */
545 if (mp_ncpus == 1)
546 return;
547
548 /* Round-robin assign a CPU to each enabled source. */
549 mtx_lock(&intr_table_lock);
550 assign_cpu = 1;
551 for (i = 0; i < NUM_IO_INTS; i++) {
552 isrc = interrupt_sources[i];
553 if (isrc != NULL && isrc->is_handlers > 0) {
554 /*
555 * If this event is already bound to a CPU,
556 * then assign the source to that CPU instead
557 * of picking one via round-robin. Note that
558 * this is careful to only advance the
559 * round-robin if the CPU assignment succeeds.
560 */
561 if (isrc->is_event->ie_cpu != NOCPU)
562 (void)isrc->is_pic->pic_assign_cpu(isrc,
563 cpu_apic_ids[isrc->is_event->ie_cpu]);
564 else if (isrc->is_pic->pic_assign_cpu(isrc,
565 cpu_apic_ids[current_cpu]) == 0)
566 (void)intr_next_cpu();
567
568 }
569 }
570 mtx_unlock(&intr_table_lock);
571 }
572 SYSINIT(intr_shuffle_irqs, SI_SUB_SMP, SI_ORDER_SECOND, intr_shuffle_irqs,
573 NULL);
574 #else
575 /*
576 * Always route interrupts to the current processor in the UP case.
577 */
578 u_int
intr_next_cpu(void)579 intr_next_cpu(void)
580 {
581
582 return (PCPU_GET(apic_id));
583 }
584 #endif
585