1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Stanislaw Skowronek 23 */ 24 25 #ifndef ATOM_NAMES_H 26 #define ATOM_NAMES_H 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD: stable/10/sys/dev/drm2/radeon/atom-names.h 254885 2013-08-25 19:37:15Z dumbbell $"); 30 31 #include "atom.h" 32 33 #ifdef ATOM_DEBUG 34 35 #define ATOM_OP_NAMES_CNT 123 36 static char *atom_op_names[ATOM_OP_NAMES_CNT] = { 37 "RESERVED", "MOVE_REG", "MOVE_PS", "MOVE_WS", "MOVE_FB", "MOVE_PLL", 38 "MOVE_MC", "AND_REG", "AND_PS", "AND_WS", "AND_FB", "AND_PLL", "AND_MC", 39 "OR_REG", "OR_PS", "OR_WS", "OR_FB", "OR_PLL", "OR_MC", "SHIFT_LEFT_REG", 40 "SHIFT_LEFT_PS", "SHIFT_LEFT_WS", "SHIFT_LEFT_FB", "SHIFT_LEFT_PLL", 41 "SHIFT_LEFT_MC", "SHIFT_RIGHT_REG", "SHIFT_RIGHT_PS", "SHIFT_RIGHT_WS", 42 "SHIFT_RIGHT_FB", "SHIFT_RIGHT_PLL", "SHIFT_RIGHT_MC", "MUL_REG", 43 "MUL_PS", "MUL_WS", "MUL_FB", "MUL_PLL", "MUL_MC", "DIV_REG", "DIV_PS", 44 "DIV_WS", "DIV_FB", "DIV_PLL", "DIV_MC", "ADD_REG", "ADD_PS", "ADD_WS", 45 "ADD_FB", "ADD_PLL", "ADD_MC", "SUB_REG", "SUB_PS", "SUB_WS", "SUB_FB", 46 "SUB_PLL", "SUB_MC", "SET_ATI_PORT", "SET_PCI_PORT", "SET_SYS_IO_PORT", 47 "SET_REG_BLOCK", "SET_FB_BASE", "COMPARE_REG", "COMPARE_PS", 48 "COMPARE_WS", "COMPARE_FB", "COMPARE_PLL", "COMPARE_MC", "SWITCH", 49 "JUMP", "JUMP_EQUAL", "JUMP_BELOW", "JUMP_ABOVE", "JUMP_BELOW_OR_EQUAL", 50 "JUMP_ABOVE_OR_EQUAL", "JUMP_NOT_EQUAL", "TEST_REG", "TEST_PS", "TEST_WS", 51 "TEST_FB", "TEST_PLL", "TEST_MC", "DELAY_MILLISEC", "DELAY_MICROSEC", 52 "CALL_TABLE", "REPEAT", "CLEAR_REG", "CLEAR_PS", "CLEAR_WS", "CLEAR_FB", 53 "CLEAR_PLL", "CLEAR_MC", "NOP", "EOT", "MASK_REG", "MASK_PS", "MASK_WS", 54 "MASK_FB", "MASK_PLL", "MASK_MC", "POST_CARD", "BEEP", "SAVE_REG", 55 "RESTORE_REG", "SET_DATA_BLOCK", "XOR_REG", "XOR_PS", "XOR_WS", "XOR_FB", 56 "XOR_PLL", "XOR_MC", "SHL_REG", "SHL_PS", "SHL_WS", "SHL_FB", "SHL_PLL", 57 "SHL_MC", "SHR_REG", "SHR_PS", "SHR_WS", "SHR_FB", "SHR_PLL", "SHR_MC", 58 "DEBUG", "CTB_DS", 59 }; 60 61 #define ATOM_TABLE_NAMES_CNT 74 62 static char *atom_table_names[ATOM_TABLE_NAMES_CNT] = { 63 "ASIC_Init", "GetDisplaySurfaceSize", "ASIC_RegistersInit", 64 "VRAM_BlockVenderDetection", "SetClocksRatio", "MemoryControllerInit", 65 "GPIO_PinInit", "MemoryParamAdjust", "DVOEncoderControl", 66 "GPIOPinControl", "SetEngineClock", "SetMemoryClock", "SetPixelClock", 67 "DynamicClockGating", "ResetMemoryDLL", "ResetMemoryDevice", 68 "MemoryPLLInit", "EnableMemorySelfRefresh", "AdjustMemoryController", 69 "EnableASIC_StaticPwrMgt", "ASIC_StaticPwrMgtStatusChange", 70 "DAC_LoadDetection", "TMDS2EncoderControl", "LCD1OutputControl", 71 "DAC1EncoderControl", "DAC2EncoderControl", "DVOOutputControl", 72 "CV1OutputControl", "SetCRTC_DPM_State", "TVEncoderControl", 73 "TMDS1EncoderControl", "LVDSEncoderControl", "TV1OutputControl", 74 "EnableScaler", "BlankCRTC", "EnableCRTC", "GetPixelClock", 75 "EnableVGA_Render", "EnableVGA_Access", "SetCRTC_Timing", 76 "SetCRTC_OverScan", "SetCRTC_Replication", "SelectCRTC_Source", 77 "EnableGraphSurfaces", "UpdateCRTC_DoubleBufferRegisters", 78 "LUT_AutoFill", "EnableHW_IconCursor", "GetMemoryClock", 79 "GetEngineClock", "SetCRTC_UsingDTDTiming", "TVBootUpStdPinDetection", 80 "DFP2OutputControl", "VRAM_BlockDetectionByStrap", "MemoryCleanUp", 81 "ReadEDIDFromHWAssistedI2C", "WriteOneByteToHWAssistedI2C", 82 "ReadHWAssistedI2CStatus", "SpeedFanControl", "PowerConnectorDetection", 83 "MC_Synchronization", "ComputeMemoryEnginePLL", "MemoryRefreshConversion", 84 "VRAM_GetCurrentInfoBlock", "DynamicMemorySettings", "MemoryTraining", 85 "EnableLVDS_SS", "DFP1OutputControl", "SetVoltage", "CRT1OutputControl", 86 "CRT2OutputControl", "SetupHWAssistedI2CStatus", "ClockSource", 87 "MemoryDeviceInit", "EnableYUV", 88 }; 89 90 #define ATOM_IO_NAMES_CNT 5 91 static char *atom_io_names[ATOM_IO_NAMES_CNT] = { 92 "MM", "PLL", "MC", "PCIE", "PCIE PORT", 93 }; 94 95 #else 96 97 #define ATOM_OP_NAMES_CNT 0 98 #define ATOM_TABLE_NAMES_CNT 0 99 #define ATOM_IO_NAMES_CNT 0 100 101 #endif 102 103 #endif 104