1 /*-
2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
15 *
16 * NO WARRANTY
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTABILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
28 */
29
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
32
33 /*
34 * Driver for the Atheros Wireless LAN controller.
35 *
36 * This software is derived from work of Atsushi Onoe; his contribution
37 * is greatly appreciated.
38 */
39
40 #include "opt_inet.h"
41 #include "opt_ath.h"
42 /*
43 * This is needed for register operations which are performed
44 * by the driver - eg, calls to ath_hal_gettsf32().
45 *
46 * It's also required for any AH_DEBUG checks in here, eg the
47 * module dependencies.
48 */
49 #include "opt_ah.h"
50 #include "opt_wlan.h"
51
52 #include <sys/param.h>
53 #include <sys/systm.h>
54 #include <sys/sysctl.h>
55 #include <sys/mbuf.h>
56 #include <sys/malloc.h>
57 #include <sys/lock.h>
58 #include <sys/kernel.h>
59 #include <sys/socket.h>
60 #include <sys/sockio.h>
61 #include <sys/errno.h>
62 #include <sys/callout.h>
63 #include <sys/bus.h>
64 #include <sys/endian.h>
65 #include <sys/kthread.h>
66 #include <sys/taskqueue.h>
67 #include <sys/caps.h>
68 #include <sys/module.h>
69 #include <sys/ktr.h>
70
71 #if defined(__DragonFly__)
72 /* empty */
73 #else
74 #include <sys/smp.h> /* for mp_ncpus */
75 #include <machine/bus.h>
76 #endif
77
78 #include <net/if.h>
79 #include <net/if_var.h>
80 #include <net/if_dl.h>
81 #include <net/if_media.h>
82 #include <net/if_types.h>
83 #include <net/if_arp.h>
84 #include <net/ethernet.h>
85 #include <net/if_llc.h>
86
87 #include <netproto/802_11/ieee80211_var.h>
88 #include <netproto/802_11/ieee80211_regdomain.h>
89 #ifdef IEEE80211_SUPPORT_SUPERG
90 #include <netproto/802_11/ieee80211_superg.h>
91 #endif
92
93 #include <net/bpf.h>
94
95 #ifdef INET
96 #include <netinet/in.h>
97 #include <netinet/if_ether.h>
98 #endif
99
100 #include <dev/netif/ath/ath/if_athvar.h>
101
102 #include <dev/netif/ath/ath/if_ath_debug.h>
103 #include <dev/netif/ath/ath/if_ath_misc.h>
104 #include <dev/netif/ath/ath/if_ath_tx.h>
105 #include <dev/netif/ath/ath/if_ath_beacon.h>
106
107 #ifdef ATH_TX99_DIAG
108 #include <dev/netif/ath/ath/ath_tx99/ath_tx99.h>
109 #endif
110
111 /*
112 * Setup a h/w transmit queue for beacons.
113 */
114 int
ath_beaconq_setup(struct ath_softc * sc)115 ath_beaconq_setup(struct ath_softc *sc)
116 {
117 struct ath_hal *ah = sc->sc_ah;
118 HAL_TXQ_INFO qi;
119
120 memset(&qi, 0, sizeof(qi));
121 qi.tqi_aifs = HAL_TXQ_USEDEFAULT;
122 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT;
123 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT;
124 /* NB: for dynamic turbo, don't enable any other interrupts */
125 qi.tqi_qflags = HAL_TXQ_TXDESCINT_ENABLE;
126 if (sc->sc_isedma)
127 qi.tqi_qflags |= HAL_TXQ_TXOKINT_ENABLE |
128 HAL_TXQ_TXERRINT_ENABLE;
129
130 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi);
131 }
132
133 /*
134 * Setup the transmit queue parameters for the beacon queue.
135 */
136 int
ath_beaconq_config(struct ath_softc * sc)137 ath_beaconq_config(struct ath_softc *sc)
138 {
139 #define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1)
140 struct ieee80211com *ic = &sc->sc_ic;
141 struct ath_hal *ah = sc->sc_ah;
142 HAL_TXQ_INFO qi;
143
144 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi);
145 if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
146 ic->ic_opmode == IEEE80211_M_MBSS) {
147 /*
148 * Always burst out beacon and CAB traffic.
149 */
150 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT;
151 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT;
152 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT;
153 } else {
154 struct wmeParams *wmep =
155 &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE];
156 /*
157 * Adhoc mode; important thing is to use 2x cwmin.
158 */
159 qi.tqi_aifs = wmep->wmep_aifsn;
160 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin);
161 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax);
162 }
163
164 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) {
165 device_printf(sc->sc_dev, "unable to update parameters for "
166 "beacon hardware queue!\n");
167 return 0;
168 } else {
169 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */
170 return 1;
171 }
172 #undef ATH_EXPONENT_TO_VALUE
173 }
174
175 /*
176 * Allocate and setup an initial beacon frame.
177 */
178 int
ath_beacon_alloc(struct ath_softc * sc,struct ieee80211_node * ni)179 ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni)
180 {
181 struct ieee80211vap *vap = ni->ni_vap;
182 struct ath_vap *avp = ATH_VAP(vap);
183 struct ath_buf *bf;
184 struct mbuf *m;
185 int error;
186
187 bf = avp->av_bcbuf;
188 DPRINTF(sc, ATH_DEBUG_NODE, "%s: bf_m=%p, bf_node=%p\n",
189 __func__, bf->bf_m, bf->bf_node);
190 if (bf->bf_m != NULL) {
191 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
192 m_freem(bf->bf_m);
193 bf->bf_m = NULL;
194 }
195 if (bf->bf_node != NULL) {
196 ieee80211_free_node(bf->bf_node);
197 bf->bf_node = NULL;
198 }
199
200 /*
201 * NB: the beacon data buffer must be 32-bit aligned;
202 * we assume the mbuf routines will return us something
203 * with this alignment (perhaps should assert).
204 */
205 m = ieee80211_beacon_alloc(ni);
206 if (m == NULL) {
207 device_printf(sc->sc_dev, "%s: cannot get mbuf\n", __func__);
208 sc->sc_stats.ast_be_nombuf++;
209 return ENOMEM;
210 }
211 #if defined(__DragonFly__)
212 error = bus_dmamap_load_mbuf_segment(sc->sc_dmat, bf->bf_dmamap, m,
213 bf->bf_segs, 1, &bf->bf_nseg,
214 BUS_DMA_NOWAIT);
215 #else
216 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m,
217 bf->bf_segs, &bf->bf_nseg,
218 BUS_DMA_NOWAIT);
219 #endif
220 if (error != 0) {
221 device_printf(sc->sc_dev,
222 "%s: cannot map mbuf, bus_dmamap_load_mbuf_sg returns %d\n",
223 __func__, error);
224 m_freem(m);
225 return error;
226 }
227
228 /*
229 * Calculate a TSF adjustment factor required for staggered
230 * beacons. Note that we assume the format of the beacon
231 * frame leaves the tstamp field immediately following the
232 * header.
233 */
234 if (sc->sc_stagbeacons && avp->av_bslot > 0) {
235 uint64_t tsfadjust;
236 struct ieee80211_frame *wh;
237
238 /*
239 * The beacon interval is in TU's; the TSF is in usecs.
240 * We figure out how many TU's to add to align the timestamp
241 * then convert to TSF units and handle byte swapping before
242 * inserting it in the frame. The hardware will then add this
243 * each time a beacon frame is sent. Note that we align vap's
244 * 1..N and leave vap 0 untouched. This means vap 0 has a
245 * timestamp in one beacon interval while the others get a
246 * timstamp aligned to the next interval.
247 */
248 tsfadjust = ni->ni_intval *
249 (ATH_BCBUF - avp->av_bslot) / ATH_BCBUF;
250 tsfadjust = htole64(tsfadjust << 10); /* TU -> TSF */
251
252 DPRINTF(sc, ATH_DEBUG_BEACON,
253 "%s: %s beacons bslot %d intval %u tsfadjust %llu\n",
254 __func__, sc->sc_stagbeacons ? "stagger" : "burst",
255 avp->av_bslot, ni->ni_intval,
256 (long long unsigned) le64toh(tsfadjust));
257
258 wh = mtod(m, struct ieee80211_frame *);
259 memcpy(&wh[1], &tsfadjust, sizeof(tsfadjust));
260 }
261 bf->bf_m = m;
262 bf->bf_node = ieee80211_ref_node(ni);
263
264 return 0;
265 }
266
267 /*
268 * Setup the beacon frame for transmit.
269 */
270 static void
ath_beacon_setup(struct ath_softc * sc,struct ath_buf * bf)271 ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf)
272 {
273 #define USE_SHPREAMBLE(_ic) \
274 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\
275 == IEEE80211_F_SHPREAMBLE)
276 struct ieee80211_node *ni = bf->bf_node;
277 struct ieee80211com *ic = ni->ni_ic;
278 struct mbuf *m = bf->bf_m;
279 struct ath_hal *ah = sc->sc_ah;
280 struct ath_desc *ds;
281 int flags, antenna;
282 const HAL_RATE_TABLE *rt;
283 u_int8_t rix, rate;
284 HAL_DMA_ADDR bufAddrList[4];
285 uint32_t segLenList[4];
286 HAL_11N_RATE_SERIES rc[4];
287
288 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: m %p len %u\n",
289 __func__, m, m->m_len);
290
291 /* setup descriptors */
292 ds = bf->bf_desc;
293 bf->bf_last = bf;
294 bf->bf_lastds = ds;
295
296 flags = HAL_TXDESC_NOACK;
297 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) {
298 /* self-linked descriptor */
299 ath_hal_settxdesclink(sc->sc_ah, ds, bf->bf_daddr);
300 flags |= HAL_TXDESC_VEOL;
301 /*
302 * Let hardware handle antenna switching.
303 */
304 antenna = sc->sc_txantenna;
305 } else {
306 ath_hal_settxdesclink(sc->sc_ah, ds, 0);
307 /*
308 * Switch antenna every 4 beacons.
309 * XXX assumes two antenna
310 */
311 if (sc->sc_txantenna != 0)
312 antenna = sc->sc_txantenna;
313 else if (sc->sc_stagbeacons && sc->sc_nbcnvaps != 0)
314 antenna = ((sc->sc_stats.ast_be_xmit / sc->sc_nbcnvaps) & 4 ? 2 : 1);
315 else
316 antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1);
317 }
318
319 KASSERT(bf->bf_nseg == 1,
320 ("multi-segment beacon frame; nseg %u", bf->bf_nseg));
321
322 /*
323 * Calculate rate code.
324 * XXX everything at min xmit rate
325 */
326 rix = 0;
327 rt = sc->sc_currates;
328 rate = rt->info[rix].rateCode;
329 if (USE_SHPREAMBLE(ic))
330 rate |= rt->info[rix].shortPreamble;
331 ath_hal_setuptxdesc(ah, ds
332 , m->m_len + IEEE80211_CRC_LEN /* frame length */
333 , sizeof(struct ieee80211_frame)/* header length */
334 , HAL_PKT_TYPE_BEACON /* Atheros packet type */
335 , ieee80211_get_node_txpower(ni) /* txpower XXX */
336 , rate, 1 /* series 0 rate/tries */
337 , HAL_TXKEYIX_INVALID /* no encryption */
338 , antenna /* antenna mode */
339 , flags /* no ack, veol for beacons */
340 , 0 /* rts/cts rate */
341 , 0 /* rts/cts duration */
342 );
343
344 /*
345 * The EDMA HAL currently assumes that _all_ rate control
346 * settings are done in ath_hal_set11nratescenario(), rather
347 * than in ath_hal_setuptxdesc().
348 */
349 if (sc->sc_isedma) {
350 memset(&rc, 0, sizeof(rc));
351
352 rc[0].ChSel = sc->sc_txchainmask;
353 rc[0].Tries = 1;
354 rc[0].Rate = rt->info[rix].rateCode;
355 rc[0].RateIndex = rix;
356 rc[0].tx_power_cap = 0x3f;
357 rc[0].PktDuration =
358 ath_hal_computetxtime(ah, rt, roundup(m->m_len, 4),
359 rix, 0);
360 ath_hal_set11nratescenario(ah, ds, 0, 0, rc, 4, flags);
361 }
362
363 /* NB: beacon's BufLen must be a multiple of 4 bytes */
364 segLenList[0] = roundup(m->m_len, 4);
365 segLenList[1] = segLenList[2] = segLenList[3] = 0;
366 bufAddrList[0] = bf->bf_segs[0].ds_addr;
367 bufAddrList[1] = bufAddrList[2] = bufAddrList[3] = 0;
368 ath_hal_filltxdesc(ah, ds
369 , bufAddrList
370 , segLenList
371 , 0 /* XXX desc id */
372 , sc->sc_bhalq /* hardware TXQ */
373 , AH_TRUE /* first segment */
374 , AH_TRUE /* last segment */
375 , ds /* first descriptor */
376 );
377 #if 0
378 ath_desc_swap(ds);
379 #endif
380 #undef USE_SHPREAMBLE
381 }
382
383 void
ath_beacon_update(struct ieee80211vap * vap,int item)384 ath_beacon_update(struct ieee80211vap *vap, int item)
385 {
386 struct ieee80211_beacon_offsets *bo = &vap->iv_bcn_off;
387
388 setbit(bo->bo_flags, item);
389 }
390
391 /*
392 * Handle a beacon miss.
393 */
394 void
ath_beacon_miss(struct ath_softc * sc)395 ath_beacon_miss(struct ath_softc *sc)
396 {
397 HAL_SURVEY_SAMPLE hs;
398 HAL_BOOL ret;
399 uint32_t hangs;
400
401 bzero(&hs, sizeof(hs));
402
403 ret = ath_hal_get_mib_cycle_counts(sc->sc_ah, &hs);
404
405 if (ath_hal_gethangstate(sc->sc_ah, 0xffff, &hangs) && hangs != 0) {
406 DPRINTF(sc, ATH_DEBUG_BEACON,
407 "%s: hang=0x%08x\n",
408 __func__,
409 hangs);
410 }
411
412 #ifdef ATH_DEBUG_ALQ
413 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_MISSED_BEACON))
414 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_MISSED_BEACON, 0, NULL);
415 #endif
416
417 DPRINTF(sc, ATH_DEBUG_BEACON,
418 "%s: valid=%d, txbusy=%u, rxbusy=%u, chanbusy=%u, "
419 "extchanbusy=%u, cyclecount=%u\n",
420 __func__,
421 ret,
422 hs.tx_busy,
423 hs.rx_busy,
424 hs.chan_busy,
425 hs.ext_chan_busy,
426 hs.cycle_count);
427 }
428
429 /*
430 * Transmit a beacon frame at SWBA. Dynamic updates to the
431 * frame contents are done as needed and the slot time is
432 * also adjusted based on current state.
433 */
434 void
ath_beacon_proc(void * arg,int pending)435 ath_beacon_proc(void *arg, int pending)
436 {
437 struct ath_softc *sc = arg;
438 struct ath_hal *ah = sc->sc_ah;
439 struct ieee80211vap *vap;
440 struct ath_buf *bf;
441 int slot, otherant;
442 uint32_t bfaddr;
443
444 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n",
445 __func__, pending);
446 /*
447 * Check if the previous beacon has gone out. If
448 * not don't try to post another, skip this period
449 * and wait for the next. Missed beacons indicate
450 * a problem and should not occur. If we miss too
451 * many consecutive beacons reset the device.
452 */
453 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) {
454 sc->sc_bmisscount++;
455 sc->sc_stats.ast_be_missed++;
456 ath_beacon_miss(sc);
457 DPRINTF(sc, ATH_DEBUG_BEACON,
458 "%s: missed %u consecutive beacons\n",
459 __func__, sc->sc_bmisscount);
460 if (sc->sc_bmisscount >= ath_bstuck_threshold)
461 taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask);
462 return;
463 }
464 if (sc->sc_bmisscount != 0) {
465 DPRINTF(sc, ATH_DEBUG_BEACON,
466 "%s: resume beacon xmit after %u misses\n",
467 __func__, sc->sc_bmisscount);
468 sc->sc_bmisscount = 0;
469 #ifdef ATH_DEBUG_ALQ
470 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_RESUME_BEACON))
471 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_RESUME_BEACON, 0, NULL);
472 #endif
473 }
474
475 if (sc->sc_stagbeacons) { /* staggered beacons */
476 struct ieee80211com *ic = &sc->sc_ic;
477 uint32_t tsftu;
478
479 tsftu = ath_hal_gettsf32(ah) >> 10;
480 /* XXX lintval */
481 slot = ((tsftu % ic->ic_lintval) * ATH_BCBUF) / ic->ic_lintval;
482 vap = sc->sc_bslot[(slot+1) % ATH_BCBUF];
483 bfaddr = 0;
484 if (vap != NULL && vap->iv_state >= IEEE80211_S_RUN) {
485 bf = ath_beacon_generate(sc, vap);
486 if (bf != NULL)
487 bfaddr = bf->bf_daddr;
488 }
489 } else { /* burst'd beacons */
490 uint32_t *bflink = &bfaddr;
491
492 for (slot = 0; slot < ATH_BCBUF; slot++) {
493 vap = sc->sc_bslot[slot];
494 if (vap != NULL && vap->iv_state >= IEEE80211_S_RUN) {
495 bf = ath_beacon_generate(sc, vap);
496 /*
497 * XXX TODO: this should use settxdesclinkptr()
498 * otherwise it won't work for EDMA chipsets!
499 */
500 if (bf != NULL) {
501 /* XXX should do this using the ds */
502 *bflink = bf->bf_daddr;
503 ath_hal_gettxdesclinkptr(sc->sc_ah,
504 bf->bf_desc, &bflink);
505 }
506 }
507 }
508 /*
509 * XXX TODO: this should use settxdesclinkptr()
510 * otherwise it won't work for EDMA chipsets!
511 */
512 *bflink = 0; /* terminate list */
513 }
514
515 /*
516 * Handle slot time change when a non-ERP station joins/leaves
517 * an 11g network. The 802.11 layer notifies us via callback,
518 * we mark updateslot, then wait one beacon before effecting
519 * the change. This gives associated stations at least one
520 * beacon interval to note the state change.
521 */
522 /* XXX locking */
523 if (sc->sc_updateslot == UPDATE) {
524 sc->sc_updateslot = COMMIT; /* commit next beacon */
525 sc->sc_slotupdate = slot;
526 } else if (sc->sc_updateslot == COMMIT && sc->sc_slotupdate == slot)
527 ath_setslottime(sc); /* commit change to h/w */
528
529 /*
530 * Check recent per-antenna transmit statistics and flip
531 * the default antenna if noticeably more frames went out
532 * on the non-default antenna.
533 * XXX assumes 2 anntenae
534 */
535 if (!sc->sc_diversity && (!sc->sc_stagbeacons || slot == 0)) {
536 otherant = sc->sc_defant & 1 ? 2 : 1;
537 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2)
538 ath_setdefantenna(sc, otherant);
539 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0;
540 }
541
542 /* Program the CABQ with the contents of the CABQ txq and start it */
543 ATH_TXQ_LOCK(sc->sc_cabq);
544 ath_beacon_cabq_start(sc);
545 ATH_TXQ_UNLOCK(sc->sc_cabq);
546
547 /* Program the new beacon frame if we have one for this interval */
548 if (bfaddr != 0) {
549 /*
550 * Stop any current dma and put the new frame on the queue.
551 * This should never fail since we check above that no frames
552 * are still pending on the queue.
553 */
554 if (! sc->sc_isedma) {
555 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) {
556 DPRINTF(sc, ATH_DEBUG_ANY,
557 "%s: beacon queue %u did not stop?\n",
558 __func__, sc->sc_bhalq);
559 }
560 }
561 /* NB: cabq traffic should already be queued and primed */
562
563 ath_hal_puttxbuf(ah, sc->sc_bhalq, bfaddr);
564 ath_hal_txstart(ah, sc->sc_bhalq);
565
566 sc->sc_stats.ast_be_xmit++;
567 }
568 }
569
570 static void
ath_beacon_cabq_start_edma(struct ath_softc * sc)571 ath_beacon_cabq_start_edma(struct ath_softc *sc)
572 {
573 struct ath_buf *bf, *bf_last;
574 struct ath_txq *cabq = sc->sc_cabq;
575 #if 0
576 struct ath_buf *bfi;
577 int i = 0;
578 #endif
579
580 ATH_TXQ_LOCK_ASSERT(cabq);
581
582 if (TAILQ_EMPTY(&cabq->axq_q))
583 return;
584 bf = TAILQ_FIRST(&cabq->axq_q);
585 bf_last = TAILQ_LAST(&cabq->axq_q, axq_q_s);
586
587 /*
588 * This is a dirty, dirty hack to push the contents of
589 * the cabq staging queue into the FIFO.
590 *
591 * This ideally should live in the EDMA code file
592 * and only push things into the CABQ if there's a FIFO
593 * slot.
594 *
595 * We can't treat this like a normal TX queue because
596 * in the case of multi-VAP traffic, we may have to flush
597 * the CABQ each new (staggered) beacon that goes out.
598 * But for non-staggered beacons, we could in theory
599 * handle multicast traffic for all VAPs in one FIFO
600 * push. Just keep all of this in mind if you're wondering
601 * how to correctly/better handle multi-VAP CABQ traffic
602 * with EDMA.
603 */
604
605 /*
606 * Is the CABQ FIFO free? If not, complain loudly and
607 * don't queue anything. Maybe we'll flush the CABQ
608 * traffic, maybe we won't. But that'll happen next
609 * beacon interval.
610 */
611 if (cabq->axq_fifo_depth >= HAL_TXFIFO_DEPTH) {
612 device_printf(sc->sc_dev,
613 "%s: Q%d: CAB FIFO queue=%d?\n",
614 __func__,
615 cabq->axq_qnum,
616 cabq->axq_fifo_depth);
617 return;
618 }
619
620 /*
621 * Ok, so here's the gymnastics reqiured to make this
622 * all sensible.
623 */
624
625 /*
626 * Tag the first/last buffer appropriately.
627 */
628 bf->bf_flags |= ATH_BUF_FIFOPTR;
629 bf_last->bf_flags |= ATH_BUF_FIFOEND;
630
631 #if 0
632 i = 0;
633 TAILQ_FOREACH(bfi, &cabq->axq_q, bf_list) {
634 ath_printtxbuf(sc, bf, cabq->axq_qnum, i, 0);
635 i++;
636 }
637 #endif
638
639 /*
640 * We now need to push this set of frames onto the tail
641 * of the FIFO queue. We don't adjust the aggregate
642 * count, only the queue depth counter(s).
643 * We also need to blank the link pointer now.
644 */
645 TAILQ_CONCAT(&cabq->fifo.axq_q, &cabq->axq_q, bf_list);
646 cabq->axq_link = NULL;
647 cabq->fifo.axq_depth += cabq->axq_depth;
648 cabq->axq_depth = 0;
649
650 /* Bump FIFO queue */
651 cabq->axq_fifo_depth++;
652
653 /* Push the first entry into the hardware */
654 ath_hal_puttxbuf(sc->sc_ah, cabq->axq_qnum, bf->bf_daddr);
655 cabq->axq_flags |= ATH_TXQ_PUTRUNNING;
656
657 /* NB: gated by beacon so safe to start here */
658 ath_hal_txstart(sc->sc_ah, cabq->axq_qnum);
659
660 }
661
662 static void
ath_beacon_cabq_start_legacy(struct ath_softc * sc)663 ath_beacon_cabq_start_legacy(struct ath_softc *sc)
664 {
665 struct ath_buf *bf;
666 struct ath_txq *cabq = sc->sc_cabq;
667
668 ATH_TXQ_LOCK_ASSERT(cabq);
669 if (TAILQ_EMPTY(&cabq->axq_q))
670 return;
671 bf = TAILQ_FIRST(&cabq->axq_q);
672
673 /* Push the first entry into the hardware */
674 ath_hal_puttxbuf(sc->sc_ah, cabq->axq_qnum, bf->bf_daddr);
675 cabq->axq_flags |= ATH_TXQ_PUTRUNNING;
676
677 /* NB: gated by beacon so safe to start here */
678 ath_hal_txstart(sc->sc_ah, cabq->axq_qnum);
679 }
680
681 /*
682 * Start CABQ transmission - this assumes that all frames are prepped
683 * and ready in the CABQ.
684 */
685 void
ath_beacon_cabq_start(struct ath_softc * sc)686 ath_beacon_cabq_start(struct ath_softc *sc)
687 {
688 struct ath_txq *cabq = sc->sc_cabq;
689
690 ATH_TXQ_LOCK_ASSERT(cabq);
691
692 if (TAILQ_EMPTY(&cabq->axq_q))
693 return;
694
695 if (sc->sc_isedma)
696 ath_beacon_cabq_start_edma(sc);
697 else
698 ath_beacon_cabq_start_legacy(sc);
699 }
700
701 struct ath_buf *
ath_beacon_generate(struct ath_softc * sc,struct ieee80211vap * vap)702 ath_beacon_generate(struct ath_softc *sc, struct ieee80211vap *vap)
703 {
704 struct ath_vap *avp = ATH_VAP(vap);
705 struct ath_txq *cabq = sc->sc_cabq;
706 struct ath_buf *bf;
707 struct mbuf *m;
708 int nmcastq, error;
709
710 KASSERT(vap->iv_state >= IEEE80211_S_RUN,
711 ("not running, state %d", vap->iv_state));
712 KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer"));
713
714 /*
715 * Update dynamic beacon contents. If this returns
716 * non-zero then we need to remap the memory because
717 * the beacon frame changed size (probably because
718 * of the TIM bitmap).
719 */
720 bf = avp->av_bcbuf;
721 m = bf->bf_m;
722 /* XXX lock mcastq? */
723 nmcastq = avp->av_mcastq.axq_depth;
724
725 if (ieee80211_beacon_update(bf->bf_node, m, nmcastq)) {
726 /* XXX too conservative? */
727 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
728 #if defined(__DragonFly__)
729 error = bus_dmamap_load_mbuf_segment(sc->sc_dmat,
730 bf->bf_dmamap, m,
731 bf->bf_segs, 1, &bf->bf_nseg,
732 BUS_DMA_NOWAIT);
733 #else
734 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m,
735 bf->bf_segs, &bf->bf_nseg,
736 BUS_DMA_NOWAIT);
737 #endif
738 if (error != 0) {
739 if_printf(vap->iv_ifp,
740 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n",
741 __func__, error);
742 return NULL;
743 }
744 }
745 if ((vap->iv_bcn_off.bo_tim[4] & 1) && cabq->axq_depth) {
746 DPRINTF(sc, ATH_DEBUG_BEACON,
747 "%s: cabq did not drain, mcastq %u cabq %u\n",
748 __func__, nmcastq, cabq->axq_depth);
749 sc->sc_stats.ast_cabq_busy++;
750 if (sc->sc_nvaps > 1 && sc->sc_stagbeacons) {
751 /*
752 * CABQ traffic from a previous vap is still pending.
753 * We must drain the q before this beacon frame goes
754 * out as otherwise this vap's stations will get cab
755 * frames from a different vap.
756 * XXX could be slow causing us to miss DBA
757 */
758 /*
759 * XXX TODO: this doesn't stop CABQ DMA - it assumes
760 * that since we're about to transmit a beacon, we've
761 * already stopped transmitting on the CABQ. But this
762 * doesn't at all mean that the CABQ DMA QCU will
763 * accept a new TXDP! So what, should we do a DMA
764 * stop? What if it fails?
765 *
766 * More thought is required here.
767 */
768 /*
769 * XXX can we even stop TX DMA here? Check what the
770 * reference driver does for cabq for beacons, given
771 * that stopping TX requires RX is paused.
772 */
773 ath_tx_draintxq(sc, cabq);
774 }
775 }
776 ath_beacon_setup(sc, bf);
777 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE);
778
779 /*
780 * Enable the CAB queue before the beacon queue to
781 * insure cab frames are triggered by this beacon.
782 */
783 if (vap->iv_bcn_off.bo_tim[4] & 1) {
784
785 /* NB: only at DTIM */
786 ATH_TXQ_LOCK(&avp->av_mcastq);
787 if (nmcastq) {
788 struct ath_buf *bfm, *bfc_last;
789
790 /*
791 * Move frames from the s/w mcast q to the h/w cab q.
792 *
793 * XXX TODO: if we chain together multiple VAPs
794 * worth of CABQ traffic, should we keep the
795 * MORE data bit set on the last frame of each
796 * intermediary VAP (ie, only clear the MORE
797 * bit of the last frame on the last vap?)
798 */
799 bfm = TAILQ_FIRST(&avp->av_mcastq.axq_q);
800 ATH_TXQ_LOCK(cabq);
801
802 /*
803 * If there's already a frame on the CABQ, we
804 * need to link to the end of the last frame.
805 * We can't use axq_link here because
806 * EDMA descriptors require some recalculation
807 * (checksum) to occur.
808 */
809 bfc_last = ATH_TXQ_LAST(cabq, axq_q_s);
810 if (bfc_last != NULL) {
811 ath_hal_settxdesclink(sc->sc_ah,
812 bfc_last->bf_lastds,
813 bfm->bf_daddr);
814 }
815 ath_txqmove(cabq, &avp->av_mcastq);
816 ATH_TXQ_UNLOCK(cabq);
817 /*
818 * XXX not entirely accurate, in case a mcast
819 * queue frame arrived before we grabbed the TX
820 * lock.
821 */
822 sc->sc_stats.ast_cabq_xmit += nmcastq;
823 }
824 ATH_TXQ_UNLOCK(&avp->av_mcastq);
825 }
826 return bf;
827 }
828
829 void
ath_beacon_start_adhoc(struct ath_softc * sc,struct ieee80211vap * vap)830 ath_beacon_start_adhoc(struct ath_softc *sc, struct ieee80211vap *vap)
831 {
832 struct ath_vap *avp = ATH_VAP(vap);
833 struct ath_hal *ah = sc->sc_ah;
834 struct ath_buf *bf;
835 struct mbuf *m;
836 int error;
837
838 KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer"));
839
840 /*
841 * Update dynamic beacon contents. If this returns
842 * non-zero then we need to remap the memory because
843 * the beacon frame changed size (probably because
844 * of the TIM bitmap).
845 */
846 bf = avp->av_bcbuf;
847 m = bf->bf_m;
848 if (ieee80211_beacon_update(bf->bf_node, m, 0)) {
849 /* XXX too conservative? */
850 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
851 #if defined(__DragonFly__)
852 error = bus_dmamap_load_mbuf_segment(sc->sc_dmat,
853 bf->bf_dmamap, m,
854 bf->bf_segs, 1, &bf->bf_nseg,
855 BUS_DMA_NOWAIT);
856 #else
857 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m,
858 bf->bf_segs, &bf->bf_nseg,
859 BUS_DMA_NOWAIT);
860 #endif
861 if (error != 0) {
862 if_printf(vap->iv_ifp,
863 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n",
864 __func__, error);
865 return;
866 }
867 }
868 ath_beacon_setup(sc, bf);
869 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE);
870
871 /* NB: caller is known to have already stopped tx dma */
872 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr);
873 ath_hal_txstart(ah, sc->sc_bhalq);
874 }
875
876 /*
877 * Reclaim beacon resources and return buffer to the pool.
878 */
879 void
ath_beacon_return(struct ath_softc * sc,struct ath_buf * bf)880 ath_beacon_return(struct ath_softc *sc, struct ath_buf *bf)
881 {
882
883 DPRINTF(sc, ATH_DEBUG_NODE, "%s: free bf=%p, bf_m=%p, bf_node=%p\n",
884 __func__, bf, bf->bf_m, bf->bf_node);
885 if (bf->bf_m != NULL) {
886 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
887 m_freem(bf->bf_m);
888 bf->bf_m = NULL;
889 }
890 if (bf->bf_node != NULL) {
891 ieee80211_free_node(bf->bf_node);
892 bf->bf_node = NULL;
893 }
894 TAILQ_INSERT_TAIL(&sc->sc_bbuf, bf, bf_list);
895 }
896
897 /*
898 * Reclaim beacon resources.
899 */
900 void
ath_beacon_free(struct ath_softc * sc)901 ath_beacon_free(struct ath_softc *sc)
902 {
903 struct ath_buf *bf;
904
905 TAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) {
906 DPRINTF(sc, ATH_DEBUG_NODE,
907 "%s: free bf=%p, bf_m=%p, bf_node=%p\n",
908 __func__, bf, bf->bf_m, bf->bf_node);
909 if (bf->bf_m != NULL) {
910 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
911 m_freem(bf->bf_m);
912 bf->bf_m = NULL;
913 }
914 if (bf->bf_node != NULL) {
915 ieee80211_free_node(bf->bf_node);
916 bf->bf_node = NULL;
917 }
918 }
919 }
920
921 /*
922 * Configure the beacon and sleep timers.
923 *
924 * When operating as an AP this resets the TSF and sets
925 * up the hardware to notify us when we need to issue beacons.
926 *
927 * When operating in station mode this sets up the beacon
928 * timers according to the timestamp of the last received
929 * beacon and the current TSF, configures PCF and DTIM
930 * handling, programs the sleep registers so the hardware
931 * will wakeup in time to receive beacons, and configures
932 * the beacon miss handling so we'll receive a BMISS
933 * interrupt when we stop seeing beacons from the AP
934 * we've associated with.
935 */
936 void
ath_beacon_config(struct ath_softc * sc,struct ieee80211vap * vap)937 ath_beacon_config(struct ath_softc *sc, struct ieee80211vap *vap)
938 {
939 #define TSF_TO_TU(_h,_l) \
940 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10))
941 #define FUDGE 2
942 struct ath_hal *ah = sc->sc_ah;
943 struct ieee80211com *ic = &sc->sc_ic;
944 struct ieee80211_node *ni;
945 u_int32_t nexttbtt, intval, tsftu;
946 u_int32_t nexttbtt_u8, intval_u8;
947 u_int64_t tsf, tsf_beacon;
948
949 if (vap == NULL)
950 vap = TAILQ_FIRST(&ic->ic_vaps); /* XXX */
951 /*
952 * Just ensure that we aren't being called when the last
953 * VAP is destroyed.
954 */
955 if (vap == NULL) {
956 device_printf(sc->sc_dev, "%s: called with no VAPs\n",
957 __func__);
958 return;
959 }
960
961 ni = ieee80211_ref_node(vap->iv_bss);
962
963 ATH_LOCK(sc);
964 ath_power_set_power_state(sc, HAL_PM_AWAKE);
965 ATH_UNLOCK(sc);
966
967 /* extract tstamp from last beacon and convert to TU */
968 nexttbtt = TSF_TO_TU(le32dec(ni->ni_tstamp.data + 4),
969 le32dec(ni->ni_tstamp.data));
970
971 tsf_beacon = ((uint64_t) le32dec(ni->ni_tstamp.data + 4)) << 32;
972 tsf_beacon |= le32dec(ni->ni_tstamp.data);
973
974 if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
975 ic->ic_opmode == IEEE80211_M_MBSS) {
976 /*
977 * For multi-bss ap/mesh support beacons are either staggered
978 * evenly over N slots or burst together. For the former
979 * arrange for the SWBA to be delivered for each slot.
980 * Slots that are not occupied will generate nothing.
981 */
982 /* NB: the beacon interval is kept internally in TU's */
983 intval = ni->ni_intval & HAL_BEACON_PERIOD;
984 if (sc->sc_stagbeacons)
985 intval /= ATH_BCBUF;
986 } else {
987 /* NB: the beacon interval is kept internally in TU's */
988 intval = ni->ni_intval & HAL_BEACON_PERIOD;
989 }
990 if (nexttbtt == 0) /* e.g. for ap mode */
991 nexttbtt = intval;
992 else if (intval) /* NB: can be 0 for monitor mode */
993 nexttbtt = roundup(nexttbtt, intval);
994 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n",
995 __func__, nexttbtt, intval, ni->ni_intval);
996 if (ic->ic_opmode == IEEE80211_M_STA && !sc->sc_swbmiss) {
997 HAL_BEACON_STATE bs;
998 int dtimperiod, dtimcount;
999 int cfpperiod, cfpcount;
1000
1001 /*
1002 * Setup dtim and cfp parameters according to
1003 * last beacon we received (which may be none).
1004 */
1005 dtimperiod = ni->ni_dtim_period;
1006 if (dtimperiod <= 0) /* NB: 0 if not known */
1007 dtimperiod = 1;
1008 dtimcount = ni->ni_dtim_count;
1009 if (dtimcount >= dtimperiod) /* NB: sanity check */
1010 dtimcount = 0; /* XXX? */
1011 cfpperiod = 1; /* NB: no PCF support yet */
1012 cfpcount = 0;
1013 /*
1014 * Pull nexttbtt forward to reflect the current
1015 * TSF and calculate dtim+cfp state for the result.
1016 */
1017 tsf = ath_hal_gettsf64(ah);
1018 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE;
1019
1020 DPRINTF(sc, ATH_DEBUG_BEACON,
1021 "%s: beacon tsf=%llu, hw tsf=%llu, nexttbtt=%u, tsftu=%u\n",
1022 __func__,
1023 (unsigned long long) tsf_beacon,
1024 (unsigned long long) tsf,
1025 nexttbtt,
1026 tsftu);
1027 DPRINTF(sc, ATH_DEBUG_BEACON,
1028 "%s: beacon tsf=%llu, hw tsf=%llu, tsf delta=%lld\n",
1029 __func__,
1030 (unsigned long long) tsf_beacon,
1031 (unsigned long long) tsf,
1032 (long long) tsf -
1033 (long long) tsf_beacon);
1034
1035 DPRINTF(sc, ATH_DEBUG_BEACON,
1036 "%s: nexttbtt=%llu, beacon tsf delta=%lld\n",
1037 __func__,
1038 (unsigned long long) nexttbtt,
1039 (long long) ((long long) nexttbtt * 1024LL) - (long long) tsf_beacon);
1040
1041 /* XXX cfpcount? */
1042
1043 if (nexttbtt > tsftu) {
1044 uint32_t countdiff, oldtbtt, remainder;
1045
1046 oldtbtt = nexttbtt;
1047 remainder = (nexttbtt - tsftu) % intval;
1048 nexttbtt = tsftu + remainder;
1049
1050 countdiff = (oldtbtt - nexttbtt) / intval % dtimperiod;
1051 if (dtimcount > countdiff) {
1052 dtimcount -= countdiff;
1053 } else {
1054 dtimcount += dtimperiod - countdiff;
1055 }
1056 } else { //nexttbtt <= tsftu
1057 uint32_t countdiff, oldtbtt, remainder;
1058
1059 oldtbtt = nexttbtt;
1060 remainder = (tsftu - nexttbtt) % intval;
1061 nexttbtt = tsftu - remainder + intval;
1062 countdiff = (nexttbtt - oldtbtt) / intval % dtimperiod;
1063 if (dtimcount > countdiff) {
1064 dtimcount -= countdiff;
1065 } else {
1066 dtimcount += dtimperiod - countdiff;
1067 }
1068 }
1069
1070 DPRINTF(sc, ATH_DEBUG_BEACON,
1071 "%s: adj nexttbtt=%llu, rx tsf delta=%lld\n",
1072 __func__,
1073 (unsigned long long) nexttbtt,
1074 (long long) ((long long)nexttbtt * 1024LL) - (long long)tsf);
1075
1076 memset(&bs, 0, sizeof(bs));
1077 bs.bs_intval = intval;
1078 bs.bs_nexttbtt = nexttbtt;
1079 bs.bs_dtimperiod = dtimperiod*intval;
1080 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval;
1081 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod;
1082 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod;
1083 bs.bs_cfpmaxduration = 0;
1084 #if 0
1085 /*
1086 * The 802.11 layer records the offset to the DTIM
1087 * bitmap while receiving beacons; use it here to
1088 * enable h/w detection of our AID being marked in
1089 * the bitmap vector (to indicate frames for us are
1090 * pending at the AP).
1091 * XXX do DTIM handling in s/w to WAR old h/w bugs
1092 * XXX enable based on h/w rev for newer chips
1093 */
1094 bs.bs_timoffset = ni->ni_timoff;
1095 #endif
1096 /*
1097 * Calculate the number of consecutive beacons to miss
1098 * before taking a BMISS interrupt.
1099 * Note that we clamp the result to at most 10 beacons.
1100 */
1101 bs.bs_bmissthreshold = vap->iv_bmissthreshold;
1102 if (bs.bs_bmissthreshold > 10)
1103 bs.bs_bmissthreshold = 10;
1104 else if (bs.bs_bmissthreshold <= 0)
1105 bs.bs_bmissthreshold = 1;
1106
1107 /*
1108 * Calculate sleep duration. The configuration is
1109 * given in ms. We insure a multiple of the beacon
1110 * period is used. Also, if the sleep duration is
1111 * greater than the DTIM period then it makes senses
1112 * to make it a multiple of that.
1113 *
1114 * XXX fixed at 100ms
1115 */
1116 bs.bs_sleepduration =
1117 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval);
1118 if (bs.bs_sleepduration > bs.bs_dtimperiod)
1119 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod);
1120
1121 DPRINTF(sc, ATH_DEBUG_BEACON,
1122 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u "
1123 "nextdtim %u bmiss %u sleep %u cfp:period %u "
1124 "maxdur %u next %u timoffset %u\n"
1125 , __func__
1126 , tsf
1127 , tsftu
1128 , bs.bs_intval
1129 , bs.bs_nexttbtt
1130 , bs.bs_dtimperiod
1131 , bs.bs_nextdtim
1132 , bs.bs_bmissthreshold
1133 , bs.bs_sleepduration
1134 , bs.bs_cfpperiod
1135 , bs.bs_cfpmaxduration
1136 , bs.bs_cfpnext
1137 , bs.bs_timoffset
1138 );
1139 ath_hal_intrset(ah, 0);
1140 ath_hal_beacontimers(ah, &bs);
1141 sc->sc_imask |= HAL_INT_BMISS;
1142 ath_hal_intrset(ah, sc->sc_imask);
1143 } else {
1144 ath_hal_intrset(ah, 0);
1145 if (nexttbtt == intval)
1146 intval |= HAL_BEACON_RESET_TSF;
1147 if (ic->ic_opmode == IEEE80211_M_IBSS) {
1148 /*
1149 * In IBSS mode enable the beacon timers but only
1150 * enable SWBA interrupts if we need to manually
1151 * prepare beacon frames. Otherwise we use a
1152 * self-linked tx descriptor and let the hardware
1153 * deal with things.
1154 */
1155 intval |= HAL_BEACON_ENA;
1156 if (!sc->sc_hasveol)
1157 sc->sc_imask |= HAL_INT_SWBA;
1158 if ((intval & HAL_BEACON_RESET_TSF) == 0) {
1159 /*
1160 * Pull nexttbtt forward to reflect
1161 * the current TSF.
1162 */
1163 tsf = ath_hal_gettsf64(ah);
1164 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE;
1165 do {
1166 nexttbtt += intval;
1167 } while (nexttbtt < tsftu);
1168 }
1169 ath_beaconq_config(sc);
1170 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
1171 ic->ic_opmode == IEEE80211_M_MBSS) {
1172 /*
1173 * In AP/mesh mode we enable the beacon timers
1174 * and SWBA interrupts to prepare beacon frames.
1175 */
1176 intval |= HAL_BEACON_ENA;
1177 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */
1178 ath_beaconq_config(sc);
1179 }
1180
1181 /*
1182 * Now dirty things because for now, the EDMA HAL has
1183 * nexttbtt and intval is TU/8.
1184 */
1185 if (sc->sc_isedma) {
1186 nexttbtt_u8 = (nexttbtt << 3);
1187 intval_u8 = (intval << 3);
1188 if (intval & HAL_BEACON_ENA)
1189 intval_u8 |= HAL_BEACON_ENA;
1190 if (intval & HAL_BEACON_RESET_TSF)
1191 intval_u8 |= HAL_BEACON_RESET_TSF;
1192 ath_hal_beaconinit(ah, nexttbtt_u8, intval_u8);
1193 } else
1194 ath_hal_beaconinit(ah, nexttbtt, intval);
1195 sc->sc_bmisscount = 0;
1196 ath_hal_intrset(ah, sc->sc_imask);
1197 /*
1198 * When using a self-linked beacon descriptor in
1199 * ibss mode load it once here.
1200 */
1201 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol)
1202 ath_beacon_start_adhoc(sc, vap);
1203 }
1204 ieee80211_free_node(ni);
1205
1206 ATH_LOCK(sc);
1207 ath_power_restore_power_state(sc);
1208 ATH_UNLOCK(sc);
1209 #undef FUDGE
1210 #undef TSF_TO_TU
1211 }
1212