1 /*-
2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27 /* local prototypes */
28 static int ata_cmd_allocate(device_t dev);
29 static int ata_cmd_status(device_t dev);
30 static void ata_cmd_setmode(device_t dev, int mode);
31 static int ata_sii_allocate(device_t dev);
32 static int ata_sii_status(device_t dev);
33 static void ata_sii_reset(device_t dev);
34 static void ata_sii_setmode(device_t dev, int mode);
35 static int ata_siiprb_allocate(device_t dev);
36 static int ata_siiprb_status(device_t dev);
37 static int ata_siiprb_begin_transaction(struct ata_request *request);
38 static int ata_siiprb_end_transaction(struct ata_request *request);
39 static u_int32_t ata_siiprb_softreset(device_t dev, int port);
40 static void ata_siiprb_reset(device_t dev);
41 static void ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
42 static void ata_siiprb_dmainit(device_t dev);
43
44 /* misc defines */
45 #undef SII_MEMIO
46 #define SII_MEMIO 1
47 #define SII_PRBIO 2
48 #define SII_INTR 0x01
49 #define SII_SETCLK 0x02
50 #define SII_BUG 0x04
51 #define SII_4CH 0x08
52
53 /*
54 * Silicon Image Inc. (SiI) (former CMD) chipset support functions
55 */
56 int
ata_sii_ident(device_t dev)57 ata_sii_ident(device_t dev)
58 {
59 struct ata_pci_controller *ctlr = device_get_softc(dev);
60 static const struct ata_chip_id ids[] =
61 {{ ATA_SII3114, 0x00, SII_MEMIO, SII_4CH, ATA_SA150, "SiI 3114" },
62 { ATA_SII3512, 0x02, SII_MEMIO, 0, ATA_SA150, "SiI 3512" },
63 { ATA_SII3112, 0x02, SII_MEMIO, 0, ATA_SA150, "SiI 3112" },
64 { ATA_SII3112_1, 0x02, SII_MEMIO, 0, ATA_SA150, "SiI 3112" },
65 { ATA_SII3512, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "SiI 3512" },
66 { ATA_SII3112, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "SiI 3112" },
67 { ATA_SII3112_1, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "SiI 3112" },
68 { ATA_SII3124, 0x00, SII_PRBIO, SII_4CH, ATA_SA300, "SiI 3124" },
69 { ATA_SII3132, 0x00, SII_PRBIO, 0, ATA_SA300, "SiI 3132" },
70 { ATA_SII3132_1, 0x00, SII_PRBIO, 0, ATA_SA300, "SiI 3132" },
71 { ATA_SII3132_2, 0x00, SII_PRBIO, 0, ATA_SA300, "SiI 3132" },
72 { ATA_SII0680, 0x00, SII_MEMIO, SII_SETCLK, ATA_UDMA6, "SiI 0680" },
73 { ATA_CMD649, 0x00, 0, SII_INTR, ATA_UDMA5, "CMD 649" },
74 { ATA_CMD648, 0x00, 0, SII_INTR, ATA_UDMA4, "CMD 648" },
75 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "CMD 646U2" },
76 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "CMD 646" },
77 { 0, 0, 0, 0, 0, 0}};
78
79 if (pci_get_vendor(dev) != ATA_SILICON_IMAGE_ID)
80 return ENXIO;
81
82 if (!(ctlr->chip = ata_match_chip(dev, ids)))
83 return ENXIO;
84
85 ata_set_desc(dev);
86 ctlr->chipinit = ata_sii_chipinit;
87 return 0;
88 }
89
90 static int
ata_sii_chipinit(device_t dev)91 ata_sii_chipinit(device_t dev)
92 {
93 struct ata_pci_controller *ctlr = device_get_softc(dev);
94
95 if (ata_setup_interrupt(dev, ata_generic_intr))
96 return ENXIO;
97
98 switch (ctlr->chip->cfg1) {
99 case SII_PRBIO:
100 ctlr->r_type1 = SYS_RES_MEMORY;
101 ctlr->r_rid1 = PCIR_BAR(0);
102 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
103 &ctlr->r_rid1, RF_ACTIVE))){
104 ata_teardown_interrupt(dev);
105 return ENXIO;
106 }
107
108 ctlr->r_rid2 = PCIR_BAR(2);
109 ctlr->r_type2 = SYS_RES_MEMORY;
110 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
111 &ctlr->r_rid2, RF_ACTIVE))){
112 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1);
113 ata_teardown_interrupt(dev);
114 return ENXIO;
115 }
116 ctlr->allocate = ata_siiprb_allocate;
117 ctlr->reset = ata_siiprb_reset;
118 ctlr->dmainit = ata_siiprb_dmainit;
119 ctlr->setmode = ata_sata_setmode;
120 ctlr->channels = (ctlr->chip->cfg2 == SII_4CH) ? 4 : 2;
121
122 /* reset controller */
123 ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000);
124 DELAY(10000);
125 ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f);
126
127 /* enable PCI interrupt */
128 pci_write_config(dev, PCIR_COMMAND,
129 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
130 break;
131
132 case SII_MEMIO:
133 ctlr->r_type2 = SYS_RES_MEMORY;
134 ctlr->r_rid2 = PCIR_BAR(5);
135 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
136 &ctlr->r_rid2, RF_ACTIVE))){
137 if (ctlr->chip->chipid != ATA_SII0680 ||
138 (pci_read_config(dev, 0x8a, 1) & 1)) {
139 ata_teardown_interrupt(dev);
140 return ENXIO;
141 }
142 }
143
144 if (ctlr->chip->cfg2 & SII_SETCLK) {
145 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
146 pci_write_config(dev, 0x8a,
147 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1);
148 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
149 device_printf(dev, "%s could not set ATA133 clock\n",
150 ctlr->chip->text);
151 }
152
153 /* if we have 4 channels enable the second set */
154 if (ctlr->chip->cfg2 & SII_4CH) {
155 ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002);
156 ctlr->channels = 4;
157 }
158
159 /* dont block interrupts from any channel */
160 pci_write_config(dev, 0x48,
161 (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4);
162
163 /* enable PCI interrupt as BIOS might not */
164 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1);
165
166 if (ctlr->r_res2)
167 ctlr->allocate = ata_sii_allocate;
168
169 if (ctlr->chip->max_dma >= ATA_SA150) {
170 ctlr->reset = ata_sii_reset;
171 ctlr->setmode = ata_sata_setmode;
172 }
173 else
174 ctlr->setmode = ata_sii_setmode;
175 break;
176
177 default:
178 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) {
179 device_printf(dev, "HW has secondary channel disabled\n");
180 ctlr->channels = 1;
181 }
182
183 /* enable interrupt as BIOS might not */
184 pci_write_config(dev, 0x71, 0x01, 1);
185
186 ctlr->allocate = ata_cmd_allocate;
187 ctlr->setmode = ata_cmd_setmode;
188 break;
189 }
190 return 0;
191 }
192
193 static int
ata_cmd_allocate(device_t dev)194 ata_cmd_allocate(device_t dev)
195 {
196 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
197 struct ata_channel *ch = device_get_softc(dev);
198
199 /* setup the usual register normal pci style */
200 if (ata_pci_allocate(dev))
201 return ENXIO;
202
203 if (ctlr->chip->cfg2 & SII_INTR)
204 ch->hw.status = ata_cmd_status;
205
206 return 0;
207 }
208
209 static int
ata_cmd_status(device_t dev)210 ata_cmd_status(device_t dev)
211 {
212 struct ata_channel *ch = device_get_softc(dev);
213 u_int8_t reg71;
214
215 if (((reg71 = pci_read_config(device_get_parent(ch->dev), 0x71, 1)) &
216 (ch->unit ? 0x08 : 0x04))) {
217 pci_write_config(device_get_parent(ch->dev), 0x71,
218 reg71 & ~(ch->unit ? 0x04 : 0x08), 1);
219 return ata_pci_status(dev);
220 }
221 return 0;
222 }
223
224 static void
ata_cmd_setmode(device_t dev,int mode)225 ata_cmd_setmode(device_t dev, int mode)
226 {
227 device_t gparent = GRANDPARENT(dev);
228 struct ata_pci_controller *ctlr = device_get_softc(gparent);
229 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
230 struct ata_device *atadev = device_get_softc(dev);
231 int devno = (ch->unit << 1) + atadev->unit;
232 int error;
233 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7);
234 int ureg = ch->unit ? 0x7b : 0x73;
235 static const uint8_t piotimings[] =
236 { 0xa9, 0x57, 0x44, 0x32, 0x3f };
237 static const uint8_t dmatimings[] = { 0x87, 0x32, 0x3f };
238 static const uint8_t udmatimings[][2] =
239 { { 0x31, 0xc2 }, { 0x21, 0x82 }, { 0x11, 0x42 },
240 { 0x25, 0x8a }, { 0x15, 0x4a }, { 0x05, 0x0a } };
241
242 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
243
244 mode = ata_check_80pin(dev, mode);
245
246 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
247
248 if (bootverbose)
249 device_printf(dev, "%ssetting %s on %s chip\n",
250 (error) ? "FAILURE " : "",
251 ata_mode2str(mode), ctlr->chip->text);
252 if (!error) {
253 if (mode >= ATA_UDMA0) {
254 u_int8_t umode = pci_read_config(gparent, ureg, 1);
255
256 umode &= ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca);
257 umode |= udmatimings[mode & ATA_MODE_MASK][atadev->unit];
258 pci_write_config(gparent, ureg, umode, 1);
259 }
260 else if (mode >= ATA_WDMA0) {
261 pci_write_config(gparent, treg, dmatimings[mode & ATA_MODE_MASK],1);
262 pci_write_config(gparent, ureg,
263 pci_read_config(gparent, ureg, 1) &
264 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1);
265 }
266 else {
267 pci_write_config(gparent, treg,
268 piotimings[(mode & ATA_MODE_MASK) - ATA_PIO0], 1);
269 pci_write_config(gparent, ureg,
270 pci_read_config(gparent, ureg, 1) &
271 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1);
272 }
273 atadev->mode = mode;
274 }
275 }
276
277 static int
ata_sii_allocate(device_t dev)278 ata_sii_allocate(device_t dev)
279 {
280 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
281 struct ata_channel *ch = device_get_softc(dev);
282 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
283 int i;
284
285 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
286 ch->r_io[i].res = ctlr->r_res2;
287 ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8);
288 }
289 ch->r_io[ATA_CONTROL].res = ctlr->r_res2;
290 ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8);
291 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
292 ata_default_registers(dev);
293
294 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2;
295 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8);
296 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2;
297 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8);
298 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2;
299 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8);
300
301 if (ctlr->chip->max_dma >= ATA_SA150) {
302 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
303 ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8);
304 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
305 ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8);
306 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
307 ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8);
308 ch->flags |= ATA_NO_SLAVE;
309
310 /* enable PHY state change interrupt */
311 ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16));
312 }
313
314 if ((ctlr->chip->cfg2 & SII_BUG) && ch->dma) {
315 /* work around errata in early chips */
316 ch->dma->boundary = 8192;
317 ch->dma->segsize = 15 * DEV_BSIZE;
318 }
319
320 ata_pci_hw(dev);
321 ch->hw.status = ata_sii_status;
322 return 0;
323 }
324
325 static int
ata_sii_status(device_t dev)326 ata_sii_status(device_t dev)
327 {
328 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
329 struct ata_channel *ch = device_get_softc(dev);
330 int offset0 = ((ch->unit & 1) << 3) + ((ch->unit & 2) << 8);
331 int offset1 = ((ch->unit & 1) << 6) + ((ch->unit & 2) << 8);
332
333 /* do we have any PHY events ? */
334 if (ctlr->chip->max_dma >= ATA_SA150 &&
335 (ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010))
336 ata_sata_phy_check_events(dev);
337
338 if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800)
339 return ata_pci_status(dev);
340 else
341 return 0;
342 }
343
344 static void
ata_sii_reset(device_t dev)345 ata_sii_reset(device_t dev)
346 {
347 if (ata_sata_phy_reset(dev))
348 ata_generic_reset(dev);
349 }
350
351 static void
ata_sii_setmode(device_t dev,int mode)352 ata_sii_setmode(device_t dev, int mode)
353 {
354 device_t gparent = GRANDPARENT(dev);
355 struct ata_pci_controller *ctlr = device_get_softc(gparent);
356 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
357 struct ata_device *atadev = device_get_softc(dev);
358 int rego = (ch->unit << 4) + (atadev->unit << 1);
359 int mreg = ch->unit ? 0x84 : 0x80;
360 int mask = 0x03 << (atadev->unit << 2);
361 int mval = pci_read_config(gparent, mreg, 1) & ~mask;
362 int error;
363 u_int8_t preg = 0xa4 + rego;
364 u_int8_t dreg = 0xa8 + rego;
365 u_int8_t ureg = 0xac + rego;
366 static const uint16_t piotimings[] =
367 { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
368 static const uint16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 };
369 static const uint8_t udmatimings[] =
370 { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 };
371
372 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
373
374 if (ctlr->chip->cfg2 & SII_SETCLK) {
375 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x79, 1) &
376 (ch->unit ? 0x02 : 0x01))) {
377 ata_print_cable(dev, "controller");
378 mode = ATA_UDMA2;
379 }
380 }
381 else
382 mode = ata_check_80pin(dev, mode);
383
384 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
385
386 if (bootverbose)
387 device_printf(dev, "%ssetting %s on %s chip\n",
388 (error) ? "FAILURE " : "",
389 ata_mode2str(mode), ctlr->chip->text);
390 if (error)
391 return;
392
393 if (mode >= ATA_UDMA0) {
394 pci_write_config(gparent, mreg,
395 mval | (0x03 << (atadev->unit << 2)), 1);
396 pci_write_config(gparent, ureg,
397 (pci_read_config(gparent, ureg, 1) & ~0x3f) |
398 udmatimings[mode & ATA_MODE_MASK], 1);
399
400 }
401 else if (mode >= ATA_WDMA0) {
402 pci_write_config(gparent, mreg,
403 mval | (0x02 << (atadev->unit << 2)), 1);
404 pci_write_config(gparent, dreg, dmatimings[mode & ATA_MODE_MASK], 2);
405
406 }
407 else {
408 pci_write_config(gparent, mreg,
409 mval | (0x01 << (atadev->unit << 2)), 1);
410 pci_write_config(gparent, preg, piotimings[mode & ATA_MODE_MASK], 2);
411 }
412 atadev->mode = mode;
413 }
414
415 struct ata_siiprb_dma_prdentry {
416 u_int64_t addr;
417 u_int32_t count;
418 u_int32_t control;
419 } __packed;
420
421 #define ATA_SIIPRB_DMA_ENTRIES 125
422 struct ata_siiprb_ata_command {
423 struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES];
424 } __packed;
425
426 struct ata_siiprb_atapi_command {
427 u_int8_t ccb[16];
428 struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES];
429 } __packed;
430
431 struct ata_siiprb_command {
432 u_int16_t control;
433 u_int16_t protocol_override;
434 u_int32_t transfer_count;
435 u_int8_t fis[24];
436 union {
437 struct ata_siiprb_ata_command ata;
438 struct ata_siiprb_atapi_command atapi;
439 } u;
440 } __packed;
441
442 static int
ata_siiprb_allocate(device_t dev)443 ata_siiprb_allocate(device_t dev)
444 {
445 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
446 struct ata_channel *ch = device_get_softc(dev);
447 int offset = ch->unit * 0x2000;
448
449 /* set the SATA resources */
450 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
451 ch->r_io[ATA_SSTATUS].offset = 0x1f04 + offset;
452 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
453 ch->r_io[ATA_SERROR].offset = 0x1f08 + offset;
454 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
455 ch->r_io[ATA_SCONTROL].offset = 0x1f00 + offset;
456 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2;
457 ch->r_io[ATA_SACTIVE].offset = 0x1f0c + offset;
458
459 ch->hw.status = ata_siiprb_status;
460 ch->hw.begin_transaction = ata_siiprb_begin_transaction;
461 ch->hw.end_transaction = ata_siiprb_end_transaction;
462 ch->hw.command = NULL; /* not used here */
463 ch->hw.softreset = ata_siiprb_softreset;
464 return 0;
465 }
466
467 static int
ata_siiprb_status(device_t dev)468 ata_siiprb_status(device_t dev)
469 {
470 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
471 struct ata_channel *ch = device_get_softc(dev);
472 u_int32_t action = ATA_INL(ctlr->r_res1, 0x0044);
473 int offset = ch->unit * 0x2000;
474
475 if (action & (1 << ch->unit)) {
476 u_int32_t istatus = ATA_INL(ctlr->r_res2, 0x1008 + offset);
477
478 /* do we have any PHY events ? */
479 ata_sata_phy_check_events(dev);
480
481 /* clear interrupt(s) */
482 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, istatus);
483
484 /* do we have any device action ? */
485 return (istatus & 0x00000003);
486 }
487 return 0;
488 }
489
490 static int
ata_siiprb_begin_transaction(struct ata_request * request)491 ata_siiprb_begin_transaction(struct ata_request *request)
492 {
493 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
494 struct ata_channel *ch = device_get_softc(request->parent);
495 struct ata_siiprb_command *prb;
496 struct ata_siiprb_dma_prdentry *prd;
497 int offset = ch->unit * 0x2000;
498 u_int64_t prb_bus;
499 int dummy;
500
501 /* SOS XXX */
502 if (request->u.ata.command == ATA_DEVICE_RESET) {
503 request->result = 0;
504 return ATA_OP_FINISHED;
505 }
506
507 /* check for 48 bit access and convert if needed */
508 ata_modify_if_48bit(request);
509
510 /* get a piece of the workspace for this request */
511 prb = (struct ata_siiprb_command *)ch->dma->work;
512
513 /* set basic prd options ata/atapi etc etc */
514 bzero(prb, sizeof(struct ata_siiprb_command));
515
516 /* setup the FIS for this request */
517 if (!ata_request2fis_h2d(request, &prb->fis[0])) {
518 device_printf(request->dev, "setting up SATA FIS failed\n");
519 request->result = EIO;
520 return ATA_OP_FINISHED;
521 }
522
523 /* setup transfer type */
524 if (request->flags & ATA_R_ATAPI) {
525 struct ata_device *atadev = device_get_softc(request->dev);
526
527 bcopy(request->u.atapi.ccb, prb->u.atapi.ccb, 16);
528 if ((atadev->param.config & ATA_PROTO_MASK) == ATA_PROTO_ATAPI_12)
529 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000020);
530 else
531 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000020);
532 if (request->flags & ATA_R_READ)
533 prb->control = htole16(0x0010);
534 if (request->flags & ATA_R_WRITE)
535 prb->control = htole16(0x0020);
536 prd = &prb->u.atapi.prd[0];
537 }
538 else
539 prd = &prb->u.ata.prd[0];
540
541 /* if request moves data setup and load SG list */
542 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
543 if (ch->dma->load(ch->dev, request->data, request->bytecount,
544 request->flags & ATA_R_READ, prd, &dummy)) {
545 device_printf(request->dev, "setting up DMA failed\n");
546 request->result = EIO;
547 return ATA_OP_FINISHED;
548 }
549 }
550
551 /* activate the prb */
552 prb_bus = ch->dma->work_bus;
553 ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus);
554 ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus>>32);
555
556 /* start the timeout */
557 callout_reset(&request->callout, request->timeout * hz,
558 (timeout_t*)ata_timeout, request);
559 return ATA_OP_CONTINUES;
560 }
561
562 static int
ata_siiprb_end_transaction(struct ata_request * request)563 ata_siiprb_end_transaction(struct ata_request *request)
564 {
565 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
566 struct ata_channel *ch = device_get_softc(request->parent);
567 struct ata_siiprb_command *prb;
568 int offset = ch->unit * 0x2000;
569 int error, timeout;
570
571 /* kill the timeout */
572 callout_cancel(&request->callout);
573
574 prb = (struct ata_siiprb_command *)
575 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
576
577 /* any controller errors flagged ? */
578 if ((error = ATA_INL(ctlr->r_res2, 0x1024 + offset))) {
579 if (bootverbose)
580 kprintf("ata_siiprb_end_transaction %s error=%08x\n",
581 ata_cmd2str(request), error);
582
583 /* if device error status get details */
584 if (error == 1 || error == 2) {
585 request->status = prb->fis[2];
586 if (request->status & ATA_S_ERROR)
587 request->error = prb->fis[3];
588 }
589
590 /* SOS XXX handle other controller errors here */
591
592 /* initialize port */
593 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000004);
594
595 /* poll for port ready */
596 for (timeout = 0; timeout < 1000; timeout++) {
597 DELAY(1000);
598 if (ATA_INL(ctlr->r_res2, 0x1008 + offset) & 0x00040000)
599 break;
600 }
601 if (bootverbose) {
602 if (timeout >= 1000)
603 device_printf(ch->dev, "port initialize timeout\n");
604 else
605 device_printf(ch->dev, "port initialize time=%dms\n", timeout);
606 }
607 }
608
609 /* update progress */
610 if (!(request->status & ATA_S_ERROR) && !(request->flags & ATA_R_TIMEOUT)) {
611 if (request->flags & ATA_R_READ)
612 request->donecount = prb->transfer_count;
613 else
614 request->donecount = request->bytecount;
615 }
616
617 /* release SG list etc */
618 ch->dma->unload(ch->dev);
619
620 return ATA_OP_FINISHED;
621 }
622
623 static int
ata_siiprb_issue_cmd(device_t dev)624 ata_siiprb_issue_cmd(device_t dev)
625 {
626 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
627 struct ata_channel *ch = device_get_softc(dev);
628 u_int64_t prb_bus = ch->dma->work_bus;
629 u_int32_t status;
630 int offset = ch->unit * 0x2000;
631 int timeout;
632
633 /* issue command to chip */
634 ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus);
635 ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus >> 32);
636
637 /* poll for command finished */
638 for (timeout = 0; timeout < 10000; timeout++) {
639 DELAY(1000);
640 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00010000)
641 break;
642 }
643 if (timeout >= 1000)
644 return EIO;
645
646 if (bootverbose)
647 device_printf(ch->dev, "ata_siiprb_issue_cmd time=%dms status=%08x\n",
648 timeout, status);
649 return 0;
650 }
651
652 static u_int32_t
ata_siiprb_softreset(device_t dev,int port)653 ata_siiprb_softreset(device_t dev, int port)
654 {
655 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
656 struct ata_channel *ch = device_get_softc(dev);
657 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma->work;
658 u_int32_t signature;
659 int offset = ch->unit * 0x2000;
660
661 /* setup the workspace for a soft reset command */
662 bzero(prb, sizeof(struct ata_siiprb_command));
663 prb->control = htole16(0x0080);
664 prb->fis[1] = port & 0x0f;
665
666 /* issue soft reset */
667 if (ata_siiprb_issue_cmd(dev))
668 return -1;
669
670 ata_udelay(150000);
671
672 /* get possible signature */
673 prb = (struct ata_siiprb_command *)
674 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
675 signature=prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24);
676
677 /* clear error bits/interrupt */
678 ATA_IDX_OUTL(ch, ATA_SERROR, 0xffffffff);
679
680 return signature;
681 }
682
683 static void
ata_siiprb_reset(device_t dev)684 ata_siiprb_reset(device_t dev)
685 {
686 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
687 struct ata_channel *ch = device_get_softc(dev);
688 int offset = ch->unit * 0x2000;
689 u_int32_t status, signature;
690 int timeout;
691
692 /* disable interrupts */
693 ATA_OUTL(ctlr->r_res2, 0x1014 + offset, 0x000000ff);
694
695 /* reset channel HW */
696 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000001);
697 DELAY(1000);
698 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000001);
699 DELAY(10000);
700
701 /* poll for channel ready */
702 for (timeout = 0; timeout < 1000; timeout++) {
703 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00040000)
704 break;
705 DELAY(1000);
706 }
707
708 if (bootverbose) {
709 if (timeout >= 1000)
710 device_printf(ch->dev, "channel HW reset timeout\n");
711 else
712 device_printf(ch->dev, "channel HW reset time=%dms\n", timeout);
713 }
714
715 /* reset phy */
716 if (!ata_sata_phy_reset(dev)) {
717 if (bootverbose)
718 device_printf(ch->dev, "phy reset found no device\n");
719 ch->devices = 0;
720 goto finish;
721 }
722
723 /* issue soft reset */
724 signature = ata_siiprb_softreset(dev, ATA_PM);
725 if (bootverbose)
726 device_printf(ch->dev, "SIGNATURE: %08x\n", signature);
727
728 /* figure out whats there */
729 switch (signature >> 16) {
730 case 0x0000:
731 ch->devices = ATA_ATA_MASTER;
732 break;
733 case 0x9669:
734 ch->devices = ATA_PORTMULTIPLIER;
735 device_printf(ch->dev, "Portmultipliers not supported yet\n");
736 ch->devices = 0;
737 break;
738 case 0xeb14:
739 ch->devices = ATA_ATAPI_MASTER;
740 break;
741 default:
742 ch->devices = 0;
743 }
744 if (bootverbose)
745 device_printf(dev, "siiprb_reset devices=%08x\n", ch->devices);
746
747 finish:
748 /* clear interrupt(s) */
749 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x000008ff);
750
751 /* require explicit interrupt ack */
752 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000008);
753
754 /* 64bit mode */
755 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000400);
756
757 /* enable interrupts wanted */
758 ATA_OUTL(ctlr->r_res2, 0x1010 + offset, 0x000000ff);
759 }
760
761 static void
ata_siiprb_dmasetprd(void * xsc,bus_dma_segment_t * segs,int nsegs,int error)762 ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
763 {
764 struct ata_dmasetprd_args *args = xsc;
765 struct ata_siiprb_dma_prdentry *prd = args->dmatab;
766 int i;
767
768 if ((args->error = error))
769 return;
770
771 for (i = 0; i < nsegs; i++) {
772 prd[i].addr = htole64(segs[i].ds_addr);
773 prd[i].count = htole32(segs[i].ds_len);
774 }
775 prd[i - 1].control = htole32(ATA_DMA_EOT);
776 KASSERT(nsegs <= ATA_SIIPRB_DMA_ENTRIES,("too many DMA segment entries\n"));
777 args->nsegs = nsegs;
778 }
779
780 static void
ata_siiprb_dmainit(device_t dev)781 ata_siiprb_dmainit(device_t dev)
782 {
783 struct ata_channel *ch = device_get_softc(dev);
784
785 ata_dmainit(dev);
786 if (ch->dma) {
787 /* note start and stop are not used here */
788 ch->dma->setprd = ata_siiprb_dmasetprd;
789 ch->dma->max_address = BUS_SPACE_MAXADDR;
790 }
791 }
792